2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include "radeon_drm.h"
31 #include "atom-bits.h"
33 /* from radeon_encoder.c */
35 radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device,
37 extern void radeon_link_encoder_connector(struct drm_device *dev);
39 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id,
40 uint32_t supported_device);
42 /* from radeon_connector.c */
44 radeon_add_atom_connector(struct drm_device *dev,
45 uint32_t connector_id,
46 uint32_t supported_device,
48 struct radeon_i2c_bus_rec *i2c_bus,
49 bool linkb, uint32_t igp_lane_info,
50 uint16_t connector_object_id,
51 struct radeon_hpd *hpd);
53 /* from radeon_legacy_encoder.c */
55 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id,
56 uint32_t supported_device);
58 union atom_supported_devices {
59 struct _ATOM_SUPPORTED_DEVICES_INFO info;
60 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
61 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
64 static inline struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
67 struct atom_context *ctx = rdev->mode_info.atom_context;
68 ATOM_GPIO_I2C_ASSIGMENT *gpio;
69 struct radeon_i2c_bus_rec i2c;
70 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
71 struct _ATOM_GPIO_I2C_INFO *i2c_info;
72 uint16_t data_offset, size;
75 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
78 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
79 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
81 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
82 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
84 for (i = 0; i < num_indices; i++) {
85 gpio = &i2c_info->asGPIO_Info[i];
87 if (gpio->sucI2cId.ucAccess == id) {
88 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
89 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
90 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
91 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
92 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
93 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
94 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
95 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
96 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
97 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
98 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
99 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
100 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
101 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
102 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
103 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
105 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
106 i2c.hw_capable = true;
108 i2c.hw_capable = false;
110 if (gpio->sucI2cId.ucAccess == 0xa0)
115 i2c.i2c_id = gpio->sucI2cId.ucAccess;
126 static inline struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev,
129 struct atom_context *ctx = rdev->mode_info.atom_context;
130 struct radeon_gpio_rec gpio;
131 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
132 struct _ATOM_GPIO_PIN_LUT *gpio_info;
133 ATOM_GPIO_PIN_ASSIGNMENT *pin;
134 u16 data_offset, size;
137 memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
140 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
141 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
143 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
144 sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
146 for (i = 0; i < num_indices; i++) {
147 pin = &gpio_info->asGPIO_Pin[i];
148 if (id == pin->ucGPIO_ID) {
149 gpio.id = pin->ucGPIO_ID;
150 gpio.reg = pin->usGpioPin_AIndex * 4;
151 gpio.mask = (1 << pin->ucGpioPinBitShift);
161 static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
162 struct radeon_gpio_rec *gpio)
164 struct radeon_hpd hpd;
167 if (ASIC_IS_DCE4(rdev))
168 reg = EVERGREEN_DC_GPIO_HPD_A;
170 reg = AVIVO_DC_GPIO_HPD_A;
173 if (gpio->reg == reg) {
176 hpd.hpd = RADEON_HPD_1;
179 hpd.hpd = RADEON_HPD_2;
182 hpd.hpd = RADEON_HPD_3;
185 hpd.hpd = RADEON_HPD_4;
188 hpd.hpd = RADEON_HPD_5;
191 hpd.hpd = RADEON_HPD_6;
194 hpd.hpd = RADEON_HPD_NONE;
198 hpd.hpd = RADEON_HPD_NONE;
202 static bool radeon_atom_apply_quirks(struct drm_device *dev,
203 uint32_t supported_device,
205 struct radeon_i2c_bus_rec *i2c_bus,
207 struct radeon_hpd *hpd)
210 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
211 if ((dev->pdev->device == 0x791e) &&
212 (dev->pdev->subsystem_vendor == 0x1043) &&
213 (dev->pdev->subsystem_device == 0x826d)) {
214 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
215 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
216 *connector_type = DRM_MODE_CONNECTOR_DVID;
219 /* Asrock RS600 board lists the DVI port as HDMI */
220 if ((dev->pdev->device == 0x7941) &&
221 (dev->pdev->subsystem_vendor == 0x1849) &&
222 (dev->pdev->subsystem_device == 0x7941)) {
223 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
224 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
225 *connector_type = DRM_MODE_CONNECTOR_DVID;
228 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
229 if ((dev->pdev->device == 0x7941) &&
230 (dev->pdev->subsystem_vendor == 0x147b) &&
231 (dev->pdev->subsystem_device == 0x2412)) {
232 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
236 /* Falcon NW laptop lists vga ddc line for LVDS */
237 if ((dev->pdev->device == 0x5653) &&
238 (dev->pdev->subsystem_vendor == 0x1462) &&
239 (dev->pdev->subsystem_device == 0x0291)) {
240 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
241 i2c_bus->valid = false;
246 /* HIS X1300 is DVI+VGA, not DVI+DVI */
247 if ((dev->pdev->device == 0x7146) &&
248 (dev->pdev->subsystem_vendor == 0x17af) &&
249 (dev->pdev->subsystem_device == 0x2058)) {
250 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
254 /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
255 if ((dev->pdev->device == 0x7142) &&
256 (dev->pdev->subsystem_vendor == 0x1458) &&
257 (dev->pdev->subsystem_device == 0x2134)) {
258 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
264 if ((dev->pdev->device == 0x71C5) &&
265 (dev->pdev->subsystem_vendor == 0x106b) &&
266 (dev->pdev->subsystem_device == 0x0080)) {
267 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
268 (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
270 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT)
274 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
275 if ((dev->pdev->device == 0x9598) &&
276 (dev->pdev->subsystem_vendor == 0x1043) &&
277 (dev->pdev->subsystem_device == 0x01da)) {
278 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
279 *connector_type = DRM_MODE_CONNECTOR_DVII;
283 /* ASUS HD 3450 board lists the DVI port as HDMI */
284 if ((dev->pdev->device == 0x95C5) &&
285 (dev->pdev->subsystem_vendor == 0x1043) &&
286 (dev->pdev->subsystem_device == 0x01e2)) {
287 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
288 *connector_type = DRM_MODE_CONNECTOR_DVII;
292 /* some BIOSes seem to report DAC on HDMI - usually this is a board with
293 * HDMI + VGA reporting as HDMI
295 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
296 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
297 *connector_type = DRM_MODE_CONNECTOR_VGA;
302 /* Acer laptop reports DVI-D as DVI-I */
303 if ((dev->pdev->device == 0x95c4) &&
304 (dev->pdev->subsystem_vendor == 0x1025) &&
305 (dev->pdev->subsystem_device == 0x013c)) {
306 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
307 (supported_device == ATOM_DEVICE_DFP1_SUPPORT))
308 *connector_type = DRM_MODE_CONNECTOR_DVID;
311 /* XFX Pine Group device rv730 reports no VGA DDC lines
312 * even though they are wired up to record 0x93
314 if ((dev->pdev->device == 0x9498) &&
315 (dev->pdev->subsystem_vendor == 0x1682) &&
316 (dev->pdev->subsystem_device == 0x2452)) {
317 struct radeon_device *rdev = dev->dev_private;
318 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
323 const int supported_devices_connector_convert[] = {
324 DRM_MODE_CONNECTOR_Unknown,
325 DRM_MODE_CONNECTOR_VGA,
326 DRM_MODE_CONNECTOR_DVII,
327 DRM_MODE_CONNECTOR_DVID,
328 DRM_MODE_CONNECTOR_DVIA,
329 DRM_MODE_CONNECTOR_SVIDEO,
330 DRM_MODE_CONNECTOR_Composite,
331 DRM_MODE_CONNECTOR_LVDS,
332 DRM_MODE_CONNECTOR_Unknown,
333 DRM_MODE_CONNECTOR_Unknown,
334 DRM_MODE_CONNECTOR_HDMIA,
335 DRM_MODE_CONNECTOR_HDMIB,
336 DRM_MODE_CONNECTOR_Unknown,
337 DRM_MODE_CONNECTOR_Unknown,
338 DRM_MODE_CONNECTOR_9PinDIN,
339 DRM_MODE_CONNECTOR_DisplayPort
342 const uint16_t supported_devices_connector_object_id_convert[] = {
343 CONNECTOR_OBJECT_ID_NONE,
344 CONNECTOR_OBJECT_ID_VGA,
345 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
346 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
347 CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
348 CONNECTOR_OBJECT_ID_COMPOSITE,
349 CONNECTOR_OBJECT_ID_SVIDEO,
350 CONNECTOR_OBJECT_ID_LVDS,
351 CONNECTOR_OBJECT_ID_9PIN_DIN,
352 CONNECTOR_OBJECT_ID_9PIN_DIN,
353 CONNECTOR_OBJECT_ID_DISPLAYPORT,
354 CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
355 CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
356 CONNECTOR_OBJECT_ID_SVIDEO
359 const int object_connector_convert[] = {
360 DRM_MODE_CONNECTOR_Unknown,
361 DRM_MODE_CONNECTOR_DVII,
362 DRM_MODE_CONNECTOR_DVII,
363 DRM_MODE_CONNECTOR_DVID,
364 DRM_MODE_CONNECTOR_DVID,
365 DRM_MODE_CONNECTOR_VGA,
366 DRM_MODE_CONNECTOR_Composite,
367 DRM_MODE_CONNECTOR_SVIDEO,
368 DRM_MODE_CONNECTOR_Unknown,
369 DRM_MODE_CONNECTOR_Unknown,
370 DRM_MODE_CONNECTOR_9PinDIN,
371 DRM_MODE_CONNECTOR_Unknown,
372 DRM_MODE_CONNECTOR_HDMIA,
373 DRM_MODE_CONNECTOR_HDMIB,
374 DRM_MODE_CONNECTOR_LVDS,
375 DRM_MODE_CONNECTOR_9PinDIN,
376 DRM_MODE_CONNECTOR_Unknown,
377 DRM_MODE_CONNECTOR_Unknown,
378 DRM_MODE_CONNECTOR_Unknown,
379 DRM_MODE_CONNECTOR_DisplayPort,
380 DRM_MODE_CONNECTOR_eDP,
381 DRM_MODE_CONNECTOR_Unknown
384 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
386 struct radeon_device *rdev = dev->dev_private;
387 struct radeon_mode_info *mode_info = &rdev->mode_info;
388 struct atom_context *ctx = mode_info->atom_context;
389 int index = GetIndexIntoMasterTable(DATA, Object_Header);
390 u16 size, data_offset;
392 ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
393 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
394 ATOM_OBJECT_HEADER *obj_header;
395 int i, j, path_size, device_support;
397 u16 igp_lane_info, conn_id, connector_object_id;
399 struct radeon_i2c_bus_rec ddc_bus;
400 struct radeon_gpio_rec gpio;
401 struct radeon_hpd hpd;
403 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
409 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
410 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
411 (ctx->bios + data_offset +
412 le16_to_cpu(obj_header->usDisplayPathTableOffset));
413 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
414 (ctx->bios + data_offset +
415 le16_to_cpu(obj_header->usConnectorObjectTableOffset));
416 device_support = le16_to_cpu(obj_header->usDeviceSupport);
419 for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
420 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
421 ATOM_DISPLAY_OBJECT_PATH *path;
423 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
424 path_size += le16_to_cpu(path->usSize);
426 if (device_support & le16_to_cpu(path->usDeviceTag)) {
427 uint8_t con_obj_id, con_obj_num, con_obj_type;
430 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
433 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
436 (le16_to_cpu(path->usConnObjectId) &
437 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
439 /* TODO CV support */
440 if (le16_to_cpu(path->usDeviceTag) ==
441 ATOM_DEVICE_CV_SUPPORT)
445 if ((rdev->flags & RADEON_IS_IGP) &&
447 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
448 uint16_t igp_offset = 0;
449 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
452 GetIndexIntoMasterTable(DATA,
453 IntegratedSystemInfo);
455 if (atom_parse_data_header(ctx, index, &size, &frev,
456 &crev, &igp_offset)) {
460 (ATOM_INTEGRATED_SYSTEM_INFO_V2
461 *) (ctx->bios + igp_offset);
464 uint32_t slot_config, ct;
466 if (con_obj_num == 1)
475 ct = (slot_config >> 16) & 0xff;
477 object_connector_convert
479 connector_object_id = ct;
481 slot_config & 0xffff;
489 object_connector_convert[con_obj_id];
490 connector_object_id = con_obj_id;
495 object_connector_convert[con_obj_id];
496 connector_object_id = con_obj_id;
499 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
502 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2);
504 uint8_t enc_obj_id, enc_obj_num, enc_obj_type;
507 (le16_to_cpu(path->usGraphicObjIds[j]) &
508 OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
510 (le16_to_cpu(path->usGraphicObjIds[j]) &
511 ENUM_ID_MASK) >> ENUM_ID_SHIFT;
513 (le16_to_cpu(path->usGraphicObjIds[j]) &
514 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
516 /* FIXME: add support for router objects */
517 if (enc_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
518 if (enc_obj_num == 2)
523 radeon_add_atom_encoder(dev,
532 /* look up gpio for ddc, hpd */
533 if ((le16_to_cpu(path->usDeviceTag) &
534 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
535 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
536 if (le16_to_cpu(path->usConnObjectId) ==
537 le16_to_cpu(con_obj->asObjects[j].
539 ATOM_COMMON_RECORD_HEADER
541 (ATOM_COMMON_RECORD_HEADER
543 (ctx->bios + data_offset +
544 le16_to_cpu(con_obj->
547 ATOM_I2C_RECORD *i2c_record;
548 ATOM_HPD_INT_RECORD *hpd_record;
549 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
550 hpd.hpd = RADEON_HPD_NONE;
552 while (record->ucRecordType > 0
555 ATOM_MAX_OBJECT_RECORD_NUMBER) {
556 switch (record->ucRecordType) {
557 case ATOM_I2C_RECORD_TYPE:
562 (ATOM_I2C_ID_CONFIG_ACCESS *)
563 &i2c_record->sucI2cId;
564 ddc_bus = radeon_lookup_i2c_gpio(rdev,
568 case ATOM_HPD_INT_RECORD_TYPE:
570 (ATOM_HPD_INT_RECORD *)
572 gpio = radeon_lookup_gpio(rdev,
573 hpd_record->ucHPDIntGPIOID);
574 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
575 hpd.plugged_state = hpd_record->ucPlugged_PinState;
579 (ATOM_COMMON_RECORD_HEADER
589 hpd.hpd = RADEON_HPD_NONE;
590 ddc_bus.valid = false;
593 /* needed for aux chan transactions */
594 ddc_bus.hpd_id = hpd.hpd ? (hpd.hpd - 1) : 0;
596 conn_id = le16_to_cpu(path->usConnObjectId);
598 if (!radeon_atom_apply_quirks
599 (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
600 &ddc_bus, &conn_id, &hpd))
603 radeon_add_atom_connector(dev,
607 connector_type, &ddc_bus,
608 linkb, igp_lane_info,
615 radeon_link_encoder_connector(dev);
620 static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
624 struct radeon_device *rdev = dev->dev_private;
626 if (rdev->flags & RADEON_IS_IGP) {
627 return supported_devices_connector_object_id_convert
629 } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
630 (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
631 (devices & ATOM_DEVICE_DFP2_SUPPORT)) {
632 struct radeon_mode_info *mode_info = &rdev->mode_info;
633 struct atom_context *ctx = mode_info->atom_context;
634 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
635 uint16_t size, data_offset;
637 ATOM_XTMDS_INFO *xtmds;
639 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
640 xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
642 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
643 if (connector_type == DRM_MODE_CONNECTOR_DVII)
644 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
646 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
648 if (connector_type == DRM_MODE_CONNECTOR_DVII)
649 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
651 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
654 return supported_devices_connector_object_id_convert
657 return supported_devices_connector_object_id_convert
662 struct bios_connector {
667 struct radeon_i2c_bus_rec ddc_bus;
668 struct radeon_hpd hpd;
671 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
675 struct radeon_device *rdev = dev->dev_private;
676 struct radeon_mode_info *mode_info = &rdev->mode_info;
677 struct atom_context *ctx = mode_info->atom_context;
678 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
679 uint16_t size, data_offset;
681 uint16_t device_support;
683 union atom_supported_devices *supported_devices;
684 int i, j, max_device;
685 struct bios_connector bios_connectors[ATOM_MAX_SUPPORTED_DEVICE];
687 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
691 (union atom_supported_devices *)(ctx->bios + data_offset);
693 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
696 max_device = ATOM_MAX_SUPPORTED_DEVICE;
698 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
700 for (i = 0; i < max_device; i++) {
701 ATOM_CONNECTOR_INFO_I2C ci =
702 supported_devices->info.asConnInfo[i];
704 bios_connectors[i].valid = false;
706 if (!(device_support & (1 << i))) {
710 if (i == ATOM_DEVICE_CV_INDEX) {
711 DRM_DEBUG("Skipping Component Video\n");
715 bios_connectors[i].connector_type =
716 supported_devices_connector_convert[ci.sucConnectorInfo.
720 if (bios_connectors[i].connector_type ==
721 DRM_MODE_CONNECTOR_Unknown)
724 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
726 bios_connectors[i].line_mux =
727 ci.sucI2cId.ucAccess;
729 /* give tv unique connector ids */
730 if (i == ATOM_DEVICE_TV1_INDEX) {
731 bios_connectors[i].ddc_bus.valid = false;
732 bios_connectors[i].line_mux = 50;
733 } else if (i == ATOM_DEVICE_TV2_INDEX) {
734 bios_connectors[i].ddc_bus.valid = false;
735 bios_connectors[i].line_mux = 51;
736 } else if (i == ATOM_DEVICE_CV_INDEX) {
737 bios_connectors[i].ddc_bus.valid = false;
738 bios_connectors[i].line_mux = 52;
740 bios_connectors[i].ddc_bus =
741 radeon_lookup_i2c_gpio(rdev,
742 bios_connectors[i].line_mux);
744 if ((crev > 1) && (frev > 1)) {
745 u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
748 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
751 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
754 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
758 if (i == ATOM_DEVICE_DFP1_INDEX)
759 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
760 else if (i == ATOM_DEVICE_DFP2_INDEX)
761 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
763 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
766 /* Always set the connector type to VGA for CRT1/CRT2. if they are
767 * shared with a DVI port, we'll pick up the DVI connector when we
768 * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
770 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
771 bios_connectors[i].connector_type =
772 DRM_MODE_CONNECTOR_VGA;
774 if (!radeon_atom_apply_quirks
775 (dev, (1 << i), &bios_connectors[i].connector_type,
776 &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
777 &bios_connectors[i].hpd))
780 bios_connectors[i].valid = true;
781 bios_connectors[i].devices = (1 << i);
783 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
784 radeon_add_atom_encoder(dev,
785 radeon_get_encoder_id(dev,
790 radeon_add_legacy_encoder(dev,
791 radeon_get_encoder_id(dev,
797 /* combine shared connectors */
798 for (i = 0; i < max_device; i++) {
799 if (bios_connectors[i].valid) {
800 for (j = 0; j < max_device; j++) {
801 if (bios_connectors[j].valid && (i != j)) {
802 if (bios_connectors[i].line_mux ==
803 bios_connectors[j].line_mux) {
804 /* make sure not to combine LVDS */
805 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
806 bios_connectors[i].line_mux = 53;
807 bios_connectors[i].ddc_bus.valid = false;
810 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
811 bios_connectors[j].line_mux = 53;
812 bios_connectors[j].ddc_bus.valid = false;
815 /* combine analog and digital for DVI-I */
816 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
817 (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
818 ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
819 (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
820 bios_connectors[i].devices |=
821 bios_connectors[j].devices;
822 bios_connectors[i].connector_type =
823 DRM_MODE_CONNECTOR_DVII;
824 if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
825 bios_connectors[i].hpd =
826 bios_connectors[j].hpd;
827 bios_connectors[j].valid = false;
835 /* add the connectors */
836 for (i = 0; i < max_device; i++) {
837 if (bios_connectors[i].valid) {
838 uint16_t connector_object_id =
839 atombios_get_connector_object_id(dev,
840 bios_connectors[i].connector_type,
841 bios_connectors[i].devices);
842 radeon_add_atom_connector(dev,
843 bios_connectors[i].line_mux,
844 bios_connectors[i].devices,
847 &bios_connectors[i].ddc_bus,
850 &bios_connectors[i].hpd);
854 radeon_link_encoder_connector(dev);
859 union firmware_info {
860 ATOM_FIRMWARE_INFO info;
861 ATOM_FIRMWARE_INFO_V1_2 info_12;
862 ATOM_FIRMWARE_INFO_V1_3 info_13;
863 ATOM_FIRMWARE_INFO_V1_4 info_14;
864 ATOM_FIRMWARE_INFO_V2_1 info_21;
867 bool radeon_atom_get_clock_info(struct drm_device *dev)
869 struct radeon_device *rdev = dev->dev_private;
870 struct radeon_mode_info *mode_info = &rdev->mode_info;
871 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
872 union firmware_info *firmware_info;
874 struct radeon_pll *p1pll = &rdev->clock.p1pll;
875 struct radeon_pll *p2pll = &rdev->clock.p2pll;
876 struct radeon_pll *dcpll = &rdev->clock.dcpll;
877 struct radeon_pll *spll = &rdev->clock.spll;
878 struct radeon_pll *mpll = &rdev->clock.mpll;
879 uint16_t data_offset;
881 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
882 &frev, &crev, &data_offset)) {
884 (union firmware_info *)(mode_info->atom_context->bios +
887 p1pll->reference_freq =
888 le16_to_cpu(firmware_info->info.usReferenceClock);
889 p1pll->reference_div = 0;
893 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
896 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
898 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
901 p1pll->lcd_pll_out_min =
902 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
903 if (p1pll->lcd_pll_out_min == 0)
904 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
905 p1pll->lcd_pll_out_max =
906 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
907 if (p1pll->lcd_pll_out_max == 0)
908 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
910 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
911 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
914 if (p1pll->pll_out_min == 0) {
915 if (ASIC_IS_AVIVO(rdev))
916 p1pll->pll_out_min = 64800;
918 p1pll->pll_out_min = 20000;
919 } else if (p1pll->pll_out_min > 64800) {
920 /* Limiting the pll output range is a good thing generally as
921 * it limits the number of possible pll combinations for a given
922 * frequency presumably to the ones that work best on each card.
923 * However, certain duallink DVI monitors seem to like
924 * pll combinations that would be limited by this at least on
925 * pre-DCE 3.0 r6xx hardware. This might need to be adjusted per
929 p1pll->pll_out_min = 64800;
933 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
935 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
940 spll->reference_freq =
941 le16_to_cpu(firmware_info->info.usReferenceClock);
942 spll->reference_div = 0;
945 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
947 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
950 if (spll->pll_out_min == 0) {
951 if (ASIC_IS_AVIVO(rdev))
952 spll->pll_out_min = 64800;
954 spll->pll_out_min = 20000;
958 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
960 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
963 mpll->reference_freq =
964 le16_to_cpu(firmware_info->info.usReferenceClock);
965 mpll->reference_div = 0;
968 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
970 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
973 if (mpll->pll_out_min == 0) {
974 if (ASIC_IS_AVIVO(rdev))
975 mpll->pll_out_min = 64800;
977 mpll->pll_out_min = 20000;
981 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
983 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
985 rdev->clock.default_sclk =
986 le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
987 rdev->clock.default_mclk =
988 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
990 if (ASIC_IS_DCE4(rdev)) {
991 rdev->clock.default_dispclk =
992 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
993 if (rdev->clock.default_dispclk == 0)
994 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
995 rdev->clock.dp_extclk =
996 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
1007 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1008 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1011 bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1013 struct radeon_mode_info *mode_info = &rdev->mode_info;
1014 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1015 union igp_info *igp_info;
1019 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1020 &frev, &crev, &data_offset)) {
1021 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1025 if (igp_info->info.ucMemoryType & 0xf0)
1029 if (igp_info->info_2.ucMemoryType & 0x0f)
1033 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1040 bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1041 struct radeon_encoder_int_tmds *tmds)
1043 struct drm_device *dev = encoder->base.dev;
1044 struct radeon_device *rdev = dev->dev_private;
1045 struct radeon_mode_info *mode_info = &rdev->mode_info;
1046 int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1047 uint16_t data_offset;
1048 struct _ATOM_TMDS_INFO *tmds_info;
1053 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1054 &frev, &crev, &data_offset)) {
1056 (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
1059 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1060 for (i = 0; i < 4; i++) {
1061 tmds->tmds_pll[i].freq =
1062 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1063 tmds->tmds_pll[i].value =
1064 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1065 tmds->tmds_pll[i].value |=
1066 (tmds_info->asMiscInfo[i].
1067 ucPLL_VCO_Gain & 0x3f) << 6;
1068 tmds->tmds_pll[i].value |=
1069 (tmds_info->asMiscInfo[i].
1070 ucPLL_DutyCycle & 0xf) << 12;
1071 tmds->tmds_pll[i].value |=
1072 (tmds_info->asMiscInfo[i].
1073 ucPLL_VoltageSwing & 0xf) << 16;
1075 DRM_DEBUG("TMDS PLL From ATOMBIOS %u %x\n",
1076 tmds->tmds_pll[i].freq,
1077 tmds->tmds_pll[i].value);
1079 if (maxfreq == tmds->tmds_pll[i].freq) {
1080 tmds->tmds_pll[i].freq = 0xffffffff;
1089 static struct radeon_atom_ss *radeon_atombios_get_ss_info(struct
1094 struct drm_device *dev = encoder->base.dev;
1095 struct radeon_device *rdev = dev->dev_private;
1096 struct radeon_mode_info *mode_info = &rdev->mode_info;
1097 int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1098 uint16_t data_offset;
1099 struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1101 struct radeon_atom_ss *ss = NULL;
1104 if (id > ATOM_MAX_SS_ENTRY)
1107 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1108 &frev, &crev, &data_offset)) {
1110 (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
1113 kzalloc(sizeof(struct radeon_atom_ss), GFP_KERNEL);
1118 for (i = 0; i < ATOM_MAX_SS_ENTRY; i++) {
1119 if (ss_info->asSS_Info[i].ucSS_Id == id) {
1121 le16_to_cpu(ss_info->asSS_Info[i].usSpreadSpectrumPercentage);
1122 ss->type = ss_info->asSS_Info[i].ucSpreadSpectrumType;
1123 ss->step = ss_info->asSS_Info[i].ucSS_Step;
1124 ss->delay = ss_info->asSS_Info[i].ucSS_Delay;
1125 ss->range = ss_info->asSS_Info[i].ucSS_Range;
1126 ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div;
1135 struct _ATOM_LVDS_INFO info;
1136 struct _ATOM_LVDS_INFO_V12 info_12;
1139 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1143 struct drm_device *dev = encoder->base.dev;
1144 struct radeon_device *rdev = dev->dev_private;
1145 struct radeon_mode_info *mode_info = &rdev->mode_info;
1146 int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
1147 uint16_t data_offset, misc;
1148 union lvds_info *lvds_info;
1150 struct radeon_encoder_atom_dig *lvds = NULL;
1152 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1153 &frev, &crev, &data_offset)) {
1155 (union lvds_info *)(mode_info->atom_context->bios + data_offset);
1157 kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1162 lvds->native_mode.clock =
1163 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
1164 lvds->native_mode.hdisplay =
1165 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
1166 lvds->native_mode.vdisplay =
1167 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
1168 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1169 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1170 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1171 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1172 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1173 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1174 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1175 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1176 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1177 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
1178 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1179 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1180 lvds->panel_pwr_delay =
1181 le16_to_cpu(lvds_info->info.usOffDelayInMs);
1182 lvds->lvds_misc = lvds_info->info.ucLVDS_Misc;
1184 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1185 if (misc & ATOM_VSYNC_POLARITY)
1186 lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1187 if (misc & ATOM_HSYNC_POLARITY)
1188 lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1189 if (misc & ATOM_COMPOSITESYNC)
1190 lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1191 if (misc & ATOM_INTERLACE)
1192 lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1193 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1194 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1196 /* set crtc values */
1197 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1199 lvds->ss = radeon_atombios_get_ss_info(encoder, lvds_info->info.ucSS_Id);
1201 if (ASIC_IS_AVIVO(rdev)) {
1202 if (radeon_new_pll == 0)
1203 lvds->pll_algo = PLL_ALGO_LEGACY;
1205 lvds->pll_algo = PLL_ALGO_NEW;
1207 if (radeon_new_pll == 1)
1208 lvds->pll_algo = PLL_ALGO_NEW;
1210 lvds->pll_algo = PLL_ALGO_LEGACY;
1213 encoder->native_mode = lvds->native_mode;
1218 struct radeon_encoder_primary_dac *
1219 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1221 struct drm_device *dev = encoder->base.dev;
1222 struct radeon_device *rdev = dev->dev_private;
1223 struct radeon_mode_info *mode_info = &rdev->mode_info;
1224 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1225 uint16_t data_offset;
1226 struct _COMPASSIONATE_DATA *dac_info;
1229 struct radeon_encoder_primary_dac *p_dac = NULL;
1231 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1232 &frev, &crev, &data_offset)) {
1233 dac_info = (struct _COMPASSIONATE_DATA *)
1234 (mode_info->atom_context->bios + data_offset);
1236 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1241 bg = dac_info->ucDAC1_BG_Adjustment;
1242 dac = dac_info->ucDAC1_DAC_Adjustment;
1243 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1249 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1250 struct drm_display_mode *mode)
1252 struct radeon_mode_info *mode_info = &rdev->mode_info;
1253 ATOM_ANALOG_TV_INFO *tv_info;
1254 ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1255 ATOM_DTD_FORMAT *dtd_timings;
1256 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1258 u16 data_offset, misc;
1260 if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
1261 &frev, &crev, &data_offset))
1266 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1267 if (index > MAX_SUPPORTED_TV_TIMING)
1270 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1271 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1272 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1273 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1274 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1276 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1277 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1278 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1279 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1280 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1283 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1284 if (misc & ATOM_VSYNC_POLARITY)
1285 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1286 if (misc & ATOM_HSYNC_POLARITY)
1287 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1288 if (misc & ATOM_COMPOSITESYNC)
1289 mode->flags |= DRM_MODE_FLAG_CSYNC;
1290 if (misc & ATOM_INTERLACE)
1291 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1292 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1293 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1295 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1298 /* PAL timings appear to have wrong values for totals */
1299 mode->crtc_htotal -= 1;
1300 mode->crtc_vtotal -= 1;
1304 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
1305 if (index > MAX_SUPPORTED_TV_TIMING_V1_2)
1308 dtd_timings = &tv_info_v1_2->aModeTimings[index];
1309 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1310 le16_to_cpu(dtd_timings->usHBlanking_Time);
1311 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1312 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1313 le16_to_cpu(dtd_timings->usHSyncOffset);
1314 mode->crtc_hsync_end = mode->crtc_hsync_start +
1315 le16_to_cpu(dtd_timings->usHSyncWidth);
1317 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1318 le16_to_cpu(dtd_timings->usVBlanking_Time);
1319 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1320 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1321 le16_to_cpu(dtd_timings->usVSyncOffset);
1322 mode->crtc_vsync_end = mode->crtc_vsync_start +
1323 le16_to_cpu(dtd_timings->usVSyncWidth);
1326 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1327 if (misc & ATOM_VSYNC_POLARITY)
1328 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1329 if (misc & ATOM_HSYNC_POLARITY)
1330 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1331 if (misc & ATOM_COMPOSITESYNC)
1332 mode->flags |= DRM_MODE_FLAG_CSYNC;
1333 if (misc & ATOM_INTERLACE)
1334 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1335 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1336 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1338 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
1345 radeon_atombios_get_tv_info(struct radeon_device *rdev)
1347 struct radeon_mode_info *mode_info = &rdev->mode_info;
1348 int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1349 uint16_t data_offset;
1351 struct _ATOM_ANALOG_TV_INFO *tv_info;
1352 enum radeon_tv_std tv_std = TV_STD_NTSC;
1354 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1355 &frev, &crev, &data_offset)) {
1357 tv_info = (struct _ATOM_ANALOG_TV_INFO *)
1358 (mode_info->atom_context->bios + data_offset);
1360 switch (tv_info->ucTV_BootUpDefaultStandard) {
1362 tv_std = TV_STD_NTSC;
1363 DRM_INFO("Default TV standard: NTSC\n");
1366 tv_std = TV_STD_NTSC_J;
1367 DRM_INFO("Default TV standard: NTSC-J\n");
1370 tv_std = TV_STD_PAL;
1371 DRM_INFO("Default TV standard: PAL\n");
1374 tv_std = TV_STD_PAL_M;
1375 DRM_INFO("Default TV standard: PAL-M\n");
1378 tv_std = TV_STD_PAL_N;
1379 DRM_INFO("Default TV standard: PAL-N\n");
1382 tv_std = TV_STD_PAL_CN;
1383 DRM_INFO("Default TV standard: PAL-CN\n");
1386 tv_std = TV_STD_PAL_60;
1387 DRM_INFO("Default TV standard: PAL-60\n");
1390 tv_std = TV_STD_SECAM;
1391 DRM_INFO("Default TV standard: SECAM\n");
1394 tv_std = TV_STD_NTSC;
1395 DRM_INFO("Unknown TV standard; defaulting to NTSC\n");
1402 struct radeon_encoder_tv_dac *
1403 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1405 struct drm_device *dev = encoder->base.dev;
1406 struct radeon_device *rdev = dev->dev_private;
1407 struct radeon_mode_info *mode_info = &rdev->mode_info;
1408 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1409 uint16_t data_offset;
1410 struct _COMPASSIONATE_DATA *dac_info;
1413 struct radeon_encoder_tv_dac *tv_dac = NULL;
1415 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1416 &frev, &crev, &data_offset)) {
1418 dac_info = (struct _COMPASSIONATE_DATA *)
1419 (mode_info->atom_context->bios + data_offset);
1421 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1426 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1427 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1428 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1430 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1431 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1432 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1434 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1435 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1436 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1438 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
1443 static const char *thermal_controller_names[] = {
1454 static const char *pp_lib_thermal_controller_names[] = {
1467 "ADT7473 with internal",
1472 struct _ATOM_POWERPLAY_INFO info;
1473 struct _ATOM_POWERPLAY_INFO_V2 info_2;
1474 struct _ATOM_POWERPLAY_INFO_V3 info_3;
1475 struct _ATOM_PPLIB_POWERPLAYTABLE info_4;
1478 void radeon_atombios_get_power_modes(struct radeon_device *rdev)
1480 struct radeon_mode_info *mode_info = &rdev->mode_info;
1481 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
1484 u32 misc, misc2 = 0, sclk, mclk;
1485 union power_info *power_info;
1486 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
1487 struct _ATOM_PPLIB_STATE *power_state;
1488 int num_modes = 0, i, j;
1489 int state_index = 0, mode_index = 0;
1490 struct radeon_i2c_bus_rec i2c_bus;
1492 rdev->pm.default_power_state_index = -1;
1494 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1495 &frev, &crev, &data_offset)) {
1496 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
1498 /* add the i2c bus for thermal/fan chip */
1499 if (power_info->info.ucOverdriveThermalController > 0) {
1500 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
1501 thermal_controller_names[power_info->info.ucOverdriveThermalController],
1502 power_info->info.ucOverdriveControllerAddress >> 1);
1503 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
1504 rdev->pm.i2c_bus = radeon_i2c_create(rdev->ddev, &i2c_bus, "Thermal");
1506 num_modes = power_info->info.ucNumOfPowerModeEntries;
1507 if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
1508 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
1509 /* last mode is usually default, array is low to high */
1510 for (i = 0; i < num_modes; i++) {
1511 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
1514 rdev->pm.power_state[state_index].num_clock_modes = 1;
1515 rdev->pm.power_state[state_index].clock_info[0].mclk =
1516 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
1517 rdev->pm.power_state[state_index].clock_info[0].sclk =
1518 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
1519 /* skip invalid modes */
1520 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1521 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1523 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
1524 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
1525 misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
1526 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
1527 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1529 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1530 radeon_lookup_gpio(rdev,
1531 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
1532 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1533 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1536 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1538 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1539 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1541 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1542 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
1544 rdev->pm.power_state[state_index].flags = RADEON_PM_SINGLE_DISPLAY_ONLY;
1545 /* order matters! */
1546 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1547 rdev->pm.power_state[state_index].type =
1548 POWER_STATE_TYPE_POWERSAVE;
1549 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1550 rdev->pm.power_state[state_index].type =
1551 POWER_STATE_TYPE_BATTERY;
1552 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1553 rdev->pm.power_state[state_index].type =
1554 POWER_STATE_TYPE_BATTERY;
1555 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1556 rdev->pm.power_state[state_index].type =
1557 POWER_STATE_TYPE_BALANCED;
1558 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
1559 rdev->pm.power_state[state_index].type =
1560 POWER_STATE_TYPE_PERFORMANCE;
1561 rdev->pm.power_state[state_index].flags &=
1562 ~RADEON_PM_SINGLE_DISPLAY_ONLY;
1564 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1565 rdev->pm.power_state[state_index].type =
1566 POWER_STATE_TYPE_DEFAULT;
1567 rdev->pm.default_power_state_index = state_index;
1568 rdev->pm.power_state[state_index].default_clock_mode =
1569 &rdev->pm.power_state[state_index].clock_info[0];
1570 rdev->pm.power_state[state_index].flags &=
1571 ~RADEON_PM_SINGLE_DISPLAY_ONLY;
1576 rdev->pm.power_state[state_index].num_clock_modes = 1;
1577 rdev->pm.power_state[state_index].clock_info[0].mclk =
1578 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
1579 rdev->pm.power_state[state_index].clock_info[0].sclk =
1580 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
1581 /* skip invalid modes */
1582 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1583 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1585 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
1586 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
1587 misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
1588 misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
1589 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
1590 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1592 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1593 radeon_lookup_gpio(rdev,
1594 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
1595 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1596 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1599 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1601 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1602 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1604 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1605 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
1607 rdev->pm.power_state[state_index].flags = RADEON_PM_SINGLE_DISPLAY_ONLY;
1608 /* order matters! */
1609 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1610 rdev->pm.power_state[state_index].type =
1611 POWER_STATE_TYPE_POWERSAVE;
1612 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1613 rdev->pm.power_state[state_index].type =
1614 POWER_STATE_TYPE_BATTERY;
1615 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1616 rdev->pm.power_state[state_index].type =
1617 POWER_STATE_TYPE_BATTERY;
1618 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1619 rdev->pm.power_state[state_index].type =
1620 POWER_STATE_TYPE_BALANCED;
1621 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
1622 rdev->pm.power_state[state_index].type =
1623 POWER_STATE_TYPE_PERFORMANCE;
1624 rdev->pm.power_state[state_index].flags &=
1625 ~RADEON_PM_SINGLE_DISPLAY_ONLY;
1627 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1628 rdev->pm.power_state[state_index].type =
1629 POWER_STATE_TYPE_BALANCED;
1630 if (misc2 & ATOM_PM_MISCINFO2_MULTI_DISPLAY_SUPPORT)
1631 rdev->pm.power_state[state_index].flags &=
1632 ~RADEON_PM_SINGLE_DISPLAY_ONLY;
1633 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1634 rdev->pm.power_state[state_index].type =
1635 POWER_STATE_TYPE_DEFAULT;
1636 rdev->pm.default_power_state_index = state_index;
1637 rdev->pm.power_state[state_index].default_clock_mode =
1638 &rdev->pm.power_state[state_index].clock_info[0];
1639 rdev->pm.power_state[state_index].flags &=
1640 ~RADEON_PM_SINGLE_DISPLAY_ONLY;
1645 rdev->pm.power_state[state_index].num_clock_modes = 1;
1646 rdev->pm.power_state[state_index].clock_info[0].mclk =
1647 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
1648 rdev->pm.power_state[state_index].clock_info[0].sclk =
1649 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
1650 /* skip invalid modes */
1651 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1652 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1654 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
1655 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
1656 misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
1657 misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
1658 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
1659 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1661 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1662 radeon_lookup_gpio(rdev,
1663 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
1664 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1665 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1668 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1670 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1671 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1673 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1674 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
1675 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
1676 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
1678 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
1679 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
1682 rdev->pm.power_state[state_index].flags = RADEON_PM_SINGLE_DISPLAY_ONLY;
1683 /* order matters! */
1684 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1685 rdev->pm.power_state[state_index].type =
1686 POWER_STATE_TYPE_POWERSAVE;
1687 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1688 rdev->pm.power_state[state_index].type =
1689 POWER_STATE_TYPE_BATTERY;
1690 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1691 rdev->pm.power_state[state_index].type =
1692 POWER_STATE_TYPE_BATTERY;
1693 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1694 rdev->pm.power_state[state_index].type =
1695 POWER_STATE_TYPE_BALANCED;
1696 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
1697 rdev->pm.power_state[state_index].type =
1698 POWER_STATE_TYPE_PERFORMANCE;
1699 rdev->pm.power_state[state_index].flags &=
1700 ~RADEON_PM_SINGLE_DISPLAY_ONLY;
1702 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1703 rdev->pm.power_state[state_index].type =
1704 POWER_STATE_TYPE_BALANCED;
1705 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1706 rdev->pm.power_state[state_index].type =
1707 POWER_STATE_TYPE_DEFAULT;
1708 rdev->pm.default_power_state_index = state_index;
1709 rdev->pm.power_state[state_index].default_clock_mode =
1710 &rdev->pm.power_state[state_index].clock_info[0];
1716 /* last mode is usually default */
1717 if (rdev->pm.default_power_state_index == -1) {
1718 rdev->pm.power_state[state_index - 1].type =
1719 POWER_STATE_TYPE_DEFAULT;
1720 rdev->pm.default_power_state_index = state_index - 1;
1721 rdev->pm.power_state[state_index - 1].default_clock_mode =
1722 &rdev->pm.power_state[state_index - 1].clock_info[0];
1723 rdev->pm.power_state[state_index].flags &=
1724 ~RADEON_PM_SINGLE_DISPLAY_ONLY;
1727 /* add the i2c bus for thermal/fan chip */
1728 /* no support for internal controller yet */
1729 if (power_info->info_4.sThermalController.ucType > 0) {
1730 if ((power_info->info_4.sThermalController.ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) ||
1731 (power_info->info_4.sThermalController.ucType == ATOM_PP_THERMALCONTROLLER_RV770) ||
1732 (power_info->info_4.sThermalController.ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN)) {
1733 DRM_INFO("Internal thermal controller %s fan control\n",
1734 (power_info->info_4.sThermalController.ucFanParameters &
1735 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
1736 } else if ((power_info->info_4.sThermalController.ucType ==
1737 ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) ||
1738 (power_info->info_4.sThermalController.ucType ==
1739 ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL)) {
1740 DRM_INFO("Special thermal controller config\n");
1742 DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
1743 pp_lib_thermal_controller_names[power_info->info_4.sThermalController.ucType],
1744 power_info->info_4.sThermalController.ucI2cAddress >> 1,
1745 (power_info->info_4.sThermalController.ucFanParameters &
1746 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
1747 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info_4.sThermalController.ucI2cLine);
1748 rdev->pm.i2c_bus = radeon_i2c_create(rdev->ddev, &i2c_bus, "Thermal");
1751 /* first mode is usually default, followed by low to high */
1752 for (i = 0; i < power_info->info_4.ucNumStates; i++) {
1754 power_state = (struct _ATOM_PPLIB_STATE *)
1755 (mode_info->atom_context->bios +
1757 le16_to_cpu(power_info->info_4.usStateArrayOffset) +
1758 i * power_info->info_4.ucStateEntrySize);
1759 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
1760 (mode_info->atom_context->bios +
1762 le16_to_cpu(power_info->info_4.usNonClockInfoArrayOffset) +
1763 (power_state->ucNonClockStateIndex *
1764 power_info->info_4.ucNonClockSize));
1765 for (j = 0; j < (power_info->info_4.ucStateEntrySize - 1); j++) {
1766 if (rdev->flags & RADEON_IS_IGP) {
1767 struct _ATOM_PPLIB_RS780_CLOCK_INFO *clock_info =
1768 (struct _ATOM_PPLIB_RS780_CLOCK_INFO *)
1769 (mode_info->atom_context->bios +
1771 le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) +
1772 (power_state->ucClockStateIndices[j] *
1773 power_info->info_4.ucClockInfoSize));
1774 sclk = le16_to_cpu(clock_info->usLowEngineClockLow);
1775 sclk |= clock_info->ucLowEngineClockHigh << 16;
1776 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
1777 /* skip invalid modes */
1778 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
1780 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
1782 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
1785 } else if (ASIC_IS_DCE4(rdev)) {
1786 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO *clock_info =
1787 (struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO *)
1788 (mode_info->atom_context->bios +
1790 le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) +
1791 (power_state->ucClockStateIndices[j] *
1792 power_info->info_4.ucClockInfoSize));
1793 sclk = le16_to_cpu(clock_info->usEngineClockLow);
1794 sclk |= clock_info->ucEngineClockHigh << 16;
1795 mclk = le16_to_cpu(clock_info->usMemoryClockLow);
1796 mclk |= clock_info->ucMemoryClockHigh << 16;
1797 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
1798 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
1799 /* skip invalid modes */
1800 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
1801 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
1803 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
1805 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
1810 struct _ATOM_PPLIB_R600_CLOCK_INFO *clock_info =
1811 (struct _ATOM_PPLIB_R600_CLOCK_INFO *)
1812 (mode_info->atom_context->bios +
1814 le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) +
1815 (power_state->ucClockStateIndices[j] *
1816 power_info->info_4.ucClockInfoSize));
1817 sclk = le16_to_cpu(clock_info->usEngineClockLow);
1818 sclk |= clock_info->ucEngineClockHigh << 16;
1819 mclk = le16_to_cpu(clock_info->usMemoryClockLow);
1820 mclk |= clock_info->ucMemoryClockHigh << 16;
1821 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
1822 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
1823 /* skip invalid modes */
1824 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
1825 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
1827 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
1829 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
1834 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
1836 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
1837 misc2 = le16_to_cpu(non_clock_info->usClassification);
1838 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
1839 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
1840 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
1841 switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
1842 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
1843 rdev->pm.power_state[state_index].type =
1844 POWER_STATE_TYPE_BATTERY;
1846 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
1847 rdev->pm.power_state[state_index].type =
1848 POWER_STATE_TYPE_BALANCED;
1850 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
1851 rdev->pm.power_state[state_index].type =
1852 POWER_STATE_TYPE_PERFORMANCE;
1855 rdev->pm.power_state[state_index].flags = 0;
1856 if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
1857 rdev->pm.power_state[state_index].flags |=
1858 RADEON_PM_SINGLE_DISPLAY_ONLY;
1859 if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
1860 rdev->pm.power_state[state_index].type =
1861 POWER_STATE_TYPE_DEFAULT;
1862 rdev->pm.default_power_state_index = state_index;
1863 rdev->pm.power_state[state_index].default_clock_mode =
1864 &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
1869 /* first mode is usually default */
1870 if (rdev->pm.default_power_state_index == -1) {
1871 rdev->pm.power_state[0].type =
1872 POWER_STATE_TYPE_DEFAULT;
1873 rdev->pm.default_power_state_index = 0;
1874 rdev->pm.power_state[0].default_clock_mode =
1875 &rdev->pm.power_state[0].clock_info[0];
1879 /* add the default mode */
1880 rdev->pm.power_state[state_index].type =
1881 POWER_STATE_TYPE_DEFAULT;
1882 rdev->pm.power_state[state_index].num_clock_modes = 1;
1883 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
1884 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
1885 rdev->pm.power_state[state_index].default_clock_mode =
1886 &rdev->pm.power_state[state_index].clock_info[0];
1887 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
1888 if (rdev->asic->get_pcie_lanes)
1889 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = radeon_get_pcie_lanes(rdev);
1891 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = 16;
1892 rdev->pm.default_power_state_index = state_index;
1893 rdev->pm.power_state[state_index].flags = 0;
1897 rdev->pm.num_power_states = state_index;
1899 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
1900 rdev->pm.current_clock_mode_index = 0;
1903 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
1905 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
1906 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
1908 args.ucEnable = enable;
1910 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1913 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
1915 GET_ENGINE_CLOCK_PS_ALLOCATION args;
1916 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
1918 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1919 return args.ulReturnEngineClock;
1922 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
1924 GET_MEMORY_CLOCK_PS_ALLOCATION args;
1925 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
1927 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1928 return args.ulReturnMemoryClock;
1931 void radeon_atom_set_engine_clock(struct radeon_device *rdev,
1934 SET_ENGINE_CLOCK_PS_ALLOCATION args;
1935 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
1937 args.ulTargetEngineClock = eng_clock; /* 10 khz */
1939 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1942 void radeon_atom_set_memory_clock(struct radeon_device *rdev,
1945 SET_MEMORY_CLOCK_PS_ALLOCATION args;
1946 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
1948 if (rdev->flags & RADEON_IS_IGP)
1951 args.ulTargetMemoryClock = mem_clock; /* 10 khz */
1953 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1956 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
1958 struct radeon_device *rdev = dev->dev_private;
1959 uint32_t bios_2_scratch, bios_6_scratch;
1961 if (rdev->family >= CHIP_R600) {
1962 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
1963 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
1965 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
1966 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
1969 /* let the bios control the backlight */
1970 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
1972 /* tell the bios not to handle mode switching */
1973 bios_6_scratch |= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH | ATOM_S6_ACC_MODE);
1975 if (rdev->family >= CHIP_R600) {
1976 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
1977 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
1979 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
1980 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
1985 void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
1987 uint32_t scratch_reg;
1990 if (rdev->family >= CHIP_R600)
1991 scratch_reg = R600_BIOS_0_SCRATCH;
1993 scratch_reg = RADEON_BIOS_0_SCRATCH;
1995 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
1996 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
1999 void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
2001 uint32_t scratch_reg;
2004 if (rdev->family >= CHIP_R600)
2005 scratch_reg = R600_BIOS_0_SCRATCH;
2007 scratch_reg = RADEON_BIOS_0_SCRATCH;
2009 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
2010 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
2013 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
2015 struct drm_device *dev = encoder->dev;
2016 struct radeon_device *rdev = dev->dev_private;
2017 uint32_t bios_6_scratch;
2019 if (rdev->family >= CHIP_R600)
2020 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2022 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2025 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
2027 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
2029 if (rdev->family >= CHIP_R600)
2030 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2032 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2035 /* at some point we may want to break this out into individual functions */
2037 radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
2038 struct drm_encoder *encoder,
2041 struct drm_device *dev = connector->dev;
2042 struct radeon_device *rdev = dev->dev_private;
2043 struct radeon_connector *radeon_connector =
2044 to_radeon_connector(connector);
2045 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2046 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
2048 if (rdev->family >= CHIP_R600) {
2049 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2050 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2051 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2053 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2054 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2055 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2058 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
2059 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
2061 DRM_DEBUG("TV1 connected\n");
2062 bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
2063 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
2065 DRM_DEBUG("TV1 disconnected\n");
2066 bios_0_scratch &= ~ATOM_S0_TV1_MASK;
2067 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
2068 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
2071 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
2072 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
2074 DRM_DEBUG("CV connected\n");
2075 bios_3_scratch |= ATOM_S3_CV_ACTIVE;
2076 bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
2078 DRM_DEBUG("CV disconnected\n");
2079 bios_0_scratch &= ~ATOM_S0_CV_MASK;
2080 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
2081 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
2084 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
2085 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
2087 DRM_DEBUG("LCD1 connected\n");
2088 bios_0_scratch |= ATOM_S0_LCD1;
2089 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
2090 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
2092 DRM_DEBUG("LCD1 disconnected\n");
2093 bios_0_scratch &= ~ATOM_S0_LCD1;
2094 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
2095 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
2098 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
2099 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
2101 DRM_DEBUG("CRT1 connected\n");
2102 bios_0_scratch |= ATOM_S0_CRT1_COLOR;
2103 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
2104 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
2106 DRM_DEBUG("CRT1 disconnected\n");
2107 bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
2108 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
2109 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
2112 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
2113 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
2115 DRM_DEBUG("CRT2 connected\n");
2116 bios_0_scratch |= ATOM_S0_CRT2_COLOR;
2117 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
2118 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
2120 DRM_DEBUG("CRT2 disconnected\n");
2121 bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
2122 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
2123 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
2126 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
2127 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
2129 DRM_DEBUG("DFP1 connected\n");
2130 bios_0_scratch |= ATOM_S0_DFP1;
2131 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
2132 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
2134 DRM_DEBUG("DFP1 disconnected\n");
2135 bios_0_scratch &= ~ATOM_S0_DFP1;
2136 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
2137 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
2140 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
2141 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
2143 DRM_DEBUG("DFP2 connected\n");
2144 bios_0_scratch |= ATOM_S0_DFP2;
2145 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
2146 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
2148 DRM_DEBUG("DFP2 disconnected\n");
2149 bios_0_scratch &= ~ATOM_S0_DFP2;
2150 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
2151 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
2154 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
2155 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
2157 DRM_DEBUG("DFP3 connected\n");
2158 bios_0_scratch |= ATOM_S0_DFP3;
2159 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
2160 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
2162 DRM_DEBUG("DFP3 disconnected\n");
2163 bios_0_scratch &= ~ATOM_S0_DFP3;
2164 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
2165 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
2168 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
2169 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
2171 DRM_DEBUG("DFP4 connected\n");
2172 bios_0_scratch |= ATOM_S0_DFP4;
2173 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
2174 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
2176 DRM_DEBUG("DFP4 disconnected\n");
2177 bios_0_scratch &= ~ATOM_S0_DFP4;
2178 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
2179 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
2182 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
2183 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
2185 DRM_DEBUG("DFP5 connected\n");
2186 bios_0_scratch |= ATOM_S0_DFP5;
2187 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
2188 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
2190 DRM_DEBUG("DFP5 disconnected\n");
2191 bios_0_scratch &= ~ATOM_S0_DFP5;
2192 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
2193 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
2197 if (rdev->family >= CHIP_R600) {
2198 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
2199 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2200 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2202 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
2203 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2204 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2209 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
2211 struct drm_device *dev = encoder->dev;
2212 struct radeon_device *rdev = dev->dev_private;
2213 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2214 uint32_t bios_3_scratch;
2216 if (rdev->family >= CHIP_R600)
2217 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2219 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2221 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2222 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
2223 bios_3_scratch |= (crtc << 18);
2225 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2226 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
2227 bios_3_scratch |= (crtc << 24);
2229 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2230 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
2231 bios_3_scratch |= (crtc << 16);
2233 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2234 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
2235 bios_3_scratch |= (crtc << 20);
2237 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2238 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
2239 bios_3_scratch |= (crtc << 17);
2241 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2242 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
2243 bios_3_scratch |= (crtc << 19);
2245 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2246 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
2247 bios_3_scratch |= (crtc << 23);
2249 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2250 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
2251 bios_3_scratch |= (crtc << 25);
2254 if (rdev->family >= CHIP_R600)
2255 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2257 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2261 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
2263 struct drm_device *dev = encoder->dev;
2264 struct radeon_device *rdev = dev->dev_private;
2265 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2266 uint32_t bios_2_scratch;
2268 if (rdev->family >= CHIP_R600)
2269 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
2271 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
2273 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2275 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
2277 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
2279 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2281 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
2283 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
2285 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2287 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
2289 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
2291 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2293 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
2295 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
2297 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2299 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
2301 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
2303 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2305 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
2307 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
2309 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2311 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
2313 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
2315 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2317 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
2319 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
2321 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
2323 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
2325 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
2327 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
2329 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
2331 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
2334 if (rdev->family >= CHIP_R600)
2335 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2337 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);