Pileus Git - ~andy/linux/blob - drivers/gpu/drm/radeon/r600.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/slab.h>
  29 #include <linux/seq_file.h>
  30 #include <linux/firmware.h>
  31 #include <linux/platform_device.h>
  32 #include "drmP.h"
  33 #include "radeon_drm.h"
  34 #include "radeon.h"
  35 #include "radeon_asic.h"
  36 #include "radeon_mode.h"
  37 #include "r600d.h"
  38 #include "atom.h"
  39 #include "avivod.h"
  40
  41 #define PFP_UCODE_SIZE 576
  42 #define PM4_UCODE_SIZE 1792
  43 #define RLC_UCODE_SIZE 768
  44 #define R700_PFP_UCODE_SIZE 848
  45 #define R700_PM4_UCODE_SIZE 1360
  46 #define R700_RLC_UCODE_SIZE 1024
  47 #define EVERGREEN_PFP_UCODE_SIZE 1120
  48 #define EVERGREEN_PM4_UCODE_SIZE 1376
  49 #define EVERGREEN_RLC_UCODE_SIZE 768
  50
  51 /* Firmware Names */
  52 MODULE_FIRMWARE("radeon/R600_pfp.bin");
  53 MODULE_FIRMWARE("radeon/R600_me.bin");
  54 MODULE_FIRMWARE("radeon/RV610_pfp.bin");
  55 MODULE_FIRMWARE("radeon/RV610_me.bin");
  56 MODULE_FIRMWARE("radeon/RV630_pfp.bin");
  57 MODULE_FIRMWARE("radeon/RV630_me.bin");
  58 MODULE_FIRMWARE("radeon/RV620_pfp.bin");
  59 MODULE_FIRMWARE("radeon/RV620_me.bin");
  60 MODULE_FIRMWARE("radeon/RV635_pfp.bin");
  61 MODULE_FIRMWARE("radeon/RV635_me.bin");
  62 MODULE_FIRMWARE("radeon/RV670_pfp.bin");
  63 MODULE_FIRMWARE("radeon/RV670_me.bin");
  64 MODULE_FIRMWARE("radeon/RS780_pfp.bin");
  65 MODULE_FIRMWARE("radeon/RS780_me.bin");
  66 MODULE_FIRMWARE("radeon/RV770_pfp.bin");
  67 MODULE_FIRMWARE("radeon/RV770_me.bin");
  68 MODULE_FIRMWARE("radeon/RV730_pfp.bin");
  69 MODULE_FIRMWARE("radeon/RV730_me.bin");
  70 MODULE_FIRMWARE("radeon/RV710_pfp.bin");
  71 MODULE_FIRMWARE("radeon/RV710_me.bin");
  72 MODULE_FIRMWARE("radeon/R600_rlc.bin");
  73 MODULE_FIRMWARE("radeon/R700_rlc.bin");
  74 MODULE_FIRMWARE("radeon/CEDAR_pfp.bin");
  75 MODULE_FIRMWARE("radeon/CEDAR_me.bin");
  76 MODULE_FIRMWARE("radeon/CEDAR_rlc.bin");
  77 MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin");
  78 MODULE_FIRMWARE("radeon/REDWOOD_me.bin");
  79 MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin");
  80 MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin");
  81 MODULE_FIRMWARE("radeon/JUNIPER_me.bin");
  82 MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin");
  83 MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin");
  84 MODULE_FIRMWARE("radeon/CYPRESS_me.bin");
  85 MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin");
  86 MODULE_FIRMWARE("radeon/PALM_pfp.bin");
  87 MODULE_FIRMWARE("radeon/PALM_me.bin");
  88 MODULE_FIRMWARE("radeon/SUMO_rlc.bin");
  89
  90 int r600_debugfs_mc_info_init(struct radeon_device *rdev);
  91
  92 /* r600,rv610,rv630,rv620,rv635,rv670 */
  93 int r600_mc_wait_for_idle(struct radeon_device *rdev);
  94 void r600_gpu_init(struct radeon_device *rdev);
  95 void r600_fini(struct radeon_device *rdev);
  96 void r600_irq_disable(struct radeon_device *rdev);
  97
  98 /* get temperature in millidegrees */
  99 u32 rv6xx_get_temp(struct radeon_device *rdev)
 100 {
 101         u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >>
 102                 ASIC_T_SHIFT;
 103
 104         return temp * 1000;
 105 }
 106
 107 void r600_pm_get_dynpm_state(struct radeon_device *rdev)
 108 {
 109         int i;
 110
 111         rdev->pm.dynpm_can_upclock = true;
 112         rdev->pm.dynpm_can_downclock = true;
 113
 114         /* power state array is low to high, default is first */
 115         if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) {
 116                 int min_power_state_index = 0;
 117
 118                 if (rdev->pm.num_power_states > 2)
 119                         min_power_state_index = 1;
 120
 121                 switch (rdev->pm.dynpm_planned_action) {
 122                 case DYNPM_ACTION_MINIMUM:
 123                         rdev->pm.requested_power_state_index = min_power_state_index;
 124                         rdev->pm.requested_clock_mode_index = 0;
 125                         rdev->pm.dynpm_can_downclock = false;
 126                         break;
 127                 case DYNPM_ACTION_DOWNCLOCK:
 128                         if (rdev->pm.current_power_state_index == min_power_state_index) {
 129                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 130                                 rdev->pm.dynpm_can_downclock = false;
 131                         } else {
 132                                 if (rdev->pm.active_crtc_count > 1) {
 133                                         for (i = 0; i < rdev->pm.num_power_states; i++) {
 134                                                 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 135                                                         continue;
 136                                                 else if (i >= rdev->pm.current_power_state_index) {
 137                                                         rdev->pm.requested_power_state_index =
 138                                                                 rdev->pm.current_power_state_index;
 139                                                         break;
 140                                                 } else {
 141                                                         rdev->pm.requested_power_state_index = i;
 142                                                         break;
 143                                                 }
 144                                         }
 145                                 } else {
 146                                         if (rdev->pm.current_power_state_index == 0)
 147                                                 rdev->pm.requested_power_state_index =
 148                                                         rdev->pm.num_power_states - 1;
 149                                         else
 150                                                 rdev->pm.requested_power_state_index =
 151                                                         rdev->pm.current_power_state_index - 1;
 152                                 }
 153                         }
 154                         rdev->pm.requested_clock_mode_index = 0;
 155                         /* don't use the power state if crtcs are active and no display flag is set */
 156                         if ((rdev->pm.active_crtc_count > 0) &&
 157                             (rdev->pm.power_state[rdev->pm.requested_power_state_index].
 158                              clock_info[rdev->pm.requested_clock_mode_index].flags &
 159                              RADEON_PM_MODE_NO_DISPLAY)) {
 160                                 rdev->pm.requested_power_state_index++;
 161                         }
 162                         break;
 163                 case DYNPM_ACTION_UPCLOCK:
 164                         if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
 165                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 166                                 rdev->pm.dynpm_can_upclock = false;
 167                         } else {
 168                                 if (rdev->pm.active_crtc_count > 1) {
 169                                         for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
 170                                                 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 171                                                         continue;
 172                                                 else if (i <= rdev->pm.current_power_state_index) {
 173                                                         rdev->pm.requested_power_state_index =
 174                                                                 rdev->pm.current_power_state_index;
 175                                                         break;
 176                                                 } else {
 177                                                         rdev->pm.requested_power_state_index = i;
 178                                                         break;
 179                                                 }
 180                                         }
 181                                 } else
 182                                         rdev->pm.requested_power_state_index =
 183                                                 rdev->pm.current_power_state_index + 1;
 184                         }
 185                         rdev->pm.requested_clock_mode_index = 0;
 186                         break;
 187                 case DYNPM_ACTION_DEFAULT:
 188                         rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
 189                         rdev->pm.requested_clock_mode_index = 0;
 190                         rdev->pm.dynpm_can_upclock = false;
 191                         break;
 192                 case DYNPM_ACTION_NONE:
 193                 default:
 194                         DRM_ERROR("Requested mode for not defined action\n");
 195                         return;
 196                 }
 197         } else {
 198                 /* XXX select a power state based on AC/DC, single/dualhead, etc. */
 199                 /* for now just select the first power state and switch between clock modes */
 200                 /* power state array is low to high, default is first (0) */
 201                 if (rdev->pm.active_crtc_count > 1) {
 202                         rdev->pm.requested_power_state_index = -1;
 203                         /* start at 1 as we don't want the default mode */
 204                         for (i = 1; i < rdev->pm.num_power_states; i++) {
 205                                 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 206                                         continue;
 207                                 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) ||
 208                                          (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) {
 209                                         rdev->pm.requested_power_state_index = i;
 210                                         break;
 211                                 }
 212                         }
 213                         /* if nothing selected, grab the default state. */
 214                         if (rdev->pm.requested_power_state_index == -1)
 215                                 rdev->pm.requested_power_state_index = 0;
 216                 } else
 217                         rdev->pm.requested_power_state_index = 1;
 218
 219                 switch (rdev->pm.dynpm_planned_action) {
 220                 case DYNPM_ACTION_MINIMUM:
 221                         rdev->pm.requested_clock_mode_index = 0;
 222                         rdev->pm.dynpm_can_downclock = false;
 223                         break;
 224                 case DYNPM_ACTION_DOWNCLOCK:
 225                         if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
 226                                 if (rdev->pm.current_clock_mode_index == 0) {
 227                                         rdev->pm.requested_clock_mode_index = 0;
 228                                         rdev->pm.dynpm_can_downclock = false;
 229                                 } else
 230                                         rdev->pm.requested_clock_mode_index =
 231                                                 rdev->pm.current_clock_mode_index - 1;
 232                         } else {
 233                                 rdev->pm.requested_clock_mode_index = 0;
 234                                 rdev->pm.dynpm_can_downclock = false;
 235                         }
 236                         /* don't use the power state if crtcs are active and no display flag is set */
 237                         if ((rdev->pm.active_crtc_count > 0) &&
 238                             (rdev->pm.power_state[rdev->pm.requested_power_state_index].
 239                              clock_info[rdev->pm.requested_clock_mode_index].flags &
 240                              RADEON_PM_MODE_NO_DISPLAY)) {
 241                                 rdev->pm.requested_clock_mode_index++;
 242                         }
 243                         break;
 244                 case DYNPM_ACTION_UPCLOCK:
 245                         if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
 246                                 if (rdev->pm.current_clock_mode_index ==
 247                                     (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) {
 248                                         rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index;
 249                                         rdev->pm.dynpm_can_upclock = false;
 250                                 } else
 251                                         rdev->pm.requested_clock_mode_index =
 252                                                 rdev->pm.current_clock_mode_index + 1;
 253                         } else {
 254                                 rdev->pm.requested_clock_mode_index =
 255                                         rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1;
 256                                 rdev->pm.dynpm_can_upclock = false;
 257                         }
 258                         break;
 259                 case DYNPM_ACTION_DEFAULT:
 260                         rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
 261                         rdev->pm.requested_clock_mode_index = 0;
 262                         rdev->pm.dynpm_can_upclock = false;
 263                         break;
 264                 case DYNPM_ACTION_NONE:
 265                 default:
 266                         DRM_ERROR("Requested mode for not defined action\n");
 267                         return;
 268                 }
 269         }
 270
 271         DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
 272                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 273                   clock_info[rdev->pm.requested_clock_mode_index].sclk,
 274                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 275                   clock_info[rdev->pm.requested_clock_mode_index].mclk,
 276                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 277                   pcie_lanes);
 278 }
 279
 280 static int r600_pm_get_type_index(struct radeon_device *rdev,
 281                                   enum radeon_pm_state_type ps_type,
 282                                   int instance)
 283 {
 284         int i;
 285         int found_instance = -1;
 286
 287         for (i = 0; i < rdev->pm.num_power_states; i++) {
 288                 if (rdev->pm.power_state[i].type == ps_type) {
 289                         found_instance++;
 290                         if (found_instance == instance)
 291                                 return i;
 292                 }
 293         }
 294         /* return default if no match */
 295         return rdev->pm.default_power_state_index;
 296 }
 297
 298 void rs780_pm_init_profile(struct radeon_device *rdev)
 299 {
 300         if (rdev->pm.num_power_states == 2) {
 301                 /* default */
 302                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 303                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 304                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 305                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 306                 /* low sh */
 307                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
 308                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
 309                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 310                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 311                 /* mid sh */
 312                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
 313                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
 314                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 315                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 316                 /* high sh */
 317                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
 318                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
 319                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 320                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 321                 /* low mh */
 322                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
 323                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
 324                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 325                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 326                 /* mid mh */
 327                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
 328                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
 329                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 330                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 331                 /* high mh */
 332                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
 333                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1;
 334                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 335                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 336         } else if (rdev->pm.num_power_states == 3) {
 337                 /* default */
 338                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 339                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 340                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 341                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 342                 /* low sh */
 343                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
 344                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
 345                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 346                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 347                 /* mid sh */
 348                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
 349                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
 350                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 351                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 352                 /* high sh */
 353                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
 354                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2;
 355                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 356                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 357                 /* low mh */
 358                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1;
 359                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1;
 360                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 361                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 362                 /* mid mh */
 363                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1;
 364                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1;
 365                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 366                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 367                 /* high mh */
 368                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1;
 369                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
 370                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 371                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 372         } else {
 373                 /* default */
 374                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 375                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 376                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 377                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 378                 /* low sh */
 379                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2;
 380                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2;
 381                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 382                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 383                 /* mid sh */
 384                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2;
 385                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2;
 386                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 387                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 388                 /* high sh */
 389                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2;
 390                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3;
 391                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 392                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 393                 /* low mh */
 394                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
 395                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
 396                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 397                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 398                 /* mid mh */
 399                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
 400                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
 401                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 402                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 403                 /* high mh */
 404                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
 405                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3;
 406                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 407                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 408         }
 409 }
 410
 411 void r600_pm_init_profile(struct radeon_device *rdev)
 412 {
 413         if (rdev->family == CHIP_R600) {
 414                 /* XXX */
 415                 /* default */
 416                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 417                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 418                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 419                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 420                 /* low sh */
 421                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 422                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 423                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 424                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 425                 /* mid sh */
 426                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 427                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 428                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 429                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 430                 /* high sh */
 431                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 432                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 433                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 434                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 435                 /* low mh */
 436                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 437                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 438                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 439                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 440                 /* mid mh */
 441                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 442                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 443                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 444                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 445                 /* high mh */
 446                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 447                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 448                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 449                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 450         } else {
 451                 if (rdev->pm.num_power_states < 4) {
 452                         /* default */
 453                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 454                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 455                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 456                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
 457                         /* low sh */
 458                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
 459                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
 460                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 461                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 462                         /* mid sh */
 463                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
 464                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
 465                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 466                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
 467                         /* high sh */
 468                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
 469                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
 470                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 471                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
 472                         /* low mh */
 473                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
 474                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2;
 475                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 476                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 477                         /* low mh */
 478                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
 479                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2;
 480                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 481                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
 482                         /* high mh */
 483                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
 484                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
 485                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 486                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
 487                 } else {
 488                         /* default */
 489                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 490                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 491                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 492                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
 493                         /* low sh */
 494                         if (rdev->flags & RADEON_IS_MOBILITY) {
 495                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx =
 496                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
 497                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx =
 498                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
 499                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 500                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 501                         } else {
 502                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx =
 503                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 504                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx =
 505                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 506                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 507                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 508                         }
 509                         /* mid sh */
 510                         if (rdev->flags & RADEON_IS_MOBILITY) {
 511                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx =
 512                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
 513                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx =
 514                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
 515                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 516                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
 517                         } else {
 518                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx =
 519                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 520                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx =
 521                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 522                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 523                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
 524                         }
 525                         /* high sh */
 526                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx =
 527                                 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 528                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx =
 529                                 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 530                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 531                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
 532                         /* low mh */
 533                         if (rdev->flags & RADEON_IS_MOBILITY) {
 534                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx =
 535                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
 536                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx =
 537                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
 538                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 539                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 540                         } else {
 541                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx =
 542                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 543                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx =
 544                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 545                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 546                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 547                         }
 548                         /* mid mh */
 549                         if (rdev->flags & RADEON_IS_MOBILITY) {
 550                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx =
 551                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
 552                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx =
 553                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
 554                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 555                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
 556                         } else {
 557                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx =
 558                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 559                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx =
 560                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 561                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 562                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
 563                         }
 564                         /* high mh */
 565                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx =
 566                                 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 567                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx =
 568                                 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 569                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 570                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
 571                 }
 572         }
 573 }
 574
 575 void r600_pm_misc(struct radeon_device *rdev)
 576 {
 577         int req_ps_idx = rdev->pm.requested_power_state_index;
 578         int req_cm_idx = rdev->pm.requested_clock_mode_index;
 579         struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
 580         struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
 581
 582         if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
 583                 if (voltage->voltage != rdev->pm.current_vddc) {
 584                         radeon_atom_set_voltage(rdev, voltage->voltage);
 585                         rdev->pm.current_vddc = voltage->voltage;
 586                         DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage->voltage);
 587                 }
 588         }
 589 }
 590
 591 bool r600_gui_idle(struct radeon_device *rdev)
 592 {
 593         if (RREG32(GRBM_STATUS) & GUI_ACTIVE)
 594                 return false;
 595         else
 596                 return true;
 597 }
 598
 599 /* hpd for digital panel detect/disconnect */
 600 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
 601 {
 602         bool connected = false;
 603
 604         if (ASIC_IS_DCE3(rdev)) {
 605                 switch (hpd) {
 606                 case RADEON_HPD_1:
 607                         if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
 608                                 connected = true;
 609                         break;
 610                 case RADEON_HPD_2:
 611                         if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
 612                                 connected = true;
 613                         break;
 614                 case RADEON_HPD_3:
 615                         if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
 616                                 connected = true;
 617                         break;
 618                 case RADEON_HPD_4:
 619                         if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
 620                                 connected = true;
 621                         break;
 622                         /* DCE 3.2 */
 623                 case RADEON_HPD_5:
 624                         if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
 625                                 connected = true;
 626                         break;
 627                 case RADEON_HPD_6:
 628                         if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
 629                                 connected = true;
 630                         break;
 631                 default:
 632                         break;
 633                 }
 634         } else {
 635                 switch (hpd) {
 636                 case RADEON_HPD_1:
 637                         if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 638                                 connected = true;
 639                         break;
 640                 case RADEON_HPD_2:
 641                         if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 642                                 connected = true;
 643                         break;
 644                 case RADEON_HPD_3:
 645                         if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 646                                 connected = true;
 647                         break;
 648                 default:
 649                         break;
 650                 }
 651         }
 652         return connected;
 653 }
 654
 655 void r600_hpd_set_polarity(struct radeon_device *rdev,
 656                            enum radeon_hpd_id hpd)
 657 {
 658         u32 tmp;
 659         bool connected = r600_hpd_sense(rdev, hpd);
 660
 661         if (ASIC_IS_DCE3(rdev)) {
 662                 switch (hpd) {
 663                 case RADEON_HPD_1:
 664                         tmp = RREG32(DC_HPD1_INT_CONTROL);
 665                         if (connected)
 666                                 tmp &= ~DC_HPDx_INT_POLARITY;
 667                         else
 668                                 tmp |= DC_HPDx_INT_POLARITY;
 669                         WREG32(DC_HPD1_INT_CONTROL, tmp);
 670                         break;
 671                 case RADEON_HPD_2:
 672                         tmp = RREG32(DC_HPD2_INT_CONTROL);
 673                         if (connected)
 674                                 tmp &= ~DC_HPDx_INT_POLARITY;
 675                         else
 676                                 tmp |= DC_HPDx_INT_POLARITY;
 677                         WREG32(DC_HPD2_INT_CONTROL, tmp);
 678                         break;
 679                 case RADEON_HPD_3:
 680                         tmp = RREG32(DC_HPD3_INT_CONTROL);
 681                         if (connected)
 682                                 tmp &= ~DC_HPDx_INT_POLARITY;
 683                         else
 684                                 tmp |= DC_HPDx_INT_POLARITY;
 685                         WREG32(DC_HPD3_INT_CONTROL, tmp);
 686                         break;
 687                 case RADEON_HPD_4:
 688                         tmp = RREG32(DC_HPD4_INT_CONTROL);
 689                         if (connected)
 690                                 tmp &= ~DC_HPDx_INT_POLARITY;
 691                         else
 692                                 tmp |= DC_HPDx_INT_POLARITY;
 693                         WREG32(DC_HPD4_INT_CONTROL, tmp);
 694                         break;
 695                 case RADEON_HPD_5:
 696                         tmp = RREG32(DC_HPD5_INT_CONTROL);
 697                         if (connected)
 698                                 tmp &= ~DC_HPDx_INT_POLARITY;
 699                         else
 700                                 tmp |= DC_HPDx_INT_POLARITY;
 701                         WREG32(DC_HPD5_INT_CONTROL, tmp);
 702                         break;
 703                         /* DCE 3.2 */
 704                 case RADEON_HPD_6:
 705                         tmp = RREG32(DC_HPD6_INT_CONTROL);
 706                         if (connected)
 707                                 tmp &= ~DC_HPDx_INT_POLARITY;
 708                         else
 709                                 tmp |= DC_HPDx_INT_POLARITY;
 710                         WREG32(DC_HPD6_INT_CONTROL, tmp);
 711                         break;
 712                 default:
 713                         break;
 714                 }
 715         } else {
 716                 switch (hpd) {
 717                 case RADEON_HPD_1:
 718                         tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
 719                         if (connected)
 720                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 721                         else
 722                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 723                         WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
 724                         break;
 725                 case RADEON_HPD_2:
 726                         tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
 727                         if (connected)
 728                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 729                         else
 730                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 731                         WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
 732                         break;
 733                 case RADEON_HPD_3:
 734                         tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
 735                         if (connected)
 736                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 737                         else
 738                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 739                         WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
 740                         break;
 741                 default:
 742                         break;
 743                 }
 744         }
 745 }
 746
 747 void r600_hpd_init(struct radeon_device *rdev)
 748 {
 749         struct drm_device *dev = rdev->ddev;
 750         struct drm_connector *connector;
 751
 752         if (ASIC_IS_DCE3(rdev)) {
 753                 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
 754                 if (ASIC_IS_DCE32(rdev))
 755                         tmp |= DC_HPDx_EN;
 756
 757                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 758                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 759                         switch (radeon_connector->hpd.hpd) {
 760                         case RADEON_HPD_1:
 761                                 WREG32(DC_HPD1_CONTROL, tmp);
 762                                 rdev->irq.hpd[0] = true;
 763                                 break;
 764                         case RADEON_HPD_2:
 765                                 WREG32(DC_HPD2_CONTROL, tmp);
 766                                 rdev->irq.hpd[1] = true;
 767                                 break;
 768                         case RADEON_HPD_3:
 769                                 WREG32(DC_HPD3_CONTROL, tmp);
 770                                 rdev->irq.hpd[2] = true;
 771                                 break;
 772                         case RADEON_HPD_4:
 773                                 WREG32(DC_HPD4_CONTROL, tmp);
 774                                 rdev->irq.hpd[3] = true;
 775                                 break;
 776                                 /* DCE 3.2 */
 777                         case RADEON_HPD_5:
 778                                 WREG32(DC_HPD5_CONTROL, tmp);
 779                                 rdev->irq.hpd[4] = true;
 780                                 break;
 781                         case RADEON_HPD_6:
 782                                 WREG32(DC_HPD6_CONTROL, tmp);
 783                                 rdev->irq.hpd[5] = true;
 784                                 break;
 785                         default:
 786                                 break;
 787                         }
 788                 }
 789         } else {
 790                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 791                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 792                         switch (radeon_connector->hpd.hpd) {
 793                         case RADEON_HPD_1:
 794                                 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 795                                 rdev->irq.hpd[0] = true;
 796                                 break;
 797                         case RADEON_HPD_2:
 798                                 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 799                                 rdev->irq.hpd[1] = true;
 800                                 break;
 801                         case RADEON_HPD_3:
 802                                 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 803                                 rdev->irq.hpd[2] = true;
 804                                 break;
 805                         default:
 806                                 break;
 807                         }
 808                 }
 809         }
 810         if (rdev->irq.installed)
 811                 r600_irq_set(rdev);
 812 }
 813
 814 void r600_hpd_fini(struct radeon_device *rdev)
 815 {
 816         struct drm_device *dev = rdev->ddev;
 817         struct drm_connector *connector;
 818
 819         if (ASIC_IS_DCE3(rdev)) {
 820                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 821                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 822                         switch (radeon_connector->hpd.hpd) {
 823                         case RADEON_HPD_1:
 824                                 WREG32(DC_HPD1_CONTROL, 0);
 825                                 rdev->irq.hpd[0] = false;
 826                                 break;
 827                         case RADEON_HPD_2:
 828                                 WREG32(DC_HPD2_CONTROL, 0);
 829                                 rdev->irq.hpd[1] = false;
 830                                 break;
 831                         case RADEON_HPD_3:
 832                                 WREG32(DC_HPD3_CONTROL, 0);
 833                                 rdev->irq.hpd[2] = false;
 834                                 break;
 835                         case RADEON_HPD_4:
 836                                 WREG32(DC_HPD4_CONTROL, 0);
 837                                 rdev->irq.hpd[3] = false;
 838                                 break;
 839                                 /* DCE 3.2 */
 840                         case RADEON_HPD_5:
 841                                 WREG32(DC_HPD5_CONTROL, 0);
 842                                 rdev->irq.hpd[4] = false;
 843                                 break;
 844                         case RADEON_HPD_6:
 845                                 WREG32(DC_HPD6_CONTROL, 0);
 846                                 rdev->irq.hpd[5] = false;
 847                                 break;
 848                         default:
 849                                 break;
 850                         }
 851                 }
 852         } else {
 853                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 854                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 855                         switch (radeon_connector->hpd.hpd) {
 856                         case RADEON_HPD_1:
 857                                 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
 858                                 rdev->irq.hpd[0] = false;
 859                                 break;
 860                         case RADEON_HPD_2:
 861                                 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
 862                                 rdev->irq.hpd[1] = false;
 863                                 break;
 864                         case RADEON_HPD_3:
 865                                 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
 866                                 rdev->irq.hpd[2] = false;
 867                                 break;
 868                         default:
 869                                 break;
 870                         }
 871                 }
 872         }
 873 }
 874
 875 /*
 876  * R600 PCIE GART
 877  */
 878 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
 879 {
 880         unsigned i;
 881         u32 tmp;
 882
 883         /* flush hdp cache so updates hit vram */
 884         if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
 885             !(rdev->flags & RADEON_IS_AGP)) {
 886                 void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
 887                 u32 tmp;
 888
 889                 /* r7xx hw bug.  write to HDP_DEBUG1 followed by fb read
 890                  * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL
 891                  * This seems to cause problems on some AGP cards. Just use the old
 892                  * method for them.
 893                  */
 894                 WREG32(HDP_DEBUG1, 0);
 895                 tmp = readl((void __iomem *)ptr);
 896         } else
 897                 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
 898
 899         WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
 900         WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
 901         WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
 902         for (i = 0; i < rdev->usec_timeout; i++) {
 903                 /* read MC_STATUS */
 904                 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
 905                 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
 906                 if (tmp == 2) {
 907                         printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
 908                         return;
 909                 }
 910                 if (tmp) {
 911                         return;
 912                 }
 913                 udelay(1);
 914         }
 915 }
 916
 917 int r600_pcie_gart_init(struct radeon_device *rdev)
 918 {
 919         int r;
 920
 921         if (rdev->gart.table.vram.robj) {
 922                 WARN(1, "R600 PCIE GART already initialized\n");
 923                 return 0;
 924         }
 925         /* Initialize common gart structure */
 926         r = radeon_gart_init(rdev);
 927         if (r)
 928                 return r;
 929         rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
 930         return radeon_gart_table_vram_alloc(rdev);
 931 }
 932
 933 int r600_pcie_gart_enable(struct radeon_device *rdev)
 934 {
 935         u32 tmp;
 936         int r, i;
 937
 938         if (rdev->gart.table.vram.robj == NULL) {
 939                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
 940                 return -EINVAL;
 941         }
 942         r = radeon_gart_table_vram_pin(rdev);
 943         if (r)
 944                 return r;
 945         radeon_gart_restore(rdev);
 946
 947         /* Setup L2 cache */
 948         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 949                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 950                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 951         WREG32(VM_L2_CNTL2, 0);
 952         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
 953         /* Setup TLB control */
 954         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
 955                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 956                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
 957                 ENABLE_WAIT_L2_QUERY;
 958         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
 959         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
 960         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
 961         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
 962         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
 963         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
 964         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
 965         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
 966         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
 967         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
 968         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
 969         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
 970         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 971         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 972         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
 973         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
 974         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
 975         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
 976                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
 977         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 978                         (u32)(rdev->dummy_page.addr >> 12));
 979         for (i = 1; i < 7; i++)
 980                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 981
 982         r600_pcie_gart_tlb_flush(rdev);
 983         rdev->gart.ready = true;
 984         return 0;
 985 }
 986
 987 void r600_pcie_gart_disable(struct radeon_device *rdev)
 988 {
 989         u32 tmp;
 990         int i, r;
 991
 992         /* Disable all tables */
 993         for (i = 0; i < 7; i++)
 994                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 995
 996         /* Disable L2 cache */
 997         WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
 998                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 999         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1000         /* Setup L1 TLB control */
1001         tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1002                 ENABLE_WAIT_L2_QUERY;
1003         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1004         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1005         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1006         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1007         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1008         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1009         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1010         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1011         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
1012         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
1013         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1014         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1015         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
1016         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1017         if (rdev->gart.table.vram.robj) {
1018                 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
1019                 if (likely(r == 0)) {
1020                         radeon_bo_kunmap(rdev->gart.table.vram.robj);
1021                         radeon_bo_unpin(rdev->gart.table.vram.robj);
1022                         radeon_bo_unreserve(rdev->gart.table.vram.robj);
1023                 }
1024         }
1025 }
1026
1027 void r600_pcie_gart_fini(struct radeon_device *rdev)
1028 {
1029         radeon_gart_fini(rdev);
1030         r600_pcie_gart_disable(rdev);
1031         radeon_gart_table_vram_free(rdev);
1032 }
1033
1034 void r600_agp_enable(struct radeon_device *rdev)
1035 {
1036         u32 tmp;
1037         int i;
1038
1039         /* Setup L2 cache */
1040         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1041                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1042                                 EFFECTIVE_L2_QUEUE_SIZE(7));
1043         WREG32(VM_L2_CNTL2, 0);
1044         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1045         /* Setup TLB control */
1046         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1047                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1048                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1049                 ENABLE_WAIT_L2_QUERY;
1050         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1051         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1052         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
1053         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1054         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1055         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1056         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1057         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1058         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1059         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1060         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1061         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1062         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1063         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1064         for (i = 0; i < 7; i++)
1065                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1066 }
1067
1068 int r600_mc_wait_for_idle(struct radeon_device *rdev)
1069 {
1070         unsigned i;
1071         u32 tmp;
1072
1073         for (i = 0; i < rdev->usec_timeout; i++) {
1074                 /* read MC_STATUS */
1075                 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
1076                 if (!tmp)
1077                         return 0;
1078                 udelay(1);
1079         }
1080         return -1;
1081 }
1082
1083 static void r600_mc_program(struct radeon_device *rdev)
1084 {
1085         struct rv515_mc_save save;
1086         u32 tmp;
1087         int i, j;
1088
1089         /* Initialize HDP */
1090         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1091                 WREG32((0x2c14 + j), 0x00000000);
1092                 WREG32((0x2c18 + j), 0x00000000);
1093                 WREG32((0x2c1c + j), 0x00000000);
1094                 WREG32((0x2c20 + j), 0x00000000);
1095                 WREG32((0x2c24 + j), 0x00000000);
1096         }
1097         WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1098
1099         rv515_mc_stop(rdev, &save);
1100         if (r600_mc_wait_for_idle(rdev)) {
1101                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1102         }
1103         /* Lockout access through VGA aperture (doesn't exist before R600) */
1104         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1105         /* Update configuration */
1106         if (rdev->flags & RADEON_IS_AGP) {
1107                 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1108                         /* VRAM before AGP */
1109                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1110                                 rdev->mc.vram_start >> 12);
1111                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1112                                 rdev->mc.gtt_end >> 12);
1113                 } else {
1114                         /* VRAM after AGP */
1115                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1116                                 rdev->mc.gtt_start >> 12);
1117                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1118                                 rdev->mc.vram_end >> 12);
1119                 }
1120         } else {
1121                 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
1122                 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
1123         }
1124         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
1125         tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1126         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1127         WREG32(MC_VM_FB_LOCATION, tmp);
1128         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1129         WREG32(HDP_NONSURFACE_INFO, (2 << 7));
1130         WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
1131         if (rdev->flags & RADEON_IS_AGP) {
1132                 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
1133                 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
1134                 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1135         } else {
1136                 WREG32(MC_VM_AGP_BASE, 0);
1137                 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1138                 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1139         }
1140         if (r600_mc_wait_for_idle(rdev)) {
1141                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1142         }
1143         rv515_mc_resume(rdev, &save);
1144         /* we need to own VRAM, so turn off the VGA renderer here
1145          * to stop it overwriting our objects */
1146         rv515_vga_render_disable(rdev);
1147 }
1148
1149 /**
1150  * r600_vram_gtt_location - try to find VRAM & GTT location
1151  * @rdev: radeon device structure holding all necessary informations
1152  * @mc: memory controller structure holding memory informations
1153  *
1154  * Function will place try to place VRAM at same place as in CPU (PCI)
1155  * address space as some GPU seems to have issue when we reprogram at
1156  * different address space.
1157  *
1158  * If there is not enough space to fit the unvisible VRAM after the
1159  * aperture then we limit the VRAM size to the aperture.
1160  *
1161  * If we are using AGP then place VRAM adjacent to AGP aperture are we need
1162  * them to be in one from GPU point of view so that we can program GPU to
1163  * catch access outside them (weird GPU policy see ??).
1164  *
1165  * This function will never fails, worst case are limiting VRAM or GTT.
1166  *
1167  * Note: GTT start, end, size should be initialized before calling this
1168  * function on AGP platform.
1169  */
1170 static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
1171 {
1172         u64 size_bf, size_af;
1173
1174         if (mc->mc_vram_size > 0xE0000000) {
1175                 /* leave room for at least 512M GTT */
1176                 dev_warn(rdev->dev, "limiting VRAM\n");
1177                 mc->real_vram_size = 0xE0000000;
1178                 mc->mc_vram_size = 0xE0000000;
1179         }
1180         if (rdev->flags & RADEON_IS_AGP) {
1181                 size_bf = mc->gtt_start;
1182                 size_af = 0xFFFFFFFF - mc->gtt_end + 1;
1183                 if (size_bf > size_af) {
1184                         if (mc->mc_vram_size > size_bf) {
1185                                 dev_warn(rdev->dev, "limiting VRAM\n");
1186                                 mc->real_vram_size = size_bf;
1187                                 mc->mc_vram_size = size_bf;
1188                         }
1189                         mc->vram_start = mc->gtt_start - mc->mc_vram_size;
1190                 } else {
1191                         if (mc->mc_vram_size > size_af) {
1192                                 dev_warn(rdev->dev, "limiting VRAM\n");
1193                                 mc->real_vram_size = size_af;
1194                                 mc->mc_vram_size = size_af;
1195                         }
1196                         mc->vram_start = mc->gtt_end;
1197                 }
1198                 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
1199                 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
1200                                 mc->mc_vram_size >> 20, mc->vram_start,
1201                                 mc->vram_end, mc->real_vram_size >> 20);
1202         } else {
1203                 u64 base = 0;
1204                 if (rdev->flags & RADEON_IS_IGP) {
1205                         base = RREG32(MC_VM_FB_LOCATION) & 0xFFFF;
1206                         base <<= 24;
1207                 }
1208                 radeon_vram_location(rdev, &rdev->mc, base);
1209                 rdev->mc.gtt_base_align = 0;
1210                 radeon_gtt_location(rdev, mc);
1211         }
1212 }
1213
1214 int r600_mc_init(struct radeon_device *rdev)
1215 {
1216         u32 tmp;
1217         int chansize, numchan;
1218
1219         /* Get VRAM informations */
1220         rdev->mc.vram_is_ddr = true;
1221         tmp = RREG32(RAMCFG);
1222         if (tmp & CHANSIZE_OVERRIDE) {
1223                 chansize = 16;
1224         } else if (tmp & CHANSIZE_MASK) {
1225                 chansize = 64;
1226         } else {
1227                 chansize = 32;
1228         }
1229         tmp = RREG32(CHMAP);
1230         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1231         case 0:
1232         default:
1233                 numchan = 1;
1234                 break;
1235         case 1:
1236                 numchan = 2;
1237                 break;
1238         case 2:
1239                 numchan = 4;
1240                 break;
1241         case 3:
1242                 numchan = 8;
1243                 break;
1244         }
1245         rdev->mc.vram_width = numchan * chansize;
1246         /* Could aper size report 0 ? */
1247         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
1248         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
1249         /* Setup GPU memory space */
1250         rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1251         rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
1252         rdev->mc.visible_vram_size = rdev->mc.aper_size;
1253         rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
1254         r600_vram_gtt_location(rdev, &rdev->mc);
1255
1256         if (rdev->flags & RADEON_IS_IGP) {
1257                 rs690_pm_info(rdev);
1258                 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
1259         }
1260         radeon_update_bandwidth_info(rdev);
1261         return 0;
1262 }
1263
1264 /* We doesn't check that the GPU really needs a reset we simply do the
1265  * reset, it's up to the caller to determine if the GPU needs one. We
1266  * might add an helper function to check that.
1267  */
1268 int r600_gpu_soft_reset(struct radeon_device *rdev)
1269 {
1270         struct rv515_mc_save save;
1271         u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
1272                                 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
1273                                 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
1274                                 S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |
1275                                 S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |
1276                                 S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |
1277                                 S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |
1278                                 S_008010_GUI_ACTIVE(1);
1279         u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
1280                         S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
1281                         S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
1282                         S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
1283                         S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
1284                         S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
1285                         S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
1286                         S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
1287         u32 tmp;
1288
1289         dev_info(rdev->dev, "GPU softreset \n");
1290         dev_info(rdev->dev, "  R_008010_GRBM_STATUS=0x%08X\n",
1291                 RREG32(R_008010_GRBM_STATUS));
1292         dev_info(rdev->dev, "  R_008014_GRBM_STATUS2=0x%08X\n",
1293                 RREG32(R_008014_GRBM_STATUS2));
1294         dev_info(rdev->dev, "  R_000E50_SRBM_STATUS=0x%08X\n",
1295                 RREG32(R_000E50_SRBM_STATUS));
1296         rv515_mc_stop(rdev, &save);
1297         if (r600_mc_wait_for_idle(rdev)) {
1298                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1299         }
1300         /* Disable CP parsing/prefetching */
1301         WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1302         /* Check if any of the rendering block is busy and reset it */
1303         if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
1304             (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
1305                 tmp = S_008020_SOFT_RESET_CR(1) |
1306                         S_008020_SOFT_RESET_DB(1) |
1307                         S_008020_SOFT_RESET_CB(1) |
1308                         S_008020_SOFT_RESET_PA(1) |
1309                         S_008020_SOFT_RESET_SC(1) |
1310                         S_008020_SOFT_RESET_SMX(1) |
1311                         S_008020_SOFT_RESET_SPI(1) |
1312                         S_008020_SOFT_RESET_SX(1) |
1313                         S_008020_SOFT_RESET_SH(1) |
1314                         S_008020_SOFT_RESET_TC(1) |
1315                         S_008020_SOFT_RESET_TA(1) |
1316                         S_008020_SOFT_RESET_VC(1) |
1317                         S_008020_SOFT_RESET_VGT(1);
1318                 dev_info(rdev->dev, "  R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1319                 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1320                 RREG32(R_008020_GRBM_SOFT_RESET);
1321                 mdelay(15);
1322                 WREG32(R_008020_GRBM_SOFT_RESET, 0);
1323         }
1324         /* Reset CP (we always reset CP) */
1325         tmp = S_008020_SOFT_RESET_CP(1);
1326         dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1327         WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1328         RREG32(R_008020_GRBM_SOFT_RESET);
1329         mdelay(15);
1330         WREG32(R_008020_GRBM_SOFT_RESET, 0);
1331         /* Wait a little for things to settle down */
1332         mdelay(1);
1333         dev_info(rdev->dev, "  R_008010_GRBM_STATUS=0x%08X\n",
1334                 RREG32(R_008010_GRBM_STATUS));
1335         dev_info(rdev->dev, "  R_008014_GRBM_STATUS2=0x%08X\n",
1336                 RREG32(R_008014_GRBM_STATUS2));
1337         dev_info(rdev->dev, "  R_000E50_SRBM_STATUS=0x%08X\n",
1338                 RREG32(R_000E50_SRBM_STATUS));
1339         rv515_mc_resume(rdev, &save);
1340         return 0;
1341 }
1342
1343 bool r600_gpu_is_lockup(struct radeon_device *rdev)
1344 {
1345         u32 srbm_status;
1346         u32 grbm_status;
1347         u32 grbm_status2;
1348         struct r100_gpu_lockup *lockup;
1349         int r;
1350
1351         if (rdev->family >= CHIP_RV770)
1352                 lockup = &rdev->config.rv770.lockup;
1353         else
1354                 lockup = &rdev->config.r600.lockup;
1355
1356         srbm_status = RREG32(R_000E50_SRBM_STATUS);
1357         grbm_status = RREG32(R_008010_GRBM_STATUS);
1358         grbm_status2 = RREG32(R_008014_GRBM_STATUS2);
1359         if (!G_008010_GUI_ACTIVE(grbm_status)) {
1360                 r100_gpu_lockup_update(lockup, &rdev->cp);
1361                 return false;
1362         }
1363         /* force CP activities */
1364         r = radeon_ring_lock(rdev, 2);
1365         if (!r) {
1366                 /* PACKET2 NOP */
1367                 radeon_ring_write(rdev, 0x80000000);
1368                 radeon_ring_write(rdev, 0x80000000);
1369                 radeon_ring_unlock_commit(rdev);
1370         }
1371         rdev->cp.rptr = RREG32(R600_CP_RB_RPTR);
1372         return r100_gpu_cp_is_lockup(rdev, lockup, &rdev->cp);
1373 }
1374
1375 int r600_asic_reset(struct radeon_device *rdev)
1376 {
1377         return r600_gpu_soft_reset(rdev);
1378 }
1379
1380 static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
1381                                              u32 num_backends,
1382                                              u32 backend_disable_mask)
1383 {
1384         u32 backend_map = 0;
1385         u32 enabled_backends_mask;
1386         u32 enabled_backends_count;
1387         u32 cur_pipe;
1388         u32 swizzle_pipe[R6XX_MAX_PIPES];
1389         u32 cur_backend;
1390         u32 i;
1391
1392         if (num_tile_pipes > R6XX_MAX_PIPES)
1393                 num_tile_pipes = R6XX_MAX_PIPES;
1394         if (num_tile_pipes < 1)
1395                 num_tile_pipes = 1;
1396         if (num_backends > R6XX_MAX_BACKENDS)
1397                 num_backends = R6XX_MAX_BACKENDS;
1398         if (num_backends < 1)
1399                 num_backends = 1;
1400
1401         enabled_backends_mask = 0;
1402         enabled_backends_count = 0;
1403         for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
1404                 if (((backend_disable_mask >> i) & 1) == 0) {
1405                         enabled_backends_mask |= (1 << i);
1406                         ++enabled_backends_count;
1407                 }
1408                 if (enabled_backends_count == num_backends)
1409                         break;
1410         }
1411
1412         if (enabled_backends_count == 0) {
1413                 enabled_backends_mask = 1;
1414                 enabled_backends_count = 1;
1415         }
1416
1417         if (enabled_backends_count != num_backends)
1418                 num_backends = enabled_backends_count;
1419
1420         memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
1421         switch (num_tile_pipes) {
1422         case 1:
1423                 swizzle_pipe[0] = 0;
1424                 break;
1425         case 2:
1426                 swizzle_pipe[0] = 0;
1427                 swizzle_pipe[1] = 1;
1428                 break;
1429         case 3:
1430                 swizzle_pipe[0] = 0;
1431                 swizzle_pipe[1] = 1;
1432                 swizzle_pipe[2] = 2;
1433                 break;
1434         case 4:
1435                 swizzle_pipe[0] = 0;
1436                 swizzle_pipe[1] = 1;
1437                 swizzle_pipe[2] = 2;
1438                 swizzle_pipe[3] = 3;
1439                 break;
1440         case 5:
1441                 swizzle_pipe[0] = 0;
1442                 swizzle_pipe[1] = 1;
1443                 swizzle_pipe[2] = 2;
1444                 swizzle_pipe[3] = 3;
1445                 swizzle_pipe[4] = 4;
1446                 break;
1447         case 6:
1448                 swizzle_pipe[0] = 0;
1449                 swizzle_pipe[1] = 2;
1450                 swizzle_pipe[2] = 4;
1451                 swizzle_pipe[3] = 5;
1452                 swizzle_pipe[4] = 1;
1453                 swizzle_pipe[5] = 3;
1454                 break;
1455         case 7:
1456                 swizzle_pipe[0] = 0;
1457                 swizzle_pipe[1] = 2;
1458                 swizzle_pipe[2] = 4;
1459                 swizzle_pipe[3] = 6;
1460                 swizzle_pipe[4] = 1;
1461                 swizzle_pipe[5] = 3;
1462                 swizzle_pipe[6] = 5;
1463                 break;
1464         case 8:
1465                 swizzle_pipe[0] = 0;
1466                 swizzle_pipe[1] = 2;
1467                 swizzle_pipe[2] = 4;
1468                 swizzle_pipe[3] = 6;
1469                 swizzle_pipe[4] = 1;
1470                 swizzle_pipe[5] = 3;
1471                 swizzle_pipe[6] = 5;
1472                 swizzle_pipe[7] = 7;
1473                 break;
1474         }
1475
1476         cur_backend = 0;
1477         for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1478                 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1479                         cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
1480
1481                 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
1482
1483                 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
1484         }
1485
1486         return backend_map;
1487 }
1488
1489 int r600_count_pipe_bits(uint32_t val)
1490 {
1491         int i, ret = 0;
1492
1493         for (i = 0; i < 32; i++) {
1494                 ret += val & 1;
1495                 val >>= 1;
1496         }
1497         return ret;
1498 }
1499
1500 void r600_gpu_init(struct radeon_device *rdev)
1501 {
1502         u32 tiling_config;
1503         u32 ramcfg;
1504         u32 backend_map;
1505         u32 cc_rb_backend_disable;
1506         u32 cc_gc_shader_pipe_config;
1507         u32 tmp;
1508         int i, j;
1509         u32 sq_config;
1510         u32 sq_gpr_resource_mgmt_1 = 0;
1511         u32 sq_gpr_resource_mgmt_2 = 0;
1512         u32 sq_thread_resource_mgmt = 0;
1513         u32 sq_stack_resource_mgmt_1 = 0;
1514         u32 sq_stack_resource_mgmt_2 = 0;
1515
1516         /* FIXME: implement */
1517         switch (rdev->family) {
1518         case CHIP_R600:
1519                 rdev->config.r600.max_pipes = 4;
1520                 rdev->config.r600.max_tile_pipes = 8;
1521                 rdev->config.r600.max_simds = 4;
1522                 rdev->config.r600.max_backends = 4;
1523                 rdev->config.r600.max_gprs = 256;
1524                 rdev->config.r600.max_threads = 192;
1525                 rdev->config.r600.max_stack_entries = 256;
1526                 rdev->config.r600.max_hw_contexts = 8;
1527                 rdev->config.r600.max_gs_threads = 16;
1528                 rdev->config.r600.sx_max_export_size = 128;
1529                 rdev->config.r600.sx_max_export_pos_size = 16;
1530                 rdev->config.r600.sx_max_export_smx_size = 128;
1531                 rdev->config.r600.sq_num_cf_insts = 2;
1532                 break;
1533         case CHIP_RV630:
1534         case CHIP_RV635:
1535                 rdev->config.r600.max_pipes = 2;
1536                 rdev->config.r600.max_tile_pipes = 2;
1537                 rdev->config.r600.max_simds = 3;
1538                 rdev->config.r600.max_backends = 1;
1539                 rdev->config.r600.max_gprs = 128;
1540                 rdev->config.r600.max_threads = 192;
1541                 rdev->config.r600.max_stack_entries = 128;
1542                 rdev->config.r600.max_hw_contexts = 8;
1543                 rdev->config.r600.max_gs_threads = 4;
1544                 rdev->config.r600.sx_max_export_size = 128;
1545                 rdev->config.r600.sx_max_export_pos_size = 16;
1546                 rdev->config.r600.sx_max_export_smx_size = 128;
1547                 rdev->config.r600.sq_num_cf_insts = 2;
1548                 break;
1549         case CHIP_RV610:
1550         case CHIP_RV620:
1551         case CHIP_RS780:
1552         case CHIP_RS880:
1553                 rdev->config.r600.max_pipes = 1;
1554                 rdev->config.r600.max_tile_pipes = 1;
1555                 rdev->config.r600.max_simds = 2;
1556                 rdev->config.r600.max_backends = 1;
1557                 rdev->config.r600.max_gprs = 128;
1558                 rdev->config.r600.max_threads = 192;
1559                 rdev->config.r600.max_stack_entries = 128;
1560                 rdev->config.r600.max_hw_contexts = 4;
1561                 rdev->config.r600.max_gs_threads = 4;
1562                 rdev->config.r600.sx_max_export_size = 128;
1563                 rdev->config.r600.sx_max_export_pos_size = 16;
1564                 rdev->config.r600.sx_max_export_smx_size = 128;
1565                 rdev->config.r600.sq_num_cf_insts = 1;
1566                 break;
1567         case CHIP_RV670:
1568                 rdev->config.r600.max_pipes = 4;
1569                 rdev->config.r600.max_tile_pipes = 4;
1570                 rdev->config.r600.max_simds = 4;
1571                 rdev->config.r600.max_backends = 4;
1572                 rdev->config.r600.max_gprs = 192;
1573                 rdev->config.r600.max_threads = 192;
1574                 rdev->config.r600.max_stack_entries = 256;
1575                 rdev->config.r600.max_hw_contexts = 8;
1576                 rdev->config.r600.max_gs_threads = 16;
1577                 rdev->config.r600.sx_max_export_size = 128;
1578                 rdev->config.r600.sx_max_export_pos_size = 16;
1579                 rdev->config.r600.sx_max_export_smx_size = 128;
1580                 rdev->config.r600.sq_num_cf_insts = 2;
1581                 break;
1582         default:
1583                 break;
1584         }
1585
1586         /* Initialize HDP */
1587         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1588                 WREG32((0x2c14 + j), 0x00000000);
1589                 WREG32((0x2c18 + j), 0x00000000);
1590                 WREG32((0x2c1c + j), 0x00000000);
1591                 WREG32((0x2c20 + j), 0x00000000);
1592                 WREG32((0x2c24 + j), 0x00000000);
1593         }
1594
1595         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1596
1597         /* Setup tiling */
1598         tiling_config = 0;
1599         ramcfg = RREG32(RAMCFG);
1600         switch (rdev->config.r600.max_tile_pipes) {
1601         case 1:
1602                 tiling_config |= PIPE_TILING(0);
1603                 break;
1604         case 2:
1605                 tiling_config |= PIPE_TILING(1);
1606                 break;
1607         case 4:
1608                 tiling_config |= PIPE_TILING(2);
1609                 break;
1610         case 8:
1611                 tiling_config |= PIPE_TILING(3);
1612                 break;
1613         default:
1614                 break;
1615         }
1616         rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes;
1617         rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1618         tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1619         tiling_config |= GROUP_SIZE((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
1620         if ((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT)
1621                 rdev->config.r600.tiling_group_size = 512;
1622         else
1623                 rdev->config.r600.tiling_group_size = 256;
1624         tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
1625         if (tmp > 3) {
1626                 tiling_config |= ROW_TILING(3);
1627                 tiling_config |= SAMPLE_SPLIT(3);
1628         } else {
1629                 tiling_config |= ROW_TILING(tmp);
1630                 tiling_config |= SAMPLE_SPLIT(tmp);
1631         }
1632         tiling_config |= BANK_SWAPS(1);
1633
1634         cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
1635         cc_rb_backend_disable |=
1636                 BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK);
1637
1638         cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
1639         cc_gc_shader_pipe_config |=
1640                 INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK);
1641         cc_gc_shader_pipe_config |=
1642                 INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK);
1643
1644         backend_map = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes,
1645                                                         (R6XX_MAX_BACKENDS -
1646                                                          r600_count_pipe_bits((cc_rb_backend_disable &
1647                                                                                R6XX_MAX_BACKENDS_MASK) >> 16)),
1648                                                         (cc_rb_backend_disable >> 16));
1649         rdev->config.r600.tile_config = tiling_config;
1650         tiling_config |= BACKEND_MAP(backend_map);
1651         WREG32(GB_TILING_CONFIG, tiling_config);
1652         WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
1653         WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
1654
1655         /* Setup pipes */
1656         WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1657         WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1658         WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1659
1660         tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
1661         WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
1662         WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
1663
1664         /* Setup some CP states */
1665         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
1666         WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
1667
1668         WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
1669                              SYNC_WALKER | SYNC_ALIGNER));
1670         /* Setup various GPU states */
1671         if (rdev->family == CHIP_RV670)
1672                 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
1673
1674         tmp = RREG32(SX_DEBUG_1);
1675         tmp |= SMX_EVENT_RELEASE;
1676         if ((rdev->family > CHIP_R600))
1677                 tmp |= ENABLE_NEW_SMX_ADDRESS;
1678         WREG32(SX_DEBUG_1, tmp);
1679
1680         if (((rdev->family) == CHIP_R600) ||
1681             ((rdev->family) == CHIP_RV630) ||
1682             ((rdev->family) == CHIP_RV610) ||
1683             ((rdev->family) == CHIP_RV620) ||
1684             ((rdev->family) == CHIP_RS780) ||
1685             ((rdev->family) == CHIP_RS880)) {
1686                 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
1687         } else {
1688                 WREG32(DB_DEBUG, 0);
1689         }
1690         WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
1691                                DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
1692
1693         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1694         WREG32(VGT_NUM_INSTANCES, 0);
1695
1696         WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
1697         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
1698
1699         tmp = RREG32(SQ_MS_FIFO_SIZES);
1700         if (((rdev->family) == CHIP_RV610) ||
1701             ((rdev->family) == CHIP_RV620) ||
1702             ((rdev->family) == CHIP_RS780) ||
1703             ((rdev->family) == CHIP_RS880)) {
1704                 tmp = (CACHE_FIFO_SIZE(0xa) |
1705                        FETCH_FIFO_HIWATER(0xa) |
1706                        DONE_FIFO_HIWATER(0xe0) |
1707                        ALU_UPDATE_FIFO_HIWATER(0x8));
1708         } else if (((rdev->family) == CHIP_R600) ||
1709                    ((rdev->family) == CHIP_RV630)) {
1710                 tmp &= ~DONE_FIFO_HIWATER(0xff);
1711                 tmp |= DONE_FIFO_HIWATER(0x4);
1712         }
1713         WREG32(SQ_MS_FIFO_SIZES, tmp);
1714
1715         /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1716          * should be adjusted as needed by the 2D/3D drivers.  This just sets default values
1717          */
1718         sq_config = RREG32(SQ_CONFIG);
1719         sq_config &= ~(PS_PRIO(3) |
1720                        VS_PRIO(3) |
1721                        GS_PRIO(3) |
1722                        ES_PRIO(3));
1723         sq_config |= (DX9_CONSTS |
1724                       VC_ENABLE |
1725                       PS_PRIO(0) |
1726                       VS_PRIO(1) |
1727                       GS_PRIO(2) |
1728                       ES_PRIO(3));
1729
1730         if ((rdev->family) == CHIP_R600) {
1731                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
1732                                           NUM_VS_GPRS(124) |
1733                                           NUM_CLAUSE_TEMP_GPRS(4));
1734                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
1735                                           NUM_ES_GPRS(0));
1736                 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
1737                                            NUM_VS_THREADS(48) |
1738                                            NUM_GS_THREADS(4) |
1739                                            NUM_ES_THREADS(4));
1740                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
1741                                             NUM_VS_STACK_ENTRIES(128));
1742                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
1743                                             NUM_ES_STACK_ENTRIES(0));
1744         } else if (((rdev->family) == CHIP_RV610) ||
1745                    ((rdev->family) == CHIP_RV620) ||
1746                    ((rdev->family) == CHIP_RS780) ||
1747                    ((rdev->family) == CHIP_RS880)) {
1748                 /* no vertex cache */
1749                 sq_config &= ~VC_ENABLE;
1750
1751                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1752                                           NUM_VS_GPRS(44) |
1753                                           NUM_CLAUSE_TEMP_GPRS(2));
1754                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1755                                           NUM_ES_GPRS(17));
1756                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1757                                            NUM_VS_THREADS(78) |
1758                                            NUM_GS_THREADS(4) |
1759                                            NUM_ES_THREADS(31));
1760                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1761                                             NUM_VS_STACK_ENTRIES(40));
1762                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1763                                             NUM_ES_STACK_ENTRIES(16));
1764         } else if (((rdev->family) == CHIP_RV630) ||
1765                    ((rdev->family) == CHIP_RV635)) {
1766                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1767                                           NUM_VS_GPRS(44) |
1768                                           NUM_CLAUSE_TEMP_GPRS(2));
1769                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
1770                                           NUM_ES_GPRS(18));
1771                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1772                                            NUM_VS_THREADS(78) |
1773                                            NUM_GS_THREADS(4) |
1774                                            NUM_ES_THREADS(31));
1775                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1776                                             NUM_VS_STACK_ENTRIES(40));
1777                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1778                                             NUM_ES_STACK_ENTRIES(16));
1779         } else if ((rdev->family) == CHIP_RV670) {
1780                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1781                                           NUM_VS_GPRS(44) |
1782                                           NUM_CLAUSE_TEMP_GPRS(2));
1783                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1784                                           NUM_ES_GPRS(17));
1785                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1786                                            NUM_VS_THREADS(78) |
1787                                            NUM_GS_THREADS(4) |
1788                                            NUM_ES_THREADS(31));
1789                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
1790                                             NUM_VS_STACK_ENTRIES(64));
1791                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
1792                                             NUM_ES_STACK_ENTRIES(64));
1793         }
1794
1795         WREG32(SQ_CONFIG, sq_config);
1796         WREG32(SQ_GPR_RESOURCE_MGMT_1,  sq_gpr_resource_mgmt_1);
1797         WREG32(SQ_GPR_RESOURCE_MGMT_2,  sq_gpr_resource_mgmt_2);
1798         WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1799         WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1800         WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1801
1802         if (((rdev->family) == CHIP_RV610) ||
1803             ((rdev->family) == CHIP_RV620) ||
1804             ((rdev->family) == CHIP_RS780) ||
1805             ((rdev->family) == CHIP_RS880)) {
1806                 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
1807         } else {
1808                 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
1809         }
1810
1811         /* More default values. 2D/3D driver should adjust as needed */
1812         WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
1813                                          S1_X(0x4) | S1_Y(0xc)));
1814         WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
1815                                          S1_X(0x2) | S1_Y(0x2) |
1816                                          S2_X(0xa) | S2_Y(0x6) |
1817                                          S3_X(0x6) | S3_Y(0xa)));
1818         WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
1819                                              S1_X(0x4) | S1_Y(0xc) |
1820                                              S2_X(0x1) | S2_Y(0x6) |
1821                                              S3_X(0xa) | S3_Y(0xe)));
1822         WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
1823                                              S5_X(0x0) | S5_Y(0x0) |
1824                                              S6_X(0xb) | S6_Y(0x4) |
1825                                              S7_X(0x7) | S7_Y(0x8)));
1826
1827         WREG32(VGT_STRMOUT_EN, 0);
1828         tmp = rdev->config.r600.max_pipes * 16;
1829         switch (rdev->family) {
1830         case CHIP_RV610:
1831         case CHIP_RV620:
1832         case CHIP_RS780:
1833         case CHIP_RS880:
1834                 tmp += 32;
1835                 break;
1836         case CHIP_RV670:
1837                 tmp += 128;
1838                 break;
1839         default:
1840                 break;
1841         }
1842         if (tmp > 256) {
1843                 tmp = 256;
1844         }
1845         WREG32(VGT_ES_PER_GS, 128);
1846         WREG32(VGT_GS_PER_ES, tmp);
1847         WREG32(VGT_GS_PER_VS, 2);
1848         WREG32(VGT_GS_VERTEX_REUSE, 16);
1849
1850         /* more default values. 2D/3D driver should adjust as needed */
1851         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1852         WREG32(VGT_STRMOUT_EN, 0);
1853         WREG32(SX_MISC, 0);
1854         WREG32(PA_SC_MODE_CNTL, 0);
1855         WREG32(PA_SC_AA_CONFIG, 0);
1856         WREG32(PA_SC_LINE_STIPPLE, 0);
1857         WREG32(SPI_INPUT_Z, 0);
1858         WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
1859         WREG32(CB_COLOR7_FRAG, 0);
1860
1861         /* Clear render buffer base addresses */
1862         WREG32(CB_COLOR0_BASE, 0);
1863         WREG32(CB_COLOR1_BASE, 0);
1864         WREG32(CB_COLOR2_BASE, 0);
1865         WREG32(CB_COLOR3_BASE, 0);
1866         WREG32(CB_COLOR4_BASE, 0);
1867         WREG32(CB_COLOR5_BASE, 0);
1868         WREG32(CB_COLOR6_BASE, 0);
1869         WREG32(CB_COLOR7_BASE, 0);
1870         WREG32(CB_COLOR7_FRAG, 0);
1871
1872         switch (rdev->family) {
1873         case CHIP_RV610:
1874         case CHIP_RV620:
1875         case CHIP_RS780:
1876         case CHIP_RS880:
1877                 tmp = TC_L2_SIZE(8);
1878                 break;
1879         case CHIP_RV630:
1880         case CHIP_RV635:
1881                 tmp = TC_L2_SIZE(4);
1882                 break;
1883         case CHIP_R600:
1884                 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
1885                 break;
1886         default:
1887                 tmp = TC_L2_SIZE(0);
1888                 break;
1889         }
1890         WREG32(TC_CNTL, tmp);
1891
1892         tmp = RREG32(HDP_HOST_PATH_CNTL);
1893         WREG32(HDP_HOST_PATH_CNTL, tmp);
1894
1895         tmp = RREG32(ARB_POP);
1896         tmp |= ENABLE_TC128;
1897         WREG32(ARB_POP, tmp);
1898
1899         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1900         WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
1901                                NUM_CLIP_SEQ(3)));
1902         WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
1903 }
1904
1905
1906 /*
1907  * Indirect registers accessor
1908  */
1909 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
1910 {
1911         u32 r;
1912
1913         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1914         (void)RREG32(PCIE_PORT_INDEX);
1915         r = RREG32(PCIE_PORT_DATA);
1916         return r;
1917 }
1918
1919 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1920 {
1921         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1922         (void)RREG32(PCIE_PORT_INDEX);
1923         WREG32(PCIE_PORT_DATA, (v));
1924         (void)RREG32(PCIE_PORT_DATA);
1925 }
1926
1927 /*
1928  * CP & Ring
1929  */
1930 void r600_cp_stop(struct radeon_device *rdev)
1931 {
1932         rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
1933         WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1934         WREG32(SCRATCH_UMSK, 0);
1935 }
1936
1937 int r600_init_microcode(struct radeon_device *rdev)
1938 {
1939         struct platform_device *pdev;
1940         const char *chip_name;
1941         const char *rlc_chip_name;
1942         size_t pfp_req_size, me_req_size, rlc_req_size;
1943         char fw_name[30];
1944         int err;
1945
1946         DRM_DEBUG("\n");
1947
1948         pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
1949         err = IS_ERR(pdev);
1950         if (err) {
1951                 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
1952                 return -EINVAL;
1953         }
1954
1955         switch (rdev->family) {
1956         case CHIP_R600:
1957                 chip_name = "R600";
1958                 rlc_chip_name = "R600";
1959                 break;
1960         case CHIP_RV610:
1961                 chip_name = "RV610";
1962                 rlc_chip_name = "R600";
1963                 break;
1964         case CHIP_RV630:
1965                 chip_name = "RV630";
1966                 rlc_chip_name = "R600";
1967                 break;
1968         case CHIP_RV620:
1969                 chip_name = "RV620";
1970                 rlc_chip_name = "R600";
1971                 break;
1972         case CHIP_RV635:
1973                 chip_name = "RV635";
1974                 rlc_chip_name = "R600";
1975                 break;
1976         case CHIP_RV670:
1977                 chip_name = "RV670";
1978                 rlc_chip_name = "R600";
1979                 break;
1980         case CHIP_RS780:
1981         case CHIP_RS880:
1982                 chip_name = "RS780";
1983                 rlc_chip_name = "R600";
1984                 break;
1985         case CHIP_RV770:
1986                 chip_name = "RV770";
1987                 rlc_chip_name = "R700";
1988                 break;
1989         case CHIP_RV730:
1990         case CHIP_RV740:
1991                 chip_name = "RV730";
1992                 rlc_chip_name = "R700";
1993                 break;
1994         case CHIP_RV710:
1995                 chip_name = "RV710";
1996                 rlc_chip_name = "R700";
1997                 break;
1998         case CHIP_CEDAR:
1999                 chip_name = "CEDAR";
2000                 rlc_chip_name = "CEDAR";
2001                 break;
2002         case CHIP_REDWOOD:
2003                 chip_name = "REDWOOD";
2004                 rlc_chip_name = "REDWOOD";
2005                 break;
2006         case CHIP_JUNIPER:
2007                 chip_name = "JUNIPER";
2008                 rlc_chip_name = "JUNIPER";
2009                 break;
2010         case CHIP_CYPRESS:
2011         case CHIP_HEMLOCK:
2012                 chip_name = "CYPRESS";
2013                 rlc_chip_name = "CYPRESS";
2014                 break;
2015         case CHIP_PALM:
2016                 chip_name = "PALM";
2017                 rlc_chip_name = "SUMO";
2018                 break;
2019         default: BUG();
2020         }
2021
2022         if (rdev->family >= CHIP_CEDAR) {
2023                 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
2024                 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
2025                 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
2026         } else if (rdev->family >= CHIP_RV770) {
2027                 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
2028                 me_req_size = R700_PM4_UCODE_SIZE * 4;
2029                 rlc_req_size = R700_RLC_UCODE_SIZE * 4;
2030         } else {
2031                 pfp_req_size = PFP_UCODE_SIZE * 4;
2032                 me_req_size = PM4_UCODE_SIZE * 12;
2033                 rlc_req_size = RLC_UCODE_SIZE * 4;
2034         }
2035
2036         DRM_INFO("Loading %s Microcode\n", chip_name);
2037
2038         snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
2039         err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
2040         if (err)
2041                 goto out;
2042         if (rdev->pfp_fw->size != pfp_req_size) {
2043                 printk(KERN_ERR
2044                        "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2045                        rdev->pfp_fw->size, fw_name);
2046                 err = -EINVAL;
2047                 goto out;
2048         }
2049
2050         snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
2051         err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
2052         if (err)
2053                 goto out;
2054         if (rdev->me_fw->size != me_req_size) {
2055                 printk(KERN_ERR
2056                        "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2057                        rdev->me_fw->size, fw_name);
2058                 err = -EINVAL;
2059         }
2060
2061         snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
2062         err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
2063         if (err)
2064                 goto out;
2065         if (rdev->rlc_fw->size != rlc_req_size) {
2066                 printk(KERN_ERR
2067                        "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
2068                        rdev->rlc_fw->size, fw_name);
2069                 err = -EINVAL;
2070         }
2071
2072 out:
2073         platform_device_unregister(pdev);
2074
2075         if (err) {
2076                 if (err != -EINVAL)
2077                         printk(KERN_ERR
2078                                "r600_cp: Failed to load firmware \"%s\"\n",
2079                                fw_name);
2080                 release_firmware(rdev->pfp_fw);
2081                 rdev->pfp_fw = NULL;
2082                 release_firmware(rdev->me_fw);
2083                 rdev->me_fw = NULL;
2084                 release_firmware(rdev->rlc_fw);
2085                 rdev->rlc_fw = NULL;
2086         }
2087         return err;
2088 }
2089
2090 static int r600_cp_load_microcode(struct radeon_device *rdev)
2091 {
2092         const __be32 *fw_data;
2093         int i;
2094
2095         if (!rdev->me_fw || !rdev->pfp_fw)
2096                 return -EINVAL;
2097
2098         r600_cp_stop(rdev);
2099
2100         WREG32(CP_RB_CNTL, RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
2101
2102         /* Reset cp */
2103         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2104         RREG32(GRBM_SOFT_RESET);
2105         mdelay(15);
2106         WREG32(GRBM_SOFT_RESET, 0);
2107
2108         WREG32(CP_ME_RAM_WADDR, 0);
2109
2110         fw_data = (const __be32 *)rdev->me_fw->data;
2111         WREG32(CP_ME_RAM_WADDR, 0);
2112         for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
2113                 WREG32(CP_ME_RAM_DATA,
2114                        be32_to_cpup(fw_data++));
2115
2116         fw_data = (const __be32 *)rdev->pfp_fw->data;
2117         WREG32(CP_PFP_UCODE_ADDR, 0);
2118         for (i = 0; i < PFP_UCODE_SIZE; i++)
2119                 WREG32(CP_PFP_UCODE_DATA,
2120                        be32_to_cpup(fw_data++));
2121
2122         WREG32(CP_PFP_UCODE_ADDR, 0);
2123         WREG32(CP_ME_RAM_WADDR, 0);
2124         WREG32(CP_ME_RAM_RADDR, 0);
2125         return 0;
2126 }
2127
2128 int r600_cp_start(struct radeon_device *rdev)
2129 {
2130         int r;
2131         uint32_t cp_me;
2132
2133         r = radeon_ring_lock(rdev, 7);
2134         if (r) {
2135                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2136                 return r;
2137         }
2138         radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
2139         radeon_ring_write(rdev, 0x1);
2140         if (rdev->family >= CHIP_RV770) {
2141                 radeon_ring_write(rdev, 0x0);
2142                 radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1);
2143         } else {
2144                 radeon_ring_write(rdev, 0x3);
2145                 radeon_ring_write(rdev, rdev->config.r600.max_hw_contexts - 1);
2146         }
2147         radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2148         radeon_ring_write(rdev, 0);
2149         radeon_ring_write(rdev, 0);
2150         radeon_ring_unlock_commit(rdev);
2151
2152         cp_me = 0xff;
2153         WREG32(R_0086D8_CP_ME_CNTL, cp_me);
2154         return 0;
2155 }
2156
2157 int r600_cp_resume(struct radeon_device *rdev)
2158 {
2159         u32 tmp;
2160         u32 rb_bufsz;
2161         int r;
2162
2163         /* Reset cp */
2164         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2165         RREG32(GRBM_SOFT_RESET);
2166         mdelay(15);
2167         WREG32(GRBM_SOFT_RESET, 0);
2168
2169         /* Set ring buffer size */
2170         rb_bufsz = drm_order(rdev->cp.ring_size / 8);
2171         tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2172 #ifdef __BIG_ENDIAN
2173         tmp |= BUF_SWAP_32BIT;
2174 #endif
2175         WREG32(CP_RB_CNTL, tmp);
2176         WREG32(CP_SEM_WAIT_TIMER, 0x4);
2177
2178         /* Set the write pointer delay */
2179         WREG32(CP_RB_WPTR_DELAY, 0);
2180
2181         /* Initialize the ring buffer's read and write pointers */
2182         WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
2183         WREG32(CP_RB_RPTR_WR, 0);
2184         WREG32(CP_RB_WPTR, 0);
2185
2186         /* set the wb address whether it's enabled or not */
2187         WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);
2188         WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
2189         WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
2190
2191         if (rdev->wb.enabled)
2192                 WREG32(SCRATCH_UMSK, 0xff);
2193         else {
2194                 tmp |= RB_NO_UPDATE;
2195                 WREG32(SCRATCH_UMSK, 0);
2196         }
2197
2198         mdelay(1);
2199         WREG32(CP_RB_CNTL, tmp);
2200
2201         WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
2202         WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
2203
2204         rdev->cp.rptr = RREG32(CP_RB_RPTR);
2205         rdev->cp.wptr = RREG32(CP_RB_WPTR);
2206
2207         r600_cp_start(rdev);
2208         rdev->cp.ready = true;
2209         r = radeon_ring_test(rdev);
2210         if (r) {
2211                 rdev->cp.ready = false;
2212                 return r;
2213         }
2214         return 0;
2215 }
2216
2217 void r600_cp_commit(struct radeon_device *rdev)
2218 {
2219         WREG32(CP_RB_WPTR, rdev->cp.wptr);
2220         (void)RREG32(CP_RB_WPTR);
2221 }
2222
2223 void r600_ring_init(struct radeon_device *rdev, unsigned ring_size)
2224 {
2225         u32 rb_bufsz;
2226
2227         /* Align ring size */
2228         rb_bufsz = drm_order(ring_size / 8);
2229         ring_size = (1 << (rb_bufsz + 1)) * 4;
2230         rdev->cp.ring_size = ring_size;
2231         rdev->cp.align_mask = 16 - 1;
2232 }
2233
2234 void r600_cp_fini(struct radeon_device *rdev)
2235 {
2236         r600_cp_stop(rdev);
2237         radeon_ring_fini(rdev);
2238 }
2239
2240
2241 /*
2242  * GPU scratch registers helpers function.
2243  */
2244 void r600_scratch_init(struct radeon_device *rdev)
2245 {
2246         int i;
2247
2248         rdev->scratch.num_reg = 7;
2249         rdev->scratch.reg_base = SCRATCH_REG0;
2250         for (i = 0; i < rdev->scratch.num_reg; i++) {
2251                 rdev->scratch.free[i] = true;
2252                 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
2253         }
2254 }
2255
2256 int r600_ring_test(struct radeon_device *rdev)
2257 {
2258         uint32_t scratch;
2259         uint32_t tmp = 0;
2260         unsigned i;
2261         int r;
2262
2263         r = radeon_scratch_get(rdev, &scratch);
2264         if (r) {
2265                 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
2266                 return r;
2267         }
2268         WREG32(scratch, 0xCAFEDEAD);
2269         r = radeon_ring_lock(rdev, 3);
2270         if (r) {
2271                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2272                 radeon_scratch_free(rdev, scratch);
2273                 return r;
2274         }
2275         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2276         radeon_ring_write(rdev, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2277         radeon_ring_write(rdev, 0xDEADBEEF);
2278         radeon_ring_unlock_commit(rdev);
2279         for (i = 0; i < rdev->usec_timeout; i++) {
2280                 tmp = RREG32(scratch);
2281                 if (tmp == 0xDEADBEEF)
2282                         break;
2283                 DRM_UDELAY(1);
2284         }
2285         if (i < rdev->usec_timeout) {
2286                 DRM_INFO("ring test succeeded in %d usecs\n", i);
2287         } else {
2288                 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
2289                           scratch, tmp);
2290                 r = -EINVAL;
2291         }
2292         radeon_scratch_free(rdev, scratch);
2293         return r;
2294 }
2295
2296 void r600_fence_ring_emit(struct radeon_device *rdev,
2297                           struct radeon_fence *fence)
2298 {
2299         if (rdev->wb.use_event) {
2300                 u64 addr = rdev->wb.gpu_addr + R600_WB_EVENT_OFFSET +
2301                         (u64)(rdev->fence_drv.scratch_reg - rdev->scratch.reg_base);
2302                 /* EVENT_WRITE_EOP - flush caches, send int */
2303                 radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2304                 radeon_ring_write(rdev, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
2305                 radeon_ring_write(rdev, addr & 0xffffffff);
2306                 radeon_ring_write(rdev, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
2307                 radeon_ring_write(rdev, fence->seq);
2308                 radeon_ring_write(rdev, 0);
2309         } else {
2310                 radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0));
2311                 radeon_ring_write(rdev, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0));
2312                 /* wait for 3D idle clean */
2313                 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2314                 radeon_ring_write(rdev, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2315                 radeon_ring_write(rdev, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
2316                 /* Emit fence sequence & fire IRQ */
2317                 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2318                 radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2319                 radeon_ring_write(rdev, fence->seq);
2320                 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
2321                 radeon_ring_write(rdev, PACKET0(CP_INT_STATUS, 0));
2322                 radeon_ring_write(rdev, RB_INT_STAT);
2323         }
2324 }
2325
2326 int r600_copy_blit(struct radeon_device *rdev,
2327                    uint64_t src_offset, uint64_t dst_offset,
2328                    unsigned num_pages, struct radeon_fence *fence)
2329 {
2330         int r;
2331
2332         mutex_lock(&rdev->r600_blit.mutex);
2333         rdev->r600_blit.vb_ib = NULL;
2334         r = r600_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE);
2335         if (r) {
2336                 if (rdev->r600_blit.vb_ib)
2337                         radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
2338                 mutex_unlock(&rdev->r600_blit.mutex);
2339                 return r;
2340         }
2341         r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE);
2342         r600_blit_done_copy(rdev, fence);
2343         mutex_unlock(&rdev->r600_blit.mutex);
2344         return 0;
2345 }
2346
2347 int r600_set_surface_reg(struct radeon_device *rdev, int reg,
2348                          uint32_t tiling_flags, uint32_t pitch,
2349                          uint32_t offset, uint32_t obj_size)
2350 {
2351         /* FIXME: implement */
2352         return 0;
2353 }
2354
2355 void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
2356 {
2357         /* FIXME: implement */
2358 }
2359
2360
2361 bool r600_card_posted(struct radeon_device *rdev)
2362 {
2363         uint32_t reg;
2364
2365         /* first check CRTCs */
2366         reg = RREG32(D1CRTC_CONTROL) |
2367                 RREG32(D2CRTC_CONTROL);
2368         if (reg & CRTC_EN)
2369                 return true;
2370
2371         /* then check MEM_SIZE, in case the crtcs are off */
2372         if (RREG32(CONFIG_MEMSIZE))
2373                 return true;
2374
2375         return false;
2376 }
2377
2378 int r600_startup(struct radeon_device *rdev)
2379 {
2380         int r;
2381
2382         if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
2383                 r = r600_init_microcode(rdev);
2384                 if (r) {
2385                         DRM_ERROR("Failed to load firmware!\n");
2386                         return r;
2387                 }
2388         }
2389
2390         r600_mc_program(rdev);
2391         if (rdev->flags & RADEON_IS_AGP) {
2392                 r600_agp_enable(rdev);
2393         } else {
2394                 r = r600_pcie_gart_enable(rdev);
2395                 if (r)
2396                         return r;
2397         }
2398         r600_gpu_init(rdev);
2399         r = r600_blit_init(rdev);
2400         if (r) {
2401                 r600_blit_fini(rdev);
2402                 rdev->asic->copy = NULL;
2403                 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
2404         }
2405
2406         /* allocate wb buffer */
2407         r = radeon_wb_init(rdev);
2408         if (r)
2409                 return r;
2410
2411         /* Enable IRQ */
2412         r = r600_irq_init(rdev);
2413         if (r) {
2414                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
2415                 radeon_irq_kms_fini(rdev);
2416                 return r;
2417         }
2418         r600_irq_set(rdev);
2419
2420         r = radeon_ring_init(rdev, rdev->cp.ring_size);
2421         if (r)
2422                 return r;
2423         r = r600_cp_load_microcode(rdev);
2424         if (r)
2425                 return r;
2426         r = r600_cp_resume(rdev);
2427         if (r)
2428                 return r;
2429
2430         return 0;
2431 }
2432
2433 void r600_vga_set_state(struct radeon_device *rdev, bool state)
2434 {
2435         uint32_t temp;
2436
2437         temp = RREG32(CONFIG_CNTL);
2438         if (state == false) {
2439                 temp &= ~(1<<0);
2440                 temp |= (1<<1);
2441         } else {
2442                 temp &= ~(1<<1);
2443         }
2444         WREG32(CONFIG_CNTL, temp);
2445 }
2446
2447 int r600_resume(struct radeon_device *rdev)
2448 {
2449         int r;
2450
2451         /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
2452          * posting will perform necessary task to bring back GPU into good
2453          * shape.
2454          */
2455         /* post card */
2456         atom_asic_init(rdev->mode_info.atom_context);
2457
2458         r = r600_startup(rdev);
2459         if (r) {
2460                 DRM_ERROR("r600 startup failed on resume\n");
2461                 return r;
2462         }
2463
2464         r = r600_ib_test(rdev);
2465         if (r) {
2466                 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
2467                 return r;
2468         }
2469
2470         r = r600_audio_init(rdev);
2471         if (r) {
2472                 DRM_ERROR("radeon: audio resume failed\n");
2473                 return r;
2474         }
2475
2476         return r;
2477 }
2478
2479 int r600_suspend(struct radeon_device *rdev)
2480 {
2481         int r;
2482
2483         r600_audio_fini(rdev);
2484         /* FIXME: we should wait for ring to be empty */
2485         r600_cp_stop(rdev);
2486         rdev->cp.ready = false;
2487         r600_irq_suspend(rdev);
2488         radeon_wb_disable(rdev);
2489         r600_pcie_gart_disable(rdev);
2490         /* unpin shaders bo */
2491         if (rdev->r600_blit.shader_obj) {
2492                 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
2493                 if (!r) {
2494                         radeon_bo_unpin(rdev->r600_blit.shader_obj);
2495                         radeon_bo_unreserve(rdev->r600_blit.shader_obj);
2496                 }
2497         }
2498         return 0;
2499 }
2500
2501 /* Plan is to move initialization in that function and use
2502  * helper function so that radeon_device_init pretty much
2503  * do nothing more than calling asic specific function. This
2504  * should also allow to remove a bunch of callback function
2505  * like vram_info.
2506  */
2507 int r600_init(struct radeon_device *rdev)
2508 {
2509         int r;
2510
2511         r = radeon_dummy_page_init(rdev);
2512         if (r)
2513                 return r;
2514         if (r600_debugfs_mc_info_init(rdev)) {
2515                 DRM_ERROR("Failed to register debugfs file for mc !\n");
2516         }
2517         /* This don't do much */
2518         r = radeon_gem_init(rdev);
2519         if (r)
2520                 return r;
2521         /* Read BIOS */
2522         if (!radeon_get_bios(rdev)) {
2523                 if (ASIC_IS_AVIVO(rdev))
2524                         return -EINVAL;
2525         }
2526         /* Must be an ATOMBIOS */
2527         if (!rdev->is_atom_bios) {
2528                 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
2529                 return -EINVAL;
2530         }
2531         r = radeon_atombios_init(rdev);
2532         if (r)
2533                 return r;
2534         /* Post card if necessary */
2535         if (!r600_card_posted(rdev)) {
2536                 if (!rdev->bios) {
2537                         dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2538                         return -EINVAL;
2539                 }
2540                 DRM_INFO("GPU not posted. posting now...\n");
2541                 atom_asic_init(rdev->mode_info.atom_context);
2542         }
2543         /* Initialize scratch registers */
2544         r600_scratch_init(rdev);
2545         /* Initialize surface registers */
2546         radeon_surface_init(rdev);
2547         /* Initialize clocks */
2548         radeon_get_clock_info(rdev->ddev);
2549         /* Fence driver */
2550         r = radeon_fence_driver_init(rdev);
2551         if (r)
2552                 return r;
2553         if (rdev->flags & RADEON_IS_AGP) {
2554                 r = radeon_agp_init(rdev);
2555                 if (r)
2556                         radeon_agp_disable(rdev);
2557         }
2558         r = r600_mc_init(rdev);
2559         if (r)
2560                 return r;
2561         /* Memory manager */
2562         r = radeon_bo_init(rdev);
2563         if (r)
2564                 return r;
2565
2566         r = radeon_irq_kms_init(rdev);
2567         if (r)
2568                 return r;
2569
2570         rdev->cp.ring_obj = NULL;
2571         r600_ring_init(rdev, 1024 * 1024);
2572
2573         rdev->ih.ring_obj = NULL;
2574         r600_ih_ring_init(rdev, 64 * 1024);
2575
2576         r = r600_pcie_gart_init(rdev);
2577         if (r)
2578                 return r;
2579
2580         rdev->accel_working = true;
2581         r = r600_startup(rdev);
2582         if (r) {
2583                 dev_err(rdev->dev, "disabling GPU acceleration\n");
2584                 r600_cp_fini(rdev);
2585                 r600_irq_fini(rdev);
2586                 radeon_wb_fini(rdev);
2587                 radeon_irq_kms_fini(rdev);
2588                 r600_pcie_gart_fini(rdev);
2589                 rdev->accel_working = false;
2590         }
2591         if (rdev->accel_working) {
2592                 r = radeon_ib_pool_init(rdev);
2593                 if (r) {
2594                         dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
2595                         rdev->accel_working = false;
2596                 } else {
2597                         r = r600_ib_test(rdev);
2598                         if (r) {
2599                                 dev_err(rdev->dev, "IB test failed (%d).\n", r);
2600                                 rdev->accel_working = false;
2601                         }
2602                 }
2603         }
2604
2605         r = r600_audio_init(rdev);
2606         if (r)
2607                 return r; /* TODO error handling */
2608         return 0;
2609 }
2610
2611 void r600_fini(struct radeon_device *rdev)
2612 {
2613         r600_audio_fini(rdev);
2614         r600_blit_fini(rdev);
2615         r600_cp_fini(rdev);
2616         r600_irq_fini(rdev);
2617         radeon_wb_fini(rdev);
2618         radeon_irq_kms_fini(rdev);
2619         r600_pcie_gart_fini(rdev);
2620         radeon_agp_fini(rdev);
2621         radeon_gem_fini(rdev);
2622         radeon_fence_driver_fini(rdev);
2623         radeon_bo_fini(rdev);
2624         radeon_atombios_fini(rdev);
2625         kfree(rdev->bios);
2626         rdev->bios = NULL;
2627         radeon_dummy_page_fini(rdev);
2628 }
2629
2630
2631 /*
2632  * CS stuff
2633  */
2634 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
2635 {
2636         /* FIXME: implement */
2637         radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
2638         radeon_ring_write(rdev, ib->gpu_addr & 0xFFFFFFFC);
2639         radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF);
2640         radeon_ring_write(rdev, ib->length_dw);
2641 }
2642
2643 int r600_ib_test(struct radeon_device *rdev)
2644 {
2645         struct radeon_ib *ib;
2646         uint32_t scratch;
2647         uint32_t tmp = 0;
2648         unsigned i;
2649         int r;
2650
2651         r = radeon_scratch_get(rdev, &scratch);
2652         if (r) {
2653                 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
2654                 return r;
2655         }
2656         WREG32(scratch, 0xCAFEDEAD);
2657         r = radeon_ib_get(rdev, &ib);
2658         if (r) {
2659                 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
2660                 return r;
2661         }
2662         ib->ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
2663         ib->ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2664         ib->ptr[2] = 0xDEADBEEF;
2665         ib->ptr[3] = PACKET2(0);
2666         ib->ptr[4] = PACKET2(0);
2667         ib->ptr[5] = PACKET2(0);
2668         ib->ptr[6] = PACKET2(0);
2669         ib->ptr[7] = PACKET2(0);
2670         ib->ptr[8] = PACKET2(0);
2671         ib->ptr[9] = PACKET2(0);
2672         ib->ptr[10] = PACKET2(0);
2673         ib->ptr[11] = PACKET2(0);
2674         ib->ptr[12] = PACKET2(0);
2675         ib->ptr[13] = PACKET2(0);
2676         ib->ptr[14] = PACKET2(0);
2677         ib->ptr[15] = PACKET2(0);
2678         ib->length_dw = 16;
2679         r = radeon_ib_schedule(rdev, ib);
2680         if (r) {
2681                 radeon_scratch_free(rdev, scratch);
2682                 radeon_ib_free(rdev, &ib);
2683                 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
2684                 return r;
2685         }
2686         r = radeon_fence_wait(ib->fence, false);
2687         if (r) {
2688                 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
2689                 return r;
2690         }
2691         for (i = 0; i < rdev->usec_timeout; i++) {
2692                 tmp = RREG32(scratch);
2693                 if (tmp == 0xDEADBEEF)
2694                         break;
2695                 DRM_UDELAY(1);
2696         }
2697         if (i < rdev->usec_timeout) {
2698                 DRM_INFO("ib test succeeded in %u usecs\n", i);
2699         } else {
2700                 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
2701                           scratch, tmp);
2702                 r = -EINVAL;
2703         }
2704         radeon_scratch_free(rdev, scratch);
2705         radeon_ib_free(rdev, &ib);
2706         return r;
2707 }
2708
2709 /*
2710  * Interrupts
2711  *
2712  * Interrupts use a ring buffer on r6xx/r7xx hardware.  It works pretty
2713  * the same as the CP ring buffer, but in reverse.  Rather than the CPU
2714  * writing to the ring and the GPU consuming, the GPU writes to the ring
2715  * and host consumes.  As the host irq handler processes interrupts, it
2716  * increments the rptr.  When the rptr catches up with the wptr, all the
2717  * current interrupts have been processed.
2718  */
2719
2720 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
2721 {
2722         u32 rb_bufsz;
2723
2724         /* Align ring size */
2725         rb_bufsz = drm_order(ring_size / 4);
2726         ring_size = (1 << rb_bufsz) * 4;
2727         rdev->ih.ring_size = ring_size;
2728         rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
2729         rdev->ih.rptr = 0;
2730 }
2731
2732 static int r600_ih_ring_alloc(struct radeon_device *rdev)
2733 {
2734         int r;
2735
2736         /* Allocate ring buffer */
2737         if (rdev->ih.ring_obj == NULL) {
2738                 r = radeon_bo_create(rdev, NULL, rdev->ih.ring_size,
2739                                      PAGE_SIZE, true,
2740                                      RADEON_GEM_DOMAIN_GTT,
2741                                      &rdev->ih.ring_obj);
2742                 if (r) {
2743                         DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
2744                         return r;
2745                 }
2746                 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2747                 if (unlikely(r != 0))
2748                         return r;
2749                 r = radeon_bo_pin(rdev->ih.ring_obj,
2750                                   RADEON_GEM_DOMAIN_GTT,
2751                                   &rdev->ih.gpu_addr);
2752                 if (r) {
2753                         radeon_bo_unreserve(rdev->ih.ring_obj);
2754                         DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
2755                         return r;
2756                 }
2757                 r = radeon_bo_kmap(rdev->ih.ring_obj,
2758                                    (void **)&rdev->ih.ring);
2759                 radeon_bo_unreserve(rdev->ih.ring_obj);
2760                 if (r) {
2761                         DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
2762                         return r;
2763                 }
2764         }
2765         return 0;
2766 }
2767
2768 static void r600_ih_ring_fini(struct radeon_device *rdev)
2769 {
2770         int r;
2771         if (rdev->ih.ring_obj) {
2772                 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2773                 if (likely(r == 0)) {
2774                         radeon_bo_kunmap(rdev->ih.ring_obj);
2775                         radeon_bo_unpin(rdev->ih.ring_obj);
2776                         radeon_bo_unreserve(rdev->ih.ring_obj);
2777                 }
2778                 radeon_bo_unref(&rdev->ih.ring_obj);
2779                 rdev->ih.ring = NULL;
2780                 rdev->ih.ring_obj = NULL;
2781         }
2782 }
2783
2784 void r600_rlc_stop(struct radeon_device *rdev)
2785 {
2786
2787         if ((rdev->family >= CHIP_RV770) &&
2788             (rdev->family <= CHIP_RV740)) {
2789                 /* r7xx asics need to soft reset RLC before halting */
2790                 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
2791                 RREG32(SRBM_SOFT_RESET);
2792                 udelay(15000);
2793                 WREG32(SRBM_SOFT_RESET, 0);
2794                 RREG32(SRBM_SOFT_RESET);
2795         }
2796
2797         WREG32(RLC_CNTL, 0);
2798 }
2799
2800 static void r600_rlc_start(struct radeon_device *rdev)
2801 {
2802         WREG32(RLC_CNTL, RLC_ENABLE);
2803 }
2804
2805 static int r600_rlc_init(struct radeon_device *rdev)
2806 {
2807         u32 i;
2808         const __be32 *fw_data;
2809
2810         if (!rdev->rlc_fw)
2811                 return -EINVAL;
2812
2813         r600_rlc_stop(rdev);
2814
2815         WREG32(RLC_HB_BASE, 0);
2816         WREG32(RLC_HB_CNTL, 0);
2817         WREG32(RLC_HB_RPTR, 0);
2818         WREG32(RLC_HB_WPTR, 0);
2819         WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
2820         WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
2821         WREG32(RLC_MC_CNTL, 0);
2822         WREG32(RLC_UCODE_CNTL, 0);
2823
2824         fw_data = (const __be32 *)rdev->rlc_fw->data;
2825         if (rdev->family >= CHIP_CEDAR) {
2826                 for (i = 0; i < EVERGREEN_RLC_UCODE_SIZE; i++) {
2827                         WREG32(RLC_UCODE_ADDR, i);
2828                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2829                 }
2830         } else if (rdev->family >= CHIP_RV770) {
2831                 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
2832                         WREG32(RLC_UCODE_ADDR, i);
2833                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2834                 }
2835         } else {
2836                 for (i = 0; i < RLC_UCODE_SIZE; i++) {
2837                         WREG32(RLC_UCODE_ADDR, i);
2838                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2839                 }
2840         }
2841         WREG32(RLC_UCODE_ADDR, 0);
2842
2843         r600_rlc_start(rdev);
2844
2845         return 0;
2846 }
2847
2848 static void r600_enable_interrupts(struct radeon_device *rdev)
2849 {
2850         u32 ih_cntl = RREG32(IH_CNTL);
2851         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2852
2853         ih_cntl |= ENABLE_INTR;
2854         ih_rb_cntl |= IH_RB_ENABLE;
2855         WREG32(IH_CNTL, ih_cntl);
2856         WREG32(IH_RB_CNTL, ih_rb_cntl);
2857         rdev->ih.enabled = true;
2858 }
2859
2860 void r600_disable_interrupts(struct radeon_device *rdev)
2861 {
2862         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2863         u32 ih_cntl = RREG32(IH_CNTL);
2864
2865         ih_rb_cntl &= ~IH_RB_ENABLE;
2866         ih_cntl &= ~ENABLE_INTR;
2867         WREG32(IH_RB_CNTL, ih_rb_cntl);
2868         WREG32(IH_CNTL, ih_cntl);
2869         /* set rptr, wptr to 0 */
2870         WREG32(IH_RB_RPTR, 0);
2871         WREG32(IH_RB_WPTR, 0);
2872         rdev->ih.enabled = false;
2873         rdev->ih.wptr = 0;
2874         rdev->ih.rptr = 0;
2875 }
2876
2877 static void r600_disable_interrupt_state(struct radeon_device *rdev)
2878 {
2879         u32 tmp;
2880
2881         WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
2882         WREG32(GRBM_INT_CNTL, 0);
2883         WREG32(DxMODE_INT_MASK, 0);
2884         WREG32(D1GRPH_INTERRUPT_CONTROL, 0);
2885         WREG32(D2GRPH_INTERRUPT_CONTROL, 0);
2886         if (ASIC_IS_DCE3(rdev)) {
2887                 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);
2888                 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);
2889                 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2890                 WREG32(DC_HPD1_INT_CONTROL, tmp);
2891                 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2892                 WREG32(DC_HPD2_INT_CONTROL, tmp);
2893                 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2894                 WREG32(DC_HPD3_INT_CONTROL, tmp);
2895                 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2896                 WREG32(DC_HPD4_INT_CONTROL, tmp);
2897                 if (ASIC_IS_DCE32(rdev)) {
2898                         tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2899                         WREG32(DC_HPD5_INT_CONTROL, tmp);
2900                         tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2901                         WREG32(DC_HPD6_INT_CONTROL, tmp);
2902                 }
2903         } else {
2904                 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2905                 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2906                 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2907                 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
2908                 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2909                 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
2910                 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2911                 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
2912         }
2913 }
2914
2915 int r600_irq_init(struct radeon_device *rdev)
2916 {
2917         int ret = 0;
2918         int rb_bufsz;
2919         u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
2920
2921         /* allocate ring */
2922         ret = r600_ih_ring_alloc(rdev);
2923         if (ret)
2924                 return ret;
2925
2926         /* disable irqs */
2927         r600_disable_interrupts(rdev);
2928
2929         /* init rlc */
2930         ret = r600_rlc_init(rdev);
2931         if (ret) {
2932                 r600_ih_ring_fini(rdev);
2933                 return ret;
2934         }
2935
2936         /* setup interrupt control */
2937         /* set dummy read address to ring address */
2938         WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
2939         interrupt_cntl = RREG32(INTERRUPT_CNTL);
2940         /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
2941          * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
2942          */
2943         interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
2944         /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
2945         interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
2946         WREG32(INTERRUPT_CNTL, interrupt_cntl);
2947
2948         WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
2949         rb_bufsz = drm_order(rdev->ih.ring_size / 4);
2950
2951         ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
2952                       IH_WPTR_OVERFLOW_CLEAR |
2953                       (rb_bufsz << 1));
2954
2955         if (rdev->wb.enabled)
2956                 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;
2957
2958         /* set the writeback address whether it's enabled or not */
2959         WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
2960         WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
2961
2962         WREG32(IH_RB_CNTL, ih_rb_cntl);
2963
2964         /* set rptr, wptr to 0 */
2965         WREG32(IH_RB_RPTR, 0);
2966         WREG32(IH_RB_WPTR, 0);
2967
2968         /* Default settings for IH_CNTL (disabled at first) */
2969         ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
2970         /* RPTR_REARM only works if msi's are enabled */
2971         if (rdev->msi_enabled)
2972                 ih_cntl |= RPTR_REARM;
2973
2974 #ifdef __BIG_ENDIAN
2975         ih_cntl |= IH_MC_SWAP(IH_MC_SWAP_32BIT);
2976 #endif
2977         WREG32(IH_CNTL, ih_cntl);
2978
2979         /* force the active interrupt state to all disabled */
2980         if (rdev->family >= CHIP_CEDAR)
2981                 evergreen_disable_interrupt_state(rdev);
2982         else
2983                 r600_disable_interrupt_state(rdev);
2984
2985         /* enable irqs */
2986         r600_enable_interrupts(rdev);
2987
2988         return ret;
2989 }
2990
2991 void r600_irq_suspend(struct radeon_device *rdev)
2992 {
2993         r600_irq_disable(rdev);
2994         r600_rlc_stop(rdev);
2995 }
2996
2997 void r600_irq_fini(struct radeon_device *rdev)
2998 {
2999         r600_irq_suspend(rdev);
3000         r600_ih_ring_fini(rdev);
3001 }
3002
3003 int r600_irq_set(struct radeon_device *rdev)
3004 {
3005         u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
3006         u32 mode_int = 0;
3007         u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
3008         u32 grbm_int_cntl = 0;
3009         u32 hdmi1, hdmi2;
3010         u32 d1grph = 0, d2grph = 0;
3011
3012         if (!rdev->irq.installed) {
3013                 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
3014                 return -EINVAL;
3015         }
3016         /* don't enable anything if the ih is disabled */
3017         if (!rdev->ih.enabled) {
3018                 r600_disable_interrupts(rdev);
3019                 /* force the active interrupt state to all disabled */
3020                 r600_disable_interrupt_state(rdev);
3021                 return 0;
3022         }
3023
3024         hdmi1 = RREG32(R600_HDMI_BLOCK1 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
3025         if (ASIC_IS_DCE3(rdev)) {
3026                 hdmi2 = RREG32(R600_HDMI_BLOCK3 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
3027                 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3028                 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3029                 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3030                 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
3031                 if (ASIC_IS_DCE32(rdev)) {
3032                         hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
3033                         hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
3034                 }
3035         } else {
3036                 hdmi2 = RREG32(R600_HDMI_BLOCK2 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
3037                 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3038                 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3039                 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3040         }
3041
3042         if (rdev->irq.sw_int) {
3043                 DRM_DEBUG("r600_irq_set: sw int\n");
3044                 cp_int_cntl |= RB_INT_ENABLE;
3045                 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
3046         }
3047         if (rdev->irq.crtc_vblank_int[0] ||
3048             rdev->irq.pflip[0]) {
3049                 DRM_DEBUG("r600_irq_set: vblank 0\n");
3050                 mode_int |= D1MODE_VBLANK_INT_MASK;
3051         }
3052         if (rdev->irq.crtc_vblank_int[1] ||
3053             rdev->irq.pflip[1]) {
3054                 DRM_DEBUG("r600_irq_set: vblank 1\n");
3055                 mode_int |= D2MODE_VBLANK_INT_MASK;
3056         }
3057         if (rdev->irq.hpd[0]) {
3058                 DRM_DEBUG("r600_irq_set: hpd 1\n");
3059                 hpd1 |= DC_HPDx_INT_EN;
3060         }
3061         if (rdev->irq.hpd[1]) {
3062                 DRM_DEBUG("r600_irq_set: hpd 2\n");
3063                 hpd2 |= DC_HPDx_INT_EN;
3064         }
3065         if (rdev->irq.hpd[2]) {
3066                 DRM_DEBUG("r600_irq_set: hpd 3\n");
3067                 hpd3 |= DC_HPDx_INT_EN;
3068         }
3069         if (rdev->irq.hpd[3]) {
3070                 DRM_DEBUG("r600_irq_set: hpd 4\n");
3071                 hpd4 |= DC_HPDx_INT_EN;
3072         }
3073         if (rdev->irq.hpd[4]) {
3074                 DRM_DEBUG("r600_irq_set: hpd 5\n");
3075                 hpd5 |= DC_HPDx_INT_EN;
3076         }
3077         if (rdev->irq.hpd[5]) {
3078                 DRM_DEBUG("r600_irq_set: hpd 6\n");
3079                 hpd6 |= DC_HPDx_INT_EN;
3080         }
3081         if (rdev->irq.hdmi[0]) {
3082                 DRM_DEBUG("r600_irq_set: hdmi 1\n");
3083                 hdmi1 |= R600_HDMI_INT_EN;
3084         }
3085         if (rdev->irq.hdmi[1]) {
3086                 DRM_DEBUG("r600_irq_set: hdmi 2\n");
3087                 hdmi2 |= R600_HDMI_INT_EN;
3088         }
3089         if (rdev->irq.gui_idle) {
3090                 DRM_DEBUG("gui idle\n");
3091                 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
3092         }
3093
3094         WREG32(CP_INT_CNTL, cp_int_cntl);
3095         WREG32(DxMODE_INT_MASK, mode_int);
3096         WREG32(D1GRPH_INTERRUPT_CONTROL, d1grph);
3097         WREG32(D2GRPH_INTERRUPT_CONTROL, d2grph);
3098         WREG32(GRBM_INT_CNTL, grbm_int_cntl);
3099         WREG32(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, hdmi1);
3100         if (ASIC_IS_DCE3(rdev)) {
3101                 WREG32(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, hdmi2);
3102                 WREG32(DC_HPD1_INT_CONTROL, hpd1);
3103                 WREG32(DC_HPD2_INT_CONTROL, hpd2);
3104                 WREG32(DC_HPD3_INT_CONTROL, hpd3);
3105                 WREG32(DC_HPD4_INT_CONTROL, hpd4);
3106                 if (ASIC_IS_DCE32(rdev)) {
3107                         WREG32(DC_HPD5_INT_CONTROL, hpd5);
3108                         WREG32(DC_HPD6_INT_CONTROL, hpd6);
3109                 }
3110         } else {
3111                 WREG32(R600_HDMI_BLOCK2 + R600_HDMI_CNTL, hdmi2);
3112                 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
3113                 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
3114                 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
3115         }
3116
3117         return 0;
3118 }
3119
3120 static inline void r600_irq_ack(struct radeon_device *rdev)
3121 {
3122         u32 tmp;
3123
3124         if (ASIC_IS_DCE3(rdev)) {
3125                 rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
3126                 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
3127                 rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
3128         } else {
3129                 rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS);
3130                 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
3131                 rdev->irq.stat_regs.r600.disp_int_cont2 = 0;
3132         }
3133         rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS);
3134         rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS);
3135
3136         if (rdev->irq.stat_regs.r600.d1grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3137                 WREG32(D1GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3138         if (rdev->irq.stat_regs.r600.d2grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3139                 WREG32(D2GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3140         if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT)
3141                 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
3142         if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT)
3143                 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
3144         if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT)
3145                 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
3146         if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT)
3147                 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
3148         if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
3149                 if (ASIC_IS_DCE3(rdev)) {
3150                         tmp = RREG32(DC_HPD1_INT_CONTROL);
3151                         tmp |= DC_HPDx_INT_ACK;
3152                         WREG32(DC_HPD1_INT_CONTROL, tmp);
3153                 } else {
3154                         tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
3155                         tmp |= DC_HPDx_INT_ACK;
3156                         WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
3157                 }
3158         }
3159         if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
3160                 if (ASIC_IS_DCE3(rdev)) {
3161                         tmp = RREG32(DC_HPD2_INT_CONTROL);
3162                         tmp |= DC_HPDx_INT_ACK;
3163                         WREG32(DC_HPD2_INT_CONTROL, tmp);
3164                 } else {
3165                         tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
3166                         tmp |= DC_HPDx_INT_ACK;
3167                         WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
3168                 }
3169         }
3170         if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
3171                 if (ASIC_IS_DCE3(rdev)) {
3172                         tmp = RREG32(DC_HPD3_INT_CONTROL);
3173                         tmp |= DC_HPDx_INT_ACK;
3174                         WREG32(DC_HPD3_INT_CONTROL, tmp);
3175                 } else {
3176                         tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
3177                         tmp |= DC_HPDx_INT_ACK;
3178                         WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
3179                 }
3180         }
3181         if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
3182                 tmp = RREG32(DC_HPD4_INT_CONTROL);
3183                 tmp |= DC_HPDx_INT_ACK;
3184                 WREG32(DC_HPD4_INT_CONTROL, tmp);
3185         }
3186         if (ASIC_IS_DCE32(rdev)) {
3187                 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
3188                         tmp = RREG32(DC_HPD5_INT_CONTROL);
3189                         tmp |= DC_HPDx_INT_ACK;
3190                         WREG32(DC_HPD5_INT_CONTROL, tmp);
3191                 }
3192                 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
3193                         tmp = RREG32(DC_HPD5_INT_CONTROL);
3194                         tmp |= DC_HPDx_INT_ACK;
3195                         WREG32(DC_HPD6_INT_CONTROL, tmp);
3196                 }
3197         }
3198         if (RREG32(R600_HDMI_BLOCK1 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3199                 WREG32_P(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3200         }
3201         if (ASIC_IS_DCE3(rdev)) {
3202                 if (RREG32(R600_HDMI_BLOCK3 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3203                         WREG32_P(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3204                 }
3205         } else {
3206                 if (RREG32(R600_HDMI_BLOCK2 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3207                         WREG32_P(R600_HDMI_BLOCK2 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3208                 }
3209         }
3210 }
3211
3212 void r600_irq_disable(struct radeon_device *rdev)
3213 {
3214         r600_disable_interrupts(rdev);
3215         /* Wait and acknowledge irq */
3216         mdelay(1);
3217         r600_irq_ack(rdev);
3218         r600_disable_interrupt_state(rdev);
3219 }
3220
3221 static inline u32 r600_get_ih_wptr(struct radeon_device *rdev)
3222 {
3223         u32 wptr, tmp;
3224
3225         if (rdev->wb.enabled)
3226                 wptr = rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4];
3227         else
3228                 wptr = RREG32(IH_RB_WPTR);
3229
3230         if (wptr & RB_OVERFLOW) {
3231                 /* When a ring buffer overflow happen start parsing interrupt
3232                  * from the last not overwritten vector (wptr + 16). Hopefully
3233                  * this should allow us to catchup.
3234                  */
3235                 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
3236                         wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
3237                 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
3238                 tmp = RREG32(IH_RB_CNTL);
3239                 tmp |= IH_WPTR_OVERFLOW_CLEAR;
3240                 WREG32(IH_RB_CNTL, tmp);
3241         }
3242         return (wptr & rdev->ih.ptr_mask);
3243 }
3244
3245 /*        r600 IV Ring
3246  * Each IV ring entry is 128 bits:
3247  * [7:0]    - interrupt source id
3248  * [31:8]   - reserved
3249  * [59:32]  - interrupt source data
3250  * [127:60]  - reserved
3251  *
3252  * The basic interrupt vector entries
3253  * are decoded as follows:
3254  * src_id  src_data  description
3255  *      1         0  D1 Vblank
3256  *      1         1  D1 Vline
3257  *      5         0  D2 Vblank
3258  *      5         1  D2 Vline
3259  *     19         0  FP Hot plug detection A
3260  *     19         1  FP Hot plug detection B
3261  *     19         2  DAC A auto-detection
3262  *     19         3  DAC B auto-detection
3263  *     21         4  HDMI block A
3264  *     21         5  HDMI block B
3265  *    176         -  CP_INT RB
3266  *    177         -  CP_INT IB1
3267  *    178         -  CP_INT IB2
3268  *    181         -  EOP Interrupt
3269  *    233         -  GUI Idle
3270  *
3271  * Note, these are based on r600 and may need to be
3272  * adjusted or added to on newer asics
3273  */
3274
3275 int r600_irq_process(struct radeon_device *rdev)
3276 {
3277         u32 wptr = r600_get_ih_wptr(rdev);
3278         u32 rptr = rdev->ih.rptr;
3279         u32 src_id, src_data;
3280         u32 ring_index;
3281         unsigned long flags;
3282         bool queue_hotplug = false;
3283
3284         DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
3285         if (!rdev->ih.enabled)
3286                 return IRQ_NONE;
3287
3288         spin_lock_irqsave(&rdev->ih.lock, flags);
3289
3290         if (rptr == wptr) {
3291                 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3292                 return IRQ_NONE;
3293         }
3294         if (rdev->shutdown) {
3295                 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3296                 return IRQ_NONE;
3297         }
3298
3299 restart_ih:
3300         /* display interrupts */
3301         r600_irq_ack(rdev);
3302
3303         rdev->ih.wptr = wptr;
3304         while (rptr != wptr) {
3305                 /* wptr/rptr are in bytes! */
3306                 ring_index = rptr / 4;
3307                 src_id =  rdev->ih.ring[ring_index] & 0xff;
3308                 src_data = rdev->ih.ring[ring_index + 1] & 0xfffffff;
3309
3310                 switch (src_id) {
3311                 case 1: /* D1 vblank/vline */
3312                         switch (src_data) {
3313                         case 0: /* D1 vblank */
3314                                 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) {
3315                                         if (rdev->irq.crtc_vblank_int[0]) {
3316                                                 drm_handle_vblank(rdev->ddev, 0);
3317                                                 rdev->pm.vblank_sync = true;
3318                                                 wake_up(&rdev->irq.vblank_queue);
3319                                         }
3320                                         if (rdev->irq.pflip[0])
3321                                                 radeon_crtc_handle_flip(rdev, 0);
3322                                         rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
3323                                         DRM_DEBUG("IH: D1 vblank\n");
3324                                 }
3325                                 break;
3326                         case 1: /* D1 vline */
3327                                 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) {
3328                                         rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT;
3329                                         DRM_DEBUG("IH: D1 vline\n");
3330                                 }
3331                                 break;
3332                         default:
3333                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3334                                 break;
3335                         }
3336                         break;
3337                 case 5: /* D2 vblank/vline */
3338                         switch (src_data) {
3339                         case 0: /* D2 vblank */
3340                                 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) {
3341                                         if (rdev->irq.crtc_vblank_int[1]) {
3342                                                 drm_handle_vblank(rdev->ddev, 1);
3343                                                 rdev->pm.vblank_sync = true;
3344                                                 wake_up(&rdev->irq.vblank_queue);
3345                                         }
3346                                         if (rdev->irq.pflip[1])
3347                                                 radeon_crtc_handle_flip(rdev, 1);
3348                                         rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT;
3349                                         DRM_DEBUG("IH: D2 vblank\n");
3350                                 }
3351                                 break;
3352                         case 1: /* D1 vline */
3353                                 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) {
3354                                         rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT;
3355                                         DRM_DEBUG("IH: D2 vline\n");
3356                                 }
3357                                 break;
3358                         default:
3359                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3360                                 break;
3361                         }
3362                         break;
3363                 case 19: /* HPD/DAC hotplug */
3364                         switch (src_data) {
3365                         case 0:
3366                                 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
3367                                         rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT;
3368                                         queue_hotplug = true;
3369                                         DRM_DEBUG("IH: HPD1\n");
3370                                 }
3371                                 break;
3372                         case 1:
3373                                 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
3374                                         rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT;
3375                                         queue_hotplug = true;
3376                                         DRM_DEBUG("IH: HPD2\n");
3377                                 }
3378                                 break;
3379                         case 4:
3380                                 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
3381                                         rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT;
3382                                         queue_hotplug = true;
3383                                         DRM_DEBUG("IH: HPD3\n");
3384                                 }
3385                                 break;
3386                         case 5:
3387                                 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
3388                                         rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT;
3389                                         queue_hotplug = true;
3390                                         DRM_DEBUG("IH: HPD4\n");
3391                                 }
3392                                 break;
3393                         case 10:
3394                                 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
3395                                         rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT;
3396                                         queue_hotplug = true;
3397                                         DRM_DEBUG("IH: HPD5\n");
3398                                 }
3399                                 break;
3400                         case 12:
3401                                 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
3402                                         rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT;
3403                                         queue_hotplug = true;
3404                                         DRM_DEBUG("IH: HPD6\n");
3405                                 }
3406                                 break;
3407                         default:
3408                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3409                                 break;
3410                         }
3411                         break;
3412                 case 21: /* HDMI */
3413                         DRM_DEBUG("IH: HDMI: 0x%x\n", src_data);
3414                         r600_audio_schedule_polling(rdev);
3415                         break;
3416                 case 176: /* CP_INT in ring buffer */
3417                 case 177: /* CP_INT in IB1 */
3418                 case 178: /* CP_INT in IB2 */
3419                         DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
3420                         radeon_fence_process(rdev);
3421                         break;
3422                 case 181: /* CP EOP event */
3423                         DRM_DEBUG("IH: CP EOP\n");
3424                         radeon_fence_process(rdev);
3425                         break;
3426                 case 233: /* GUI IDLE */
3427                         DRM_DEBUG("IH: CP EOP\n");
3428                         rdev->pm.gui_idle = true;
3429                         wake_up(&rdev->irq.idle_queue);
3430                         break;
3431                 default:
3432                         DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3433                         break;
3434                 }
3435
3436                 /* wptr/rptr are in bytes! */
3437                 rptr += 16;
3438                 rptr &= rdev->ih.ptr_mask;
3439         }
3440         /* make sure wptr hasn't changed while processing */
3441         wptr = r600_get_ih_wptr(rdev);
3442         if (wptr != rdev->ih.wptr)
3443                 goto restart_ih;
3444         if (queue_hotplug)
3445                 schedule_work(&rdev->hotplug_work);
3446         rdev->ih.rptr = rptr;
3447         WREG32(IH_RB_RPTR, rdev->ih.rptr);
3448         spin_unlock_irqrestore(&rdev->ih.lock, flags);
3449         return IRQ_HANDLED;
3450 }
3451
3452 /*
3453  * Debugfs info
3454  */
3455 #if defined(CONFIG_DEBUG_FS)
3456
3457 static int r600_debugfs_cp_ring_info(struct seq_file *m, void *data)
3458 {
3459         struct drm_info_node *node = (struct drm_info_node *) m->private;
3460         struct drm_device *dev = node->minor->dev;
3461         struct radeon_device *rdev = dev->dev_private;
3462         unsigned count, i, j;
3463
3464         radeon_ring_free_size(rdev);
3465         count = (rdev->cp.ring_size / 4) - rdev->cp.ring_free_dw;
3466         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(CP_STAT));
3467         seq_printf(m, "CP_RB_WPTR 0x%08x\n", RREG32(CP_RB_WPTR));
3468         seq_printf(m, "CP_RB_RPTR 0x%08x\n", RREG32(CP_RB_RPTR));
3469         seq_printf(m, "driver's copy of the CP_RB_WPTR 0x%08x\n", rdev->cp.wptr);
3470         seq_printf(m, "driver's copy of the CP_RB_RPTR 0x%08x\n", rdev->cp.rptr);
3471         seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
3472         seq_printf(m, "%u dwords in ring\n", count);
3473         i = rdev->cp.rptr;
3474         for (j = 0; j <= count; j++) {
3475                 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
3476                 i = (i + 1) & rdev->cp.ptr_mask;
3477         }
3478         return 0;
3479 }
3480
3481 static int r600_debugfs_mc_info(struct seq_file *m, void *data)
3482 {
3483         struct drm_info_node *node = (struct drm_info_node *) m->private;
3484         struct drm_device *dev = node->minor->dev;
3485         struct radeon_device *rdev = dev->dev_private;
3486
3487         DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
3488         DREG32_SYS(m, rdev, VM_L2_STATUS);
3489         return 0;
3490 }
3491
3492 static struct drm_info_list r600_mc_info_list[] = {
3493         {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
3494         {"r600_ring_info", r600_debugfs_cp_ring_info, 0, NULL},
3495 };
3496 #endif
3497
3498 int r600_debugfs_mc_info_init(struct radeon_device *rdev)
3499 {
3500 #if defined(CONFIG_DEBUG_FS)
3501         return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
3502 #else
3503         return 0;
3504 #endif
3505 }
3506
3507 /**
3508  * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl
3509  * rdev: radeon device structure
3510  * bo: buffer object struct which userspace is waiting for idle
3511  *
3512  * Some R6XX/R7XX doesn't seems to take into account HDP flush performed
3513  * through ring buffer, this leads to corruption in rendering, see
3514  * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we
3515  * directly perform HDP flush by writing register through MMIO.
3516  */
3517 void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
3518 {
3519         /* r7xx hw bug.  write to HDP_DEBUG1 followed by fb read
3520          * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL.
3521          * This seems to cause problems on some AGP cards. Just use the old
3522          * method for them.
3523          */
3524         if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
3525             rdev->vram_scratch.ptr && !(rdev->flags & RADEON_IS_AGP)) {
3526                 void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
3527                 u32 tmp;
3528
3529                 WREG32(HDP_DEBUG1, 0);
3530                 tmp = readl((void __iomem *)ptr);
3531         } else
3532                 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
3533 }