Pileus Git - ~andy/linux/blob - drivers/gpu/drm/radeon/r600.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/slab.h>
  29 #include <linux/seq_file.h>
  30 #include <linux/firmware.h>
  31 #include <linux/platform_device.h>
  32 #include "drmP.h"
  33 #include "radeon_drm.h"
  34 #include "radeon.h"
  35 #include "radeon_asic.h"
  36 #include "radeon_mode.h"
  37 #include "r600d.h"
  38 #include "atom.h"
  39 #include "avivod.h"
  40
  41 #define PFP_UCODE_SIZE 576
  42 #define PM4_UCODE_SIZE 1792
  43 #define RLC_UCODE_SIZE 768
  44 #define R700_PFP_UCODE_SIZE 848
  45 #define R700_PM4_UCODE_SIZE 1360
  46 #define R700_RLC_UCODE_SIZE 1024
  47 #define EVERGREEN_PFP_UCODE_SIZE 1120
  48 #define EVERGREEN_PM4_UCODE_SIZE 1376
  49 #define EVERGREEN_RLC_UCODE_SIZE 768
  50 #define CAYMAN_RLC_UCODE_SIZE 1024
  51
  52 /* Firmware Names */
  53 MODULE_FIRMWARE("radeon/R600_pfp.bin");
  54 MODULE_FIRMWARE("radeon/R600_me.bin");
  55 MODULE_FIRMWARE("radeon/RV610_pfp.bin");
  56 MODULE_FIRMWARE("radeon/RV610_me.bin");
  57 MODULE_FIRMWARE("radeon/RV630_pfp.bin");
  58 MODULE_FIRMWARE("radeon/RV630_me.bin");
  59 MODULE_FIRMWARE("radeon/RV620_pfp.bin");
  60 MODULE_FIRMWARE("radeon/RV620_me.bin");
  61 MODULE_FIRMWARE("radeon/RV635_pfp.bin");
  62 MODULE_FIRMWARE("radeon/RV635_me.bin");
  63 MODULE_FIRMWARE("radeon/RV670_pfp.bin");
  64 MODULE_FIRMWARE("radeon/RV670_me.bin");
  65 MODULE_FIRMWARE("radeon/RS780_pfp.bin");
  66 MODULE_FIRMWARE("radeon/RS780_me.bin");
  67 MODULE_FIRMWARE("radeon/RV770_pfp.bin");
  68 MODULE_FIRMWARE("radeon/RV770_me.bin");
  69 MODULE_FIRMWARE("radeon/RV730_pfp.bin");
  70 MODULE_FIRMWARE("radeon/RV730_me.bin");
  71 MODULE_FIRMWARE("radeon/RV710_pfp.bin");
  72 MODULE_FIRMWARE("radeon/RV710_me.bin");
  73 MODULE_FIRMWARE("radeon/R600_rlc.bin");
  74 MODULE_FIRMWARE("radeon/R700_rlc.bin");
  75 MODULE_FIRMWARE("radeon/CEDAR_pfp.bin");
  76 MODULE_FIRMWARE("radeon/CEDAR_me.bin");
  77 MODULE_FIRMWARE("radeon/CEDAR_rlc.bin");
  78 MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin");
  79 MODULE_FIRMWARE("radeon/REDWOOD_me.bin");
  80 MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin");
  81 MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin");
  82 MODULE_FIRMWARE("radeon/JUNIPER_me.bin");
  83 MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin");
  84 MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin");
  85 MODULE_FIRMWARE("radeon/CYPRESS_me.bin");
  86 MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin");
  87 MODULE_FIRMWARE("radeon/PALM_pfp.bin");
  88 MODULE_FIRMWARE("radeon/PALM_me.bin");
  89 MODULE_FIRMWARE("radeon/SUMO_rlc.bin");
  90
  91 int r600_debugfs_mc_info_init(struct radeon_device *rdev);
  92
  93 /* r600,rv610,rv630,rv620,rv635,rv670 */
  94 int r600_mc_wait_for_idle(struct radeon_device *rdev);
  95 void r600_gpu_init(struct radeon_device *rdev);
  96 void r600_fini(struct radeon_device *rdev);
  97 void r600_irq_disable(struct radeon_device *rdev);
  98 static void r600_pcie_gen2_enable(struct radeon_device *rdev);
  99
 100 /* get temperature in millidegrees */
 101 int rv6xx_get_temp(struct radeon_device *rdev)
 102 {
 103         u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >>
 104                 ASIC_T_SHIFT;
 105         int actual_temp = temp & 0xff;
 106
 107         if (temp & 0x100)
 108                 actual_temp -= 256;
 109
 110         return actual_temp * 1000;
 111 }
 112
 113 void r600_pm_get_dynpm_state(struct radeon_device *rdev)
 114 {
 115         int i;
 116
 117         rdev->pm.dynpm_can_upclock = true;
 118         rdev->pm.dynpm_can_downclock = true;
 119
 120         /* power state array is low to high, default is first */
 121         if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) {
 122                 int min_power_state_index = 0;
 123
 124                 if (rdev->pm.num_power_states > 2)
 125                         min_power_state_index = 1;
 126
 127                 switch (rdev->pm.dynpm_planned_action) {
 128                 case DYNPM_ACTION_MINIMUM:
 129                         rdev->pm.requested_power_state_index = min_power_state_index;
 130                         rdev->pm.requested_clock_mode_index = 0;
 131                         rdev->pm.dynpm_can_downclock = false;
 132                         break;
 133                 case DYNPM_ACTION_DOWNCLOCK:
 134                         if (rdev->pm.current_power_state_index == min_power_state_index) {
 135                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 136                                 rdev->pm.dynpm_can_downclock = false;
 137                         } else {
 138                                 if (rdev->pm.active_crtc_count > 1) {
 139                                         for (i = 0; i < rdev->pm.num_power_states; i++) {
 140                                                 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 141                                                         continue;
 142                                                 else if (i >= rdev->pm.current_power_state_index) {
 143                                                         rdev->pm.requested_power_state_index =
 144                                                                 rdev->pm.current_power_state_index;
 145                                                         break;
 146                                                 } else {
 147                                                         rdev->pm.requested_power_state_index = i;
 148                                                         break;
 149                                                 }
 150                                         }
 151                                 } else {
 152                                         if (rdev->pm.current_power_state_index == 0)
 153                                                 rdev->pm.requested_power_state_index =
 154                                                         rdev->pm.num_power_states - 1;
 155                                         else
 156                                                 rdev->pm.requested_power_state_index =
 157                                                         rdev->pm.current_power_state_index - 1;
 158                                 }
 159                         }
 160                         rdev->pm.requested_clock_mode_index = 0;
 161                         /* don't use the power state if crtcs are active and no display flag is set */
 162                         if ((rdev->pm.active_crtc_count > 0) &&
 163                             (rdev->pm.power_state[rdev->pm.requested_power_state_index].
 164                              clock_info[rdev->pm.requested_clock_mode_index].flags &
 165                              RADEON_PM_MODE_NO_DISPLAY)) {
 166                                 rdev->pm.requested_power_state_index++;
 167                         }
 168                         break;
 169                 case DYNPM_ACTION_UPCLOCK:
 170                         if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
 171                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 172                                 rdev->pm.dynpm_can_upclock = false;
 173                         } else {
 174                                 if (rdev->pm.active_crtc_count > 1) {
 175                                         for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
 176                                                 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 177                                                         continue;
 178                                                 else if (i <= rdev->pm.current_power_state_index) {
 179                                                         rdev->pm.requested_power_state_index =
 180                                                                 rdev->pm.current_power_state_index;
 181                                                         break;
 182                                                 } else {
 183                                                         rdev->pm.requested_power_state_index = i;
 184                                                         break;
 185                                                 }
 186                                         }
 187                                 } else
 188                                         rdev->pm.requested_power_state_index =
 189                                                 rdev->pm.current_power_state_index + 1;
 190                         }
 191                         rdev->pm.requested_clock_mode_index = 0;
 192                         break;
 193                 case DYNPM_ACTION_DEFAULT:
 194                         rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
 195                         rdev->pm.requested_clock_mode_index = 0;
 196                         rdev->pm.dynpm_can_upclock = false;
 197                         break;
 198                 case DYNPM_ACTION_NONE:
 199                 default:
 200                         DRM_ERROR("Requested mode for not defined action\n");
 201                         return;
 202                 }
 203         } else {
 204                 /* XXX select a power state based on AC/DC, single/dualhead, etc. */
 205                 /* for now just select the first power state and switch between clock modes */
 206                 /* power state array is low to high, default is first (0) */
 207                 if (rdev->pm.active_crtc_count > 1) {
 208                         rdev->pm.requested_power_state_index = -1;
 209                         /* start at 1 as we don't want the default mode */
 210                         for (i = 1; i < rdev->pm.num_power_states; i++) {
 211                                 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 212                                         continue;
 213                                 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) ||
 214                                          (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) {
 215                                         rdev->pm.requested_power_state_index = i;
 216                                         break;
 217                                 }
 218                         }
 219                         /* if nothing selected, grab the default state. */
 220                         if (rdev->pm.requested_power_state_index == -1)
 221                                 rdev->pm.requested_power_state_index = 0;
 222                 } else
 223                         rdev->pm.requested_power_state_index = 1;
 224
 225                 switch (rdev->pm.dynpm_planned_action) {
 226                 case DYNPM_ACTION_MINIMUM:
 227                         rdev->pm.requested_clock_mode_index = 0;
 228                         rdev->pm.dynpm_can_downclock = false;
 229                         break;
 230                 case DYNPM_ACTION_DOWNCLOCK:
 231                         if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
 232                                 if (rdev->pm.current_clock_mode_index == 0) {
 233                                         rdev->pm.requested_clock_mode_index = 0;
 234                                         rdev->pm.dynpm_can_downclock = false;
 235                                 } else
 236                                         rdev->pm.requested_clock_mode_index =
 237                                                 rdev->pm.current_clock_mode_index - 1;
 238                         } else {
 239                                 rdev->pm.requested_clock_mode_index = 0;
 240                                 rdev->pm.dynpm_can_downclock = false;
 241                         }
 242                         /* don't use the power state if crtcs are active and no display flag is set */
 243                         if ((rdev->pm.active_crtc_count > 0) &&
 244                             (rdev->pm.power_state[rdev->pm.requested_power_state_index].
 245                              clock_info[rdev->pm.requested_clock_mode_index].flags &
 246                              RADEON_PM_MODE_NO_DISPLAY)) {
 247                                 rdev->pm.requested_clock_mode_index++;
 248                         }
 249                         break;
 250                 case DYNPM_ACTION_UPCLOCK:
 251                         if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
 252                                 if (rdev->pm.current_clock_mode_index ==
 253                                     (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) {
 254                                         rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index;
 255                                         rdev->pm.dynpm_can_upclock = false;
 256                                 } else
 257                                         rdev->pm.requested_clock_mode_index =
 258                                                 rdev->pm.current_clock_mode_index + 1;
 259                         } else {
 260                                 rdev->pm.requested_clock_mode_index =
 261                                         rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1;
 262                                 rdev->pm.dynpm_can_upclock = false;
 263                         }
 264                         break;
 265                 case DYNPM_ACTION_DEFAULT:
 266                         rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
 267                         rdev->pm.requested_clock_mode_index = 0;
 268                         rdev->pm.dynpm_can_upclock = false;
 269                         break;
 270                 case DYNPM_ACTION_NONE:
 271                 default:
 272                         DRM_ERROR("Requested mode for not defined action\n");
 273                         return;
 274                 }
 275         }
 276
 277         DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
 278                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 279                   clock_info[rdev->pm.requested_clock_mode_index].sclk,
 280                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 281                   clock_info[rdev->pm.requested_clock_mode_index].mclk,
 282                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 283                   pcie_lanes);
 284 }
 285
 286 static int r600_pm_get_type_index(struct radeon_device *rdev,
 287                                   enum radeon_pm_state_type ps_type,
 288                                   int instance)
 289 {
 290         int i;
 291         int found_instance = -1;
 292
 293         for (i = 0; i < rdev->pm.num_power_states; i++) {
 294                 if (rdev->pm.power_state[i].type == ps_type) {
 295                         found_instance++;
 296                         if (found_instance == instance)
 297                                 return i;
 298                 }
 299         }
 300         /* return default if no match */
 301         return rdev->pm.default_power_state_index;
 302 }
 303
 304 void rs780_pm_init_profile(struct radeon_device *rdev)
 305 {
 306         if (rdev->pm.num_power_states == 2) {
 307                 /* default */
 308                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 309                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 310                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 311                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 312                 /* low sh */
 313                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
 314                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
 315                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 316                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 317                 /* mid sh */
 318                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
 319                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
 320                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 321                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 322                 /* high sh */
 323                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
 324                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
 325                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 326                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 327                 /* low mh */
 328                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
 329                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
 330                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 331                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 332                 /* mid mh */
 333                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
 334                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
 335                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 336                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 337                 /* high mh */
 338                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
 339                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1;
 340                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 341                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 342         } else if (rdev->pm.num_power_states == 3) {
 343                 /* default */
 344                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 345                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 346                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 347                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 348                 /* low sh */
 349                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
 350                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
 351                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 352                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 353                 /* mid sh */
 354                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
 355                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
 356                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 357                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 358                 /* high sh */
 359                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
 360                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2;
 361                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 362                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 363                 /* low mh */
 364                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1;
 365                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1;
 366                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 367                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 368                 /* mid mh */
 369                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1;
 370                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1;
 371                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 372                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 373                 /* high mh */
 374                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1;
 375                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
 376                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 377                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 378         } else {
 379                 /* default */
 380                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 381                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 382                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 383                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 384                 /* low sh */
 385                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2;
 386                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2;
 387                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 388                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 389                 /* mid sh */
 390                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2;
 391                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2;
 392                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 393                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 394                 /* high sh */
 395                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2;
 396                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3;
 397                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 398                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 399                 /* low mh */
 400                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
 401                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
 402                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 403                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 404                 /* mid mh */
 405                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
 406                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
 407                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 408                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 409                 /* high mh */
 410                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
 411                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3;
 412                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 413                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 414         }
 415 }
 416
 417 void r600_pm_init_profile(struct radeon_device *rdev)
 418 {
 419         if (rdev->family == CHIP_R600) {
 420                 /* XXX */
 421                 /* default */
 422                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 423                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 424                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 425                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 426                 /* low sh */
 427                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 428                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 429                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 430                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 431                 /* mid sh */
 432                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 433                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 434                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 435                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 436                 /* high sh */
 437                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 438                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 439                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 440                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 441                 /* low mh */
 442                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 443                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 444                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 445                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 446                 /* mid mh */
 447                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 448                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 449                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 450                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 451                 /* high mh */
 452                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 453                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 454                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 455                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 456         } else {
 457                 if (rdev->pm.num_power_states < 4) {
 458                         /* default */
 459                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 460                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 461                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 462                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
 463                         /* low sh */
 464                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
 465                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
 466                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 467                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 468                         /* mid sh */
 469                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
 470                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
 471                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 472                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
 473                         /* high sh */
 474                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
 475                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
 476                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 477                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
 478                         /* low mh */
 479                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
 480                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2;
 481                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 482                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 483                         /* low mh */
 484                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
 485                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2;
 486                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 487                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
 488                         /* high mh */
 489                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
 490                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
 491                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 492                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
 493                 } else {
 494                         /* default */
 495                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 496                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 497                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 498                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
 499                         /* low sh */
 500                         if (rdev->flags & RADEON_IS_MOBILITY) {
 501                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx =
 502                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
 503                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx =
 504                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
 505                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 506                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 507                         } else {
 508                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx =
 509                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 510                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx =
 511                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 512                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 513                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 514                         }
 515                         /* mid sh */
 516                         if (rdev->flags & RADEON_IS_MOBILITY) {
 517                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx =
 518                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
 519                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx =
 520                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
 521                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 522                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
 523                         } else {
 524                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx =
 525                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 526                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx =
 527                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 528                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 529                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
 530                         }
 531                         /* high sh */
 532                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx =
 533                                 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 534                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx =
 535                                 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 536                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 537                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
 538                         /* low mh */
 539                         if (rdev->flags & RADEON_IS_MOBILITY) {
 540                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx =
 541                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
 542                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx =
 543                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
 544                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 545                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 546                         } else {
 547                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx =
 548                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 549                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx =
 550                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 551                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 552                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 553                         }
 554                         /* mid mh */
 555                         if (rdev->flags & RADEON_IS_MOBILITY) {
 556                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx =
 557                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
 558                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx =
 559                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
 560                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 561                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
 562                         } else {
 563                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx =
 564                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 565                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx =
 566                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 567                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 568                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
 569                         }
 570                         /* high mh */
 571                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx =
 572                                 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 573                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx =
 574                                 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 575                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 576                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
 577                 }
 578         }
 579 }
 580
 581 void r600_pm_misc(struct radeon_device *rdev)
 582 {
 583         int req_ps_idx = rdev->pm.requested_power_state_index;
 584         int req_cm_idx = rdev->pm.requested_clock_mode_index;
 585         struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
 586         struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
 587
 588         if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
 589                 if (voltage->voltage != rdev->pm.current_vddc) {
 590                         radeon_atom_set_voltage(rdev, voltage->voltage);
 591                         rdev->pm.current_vddc = voltage->voltage;
 592                         DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage->voltage);
 593                 }
 594         }
 595 }
 596
 597 bool r600_gui_idle(struct radeon_device *rdev)
 598 {
 599         if (RREG32(GRBM_STATUS) & GUI_ACTIVE)
 600                 return false;
 601         else
 602                 return true;
 603 }
 604
 605 /* hpd for digital panel detect/disconnect */
 606 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
 607 {
 608         bool connected = false;
 609
 610         if (ASIC_IS_DCE3(rdev)) {
 611                 switch (hpd) {
 612                 case RADEON_HPD_1:
 613                         if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
 614                                 connected = true;
 615                         break;
 616                 case RADEON_HPD_2:
 617                         if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
 618                                 connected = true;
 619                         break;
 620                 case RADEON_HPD_3:
 621                         if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
 622                                 connected = true;
 623                         break;
 624                 case RADEON_HPD_4:
 625                         if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
 626                                 connected = true;
 627                         break;
 628                         /* DCE 3.2 */
 629                 case RADEON_HPD_5:
 630                         if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
 631                                 connected = true;
 632                         break;
 633                 case RADEON_HPD_6:
 634                         if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
 635                                 connected = true;
 636                         break;
 637                 default:
 638                         break;
 639                 }
 640         } else {
 641                 switch (hpd) {
 642                 case RADEON_HPD_1:
 643                         if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 644                                 connected = true;
 645                         break;
 646                 case RADEON_HPD_2:
 647                         if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 648                                 connected = true;
 649                         break;
 650                 case RADEON_HPD_3:
 651                         if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 652                                 connected = true;
 653                         break;
 654                 default:
 655                         break;
 656                 }
 657         }
 658         return connected;
 659 }
 660
 661 void r600_hpd_set_polarity(struct radeon_device *rdev,
 662                            enum radeon_hpd_id hpd)
 663 {
 664         u32 tmp;
 665         bool connected = r600_hpd_sense(rdev, hpd);
 666
 667         if (ASIC_IS_DCE3(rdev)) {
 668                 switch (hpd) {
 669                 case RADEON_HPD_1:
 670                         tmp = RREG32(DC_HPD1_INT_CONTROL);
 671                         if (connected)
 672                                 tmp &= ~DC_HPDx_INT_POLARITY;
 673                         else
 674                                 tmp |= DC_HPDx_INT_POLARITY;
 675                         WREG32(DC_HPD1_INT_CONTROL, tmp);
 676                         break;
 677                 case RADEON_HPD_2:
 678                         tmp = RREG32(DC_HPD2_INT_CONTROL);
 679                         if (connected)
 680                                 tmp &= ~DC_HPDx_INT_POLARITY;
 681                         else
 682                                 tmp |= DC_HPDx_INT_POLARITY;
 683                         WREG32(DC_HPD2_INT_CONTROL, tmp);
 684                         break;
 685                 case RADEON_HPD_3:
 686                         tmp = RREG32(DC_HPD3_INT_CONTROL);
 687                         if (connected)
 688                                 tmp &= ~DC_HPDx_INT_POLARITY;
 689                         else
 690                                 tmp |= DC_HPDx_INT_POLARITY;
 691                         WREG32(DC_HPD3_INT_CONTROL, tmp);
 692                         break;
 693                 case RADEON_HPD_4:
 694                         tmp = RREG32(DC_HPD4_INT_CONTROL);
 695                         if (connected)
 696                                 tmp &= ~DC_HPDx_INT_POLARITY;
 697                         else
 698                                 tmp |= DC_HPDx_INT_POLARITY;
 699                         WREG32(DC_HPD4_INT_CONTROL, tmp);
 700                         break;
 701                 case RADEON_HPD_5:
 702                         tmp = RREG32(DC_HPD5_INT_CONTROL);
 703                         if (connected)
 704                                 tmp &= ~DC_HPDx_INT_POLARITY;
 705                         else
 706                                 tmp |= DC_HPDx_INT_POLARITY;
 707                         WREG32(DC_HPD5_INT_CONTROL, tmp);
 708                         break;
 709                         /* DCE 3.2 */
 710                 case RADEON_HPD_6:
 711                         tmp = RREG32(DC_HPD6_INT_CONTROL);
 712                         if (connected)
 713                                 tmp &= ~DC_HPDx_INT_POLARITY;
 714                         else
 715                                 tmp |= DC_HPDx_INT_POLARITY;
 716                         WREG32(DC_HPD6_INT_CONTROL, tmp);
 717                         break;
 718                 default:
 719                         break;
 720                 }
 721         } else {
 722                 switch (hpd) {
 723                 case RADEON_HPD_1:
 724                         tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
 725                         if (connected)
 726                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 727                         else
 728                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 729                         WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
 730                         break;
 731                 case RADEON_HPD_2:
 732                         tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
 733                         if (connected)
 734                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 735                         else
 736                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 737                         WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
 738                         break;
 739                 case RADEON_HPD_3:
 740                         tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
 741                         if (connected)
 742                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 743                         else
 744                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 745                         WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
 746                         break;
 747                 default:
 748                         break;
 749                 }
 750         }
 751 }
 752
 753 void r600_hpd_init(struct radeon_device *rdev)
 754 {
 755         struct drm_device *dev = rdev->ddev;
 756         struct drm_connector *connector;
 757
 758         if (ASIC_IS_DCE3(rdev)) {
 759                 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
 760                 if (ASIC_IS_DCE32(rdev))
 761                         tmp |= DC_HPDx_EN;
 762
 763                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 764                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 765                         switch (radeon_connector->hpd.hpd) {
 766                         case RADEON_HPD_1:
 767                                 WREG32(DC_HPD1_CONTROL, tmp);
 768                                 rdev->irq.hpd[0] = true;
 769                                 break;
 770                         case RADEON_HPD_2:
 771                                 WREG32(DC_HPD2_CONTROL, tmp);
 772                                 rdev->irq.hpd[1] = true;
 773                                 break;
 774                         case RADEON_HPD_3:
 775                                 WREG32(DC_HPD3_CONTROL, tmp);
 776                                 rdev->irq.hpd[2] = true;
 777                                 break;
 778                         case RADEON_HPD_4:
 779                                 WREG32(DC_HPD4_CONTROL, tmp);
 780                                 rdev->irq.hpd[3] = true;
 781                                 break;
 782                                 /* DCE 3.2 */
 783                         case RADEON_HPD_5:
 784                                 WREG32(DC_HPD5_CONTROL, tmp);
 785                                 rdev->irq.hpd[4] = true;
 786                                 break;
 787                         case RADEON_HPD_6:
 788                                 WREG32(DC_HPD6_CONTROL, tmp);
 789                                 rdev->irq.hpd[5] = true;
 790                                 break;
 791                         default:
 792                                 break;
 793                         }
 794                 }
 795         } else {
 796                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 797                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 798                         switch (radeon_connector->hpd.hpd) {
 799                         case RADEON_HPD_1:
 800                                 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 801                                 rdev->irq.hpd[0] = true;
 802                                 break;
 803                         case RADEON_HPD_2:
 804                                 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 805                                 rdev->irq.hpd[1] = true;
 806                                 break;
 807                         case RADEON_HPD_3:
 808                                 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 809                                 rdev->irq.hpd[2] = true;
 810                                 break;
 811                         default:
 812                                 break;
 813                         }
 814                 }
 815         }
 816         if (rdev->irq.installed)
 817                 r600_irq_set(rdev);
 818 }
 819
 820 void r600_hpd_fini(struct radeon_device *rdev)
 821 {
 822         struct drm_device *dev = rdev->ddev;
 823         struct drm_connector *connector;
 824
 825         if (ASIC_IS_DCE3(rdev)) {
 826                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 827                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 828                         switch (radeon_connector->hpd.hpd) {
 829                         case RADEON_HPD_1:
 830                                 WREG32(DC_HPD1_CONTROL, 0);
 831                                 rdev->irq.hpd[0] = false;
 832                                 break;
 833                         case RADEON_HPD_2:
 834                                 WREG32(DC_HPD2_CONTROL, 0);
 835                                 rdev->irq.hpd[1] = false;
 836                                 break;
 837                         case RADEON_HPD_3:
 838                                 WREG32(DC_HPD3_CONTROL, 0);
 839                                 rdev->irq.hpd[2] = false;
 840                                 break;
 841                         case RADEON_HPD_4:
 842                                 WREG32(DC_HPD4_CONTROL, 0);
 843                                 rdev->irq.hpd[3] = false;
 844                                 break;
 845                                 /* DCE 3.2 */
 846                         case RADEON_HPD_5:
 847                                 WREG32(DC_HPD5_CONTROL, 0);
 848                                 rdev->irq.hpd[4] = false;
 849                                 break;
 850                         case RADEON_HPD_6:
 851                                 WREG32(DC_HPD6_CONTROL, 0);
 852                                 rdev->irq.hpd[5] = false;
 853                                 break;
 854                         default:
 855                                 break;
 856                         }
 857                 }
 858         } else {
 859                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 860                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 861                         switch (radeon_connector->hpd.hpd) {
 862                         case RADEON_HPD_1:
 863                                 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
 864                                 rdev->irq.hpd[0] = false;
 865                                 break;
 866                         case RADEON_HPD_2:
 867                                 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
 868                                 rdev->irq.hpd[1] = false;
 869                                 break;
 870                         case RADEON_HPD_3:
 871                                 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
 872                                 rdev->irq.hpd[2] = false;
 873                                 break;
 874                         default:
 875                                 break;
 876                         }
 877                 }
 878         }
 879 }
 880
 881 /*
 882  * R600 PCIE GART
 883  */
 884 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
 885 {
 886         unsigned i;
 887         u32 tmp;
 888
 889         /* flush hdp cache so updates hit vram */
 890         if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
 891             !(rdev->flags & RADEON_IS_AGP)) {
 892                 void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
 893                 u32 tmp;
 894
 895                 /* r7xx hw bug.  write to HDP_DEBUG1 followed by fb read
 896                  * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL
 897                  * This seems to cause problems on some AGP cards. Just use the old
 898                  * method for them.
 899                  */
 900                 WREG32(HDP_DEBUG1, 0);
 901                 tmp = readl((void __iomem *)ptr);
 902         } else
 903                 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
 904
 905         WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
 906         WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
 907         WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
 908         for (i = 0; i < rdev->usec_timeout; i++) {
 909                 /* read MC_STATUS */
 910                 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
 911                 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
 912                 if (tmp == 2) {
 913                         printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
 914                         return;
 915                 }
 916                 if (tmp) {
 917                         return;
 918                 }
 919                 udelay(1);
 920         }
 921 }
 922
 923 int r600_pcie_gart_init(struct radeon_device *rdev)
 924 {
 925         int r;
 926
 927         if (rdev->gart.table.vram.robj) {
 928                 WARN(1, "R600 PCIE GART already initialized\n");
 929                 return 0;
 930         }
 931         /* Initialize common gart structure */
 932         r = radeon_gart_init(rdev);
 933         if (r)
 934                 return r;
 935         rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
 936         return radeon_gart_table_vram_alloc(rdev);
 937 }
 938
 939 int r600_pcie_gart_enable(struct radeon_device *rdev)
 940 {
 941         u32 tmp;
 942         int r, i;
 943
 944         if (rdev->gart.table.vram.robj == NULL) {
 945                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
 946                 return -EINVAL;
 947         }
 948         r = radeon_gart_table_vram_pin(rdev);
 949         if (r)
 950                 return r;
 951         radeon_gart_restore(rdev);
 952
 953         /* Setup L2 cache */
 954         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 955                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 956                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 957         WREG32(VM_L2_CNTL2, 0);
 958         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
 959         /* Setup TLB control */
 960         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
 961                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 962                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
 963                 ENABLE_WAIT_L2_QUERY;
 964         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
 965         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
 966         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
 967         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
 968         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
 969         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
 970         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
 971         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
 972         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
 973         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
 974         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
 975         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
 976         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 977         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 978         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
 979         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
 980         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
 981         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
 982                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
 983         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 984                         (u32)(rdev->dummy_page.addr >> 12));
 985         for (i = 1; i < 7; i++)
 986                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 987
 988         r600_pcie_gart_tlb_flush(rdev);
 989         rdev->gart.ready = true;
 990         return 0;
 991 }
 992
 993 void r600_pcie_gart_disable(struct radeon_device *rdev)
 994 {
 995         u32 tmp;
 996         int i, r;
 997
 998         /* Disable all tables */
 999         for (i = 0; i < 7; i++)
1000                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1001
1002         /* Disable L2 cache */
1003         WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
1004                                 EFFECTIVE_L2_QUEUE_SIZE(7));
1005         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1006         /* Setup L1 TLB control */
1007         tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1008                 ENABLE_WAIT_L2_QUERY;
1009         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1010         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1011         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1012         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1013         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1014         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1015         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1016         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1017         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
1018         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
1019         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1020         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1021         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
1022         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1023         if (rdev->gart.table.vram.robj) {
1024                 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
1025                 if (likely(r == 0)) {
1026                         radeon_bo_kunmap(rdev->gart.table.vram.robj);
1027                         radeon_bo_unpin(rdev->gart.table.vram.robj);
1028                         radeon_bo_unreserve(rdev->gart.table.vram.robj);
1029                 }
1030         }
1031 }
1032
1033 void r600_pcie_gart_fini(struct radeon_device *rdev)
1034 {
1035         radeon_gart_fini(rdev);
1036         r600_pcie_gart_disable(rdev);
1037         radeon_gart_table_vram_free(rdev);
1038 }
1039
1040 void r600_agp_enable(struct radeon_device *rdev)
1041 {
1042         u32 tmp;
1043         int i;
1044
1045         /* Setup L2 cache */
1046         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1047                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1048                                 EFFECTIVE_L2_QUEUE_SIZE(7));
1049         WREG32(VM_L2_CNTL2, 0);
1050         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1051         /* Setup TLB control */
1052         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1053                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1054                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1055                 ENABLE_WAIT_L2_QUERY;
1056         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1057         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1058         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
1059         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1060         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1061         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1062         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1063         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1064         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1065         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1066         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1067         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1068         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1069         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1070         for (i = 0; i < 7; i++)
1071                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1072 }
1073
1074 int r600_mc_wait_for_idle(struct radeon_device *rdev)
1075 {
1076         unsigned i;
1077         u32 tmp;
1078
1079         for (i = 0; i < rdev->usec_timeout; i++) {
1080                 /* read MC_STATUS */
1081                 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
1082                 if (!tmp)
1083                         return 0;
1084                 udelay(1);
1085         }
1086         return -1;
1087 }
1088
1089 static void r600_mc_program(struct radeon_device *rdev)
1090 {
1091         struct rv515_mc_save save;
1092         u32 tmp;
1093         int i, j;
1094
1095         /* Initialize HDP */
1096         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1097                 WREG32((0x2c14 + j), 0x00000000);
1098                 WREG32((0x2c18 + j), 0x00000000);
1099                 WREG32((0x2c1c + j), 0x00000000);
1100                 WREG32((0x2c20 + j), 0x00000000);
1101                 WREG32((0x2c24 + j), 0x00000000);
1102         }
1103         WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1104
1105         rv515_mc_stop(rdev, &save);
1106         if (r600_mc_wait_for_idle(rdev)) {
1107                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1108         }
1109         /* Lockout access through VGA aperture (doesn't exist before R600) */
1110         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1111         /* Update configuration */
1112         if (rdev->flags & RADEON_IS_AGP) {
1113                 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1114                         /* VRAM before AGP */
1115                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1116                                 rdev->mc.vram_start >> 12);
1117                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1118                                 rdev->mc.gtt_end >> 12);
1119                 } else {
1120                         /* VRAM after AGP */
1121                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1122                                 rdev->mc.gtt_start >> 12);
1123                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1124                                 rdev->mc.vram_end >> 12);
1125                 }
1126         } else {
1127                 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
1128                 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
1129         }
1130         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
1131         tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1132         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1133         WREG32(MC_VM_FB_LOCATION, tmp);
1134         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1135         WREG32(HDP_NONSURFACE_INFO, (2 << 7));
1136         WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
1137         if (rdev->flags & RADEON_IS_AGP) {
1138                 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
1139                 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
1140                 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1141         } else {
1142                 WREG32(MC_VM_AGP_BASE, 0);
1143                 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1144                 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1145         }
1146         if (r600_mc_wait_for_idle(rdev)) {
1147                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1148         }
1149         rv515_mc_resume(rdev, &save);
1150         /* we need to own VRAM, so turn off the VGA renderer here
1151          * to stop it overwriting our objects */
1152         rv515_vga_render_disable(rdev);
1153 }
1154
1155 /**
1156  * r600_vram_gtt_location - try to find VRAM & GTT location
1157  * @rdev: radeon device structure holding all necessary informations
1158  * @mc: memory controller structure holding memory informations
1159  *
1160  * Function will place try to place VRAM at same place as in CPU (PCI)
1161  * address space as some GPU seems to have issue when we reprogram at
1162  * different address space.
1163  *
1164  * If there is not enough space to fit the unvisible VRAM after the
1165  * aperture then we limit the VRAM size to the aperture.
1166  *
1167  * If we are using AGP then place VRAM adjacent to AGP aperture are we need
1168  * them to be in one from GPU point of view so that we can program GPU to
1169  * catch access outside them (weird GPU policy see ??).
1170  *
1171  * This function will never fails, worst case are limiting VRAM or GTT.
1172  *
1173  * Note: GTT start, end, size should be initialized before calling this
1174  * function on AGP platform.
1175  */
1176 static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
1177 {
1178         u64 size_bf, size_af;
1179
1180         if (mc->mc_vram_size > 0xE0000000) {
1181                 /* leave room for at least 512M GTT */
1182                 dev_warn(rdev->dev, "limiting VRAM\n");
1183                 mc->real_vram_size = 0xE0000000;
1184                 mc->mc_vram_size = 0xE0000000;
1185         }
1186         if (rdev->flags & RADEON_IS_AGP) {
1187                 size_bf = mc->gtt_start;
1188                 size_af = 0xFFFFFFFF - mc->gtt_end + 1;
1189                 if (size_bf > size_af) {
1190                         if (mc->mc_vram_size > size_bf) {
1191                                 dev_warn(rdev->dev, "limiting VRAM\n");
1192                                 mc->real_vram_size = size_bf;
1193                                 mc->mc_vram_size = size_bf;
1194                         }
1195                         mc->vram_start = mc->gtt_start - mc->mc_vram_size;
1196                 } else {
1197                         if (mc->mc_vram_size > size_af) {
1198                                 dev_warn(rdev->dev, "limiting VRAM\n");
1199                                 mc->real_vram_size = size_af;
1200                                 mc->mc_vram_size = size_af;
1201                         }
1202                         mc->vram_start = mc->gtt_end;
1203                 }
1204                 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
1205                 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
1206                                 mc->mc_vram_size >> 20, mc->vram_start,
1207                                 mc->vram_end, mc->real_vram_size >> 20);
1208         } else {
1209                 u64 base = 0;
1210                 if (rdev->flags & RADEON_IS_IGP) {
1211                         base = RREG32(MC_VM_FB_LOCATION) & 0xFFFF;
1212                         base <<= 24;
1213                 }
1214                 radeon_vram_location(rdev, &rdev->mc, base);
1215                 rdev->mc.gtt_base_align = 0;
1216                 radeon_gtt_location(rdev, mc);
1217         }
1218 }
1219
1220 int r600_mc_init(struct radeon_device *rdev)
1221 {
1222         u32 tmp;
1223         int chansize, numchan;
1224
1225         /* Get VRAM informations */
1226         rdev->mc.vram_is_ddr = true;
1227         tmp = RREG32(RAMCFG);
1228         if (tmp & CHANSIZE_OVERRIDE) {
1229                 chansize = 16;
1230         } else if (tmp & CHANSIZE_MASK) {
1231                 chansize = 64;
1232         } else {
1233                 chansize = 32;
1234         }
1235         tmp = RREG32(CHMAP);
1236         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1237         case 0:
1238         default:
1239                 numchan = 1;
1240                 break;
1241         case 1:
1242                 numchan = 2;
1243                 break;
1244         case 2:
1245                 numchan = 4;
1246                 break;
1247         case 3:
1248                 numchan = 8;
1249                 break;
1250         }
1251         rdev->mc.vram_width = numchan * chansize;
1252         /* Could aper size report 0 ? */
1253         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
1254         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
1255         /* Setup GPU memory space */
1256         rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1257         rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
1258         rdev->mc.visible_vram_size = rdev->mc.aper_size;
1259         rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
1260         r600_vram_gtt_location(rdev, &rdev->mc);
1261
1262         if (rdev->flags & RADEON_IS_IGP) {
1263                 rs690_pm_info(rdev);
1264                 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
1265         }
1266         radeon_update_bandwidth_info(rdev);
1267         return 0;
1268 }
1269
1270 /* We doesn't check that the GPU really needs a reset we simply do the
1271  * reset, it's up to the caller to determine if the GPU needs one. We
1272  * might add an helper function to check that.
1273  */
1274 int r600_gpu_soft_reset(struct radeon_device *rdev)
1275 {
1276         struct rv515_mc_save save;
1277         u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
1278                                 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
1279                                 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
1280                                 S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |
1281                                 S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |
1282                                 S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |
1283                                 S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |
1284                                 S_008010_GUI_ACTIVE(1);
1285         u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
1286                         S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
1287                         S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
1288                         S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
1289                         S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
1290                         S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
1291                         S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
1292                         S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
1293         u32 tmp;
1294
1295         if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
1296                 return 0;
1297
1298         dev_info(rdev->dev, "GPU softreset \n");
1299         dev_info(rdev->dev, "  R_008010_GRBM_STATUS=0x%08X\n",
1300                 RREG32(R_008010_GRBM_STATUS));
1301         dev_info(rdev->dev, "  R_008014_GRBM_STATUS2=0x%08X\n",
1302                 RREG32(R_008014_GRBM_STATUS2));
1303         dev_info(rdev->dev, "  R_000E50_SRBM_STATUS=0x%08X\n",
1304                 RREG32(R_000E50_SRBM_STATUS));
1305         rv515_mc_stop(rdev, &save);
1306         if (r600_mc_wait_for_idle(rdev)) {
1307                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1308         }
1309         /* Disable CP parsing/prefetching */
1310         WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1311         /* Check if any of the rendering block is busy and reset it */
1312         if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
1313             (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
1314                 tmp = S_008020_SOFT_RESET_CR(1) |
1315                         S_008020_SOFT_RESET_DB(1) |
1316                         S_008020_SOFT_RESET_CB(1) |
1317                         S_008020_SOFT_RESET_PA(1) |
1318                         S_008020_SOFT_RESET_SC(1) |
1319                         S_008020_SOFT_RESET_SMX(1) |
1320                         S_008020_SOFT_RESET_SPI(1) |
1321                         S_008020_SOFT_RESET_SX(1) |
1322                         S_008020_SOFT_RESET_SH(1) |
1323                         S_008020_SOFT_RESET_TC(1) |
1324                         S_008020_SOFT_RESET_TA(1) |
1325                         S_008020_SOFT_RESET_VC(1) |
1326                         S_008020_SOFT_RESET_VGT(1);
1327                 dev_info(rdev->dev, "  R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1328                 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1329                 RREG32(R_008020_GRBM_SOFT_RESET);
1330                 mdelay(15);
1331                 WREG32(R_008020_GRBM_SOFT_RESET, 0);
1332         }
1333         /* Reset CP (we always reset CP) */
1334         tmp = S_008020_SOFT_RESET_CP(1);
1335         dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1336         WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1337         RREG32(R_008020_GRBM_SOFT_RESET);
1338         mdelay(15);
1339         WREG32(R_008020_GRBM_SOFT_RESET, 0);
1340         /* Wait a little for things to settle down */
1341         mdelay(1);
1342         dev_info(rdev->dev, "  R_008010_GRBM_STATUS=0x%08X\n",
1343                 RREG32(R_008010_GRBM_STATUS));
1344         dev_info(rdev->dev, "  R_008014_GRBM_STATUS2=0x%08X\n",
1345                 RREG32(R_008014_GRBM_STATUS2));
1346         dev_info(rdev->dev, "  R_000E50_SRBM_STATUS=0x%08X\n",
1347                 RREG32(R_000E50_SRBM_STATUS));
1348         rv515_mc_resume(rdev, &save);
1349         return 0;
1350 }
1351
1352 bool r600_gpu_is_lockup(struct radeon_device *rdev)
1353 {
1354         u32 srbm_status;
1355         u32 grbm_status;
1356         u32 grbm_status2;
1357         struct r100_gpu_lockup *lockup;
1358         int r;
1359
1360         if (rdev->family >= CHIP_RV770)
1361                 lockup = &rdev->config.rv770.lockup;
1362         else
1363                 lockup = &rdev->config.r600.lockup;
1364
1365         srbm_status = RREG32(R_000E50_SRBM_STATUS);
1366         grbm_status = RREG32(R_008010_GRBM_STATUS);
1367         grbm_status2 = RREG32(R_008014_GRBM_STATUS2);
1368         if (!G_008010_GUI_ACTIVE(grbm_status)) {
1369                 r100_gpu_lockup_update(lockup, &rdev->cp);
1370                 return false;
1371         }
1372         /* force CP activities */
1373         r = radeon_ring_lock(rdev, 2);
1374         if (!r) {
1375                 /* PACKET2 NOP */
1376                 radeon_ring_write(rdev, 0x80000000);
1377                 radeon_ring_write(rdev, 0x80000000);
1378                 radeon_ring_unlock_commit(rdev);
1379         }
1380         rdev->cp.rptr = RREG32(R600_CP_RB_RPTR);
1381         return r100_gpu_cp_is_lockup(rdev, lockup, &rdev->cp);
1382 }
1383
1384 int r600_asic_reset(struct radeon_device *rdev)
1385 {
1386         return r600_gpu_soft_reset(rdev);
1387 }
1388
1389 static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
1390                                              u32 num_backends,
1391                                              u32 backend_disable_mask)
1392 {
1393         u32 backend_map = 0;
1394         u32 enabled_backends_mask;
1395         u32 enabled_backends_count;
1396         u32 cur_pipe;
1397         u32 swizzle_pipe[R6XX_MAX_PIPES];
1398         u32 cur_backend;
1399         u32 i;
1400
1401         if (num_tile_pipes > R6XX_MAX_PIPES)
1402                 num_tile_pipes = R6XX_MAX_PIPES;
1403         if (num_tile_pipes < 1)
1404                 num_tile_pipes = 1;
1405         if (num_backends > R6XX_MAX_BACKENDS)
1406                 num_backends = R6XX_MAX_BACKENDS;
1407         if (num_backends < 1)
1408                 num_backends = 1;
1409
1410         enabled_backends_mask = 0;
1411         enabled_backends_count = 0;
1412         for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
1413                 if (((backend_disable_mask >> i) & 1) == 0) {
1414                         enabled_backends_mask |= (1 << i);
1415                         ++enabled_backends_count;
1416                 }
1417                 if (enabled_backends_count == num_backends)
1418                         break;
1419         }
1420
1421         if (enabled_backends_count == 0) {
1422                 enabled_backends_mask = 1;
1423                 enabled_backends_count = 1;
1424         }
1425
1426         if (enabled_backends_count != num_backends)
1427                 num_backends = enabled_backends_count;
1428
1429         memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
1430         switch (num_tile_pipes) {
1431         case 1:
1432                 swizzle_pipe[0] = 0;
1433                 break;
1434         case 2:
1435                 swizzle_pipe[0] = 0;
1436                 swizzle_pipe[1] = 1;
1437                 break;
1438         case 3:
1439                 swizzle_pipe[0] = 0;
1440                 swizzle_pipe[1] = 1;
1441                 swizzle_pipe[2] = 2;
1442                 break;
1443         case 4:
1444                 swizzle_pipe[0] = 0;
1445                 swizzle_pipe[1] = 1;
1446                 swizzle_pipe[2] = 2;
1447                 swizzle_pipe[3] = 3;
1448                 break;
1449         case 5:
1450                 swizzle_pipe[0] = 0;
1451                 swizzle_pipe[1] = 1;
1452                 swizzle_pipe[2] = 2;
1453                 swizzle_pipe[3] = 3;
1454                 swizzle_pipe[4] = 4;
1455                 break;
1456         case 6:
1457                 swizzle_pipe[0] = 0;
1458                 swizzle_pipe[1] = 2;
1459                 swizzle_pipe[2] = 4;
1460                 swizzle_pipe[3] = 5;
1461                 swizzle_pipe[4] = 1;
1462                 swizzle_pipe[5] = 3;
1463                 break;
1464         case 7:
1465                 swizzle_pipe[0] = 0;
1466                 swizzle_pipe[1] = 2;
1467                 swizzle_pipe[2] = 4;
1468                 swizzle_pipe[3] = 6;
1469                 swizzle_pipe[4] = 1;
1470                 swizzle_pipe[5] = 3;
1471                 swizzle_pipe[6] = 5;
1472                 break;
1473         case 8:
1474                 swizzle_pipe[0] = 0;
1475                 swizzle_pipe[1] = 2;
1476                 swizzle_pipe[2] = 4;
1477                 swizzle_pipe[3] = 6;
1478                 swizzle_pipe[4] = 1;
1479                 swizzle_pipe[5] = 3;
1480                 swizzle_pipe[6] = 5;
1481                 swizzle_pipe[7] = 7;
1482                 break;
1483         }
1484
1485         cur_backend = 0;
1486         for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1487                 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1488                         cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
1489
1490                 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
1491
1492                 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
1493         }
1494
1495         return backend_map;
1496 }
1497
1498 int r600_count_pipe_bits(uint32_t val)
1499 {
1500         int i, ret = 0;
1501
1502         for (i = 0; i < 32; i++) {
1503                 ret += val & 1;
1504                 val >>= 1;
1505         }
1506         return ret;
1507 }
1508
1509 void r600_gpu_init(struct radeon_device *rdev)
1510 {
1511         u32 tiling_config;
1512         u32 ramcfg;
1513         u32 backend_map;
1514         u32 cc_rb_backend_disable;
1515         u32 cc_gc_shader_pipe_config;
1516         u32 tmp;
1517         int i, j;
1518         u32 sq_config;
1519         u32 sq_gpr_resource_mgmt_1 = 0;
1520         u32 sq_gpr_resource_mgmt_2 = 0;
1521         u32 sq_thread_resource_mgmt = 0;
1522         u32 sq_stack_resource_mgmt_1 = 0;
1523         u32 sq_stack_resource_mgmt_2 = 0;
1524
1525         /* FIXME: implement */
1526         switch (rdev->family) {
1527         case CHIP_R600:
1528                 rdev->config.r600.max_pipes = 4;
1529                 rdev->config.r600.max_tile_pipes = 8;
1530                 rdev->config.r600.max_simds = 4;
1531                 rdev->config.r600.max_backends = 4;
1532                 rdev->config.r600.max_gprs = 256;
1533                 rdev->config.r600.max_threads = 192;
1534                 rdev->config.r600.max_stack_entries = 256;
1535                 rdev->config.r600.max_hw_contexts = 8;
1536                 rdev->config.r600.max_gs_threads = 16;
1537                 rdev->config.r600.sx_max_export_size = 128;
1538                 rdev->config.r600.sx_max_export_pos_size = 16;
1539                 rdev->config.r600.sx_max_export_smx_size = 128;
1540                 rdev->config.r600.sq_num_cf_insts = 2;
1541                 break;
1542         case CHIP_RV630:
1543         case CHIP_RV635:
1544                 rdev->config.r600.max_pipes = 2;
1545                 rdev->config.r600.max_tile_pipes = 2;
1546                 rdev->config.r600.max_simds = 3;
1547                 rdev->config.r600.max_backends = 1;
1548                 rdev->config.r600.max_gprs = 128;
1549                 rdev->config.r600.max_threads = 192;
1550                 rdev->config.r600.max_stack_entries = 128;
1551                 rdev->config.r600.max_hw_contexts = 8;
1552                 rdev->config.r600.max_gs_threads = 4;
1553                 rdev->config.r600.sx_max_export_size = 128;
1554                 rdev->config.r600.sx_max_export_pos_size = 16;
1555                 rdev->config.r600.sx_max_export_smx_size = 128;
1556                 rdev->config.r600.sq_num_cf_insts = 2;
1557                 break;
1558         case CHIP_RV610:
1559         case CHIP_RV620:
1560         case CHIP_RS780:
1561         case CHIP_RS880:
1562                 rdev->config.r600.max_pipes = 1;
1563                 rdev->config.r600.max_tile_pipes = 1;
1564                 rdev->config.r600.max_simds = 2;
1565                 rdev->config.r600.max_backends = 1;
1566                 rdev->config.r600.max_gprs = 128;
1567                 rdev->config.r600.max_threads = 192;
1568                 rdev->config.r600.max_stack_entries = 128;
1569                 rdev->config.r600.max_hw_contexts = 4;
1570                 rdev->config.r600.max_gs_threads = 4;
1571                 rdev->config.r600.sx_max_export_size = 128;
1572                 rdev->config.r600.sx_max_export_pos_size = 16;
1573                 rdev->config.r600.sx_max_export_smx_size = 128;
1574                 rdev->config.r600.sq_num_cf_insts = 1;
1575                 break;
1576         case CHIP_RV670:
1577                 rdev->config.r600.max_pipes = 4;
1578                 rdev->config.r600.max_tile_pipes = 4;
1579                 rdev->config.r600.max_simds = 4;
1580                 rdev->config.r600.max_backends = 4;
1581                 rdev->config.r600.max_gprs = 192;
1582                 rdev->config.r600.max_threads = 192;
1583                 rdev->config.r600.max_stack_entries = 256;
1584                 rdev->config.r600.max_hw_contexts = 8;
1585                 rdev->config.r600.max_gs_threads = 16;
1586                 rdev->config.r600.sx_max_export_size = 128;
1587                 rdev->config.r600.sx_max_export_pos_size = 16;
1588                 rdev->config.r600.sx_max_export_smx_size = 128;
1589                 rdev->config.r600.sq_num_cf_insts = 2;
1590                 break;
1591         default:
1592                 break;
1593         }
1594
1595         /* Initialize HDP */
1596         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1597                 WREG32((0x2c14 + j), 0x00000000);
1598                 WREG32((0x2c18 + j), 0x00000000);
1599                 WREG32((0x2c1c + j), 0x00000000);
1600                 WREG32((0x2c20 + j), 0x00000000);
1601                 WREG32((0x2c24 + j), 0x00000000);
1602         }
1603
1604         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1605
1606         /* Setup tiling */
1607         tiling_config = 0;
1608         ramcfg = RREG32(RAMCFG);
1609         switch (rdev->config.r600.max_tile_pipes) {
1610         case 1:
1611                 tiling_config |= PIPE_TILING(0);
1612                 break;
1613         case 2:
1614                 tiling_config |= PIPE_TILING(1);
1615                 break;
1616         case 4:
1617                 tiling_config |= PIPE_TILING(2);
1618                 break;
1619         case 8:
1620                 tiling_config |= PIPE_TILING(3);
1621                 break;
1622         default:
1623                 break;
1624         }
1625         rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes;
1626         rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1627         tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1628         tiling_config |= GROUP_SIZE((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
1629         if ((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT)
1630                 rdev->config.r600.tiling_group_size = 512;
1631         else
1632                 rdev->config.r600.tiling_group_size = 256;
1633         tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
1634         if (tmp > 3) {
1635                 tiling_config |= ROW_TILING(3);
1636                 tiling_config |= SAMPLE_SPLIT(3);
1637         } else {
1638                 tiling_config |= ROW_TILING(tmp);
1639                 tiling_config |= SAMPLE_SPLIT(tmp);
1640         }
1641         tiling_config |= BANK_SWAPS(1);
1642
1643         cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
1644         cc_rb_backend_disable |=
1645                 BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK);
1646
1647         cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
1648         cc_gc_shader_pipe_config |=
1649                 INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK);
1650         cc_gc_shader_pipe_config |=
1651                 INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK);
1652
1653         backend_map = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes,
1654                                                         (R6XX_MAX_BACKENDS -
1655                                                          r600_count_pipe_bits((cc_rb_backend_disable &
1656                                                                                R6XX_MAX_BACKENDS_MASK) >> 16)),
1657                                                         (cc_rb_backend_disable >> 16));
1658         rdev->config.r600.tile_config = tiling_config;
1659         tiling_config |= BACKEND_MAP(backend_map);
1660         WREG32(GB_TILING_CONFIG, tiling_config);
1661         WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
1662         WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
1663
1664         /* Setup pipes */
1665         WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1666         WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1667         WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1668
1669         tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
1670         WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
1671         WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
1672
1673         /* Setup some CP states */
1674         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
1675         WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
1676
1677         WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
1678                              SYNC_WALKER | SYNC_ALIGNER));
1679         /* Setup various GPU states */
1680         if (rdev->family == CHIP_RV670)
1681                 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
1682
1683         tmp = RREG32(SX_DEBUG_1);
1684         tmp |= SMX_EVENT_RELEASE;
1685         if ((rdev->family > CHIP_R600))
1686                 tmp |= ENABLE_NEW_SMX_ADDRESS;
1687         WREG32(SX_DEBUG_1, tmp);
1688
1689         if (((rdev->family) == CHIP_R600) ||
1690             ((rdev->family) == CHIP_RV630) ||
1691             ((rdev->family) == CHIP_RV610) ||
1692             ((rdev->family) == CHIP_RV620) ||
1693             ((rdev->family) == CHIP_RS780) ||
1694             ((rdev->family) == CHIP_RS880)) {
1695                 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
1696         } else {
1697                 WREG32(DB_DEBUG, 0);
1698         }
1699         WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
1700                                DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
1701
1702         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1703         WREG32(VGT_NUM_INSTANCES, 0);
1704
1705         WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
1706         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
1707
1708         tmp = RREG32(SQ_MS_FIFO_SIZES);
1709         if (((rdev->family) == CHIP_RV610) ||
1710             ((rdev->family) == CHIP_RV620) ||
1711             ((rdev->family) == CHIP_RS780) ||
1712             ((rdev->family) == CHIP_RS880)) {
1713                 tmp = (CACHE_FIFO_SIZE(0xa) |
1714                        FETCH_FIFO_HIWATER(0xa) |
1715                        DONE_FIFO_HIWATER(0xe0) |
1716                        ALU_UPDATE_FIFO_HIWATER(0x8));
1717         } else if (((rdev->family) == CHIP_R600) ||
1718                    ((rdev->family) == CHIP_RV630)) {
1719                 tmp &= ~DONE_FIFO_HIWATER(0xff);
1720                 tmp |= DONE_FIFO_HIWATER(0x4);
1721         }
1722         WREG32(SQ_MS_FIFO_SIZES, tmp);
1723
1724         /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1725          * should be adjusted as needed by the 2D/3D drivers.  This just sets default values
1726          */
1727         sq_config = RREG32(SQ_CONFIG);
1728         sq_config &= ~(PS_PRIO(3) |
1729                        VS_PRIO(3) |
1730                        GS_PRIO(3) |
1731                        ES_PRIO(3));
1732         sq_config |= (DX9_CONSTS |
1733                       VC_ENABLE |
1734                       PS_PRIO(0) |
1735                       VS_PRIO(1) |
1736                       GS_PRIO(2) |
1737                       ES_PRIO(3));
1738
1739         if ((rdev->family) == CHIP_R600) {
1740                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
1741                                           NUM_VS_GPRS(124) |
1742                                           NUM_CLAUSE_TEMP_GPRS(4));
1743                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
1744                                           NUM_ES_GPRS(0));
1745                 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
1746                                            NUM_VS_THREADS(48) |
1747                                            NUM_GS_THREADS(4) |
1748                                            NUM_ES_THREADS(4));
1749                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
1750                                             NUM_VS_STACK_ENTRIES(128));
1751                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
1752                                             NUM_ES_STACK_ENTRIES(0));
1753         } else if (((rdev->family) == CHIP_RV610) ||
1754                    ((rdev->family) == CHIP_RV620) ||
1755                    ((rdev->family) == CHIP_RS780) ||
1756                    ((rdev->family) == CHIP_RS880)) {
1757                 /* no vertex cache */
1758                 sq_config &= ~VC_ENABLE;
1759
1760                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1761                                           NUM_VS_GPRS(44) |
1762                                           NUM_CLAUSE_TEMP_GPRS(2));
1763                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1764                                           NUM_ES_GPRS(17));
1765                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1766                                            NUM_VS_THREADS(78) |
1767                                            NUM_GS_THREADS(4) |
1768                                            NUM_ES_THREADS(31));
1769                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1770                                             NUM_VS_STACK_ENTRIES(40));
1771                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1772                                             NUM_ES_STACK_ENTRIES(16));
1773         } else if (((rdev->family) == CHIP_RV630) ||
1774                    ((rdev->family) == CHIP_RV635)) {
1775                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1776                                           NUM_VS_GPRS(44) |
1777                                           NUM_CLAUSE_TEMP_GPRS(2));
1778                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
1779                                           NUM_ES_GPRS(18));
1780                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1781                                            NUM_VS_THREADS(78) |
1782                                            NUM_GS_THREADS(4) |
1783                                            NUM_ES_THREADS(31));
1784                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1785                                             NUM_VS_STACK_ENTRIES(40));
1786                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1787                                             NUM_ES_STACK_ENTRIES(16));
1788         } else if ((rdev->family) == CHIP_RV670) {
1789                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1790                                           NUM_VS_GPRS(44) |
1791                                           NUM_CLAUSE_TEMP_GPRS(2));
1792                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1793                                           NUM_ES_GPRS(17));
1794                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1795                                            NUM_VS_THREADS(78) |
1796                                            NUM_GS_THREADS(4) |
1797                                            NUM_ES_THREADS(31));
1798                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
1799                                             NUM_VS_STACK_ENTRIES(64));
1800                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
1801                                             NUM_ES_STACK_ENTRIES(64));
1802         }
1803
1804         WREG32(SQ_CONFIG, sq_config);
1805         WREG32(SQ_GPR_RESOURCE_MGMT_1,  sq_gpr_resource_mgmt_1);
1806         WREG32(SQ_GPR_RESOURCE_MGMT_2,  sq_gpr_resource_mgmt_2);
1807         WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1808         WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1809         WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1810
1811         if (((rdev->family) == CHIP_RV610) ||
1812             ((rdev->family) == CHIP_RV620) ||
1813             ((rdev->family) == CHIP_RS780) ||
1814             ((rdev->family) == CHIP_RS880)) {
1815                 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
1816         } else {
1817                 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
1818         }
1819
1820         /* More default values. 2D/3D driver should adjust as needed */
1821         WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
1822                                          S1_X(0x4) | S1_Y(0xc)));
1823         WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
1824                                          S1_X(0x2) | S1_Y(0x2) |
1825                                          S2_X(0xa) | S2_Y(0x6) |
1826                                          S3_X(0x6) | S3_Y(0xa)));
1827         WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
1828                                              S1_X(0x4) | S1_Y(0xc) |
1829                                              S2_X(0x1) | S2_Y(0x6) |
1830                                              S3_X(0xa) | S3_Y(0xe)));
1831         WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
1832                                              S5_X(0x0) | S5_Y(0x0) |
1833                                              S6_X(0xb) | S6_Y(0x4) |
1834                                              S7_X(0x7) | S7_Y(0x8)));
1835
1836         WREG32(VGT_STRMOUT_EN, 0);
1837         tmp = rdev->config.r600.max_pipes * 16;
1838         switch (rdev->family) {
1839         case CHIP_RV610:
1840         case CHIP_RV620:
1841         case CHIP_RS780:
1842         case CHIP_RS880:
1843                 tmp += 32;
1844                 break;
1845         case CHIP_RV670:
1846                 tmp += 128;
1847                 break;
1848         default:
1849                 break;
1850         }
1851         if (tmp > 256) {
1852                 tmp = 256;
1853         }
1854         WREG32(VGT_ES_PER_GS, 128);
1855         WREG32(VGT_GS_PER_ES, tmp);
1856         WREG32(VGT_GS_PER_VS, 2);
1857         WREG32(VGT_GS_VERTEX_REUSE, 16);
1858
1859         /* more default values. 2D/3D driver should adjust as needed */
1860         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1861         WREG32(VGT_STRMOUT_EN, 0);
1862         WREG32(SX_MISC, 0);
1863         WREG32(PA_SC_MODE_CNTL, 0);
1864         WREG32(PA_SC_AA_CONFIG, 0);
1865         WREG32(PA_SC_LINE_STIPPLE, 0);
1866         WREG32(SPI_INPUT_Z, 0);
1867         WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
1868         WREG32(CB_COLOR7_FRAG, 0);
1869
1870         /* Clear render buffer base addresses */
1871         WREG32(CB_COLOR0_BASE, 0);
1872         WREG32(CB_COLOR1_BASE, 0);
1873         WREG32(CB_COLOR2_BASE, 0);
1874         WREG32(CB_COLOR3_BASE, 0);
1875         WREG32(CB_COLOR4_BASE, 0);
1876         WREG32(CB_COLOR5_BASE, 0);
1877         WREG32(CB_COLOR6_BASE, 0);
1878         WREG32(CB_COLOR7_BASE, 0);
1879         WREG32(CB_COLOR7_FRAG, 0);
1880
1881         switch (rdev->family) {
1882         case CHIP_RV610:
1883         case CHIP_RV620:
1884         case CHIP_RS780:
1885         case CHIP_RS880:
1886                 tmp = TC_L2_SIZE(8);
1887                 break;
1888         case CHIP_RV630:
1889         case CHIP_RV635:
1890                 tmp = TC_L2_SIZE(4);
1891                 break;
1892         case CHIP_R600:
1893                 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
1894                 break;
1895         default:
1896                 tmp = TC_L2_SIZE(0);
1897                 break;
1898         }
1899         WREG32(TC_CNTL, tmp);
1900
1901         tmp = RREG32(HDP_HOST_PATH_CNTL);
1902         WREG32(HDP_HOST_PATH_CNTL, tmp);
1903
1904         tmp = RREG32(ARB_POP);
1905         tmp |= ENABLE_TC128;
1906         WREG32(ARB_POP, tmp);
1907
1908         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1909         WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
1910                                NUM_CLIP_SEQ(3)));
1911         WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
1912 }
1913
1914
1915 /*
1916  * Indirect registers accessor
1917  */
1918 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
1919 {
1920         u32 r;
1921
1922         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1923         (void)RREG32(PCIE_PORT_INDEX);
1924         r = RREG32(PCIE_PORT_DATA);
1925         return r;
1926 }
1927
1928 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1929 {
1930         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1931         (void)RREG32(PCIE_PORT_INDEX);
1932         WREG32(PCIE_PORT_DATA, (v));
1933         (void)RREG32(PCIE_PORT_DATA);
1934 }
1935
1936 /*
1937  * CP & Ring
1938  */
1939 void r600_cp_stop(struct radeon_device *rdev)
1940 {
1941         rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
1942         WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1943         WREG32(SCRATCH_UMSK, 0);
1944 }
1945
1946 int r600_init_microcode(struct radeon_device *rdev)
1947 {
1948         struct platform_device *pdev;
1949         const char *chip_name;
1950         const char *rlc_chip_name;
1951         size_t pfp_req_size, me_req_size, rlc_req_size;
1952         char fw_name[30];
1953         int err;
1954
1955         DRM_DEBUG("\n");
1956
1957         pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
1958         err = IS_ERR(pdev);
1959         if (err) {
1960                 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
1961                 return -EINVAL;
1962         }
1963
1964         switch (rdev->family) {
1965         case CHIP_R600:
1966                 chip_name = "R600";
1967                 rlc_chip_name = "R600";
1968                 break;
1969         case CHIP_RV610:
1970                 chip_name = "RV610";
1971                 rlc_chip_name = "R600";
1972                 break;
1973         case CHIP_RV630:
1974                 chip_name = "RV630";
1975                 rlc_chip_name = "R600";
1976                 break;
1977         case CHIP_RV620:
1978                 chip_name = "RV620";
1979                 rlc_chip_name = "R600";
1980                 break;
1981         case CHIP_RV635:
1982                 chip_name = "RV635";
1983                 rlc_chip_name = "R600";
1984                 break;
1985         case CHIP_RV670:
1986                 chip_name = "RV670";
1987                 rlc_chip_name = "R600";
1988                 break;
1989         case CHIP_RS780:
1990         case CHIP_RS880:
1991                 chip_name = "RS780";
1992                 rlc_chip_name = "R600";
1993                 break;
1994         case CHIP_RV770:
1995                 chip_name = "RV770";
1996                 rlc_chip_name = "R700";
1997                 break;
1998         case CHIP_RV730:
1999         case CHIP_RV740:
2000                 chip_name = "RV730";
2001                 rlc_chip_name = "R700";
2002                 break;
2003         case CHIP_RV710:
2004                 chip_name = "RV710";
2005                 rlc_chip_name = "R700";
2006                 break;
2007         case CHIP_CEDAR:
2008                 chip_name = "CEDAR";
2009                 rlc_chip_name = "CEDAR";
2010                 break;
2011         case CHIP_REDWOOD:
2012                 chip_name = "REDWOOD";
2013                 rlc_chip_name = "REDWOOD";
2014                 break;
2015         case CHIP_JUNIPER:
2016                 chip_name = "JUNIPER";
2017                 rlc_chip_name = "JUNIPER";
2018                 break;
2019         case CHIP_CYPRESS:
2020         case CHIP_HEMLOCK:
2021                 chip_name = "CYPRESS";
2022                 rlc_chip_name = "CYPRESS";
2023                 break;
2024         case CHIP_PALM:
2025                 chip_name = "PALM";
2026                 rlc_chip_name = "SUMO";
2027                 break;
2028         default: BUG();
2029         }
2030
2031         if (rdev->family >= CHIP_CEDAR) {
2032                 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
2033                 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
2034                 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
2035         } else if (rdev->family >= CHIP_RV770) {
2036                 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
2037                 me_req_size = R700_PM4_UCODE_SIZE * 4;
2038                 rlc_req_size = R700_RLC_UCODE_SIZE * 4;
2039         } else {
2040                 pfp_req_size = PFP_UCODE_SIZE * 4;
2041                 me_req_size = PM4_UCODE_SIZE * 12;
2042                 rlc_req_size = RLC_UCODE_SIZE * 4;
2043         }
2044
2045         DRM_INFO("Loading %s Microcode\n", chip_name);
2046
2047         snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
2048         err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
2049         if (err)
2050                 goto out;
2051         if (rdev->pfp_fw->size != pfp_req_size) {
2052                 printk(KERN_ERR
2053                        "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2054                        rdev->pfp_fw->size, fw_name);
2055                 err = -EINVAL;
2056                 goto out;
2057         }
2058
2059         snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
2060         err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
2061         if (err)
2062                 goto out;
2063         if (rdev->me_fw->size != me_req_size) {
2064                 printk(KERN_ERR
2065                        "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2066                        rdev->me_fw->size, fw_name);
2067                 err = -EINVAL;
2068         }
2069
2070         snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
2071         err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
2072         if (err)
2073                 goto out;
2074         if (rdev->rlc_fw->size != rlc_req_size) {
2075                 printk(KERN_ERR
2076                        "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
2077                        rdev->rlc_fw->size, fw_name);
2078                 err = -EINVAL;
2079         }
2080
2081 out:
2082         platform_device_unregister(pdev);
2083
2084         if (err) {
2085                 if (err != -EINVAL)
2086                         printk(KERN_ERR
2087                                "r600_cp: Failed to load firmware \"%s\"\n",
2088                                fw_name);
2089                 release_firmware(rdev->pfp_fw);
2090                 rdev->pfp_fw = NULL;
2091                 release_firmware(rdev->me_fw);
2092                 rdev->me_fw = NULL;
2093                 release_firmware(rdev->rlc_fw);
2094                 rdev->rlc_fw = NULL;
2095         }
2096         return err;
2097 }
2098
2099 static int r600_cp_load_microcode(struct radeon_device *rdev)
2100 {
2101         const __be32 *fw_data;
2102         int i;
2103
2104         if (!rdev->me_fw || !rdev->pfp_fw)
2105                 return -EINVAL;
2106
2107         r600_cp_stop(rdev);
2108
2109         WREG32(CP_RB_CNTL, RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
2110
2111         /* Reset cp */
2112         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2113         RREG32(GRBM_SOFT_RESET);
2114         mdelay(15);
2115         WREG32(GRBM_SOFT_RESET, 0);
2116
2117         WREG32(CP_ME_RAM_WADDR, 0);
2118
2119         fw_data = (const __be32 *)rdev->me_fw->data;
2120         WREG32(CP_ME_RAM_WADDR, 0);
2121         for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
2122                 WREG32(CP_ME_RAM_DATA,
2123                        be32_to_cpup(fw_data++));
2124
2125         fw_data = (const __be32 *)rdev->pfp_fw->data;
2126         WREG32(CP_PFP_UCODE_ADDR, 0);
2127         for (i = 0; i < PFP_UCODE_SIZE; i++)
2128                 WREG32(CP_PFP_UCODE_DATA,
2129                        be32_to_cpup(fw_data++));
2130
2131         WREG32(CP_PFP_UCODE_ADDR, 0);
2132         WREG32(CP_ME_RAM_WADDR, 0);
2133         WREG32(CP_ME_RAM_RADDR, 0);
2134         return 0;
2135 }
2136
2137 int r600_cp_start(struct radeon_device *rdev)
2138 {
2139         int r;
2140         uint32_t cp_me;
2141
2142         r = radeon_ring_lock(rdev, 7);
2143         if (r) {
2144                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2145                 return r;
2146         }
2147         radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
2148         radeon_ring_write(rdev, 0x1);
2149         if (rdev->family >= CHIP_RV770) {
2150                 radeon_ring_write(rdev, 0x0);
2151                 radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1);
2152         } else {
2153                 radeon_ring_write(rdev, 0x3);
2154                 radeon_ring_write(rdev, rdev->config.r600.max_hw_contexts - 1);
2155         }
2156         radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2157         radeon_ring_write(rdev, 0);
2158         radeon_ring_write(rdev, 0);
2159         radeon_ring_unlock_commit(rdev);
2160
2161         cp_me = 0xff;
2162         WREG32(R_0086D8_CP_ME_CNTL, cp_me);
2163         return 0;
2164 }
2165
2166 int r600_cp_resume(struct radeon_device *rdev)
2167 {
2168         u32 tmp;
2169         u32 rb_bufsz;
2170         int r;
2171
2172         /* Reset cp */
2173         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2174         RREG32(GRBM_SOFT_RESET);
2175         mdelay(15);
2176         WREG32(GRBM_SOFT_RESET, 0);
2177
2178         /* Set ring buffer size */
2179         rb_bufsz = drm_order(rdev->cp.ring_size / 8);
2180         tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2181 #ifdef __BIG_ENDIAN
2182         tmp |= BUF_SWAP_32BIT;
2183 #endif
2184         WREG32(CP_RB_CNTL, tmp);
2185         WREG32(CP_SEM_WAIT_TIMER, 0x4);
2186
2187         /* Set the write pointer delay */
2188         WREG32(CP_RB_WPTR_DELAY, 0);
2189
2190         /* Initialize the ring buffer's read and write pointers */
2191         WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
2192         WREG32(CP_RB_RPTR_WR, 0);
2193         WREG32(CP_RB_WPTR, 0);
2194
2195         /* set the wb address whether it's enabled or not */
2196         WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);
2197         WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
2198         WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
2199
2200         if (rdev->wb.enabled)
2201                 WREG32(SCRATCH_UMSK, 0xff);
2202         else {
2203                 tmp |= RB_NO_UPDATE;
2204                 WREG32(SCRATCH_UMSK, 0);
2205         }
2206
2207         mdelay(1);
2208         WREG32(CP_RB_CNTL, tmp);
2209
2210         WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
2211         WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
2212
2213         rdev->cp.rptr = RREG32(CP_RB_RPTR);
2214         rdev->cp.wptr = RREG32(CP_RB_WPTR);
2215
2216         r600_cp_start(rdev);
2217         rdev->cp.ready = true;
2218         r = radeon_ring_test(rdev);
2219         if (r) {
2220                 rdev->cp.ready = false;
2221                 return r;
2222         }
2223         return 0;
2224 }
2225
2226 void r600_cp_commit(struct radeon_device *rdev)
2227 {
2228         WREG32(CP_RB_WPTR, rdev->cp.wptr);
2229         (void)RREG32(CP_RB_WPTR);
2230 }
2231
2232 void r600_ring_init(struct radeon_device *rdev, unsigned ring_size)
2233 {
2234         u32 rb_bufsz;
2235
2236         /* Align ring size */
2237         rb_bufsz = drm_order(ring_size / 8);
2238         ring_size = (1 << (rb_bufsz + 1)) * 4;
2239         rdev->cp.ring_size = ring_size;
2240         rdev->cp.align_mask = 16 - 1;
2241 }
2242
2243 void r600_cp_fini(struct radeon_device *rdev)
2244 {
2245         r600_cp_stop(rdev);
2246         radeon_ring_fini(rdev);
2247 }
2248
2249
2250 /*
2251  * GPU scratch registers helpers function.
2252  */
2253 void r600_scratch_init(struct radeon_device *rdev)
2254 {
2255         int i;
2256
2257         rdev->scratch.num_reg = 7;
2258         rdev->scratch.reg_base = SCRATCH_REG0;
2259         for (i = 0; i < rdev->scratch.num_reg; i++) {
2260                 rdev->scratch.free[i] = true;
2261                 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
2262         }
2263 }
2264
2265 int r600_ring_test(struct radeon_device *rdev)
2266 {
2267         uint32_t scratch;
2268         uint32_t tmp = 0;
2269         unsigned i;
2270         int r;
2271
2272         r = radeon_scratch_get(rdev, &scratch);
2273         if (r) {
2274                 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
2275                 return r;
2276         }
2277         WREG32(scratch, 0xCAFEDEAD);
2278         r = radeon_ring_lock(rdev, 3);
2279         if (r) {
2280                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2281                 radeon_scratch_free(rdev, scratch);
2282                 return r;
2283         }
2284         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2285         radeon_ring_write(rdev, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2286         radeon_ring_write(rdev, 0xDEADBEEF);
2287         radeon_ring_unlock_commit(rdev);
2288         for (i = 0; i < rdev->usec_timeout; i++) {
2289                 tmp = RREG32(scratch);
2290                 if (tmp == 0xDEADBEEF)
2291                         break;
2292                 DRM_UDELAY(1);
2293         }
2294         if (i < rdev->usec_timeout) {
2295                 DRM_INFO("ring test succeeded in %d usecs\n", i);
2296         } else {
2297                 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
2298                           scratch, tmp);
2299                 r = -EINVAL;
2300         }
2301         radeon_scratch_free(rdev, scratch);
2302         return r;
2303 }
2304
2305 void r600_fence_ring_emit(struct radeon_device *rdev,
2306                           struct radeon_fence *fence)
2307 {
2308         if (rdev->wb.use_event) {
2309                 u64 addr = rdev->wb.gpu_addr + R600_WB_EVENT_OFFSET +
2310                         (u64)(rdev->fence_drv.scratch_reg - rdev->scratch.reg_base);
2311                 /* EVENT_WRITE_EOP - flush caches, send int */
2312                 radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2313                 radeon_ring_write(rdev, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
2314                 radeon_ring_write(rdev, addr & 0xffffffff);
2315                 radeon_ring_write(rdev, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
2316                 radeon_ring_write(rdev, fence->seq);
2317                 radeon_ring_write(rdev, 0);
2318         } else {
2319                 radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0));
2320                 radeon_ring_write(rdev, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0));
2321                 /* wait for 3D idle clean */
2322                 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2323                 radeon_ring_write(rdev, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2324                 radeon_ring_write(rdev, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
2325                 /* Emit fence sequence & fire IRQ */
2326                 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2327                 radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2328                 radeon_ring_write(rdev, fence->seq);
2329                 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
2330                 radeon_ring_write(rdev, PACKET0(CP_INT_STATUS, 0));
2331                 radeon_ring_write(rdev, RB_INT_STAT);
2332         }
2333 }
2334
2335 int r600_copy_blit(struct radeon_device *rdev,
2336                    uint64_t src_offset, uint64_t dst_offset,
2337                    unsigned num_pages, struct radeon_fence *fence)
2338 {
2339         int r;
2340
2341         mutex_lock(&rdev->r600_blit.mutex);
2342         rdev->r600_blit.vb_ib = NULL;
2343         r = r600_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE);
2344         if (r) {
2345                 if (rdev->r600_blit.vb_ib)
2346                         radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
2347                 mutex_unlock(&rdev->r600_blit.mutex);
2348                 return r;
2349         }
2350         r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE);
2351         r600_blit_done_copy(rdev, fence);
2352         mutex_unlock(&rdev->r600_blit.mutex);
2353         return 0;
2354 }
2355
2356 int r600_set_surface_reg(struct radeon_device *rdev, int reg,
2357                          uint32_t tiling_flags, uint32_t pitch,
2358                          uint32_t offset, uint32_t obj_size)
2359 {
2360         /* FIXME: implement */
2361         return 0;
2362 }
2363
2364 void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
2365 {
2366         /* FIXME: implement */
2367 }
2368
2369 int r600_startup(struct radeon_device *rdev)
2370 {
2371         int r;
2372
2373         /* enable pcie gen2 link */
2374         r600_pcie_gen2_enable(rdev);
2375
2376         if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
2377                 r = r600_init_microcode(rdev);
2378                 if (r) {
2379                         DRM_ERROR("Failed to load firmware!\n");
2380                         return r;
2381                 }
2382         }
2383
2384         r600_mc_program(rdev);
2385         if (rdev->flags & RADEON_IS_AGP) {
2386                 r600_agp_enable(rdev);
2387         } else {
2388                 r = r600_pcie_gart_enable(rdev);
2389                 if (r)
2390                         return r;
2391         }
2392         r600_gpu_init(rdev);
2393         r = r600_blit_init(rdev);
2394         if (r) {
2395                 r600_blit_fini(rdev);
2396                 rdev->asic->copy = NULL;
2397                 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
2398         }
2399
2400         /* allocate wb buffer */
2401         r = radeon_wb_init(rdev);
2402         if (r)
2403                 return r;
2404
2405         /* Enable IRQ */
2406         r = r600_irq_init(rdev);
2407         if (r) {
2408                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
2409                 radeon_irq_kms_fini(rdev);
2410                 return r;
2411         }
2412         r600_irq_set(rdev);
2413
2414         r = radeon_ring_init(rdev, rdev->cp.ring_size);
2415         if (r)
2416                 return r;
2417         r = r600_cp_load_microcode(rdev);
2418         if (r)
2419                 return r;
2420         r = r600_cp_resume(rdev);
2421         if (r)
2422                 return r;
2423
2424         return 0;
2425 }
2426
2427 void r600_vga_set_state(struct radeon_device *rdev, bool state)
2428 {
2429         uint32_t temp;
2430
2431         temp = RREG32(CONFIG_CNTL);
2432         if (state == false) {
2433                 temp &= ~(1<<0);
2434                 temp |= (1<<1);
2435         } else {
2436                 temp &= ~(1<<1);
2437         }
2438         WREG32(CONFIG_CNTL, temp);
2439 }
2440
2441 int r600_resume(struct radeon_device *rdev)
2442 {
2443         int r;
2444
2445         /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
2446          * posting will perform necessary task to bring back GPU into good
2447          * shape.
2448          */
2449         /* post card */
2450         atom_asic_init(rdev->mode_info.atom_context);
2451
2452         r = r600_startup(rdev);
2453         if (r) {
2454                 DRM_ERROR("r600 startup failed on resume\n");
2455                 return r;
2456         }
2457
2458         r = r600_ib_test(rdev);
2459         if (r) {
2460                 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
2461                 return r;
2462         }
2463
2464         r = r600_audio_init(rdev);
2465         if (r) {
2466                 DRM_ERROR("radeon: audio resume failed\n");
2467                 return r;
2468         }
2469
2470         return r;
2471 }
2472
2473 int r600_suspend(struct radeon_device *rdev)
2474 {
2475         int r;
2476
2477         r600_audio_fini(rdev);
2478         /* FIXME: we should wait for ring to be empty */
2479         r600_cp_stop(rdev);
2480         rdev->cp.ready = false;
2481         r600_irq_suspend(rdev);
2482         radeon_wb_disable(rdev);
2483         r600_pcie_gart_disable(rdev);
2484         /* unpin shaders bo */
2485         if (rdev->r600_blit.shader_obj) {
2486                 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
2487                 if (!r) {
2488                         radeon_bo_unpin(rdev->r600_blit.shader_obj);
2489                         radeon_bo_unreserve(rdev->r600_blit.shader_obj);
2490                 }
2491         }
2492         return 0;
2493 }
2494
2495 /* Plan is to move initialization in that function and use
2496  * helper function so that radeon_device_init pretty much
2497  * do nothing more than calling asic specific function. This
2498  * should also allow to remove a bunch of callback function
2499  * like vram_info.
2500  */
2501 int r600_init(struct radeon_device *rdev)
2502 {
2503         int r;
2504
2505         r = radeon_dummy_page_init(rdev);
2506         if (r)
2507                 return r;
2508         if (r600_debugfs_mc_info_init(rdev)) {
2509                 DRM_ERROR("Failed to register debugfs file for mc !\n");
2510         }
2511         /* This don't do much */
2512         r = radeon_gem_init(rdev);
2513         if (r)
2514                 return r;
2515         /* Read BIOS */
2516         if (!radeon_get_bios(rdev)) {
2517                 if (ASIC_IS_AVIVO(rdev))
2518                         return -EINVAL;
2519         }
2520         /* Must be an ATOMBIOS */
2521         if (!rdev->is_atom_bios) {
2522                 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
2523                 return -EINVAL;
2524         }
2525         r = radeon_atombios_init(rdev);
2526         if (r)
2527                 return r;
2528         /* Post card if necessary */
2529         if (!radeon_card_posted(rdev)) {
2530                 if (!rdev->bios) {
2531                         dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2532                         return -EINVAL;
2533                 }
2534                 DRM_INFO("GPU not posted. posting now...\n");
2535                 atom_asic_init(rdev->mode_info.atom_context);
2536         }
2537         /* Initialize scratch registers */
2538         r600_scratch_init(rdev);
2539         /* Initialize surface registers */
2540         radeon_surface_init(rdev);
2541         /* Initialize clocks */
2542         radeon_get_clock_info(rdev->ddev);
2543         /* Fence driver */
2544         r = radeon_fence_driver_init(rdev);
2545         if (r)
2546                 return r;
2547         if (rdev->flags & RADEON_IS_AGP) {
2548                 r = radeon_agp_init(rdev);
2549                 if (r)
2550                         radeon_agp_disable(rdev);
2551         }
2552         r = r600_mc_init(rdev);
2553         if (r)
2554                 return r;
2555         /* Memory manager */
2556         r = radeon_bo_init(rdev);
2557         if (r)
2558                 return r;
2559
2560         r = radeon_irq_kms_init(rdev);
2561         if (r)
2562                 return r;
2563
2564         rdev->cp.ring_obj = NULL;
2565         r600_ring_init(rdev, 1024 * 1024);
2566
2567         rdev->ih.ring_obj = NULL;
2568         r600_ih_ring_init(rdev, 64 * 1024);
2569
2570         r = r600_pcie_gart_init(rdev);
2571         if (r)
2572                 return r;
2573
2574         rdev->accel_working = true;
2575         r = r600_startup(rdev);
2576         if (r) {
2577                 dev_err(rdev->dev, "disabling GPU acceleration\n");
2578                 r600_cp_fini(rdev);
2579                 r600_irq_fini(rdev);
2580                 radeon_wb_fini(rdev);
2581                 radeon_irq_kms_fini(rdev);
2582                 r600_pcie_gart_fini(rdev);
2583                 rdev->accel_working = false;
2584         }
2585         if (rdev->accel_working) {
2586                 r = radeon_ib_pool_init(rdev);
2587                 if (r) {
2588                         dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
2589                         rdev->accel_working = false;
2590                 } else {
2591                         r = r600_ib_test(rdev);
2592                         if (r) {
2593                                 dev_err(rdev->dev, "IB test failed (%d).\n", r);
2594                                 rdev->accel_working = false;
2595                         }
2596                 }
2597         }
2598
2599         r = r600_audio_init(rdev);
2600         if (r)
2601                 return r; /* TODO error handling */
2602         return 0;
2603 }
2604
2605 void r600_fini(struct radeon_device *rdev)
2606 {
2607         r600_audio_fini(rdev);
2608         r600_blit_fini(rdev);
2609         r600_cp_fini(rdev);
2610         r600_irq_fini(rdev);
2611         radeon_wb_fini(rdev);
2612         radeon_irq_kms_fini(rdev);
2613         r600_pcie_gart_fini(rdev);
2614         radeon_agp_fini(rdev);
2615         radeon_gem_fini(rdev);
2616         radeon_fence_driver_fini(rdev);
2617         radeon_bo_fini(rdev);
2618         radeon_atombios_fini(rdev);
2619         kfree(rdev->bios);
2620         rdev->bios = NULL;
2621         radeon_dummy_page_fini(rdev);
2622 }
2623
2624
2625 /*
2626  * CS stuff
2627  */
2628 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
2629 {
2630         /* FIXME: implement */
2631         radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
2632         radeon_ring_write(rdev, ib->gpu_addr & 0xFFFFFFFC);
2633         radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF);
2634         radeon_ring_write(rdev, ib->length_dw);
2635 }
2636
2637 int r600_ib_test(struct radeon_device *rdev)
2638 {
2639         struct radeon_ib *ib;
2640         uint32_t scratch;
2641         uint32_t tmp = 0;
2642         unsigned i;
2643         int r;
2644
2645         r = radeon_scratch_get(rdev, &scratch);
2646         if (r) {
2647                 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
2648                 return r;
2649         }
2650         WREG32(scratch, 0xCAFEDEAD);
2651         r = radeon_ib_get(rdev, &ib);
2652         if (r) {
2653                 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
2654                 return r;
2655         }
2656         ib->ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
2657         ib->ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2658         ib->ptr[2] = 0xDEADBEEF;
2659         ib->ptr[3] = PACKET2(0);
2660         ib->ptr[4] = PACKET2(0);
2661         ib->ptr[5] = PACKET2(0);
2662         ib->ptr[6] = PACKET2(0);
2663         ib->ptr[7] = PACKET2(0);
2664         ib->ptr[8] = PACKET2(0);
2665         ib->ptr[9] = PACKET2(0);
2666         ib->ptr[10] = PACKET2(0);
2667         ib->ptr[11] = PACKET2(0);
2668         ib->ptr[12] = PACKET2(0);
2669         ib->ptr[13] = PACKET2(0);
2670         ib->ptr[14] = PACKET2(0);
2671         ib->ptr[15] = PACKET2(0);
2672         ib->length_dw = 16;
2673         r = radeon_ib_schedule(rdev, ib);
2674         if (r) {
2675                 radeon_scratch_free(rdev, scratch);
2676                 radeon_ib_free(rdev, &ib);
2677                 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
2678                 return r;
2679         }
2680         r = radeon_fence_wait(ib->fence, false);
2681         if (r) {
2682                 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
2683                 return r;
2684         }
2685         for (i = 0; i < rdev->usec_timeout; i++) {
2686                 tmp = RREG32(scratch);
2687                 if (tmp == 0xDEADBEEF)
2688                         break;
2689                 DRM_UDELAY(1);
2690         }
2691         if (i < rdev->usec_timeout) {
2692                 DRM_INFO("ib test succeeded in %u usecs\n", i);
2693         } else {
2694                 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
2695                           scratch, tmp);
2696                 r = -EINVAL;
2697         }
2698         radeon_scratch_free(rdev, scratch);
2699         radeon_ib_free(rdev, &ib);
2700         return r;
2701 }
2702
2703 /*
2704  * Interrupts
2705  *
2706  * Interrupts use a ring buffer on r6xx/r7xx hardware.  It works pretty
2707  * the same as the CP ring buffer, but in reverse.  Rather than the CPU
2708  * writing to the ring and the GPU consuming, the GPU writes to the ring
2709  * and host consumes.  As the host irq handler processes interrupts, it
2710  * increments the rptr.  When the rptr catches up with the wptr, all the
2711  * current interrupts have been processed.
2712  */
2713
2714 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
2715 {
2716         u32 rb_bufsz;
2717
2718         /* Align ring size */
2719         rb_bufsz = drm_order(ring_size / 4);
2720         ring_size = (1 << rb_bufsz) * 4;
2721         rdev->ih.ring_size = ring_size;
2722         rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
2723         rdev->ih.rptr = 0;
2724 }
2725
2726 static int r600_ih_ring_alloc(struct radeon_device *rdev)
2727 {
2728         int r;
2729
2730         /* Allocate ring buffer */
2731         if (rdev->ih.ring_obj == NULL) {
2732                 r = radeon_bo_create(rdev, rdev->ih.ring_size,
2733                                      PAGE_SIZE, true,
2734                                      RADEON_GEM_DOMAIN_GTT,
2735                                      &rdev->ih.ring_obj);
2736                 if (r) {
2737                         DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
2738                         return r;
2739                 }
2740                 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2741                 if (unlikely(r != 0))
2742                         return r;
2743                 r = radeon_bo_pin(rdev->ih.ring_obj,
2744                                   RADEON_GEM_DOMAIN_GTT,
2745                                   &rdev->ih.gpu_addr);
2746                 if (r) {
2747                         radeon_bo_unreserve(rdev->ih.ring_obj);
2748                         DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
2749                         return r;
2750                 }
2751                 r = radeon_bo_kmap(rdev->ih.ring_obj,
2752                                    (void **)&rdev->ih.ring);
2753                 radeon_bo_unreserve(rdev->ih.ring_obj);
2754                 if (r) {
2755                         DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
2756                         return r;
2757                 }
2758         }
2759         return 0;
2760 }
2761
2762 static void r600_ih_ring_fini(struct radeon_device *rdev)
2763 {
2764         int r;
2765         if (rdev->ih.ring_obj) {
2766                 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2767                 if (likely(r == 0)) {
2768                         radeon_bo_kunmap(rdev->ih.ring_obj);
2769                         radeon_bo_unpin(rdev->ih.ring_obj);
2770                         radeon_bo_unreserve(rdev->ih.ring_obj);
2771                 }
2772                 radeon_bo_unref(&rdev->ih.ring_obj);
2773                 rdev->ih.ring = NULL;
2774                 rdev->ih.ring_obj = NULL;
2775         }
2776 }
2777
2778 void r600_rlc_stop(struct radeon_device *rdev)
2779 {
2780
2781         if ((rdev->family >= CHIP_RV770) &&
2782             (rdev->family <= CHIP_RV740)) {
2783                 /* r7xx asics need to soft reset RLC before halting */
2784                 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
2785                 RREG32(SRBM_SOFT_RESET);
2786                 udelay(15000);
2787                 WREG32(SRBM_SOFT_RESET, 0);
2788                 RREG32(SRBM_SOFT_RESET);
2789         }
2790
2791         WREG32(RLC_CNTL, 0);
2792 }
2793
2794 static void r600_rlc_start(struct radeon_device *rdev)
2795 {
2796         WREG32(RLC_CNTL, RLC_ENABLE);
2797 }
2798
2799 static int r600_rlc_init(struct radeon_device *rdev)
2800 {
2801         u32 i;
2802         const __be32 *fw_data;
2803
2804         if (!rdev->rlc_fw)
2805                 return -EINVAL;
2806
2807         r600_rlc_stop(rdev);
2808
2809         WREG32(RLC_HB_BASE, 0);
2810         WREG32(RLC_HB_CNTL, 0);
2811         WREG32(RLC_HB_RPTR, 0);
2812         WREG32(RLC_HB_WPTR, 0);
2813         if (rdev->family <= CHIP_CAICOS) {
2814                 WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
2815                 WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
2816         }
2817         WREG32(RLC_MC_CNTL, 0);
2818         WREG32(RLC_UCODE_CNTL, 0);
2819
2820         fw_data = (const __be32 *)rdev->rlc_fw->data;
2821         if (rdev->family >= CHIP_CAYMAN) {
2822                 for (i = 0; i < CAYMAN_RLC_UCODE_SIZE; i++) {
2823                         WREG32(RLC_UCODE_ADDR, i);
2824                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2825                 }
2826         } else if (rdev->family >= CHIP_CEDAR) {
2827                 for (i = 0; i < EVERGREEN_RLC_UCODE_SIZE; i++) {
2828                         WREG32(RLC_UCODE_ADDR, i);
2829                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2830                 }
2831         } else if (rdev->family >= CHIP_RV770) {
2832                 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
2833                         WREG32(RLC_UCODE_ADDR, i);
2834                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2835                 }
2836         } else {
2837                 for (i = 0; i < RLC_UCODE_SIZE; i++) {
2838                         WREG32(RLC_UCODE_ADDR, i);
2839                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2840                 }
2841         }
2842         WREG32(RLC_UCODE_ADDR, 0);
2843
2844         r600_rlc_start(rdev);
2845
2846         return 0;
2847 }
2848
2849 static void r600_enable_interrupts(struct radeon_device *rdev)
2850 {
2851         u32 ih_cntl = RREG32(IH_CNTL);
2852         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2853
2854         ih_cntl |= ENABLE_INTR;
2855         ih_rb_cntl |= IH_RB_ENABLE;
2856         WREG32(IH_CNTL, ih_cntl);
2857         WREG32(IH_RB_CNTL, ih_rb_cntl);
2858         rdev->ih.enabled = true;
2859 }
2860
2861 void r600_disable_interrupts(struct radeon_device *rdev)
2862 {
2863         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2864         u32 ih_cntl = RREG32(IH_CNTL);
2865
2866         ih_rb_cntl &= ~IH_RB_ENABLE;
2867         ih_cntl &= ~ENABLE_INTR;
2868         WREG32(IH_RB_CNTL, ih_rb_cntl);
2869         WREG32(IH_CNTL, ih_cntl);
2870         /* set rptr, wptr to 0 */
2871         WREG32(IH_RB_RPTR, 0);
2872         WREG32(IH_RB_WPTR, 0);
2873         rdev->ih.enabled = false;
2874         rdev->ih.wptr = 0;
2875         rdev->ih.rptr = 0;
2876 }
2877
2878 static void r600_disable_interrupt_state(struct radeon_device *rdev)
2879 {
2880         u32 tmp;
2881
2882         WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
2883         WREG32(GRBM_INT_CNTL, 0);
2884         WREG32(DxMODE_INT_MASK, 0);
2885         WREG32(D1GRPH_INTERRUPT_CONTROL, 0);
2886         WREG32(D2GRPH_INTERRUPT_CONTROL, 0);
2887         if (ASIC_IS_DCE3(rdev)) {
2888                 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);
2889                 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);
2890                 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2891                 WREG32(DC_HPD1_INT_CONTROL, tmp);
2892                 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2893                 WREG32(DC_HPD2_INT_CONTROL, tmp);
2894                 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2895                 WREG32(DC_HPD3_INT_CONTROL, tmp);
2896                 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2897                 WREG32(DC_HPD4_INT_CONTROL, tmp);
2898                 if (ASIC_IS_DCE32(rdev)) {
2899                         tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2900                         WREG32(DC_HPD5_INT_CONTROL, tmp);
2901                         tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2902                         WREG32(DC_HPD6_INT_CONTROL, tmp);
2903                 }
2904         } else {
2905                 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2906                 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2907                 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2908                 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
2909                 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2910                 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
2911                 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2912                 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
2913         }
2914 }
2915
2916 int r600_irq_init(struct radeon_device *rdev)
2917 {
2918         int ret = 0;
2919         int rb_bufsz;
2920         u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
2921
2922         /* allocate ring */
2923         ret = r600_ih_ring_alloc(rdev);
2924         if (ret)
2925                 return ret;
2926
2927         /* disable irqs */
2928         r600_disable_interrupts(rdev);
2929
2930         /* init rlc */
2931         ret = r600_rlc_init(rdev);
2932         if (ret) {
2933                 r600_ih_ring_fini(rdev);
2934                 return ret;
2935         }
2936
2937         /* setup interrupt control */
2938         /* set dummy read address to ring address */
2939         WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
2940         interrupt_cntl = RREG32(INTERRUPT_CNTL);
2941         /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
2942          * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
2943          */
2944         interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
2945         /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
2946         interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
2947         WREG32(INTERRUPT_CNTL, interrupt_cntl);
2948
2949         WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
2950         rb_bufsz = drm_order(rdev->ih.ring_size / 4);
2951
2952         ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
2953                       IH_WPTR_OVERFLOW_CLEAR |
2954                       (rb_bufsz << 1));
2955
2956         if (rdev->wb.enabled)
2957                 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;
2958
2959         /* set the writeback address whether it's enabled or not */
2960         WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
2961         WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
2962
2963         WREG32(IH_RB_CNTL, ih_rb_cntl);
2964
2965         /* set rptr, wptr to 0 */
2966         WREG32(IH_RB_RPTR, 0);
2967         WREG32(IH_RB_WPTR, 0);
2968
2969         /* Default settings for IH_CNTL (disabled at first) */
2970         ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
2971         /* RPTR_REARM only works if msi's are enabled */
2972         if (rdev->msi_enabled)
2973                 ih_cntl |= RPTR_REARM;
2974
2975 #ifdef __BIG_ENDIAN
2976         ih_cntl |= IH_MC_SWAP(IH_MC_SWAP_32BIT);
2977 #endif
2978         WREG32(IH_CNTL, ih_cntl);
2979
2980         /* force the active interrupt state to all disabled */
2981         if (rdev->family >= CHIP_CEDAR)
2982                 evergreen_disable_interrupt_state(rdev);
2983         else
2984                 r600_disable_interrupt_state(rdev);
2985
2986         /* enable irqs */
2987         r600_enable_interrupts(rdev);
2988
2989         return ret;
2990 }
2991
2992 void r600_irq_suspend(struct radeon_device *rdev)
2993 {
2994         r600_irq_disable(rdev);
2995         r600_rlc_stop(rdev);
2996 }
2997
2998 void r600_irq_fini(struct radeon_device *rdev)
2999 {
3000         r600_irq_suspend(rdev);
3001         r600_ih_ring_fini(rdev);
3002 }
3003
3004 int r600_irq_set(struct radeon_device *rdev)
3005 {
3006         u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
3007         u32 mode_int = 0;
3008         u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
3009         u32 grbm_int_cntl = 0;
3010         u32 hdmi1, hdmi2;
3011         u32 d1grph = 0, d2grph = 0;
3012
3013         if (!rdev->irq.installed) {
3014                 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
3015                 return -EINVAL;
3016         }
3017         /* don't enable anything if the ih is disabled */
3018         if (!rdev->ih.enabled) {
3019                 r600_disable_interrupts(rdev);
3020                 /* force the active interrupt state to all disabled */
3021                 r600_disable_interrupt_state(rdev);
3022                 return 0;
3023         }
3024
3025         hdmi1 = RREG32(R600_HDMI_BLOCK1 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
3026         if (ASIC_IS_DCE3(rdev)) {
3027                 hdmi2 = RREG32(R600_HDMI_BLOCK3 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
3028                 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3029                 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3030                 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3031                 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
3032                 if (ASIC_IS_DCE32(rdev)) {
3033                         hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
3034                         hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
3035                 }
3036         } else {
3037                 hdmi2 = RREG32(R600_HDMI_BLOCK2 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
3038                 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3039                 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3040                 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3041         }
3042
3043         if (rdev->irq.sw_int) {
3044                 DRM_DEBUG("r600_irq_set: sw int\n");
3045                 cp_int_cntl |= RB_INT_ENABLE;
3046                 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
3047         }
3048         if (rdev->irq.crtc_vblank_int[0] ||
3049             rdev->irq.pflip[0]) {
3050                 DRM_DEBUG("r600_irq_set: vblank 0\n");
3051                 mode_int |= D1MODE_VBLANK_INT_MASK;
3052         }
3053         if (rdev->irq.crtc_vblank_int[1] ||
3054             rdev->irq.pflip[1]) {
3055                 DRM_DEBUG("r600_irq_set: vblank 1\n");
3056                 mode_int |= D2MODE_VBLANK_INT_MASK;
3057         }
3058         if (rdev->irq.hpd[0]) {
3059                 DRM_DEBUG("r600_irq_set: hpd 1\n");
3060                 hpd1 |= DC_HPDx_INT_EN;
3061         }
3062         if (rdev->irq.hpd[1]) {
3063                 DRM_DEBUG("r600_irq_set: hpd 2\n");
3064                 hpd2 |= DC_HPDx_INT_EN;
3065         }
3066         if (rdev->irq.hpd[2]) {
3067                 DRM_DEBUG("r600_irq_set: hpd 3\n");
3068                 hpd3 |= DC_HPDx_INT_EN;
3069         }
3070         if (rdev->irq.hpd[3]) {
3071                 DRM_DEBUG("r600_irq_set: hpd 4\n");
3072                 hpd4 |= DC_HPDx_INT_EN;
3073         }
3074         if (rdev->irq.hpd[4]) {
3075                 DRM_DEBUG("r600_irq_set: hpd 5\n");
3076                 hpd5 |= DC_HPDx_INT_EN;
3077         }
3078         if (rdev->irq.hpd[5]) {
3079                 DRM_DEBUG("r600_irq_set: hpd 6\n");
3080                 hpd6 |= DC_HPDx_INT_EN;
3081         }
3082         if (rdev->irq.hdmi[0]) {
3083                 DRM_DEBUG("r600_irq_set: hdmi 1\n");
3084                 hdmi1 |= R600_HDMI_INT_EN;
3085         }
3086         if (rdev->irq.hdmi[1]) {
3087                 DRM_DEBUG("r600_irq_set: hdmi 2\n");
3088                 hdmi2 |= R600_HDMI_INT_EN;
3089         }
3090         if (rdev->irq.gui_idle) {
3091                 DRM_DEBUG("gui idle\n");
3092                 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
3093         }
3094
3095         WREG32(CP_INT_CNTL, cp_int_cntl);
3096         WREG32(DxMODE_INT_MASK, mode_int);
3097         WREG32(D1GRPH_INTERRUPT_CONTROL, d1grph);
3098         WREG32(D2GRPH_INTERRUPT_CONTROL, d2grph);
3099         WREG32(GRBM_INT_CNTL, grbm_int_cntl);
3100         WREG32(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, hdmi1);
3101         if (ASIC_IS_DCE3(rdev)) {
3102                 WREG32(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, hdmi2);
3103                 WREG32(DC_HPD1_INT_CONTROL, hpd1);
3104                 WREG32(DC_HPD2_INT_CONTROL, hpd2);
3105                 WREG32(DC_HPD3_INT_CONTROL, hpd3);
3106                 WREG32(DC_HPD4_INT_CONTROL, hpd4);
3107                 if (ASIC_IS_DCE32(rdev)) {
3108                         WREG32(DC_HPD5_INT_CONTROL, hpd5);
3109                         WREG32(DC_HPD6_INT_CONTROL, hpd6);
3110                 }
3111         } else {
3112                 WREG32(R600_HDMI_BLOCK2 + R600_HDMI_CNTL, hdmi2);
3113                 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
3114                 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
3115                 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
3116         }
3117
3118         return 0;
3119 }
3120
3121 static inline void r600_irq_ack(struct radeon_device *rdev)
3122 {
3123         u32 tmp;
3124
3125         if (ASIC_IS_DCE3(rdev)) {
3126                 rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
3127                 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
3128                 rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
3129         } else {
3130                 rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS);
3131                 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
3132                 rdev->irq.stat_regs.r600.disp_int_cont2 = 0;
3133         }
3134         rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS);
3135         rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS);
3136
3137         if (rdev->irq.stat_regs.r600.d1grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3138                 WREG32(D1GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3139         if (rdev->irq.stat_regs.r600.d2grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3140                 WREG32(D2GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3141         if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT)
3142                 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
3143         if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT)
3144                 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
3145         if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT)
3146                 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
3147         if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT)
3148                 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
3149         if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
3150                 if (ASIC_IS_DCE3(rdev)) {
3151                         tmp = RREG32(DC_HPD1_INT_CONTROL);
3152                         tmp |= DC_HPDx_INT_ACK;
3153                         WREG32(DC_HPD1_INT_CONTROL, tmp);
3154                 } else {
3155                         tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
3156                         tmp |= DC_HPDx_INT_ACK;
3157                         WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
3158                 }
3159         }
3160         if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
3161                 if (ASIC_IS_DCE3(rdev)) {
3162                         tmp = RREG32(DC_HPD2_INT_CONTROL);
3163                         tmp |= DC_HPDx_INT_ACK;
3164                         WREG32(DC_HPD2_INT_CONTROL, tmp);
3165                 } else {
3166                         tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
3167                         tmp |= DC_HPDx_INT_ACK;
3168                         WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
3169                 }
3170         }
3171         if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
3172                 if (ASIC_IS_DCE3(rdev)) {
3173                         tmp = RREG32(DC_HPD3_INT_CONTROL);
3174                         tmp |= DC_HPDx_INT_ACK;
3175                         WREG32(DC_HPD3_INT_CONTROL, tmp);
3176                 } else {
3177                         tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
3178                         tmp |= DC_HPDx_INT_ACK;
3179                         WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
3180                 }
3181         }
3182         if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
3183                 tmp = RREG32(DC_HPD4_INT_CONTROL);
3184                 tmp |= DC_HPDx_INT_ACK;
3185                 WREG32(DC_HPD4_INT_CONTROL, tmp);
3186         }
3187         if (ASIC_IS_DCE32(rdev)) {
3188                 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
3189                         tmp = RREG32(DC_HPD5_INT_CONTROL);
3190                         tmp |= DC_HPDx_INT_ACK;
3191                         WREG32(DC_HPD5_INT_CONTROL, tmp);
3192                 }
3193                 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
3194                         tmp = RREG32(DC_HPD5_INT_CONTROL);
3195                         tmp |= DC_HPDx_INT_ACK;
3196                         WREG32(DC_HPD6_INT_CONTROL, tmp);
3197                 }
3198         }
3199         if (RREG32(R600_HDMI_BLOCK1 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3200                 WREG32_P(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3201         }
3202         if (ASIC_IS_DCE3(rdev)) {
3203                 if (RREG32(R600_HDMI_BLOCK3 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3204                         WREG32_P(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3205                 }
3206         } else {
3207                 if (RREG32(R600_HDMI_BLOCK2 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3208                         WREG32_P(R600_HDMI_BLOCK2 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3209                 }
3210         }
3211 }
3212
3213 void r600_irq_disable(struct radeon_device *rdev)
3214 {
3215         r600_disable_interrupts(rdev);
3216         /* Wait and acknowledge irq */
3217         mdelay(1);
3218         r600_irq_ack(rdev);
3219         r600_disable_interrupt_state(rdev);
3220 }
3221
3222 static inline u32 r600_get_ih_wptr(struct radeon_device *rdev)
3223 {
3224         u32 wptr, tmp;
3225
3226         if (rdev->wb.enabled)
3227                 wptr = rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4];
3228         else
3229                 wptr = RREG32(IH_RB_WPTR);
3230
3231         if (wptr & RB_OVERFLOW) {
3232                 /* When a ring buffer overflow happen start parsing interrupt
3233                  * from the last not overwritten vector (wptr + 16). Hopefully
3234                  * this should allow us to catchup.
3235                  */
3236                 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
3237                         wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
3238                 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
3239                 tmp = RREG32(IH_RB_CNTL);
3240                 tmp |= IH_WPTR_OVERFLOW_CLEAR;
3241                 WREG32(IH_RB_CNTL, tmp);
3242         }
3243         return (wptr & rdev->ih.ptr_mask);
3244 }
3245
3246 /*        r600 IV Ring
3247  * Each IV ring entry is 128 bits:
3248  * [7:0]    - interrupt source id
3249  * [31:8]   - reserved
3250  * [59:32]  - interrupt source data
3251  * [127:60]  - reserved
3252  *
3253  * The basic interrupt vector entries
3254  * are decoded as follows:
3255  * src_id  src_data  description
3256  *      1         0  D1 Vblank
3257  *      1         1  D1 Vline
3258  *      5         0  D2 Vblank
3259  *      5         1  D2 Vline
3260  *     19         0  FP Hot plug detection A
3261  *     19         1  FP Hot plug detection B
3262  *     19         2  DAC A auto-detection
3263  *     19         3  DAC B auto-detection
3264  *     21         4  HDMI block A
3265  *     21         5  HDMI block B
3266  *    176         -  CP_INT RB
3267  *    177         -  CP_INT IB1
3268  *    178         -  CP_INT IB2
3269  *    181         -  EOP Interrupt
3270  *    233         -  GUI Idle
3271  *
3272  * Note, these are based on r600 and may need to be
3273  * adjusted or added to on newer asics
3274  */
3275
3276 int r600_irq_process(struct radeon_device *rdev)
3277 {
3278         u32 wptr = r600_get_ih_wptr(rdev);
3279         u32 rptr = rdev->ih.rptr;
3280         u32 src_id, src_data;
3281         u32 ring_index;
3282         unsigned long flags;
3283         bool queue_hotplug = false;
3284
3285         DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
3286         if (!rdev->ih.enabled)
3287                 return IRQ_NONE;
3288
3289         spin_lock_irqsave(&rdev->ih.lock, flags);
3290
3291         if (rptr == wptr) {
3292                 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3293                 return IRQ_NONE;
3294         }
3295         if (rdev->shutdown) {
3296                 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3297                 return IRQ_NONE;
3298         }
3299
3300 restart_ih:
3301         /* display interrupts */
3302         r600_irq_ack(rdev);
3303
3304         rdev->ih.wptr = wptr;
3305         while (rptr != wptr) {
3306                 /* wptr/rptr are in bytes! */
3307                 ring_index = rptr / 4;
3308                 src_id =  rdev->ih.ring[ring_index] & 0xff;
3309                 src_data = rdev->ih.ring[ring_index + 1] & 0xfffffff;
3310
3311                 switch (src_id) {
3312                 case 1: /* D1 vblank/vline */
3313                         switch (src_data) {
3314                         case 0: /* D1 vblank */
3315                                 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) {
3316                                         if (rdev->irq.crtc_vblank_int[0]) {
3317                                                 drm_handle_vblank(rdev->ddev, 0);
3318                                                 rdev->pm.vblank_sync = true;
3319                                                 wake_up(&rdev->irq.vblank_queue);
3320                                         }
3321                                         if (rdev->irq.pflip[0])
3322                                                 radeon_crtc_handle_flip(rdev, 0);
3323                                         rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
3324                                         DRM_DEBUG("IH: D1 vblank\n");
3325                                 }
3326                                 break;
3327                         case 1: /* D1 vline */
3328                                 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) {
3329                                         rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT;
3330                                         DRM_DEBUG("IH: D1 vline\n");
3331                                 }
3332                                 break;
3333                         default:
3334                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3335                                 break;
3336                         }
3337                         break;
3338                 case 5: /* D2 vblank/vline */
3339                         switch (src_data) {
3340                         case 0: /* D2 vblank */
3341                                 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) {
3342                                         if (rdev->irq.crtc_vblank_int[1]) {
3343                                                 drm_handle_vblank(rdev->ddev, 1);
3344                                                 rdev->pm.vblank_sync = true;
3345                                                 wake_up(&rdev->irq.vblank_queue);
3346                                         }
3347                                         if (rdev->irq.pflip[1])
3348                                                 radeon_crtc_handle_flip(rdev, 1);
3349                                         rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT;
3350                                         DRM_DEBUG("IH: D2 vblank\n");
3351                                 }
3352                                 break;
3353                         case 1: /* D1 vline */
3354                                 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) {
3355                                         rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT;
3356                                         DRM_DEBUG("IH: D2 vline\n");
3357                                 }
3358                                 break;
3359                         default:
3360                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3361                                 break;
3362                         }
3363                         break;
3364                 case 19: /* HPD/DAC hotplug */
3365                         switch (src_data) {
3366                         case 0:
3367                                 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
3368                                         rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT;
3369                                         queue_hotplug = true;
3370                                         DRM_DEBUG("IH: HPD1\n");
3371                                 }
3372                                 break;
3373                         case 1:
3374                                 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
3375                                         rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT;
3376                                         queue_hotplug = true;
3377                                         DRM_DEBUG("IH: HPD2\n");
3378                                 }
3379                                 break;
3380                         case 4:
3381                                 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
3382                                         rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT;
3383                                         queue_hotplug = true;
3384                                         DRM_DEBUG("IH: HPD3\n");
3385                                 }
3386                                 break;
3387                         case 5:
3388                                 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
3389                                         rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT;
3390                                         queue_hotplug = true;
3391                                         DRM_DEBUG("IH: HPD4\n");
3392                                 }
3393                                 break;
3394                         case 10:
3395                                 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
3396                                         rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT;
3397                                         queue_hotplug = true;
3398                                         DRM_DEBUG("IH: HPD5\n");
3399                                 }
3400                                 break;
3401                         case 12:
3402                                 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
3403                                         rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT;
3404                                         queue_hotplug = true;
3405                                         DRM_DEBUG("IH: HPD6\n");
3406                                 }
3407                                 break;
3408                         default:
3409                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3410                                 break;
3411                         }
3412                         break;
3413                 case 21: /* HDMI */
3414                         DRM_DEBUG("IH: HDMI: 0x%x\n", src_data);
3415                         r600_audio_schedule_polling(rdev);
3416                         break;
3417                 case 176: /* CP_INT in ring buffer */
3418                 case 177: /* CP_INT in IB1 */
3419                 case 178: /* CP_INT in IB2 */
3420                         DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
3421                         radeon_fence_process(rdev);
3422                         break;
3423                 case 181: /* CP EOP event */
3424                         DRM_DEBUG("IH: CP EOP\n");
3425                         radeon_fence_process(rdev);
3426                         break;
3427                 case 233: /* GUI IDLE */
3428                         DRM_DEBUG("IH: CP EOP\n");
3429                         rdev->pm.gui_idle = true;
3430                         wake_up(&rdev->irq.idle_queue);
3431                         break;
3432                 default:
3433                         DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3434                         break;
3435                 }
3436
3437                 /* wptr/rptr are in bytes! */
3438                 rptr += 16;
3439                 rptr &= rdev->ih.ptr_mask;
3440         }
3441         /* make sure wptr hasn't changed while processing */
3442         wptr = r600_get_ih_wptr(rdev);
3443         if (wptr != rdev->ih.wptr)
3444                 goto restart_ih;
3445         if (queue_hotplug)
3446                 schedule_work(&rdev->hotplug_work);
3447         rdev->ih.rptr = rptr;
3448         WREG32(IH_RB_RPTR, rdev->ih.rptr);
3449         spin_unlock_irqrestore(&rdev->ih.lock, flags);
3450         return IRQ_HANDLED;
3451 }
3452
3453 /*
3454  * Debugfs info
3455  */
3456 #if defined(CONFIG_DEBUG_FS)
3457
3458 static int r600_debugfs_cp_ring_info(struct seq_file *m, void *data)
3459 {
3460         struct drm_info_node *node = (struct drm_info_node *) m->private;
3461         struct drm_device *dev = node->minor->dev;
3462         struct radeon_device *rdev = dev->dev_private;
3463         unsigned count, i, j;
3464
3465         radeon_ring_free_size(rdev);
3466         count = (rdev->cp.ring_size / 4) - rdev->cp.ring_free_dw;
3467         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(CP_STAT));
3468         seq_printf(m, "CP_RB_WPTR 0x%08x\n", RREG32(CP_RB_WPTR));
3469         seq_printf(m, "CP_RB_RPTR 0x%08x\n", RREG32(CP_RB_RPTR));
3470         seq_printf(m, "driver's copy of the CP_RB_WPTR 0x%08x\n", rdev->cp.wptr);
3471         seq_printf(m, "driver's copy of the CP_RB_RPTR 0x%08x\n", rdev->cp.rptr);
3472         seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
3473         seq_printf(m, "%u dwords in ring\n", count);
3474         i = rdev->cp.rptr;
3475         for (j = 0; j <= count; j++) {
3476                 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
3477                 i = (i + 1) & rdev->cp.ptr_mask;
3478         }
3479         return 0;
3480 }
3481
3482 static int r600_debugfs_mc_info(struct seq_file *m, void *data)
3483 {
3484         struct drm_info_node *node = (struct drm_info_node *) m->private;
3485         struct drm_device *dev = node->minor->dev;
3486         struct radeon_device *rdev = dev->dev_private;
3487
3488         DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
3489         DREG32_SYS(m, rdev, VM_L2_STATUS);
3490         return 0;
3491 }
3492
3493 static struct drm_info_list r600_mc_info_list[] = {
3494         {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
3495         {"r600_ring_info", r600_debugfs_cp_ring_info, 0, NULL},
3496 };
3497 #endif
3498
3499 int r600_debugfs_mc_info_init(struct radeon_device *rdev)
3500 {
3501 #if defined(CONFIG_DEBUG_FS)
3502         return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
3503 #else
3504         return 0;
3505 #endif
3506 }
3507
3508 /**
3509  * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl
3510  * rdev: radeon device structure
3511  * bo: buffer object struct which userspace is waiting for idle
3512  *
3513  * Some R6XX/R7XX doesn't seems to take into account HDP flush performed
3514  * through ring buffer, this leads to corruption in rendering, see
3515  * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we
3516  * directly perform HDP flush by writing register through MMIO.
3517  */
3518 void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
3519 {
3520         /* r7xx hw bug.  write to HDP_DEBUG1 followed by fb read
3521          * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL.
3522          * This seems to cause problems on some AGP cards. Just use the old
3523          * method for them.
3524          */
3525         if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
3526             rdev->vram_scratch.ptr && !(rdev->flags & RADEON_IS_AGP)) {
3527                 void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
3528                 u32 tmp;
3529
3530                 WREG32(HDP_DEBUG1, 0);
3531                 tmp = readl((void __iomem *)ptr);
3532         } else
3533                 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
3534 }
3535
3536 void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes)
3537 {
3538         u32 link_width_cntl, mask, target_reg;
3539
3540         if (rdev->flags & RADEON_IS_IGP)
3541                 return;
3542
3543         if (!(rdev->flags & RADEON_IS_PCIE))
3544                 return;
3545
3546         /* x2 cards have a special sequence */
3547         if (ASIC_IS_X2(rdev))
3548                 return;
3549
3550         /* FIXME wait for idle */
3551
3552         switch (lanes) {
3553         case 0:
3554                 mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
3555                 break;
3556         case 1:
3557                 mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
3558                 break;
3559         case 2:
3560                 mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
3561                 break;
3562         case 4:
3563                 mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
3564                 break;
3565         case 8:
3566                 mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
3567                 break;
3568         case 12:
3569                 mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
3570                 break;
3571         case 16:
3572         default:
3573                 mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
3574                 break;
3575         }
3576
3577         link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
3578
3579         if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
3580             (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
3581                 return;
3582
3583         if (link_width_cntl & R600_PCIE_LC_UPCONFIGURE_DIS)
3584                 return;
3585
3586         link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK |
3587                              RADEON_PCIE_LC_RECONFIG_NOW |
3588                              R600_PCIE_LC_RENEGOTIATE_EN |
3589                              R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE);
3590         link_width_cntl |= mask;
3591
3592         WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3593
3594         /* some northbridges can renegotiate the link rather than requiring
3595          * a complete re-config.
3596          * e.g., AMD 780/790 northbridges (pci ids: 0x5956, 0x5957, 0x5958, etc.)
3597          */
3598         if (link_width_cntl & R600_PCIE_LC_RENEGOTIATION_SUPPORT)
3599                 link_width_cntl |= R600_PCIE_LC_RENEGOTIATE_EN | R600_PCIE_LC_UPCONFIGURE_SUPPORT;
3600         else
3601                 link_width_cntl |= R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE;
3602
3603         WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl |
3604                                                        RADEON_PCIE_LC_RECONFIG_NOW));
3605
3606         if (rdev->family >= CHIP_RV770)
3607                 target_reg = R700_TARGET_AND_CURRENT_PROFILE_INDEX;
3608         else
3609                 target_reg = R600_TARGET_AND_CURRENT_PROFILE_INDEX;
3610
3611         /* wait for lane set to complete */
3612         link_width_cntl = RREG32(target_reg);
3613         while (link_width_cntl == 0xffffffff)
3614                 link_width_cntl = RREG32(target_reg);
3615
3616 }
3617
3618 int r600_get_pcie_lanes(struct radeon_device *rdev)
3619 {
3620         u32 link_width_cntl;
3621
3622         if (rdev->flags & RADEON_IS_IGP)
3623                 return 0;
3624
3625         if (!(rdev->flags & RADEON_IS_PCIE))
3626                 return 0;
3627
3628         /* x2 cards have a special sequence */
3629         if (ASIC_IS_X2(rdev))
3630                 return 0;
3631
3632         /* FIXME wait for idle */
3633
3634         link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
3635
3636         switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
3637         case RADEON_PCIE_LC_LINK_WIDTH_X0:
3638                 return 0;
3639         case RADEON_PCIE_LC_LINK_WIDTH_X1:
3640                 return 1;
3641         case RADEON_PCIE_LC_LINK_WIDTH_X2:
3642                 return 2;
3643         case RADEON_PCIE_LC_LINK_WIDTH_X4:
3644                 return 4;
3645         case RADEON_PCIE_LC_LINK_WIDTH_X8:
3646                 return 8;
3647         case RADEON_PCIE_LC_LINK_WIDTH_X16:
3648         default:
3649                 return 16;
3650         }
3651 }
3652
3653 static void r600_pcie_gen2_enable(struct radeon_device *rdev)
3654 {
3655         u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp;
3656         u16 link_cntl2;
3657
3658         if (radeon_pcie_gen2 == 0)
3659                 return;
3660
3661         if (rdev->flags & RADEON_IS_IGP)
3662                 return;
3663
3664         if (!(rdev->flags & RADEON_IS_PCIE))
3665                 return;
3666
3667         /* x2 cards have a special sequence */
3668         if (ASIC_IS_X2(rdev))
3669                 return;
3670
3671         /* only RV6xx+ chips are supported */
3672         if (rdev->family <= CHIP_R600)
3673                 return;
3674
3675         /* 55 nm r6xx asics */
3676         if ((rdev->family == CHIP_RV670) ||
3677             (rdev->family == CHIP_RV620) ||
3678             (rdev->family == CHIP_RV635)) {
3679                 /* advertise upconfig capability */
3680                 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3681                 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3682                 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3683                 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3684                 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {
3685                         lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
3686                         link_width_cntl &= ~(LC_LINK_WIDTH_MASK |
3687                                              LC_RECONFIG_ARC_MISSING_ESCAPE);
3688                         link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN;
3689                         WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3690                 } else {
3691                         link_width_cntl |= LC_UPCONFIGURE_DIS;
3692                         WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3693                 }
3694         }
3695
3696         speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3697         if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
3698             (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
3699
3700                 /* 55 nm r6xx asics */
3701                 if ((rdev->family == CHIP_RV670) ||
3702                     (rdev->family == CHIP_RV620) ||
3703                     (rdev->family == CHIP_RV635)) {
3704                         WREG32(MM_CFGREGS_CNTL, 0x8);
3705                         link_cntl2 = RREG32(0x4088);
3706                         WREG32(MM_CFGREGS_CNTL, 0);
3707                         /* not supported yet */
3708                         if (link_cntl2 & SELECTABLE_DEEMPHASIS)
3709                                 return;
3710                 }
3711
3712                 speed_cntl &= ~LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK;
3713                 speed_cntl |= (0x3 << LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT);
3714                 speed_cntl &= ~LC_VOLTAGE_TIMER_SEL_MASK;
3715                 speed_cntl &= ~LC_FORCE_DIS_HW_SPEED_CHANGE;
3716                 speed_cntl |= LC_FORCE_EN_HW_SPEED_CHANGE;
3717                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3718
3719                 tmp = RREG32(0x541c);
3720                 WREG32(0x541c, tmp | 0x8);
3721                 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN);
3722                 link_cntl2 = RREG16(0x4088);
3723                 link_cntl2 &= ~TARGET_LINK_SPEED_MASK;
3724                 link_cntl2 |= 0x2;
3725                 WREG16(0x4088, link_cntl2);
3726                 WREG32(MM_CFGREGS_CNTL, 0);
3727
3728                 if ((rdev->family == CHIP_RV670) ||
3729                     (rdev->family == CHIP_RV620) ||
3730                     (rdev->family == CHIP_RV635)) {
3731                         training_cntl = RREG32_PCIE_P(PCIE_LC_TRAINING_CNTL);
3732                         training_cntl &= ~LC_POINT_7_PLUS_EN;
3733                         WREG32_PCIE_P(PCIE_LC_TRAINING_CNTL, training_cntl);
3734                 } else {
3735                         speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3736                         speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
3737                         WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3738                 }
3739
3740                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3741                 speed_cntl |= LC_GEN2_EN_STRAP;
3742                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3743
3744         } else {
3745                 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3746                 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
3747                 if (1)
3748                         link_width_cntl |= LC_UPCONFIGURE_DIS;
3749                 else
3750                         link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3751                 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3752         }
3753 }