Pileus Git - ~andy/linux/blob - drivers/gpu/drm/radeon/ni.c

   1 /*
   2  * Copyright 2010 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24 #include <linux/firmware.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/slab.h>
  27 #include "drmP.h"
  28 #include "radeon.h"
  29 #include "radeon_asic.h"
  30 #include "radeon_drm.h"
  31 #include "nid.h"
  32 #include "atom.h"
  33 #include "ni_reg.h"
  34
  35 #define EVERGREEN_PFP_UCODE_SIZE 1120
  36 #define EVERGREEN_PM4_UCODE_SIZE 1376
  37 #define EVERGREEN_RLC_UCODE_SIZE 768
  38 #define BTC_MC_UCODE_SIZE 6024
  39
  40 #define CAYMAN_PFP_UCODE_SIZE 2176
  41 #define CAYMAN_PM4_UCODE_SIZE 2176
  42 #define CAYMAN_RLC_UCODE_SIZE 1024
  43 #define CAYMAN_MC_UCODE_SIZE 6037
  44
  45 /* Firmware Names */
  46 MODULE_FIRMWARE("radeon/BARTS_pfp.bin");
  47 MODULE_FIRMWARE("radeon/BARTS_me.bin");
  48 MODULE_FIRMWARE("radeon/BARTS_mc.bin");
  49 MODULE_FIRMWARE("radeon/BTC_rlc.bin");
  50 MODULE_FIRMWARE("radeon/TURKS_pfp.bin");
  51 MODULE_FIRMWARE("radeon/TURKS_me.bin");
  52 MODULE_FIRMWARE("radeon/TURKS_mc.bin");
  53 MODULE_FIRMWARE("radeon/CAICOS_pfp.bin");
  54 MODULE_FIRMWARE("radeon/CAICOS_me.bin");
  55 MODULE_FIRMWARE("radeon/CAICOS_mc.bin");
  56 MODULE_FIRMWARE("radeon/CAYMAN_pfp.bin");
  57 MODULE_FIRMWARE("radeon/CAYMAN_me.bin");
  58 MODULE_FIRMWARE("radeon/CAYMAN_mc.bin");
  59 MODULE_FIRMWARE("radeon/CAYMAN_rlc.bin");
  60
  61 #define BTC_IO_MC_REGS_SIZE 29
  62
  63 static const u32 barts_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
  64         {0x00000077, 0xff010100},
  65         {0x00000078, 0x00000000},
  66         {0x00000079, 0x00001434},
  67         {0x0000007a, 0xcc08ec08},
  68         {0x0000007b, 0x00040000},
  69         {0x0000007c, 0x000080c0},
  70         {0x0000007d, 0x09000000},
  71         {0x0000007e, 0x00210404},
  72         {0x00000081, 0x08a8e800},
  73         {0x00000082, 0x00030444},
  74         {0x00000083, 0x00000000},
  75         {0x00000085, 0x00000001},
  76         {0x00000086, 0x00000002},
  77         {0x00000087, 0x48490000},
  78         {0x00000088, 0x20244647},
  79         {0x00000089, 0x00000005},
  80         {0x0000008b, 0x66030000},
  81         {0x0000008c, 0x00006603},
  82         {0x0000008d, 0x00000100},
  83         {0x0000008f, 0x00001c0a},
  84         {0x00000090, 0xff000001},
  85         {0x00000094, 0x00101101},
  86         {0x00000095, 0x00000fff},
  87         {0x00000096, 0x00116fff},
  88         {0x00000097, 0x60010000},
  89         {0x00000098, 0x10010000},
  90         {0x00000099, 0x00006000},
  91         {0x0000009a, 0x00001000},
  92         {0x0000009f, 0x00946a00}
  93 };
  94
  95 static const u32 turks_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
  96         {0x00000077, 0xff010100},
  97         {0x00000078, 0x00000000},
  98         {0x00000079, 0x00001434},
  99         {0x0000007a, 0xcc08ec08},
 100         {0x0000007b, 0x00040000},
 101         {0x0000007c, 0x000080c0},
 102         {0x0000007d, 0x09000000},
 103         {0x0000007e, 0x00210404},
 104         {0x00000081, 0x08a8e800},
 105         {0x00000082, 0x00030444},
 106         {0x00000083, 0x00000000},
 107         {0x00000085, 0x00000001},
 108         {0x00000086, 0x00000002},
 109         {0x00000087, 0x48490000},
 110         {0x00000088, 0x20244647},
 111         {0x00000089, 0x00000005},
 112         {0x0000008b, 0x66030000},
 113         {0x0000008c, 0x00006603},
 114         {0x0000008d, 0x00000100},
 115         {0x0000008f, 0x00001c0a},
 116         {0x00000090, 0xff000001},
 117         {0x00000094, 0x00101101},
 118         {0x00000095, 0x00000fff},
 119         {0x00000096, 0x00116fff},
 120         {0x00000097, 0x60010000},
 121         {0x00000098, 0x10010000},
 122         {0x00000099, 0x00006000},
 123         {0x0000009a, 0x00001000},
 124         {0x0000009f, 0x00936a00}
 125 };
 126
 127 static const u32 caicos_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
 128         {0x00000077, 0xff010100},
 129         {0x00000078, 0x00000000},
 130         {0x00000079, 0x00001434},
 131         {0x0000007a, 0xcc08ec08},
 132         {0x0000007b, 0x00040000},
 133         {0x0000007c, 0x000080c0},
 134         {0x0000007d, 0x09000000},
 135         {0x0000007e, 0x00210404},
 136         {0x00000081, 0x08a8e800},
 137         {0x00000082, 0x00030444},
 138         {0x00000083, 0x00000000},
 139         {0x00000085, 0x00000001},
 140         {0x00000086, 0x00000002},
 141         {0x00000087, 0x48490000},
 142         {0x00000088, 0x20244647},
 143         {0x00000089, 0x00000005},
 144         {0x0000008b, 0x66030000},
 145         {0x0000008c, 0x00006603},
 146         {0x0000008d, 0x00000100},
 147         {0x0000008f, 0x00001c0a},
 148         {0x00000090, 0xff000001},
 149         {0x00000094, 0x00101101},
 150         {0x00000095, 0x00000fff},
 151         {0x00000096, 0x00116fff},
 152         {0x00000097, 0x60010000},
 153         {0x00000098, 0x10010000},
 154         {0x00000099, 0x00006000},
 155         {0x0000009a, 0x00001000},
 156         {0x0000009f, 0x00916a00}
 157 };
 158
 159 static const u32 cayman_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
 160         {0x00000077, 0xff010100},
 161         {0x00000078, 0x00000000},
 162         {0x00000079, 0x00001434},
 163         {0x0000007a, 0xcc08ec08},
 164         {0x0000007b, 0x00040000},
 165         {0x0000007c, 0x000080c0},
 166         {0x0000007d, 0x09000000},
 167         {0x0000007e, 0x00210404},
 168         {0x00000081, 0x08a8e800},
 169         {0x00000082, 0x00030444},
 170         {0x00000083, 0x00000000},
 171         {0x00000085, 0x00000001},
 172         {0x00000086, 0x00000002},
 173         {0x00000087, 0x48490000},
 174         {0x00000088, 0x20244647},
 175         {0x00000089, 0x00000005},
 176         {0x0000008b, 0x66030000},
 177         {0x0000008c, 0x00006603},
 178         {0x0000008d, 0x00000100},
 179         {0x0000008f, 0x00001c0a},
 180         {0x00000090, 0xff000001},
 181         {0x00000094, 0x00101101},
 182         {0x00000095, 0x00000fff},
 183         {0x00000096, 0x00116fff},
 184         {0x00000097, 0x60010000},
 185         {0x00000098, 0x10010000},
 186         {0x00000099, 0x00006000},
 187         {0x0000009a, 0x00001000},
 188         {0x0000009f, 0x00976b00}
 189 };
 190
 191 int btc_mc_load_microcode(struct radeon_device *rdev)
 192 {
 193         const __be32 *fw_data;
 194         u32 mem_type, running, blackout = 0;
 195         u32 *io_mc_regs;
 196         int i, ucode_size, regs_size;
 197
 198         if (!rdev->mc_fw)
 199                 return -EINVAL;
 200
 201         switch (rdev->family) {
 202         case CHIP_BARTS:
 203                 io_mc_regs = (u32 *)&barts_io_mc_regs;
 204                 ucode_size = BTC_MC_UCODE_SIZE;
 205                 regs_size = BTC_IO_MC_REGS_SIZE;
 206                 break;
 207         case CHIP_TURKS:
 208                 io_mc_regs = (u32 *)&turks_io_mc_regs;
 209                 ucode_size = BTC_MC_UCODE_SIZE;
 210                 regs_size = BTC_IO_MC_REGS_SIZE;
 211                 break;
 212         case CHIP_CAICOS:
 213         default:
 214                 io_mc_regs = (u32 *)&caicos_io_mc_regs;
 215                 ucode_size = BTC_MC_UCODE_SIZE;
 216                 regs_size = BTC_IO_MC_REGS_SIZE;
 217                 break;
 218         case CHIP_CAYMAN:
 219                 io_mc_regs = (u32 *)&cayman_io_mc_regs;
 220                 ucode_size = CAYMAN_MC_UCODE_SIZE;
 221                 regs_size = BTC_IO_MC_REGS_SIZE;
 222                 break;
 223         }
 224
 225         mem_type = (RREG32(MC_SEQ_MISC0) & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT;
 226         running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
 227
 228         if ((mem_type == MC_SEQ_MISC0_GDDR5_VALUE) && (running == 0)) {
 229                 if (running) {
 230                         blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
 231                         WREG32(MC_SHARED_BLACKOUT_CNTL, 1);
 232                 }
 233
 234                 /* reset the engine and set to writable */
 235                 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
 236                 WREG32(MC_SEQ_SUP_CNTL, 0x00000010);
 237
 238                 /* load mc io regs */
 239                 for (i = 0; i < regs_size; i++) {
 240                         WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);
 241                         WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);
 242                 }
 243                 /* load the MC ucode */
 244                 fw_data = (const __be32 *)rdev->mc_fw->data;
 245                 for (i = 0; i < ucode_size; i++)
 246                         WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));
 247
 248                 /* put the engine back into the active state */
 249                 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
 250                 WREG32(MC_SEQ_SUP_CNTL, 0x00000004);
 251                 WREG32(MC_SEQ_SUP_CNTL, 0x00000001);
 252
 253                 /* wait for training to complete */
 254                 while (!(RREG32(MC_IO_PAD_CNTL_D0) & MEM_FALL_OUT_CMD))
 255                         udelay(10);
 256
 257                 if (running)
 258                         WREG32(MC_SHARED_BLACKOUT_CNTL, blackout);
 259         }
 260
 261         return 0;
 262 }
 263
 264 int ni_init_microcode(struct radeon_device *rdev)
 265 {
 266         struct platform_device *pdev;
 267         const char *chip_name;
 268         const char *rlc_chip_name;
 269         size_t pfp_req_size, me_req_size, rlc_req_size, mc_req_size;
 270         char fw_name[30];
 271         int err;
 272
 273         DRM_DEBUG("\n");
 274
 275         pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
 276         err = IS_ERR(pdev);
 277         if (err) {
 278                 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
 279                 return -EINVAL;
 280         }
 281
 282         switch (rdev->family) {
 283         case CHIP_BARTS:
 284                 chip_name = "BARTS";
 285                 rlc_chip_name = "BTC";
 286                 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
 287                 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
 288                 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
 289                 mc_req_size = BTC_MC_UCODE_SIZE * 4;
 290                 break;
 291         case CHIP_TURKS:
 292                 chip_name = "TURKS";
 293                 rlc_chip_name = "BTC";
 294                 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
 295                 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
 296                 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
 297                 mc_req_size = BTC_MC_UCODE_SIZE * 4;
 298                 break;
 299         case CHIP_CAICOS:
 300                 chip_name = "CAICOS";
 301                 rlc_chip_name = "BTC";
 302                 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
 303                 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
 304                 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
 305                 mc_req_size = BTC_MC_UCODE_SIZE * 4;
 306                 break;
 307         case CHIP_CAYMAN:
 308                 chip_name = "CAYMAN";
 309                 rlc_chip_name = "CAYMAN";
 310                 pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4;
 311                 me_req_size = CAYMAN_PM4_UCODE_SIZE * 4;
 312                 rlc_req_size = CAYMAN_RLC_UCODE_SIZE * 4;
 313                 mc_req_size = CAYMAN_MC_UCODE_SIZE * 4;
 314                 break;
 315         default: BUG();
 316         }
 317
 318         DRM_INFO("Loading %s Microcode\n", chip_name);
 319
 320         snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
 321         err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
 322         if (err)
 323                 goto out;
 324         if (rdev->pfp_fw->size != pfp_req_size) {
 325                 printk(KERN_ERR
 326                        "ni_cp: Bogus length %zu in firmware \"%s\"\n",
 327                        rdev->pfp_fw->size, fw_name);
 328                 err = -EINVAL;
 329                 goto out;
 330         }
 331
 332         snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
 333         err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
 334         if (err)
 335                 goto out;
 336         if (rdev->me_fw->size != me_req_size) {
 337                 printk(KERN_ERR
 338                        "ni_cp: Bogus length %zu in firmware \"%s\"\n",
 339                        rdev->me_fw->size, fw_name);
 340                 err = -EINVAL;
 341         }
 342
 343         snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
 344         err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
 345         if (err)
 346                 goto out;
 347         if (rdev->rlc_fw->size != rlc_req_size) {
 348                 printk(KERN_ERR
 349                        "ni_rlc: Bogus length %zu in firmware \"%s\"\n",
 350                        rdev->rlc_fw->size, fw_name);
 351                 err = -EINVAL;
 352         }
 353
 354         snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
 355         err = request_firmware(&rdev->mc_fw, fw_name, &pdev->dev);
 356         if (err)
 357                 goto out;
 358         if (rdev->mc_fw->size != mc_req_size) {
 359                 printk(KERN_ERR
 360                        "ni_mc: Bogus length %zu in firmware \"%s\"\n",
 361                        rdev->mc_fw->size, fw_name);
 362                 err = -EINVAL;
 363         }
 364 out:
 365         platform_device_unregister(pdev);
 366
 367         if (err) {
 368                 if (err != -EINVAL)
 369                         printk(KERN_ERR
 370                                "ni_cp: Failed to load firmware \"%s\"\n",
 371                                fw_name);
 372                 release_firmware(rdev->pfp_fw);
 373                 rdev->pfp_fw = NULL;
 374                 release_firmware(rdev->me_fw);
 375                 rdev->me_fw = NULL;
 376                 release_firmware(rdev->rlc_fw);
 377                 rdev->rlc_fw = NULL;
 378                 release_firmware(rdev->mc_fw);
 379                 rdev->mc_fw = NULL;
 380         }
 381         return err;
 382 }
 383