Pileus Git - ~andy/linux/blob - drivers/gpu/drm/radeon/evergreen_cs.c

   1 /*
   2  * Copyright 2010 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include "drmP.h"
  29 #include "radeon.h"
  30 #include "evergreend.h"
  31 #include "evergreen_reg_safe.h"
  32 #include "cayman_reg_safe.h"
  33
  34 #define MAX(a,b)                   (((a)>(b))?(a):(b))
  35 #define MIN(a,b)                   (((a)<(b))?(a):(b))
  36
  37 static int evergreen_cs_packet_next_reloc(struct radeon_cs_parser *p,
  38                                           struct radeon_cs_reloc **cs_reloc);
  39
  40 struct evergreen_cs_track {
  41         u32                     group_size;
  42         u32                     nbanks;
  43         u32                     npipes;
  44         u32                     row_size;
  45         /* value we track */
  46         u32                     nsamples;               /* unused */
  47         struct radeon_bo        *cb_color_bo[12];
  48         u32                     cb_color_bo_offset[12];
  49         struct radeon_bo        *cb_color_fmask_bo[8];  /* unused */
  50         struct radeon_bo        *cb_color_cmask_bo[8];  /* unused */
  51         u32                     cb_color_info[12];
  52         u32                     cb_color_view[12];
  53         u32                     cb_color_pitch[12];
  54         u32                     cb_color_slice[12];
  55         u32                     cb_color_attrib[12];
  56         u32                     cb_color_cmask_slice[8];/* unused */
  57         u32                     cb_color_fmask_slice[8];/* unused */
  58         u32                     cb_target_mask;
  59         u32                     cb_shader_mask; /* unused */
  60         u32                     vgt_strmout_config;
  61         u32                     vgt_strmout_buffer_config;
  62         struct radeon_bo        *vgt_strmout_bo[4];
  63         u32                     vgt_strmout_bo_offset[4];
  64         u32                     vgt_strmout_size[4];
  65         u32                     db_depth_control;
  66         u32                     db_depth_view;
  67         u32                     db_depth_slice;
  68         u32                     db_depth_size;
  69         u32                     db_z_info;
  70         u32                     db_z_read_offset;
  71         u32                     db_z_write_offset;
  72         struct radeon_bo        *db_z_read_bo;
  73         struct radeon_bo        *db_z_write_bo;
  74         u32                     db_s_info;
  75         u32                     db_s_read_offset;
  76         u32                     db_s_write_offset;
  77         struct radeon_bo        *db_s_read_bo;
  78         struct radeon_bo        *db_s_write_bo;
  79         bool                    sx_misc_kill_all_prims;
  80         bool                    cb_dirty;
  81         bool                    db_dirty;
  82         bool                    streamout_dirty;
  83 };
  84
  85 static u32 evergreen_cs_get_aray_mode(u32 tiling_flags)
  86 {
  87         if (tiling_flags & RADEON_TILING_MACRO)
  88                 return ARRAY_2D_TILED_THIN1;
  89         else if (tiling_flags & RADEON_TILING_MICRO)
  90                 return ARRAY_1D_TILED_THIN1;
  91         else
  92                 return ARRAY_LINEAR_GENERAL;
  93 }
  94
  95 static u32 evergreen_cs_get_num_banks(u32 nbanks)
  96 {
  97         switch (nbanks) {
  98         case 2:
  99                 return ADDR_SURF_2_BANK;
 100         case 4:
 101                 return ADDR_SURF_4_BANK;
 102         case 8:
 103         default:
 104                 return ADDR_SURF_8_BANK;
 105         case 16:
 106                 return ADDR_SURF_16_BANK;
 107         }
 108 }
 109
 110 static void evergreen_cs_track_init(struct evergreen_cs_track *track)
 111 {
 112         int i;
 113
 114         for (i = 0; i < 8; i++) {
 115                 track->cb_color_fmask_bo[i] = NULL;
 116                 track->cb_color_cmask_bo[i] = NULL;
 117                 track->cb_color_cmask_slice[i] = 0;
 118                 track->cb_color_fmask_slice[i] = 0;
 119         }
 120
 121         for (i = 0; i < 12; i++) {
 122                 track->cb_color_bo[i] = NULL;
 123                 track->cb_color_bo_offset[i] = 0xFFFFFFFF;
 124                 track->cb_color_info[i] = 0;
 125                 track->cb_color_view[i] = 0xFFFFFFFF;
 126                 track->cb_color_pitch[i] = 0;
 127                 track->cb_color_slice[i] = 0;
 128         }
 129         track->cb_target_mask = 0xFFFFFFFF;
 130         track->cb_shader_mask = 0xFFFFFFFF;
 131         track->cb_dirty = true;
 132
 133         track->db_depth_view = 0xFFFFC000;
 134         track->db_depth_size = 0xFFFFFFFF;
 135         track->db_depth_control = 0xFFFFFFFF;
 136         track->db_z_info = 0xFFFFFFFF;
 137         track->db_z_read_offset = 0xFFFFFFFF;
 138         track->db_z_write_offset = 0xFFFFFFFF;
 139         track->db_z_read_bo = NULL;
 140         track->db_z_write_bo = NULL;
 141         track->db_s_info = 0xFFFFFFFF;
 142         track->db_s_read_offset = 0xFFFFFFFF;
 143         track->db_s_write_offset = 0xFFFFFFFF;
 144         track->db_s_read_bo = NULL;
 145         track->db_s_write_bo = NULL;
 146         track->db_dirty = true;
 147
 148         for (i = 0; i < 4; i++) {
 149                 track->vgt_strmout_size[i] = 0;
 150                 track->vgt_strmout_bo[i] = NULL;
 151                 track->vgt_strmout_bo_offset[i] = 0xFFFFFFFF;
 152         }
 153         track->streamout_dirty = true;
 154         track->sx_misc_kill_all_prims = false;
 155 }
 156
 157 struct eg_surface {
 158         /* value gathered from cs */
 159         unsigned        nbx;
 160         unsigned        nby;
 161         unsigned        format;
 162         unsigned        mode;
 163         unsigned        nbanks;
 164         unsigned        bankw;
 165         unsigned        bankh;
 166         unsigned        tsplit;
 167         unsigned        mtilea;
 168         unsigned        nsamples;
 169         /* output value */
 170         unsigned        bpe;
 171         unsigned        layer_size;
 172         unsigned        palign;
 173         unsigned        halign;
 174         unsigned long   base_align;
 175 };
 176
 177 static int evergreen_surface_check_linear(struct radeon_cs_parser *p,
 178                                           struct eg_surface *surf,
 179                                           const char *prefix)
 180 {
 181         surf->layer_size = surf->nbx * surf->nby * surf->bpe * surf->nsamples;
 182         surf->base_align = surf->bpe;
 183         surf->palign = 1;
 184         surf->halign = 1;
 185         return 0;
 186 }
 187
 188 static int evergreen_surface_check_linear_aligned(struct radeon_cs_parser *p,
 189                                                   struct eg_surface *surf,
 190                                                   const char *prefix)
 191 {
 192         struct evergreen_cs_track *track = p->track;
 193         unsigned palign;
 194
 195         palign = MAX(64, track->group_size / surf->bpe);
 196         surf->layer_size = surf->nbx * surf->nby * surf->bpe * surf->nsamples;
 197         surf->base_align = track->group_size;
 198         surf->palign = palign;
 199         surf->halign = 1;
 200         if (surf->nbx & (palign - 1)) {
 201                 if (prefix) {
 202                         dev_warn(p->dev, "%s:%d %s pitch %d invalid must be aligned with %d\n",
 203                                  __func__, __LINE__, prefix, surf->nbx, palign);
 204                 }
 205                 return -EINVAL;
 206         }
 207         return 0;
 208 }
 209
 210 static int evergreen_surface_check_1d(struct radeon_cs_parser *p,
 211                                       struct eg_surface *surf,
 212                                       const char *prefix)
 213 {
 214         struct evergreen_cs_track *track = p->track;
 215         unsigned palign;
 216
 217         palign = track->group_size / (8 * surf->bpe * surf->nsamples);
 218         palign = MAX(8, palign);
 219         surf->layer_size = surf->nbx * surf->nby * surf->bpe;
 220         surf->base_align = track->group_size;
 221         surf->palign = palign;
 222         surf->halign = 8;
 223         if ((surf->nbx & (palign - 1))) {
 224                 if (prefix) {
 225                         dev_warn(p->dev, "%s:%d %s pitch %d invalid must be aligned with %d (%d %d %d)\n",
 226                                  __func__, __LINE__, prefix, surf->nbx, palign,
 227                                  track->group_size, surf->bpe, surf->nsamples);
 228                 }
 229                 return -EINVAL;
 230         }
 231         if ((surf->nby & (8 - 1))) {
 232                 if (prefix) {
 233                         dev_warn(p->dev, "%s:%d %s height %d invalid must be aligned with 8\n",
 234                                  __func__, __LINE__, prefix, surf->nby);
 235                 }
 236                 return -EINVAL;
 237         }
 238         return 0;
 239 }
 240
 241 static int evergreen_surface_check_2d(struct radeon_cs_parser *p,
 242                                       struct eg_surface *surf,
 243                                       const char *prefix)
 244 {
 245         struct evergreen_cs_track *track = p->track;
 246         unsigned palign, halign, tileb, slice_pt;
 247
 248         tileb = 64 * surf->bpe * surf->nsamples;
 249         palign = track->group_size / (8 * surf->bpe * surf->nsamples);
 250         palign = MAX(8, palign);
 251         slice_pt = 1;
 252         if (tileb > surf->tsplit) {
 253                 slice_pt = tileb / surf->tsplit;
 254         }
 255         tileb = tileb / slice_pt;
 256         /* macro tile width & height */
 257         palign = (8 * surf->bankw * track->npipes) * surf->mtilea;
 258         halign = (8 * surf->bankh * surf->nbanks) / surf->mtilea;
 259         surf->layer_size = surf->nbx * surf->nby * surf->bpe * slice_pt;
 260         surf->base_align = (palign / 8) * (halign / 8) * tileb;
 261         surf->palign = palign;
 262         surf->halign = halign;
 263
 264         if ((surf->nbx & (palign - 1))) {
 265                 if (prefix) {
 266                         dev_warn(p->dev, "%s:%d %s pitch %d invalid must be aligned with %d\n",
 267                                  __func__, __LINE__, prefix, surf->nbx, palign);
 268                 }
 269                 return -EINVAL;
 270         }
 271         if ((surf->nby & (halign - 1))) {
 272                 if (prefix) {
 273                         dev_warn(p->dev, "%s:%d %s height %d invalid must be aligned with %d\n",
 274                                  __func__, __LINE__, prefix, surf->nby, halign);
 275                 }
 276                 return -EINVAL;
 277         }
 278
 279         return 0;
 280 }
 281
 282 static int evergreen_surface_check(struct radeon_cs_parser *p,
 283                                    struct eg_surface *surf,
 284                                    const char *prefix)
 285 {
 286         /* some common value computed here */
 287         surf->bpe = r600_fmt_get_blocksize(surf->format);
 288
 289         switch (surf->mode) {
 290         case ARRAY_LINEAR_GENERAL:
 291                 return evergreen_surface_check_linear(p, surf, prefix);
 292         case ARRAY_LINEAR_ALIGNED:
 293                 return evergreen_surface_check_linear_aligned(p, surf, prefix);
 294         case ARRAY_1D_TILED_THIN1:
 295                 return evergreen_surface_check_1d(p, surf, prefix);
 296         case ARRAY_2D_TILED_THIN1:
 297                 return evergreen_surface_check_2d(p, surf, prefix);
 298         default:
 299                 dev_warn(p->dev, "%s:%d %s invalid array mode %d\n",
 300                                 __func__, __LINE__, prefix, surf->mode);
 301                 return -EINVAL;
 302         }
 303         return -EINVAL;
 304 }
 305
 306 static int evergreen_surface_value_conv_check(struct radeon_cs_parser *p,
 307                                               struct eg_surface *surf,
 308                                               const char *prefix)
 309 {
 310         switch (surf->mode) {
 311         case ARRAY_2D_TILED_THIN1:
 312                 break;
 313         case ARRAY_LINEAR_GENERAL:
 314         case ARRAY_LINEAR_ALIGNED:
 315         case ARRAY_1D_TILED_THIN1:
 316                 return 0;
 317         default:
 318                 dev_warn(p->dev, "%s:%d %s invalid array mode %d\n",
 319                                 __func__, __LINE__, prefix, surf->mode);
 320                 return -EINVAL;
 321         }
 322
 323         switch (surf->nbanks) {
 324         case 0: surf->nbanks = 2; break;
 325         case 1: surf->nbanks = 4; break;
 326         case 2: surf->nbanks = 8; break;
 327         case 3: surf->nbanks = 16; break;
 328         default:
 329                 dev_warn(p->dev, "%s:%d %s invalid number of banks %d\n",
 330                          __func__, __LINE__, prefix, surf->nbanks);
 331                 return -EINVAL;
 332         }
 333         switch (surf->bankw) {
 334         case 0: surf->bankw = 1; break;
 335         case 1: surf->bankw = 2; break;
 336         case 2: surf->bankw = 4; break;
 337         case 3: surf->bankw = 8; break;
 338         default:
 339                 dev_warn(p->dev, "%s:%d %s invalid bankw %d\n",
 340                          __func__, __LINE__, prefix, surf->bankw);
 341                 return -EINVAL;
 342         }
 343         switch (surf->bankh) {
 344         case 0: surf->bankh = 1; break;
 345         case 1: surf->bankh = 2; break;
 346         case 2: surf->bankh = 4; break;
 347         case 3: surf->bankh = 8; break;
 348         default:
 349                 dev_warn(p->dev, "%s:%d %s invalid bankh %d\n",
 350                          __func__, __LINE__, prefix, surf->bankh);
 351                 return -EINVAL;
 352         }
 353         switch (surf->mtilea) {
 354         case 0: surf->mtilea = 1; break;
 355         case 1: surf->mtilea = 2; break;
 356         case 2: surf->mtilea = 4; break;
 357         case 3: surf->mtilea = 8; break;
 358         default:
 359                 dev_warn(p->dev, "%s:%d %s invalid macro tile aspect %d\n",
 360                          __func__, __LINE__, prefix, surf->mtilea);
 361                 return -EINVAL;
 362         }
 363         switch (surf->tsplit) {
 364         case 0: surf->tsplit = 64; break;
 365         case 1: surf->tsplit = 128; break;
 366         case 2: surf->tsplit = 256; break;
 367         case 3: surf->tsplit = 512; break;
 368         case 4: surf->tsplit = 1024; break;
 369         case 5: surf->tsplit = 2048; break;
 370         case 6: surf->tsplit = 4096; break;
 371         default:
 372                 dev_warn(p->dev, "%s:%d %s invalid tile split %d\n",
 373                          __func__, __LINE__, prefix, surf->tsplit);
 374                 return -EINVAL;
 375         }
 376         return 0;
 377 }
 378
 379 static int evergreen_cs_track_validate_cb(struct radeon_cs_parser *p, unsigned id)
 380 {
 381         struct evergreen_cs_track *track = p->track;
 382         struct eg_surface surf;
 383         unsigned pitch, slice, mslice;
 384         unsigned long offset;
 385         int r;
 386
 387         mslice = G_028C6C_SLICE_MAX(track->cb_color_view[id]) + 1;
 388         pitch = track->cb_color_pitch[id];
 389         slice = track->cb_color_slice[id];
 390         surf.nbx = (pitch + 1) * 8;
 391         surf.nby = ((slice + 1) * 64) / surf.nbx;
 392         surf.mode = G_028C70_ARRAY_MODE(track->cb_color_info[id]);
 393         surf.format = G_028C70_FORMAT(track->cb_color_info[id]);
 394         surf.tsplit = G_028C74_TILE_SPLIT(track->cb_color_attrib[id]);
 395         surf.nbanks = G_028C74_NUM_BANKS(track->cb_color_attrib[id]);
 396         surf.bankw = G_028C74_BANK_WIDTH(track->cb_color_attrib[id]);
 397         surf.bankh = G_028C74_BANK_HEIGHT(track->cb_color_attrib[id]);
 398         surf.mtilea = G_028C74_MACRO_TILE_ASPECT(track->cb_color_attrib[id]);
 399         surf.nsamples = 1;
 400
 401         if (!r600_fmt_is_valid_color(surf.format)) {
 402                 dev_warn(p->dev, "%s:%d cb invalid format %d for %d (0x%08x)\n",
 403                          __func__, __LINE__, surf.format,
 404                         id, track->cb_color_info[id]);
 405                 return -EINVAL;
 406         }
 407
 408         r = evergreen_surface_value_conv_check(p, &surf, "cb");
 409         if (r) {
 410                 return r;
 411         }
 412
 413         r = evergreen_surface_check(p, &surf, "cb");
 414         if (r) {
 415                 dev_warn(p->dev, "%s:%d cb[%d] invalid (0x%08x 0x%08x 0x%08x 0x%08x)\n",
 416                          __func__, __LINE__, id, track->cb_color_pitch[id],
 417                          track->cb_color_slice[id], track->cb_color_attrib[id],
 418                          track->cb_color_info[id]);
 419                 return r;
 420         }
 421
 422         offset = track->cb_color_bo_offset[id] << 8;
 423         if (offset & (surf.base_align - 1)) {
 424                 dev_warn(p->dev, "%s:%d cb[%d] bo base %ld not aligned with %ld\n",
 425                          __func__, __LINE__, id, offset, surf.base_align);
 426                 return -EINVAL;
 427         }
 428
 429         offset += surf.layer_size * mslice;
 430         if (offset > radeon_bo_size(track->cb_color_bo[id])) {
 431                 dev_warn(p->dev, "%s:%d cb[%d] bo too small (layer size %d, "
 432                          "offset %d, max layer %d, bo size %ld, slice %d)\n",
 433                          __func__, __LINE__, id, surf.layer_size,
 434                         track->cb_color_bo_offset[id] << 8, mslice,
 435                         radeon_bo_size(track->cb_color_bo[id]), slice);
 436                 dev_warn(p->dev, "%s:%d problematic surf: (%d %d) (%d %d %d %d %d %d %d)\n",
 437                          __func__, __LINE__, surf.nbx, surf.nby,
 438                         surf.mode, surf.bpe, surf.nsamples,
 439                         surf.bankw, surf.bankh,
 440                         surf.tsplit, surf.mtilea);
 441                 return -EINVAL;
 442         }
 443
 444         return 0;
 445 }
 446
 447 static int evergreen_cs_track_validate_stencil(struct radeon_cs_parser *p)
 448 {
 449         struct evergreen_cs_track *track = p->track;
 450         struct eg_surface surf;
 451         unsigned pitch, slice, mslice;
 452         unsigned long offset;
 453         int r;
 454
 455         mslice = G_028008_SLICE_MAX(track->db_depth_view) + 1;
 456         pitch = G_028058_PITCH_TILE_MAX(track->db_depth_size);
 457         slice = track->db_depth_slice;
 458         surf.nbx = (pitch + 1) * 8;
 459         surf.nby = ((slice + 1) * 64) / surf.nbx;
 460         surf.mode = G_028040_ARRAY_MODE(track->db_z_info);
 461         surf.format = G_028044_FORMAT(track->db_s_info);
 462         surf.tsplit = G_028044_TILE_SPLIT(track->db_s_info);
 463         surf.nbanks = G_028040_NUM_BANKS(track->db_z_info);
 464         surf.bankw = G_028040_BANK_WIDTH(track->db_z_info);
 465         surf.bankh = G_028040_BANK_HEIGHT(track->db_z_info);
 466         surf.mtilea = G_028040_MACRO_TILE_ASPECT(track->db_z_info);
 467         surf.nsamples = 1;
 468
 469         if (surf.format != 1) {
 470                 dev_warn(p->dev, "%s:%d stencil invalid format %d\n",
 471                          __func__, __LINE__, surf.format);
 472                 return -EINVAL;
 473         }
 474         /* replace by color format so we can use same code */
 475         surf.format = V_028C70_COLOR_8;
 476
 477         r = evergreen_surface_value_conv_check(p, &surf, "stencil");
 478         if (r) {
 479                 return r;
 480         }
 481
 482         r = evergreen_surface_check(p, &surf, NULL);
 483         if (r) {
 484                 /* old userspace doesn't compute proper depth/stencil alignment
 485                  * check that alignment against a bigger byte per elements and
 486                  * only report if that alignment is wrong too.
 487                  */
 488                 surf.format = V_028C70_COLOR_8_8_8_8;
 489                 r = evergreen_surface_check(p, &surf, "stencil");
 490                 if (r) {
 491                         dev_warn(p->dev, "%s:%d stencil invalid (0x%08x 0x%08x 0x%08x 0x%08x)\n",
 492                                  __func__, __LINE__, track->db_depth_size,
 493                                  track->db_depth_slice, track->db_s_info, track->db_z_info);
 494                 }
 495                 return r;
 496         }
 497
 498         offset = track->db_s_read_offset << 8;
 499         if (offset & (surf.base_align - 1)) {
 500                 dev_warn(p->dev, "%s:%d stencil read bo base %ld not aligned with %ld\n",
 501                          __func__, __LINE__, offset, surf.base_align);
 502                 return -EINVAL;
 503         }
 504         offset += surf.layer_size * mslice;
 505         if (offset > radeon_bo_size(track->db_s_read_bo)) {
 506                 dev_warn(p->dev, "%s:%d stencil read bo too small (layer size %d, "
 507                          "offset %ld, max layer %d, bo size %ld)\n",
 508                          __func__, __LINE__, surf.layer_size,
 509                         (unsigned long)track->db_s_read_offset << 8, mslice,
 510                         radeon_bo_size(track->db_s_read_bo));
 511                 dev_warn(p->dev, "%s:%d stencil invalid (0x%08x 0x%08x 0x%08x 0x%08x)\n",
 512                          __func__, __LINE__, track->db_depth_size,
 513                          track->db_depth_slice, track->db_s_info, track->db_z_info);
 514                 return -EINVAL;
 515         }
 516
 517         offset = track->db_s_write_offset << 8;
 518         if (offset & (surf.base_align - 1)) {
 519                 dev_warn(p->dev, "%s:%d stencil write bo base %ld not aligned with %ld\n",
 520                          __func__, __LINE__, offset, surf.base_align);
 521                 return -EINVAL;
 522         }
 523         offset += surf.layer_size * mslice;
 524         if (offset > radeon_bo_size(track->db_s_write_bo)) {
 525                 dev_warn(p->dev, "%s:%d stencil write bo too small (layer size %d, "
 526                          "offset %ld, max layer %d, bo size %ld)\n",
 527                          __func__, __LINE__, surf.layer_size,
 528                         (unsigned long)track->db_s_write_offset << 8, mslice,
 529                         radeon_bo_size(track->db_s_write_bo));
 530                 return -EINVAL;
 531         }
 532
 533         return 0;
 534 }
 535
 536 static int evergreen_cs_track_validate_depth(struct radeon_cs_parser *p)
 537 {
 538         struct evergreen_cs_track *track = p->track;
 539         struct eg_surface surf;
 540         unsigned pitch, slice, mslice;
 541         unsigned long offset;
 542         int r;
 543
 544         mslice = G_028008_SLICE_MAX(track->db_depth_view) + 1;
 545         pitch = G_028058_PITCH_TILE_MAX(track->db_depth_size);
 546         slice = track->db_depth_slice;
 547         surf.nbx = (pitch + 1) * 8;
 548         surf.nby = ((slice + 1) * 64) / surf.nbx;
 549         surf.mode = G_028040_ARRAY_MODE(track->db_z_info);
 550         surf.format = G_028040_FORMAT(track->db_z_info);
 551         surf.tsplit = G_028040_TILE_SPLIT(track->db_z_info);
 552         surf.nbanks = G_028040_NUM_BANKS(track->db_z_info);
 553         surf.bankw = G_028040_BANK_WIDTH(track->db_z_info);
 554         surf.bankh = G_028040_BANK_HEIGHT(track->db_z_info);
 555         surf.mtilea = G_028040_MACRO_TILE_ASPECT(track->db_z_info);
 556         surf.nsamples = 1;
 557
 558         switch (surf.format) {
 559         case V_028040_Z_16:
 560                 surf.format = V_028C70_COLOR_16;
 561                 break;
 562         case V_028040_Z_24:
 563         case V_028040_Z_32_FLOAT:
 564                 surf.format = V_028C70_COLOR_8_8_8_8;
 565                 break;
 566         default:
 567                 dev_warn(p->dev, "%s:%d depth invalid format %d\n",
 568                          __func__, __LINE__, surf.format);
 569                 return -EINVAL;
 570         }
 571
 572         r = evergreen_surface_value_conv_check(p, &surf, "depth");
 573         if (r) {
 574                 dev_warn(p->dev, "%s:%d depth invalid (0x%08x 0x%08x 0x%08x)\n",
 575                          __func__, __LINE__, track->db_depth_size,
 576                          track->db_depth_slice, track->db_z_info);
 577                 return r;
 578         }
 579
 580         r = evergreen_surface_check(p, &surf, "depth");
 581         if (r) {
 582                 dev_warn(p->dev, "%s:%d depth invalid (0x%08x 0x%08x 0x%08x)\n",
 583                          __func__, __LINE__, track->db_depth_size,
 584                          track->db_depth_slice, track->db_z_info);
 585                 return r;
 586         }
 587
 588         offset = track->db_z_read_offset << 8;
 589         if (offset & (surf.base_align - 1)) {
 590                 dev_warn(p->dev, "%s:%d stencil read bo base %ld not aligned with %ld\n",
 591                          __func__, __LINE__, offset, surf.base_align);
 592                 return -EINVAL;
 593         }
 594         offset += surf.layer_size * mslice;
 595         if (offset > radeon_bo_size(track->db_z_read_bo)) {
 596                 dev_warn(p->dev, "%s:%d depth read bo too small (layer size %d, "
 597                          "offset %ld, max layer %d, bo size %ld)\n",
 598                          __func__, __LINE__, surf.layer_size,
 599                         (unsigned long)track->db_z_read_offset << 8, mslice,
 600                         radeon_bo_size(track->db_z_read_bo));
 601                 return -EINVAL;
 602         }
 603
 604         offset = track->db_z_write_offset << 8;
 605         if (offset & (surf.base_align - 1)) {
 606                 dev_warn(p->dev, "%s:%d stencil write bo base %ld not aligned with %ld\n",
 607                          __func__, __LINE__, offset, surf.base_align);
 608                 return -EINVAL;
 609         }
 610         offset += surf.layer_size * mslice;
 611         if (offset > radeon_bo_size(track->db_z_write_bo)) {
 612                 dev_warn(p->dev, "%s:%d depth write bo too small (layer size %d, "
 613                          "offset %ld, max layer %d, bo size %ld)\n",
 614                          __func__, __LINE__, surf.layer_size,
 615                         (unsigned long)track->db_z_write_offset << 8, mslice,
 616                         radeon_bo_size(track->db_z_write_bo));
 617                 return -EINVAL;
 618         }
 619
 620         return 0;
 621 }
 622
 623 static int evergreen_cs_track_validate_texture(struct radeon_cs_parser *p,
 624                                                struct radeon_bo *texture,
 625                                                struct radeon_bo *mipmap,
 626                                                unsigned idx)
 627 {
 628         struct eg_surface surf;
 629         unsigned long toffset, moffset;
 630         unsigned dim, llevel, mslice, width, height, depth, i;
 631         u32 texdw[8];
 632         int r;
 633
 634         texdw[0] = radeon_get_ib_value(p, idx + 0);
 635         texdw[1] = radeon_get_ib_value(p, idx + 1);
 636         texdw[2] = radeon_get_ib_value(p, idx + 2);
 637         texdw[3] = radeon_get_ib_value(p, idx + 3);
 638         texdw[4] = radeon_get_ib_value(p, idx + 4);
 639         texdw[5] = radeon_get_ib_value(p, idx + 5);
 640         texdw[6] = radeon_get_ib_value(p, idx + 6);
 641         texdw[7] = radeon_get_ib_value(p, idx + 7);
 642         dim = G_030000_DIM(texdw[0]);
 643         llevel = G_030014_LAST_LEVEL(texdw[5]);
 644         mslice = G_030014_LAST_ARRAY(texdw[5]) + 1;
 645         width = G_030000_TEX_WIDTH(texdw[0]) + 1;
 646         height =  G_030004_TEX_HEIGHT(texdw[1]) + 1;
 647         depth = G_030004_TEX_DEPTH(texdw[1]) + 1;
 648         surf.format = G_03001C_DATA_FORMAT(texdw[7]);
 649         surf.nbx = (G_030000_PITCH(texdw[0]) + 1) * 8;
 650         surf.nbx = r600_fmt_get_nblocksx(surf.format, surf.nbx);
 651         surf.nby = r600_fmt_get_nblocksy(surf.format, height);
 652         surf.mode = G_030004_ARRAY_MODE(texdw[1]);
 653         surf.tsplit = G_030018_TILE_SPLIT(texdw[6]);
 654         surf.nbanks = G_03001C_NUM_BANKS(texdw[7]);
 655         surf.bankw = G_03001C_BANK_WIDTH(texdw[7]);
 656         surf.bankh = G_03001C_BANK_HEIGHT(texdw[7]);
 657         surf.mtilea = G_03001C_MACRO_TILE_ASPECT(texdw[7]);
 658         surf.nsamples = 1;
 659         toffset = texdw[2] << 8;
 660         moffset = texdw[3] << 8;
 661
 662         if (!r600_fmt_is_valid_texture(surf.format, p->family)) {
 663                 dev_warn(p->dev, "%s:%d texture invalid format %d\n",
 664                          __func__, __LINE__, surf.format);
 665                 return -EINVAL;
 666         }
 667         switch (dim) {
 668         case V_030000_SQ_TEX_DIM_1D:
 669         case V_030000_SQ_TEX_DIM_2D:
 670         case V_030000_SQ_TEX_DIM_CUBEMAP:
 671         case V_030000_SQ_TEX_DIM_1D_ARRAY:
 672         case V_030000_SQ_TEX_DIM_2D_ARRAY:
 673                 depth = 1;
 674         case V_030000_SQ_TEX_DIM_3D:
 675                 break;
 676         default:
 677                 dev_warn(p->dev, "%s:%d texture invalid dimension %d\n",
 678                          __func__, __LINE__, dim);
 679                 return -EINVAL;
 680         }
 681
 682         r = evergreen_surface_value_conv_check(p, &surf, "texture");
 683         if (r) {
 684                 return r;
 685         }
 686
 687         /* align height */
 688         evergreen_surface_check(p, &surf, NULL);
 689         surf.nby = ALIGN(surf.nby, surf.halign);
 690
 691         r = evergreen_surface_check(p, &surf, "texture");
 692         if (r) {
 693                 dev_warn(p->dev, "%s:%d texture invalid 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
 694                          __func__, __LINE__, texdw[0], texdw[1], texdw[4],
 695                          texdw[5], texdw[6], texdw[7]);
 696                 return r;
 697         }
 698
 699         /* check texture size */
 700         if (toffset & (surf.base_align - 1)) {
 701                 dev_warn(p->dev, "%s:%d texture bo base %ld not aligned with %ld\n",
 702                          __func__, __LINE__, toffset, surf.base_align);
 703                 return -EINVAL;
 704         }
 705         if (moffset & (surf.base_align - 1)) {
 706                 dev_warn(p->dev, "%s:%d mipmap bo base %ld not aligned with %ld\n",
 707                          __func__, __LINE__, moffset, surf.base_align);
 708                 return -EINVAL;
 709         }
 710         if (dim == SQ_TEX_DIM_3D) {
 711                 toffset += surf.layer_size * depth;
 712         } else {
 713                 toffset += surf.layer_size * mslice;
 714         }
 715         if (toffset > radeon_bo_size(texture)) {
 716                 dev_warn(p->dev, "%s:%d texture bo too small (layer size %d, "
 717                          "offset %ld, max layer %d, depth %d, bo size %ld) (%d %d)\n",
 718                          __func__, __LINE__, surf.layer_size,
 719                         (unsigned long)texdw[2] << 8, mslice,
 720                         depth, radeon_bo_size(texture),
 721                         surf.nbx, surf.nby);
 722                 return -EINVAL;
 723         }
 724
 725         /* check mipmap size */
 726         for (i = 1; i <= llevel; i++) {
 727                 unsigned w, h, d;
 728
 729                 w = r600_mip_minify(width, i);
 730                 h = r600_mip_minify(height, i);
 731                 d = r600_mip_minify(depth, i);
 732                 surf.nbx = r600_fmt_get_nblocksx(surf.format, w);
 733                 surf.nby = r600_fmt_get_nblocksy(surf.format, h);
 734
 735                 switch (surf.mode) {
 736                 case ARRAY_2D_TILED_THIN1:
 737                         if (surf.nbx < surf.palign || surf.nby < surf.halign) {
 738                                 surf.mode = ARRAY_1D_TILED_THIN1;
 739                         }
 740                         /* recompute alignment */
 741                         evergreen_surface_check(p, &surf, NULL);
 742                         break;
 743                 case ARRAY_LINEAR_GENERAL:
 744                 case ARRAY_LINEAR_ALIGNED:
 745                 case ARRAY_1D_TILED_THIN1:
 746                         break;
 747                 default:
 748                         dev_warn(p->dev, "%s:%d invalid array mode %d\n",
 749                                  __func__, __LINE__, surf.mode);
 750                         return -EINVAL;
 751                 }
 752                 surf.nbx = ALIGN(surf.nbx, surf.palign);
 753                 surf.nby = ALIGN(surf.nby, surf.halign);
 754
 755                 r = evergreen_surface_check(p, &surf, "mipmap");
 756                 if (r) {
 757                         return r;
 758                 }
 759
 760                 if (dim == SQ_TEX_DIM_3D) {
 761                         moffset += surf.layer_size * d;
 762                 } else {
 763                         moffset += surf.layer_size * mslice;
 764                 }
 765                 if (moffset > radeon_bo_size(mipmap)) {
 766                         dev_warn(p->dev, "%s:%d mipmap [%d] bo too small (layer size %d, "
 767                                         "offset %ld, coffset %ld, max layer %d, depth %d, "
 768                                         "bo size %ld) level0 (%d %d %d)\n",
 769                                         __func__, __LINE__, i, surf.layer_size,
 770                                         (unsigned long)texdw[3] << 8, moffset, mslice,
 771                                         d, radeon_bo_size(mipmap),
 772                                         width, height, depth);
 773                         dev_warn(p->dev, "%s:%d problematic surf: (%d %d) (%d %d %d %d %d %d %d)\n",
 774                                  __func__, __LINE__, surf.nbx, surf.nby,
 775                                 surf.mode, surf.bpe, surf.nsamples,
 776                                 surf.bankw, surf.bankh,
 777                                 surf.tsplit, surf.mtilea);
 778                         return -EINVAL;
 779                 }
 780         }
 781
 782         return 0;
 783 }
 784
 785 static int evergreen_cs_track_check(struct radeon_cs_parser *p)
 786 {
 787         struct evergreen_cs_track *track = p->track;
 788         unsigned tmp, i;
 789         int r;
 790         unsigned buffer_mask = 0;
 791
 792         /* check streamout */
 793         if (track->streamout_dirty && track->vgt_strmout_config) {
 794                 for (i = 0; i < 4; i++) {
 795                         if (track->vgt_strmout_config & (1 << i)) {
 796                                 buffer_mask |= (track->vgt_strmout_buffer_config >> (i * 4)) & 0xf;
 797                         }
 798                 }
 799
 800                 for (i = 0; i < 4; i++) {
 801                         if (buffer_mask & (1 << i)) {
 802                                 if (track->vgt_strmout_bo[i]) {
 803                                         u64 offset = (u64)track->vgt_strmout_bo_offset[i] +
 804                                                         (u64)track->vgt_strmout_size[i];
 805                                         if (offset > radeon_bo_size(track->vgt_strmout_bo[i])) {
 806                                                 DRM_ERROR("streamout %d bo too small: 0x%llx, 0x%lx\n",
 807                                                           i, offset,
 808                                                           radeon_bo_size(track->vgt_strmout_bo[i]));
 809                                                 return -EINVAL;
 810                                         }
 811                                 } else {
 812                                         dev_warn(p->dev, "No buffer for streamout %d\n", i);
 813                                         return -EINVAL;
 814                                 }
 815                         }
 816                 }
 817                 track->streamout_dirty = false;
 818         }
 819
 820         if (track->sx_misc_kill_all_prims)
 821                 return 0;
 822
 823         /* check that we have a cb for each enabled target
 824          */
 825         if (track->cb_dirty) {
 826                 tmp = track->cb_target_mask;
 827                 for (i = 0; i < 8; i++) {
 828                         if ((tmp >> (i * 4)) & 0xF) {
 829                                 /* at least one component is enabled */
 830                                 if (track->cb_color_bo[i] == NULL) {
 831                                         dev_warn(p->dev, "%s:%d mask 0x%08X | 0x%08X no cb for %d\n",
 832                                                 __func__, __LINE__, track->cb_target_mask, track->cb_shader_mask, i);
 833                                         return -EINVAL;
 834                                 }
 835                                 /* check cb */
 836                                 r = evergreen_cs_track_validate_cb(p, i);
 837                                 if (r) {
 838                                         return r;
 839                                 }
 840                         }
 841                 }
 842                 track->cb_dirty = false;
 843         }
 844
 845         if (track->db_dirty) {
 846                 /* Check stencil buffer */
 847                 if (G_028800_STENCIL_ENABLE(track->db_depth_control)) {
 848                         r = evergreen_cs_track_validate_stencil(p);
 849                         if (r)
 850                                 return r;
 851                 }
 852                 /* Check depth buffer */
 853                 if (G_028800_Z_WRITE_ENABLE(track->db_depth_control)) {
 854                         r = evergreen_cs_track_validate_depth(p);
 855                         if (r)
 856                                 return r;
 857                 }
 858                 track->db_dirty = false;
 859         }
 860
 861         return 0;
 862 }
 863
 864 /**
 865  * evergreen_cs_packet_parse() - parse cp packet and point ib index to next packet
 866  * @parser:     parser structure holding parsing context.
 867  * @pkt:        where to store packet informations
 868  *
 869  * Assume that chunk_ib_index is properly set. Will return -EINVAL
 870  * if packet is bigger than remaining ib size. or if packets is unknown.
 871  **/
 872 int evergreen_cs_packet_parse(struct radeon_cs_parser *p,
 873                               struct radeon_cs_packet *pkt,
 874                               unsigned idx)
 875 {
 876         struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
 877         uint32_t header;
 878
 879         if (idx >= ib_chunk->length_dw) {
 880                 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
 881                           idx, ib_chunk->length_dw);
 882                 return -EINVAL;
 883         }
 884         header = radeon_get_ib_value(p, idx);
 885         pkt->idx = idx;
 886         pkt->type = CP_PACKET_GET_TYPE(header);
 887         pkt->count = CP_PACKET_GET_COUNT(header);
 888         pkt->one_reg_wr = 0;
 889         switch (pkt->type) {
 890         case PACKET_TYPE0:
 891                 pkt->reg = CP_PACKET0_GET_REG(header);
 892                 break;
 893         case PACKET_TYPE3:
 894                 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
 895                 break;
 896         case PACKET_TYPE2:
 897                 pkt->count = -1;
 898                 break;
 899         default:
 900                 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
 901                 return -EINVAL;
 902         }
 903         if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
 904                 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
 905                           pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
 906                 return -EINVAL;
 907         }
 908         return 0;
 909 }
 910
 911 /**
 912  * evergreen_cs_packet_next_reloc() - parse next packet which should be reloc packet3
 913  * @parser:             parser structure holding parsing context.
 914  * @data:               pointer to relocation data
 915  * @offset_start:       starting offset
 916  * @offset_mask:        offset mask (to align start offset on)
 917  * @reloc:              reloc informations
 918  *
 919  * Check next packet is relocation packet3, do bo validation and compute
 920  * GPU offset using the provided start.
 921  **/
 922 static int evergreen_cs_packet_next_reloc(struct radeon_cs_parser *p,
 923                                           struct radeon_cs_reloc **cs_reloc)
 924 {
 925         struct radeon_cs_chunk *relocs_chunk;
 926         struct radeon_cs_packet p3reloc;
 927         unsigned idx;
 928         int r;
 929
 930         if (p->chunk_relocs_idx == -1) {
 931                 DRM_ERROR("No relocation chunk !\n");
 932                 return -EINVAL;
 933         }
 934         *cs_reloc = NULL;
 935         relocs_chunk = &p->chunks[p->chunk_relocs_idx];
 936         r = evergreen_cs_packet_parse(p, &p3reloc, p->idx);
 937         if (r) {
 938                 return r;
 939         }
 940         p->idx += p3reloc.count + 2;
 941         if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
 942                 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
 943                           p3reloc.idx);
 944                 return -EINVAL;
 945         }
 946         idx = radeon_get_ib_value(p, p3reloc.idx + 1);
 947         if (idx >= relocs_chunk->length_dw) {
 948                 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
 949                           idx, relocs_chunk->length_dw);
 950                 return -EINVAL;
 951         }
 952         /* FIXME: we assume reloc size is 4 dwords */
 953         *cs_reloc = p->relocs_ptr[(idx / 4)];
 954         return 0;
 955 }
 956
 957 /**
 958  * evergreen_cs_packet_next_vline() - parse userspace VLINE packet
 959  * @parser:             parser structure holding parsing context.
 960  *
 961  * Userspace sends a special sequence for VLINE waits.
 962  * PACKET0 - VLINE_START_END + value
 963  * PACKET3 - WAIT_REG_MEM poll vline status reg
 964  * RELOC (P3) - crtc_id in reloc.
 965  *
 966  * This function parses this and relocates the VLINE START END
 967  * and WAIT_REG_MEM packets to the correct crtc.
 968  * It also detects a switched off crtc and nulls out the
 969  * wait in that case.
 970  */
 971 static int evergreen_cs_packet_parse_vline(struct radeon_cs_parser *p)
 972 {
 973         struct drm_mode_object *obj;
 974         struct drm_crtc *crtc;
 975         struct radeon_crtc *radeon_crtc;
 976         struct radeon_cs_packet p3reloc, wait_reg_mem;
 977         int crtc_id;
 978         int r;
 979         uint32_t header, h_idx, reg, wait_reg_mem_info;
 980         volatile uint32_t *ib;
 981
 982         ib = p->ib->ptr;
 983
 984         /* parse the WAIT_REG_MEM */
 985         r = evergreen_cs_packet_parse(p, &wait_reg_mem, p->idx);
 986         if (r)
 987                 return r;
 988
 989         /* check its a WAIT_REG_MEM */
 990         if (wait_reg_mem.type != PACKET_TYPE3 ||
 991             wait_reg_mem.opcode != PACKET3_WAIT_REG_MEM) {
 992                 DRM_ERROR("vline wait missing WAIT_REG_MEM segment\n");
 993                 return -EINVAL;
 994         }
 995
 996         wait_reg_mem_info = radeon_get_ib_value(p, wait_reg_mem.idx + 1);
 997         /* bit 4 is reg (0) or mem (1) */
 998         if (wait_reg_mem_info & 0x10) {
 999                 DRM_ERROR("vline WAIT_REG_MEM waiting on MEM rather than REG\n");
1000                 return -EINVAL;
1001         }
1002         /* waiting for value to be equal */
1003         if ((wait_reg_mem_info & 0x7) != 0x3) {
1004                 DRM_ERROR("vline WAIT_REG_MEM function not equal\n");
1005                 return -EINVAL;
1006         }
1007         if ((radeon_get_ib_value(p, wait_reg_mem.idx + 2) << 2) != EVERGREEN_VLINE_STATUS) {
1008                 DRM_ERROR("vline WAIT_REG_MEM bad reg\n");
1009                 return -EINVAL;
1010         }
1011
1012         if (radeon_get_ib_value(p, wait_reg_mem.idx + 5) != EVERGREEN_VLINE_STAT) {
1013                 DRM_ERROR("vline WAIT_REG_MEM bad bit mask\n");
1014                 return -EINVAL;
1015         }
1016
1017         /* jump over the NOP */
1018         r = evergreen_cs_packet_parse(p, &p3reloc, p->idx + wait_reg_mem.count + 2);
1019         if (r)
1020                 return r;
1021
1022         h_idx = p->idx - 2;
1023         p->idx += wait_reg_mem.count + 2;
1024         p->idx += p3reloc.count + 2;
1025
1026         header = radeon_get_ib_value(p, h_idx);
1027         crtc_id = radeon_get_ib_value(p, h_idx + 2 + 7 + 1);
1028         reg = CP_PACKET0_GET_REG(header);
1029         obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
1030         if (!obj) {
1031                 DRM_ERROR("cannot find crtc %d\n", crtc_id);
1032                 return -EINVAL;
1033         }
1034         crtc = obj_to_crtc(obj);
1035         radeon_crtc = to_radeon_crtc(crtc);
1036         crtc_id = radeon_crtc->crtc_id;
1037
1038         if (!crtc->enabled) {
1039                 /* if the CRTC isn't enabled - we need to nop out the WAIT_REG_MEM */
1040                 ib[h_idx + 2] = PACKET2(0);
1041                 ib[h_idx + 3] = PACKET2(0);
1042                 ib[h_idx + 4] = PACKET2(0);
1043                 ib[h_idx + 5] = PACKET2(0);
1044                 ib[h_idx + 6] = PACKET2(0);
1045                 ib[h_idx + 7] = PACKET2(0);
1046                 ib[h_idx + 8] = PACKET2(0);
1047         } else {
1048                 switch (reg) {
1049                 case EVERGREEN_VLINE_START_END:
1050                         header &= ~R600_CP_PACKET0_REG_MASK;
1051                         header |= (EVERGREEN_VLINE_START_END + radeon_crtc->crtc_offset) >> 2;
1052                         ib[h_idx] = header;
1053                         ib[h_idx + 4] = (EVERGREEN_VLINE_STATUS + radeon_crtc->crtc_offset) >> 2;
1054                         break;
1055                 default:
1056                         DRM_ERROR("unknown crtc reloc\n");
1057                         return -EINVAL;
1058                 }
1059         }
1060         return 0;
1061 }
1062
1063 static int evergreen_packet0_check(struct radeon_cs_parser *p,
1064                                    struct radeon_cs_packet *pkt,
1065                                    unsigned idx, unsigned reg)
1066 {
1067         int r;
1068
1069         switch (reg) {
1070         case EVERGREEN_VLINE_START_END:
1071                 r = evergreen_cs_packet_parse_vline(p);
1072                 if (r) {
1073                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1074                                         idx, reg);
1075                         return r;
1076                 }
1077                 break;
1078         default:
1079                 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1080                        reg, idx);
1081                 return -EINVAL;
1082         }
1083         return 0;
1084 }
1085
1086 static int evergreen_cs_parse_packet0(struct radeon_cs_parser *p,
1087                                       struct radeon_cs_packet *pkt)
1088 {
1089         unsigned reg, i;
1090         unsigned idx;
1091         int r;
1092
1093         idx = pkt->idx + 1;
1094         reg = pkt->reg;
1095         for (i = 0; i <= pkt->count; i++, idx++, reg += 4) {
1096                 r = evergreen_packet0_check(p, pkt, idx, reg);
1097                 if (r) {
1098                         return r;
1099                 }
1100         }
1101         return 0;
1102 }
1103
1104 /**
1105  * evergreen_cs_check_reg() - check if register is authorized or not
1106  * @parser: parser structure holding parsing context
1107  * @reg: register we are testing
1108  * @idx: index into the cs buffer
1109  *
1110  * This function will test against evergreen_reg_safe_bm and return 0
1111  * if register is safe. If register is not flag as safe this function
1112  * will test it against a list of register needind special handling.
1113  */
1114 static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1115 {
1116         struct evergreen_cs_track *track = (struct evergreen_cs_track *)p->track;
1117         struct radeon_cs_reloc *reloc;
1118         u32 last_reg;
1119         u32 m, i, tmp, *ib;
1120         int r;
1121
1122         if (p->rdev->family >= CHIP_CAYMAN)
1123                 last_reg = ARRAY_SIZE(cayman_reg_safe_bm);
1124         else
1125                 last_reg = ARRAY_SIZE(evergreen_reg_safe_bm);
1126
1127         i = (reg >> 7);
1128         if (i >= last_reg) {
1129                 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
1130                 return -EINVAL;
1131         }
1132         m = 1 << ((reg >> 2) & 31);
1133         if (p->rdev->family >= CHIP_CAYMAN) {
1134                 if (!(cayman_reg_safe_bm[i] & m))
1135                         return 0;
1136         } else {
1137                 if (!(evergreen_reg_safe_bm[i] & m))
1138                         return 0;
1139         }
1140         ib = p->ib->ptr;
1141         switch (reg) {
1142         /* force following reg to 0 in an attempt to disable out buffer
1143          * which will need us to better understand how it works to perform
1144          * security check on it (Jerome)
1145          */
1146         case SQ_ESGS_RING_SIZE:
1147         case SQ_GSVS_RING_SIZE:
1148         case SQ_ESTMP_RING_SIZE:
1149         case SQ_GSTMP_RING_SIZE:
1150         case SQ_HSTMP_RING_SIZE:
1151         case SQ_LSTMP_RING_SIZE:
1152         case SQ_PSTMP_RING_SIZE:
1153         case SQ_VSTMP_RING_SIZE:
1154         case SQ_ESGS_RING_ITEMSIZE:
1155         case SQ_ESTMP_RING_ITEMSIZE:
1156         case SQ_GSTMP_RING_ITEMSIZE:
1157         case SQ_GSVS_RING_ITEMSIZE:
1158         case SQ_GS_VERT_ITEMSIZE:
1159         case SQ_GS_VERT_ITEMSIZE_1:
1160         case SQ_GS_VERT_ITEMSIZE_2:
1161         case SQ_GS_VERT_ITEMSIZE_3:
1162         case SQ_GSVS_RING_OFFSET_1:
1163         case SQ_GSVS_RING_OFFSET_2:
1164         case SQ_GSVS_RING_OFFSET_3:
1165         case SQ_HSTMP_RING_ITEMSIZE:
1166         case SQ_LSTMP_RING_ITEMSIZE:
1167         case SQ_PSTMP_RING_ITEMSIZE:
1168         case SQ_VSTMP_RING_ITEMSIZE:
1169         case VGT_TF_RING_SIZE:
1170                 /* get value to populate the IB don't remove */
1171                 /*tmp =radeon_get_ib_value(p, idx);
1172                   ib[idx] = 0;*/
1173                 break;
1174         case SQ_ESGS_RING_BASE:
1175         case SQ_GSVS_RING_BASE:
1176         case SQ_ESTMP_RING_BASE:
1177         case SQ_GSTMP_RING_BASE:
1178         case SQ_HSTMP_RING_BASE:
1179         case SQ_LSTMP_RING_BASE:
1180         case SQ_PSTMP_RING_BASE:
1181         case SQ_VSTMP_RING_BASE:
1182                 r = evergreen_cs_packet_next_reloc(p, &reloc);
1183                 if (r) {
1184                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
1185                                         "0x%04X\n", reg);
1186                         return -EINVAL;
1187                 }
1188                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1189                 break;
1190         case DB_DEPTH_CONTROL:
1191                 track->db_depth_control = radeon_get_ib_value(p, idx);
1192                 track->db_dirty = true;
1193                 break;
1194         case CAYMAN_DB_EQAA:
1195                 if (p->rdev->family < CHIP_CAYMAN) {
1196                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
1197                                  "0x%04X\n", reg);
1198                         return -EINVAL;
1199                 }
1200                 break;
1201         case CAYMAN_DB_DEPTH_INFO:
1202                 if (p->rdev->family < CHIP_CAYMAN) {
1203                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
1204                                  "0x%04X\n", reg);
1205                         return -EINVAL;
1206                 }
1207                 break;
1208         case DB_Z_INFO:
1209                 track->db_z_info = radeon_get_ib_value(p, idx);
1210                 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1211                         r = evergreen_cs_packet_next_reloc(p, &reloc);
1212                         if (r) {
1213                                 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1214                                                 "0x%04X\n", reg);
1215                                 return -EINVAL;
1216                         }
1217                         ib[idx] &= ~Z_ARRAY_MODE(0xf);
1218                         track->db_z_info &= ~Z_ARRAY_MODE(0xf);
1219                         ib[idx] |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
1220                         track->db_z_info |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
1221                         if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
1222                                 unsigned bankw, bankh, mtaspect, tile_split;
1223
1224                                 evergreen_tiling_fields(reloc->lobj.tiling_flags,
1225                                                         &bankw, &bankh, &mtaspect,
1226                                                         &tile_split);
1227                                 ib[idx] |= DB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks));
1228                                 ib[idx] |= DB_TILE_SPLIT(tile_split) |
1229                                                 DB_BANK_WIDTH(bankw) |
1230                                                 DB_BANK_HEIGHT(bankh) |
1231                                                 DB_MACRO_TILE_ASPECT(mtaspect);
1232                         }
1233                 }
1234                 track->db_dirty = true;
1235                 break;
1236         case DB_STENCIL_INFO:
1237                 track->db_s_info = radeon_get_ib_value(p, idx);
1238                 track->db_dirty = true;
1239                 break;
1240         case DB_DEPTH_VIEW:
1241                 track->db_depth_view = radeon_get_ib_value(p, idx);
1242                 track->db_dirty = true;
1243                 break;
1244         case DB_DEPTH_SIZE:
1245                 track->db_depth_size = radeon_get_ib_value(p, idx);
1246                 track->db_dirty = true;
1247                 break;
1248         case R_02805C_DB_DEPTH_SLICE:
1249                 track->db_depth_slice = radeon_get_ib_value(p, idx);
1250                 track->db_dirty = true;
1251                 break;
1252         case DB_Z_READ_BASE:
1253                 r = evergreen_cs_packet_next_reloc(p, &reloc);
1254                 if (r) {
1255                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
1256                                         "0x%04X\n", reg);
1257                         return -EINVAL;
1258                 }
1259                 track->db_z_read_offset = radeon_get_ib_value(p, idx);
1260                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1261                 track->db_z_read_bo = reloc->robj;
1262                 track->db_dirty = true;
1263                 break;
1264         case DB_Z_WRITE_BASE:
1265                 r = evergreen_cs_packet_next_reloc(p, &reloc);
1266                 if (r) {
1267                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
1268                                         "0x%04X\n", reg);
1269                         return -EINVAL;
1270                 }
1271                 track->db_z_write_offset = radeon_get_ib_value(p, idx);
1272                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1273                 track->db_z_write_bo = reloc->robj;
1274                 track->db_dirty = true;
1275                 break;
1276         case DB_STENCIL_READ_BASE:
1277                 r = evergreen_cs_packet_next_reloc(p, &reloc);
1278                 if (r) {
1279                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
1280                                         "0x%04X\n", reg);
1281                         return -EINVAL;
1282                 }
1283                 track->db_s_read_offset = radeon_get_ib_value(p, idx);
1284                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1285                 track->db_s_read_bo = reloc->robj;
1286                 track->db_dirty = true;
1287                 break;
1288         case DB_STENCIL_WRITE_BASE:
1289                 r = evergreen_cs_packet_next_reloc(p, &reloc);
1290                 if (r) {
1291                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
1292                                         "0x%04X\n", reg);
1293                         return -EINVAL;
1294                 }
1295                 track->db_s_write_offset = radeon_get_ib_value(p, idx);
1296                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1297                 track->db_s_write_bo = reloc->robj;
1298                 track->db_dirty = true;
1299                 break;
1300         case VGT_STRMOUT_CONFIG:
1301                 track->vgt_strmout_config = radeon_get_ib_value(p, idx);
1302                 track->streamout_dirty = true;
1303                 break;
1304         case VGT_STRMOUT_BUFFER_CONFIG:
1305                 track->vgt_strmout_buffer_config = radeon_get_ib_value(p, idx);
1306                 track->streamout_dirty = true;
1307                 break;
1308         case VGT_STRMOUT_BUFFER_BASE_0:
1309         case VGT_STRMOUT_BUFFER_BASE_1:
1310         case VGT_STRMOUT_BUFFER_BASE_2:
1311         case VGT_STRMOUT_BUFFER_BASE_3:
1312                 r = evergreen_cs_packet_next_reloc(p, &reloc);
1313                 if (r) {
1314                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
1315                                         "0x%04X\n", reg);
1316                         return -EINVAL;
1317                 }
1318                 tmp = (reg - VGT_STRMOUT_BUFFER_BASE_0) / 16;
1319                 track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;
1320                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1321                 track->vgt_strmout_bo[tmp] = reloc->robj;
1322                 track->streamout_dirty = true;
1323                 break;
1324         case VGT_STRMOUT_BUFFER_SIZE_0:
1325         case VGT_STRMOUT_BUFFER_SIZE_1:
1326         case VGT_STRMOUT_BUFFER_SIZE_2:
1327         case VGT_STRMOUT_BUFFER_SIZE_3:
1328                 tmp = (reg - VGT_STRMOUT_BUFFER_SIZE_0) / 16;
1329                 /* size in register is DWs, convert to bytes */
1330                 track->vgt_strmout_size[tmp] = radeon_get_ib_value(p, idx) * 4;
1331                 track->streamout_dirty = true;
1332                 break;
1333         case CP_COHER_BASE:
1334                 r = evergreen_cs_packet_next_reloc(p, &reloc);
1335                 if (r) {
1336                         dev_warn(p->dev, "missing reloc for CP_COHER_BASE "
1337                                         "0x%04X\n", reg);
1338                         return -EINVAL;
1339                 }
1340                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1341         case CB_TARGET_MASK:
1342                 track->cb_target_mask = radeon_get_ib_value(p, idx);
1343                 track->cb_dirty = true;
1344                 break;
1345         case CB_SHADER_MASK:
1346                 track->cb_shader_mask = radeon_get_ib_value(p, idx);
1347                 track->cb_dirty = true;
1348                 break;
1349         case PA_SC_AA_CONFIG:
1350                 if (p->rdev->family >= CHIP_CAYMAN) {
1351                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
1352                                  "0x%04X\n", reg);
1353                         return -EINVAL;
1354                 }
1355                 tmp = radeon_get_ib_value(p, idx) & MSAA_NUM_SAMPLES_MASK;
1356                 track->nsamples = 1 << tmp;
1357                 break;
1358         case CAYMAN_PA_SC_AA_CONFIG:
1359                 if (p->rdev->family < CHIP_CAYMAN) {
1360                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
1361                                  "0x%04X\n", reg);
1362                         return -EINVAL;
1363                 }
1364                 tmp = radeon_get_ib_value(p, idx) & CAYMAN_MSAA_NUM_SAMPLES_MASK;
1365                 track->nsamples = 1 << tmp;
1366                 break;
1367         case CB_COLOR0_VIEW:
1368         case CB_COLOR1_VIEW:
1369         case CB_COLOR2_VIEW:
1370         case CB_COLOR3_VIEW:
1371         case CB_COLOR4_VIEW:
1372         case CB_COLOR5_VIEW:
1373         case CB_COLOR6_VIEW:
1374         case CB_COLOR7_VIEW:
1375                 tmp = (reg - CB_COLOR0_VIEW) / 0x3c;
1376                 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx);
1377                 track->cb_dirty = true;
1378                 break;
1379         case CB_COLOR8_VIEW:
1380         case CB_COLOR9_VIEW:
1381         case CB_COLOR10_VIEW:
1382         case CB_COLOR11_VIEW:
1383                 tmp = ((reg - CB_COLOR8_VIEW) / 0x1c) + 8;
1384                 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx);
1385                 track->cb_dirty = true;
1386                 break;
1387         case CB_COLOR0_INFO:
1388         case CB_COLOR1_INFO:
1389         case CB_COLOR2_INFO:
1390         case CB_COLOR3_INFO:
1391         case CB_COLOR4_INFO:
1392         case CB_COLOR5_INFO:
1393         case CB_COLOR6_INFO:
1394         case CB_COLOR7_INFO:
1395                 tmp = (reg - CB_COLOR0_INFO) / 0x3c;
1396                 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
1397                 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1398                         r = evergreen_cs_packet_next_reloc(p, &reloc);
1399                         if (r) {
1400                                 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1401                                                 "0x%04X\n", reg);
1402                                 return -EINVAL;
1403                         }
1404                         ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
1405                         track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
1406                 }
1407                 track->cb_dirty = true;
1408                 break;
1409         case CB_COLOR8_INFO:
1410         case CB_COLOR9_INFO:
1411         case CB_COLOR10_INFO:
1412         case CB_COLOR11_INFO:
1413                 tmp = ((reg - CB_COLOR8_INFO) / 0x1c) + 8;
1414                 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);
1415                 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1416                         r = evergreen_cs_packet_next_reloc(p, &reloc);
1417                         if (r) {
1418                                 dev_warn(p->dev, "bad SET_CONTEXT_REG "
1419                                                 "0x%04X\n", reg);
1420                                 return -EINVAL;
1421                         }
1422                         ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
1423                         track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
1424                 }
1425                 track->cb_dirty = true;
1426                 break;
1427         case CB_COLOR0_PITCH:
1428         case CB_COLOR1_PITCH:
1429         case CB_COLOR2_PITCH:
1430         case CB_COLOR3_PITCH:
1431         case CB_COLOR4_PITCH:
1432         case CB_COLOR5_PITCH:
1433         case CB_COLOR6_PITCH:
1434         case CB_COLOR7_PITCH:
1435                 tmp = (reg - CB_COLOR0_PITCH) / 0x3c;
1436                 track->cb_color_pitch[tmp] = radeon_get_ib_value(p, idx);
1437                 track->cb_dirty = true;
1438                 break;
1439         case CB_COLOR8_PITCH:
1440         case CB_COLOR9_PITCH:
1441         case CB_COLOR10_PITCH:
1442         case CB_COLOR11_PITCH:
1443                 tmp = ((reg - CB_COLOR8_PITCH) / 0x1c) + 8;
1444                 track->cb_color_pitch[tmp] = radeon_get_ib_value(p, idx);
1445                 track->cb_dirty = true;
1446                 break;
1447         case CB_COLOR0_SLICE:
1448         case CB_COLOR1_SLICE:
1449         case CB_COLOR2_SLICE:
1450         case CB_COLOR3_SLICE:
1451         case CB_COLOR4_SLICE:
1452         case CB_COLOR5_SLICE:
1453         case CB_COLOR6_SLICE:
1454         case CB_COLOR7_SLICE:
1455                 tmp = (reg - CB_COLOR0_SLICE) / 0x3c;
1456                 track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx);
1457                 track->cb_dirty = true;
1458                 break;
1459         case CB_COLOR8_SLICE:
1460         case CB_COLOR9_SLICE:
1461         case CB_COLOR10_SLICE:
1462         case CB_COLOR11_SLICE:
1463                 tmp = ((reg - CB_COLOR8_SLICE) / 0x1c) + 8;
1464                 track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx);
1465                 track->cb_dirty = true;
1466                 break;
1467         case CB_COLOR0_ATTRIB:
1468         case CB_COLOR1_ATTRIB:
1469         case CB_COLOR2_ATTRIB:
1470         case CB_COLOR3_ATTRIB:
1471         case CB_COLOR4_ATTRIB:
1472         case CB_COLOR5_ATTRIB:
1473         case CB_COLOR6_ATTRIB:
1474         case CB_COLOR7_ATTRIB:
1475                 r = evergreen_cs_packet_next_reloc(p, &reloc);
1476                 if (r) {
1477                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
1478                                         "0x%04X\n", reg);
1479                         return -EINVAL;
1480                 }
1481                 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1482                         if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
1483                                 unsigned bankw, bankh, mtaspect, tile_split;
1484
1485                                 evergreen_tiling_fields(reloc->lobj.tiling_flags,
1486                                                         &bankw, &bankh, &mtaspect,
1487                                                         &tile_split);
1488                                 ib[idx] |= CB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks));
1489                                 ib[idx] |= CB_TILE_SPLIT(tile_split) |
1490                                            CB_BANK_WIDTH(bankw) |
1491                                            CB_BANK_HEIGHT(bankh) |
1492                                            CB_MACRO_TILE_ASPECT(mtaspect);
1493                         }
1494                 }
1495                 tmp = ((reg - CB_COLOR0_ATTRIB) / 0x3c);
1496                 track->cb_color_attrib[tmp] = ib[idx];
1497                 track->cb_dirty = true;
1498                 break;
1499         case CB_COLOR8_ATTRIB:
1500         case CB_COLOR9_ATTRIB:
1501         case CB_COLOR10_ATTRIB:
1502         case CB_COLOR11_ATTRIB:
1503                 r = evergreen_cs_packet_next_reloc(p, &reloc);
1504                 if (r) {
1505                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
1506                                         "0x%04X\n", reg);
1507                         return -EINVAL;
1508                 }
1509                 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1510                         if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
1511                                 unsigned bankw, bankh, mtaspect, tile_split;
1512
1513                                 evergreen_tiling_fields(reloc->lobj.tiling_flags,
1514                                                         &bankw, &bankh, &mtaspect,
1515                                                         &tile_split);
1516                                 ib[idx] |= CB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks));
1517                                 ib[idx] |= CB_TILE_SPLIT(tile_split) |
1518                                            CB_BANK_WIDTH(bankw) |
1519                                            CB_BANK_HEIGHT(bankh) |
1520                                            CB_MACRO_TILE_ASPECT(mtaspect);
1521                         }
1522                 }
1523                 tmp = ((reg - CB_COLOR8_ATTRIB) / 0x1c) + 8;
1524                 track->cb_color_attrib[tmp] = ib[idx];
1525                 track->cb_dirty = true;
1526                 break;
1527         case CB_COLOR0_FMASK:
1528         case CB_COLOR1_FMASK:
1529         case CB_COLOR2_FMASK:
1530         case CB_COLOR3_FMASK:
1531         case CB_COLOR4_FMASK:
1532         case CB_COLOR5_FMASK:
1533         case CB_COLOR6_FMASK:
1534         case CB_COLOR7_FMASK:
1535                 tmp = (reg - CB_COLOR0_FMASK) / 0x3c;
1536                 r = evergreen_cs_packet_next_reloc(p, &reloc);
1537                 if (r) {
1538                         dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
1539                         return -EINVAL;
1540                 }
1541                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1542                 track->cb_color_fmask_bo[tmp] = reloc->robj;
1543                 break;
1544         case CB_COLOR0_CMASK:
1545         case CB_COLOR1_CMASK:
1546         case CB_COLOR2_CMASK:
1547         case CB_COLOR3_CMASK:
1548         case CB_COLOR4_CMASK:
1549         case CB_COLOR5_CMASK:
1550         case CB_COLOR6_CMASK:
1551         case CB_COLOR7_CMASK:
1552                 tmp = (reg - CB_COLOR0_CMASK) / 0x3c;
1553                 r = evergreen_cs_packet_next_reloc(p, &reloc);
1554                 if (r) {
1555                         dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
1556                         return -EINVAL;
1557                 }
1558                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1559                 track->cb_color_cmask_bo[tmp] = reloc->robj;
1560                 break;
1561         case CB_COLOR0_FMASK_SLICE:
1562         case CB_COLOR1_FMASK_SLICE:
1563         case CB_COLOR2_FMASK_SLICE:
1564         case CB_COLOR3_FMASK_SLICE:
1565         case CB_COLOR4_FMASK_SLICE:
1566         case CB_COLOR5_FMASK_SLICE:
1567         case CB_COLOR6_FMASK_SLICE:
1568         case CB_COLOR7_FMASK_SLICE:
1569                 tmp = (reg - CB_COLOR0_FMASK_SLICE) / 0x3c;
1570                 track->cb_color_fmask_slice[tmp] = radeon_get_ib_value(p, idx);
1571                 break;
1572         case CB_COLOR0_CMASK_SLICE:
1573         case CB_COLOR1_CMASK_SLICE:
1574         case CB_COLOR2_CMASK_SLICE:
1575         case CB_COLOR3_CMASK_SLICE:
1576         case CB_COLOR4_CMASK_SLICE:
1577         case CB_COLOR5_CMASK_SLICE:
1578         case CB_COLOR6_CMASK_SLICE:
1579         case CB_COLOR7_CMASK_SLICE:
1580                 tmp = (reg - CB_COLOR0_CMASK_SLICE) / 0x3c;
1581                 track->cb_color_cmask_slice[tmp] = radeon_get_ib_value(p, idx);
1582                 break;
1583         case CB_COLOR0_BASE:
1584         case CB_COLOR1_BASE:
1585         case CB_COLOR2_BASE:
1586         case CB_COLOR3_BASE:
1587         case CB_COLOR4_BASE:
1588         case CB_COLOR5_BASE:
1589         case CB_COLOR6_BASE:
1590         case CB_COLOR7_BASE:
1591                 r = evergreen_cs_packet_next_reloc(p, &reloc);
1592                 if (r) {
1593                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
1594                                         "0x%04X\n", reg);
1595                         return -EINVAL;
1596                 }
1597                 tmp = (reg - CB_COLOR0_BASE) / 0x3c;
1598                 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx);
1599                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1600                 track->cb_color_bo[tmp] = reloc->robj;
1601                 track->cb_dirty = true;
1602                 break;
1603         case CB_COLOR8_BASE:
1604         case CB_COLOR9_BASE:
1605         case CB_COLOR10_BASE:
1606         case CB_COLOR11_BASE:
1607                 r = evergreen_cs_packet_next_reloc(p, &reloc);
1608                 if (r) {
1609                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
1610                                         "0x%04X\n", reg);
1611                         return -EINVAL;
1612                 }
1613                 tmp = ((reg - CB_COLOR8_BASE) / 0x1c) + 8;
1614                 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx);
1615                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1616                 track->cb_color_bo[tmp] = reloc->robj;
1617                 track->cb_dirty = true;
1618                 break;
1619         case CB_IMMED0_BASE:
1620         case CB_IMMED1_BASE:
1621         case CB_IMMED2_BASE:
1622         case CB_IMMED3_BASE:
1623         case CB_IMMED4_BASE:
1624         case CB_IMMED5_BASE:
1625         case CB_IMMED6_BASE:
1626         case CB_IMMED7_BASE:
1627         case CB_IMMED8_BASE:
1628         case CB_IMMED9_BASE:
1629         case CB_IMMED10_BASE:
1630         case CB_IMMED11_BASE:
1631         case DB_HTILE_DATA_BASE:
1632         case SQ_PGM_START_FS:
1633         case SQ_PGM_START_ES:
1634         case SQ_PGM_START_VS:
1635         case SQ_PGM_START_GS:
1636         case SQ_PGM_START_PS:
1637         case SQ_PGM_START_HS:
1638         case SQ_PGM_START_LS:
1639         case SQ_CONST_MEM_BASE:
1640         case SQ_ALU_CONST_CACHE_GS_0:
1641         case SQ_ALU_CONST_CACHE_GS_1:
1642         case SQ_ALU_CONST_CACHE_GS_2:
1643         case SQ_ALU_CONST_CACHE_GS_3:
1644         case SQ_ALU_CONST_CACHE_GS_4:
1645         case SQ_ALU_CONST_CACHE_GS_5:
1646         case SQ_ALU_CONST_CACHE_GS_6:
1647         case SQ_ALU_CONST_CACHE_GS_7:
1648         case SQ_ALU_CONST_CACHE_GS_8:
1649         case SQ_ALU_CONST_CACHE_GS_9:
1650         case SQ_ALU_CONST_CACHE_GS_10:
1651         case SQ_ALU_CONST_CACHE_GS_11:
1652         case SQ_ALU_CONST_CACHE_GS_12:
1653         case SQ_ALU_CONST_CACHE_GS_13:
1654         case SQ_ALU_CONST_CACHE_GS_14:
1655         case SQ_ALU_CONST_CACHE_GS_15:
1656         case SQ_ALU_CONST_CACHE_PS_0:
1657         case SQ_ALU_CONST_CACHE_PS_1:
1658         case SQ_ALU_CONST_CACHE_PS_2:
1659         case SQ_ALU_CONST_CACHE_PS_3:
1660         case SQ_ALU_CONST_CACHE_PS_4:
1661         case SQ_ALU_CONST_CACHE_PS_5:
1662         case SQ_ALU_CONST_CACHE_PS_6:
1663         case SQ_ALU_CONST_CACHE_PS_7:
1664         case SQ_ALU_CONST_CACHE_PS_8:
1665         case SQ_ALU_CONST_CACHE_PS_9:
1666         case SQ_ALU_CONST_CACHE_PS_10:
1667         case SQ_ALU_CONST_CACHE_PS_11:
1668         case SQ_ALU_CONST_CACHE_PS_12:
1669         case SQ_ALU_CONST_CACHE_PS_13:
1670         case SQ_ALU_CONST_CACHE_PS_14:
1671         case SQ_ALU_CONST_CACHE_PS_15:
1672         case SQ_ALU_CONST_CACHE_VS_0:
1673         case SQ_ALU_CONST_CACHE_VS_1:
1674         case SQ_ALU_CONST_CACHE_VS_2:
1675         case SQ_ALU_CONST_CACHE_VS_3:
1676         case SQ_ALU_CONST_CACHE_VS_4:
1677         case SQ_ALU_CONST_CACHE_VS_5:
1678         case SQ_ALU_CONST_CACHE_VS_6:
1679         case SQ_ALU_CONST_CACHE_VS_7:
1680         case SQ_ALU_CONST_CACHE_VS_8:
1681         case SQ_ALU_CONST_CACHE_VS_9:
1682         case SQ_ALU_CONST_CACHE_VS_10:
1683         case SQ_ALU_CONST_CACHE_VS_11:
1684         case SQ_ALU_CONST_CACHE_VS_12:
1685         case SQ_ALU_CONST_CACHE_VS_13:
1686         case SQ_ALU_CONST_CACHE_VS_14:
1687         case SQ_ALU_CONST_CACHE_VS_15:
1688         case SQ_ALU_CONST_CACHE_HS_0:
1689         case SQ_ALU_CONST_CACHE_HS_1:
1690         case SQ_ALU_CONST_CACHE_HS_2:
1691         case SQ_ALU_CONST_CACHE_HS_3:
1692         case SQ_ALU_CONST_CACHE_HS_4:
1693         case SQ_ALU_CONST_CACHE_HS_5:
1694         case SQ_ALU_CONST_CACHE_HS_6:
1695         case SQ_ALU_CONST_CACHE_HS_7:
1696         case SQ_ALU_CONST_CACHE_HS_8:
1697         case SQ_ALU_CONST_CACHE_HS_9:
1698         case SQ_ALU_CONST_CACHE_HS_10:
1699         case SQ_ALU_CONST_CACHE_HS_11:
1700         case SQ_ALU_CONST_CACHE_HS_12:
1701         case SQ_ALU_CONST_CACHE_HS_13:
1702         case SQ_ALU_CONST_CACHE_HS_14:
1703         case SQ_ALU_CONST_CACHE_HS_15:
1704         case SQ_ALU_CONST_CACHE_LS_0:
1705         case SQ_ALU_CONST_CACHE_LS_1:
1706         case SQ_ALU_CONST_CACHE_LS_2:
1707         case SQ_ALU_CONST_CACHE_LS_3:
1708         case SQ_ALU_CONST_CACHE_LS_4:
1709         case SQ_ALU_CONST_CACHE_LS_5:
1710         case SQ_ALU_CONST_CACHE_LS_6:
1711         case SQ_ALU_CONST_CACHE_LS_7:
1712         case SQ_ALU_CONST_CACHE_LS_8:
1713         case SQ_ALU_CONST_CACHE_LS_9:
1714         case SQ_ALU_CONST_CACHE_LS_10:
1715         case SQ_ALU_CONST_CACHE_LS_11:
1716         case SQ_ALU_CONST_CACHE_LS_12:
1717         case SQ_ALU_CONST_CACHE_LS_13:
1718         case SQ_ALU_CONST_CACHE_LS_14:
1719         case SQ_ALU_CONST_CACHE_LS_15:
1720                 r = evergreen_cs_packet_next_reloc(p, &reloc);
1721                 if (r) {
1722                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
1723                                         "0x%04X\n", reg);
1724                         return -EINVAL;
1725                 }
1726                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1727                 break;
1728         case SX_MEMORY_EXPORT_BASE:
1729                 if (p->rdev->family >= CHIP_CAYMAN) {
1730                         dev_warn(p->dev, "bad SET_CONFIG_REG "
1731                                  "0x%04X\n", reg);
1732                         return -EINVAL;
1733                 }
1734                 r = evergreen_cs_packet_next_reloc(p, &reloc);
1735                 if (r) {
1736                         dev_warn(p->dev, "bad SET_CONFIG_REG "
1737                                         "0x%04X\n", reg);
1738                         return -EINVAL;
1739                 }
1740                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1741                 break;
1742         case CAYMAN_SX_SCATTER_EXPORT_BASE:
1743                 if (p->rdev->family < CHIP_CAYMAN) {
1744                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
1745                                  "0x%04X\n", reg);
1746                         return -EINVAL;
1747                 }
1748                 r = evergreen_cs_packet_next_reloc(p, &reloc);
1749                 if (r) {
1750                         dev_warn(p->dev, "bad SET_CONTEXT_REG "
1751                                         "0x%04X\n", reg);
1752                         return -EINVAL;
1753                 }
1754                 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1755                 break;
1756         case SX_MISC:
1757                 track->sx_misc_kill_all_prims = (radeon_get_ib_value(p, idx) & 0x1) != 0;
1758                 break;
1759         default:
1760                 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
1761                 return -EINVAL;
1762         }
1763         return 0;
1764 }
1765
1766 static bool evergreen_is_safe_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1767 {
1768         u32 last_reg, m, i;
1769
1770         if (p->rdev->family >= CHIP_CAYMAN)
1771                 last_reg = ARRAY_SIZE(cayman_reg_safe_bm);
1772         else
1773                 last_reg = ARRAY_SIZE(evergreen_reg_safe_bm);
1774
1775         i = (reg >> 7);
1776         if (i >= last_reg) {
1777                 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
1778                 return false;
1779         }
1780         m = 1 << ((reg >> 2) & 31);
1781         if (p->rdev->family >= CHIP_CAYMAN) {
1782                 if (!(cayman_reg_safe_bm[i] & m))
1783                         return true;
1784         } else {
1785                 if (!(evergreen_reg_safe_bm[i] & m))
1786                         return true;
1787         }
1788         dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
1789         return false;
1790 }
1791
1792 static int evergreen_packet3_check(struct radeon_cs_parser *p,
1793                                    struct radeon_cs_packet *pkt)
1794 {
1795         struct radeon_cs_reloc *reloc;
1796         struct evergreen_cs_track *track;
1797         volatile u32 *ib;
1798         unsigned idx;
1799         unsigned i;
1800         unsigned start_reg, end_reg, reg;
1801         int r;
1802         u32 idx_value;
1803
1804         track = (struct evergreen_cs_track *)p->track;
1805         ib = p->ib->ptr;
1806         idx = pkt->idx + 1;
1807         idx_value = radeon_get_ib_value(p, idx);
1808
1809         switch (pkt->opcode) {
1810         case PACKET3_SET_PREDICATION:
1811         {
1812                 int pred_op;
1813                 int tmp;
1814                 uint64_t offset;
1815
1816                 if (pkt->count != 1) {
1817                         DRM_ERROR("bad SET PREDICATION\n");
1818                         return -EINVAL;
1819                 }
1820
1821                 tmp = radeon_get_ib_value(p, idx + 1);
1822                 pred_op = (tmp >> 16) & 0x7;
1823
1824                 /* for the clear predicate operation */
1825                 if (pred_op == 0)
1826                         return 0;
1827
1828                 if (pred_op > 2) {
1829                         DRM_ERROR("bad SET PREDICATION operation %d\n", pred_op);
1830                         return -EINVAL;
1831                 }
1832
1833                 r = evergreen_cs_packet_next_reloc(p, &reloc);
1834                 if (r) {
1835                         DRM_ERROR("bad SET PREDICATION\n");
1836                         return -EINVAL;
1837                 }
1838
1839                 offset = reloc->lobj.gpu_offset +
1840                          (idx_value & 0xfffffff0) +
1841                          ((u64)(tmp & 0xff) << 32);
1842
1843                 ib[idx + 0] = offset;
1844                 ib[idx + 1] = (tmp & 0xffffff00) | (upper_32_bits(offset) & 0xff);
1845         }
1846         break;
1847         case PACKET3_CONTEXT_CONTROL:
1848                 if (pkt->count != 1) {
1849                         DRM_ERROR("bad CONTEXT_CONTROL\n");
1850                         return -EINVAL;
1851                 }
1852                 break;
1853         case PACKET3_INDEX_TYPE:
1854         case PACKET3_NUM_INSTANCES:
1855         case PACKET3_CLEAR_STATE:
1856                 if (pkt->count) {
1857                         DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES/CLEAR_STATE\n");
1858                         return -EINVAL;
1859                 }
1860                 break;
1861         case CAYMAN_PACKET3_DEALLOC_STATE:
1862                 if (p->rdev->family < CHIP_CAYMAN) {
1863                         DRM_ERROR("bad PACKET3_DEALLOC_STATE\n");
1864                         return -EINVAL;
1865                 }
1866                 if (pkt->count) {
1867                         DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES/CLEAR_STATE\n");
1868                         return -EINVAL;
1869                 }
1870                 break;
1871         case PACKET3_INDEX_BASE:
1872         {
1873                 uint64_t offset;
1874
1875                 if (pkt->count != 1) {
1876                         DRM_ERROR("bad INDEX_BASE\n");
1877                         return -EINVAL;
1878                 }
1879                 r = evergreen_cs_packet_next_reloc(p, &reloc);
1880                 if (r) {
1881                         DRM_ERROR("bad INDEX_BASE\n");
1882                         return -EINVAL;
1883                 }
1884
1885                 offset = reloc->lobj.gpu_offset +
1886                          idx_value +
1887                          ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32);
1888
1889                 ib[idx+0] = offset;
1890                 ib[idx+1] = upper_32_bits(offset) & 0xff;
1891
1892                 r = evergreen_cs_track_check(p);
1893                 if (r) {
1894                         dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1895                         return r;
1896                 }
1897                 break;
1898         }
1899         case PACKET3_DRAW_INDEX:
1900         {
1901                 uint64_t offset;
1902                 if (pkt->count != 3) {
1903                         DRM_ERROR("bad DRAW_INDEX\n");
1904                         return -EINVAL;
1905                 }
1906                 r = evergreen_cs_packet_next_reloc(p, &reloc);
1907                 if (r) {
1908                         DRM_ERROR("bad DRAW_INDEX\n");
1909                         return -EINVAL;
1910                 }
1911
1912                 offset = reloc->lobj.gpu_offset +
1913                          idx_value +
1914                          ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32);
1915
1916                 ib[idx+0] = offset;
1917                 ib[idx+1] = upper_32_bits(offset) & 0xff;
1918
1919                 r = evergreen_cs_track_check(p);
1920                 if (r) {
1921                         dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1922                         return r;
1923                 }
1924                 break;
1925         }
1926         case PACKET3_DRAW_INDEX_2:
1927         {
1928                 uint64_t offset;
1929
1930                 if (pkt->count != 4) {
1931                         DRM_ERROR("bad DRAW_INDEX_2\n");
1932                         return -EINVAL;
1933                 }
1934                 r = evergreen_cs_packet_next_reloc(p, &reloc);
1935                 if (r) {
1936                         DRM_ERROR("bad DRAW_INDEX_2\n");
1937                         return -EINVAL;
1938                 }
1939
1940                 offset = reloc->lobj.gpu_offset +
1941                          radeon_get_ib_value(p, idx+1) +
1942                          ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
1943
1944                 ib[idx+1] = offset;
1945                 ib[idx+2] = upper_32_bits(offset) & 0xff;
1946
1947                 r = evergreen_cs_track_check(p);
1948                 if (r) {
1949                         dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1950                         return r;
1951                 }
1952                 break;
1953         }
1954         case PACKET3_DRAW_INDEX_AUTO:
1955                 if (pkt->count != 1) {
1956                         DRM_ERROR("bad DRAW_INDEX_AUTO\n");
1957                         return -EINVAL;
1958                 }
1959                 r = evergreen_cs_track_check(p);
1960                 if (r) {
1961                         dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx);
1962                         return r;
1963                 }
1964                 break;
1965         case PACKET3_DRAW_INDEX_MULTI_AUTO:
1966                 if (pkt->count != 2) {
1967                         DRM_ERROR("bad DRAW_INDEX_MULTI_AUTO\n");
1968                         return -EINVAL;
1969                 }
1970                 r = evergreen_cs_track_check(p);
1971                 if (r) {
1972                         dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx);
1973                         return r;
1974                 }
1975                 break;
1976         case PACKET3_DRAW_INDEX_IMMD:
1977                 if (pkt->count < 2) {
1978                         DRM_ERROR("bad DRAW_INDEX_IMMD\n");
1979                         return -EINVAL;
1980                 }
1981                 r = evergreen_cs_track_check(p);
1982                 if (r) {
1983                         dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1984                         return r;
1985                 }
1986                 break;
1987         case PACKET3_DRAW_INDEX_OFFSET:
1988                 if (pkt->count != 2) {
1989                         DRM_ERROR("bad DRAW_INDEX_OFFSET\n");
1990                         return -EINVAL;
1991                 }
1992                 r = evergreen_cs_track_check(p);
1993                 if (r) {
1994                         dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
1995                         return r;
1996                 }
1997                 break;
1998         case PACKET3_DRAW_INDEX_OFFSET_2:
1999                 if (pkt->count != 3) {
2000                         DRM_ERROR("bad DRAW_INDEX_OFFSET_2\n");
2001                         return -EINVAL;
2002                 }
2003                 r = evergreen_cs_track_check(p);
2004                 if (r) {
2005                         dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
2006                         return r;
2007                 }
2008                 break;
2009         case PACKET3_DISPATCH_DIRECT:
2010                 if (pkt->count != 3) {
2011                         DRM_ERROR("bad DISPATCH_DIRECT\n");
2012                         return -EINVAL;
2013                 }
2014                 r = evergreen_cs_track_check(p);
2015                 if (r) {
2016                         dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx);
2017                         return r;
2018                 }
2019                 break;
2020         case PACKET3_DISPATCH_INDIRECT:
2021                 if (pkt->count != 1) {
2022                         DRM_ERROR("bad DISPATCH_INDIRECT\n");
2023                         return -EINVAL;
2024                 }
2025                 r = evergreen_cs_packet_next_reloc(p, &reloc);
2026                 if (r) {
2027                         DRM_ERROR("bad DISPATCH_INDIRECT\n");
2028                         return -EINVAL;
2029                 }
2030                 ib[idx+0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff);
2031                 r = evergreen_cs_track_check(p);
2032                 if (r) {
2033                         dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);
2034                         return r;
2035                 }
2036                 break;
2037         case PACKET3_WAIT_REG_MEM:
2038                 if (pkt->count != 5) {
2039                         DRM_ERROR("bad WAIT_REG_MEM\n");
2040                         return -EINVAL;
2041                 }
2042                 /* bit 4 is reg (0) or mem (1) */
2043                 if (idx_value & 0x10) {
2044                         uint64_t offset;
2045
2046                         r = evergreen_cs_packet_next_reloc(p, &reloc);
2047                         if (r) {
2048                                 DRM_ERROR("bad WAIT_REG_MEM\n");
2049                                 return -EINVAL;
2050                         }
2051
2052                         offset = reloc->lobj.gpu_offset +
2053                                  (radeon_get_ib_value(p, idx+1) & 0xfffffffc) +
2054                                  ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
2055
2056                         ib[idx+1] = (ib[idx+1] & 0x3) | (offset & 0xfffffffc);
2057                         ib[idx+2] = upper_32_bits(offset) & 0xff;
2058                 }
2059                 break;
2060         case PACKET3_SURFACE_SYNC:
2061                 if (pkt->count != 3) {
2062                         DRM_ERROR("bad SURFACE_SYNC\n");
2063                         return -EINVAL;
2064                 }
2065                 /* 0xffffffff/0x0 is flush all cache flag */
2066                 if (radeon_get_ib_value(p, idx + 1) != 0xffffffff ||
2067                     radeon_get_ib_value(p, idx + 2) != 0) {
2068                         r = evergreen_cs_packet_next_reloc(p, &reloc);
2069                         if (r) {
2070                                 DRM_ERROR("bad SURFACE_SYNC\n");
2071                                 return -EINVAL;
2072                         }
2073                         ib[idx+2] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
2074                 }
2075                 break;
2076         case PACKET3_EVENT_WRITE:
2077                 if (pkt->count != 2 && pkt->count != 0) {
2078                         DRM_ERROR("bad EVENT_WRITE\n");
2079                         return -EINVAL;
2080                 }
2081                 if (pkt->count) {
2082                         uint64_t offset;
2083
2084                         r = evergreen_cs_packet_next_reloc(p, &reloc);
2085                         if (r) {
2086                                 DRM_ERROR("bad EVENT_WRITE\n");
2087                                 return -EINVAL;
2088                         }
2089                         offset = reloc->lobj.gpu_offset +
2090                                  (radeon_get_ib_value(p, idx+1) & 0xfffffff8) +
2091                                  ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
2092
2093                         ib[idx+1] = offset & 0xfffffff8;
2094                         ib[idx+2] = upper_32_bits(offset) & 0xff;
2095                 }
2096                 break;
2097         case PACKET3_EVENT_WRITE_EOP:
2098         {
2099                 uint64_t offset;
2100
2101                 if (pkt->count != 4) {
2102                         DRM_ERROR("bad EVENT_WRITE_EOP\n");
2103                         return -EINVAL;
2104                 }
2105                 r = evergreen_cs_packet_next_reloc(p, &reloc);
2106                 if (r) {
2107                         DRM_ERROR("bad EVENT_WRITE_EOP\n");
2108                         return -EINVAL;
2109                 }
2110
2111                 offset = reloc->lobj.gpu_offset +
2112                          (radeon_get_ib_value(p, idx+1) & 0xfffffffc) +
2113                          ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
2114
2115                 ib[idx+1] = offset & 0xfffffffc;
2116                 ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff);
2117                 break;
2118         }
2119         case PACKET3_EVENT_WRITE_EOS:
2120         {
2121                 uint64_t offset;
2122
2123                 if (pkt->count != 3) {
2124                         DRM_ERROR("bad EVENT_WRITE_EOS\n");
2125                         return -EINVAL;
2126                 }
2127                 r = evergreen_cs_packet_next_reloc(p, &reloc);
2128                 if (r) {
2129                         DRM_ERROR("bad EVENT_WRITE_EOS\n");
2130                         return -EINVAL;
2131                 }
2132
2133                 offset = reloc->lobj.gpu_offset +
2134                          (radeon_get_ib_value(p, idx+1) & 0xfffffffc) +
2135                          ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);
2136
2137                 ib[idx+1] = offset & 0xfffffffc;
2138                 ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff);
2139                 break;
2140         }
2141         case PACKET3_SET_CONFIG_REG:
2142                 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START;
2143                 end_reg = 4 * pkt->count + start_reg - 4;
2144                 if ((start_reg < PACKET3_SET_CONFIG_REG_START) ||
2145                     (start_reg >= PACKET3_SET_CONFIG_REG_END) ||
2146                     (end_reg >= PACKET3_SET_CONFIG_REG_END)) {
2147                         DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n");
2148                         return -EINVAL;
2149                 }
2150                 for (i = 0; i < pkt->count; i++) {
2151                         reg = start_reg + (4 * i);
2152                         r = evergreen_cs_check_reg(p, reg, idx+1+i);
2153                         if (r)
2154                                 return r;
2155                 }
2156                 break;
2157         case PACKET3_SET_CONTEXT_REG:
2158                 start_reg = (idx_value << 2) + PACKET3_SET_CONTEXT_REG_START;
2159                 end_reg = 4 * pkt->count + start_reg - 4;
2160                 if ((start_reg < PACKET3_SET_CONTEXT_REG_START) ||
2161                     (start_reg >= PACKET3_SET_CONTEXT_REG_END) ||
2162                     (end_reg >= PACKET3_SET_CONTEXT_REG_END)) {
2163                         DRM_ERROR("bad PACKET3_SET_CONTEXT_REG\n");
2164                         return -EINVAL;
2165                 }
2166                 for (i = 0; i < pkt->count; i++) {
2167                         reg = start_reg + (4 * i);
2168                         r = evergreen_cs_check_reg(p, reg, idx+1+i);
2169                         if (r)
2170                                 return r;
2171                 }
2172                 break;
2173         case PACKET3_SET_RESOURCE:
2174                 if (pkt->count % 8) {
2175                         DRM_ERROR("bad SET_RESOURCE\n");
2176                         return -EINVAL;
2177                 }
2178                 start_reg = (idx_value << 2) + PACKET3_SET_RESOURCE_START;
2179                 end_reg = 4 * pkt->count + start_reg - 4;
2180                 if ((start_reg < PACKET3_SET_RESOURCE_START) ||
2181                     (start_reg >= PACKET3_SET_RESOURCE_END) ||
2182                     (end_reg >= PACKET3_SET_RESOURCE_END)) {
2183                         DRM_ERROR("bad SET_RESOURCE\n");
2184                         return -EINVAL;
2185                 }
2186                 for (i = 0; i < (pkt->count / 8); i++) {
2187                         struct radeon_bo *texture, *mipmap;
2188                         u32 toffset, moffset;
2189                         u32 size, offset;
2190
2191                         switch (G__SQ_CONSTANT_TYPE(radeon_get_ib_value(p, idx+1+(i*8)+7))) {
2192                         case SQ_TEX_VTX_VALID_TEXTURE:
2193                                 /* tex base */
2194                                 r = evergreen_cs_packet_next_reloc(p, &reloc);
2195                                 if (r) {
2196                                         DRM_ERROR("bad SET_RESOURCE (tex)\n");
2197                                         return -EINVAL;
2198                                 }
2199                                 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
2200                                         ib[idx+1+(i*8)+1] |=
2201                                                 TEX_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
2202                                         if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) {
2203                                                 unsigned bankw, bankh, mtaspect, tile_split;
2204
2205                                                 evergreen_tiling_fields(reloc->lobj.tiling_flags,
2206                                                                         &bankw, &bankh, &mtaspect,
2207                                                                         &tile_split);
2208                                                 ib[idx+1+(i*8)+6] |= TEX_TILE_SPLIT(tile_split);
2209                                                 ib[idx+1+(i*8)+7] |=
2210                                                         TEX_BANK_WIDTH(bankw) |
2211                                                         TEX_BANK_HEIGHT(bankh) |
2212                                                         MACRO_TILE_ASPECT(mtaspect) |
2213                                                         TEX_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks));
2214                                         }
2215                                 }
2216                                 texture = reloc->robj;
2217                                 toffset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
2218                                 /* tex mip base */
2219                                 r = evergreen_cs_packet_next_reloc(p, &reloc);
2220                                 if (r) {
2221                                         DRM_ERROR("bad SET_RESOURCE (tex)\n");
2222                                         return -EINVAL;
2223                                 }
2224                                 moffset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
2225                                 mipmap = reloc->robj;
2226                                 r = evergreen_cs_track_validate_texture(p, texture, mipmap, idx+1+(i*8));
2227                                 if (r)
2228                                         return r;
2229                                 ib[idx+1+(i*8)+2] += toffset;
2230                                 ib[idx+1+(i*8)+3] += moffset;
2231                                 break;
2232                         case SQ_TEX_VTX_VALID_BUFFER:
2233                         {
2234                                 uint64_t offset64;
2235                                 /* vtx base */
2236                                 r = evergreen_cs_packet_next_reloc(p, &reloc);
2237                                 if (r) {
2238                                         DRM_ERROR("bad SET_RESOURCE (vtx)\n");
2239                                         return -EINVAL;
2240                                 }
2241                                 offset = radeon_get_ib_value(p, idx+1+(i*8)+0);
2242                                 size = radeon_get_ib_value(p, idx+1+(i*8)+1);
2243                                 if (p->rdev && (size + offset) > radeon_bo_size(reloc->robj)) {
2244                                         /* force size to size of the buffer */
2245                                         dev_warn(p->dev, "vbo resource seems too big for the bo\n");
2246                                         ib[idx+1+(i*8)+1] = radeon_bo_size(reloc->robj) - offset;
2247                                 }
2248
2249                                 offset64 = reloc->lobj.gpu_offset + offset;
2250                                 ib[idx+1+(i*8)+0] = offset64;
2251                                 ib[idx+1+(i*8)+2] = (ib[idx+1+(i*8)+2] & 0xffffff00) |
2252                                                     (upper_32_bits(offset64) & 0xff);
2253                                 break;
2254                         }
2255                         case SQ_TEX_VTX_INVALID_TEXTURE:
2256                         case SQ_TEX_VTX_INVALID_BUFFER:
2257                         default:
2258                                 DRM_ERROR("bad SET_RESOURCE\n");
2259                                 return -EINVAL;
2260                         }
2261                 }
2262                 break;
2263         case PACKET3_SET_ALU_CONST:
2264                 /* XXX fix me ALU const buffers only */
2265                 break;
2266         case PACKET3_SET_BOOL_CONST:
2267                 start_reg = (idx_value << 2) + PACKET3_SET_BOOL_CONST_START;
2268                 end_reg = 4 * pkt->count + start_reg - 4;
2269                 if ((start_reg < PACKET3_SET_BOOL_CONST_START) ||
2270                     (start_reg >= PACKET3_SET_BOOL_CONST_END) ||
2271                     (end_reg >= PACKET3_SET_BOOL_CONST_END)) {
2272                         DRM_ERROR("bad SET_BOOL_CONST\n");
2273                         return -EINVAL;
2274                 }
2275                 break;
2276         case PACKET3_SET_LOOP_CONST:
2277                 start_reg = (idx_value << 2) + PACKET3_SET_LOOP_CONST_START;
2278                 end_reg = 4 * pkt->count + start_reg - 4;
2279                 if ((start_reg < PACKET3_SET_LOOP_CONST_START) ||
2280                     (start_reg >= PACKET3_SET_LOOP_CONST_END) ||
2281                     (end_reg >= PACKET3_SET_LOOP_CONST_END)) {
2282                         DRM_ERROR("bad SET_LOOP_CONST\n");
2283                         return -EINVAL;
2284                 }
2285                 break;
2286         case PACKET3_SET_CTL_CONST:
2287                 start_reg = (idx_value << 2) + PACKET3_SET_CTL_CONST_START;
2288                 end_reg = 4 * pkt->count + start_reg - 4;
2289                 if ((start_reg < PACKET3_SET_CTL_CONST_START) ||
2290                     (start_reg >= PACKET3_SET_CTL_CONST_END) ||
2291                     (end_reg >= PACKET3_SET_CTL_CONST_END)) {
2292                         DRM_ERROR("bad SET_CTL_CONST\n");
2293                         return -EINVAL;
2294                 }
2295                 break;
2296         case PACKET3_SET_SAMPLER:
2297                 if (pkt->count % 3) {
2298                         DRM_ERROR("bad SET_SAMPLER\n");
2299                         return -EINVAL;
2300                 }
2301                 start_reg = (idx_value << 2) + PACKET3_SET_SAMPLER_START;
2302                 end_reg = 4 * pkt->count + start_reg - 4;
2303                 if ((start_reg < PACKET3_SET_SAMPLER_START) ||
2304                     (start_reg >= PACKET3_SET_SAMPLER_END) ||
2305                     (end_reg >= PACKET3_SET_SAMPLER_END)) {
2306                         DRM_ERROR("bad SET_SAMPLER\n");
2307                         return -EINVAL;
2308                 }
2309                 break;
2310         case PACKET3_STRMOUT_BUFFER_UPDATE:
2311                 if (pkt->count != 4) {
2312                         DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (invalid count)\n");
2313                         return -EINVAL;
2314                 }
2315                 /* Updating memory at DST_ADDRESS. */
2316                 if (idx_value & 0x1) {
2317                         u64 offset;
2318                         r = evergreen_cs_packet_next_reloc(p, &reloc);
2319                         if (r) {
2320                                 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing dst reloc)\n");
2321                                 return -EINVAL;
2322                         }
2323                         offset = radeon_get_ib_value(p, idx+1);
2324                         offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;
2325                         if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2326                                 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE dst bo too small: 0x%llx, 0x%lx\n",
2327                                           offset + 4, radeon_bo_size(reloc->robj));
2328                                 return -EINVAL;
2329                         }
2330                         offset += reloc->lobj.gpu_offset;
2331                         ib[idx+1] = offset;
2332                         ib[idx+2] = upper_32_bits(offset) & 0xff;
2333                 }
2334                 /* Reading data from SRC_ADDRESS. */
2335                 if (((idx_value >> 1) & 0x3) == 2) {
2336                         u64 offset;
2337                         r = evergreen_cs_packet_next_reloc(p, &reloc);
2338                         if (r) {
2339                                 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing src reloc)\n");
2340                                 return -EINVAL;
2341                         }
2342                         offset = radeon_get_ib_value(p, idx+3);
2343                         offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;
2344                         if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2345                                 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE src bo too small: 0x%llx, 0x%lx\n",
2346                                           offset + 4, radeon_bo_size(reloc->robj));
2347                                 return -EINVAL;
2348                         }
2349                         offset += reloc->lobj.gpu_offset;
2350                         ib[idx+3] = offset;
2351                         ib[idx+4] = upper_32_bits(offset) & 0xff;
2352                 }
2353                 break;
2354         case PACKET3_COPY_DW:
2355                 if (pkt->count != 4) {
2356                         DRM_ERROR("bad COPY_DW (invalid count)\n");
2357                         return -EINVAL;
2358                 }
2359                 if (idx_value & 0x1) {
2360                         u64 offset;
2361                         /* SRC is memory. */
2362                         r = evergreen_cs_packet_next_reloc(p, &reloc);
2363                         if (r) {
2364                                 DRM_ERROR("bad COPY_DW (missing src reloc)\n");
2365                                 return -EINVAL;
2366                         }
2367                         offset = radeon_get_ib_value(p, idx+1);
2368                         offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;
2369                         if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2370                                 DRM_ERROR("bad COPY_DW src bo too small: 0x%llx, 0x%lx\n",
2371                                           offset + 4, radeon_bo_size(reloc->robj));
2372                                 return -EINVAL;
2373                         }
2374                         offset += reloc->lobj.gpu_offset;
2375                         ib[idx+1] = offset;
2376                         ib[idx+2] = upper_32_bits(offset) & 0xff;
2377                 } else {
2378                         /* SRC is a reg. */
2379                         reg = radeon_get_ib_value(p, idx+1) << 2;
2380                         if (!evergreen_is_safe_reg(p, reg, idx+1))
2381                                 return -EINVAL;
2382                 }
2383                 if (idx_value & 0x2) {
2384                         u64 offset;
2385                         /* DST is memory. */
2386                         r = evergreen_cs_packet_next_reloc(p, &reloc);
2387                         if (r) {
2388                                 DRM_ERROR("bad COPY_DW (missing dst reloc)\n");
2389                                 return -EINVAL;
2390                         }
2391                         offset = radeon_get_ib_value(p, idx+3);
2392                         offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;
2393                         if ((offset + 4) > radeon_bo_size(reloc->robj)) {
2394                                 DRM_ERROR("bad COPY_DW dst bo too small: 0x%llx, 0x%lx\n",
2395                                           offset + 4, radeon_bo_size(reloc->robj));
2396                                 return -EINVAL;
2397                         }
2398                         offset += reloc->lobj.gpu_offset;
2399                         ib[idx+3] = offset;
2400                         ib[idx+4] = upper_32_bits(offset) & 0xff;
2401                 } else {
2402                         /* DST is a reg. */
2403                         reg = radeon_get_ib_value(p, idx+3) << 2;
2404                         if (!evergreen_is_safe_reg(p, reg, idx+3))
2405                                 return -EINVAL;
2406                 }
2407                 break;
2408         case PACKET3_NOP:
2409                 break;
2410         default:
2411                 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
2412                 return -EINVAL;
2413         }
2414         return 0;
2415 }
2416
2417 int evergreen_cs_parse(struct radeon_cs_parser *p)
2418 {
2419         struct radeon_cs_packet pkt;
2420         struct evergreen_cs_track *track;
2421         u32 tmp;
2422         int r;
2423
2424         if (p->track == NULL) {
2425                 /* initialize tracker, we are in kms */
2426                 track = kzalloc(sizeof(*track), GFP_KERNEL);
2427                 if (track == NULL)
2428                         return -ENOMEM;
2429                 evergreen_cs_track_init(track);
2430                 if (p->rdev->family >= CHIP_CAYMAN)
2431                         tmp = p->rdev->config.cayman.tile_config;
2432                 else
2433                         tmp = p->rdev->config.evergreen.tile_config;
2434
2435                 switch (tmp & 0xf) {
2436                 case 0:
2437                         track->npipes = 1;
2438                         break;
2439                 case 1:
2440                 default:
2441                         track->npipes = 2;
2442                         break;
2443                 case 2:
2444                         track->npipes = 4;
2445                         break;
2446                 case 3:
2447                         track->npipes = 8;
2448                         break;
2449                 }
2450
2451                 switch ((tmp & 0xf0) >> 4) {
2452                 case 0:
2453                         track->nbanks = 4;
2454                         break;
2455                 case 1:
2456                 default:
2457                         track->nbanks = 8;
2458                         break;
2459                 case 2:
2460                         track->nbanks = 16;
2461                         break;
2462                 }
2463
2464                 switch ((tmp & 0xf00) >> 8) {
2465                 case 0:
2466                         track->group_size = 256;
2467                         break;
2468                 case 1:
2469                 default:
2470                         track->group_size = 512;
2471                         break;
2472                 }
2473
2474                 switch ((tmp & 0xf000) >> 12) {
2475                 case 0:
2476                         track->row_size = 1;
2477                         break;
2478                 case 1:
2479                 default:
2480                         track->row_size = 2;
2481                         break;
2482                 case 2:
2483                         track->row_size = 4;
2484                         break;
2485                 }
2486
2487                 p->track = track;
2488         }
2489         do {
2490                 r = evergreen_cs_packet_parse(p, &pkt, p->idx);
2491                 if (r) {
2492                         kfree(p->track);
2493                         p->track = NULL;
2494                         return r;
2495                 }
2496                 p->idx += pkt.count + 2;
2497                 switch (pkt.type) {
2498                 case PACKET_TYPE0:
2499                         r = evergreen_cs_parse_packet0(p, &pkt);
2500                         break;
2501                 case PACKET_TYPE2:
2502                         break;
2503                 case PACKET_TYPE3:
2504                         r = evergreen_packet3_check(p, &pkt);
2505                         break;
2506                 default:
2507                         DRM_ERROR("Unknown packet type %d !\n", pkt.type);
2508                         kfree(p->track);
2509                         p->track = NULL;
2510                         return -EINVAL;
2511                 }
2512                 if (r) {
2513                         kfree(p->track);
2514                         p->track = NULL;
2515                         return r;
2516                 }
2517         } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
2518 #if 0
2519         for (r = 0; r < p->ib->length_dw; r++) {
2520                 printk(KERN_INFO "%05d  0x%08X\n", r, p->ib->ptr[r]);
2521                 mdelay(1);
2522         }
2523 #endif
2524         kfree(p->track);
2525         p->track = NULL;
2526         return 0;
2527 }
2528
2529 /* vm parser */
2530 static bool evergreen_vm_reg_valid(u32 reg)
2531 {
2532         /* context regs are fine */
2533         if (reg >= 0x28000)
2534                 return true;
2535
2536         /* check config regs */
2537         switch (reg) {
2538         case GRBM_GFX_INDEX:
2539         case VGT_VTX_VECT_EJECT_REG:
2540         case VGT_CACHE_INVALIDATION:
2541         case VGT_GS_VERTEX_REUSE:
2542         case VGT_PRIMITIVE_TYPE:
2543         case VGT_INDEX_TYPE:
2544         case VGT_NUM_INDICES:
2545         case VGT_NUM_INSTANCES:
2546         case VGT_COMPUTE_DIM_X:
2547         case VGT_COMPUTE_DIM_Y:
2548         case VGT_COMPUTE_DIM_Z:
2549         case VGT_COMPUTE_START_X:
2550         case VGT_COMPUTE_START_Y:
2551         case VGT_COMPUTE_START_Z:
2552         case VGT_COMPUTE_INDEX:
2553         case VGT_COMPUTE_THREAD_GROUP_SIZE:
2554         case VGT_HS_OFFCHIP_PARAM:
2555         case PA_CL_ENHANCE:
2556         case PA_SU_LINE_STIPPLE_VALUE:
2557         case PA_SC_LINE_STIPPLE_STATE:
2558         case PA_SC_ENHANCE:
2559         case SQ_DYN_GPR_CNTL_PS_FLUSH_REQ:
2560         case SQ_DYN_GPR_SIMD_LOCK_EN:
2561         case SQ_CONFIG:
2562         case SQ_GPR_RESOURCE_MGMT_1:
2563         case SQ_GLOBAL_GPR_RESOURCE_MGMT_1:
2564         case SQ_GLOBAL_GPR_RESOURCE_MGMT_2:
2565         case SQ_CONST_MEM_BASE:
2566         case SQ_STATIC_THREAD_MGMT_1:
2567         case SQ_STATIC_THREAD_MGMT_2:
2568         case SQ_STATIC_THREAD_MGMT_3:
2569         case SPI_CONFIG_CNTL:
2570         case SPI_CONFIG_CNTL_1:
2571         case TA_CNTL_AUX:
2572         case DB_DEBUG:
2573         case DB_DEBUG2:
2574         case DB_DEBUG3:
2575         case DB_DEBUG4:
2576         case DB_WATERMARKS:
2577         case TD_PS_BORDER_COLOR_INDEX:
2578         case TD_PS_BORDER_COLOR_RED:
2579         case TD_PS_BORDER_COLOR_GREEN:
2580         case TD_PS_BORDER_COLOR_BLUE:
2581         case TD_PS_BORDER_COLOR_ALPHA:
2582         case TD_VS_BORDER_COLOR_INDEX:
2583         case TD_VS_BORDER_COLOR_RED:
2584         case TD_VS_BORDER_COLOR_GREEN:
2585         case TD_VS_BORDER_COLOR_BLUE:
2586         case TD_VS_BORDER_COLOR_ALPHA:
2587         case TD_GS_BORDER_COLOR_INDEX:
2588         case TD_GS_BORDER_COLOR_RED:
2589         case TD_GS_BORDER_COLOR_GREEN:
2590         case TD_GS_BORDER_COLOR_BLUE:
2591         case TD_GS_BORDER_COLOR_ALPHA:
2592         case TD_HS_BORDER_COLOR_INDEX:
2593         case TD_HS_BORDER_COLOR_RED:
2594         case TD_HS_BORDER_COLOR_GREEN:
2595         case TD_HS_BORDER_COLOR_BLUE:
2596         case TD_HS_BORDER_COLOR_ALPHA:
2597         case TD_LS_BORDER_COLOR_INDEX:
2598         case TD_LS_BORDER_COLOR_RED:
2599         case TD_LS_BORDER_COLOR_GREEN:
2600         case TD_LS_BORDER_COLOR_BLUE:
2601         case TD_LS_BORDER_COLOR_ALPHA:
2602         case TD_CS_BORDER_COLOR_INDEX:
2603         case TD_CS_BORDER_COLOR_RED:
2604         case TD_CS_BORDER_COLOR_GREEN:
2605         case TD_CS_BORDER_COLOR_BLUE:
2606         case TD_CS_BORDER_COLOR_ALPHA:
2607         case SQ_ESGS_RING_SIZE:
2608         case SQ_GSVS_RING_SIZE:
2609         case SQ_ESTMP_RING_SIZE:
2610         case SQ_GSTMP_RING_SIZE:
2611         case SQ_HSTMP_RING_SIZE:
2612         case SQ_LSTMP_RING_SIZE:
2613         case SQ_PSTMP_RING_SIZE:
2614         case SQ_VSTMP_RING_SIZE:
2615         case SQ_ESGS_RING_ITEMSIZE:
2616         case SQ_ESTMP_RING_ITEMSIZE:
2617         case SQ_GSTMP_RING_ITEMSIZE:
2618         case SQ_GSVS_RING_ITEMSIZE:
2619         case SQ_GS_VERT_ITEMSIZE:
2620         case SQ_GS_VERT_ITEMSIZE_1:
2621         case SQ_GS_VERT_ITEMSIZE_2:
2622         case SQ_GS_VERT_ITEMSIZE_3:
2623         case SQ_GSVS_RING_OFFSET_1:
2624         case SQ_GSVS_RING_OFFSET_2:
2625         case SQ_GSVS_RING_OFFSET_3:
2626         case SQ_HSTMP_RING_ITEMSIZE:
2627         case SQ_LSTMP_RING_ITEMSIZE:
2628         case SQ_PSTMP_RING_ITEMSIZE:
2629         case SQ_VSTMP_RING_ITEMSIZE:
2630         case VGT_TF_RING_SIZE:
2631         case SQ_ESGS_RING_BASE:
2632         case SQ_GSVS_RING_BASE:
2633         case SQ_ESTMP_RING_BASE:
2634         case SQ_GSTMP_RING_BASE:
2635         case SQ_HSTMP_RING_BASE:
2636         case SQ_LSTMP_RING_BASE:
2637         case SQ_PSTMP_RING_BASE:
2638         case SQ_VSTMP_RING_BASE:
2639         case CAYMAN_VGT_OFFCHIP_LDS_BASE:
2640         case CAYMAN_SQ_EX_ALLOC_TABLE_SLOTS:
2641                 return true;
2642         default:
2643                 return false;
2644         }
2645 }
2646
2647 static int evergreen_vm_packet3_check(struct radeon_device *rdev,
2648                                       u32 *ib, struct radeon_cs_packet *pkt)
2649 {
2650         u32 idx = pkt->idx + 1;
2651         u32 idx_value = ib[idx];
2652         u32 start_reg, end_reg, reg, i;
2653
2654         switch (pkt->opcode) {
2655         case PACKET3_NOP:
2656         case PACKET3_SET_BASE:
2657         case PACKET3_CLEAR_STATE:
2658         case PACKET3_INDEX_BUFFER_SIZE:
2659         case PACKET3_DISPATCH_DIRECT:
2660         case PACKET3_DISPATCH_INDIRECT:
2661         case PACKET3_MODE_CONTROL:
2662         case PACKET3_SET_PREDICATION:
2663         case PACKET3_COND_EXEC:
2664         case PACKET3_PRED_EXEC:
2665         case PACKET3_DRAW_INDIRECT:
2666         case PACKET3_DRAW_INDEX_INDIRECT:
2667         case PACKET3_INDEX_BASE:
2668         case PACKET3_DRAW_INDEX_2:
2669         case PACKET3_CONTEXT_CONTROL:
2670         case PACKET3_DRAW_INDEX_OFFSET:
2671         case PACKET3_INDEX_TYPE:
2672         case PACKET3_DRAW_INDEX:
2673         case PACKET3_DRAW_INDEX_AUTO:
2674         case PACKET3_DRAW_INDEX_IMMD:
2675         case PACKET3_NUM_INSTANCES:
2676         case PACKET3_DRAW_INDEX_MULTI_AUTO:
2677         case PACKET3_STRMOUT_BUFFER_UPDATE:
2678         case PACKET3_DRAW_INDEX_OFFSET_2:
2679         case PACKET3_DRAW_INDEX_MULTI_ELEMENT:
2680         case PACKET3_MPEG_INDEX:
2681         case PACKET3_WAIT_REG_MEM:
2682         case PACKET3_MEM_WRITE:
2683         case PACKET3_SURFACE_SYNC:
2684         case PACKET3_EVENT_WRITE:
2685         case PACKET3_EVENT_WRITE_EOP:
2686         case PACKET3_EVENT_WRITE_EOS:
2687         case PACKET3_SET_CONTEXT_REG:
2688         case PACKET3_SET_BOOL_CONST:
2689         case PACKET3_SET_LOOP_CONST:
2690         case PACKET3_SET_RESOURCE:
2691         case PACKET3_SET_SAMPLER:
2692         case PACKET3_SET_CTL_CONST:
2693         case PACKET3_SET_RESOURCE_OFFSET:
2694         case PACKET3_SET_CONTEXT_REG_INDIRECT:
2695         case PACKET3_SET_RESOURCE_INDIRECT:
2696         case CAYMAN_PACKET3_DEALLOC_STATE:
2697                 break;
2698         case PACKET3_COND_WRITE:
2699                 if (idx_value & 0x100) {
2700                         reg = ib[idx + 5] * 4;
2701                         if (!evergreen_vm_reg_valid(reg))
2702                                 return -EINVAL;
2703                 }
2704                 break;
2705         case PACKET3_COPY_DW:
2706                 if (idx_value & 0x2) {
2707                         reg = ib[idx + 3] * 4;
2708                         if (!evergreen_vm_reg_valid(reg))
2709                                 return -EINVAL;
2710                 }
2711                 break;
2712         case PACKET3_SET_CONFIG_REG:
2713                 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START;
2714                 end_reg = 4 * pkt->count + start_reg - 4;
2715                 if ((start_reg < PACKET3_SET_CONFIG_REG_START) ||
2716                     (start_reg >= PACKET3_SET_CONFIG_REG_END) ||
2717                     (end_reg >= PACKET3_SET_CONFIG_REG_END)) {
2718                         DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n");
2719                         return -EINVAL;
2720                 }
2721                 for (i = 0; i < pkt->count; i++) {
2722                         reg = start_reg + (4 * i);
2723                         if (!evergreen_vm_reg_valid(reg))
2724                                 return -EINVAL;
2725                 }
2726                 break;
2727         default:
2728                 return -EINVAL;
2729         }
2730         return 0;
2731 }
2732
2733 int evergreen_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib)
2734 {
2735         int ret = 0;
2736         u32 idx = 0;
2737         struct radeon_cs_packet pkt;
2738
2739         do {
2740                 pkt.idx = idx;
2741                 pkt.type = CP_PACKET_GET_TYPE(ib->ptr[idx]);
2742                 pkt.count = CP_PACKET_GET_COUNT(ib->ptr[idx]);
2743                 pkt.one_reg_wr = 0;
2744                 switch (pkt.type) {
2745                 case PACKET_TYPE0:
2746                         dev_err(rdev->dev, "Packet0 not allowed!\n");
2747                         ret = -EINVAL;
2748                         break;
2749                 case PACKET_TYPE2:
2750                         idx += 1;
2751                         break;
2752                 case PACKET_TYPE3:
2753                         pkt.opcode = CP_PACKET3_GET_OPCODE(ib->ptr[idx]);
2754                         ret = evergreen_vm_packet3_check(rdev, ib->ptr, &pkt);
2755                         idx += pkt.count + 2;
2756                         break;
2757                 default:
2758                         dev_err(rdev->dev, "Unknown packet type %d !\n", pkt.type);
2759                         ret = -EINVAL;
2760                         break;
2761                 }
2762                 if (ret)
2763                         break;
2764         } while (idx < ib->length_dw);
2765
2766         return ret;
2767 }