Pileus Git - ~andy/linux/blob - drivers/gpu/drm/radeon/evergreen_blit_kms.c

   1 /*
   2  * Copyright 2010 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *     Alex Deucher <alexander.deucher@amd.com>
  25  */
  26
  27 #include "drmP.h"
  28 #include "drm.h"
  29 #include "radeon_drm.h"
  30 #include "radeon.h"
  31
  32 #include "evergreend.h"
  33 #include "evergreen_blit_shaders.h"
  34
  35 #define DI_PT_RECTLIST        0x11
  36 #define DI_INDEX_SIZE_16_BIT  0x0
  37 #define DI_SRC_SEL_AUTO_INDEX 0x2
  38
  39 #define FMT_8                 0x1
  40 #define FMT_5_6_5             0x8
  41 #define FMT_8_8_8_8           0x1a
  42 #define COLOR_8               0x1
  43 #define COLOR_5_6_5           0x8
  44 #define COLOR_8_8_8_8         0x1a
  45
  46 /* emits 17 */
  47 static void
  48 set_render_target(struct radeon_device *rdev, int format,
  49                   int w, int h, u64 gpu_addr)
  50 {
  51         u32 cb_color_info;
  52         int pitch, slice;
  53
  54         h = ALIGN(h, 8);
  55         if (h < 8)
  56                 h = 8;
  57
  58         cb_color_info = ((format << 2) | (1 << 24));
  59         pitch = (w / 8) - 1;
  60         slice = ((w * h) / 64) - 1;
  61
  62         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 15));
  63         radeon_ring_write(rdev, (CB_COLOR0_BASE - PACKET3_SET_CONTEXT_REG_START) >> 2);
  64         radeon_ring_write(rdev, gpu_addr >> 8);
  65         radeon_ring_write(rdev, pitch);
  66         radeon_ring_write(rdev, slice);
  67         radeon_ring_write(rdev, 0);
  68         radeon_ring_write(rdev, cb_color_info);
  69         radeon_ring_write(rdev, (1 << 4));
  70         radeon_ring_write(rdev, (w - 1) | ((h - 1) << 16));
  71         radeon_ring_write(rdev, 0);
  72         radeon_ring_write(rdev, 0);
  73         radeon_ring_write(rdev, 0);
  74         radeon_ring_write(rdev, 0);
  75         radeon_ring_write(rdev, 0);
  76         radeon_ring_write(rdev, 0);
  77         radeon_ring_write(rdev, 0);
  78         radeon_ring_write(rdev, 0);
  79 }
  80
  81 /* emits 5dw */
  82 static void
  83 cp_set_surface_sync(struct radeon_device *rdev,
  84                     u32 sync_type, u32 size,
  85                     u64 mc_addr)
  86 {
  87         u32 cp_coher_size;
  88
  89         if (size == 0xffffffff)
  90                 cp_coher_size = 0xffffffff;
  91         else
  92                 cp_coher_size = ((size + 255) >> 8);
  93
  94         radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_SYNC, 3));
  95         radeon_ring_write(rdev, sync_type);
  96         radeon_ring_write(rdev, cp_coher_size);
  97         radeon_ring_write(rdev, mc_addr >> 8);
  98         radeon_ring_write(rdev, 10); /* poll interval */
  99 }
 100
 101 /* emits 11dw + 1 surface sync = 16dw */
 102 static void
 103 set_shaders(struct radeon_device *rdev)
 104 {
 105         u64 gpu_addr;
 106
 107         /* VS */
 108         gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
 109         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 3));
 110         radeon_ring_write(rdev, (SQ_PGM_START_VS - PACKET3_SET_CONTEXT_REG_START) >> 2);
 111         radeon_ring_write(rdev, gpu_addr >> 8);
 112         radeon_ring_write(rdev, 2);
 113         radeon_ring_write(rdev, 0);
 114
 115         /* PS */
 116         gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.ps_offset;
 117         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 4));
 118         radeon_ring_write(rdev, (SQ_PGM_START_PS - PACKET3_SET_CONTEXT_REG_START) >> 2);
 119         radeon_ring_write(rdev, gpu_addr >> 8);
 120         radeon_ring_write(rdev, 1);
 121         radeon_ring_write(rdev, 0);
 122         radeon_ring_write(rdev, 2);
 123
 124         gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
 125         cp_set_surface_sync(rdev, PACKET3_SH_ACTION_ENA, 512, gpu_addr);
 126 }
 127
 128 /* emits 10 + 1 sync (5) = 15 */
 129 static void
 130 set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr)
 131 {
 132         u32 sq_vtx_constant_word2, sq_vtx_constant_word3;
 133
 134         /* high addr, stride */
 135         sq_vtx_constant_word2 = ((upper_32_bits(gpu_addr) & 0xff) | (16 << 8));
 136         /* xyzw swizzles */
 137         sq_vtx_constant_word3 = (0 << 3) | (1 << 6) | (2 << 9) | (3 << 12);
 138
 139         radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 8));
 140         radeon_ring_write(rdev, 0x580);
 141         radeon_ring_write(rdev, gpu_addr & 0xffffffff);
 142         radeon_ring_write(rdev, 48 - 1); /* size */
 143         radeon_ring_write(rdev, sq_vtx_constant_word2);
 144         radeon_ring_write(rdev, sq_vtx_constant_word3);
 145         radeon_ring_write(rdev, 0);
 146         radeon_ring_write(rdev, 0);
 147         radeon_ring_write(rdev, 0);
 148         radeon_ring_write(rdev, SQ_TEX_VTX_VALID_BUFFER << 30);
 149
 150         if ((rdev->family == CHIP_CEDAR) ||
 151             (rdev->family == CHIP_PALM))
 152                 cp_set_surface_sync(rdev,
 153                                     PACKET3_TC_ACTION_ENA, 48, gpu_addr);
 154         else
 155                 cp_set_surface_sync(rdev,
 156                                     PACKET3_VC_ACTION_ENA, 48, gpu_addr);
 157
 158 }
 159
 160 /* emits 10 */
 161 static void
 162 set_tex_resource(struct radeon_device *rdev,
 163                  int format, int w, int h, int pitch,
 164                  u64 gpu_addr)
 165 {
 166         u32 sq_tex_resource_word0, sq_tex_resource_word1;
 167         u32 sq_tex_resource_word4, sq_tex_resource_word7;
 168
 169         if (h < 1)
 170                 h = 1;
 171
 172         sq_tex_resource_word0 = (1 << 0); /* 2D */
 173         sq_tex_resource_word0 |= ((((pitch >> 3) - 1) << 6) |
 174                                   ((w - 1) << 18));
 175         sq_tex_resource_word1 = ((h - 1) << 0);
 176         /* xyzw swizzles */
 177         sq_tex_resource_word4 = (0 << 16) | (1 << 19) | (2 << 22) | (3 << 25);
 178
 179         sq_tex_resource_word7 = format | (SQ_TEX_VTX_VALID_TEXTURE << 30);
 180
 181         radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 8));
 182         radeon_ring_write(rdev, 0);
 183         radeon_ring_write(rdev, sq_tex_resource_word0);
 184         radeon_ring_write(rdev, sq_tex_resource_word1);
 185         radeon_ring_write(rdev, gpu_addr >> 8);
 186         radeon_ring_write(rdev, gpu_addr >> 8);
 187         radeon_ring_write(rdev, sq_tex_resource_word4);
 188         radeon_ring_write(rdev, 0);
 189         radeon_ring_write(rdev, 0);
 190         radeon_ring_write(rdev, sq_tex_resource_word7);
 191 }
 192
 193 /* emits 12 */
 194 static void
 195 set_scissors(struct radeon_device *rdev, int x1, int y1,
 196              int x2, int y2)
 197 {
 198         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
 199         radeon_ring_write(rdev, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2);
 200         radeon_ring_write(rdev, (x1 << 0) | (y1 << 16));
 201         radeon_ring_write(rdev, (x2 << 0) | (y2 << 16));
 202
 203         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
 204         radeon_ring_write(rdev, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2);
 205         radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31));
 206         radeon_ring_write(rdev, (x2 << 0) | (y2 << 16));
 207
 208         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
 209         radeon_ring_write(rdev, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2);
 210         radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31));
 211         radeon_ring_write(rdev, (x2 << 0) | (y2 << 16));
 212 }
 213
 214 /* emits 10 */
 215 static void
 216 draw_auto(struct radeon_device *rdev)
 217 {
 218         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
 219         radeon_ring_write(rdev, (VGT_PRIMITIVE_TYPE - PACKET3_SET_CONFIG_REG_START) >> 2);
 220         radeon_ring_write(rdev, DI_PT_RECTLIST);
 221
 222         radeon_ring_write(rdev, PACKET3(PACKET3_INDEX_TYPE, 0));
 223         radeon_ring_write(rdev, DI_INDEX_SIZE_16_BIT);
 224
 225         radeon_ring_write(rdev, PACKET3(PACKET3_NUM_INSTANCES, 0));
 226         radeon_ring_write(rdev, 1);
 227
 228         radeon_ring_write(rdev, PACKET3(PACKET3_DRAW_INDEX_AUTO, 1));
 229         radeon_ring_write(rdev, 3);
 230         radeon_ring_write(rdev, DI_SRC_SEL_AUTO_INDEX);
 231
 232 }
 233
 234 /* emits 30 */
 235 static void
 236 set_default_state(struct radeon_device *rdev)
 237 {
 238         u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2, sq_gpr_resource_mgmt_3;
 239         u32 sq_thread_resource_mgmt, sq_thread_resource_mgmt_2;
 240         u32 sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2, sq_stack_resource_mgmt_3;
 241         int num_ps_gprs, num_vs_gprs, num_temp_gprs;
 242         int num_gs_gprs, num_es_gprs, num_hs_gprs, num_ls_gprs;
 243         int num_ps_threads, num_vs_threads, num_gs_threads, num_es_threads;
 244         int num_hs_threads, num_ls_threads;
 245         int num_ps_stack_entries, num_vs_stack_entries, num_gs_stack_entries, num_es_stack_entries;
 246         int num_hs_stack_entries, num_ls_stack_entries;
 247
 248         switch (rdev->family) {
 249         case CHIP_CEDAR:
 250         default:
 251                 num_ps_gprs = 93;
 252                 num_vs_gprs = 46;
 253                 num_temp_gprs = 4;
 254                 num_gs_gprs = 31;
 255                 num_es_gprs = 31;
 256                 num_hs_gprs = 23;
 257                 num_ls_gprs = 23;
 258                 num_ps_threads = 96;
 259                 num_vs_threads = 16;
 260                 num_gs_threads = 16;
 261                 num_es_threads = 16;
 262                 num_hs_threads = 16;
 263                 num_ls_threads = 16;
 264                 num_ps_stack_entries = 42;
 265                 num_vs_stack_entries = 42;
 266                 num_gs_stack_entries = 42;
 267                 num_es_stack_entries = 42;
 268                 num_hs_stack_entries = 42;
 269                 num_ls_stack_entries = 42;
 270                 break;
 271         case CHIP_REDWOOD:
 272                 num_ps_gprs = 93;
 273                 num_vs_gprs = 46;
 274                 num_temp_gprs = 4;
 275                 num_gs_gprs = 31;
 276                 num_es_gprs = 31;
 277                 num_hs_gprs = 23;
 278                 num_ls_gprs = 23;
 279                 num_ps_threads = 128;
 280                 num_vs_threads = 20;
 281                 num_gs_threads = 20;
 282                 num_es_threads = 20;
 283                 num_hs_threads = 20;
 284                 num_ls_threads = 20;
 285                 num_ps_stack_entries = 42;
 286                 num_vs_stack_entries = 42;
 287                 num_gs_stack_entries = 42;
 288                 num_es_stack_entries = 42;
 289                 num_hs_stack_entries = 42;
 290                 num_ls_stack_entries = 42;
 291                 break;
 292         case CHIP_JUNIPER:
 293                 num_ps_gprs = 93;
 294                 num_vs_gprs = 46;
 295                 num_temp_gprs = 4;
 296                 num_gs_gprs = 31;
 297                 num_es_gprs = 31;
 298                 num_hs_gprs = 23;
 299                 num_ls_gprs = 23;
 300                 num_ps_threads = 128;
 301                 num_vs_threads = 20;
 302                 num_gs_threads = 20;
 303                 num_es_threads = 20;
 304                 num_hs_threads = 20;
 305                 num_ls_threads = 20;
 306                 num_ps_stack_entries = 85;
 307                 num_vs_stack_entries = 85;
 308                 num_gs_stack_entries = 85;
 309                 num_es_stack_entries = 85;
 310                 num_hs_stack_entries = 85;
 311                 num_ls_stack_entries = 85;
 312                 break;
 313         case CHIP_CYPRESS:
 314         case CHIP_HEMLOCK:
 315                 num_ps_gprs = 93;
 316                 num_vs_gprs = 46;
 317                 num_temp_gprs = 4;
 318                 num_gs_gprs = 31;
 319                 num_es_gprs = 31;
 320                 num_hs_gprs = 23;
 321                 num_ls_gprs = 23;
 322                 num_ps_threads = 128;
 323                 num_vs_threads = 20;
 324                 num_gs_threads = 20;
 325                 num_es_threads = 20;
 326                 num_hs_threads = 20;
 327                 num_ls_threads = 20;
 328                 num_ps_stack_entries = 85;
 329                 num_vs_stack_entries = 85;
 330                 num_gs_stack_entries = 85;
 331                 num_es_stack_entries = 85;
 332                 num_hs_stack_entries = 85;
 333                 num_ls_stack_entries = 85;
 334                 break;
 335         case CHIP_PALM:
 336                 num_ps_gprs = 93;
 337                 num_vs_gprs = 46;
 338                 num_temp_gprs = 4;
 339                 num_gs_gprs = 31;
 340                 num_es_gprs = 31;
 341                 num_hs_gprs = 23;
 342                 num_ls_gprs = 23;
 343                 num_ps_threads = 96;
 344                 num_vs_threads = 16;
 345                 num_gs_threads = 16;
 346                 num_es_threads = 16;
 347                 num_hs_threads = 16;
 348                 num_ls_threads = 16;
 349                 num_ps_stack_entries = 42;
 350                 num_vs_stack_entries = 42;
 351                 num_gs_stack_entries = 42;
 352                 num_es_stack_entries = 42;
 353                 num_hs_stack_entries = 42;
 354                 num_ls_stack_entries = 42;
 355                 break;
 356         }
 357
 358         if ((rdev->family == CHIP_CEDAR) ||
 359             (rdev->family == CHIP_PALM))
 360                 sq_config = 0;
 361         else
 362                 sq_config = VC_ENABLE;
 363
 364         sq_config |= (EXPORT_SRC_C |
 365                       CS_PRIO(0) |
 366                       LS_PRIO(0) |
 367                       HS_PRIO(0) |
 368                       PS_PRIO(0) |
 369                       VS_PRIO(1) |
 370                       GS_PRIO(2) |
 371                       ES_PRIO(3));
 372
 373         sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(num_ps_gprs) |
 374                                   NUM_VS_GPRS(num_vs_gprs) |
 375                                   NUM_CLAUSE_TEMP_GPRS(num_temp_gprs));
 376         sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(num_gs_gprs) |
 377                                   NUM_ES_GPRS(num_es_gprs));
 378         sq_gpr_resource_mgmt_3 = (NUM_HS_GPRS(num_hs_gprs) |
 379                                   NUM_LS_GPRS(num_ls_gprs));
 380         sq_thread_resource_mgmt = (NUM_PS_THREADS(num_ps_threads) |
 381                                    NUM_VS_THREADS(num_vs_threads) |
 382                                    NUM_GS_THREADS(num_gs_threads) |
 383                                    NUM_ES_THREADS(num_es_threads));
 384         sq_thread_resource_mgmt_2 = (NUM_HS_THREADS(num_hs_threads) |
 385                                      NUM_LS_THREADS(num_ls_threads));
 386         sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(num_ps_stack_entries) |
 387                                     NUM_VS_STACK_ENTRIES(num_vs_stack_entries));
 388         sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(num_gs_stack_entries) |
 389                                     NUM_ES_STACK_ENTRIES(num_es_stack_entries));
 390         sq_stack_resource_mgmt_3 = (NUM_HS_STACK_ENTRIES(num_hs_stack_entries) |
 391                                     NUM_LS_STACK_ENTRIES(num_ls_stack_entries));
 392
 393         /* set clear context state */
 394         radeon_ring_write(rdev, PACKET3(PACKET3_CLEAR_STATE, 0));
 395         radeon_ring_write(rdev, 0);
 396
 397         /* disable dyn gprs */
 398         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
 399         radeon_ring_write(rdev, (SQ_DYN_GPR_CNTL_PS_FLUSH_REQ - PACKET3_SET_CONFIG_REG_START) >> 2);
 400         radeon_ring_write(rdev, 0);
 401
 402         /* SQ config */
 403         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 11));
 404         radeon_ring_write(rdev, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_START) >> 2);
 405         radeon_ring_write(rdev, sq_config);
 406         radeon_ring_write(rdev, sq_gpr_resource_mgmt_1);
 407         radeon_ring_write(rdev, sq_gpr_resource_mgmt_2);
 408         radeon_ring_write(rdev, sq_gpr_resource_mgmt_3);
 409         radeon_ring_write(rdev, 0);
 410         radeon_ring_write(rdev, 0);
 411         radeon_ring_write(rdev, sq_thread_resource_mgmt);
 412         radeon_ring_write(rdev, sq_thread_resource_mgmt_2);
 413         radeon_ring_write(rdev, sq_stack_resource_mgmt_1);
 414         radeon_ring_write(rdev, sq_stack_resource_mgmt_2);
 415         radeon_ring_write(rdev, sq_stack_resource_mgmt_3);
 416
 417         /* CONTEXT_CONTROL */
 418         radeon_ring_write(rdev, 0xc0012800);
 419         radeon_ring_write(rdev, 0x80000000);
 420         radeon_ring_write(rdev, 0x80000000);
 421
 422         /* SQ_VTX_BASE_VTX_LOC */
 423         radeon_ring_write(rdev, 0xc0026f00);
 424         radeon_ring_write(rdev, 0x00000000);
 425         radeon_ring_write(rdev, 0x00000000);
 426         radeon_ring_write(rdev, 0x00000000);
 427
 428         /* SET_SAMPLER */
 429         radeon_ring_write(rdev, 0xc0036e00);
 430         radeon_ring_write(rdev, 0x00000000);
 431         radeon_ring_write(rdev, 0x00000012);
 432         radeon_ring_write(rdev, 0x00000000);
 433         radeon_ring_write(rdev, 0x00000000);
 434
 435 }
 436
 437 static inline uint32_t i2f(uint32_t input)
 438 {
 439         u32 result, i, exponent, fraction;
 440
 441         if ((input & 0x3fff) == 0)
 442                 result = 0; /* 0 is a special case */
 443         else {
 444                 exponent = 140; /* exponent biased by 127; */
 445                 fraction = (input & 0x3fff) << 10; /* cheat and only
 446                                                       handle numbers below 2^^15 */
 447                 for (i = 0; i < 14; i++) {
 448                         if (fraction & 0x800000)
 449                                 break;
 450                         else {
 451                                 fraction = fraction << 1; /* keep
 452                                                              shifting left until top bit = 1 */
 453                                 exponent = exponent - 1;
 454                         }
 455                 }
 456                 result = exponent << 23 | (fraction & 0x7fffff); /* mask
 457                                                                     off top bit; assumed 1 */
 458         }
 459         return result;
 460 }
 461
 462 int evergreen_blit_init(struct radeon_device *rdev)
 463 {
 464         u32 obj_size;
 465         int r;
 466         void *ptr;
 467
 468         /* pin copy shader into vram if already initialized */
 469         if (rdev->r600_blit.shader_obj)
 470                 goto done;
 471
 472         mutex_init(&rdev->r600_blit.mutex);
 473         rdev->r600_blit.state_offset = 0;
 474         rdev->r600_blit.state_len = 0;
 475         obj_size = 0;
 476
 477         rdev->r600_blit.vs_offset = obj_size;
 478         obj_size += evergreen_vs_size * 4;
 479         obj_size = ALIGN(obj_size, 256);
 480
 481         rdev->r600_blit.ps_offset = obj_size;
 482         obj_size += evergreen_ps_size * 4;
 483         obj_size = ALIGN(obj_size, 256);
 484
 485         r = radeon_bo_create(rdev, NULL, obj_size, PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
 486                                 &rdev->r600_blit.shader_obj);
 487         if (r) {
 488                 DRM_ERROR("evergreen failed to allocate shader\n");
 489                 return r;
 490         }
 491
 492         DRM_DEBUG("evergreen blit allocated bo %08x vs %08x ps %08x\n",
 493                   obj_size,
 494                   rdev->r600_blit.vs_offset, rdev->r600_blit.ps_offset);
 495
 496         r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
 497         if (unlikely(r != 0))
 498                 return r;
 499         r = radeon_bo_kmap(rdev->r600_blit.shader_obj, &ptr);
 500         if (r) {
 501                 DRM_ERROR("failed to map blit object %d\n", r);
 502                 return r;
 503         }
 504
 505         memcpy(ptr + rdev->r600_blit.vs_offset, evergreen_vs, evergreen_vs_size * 4);
 506         memcpy(ptr + rdev->r600_blit.ps_offset, evergreen_ps, evergreen_ps_size * 4);
 507         radeon_bo_kunmap(rdev->r600_blit.shader_obj);
 508         radeon_bo_unreserve(rdev->r600_blit.shader_obj);
 509
 510 done:
 511         r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
 512         if (unlikely(r != 0))
 513                 return r;
 514         r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
 515                           &rdev->r600_blit.shader_gpu_addr);
 516         radeon_bo_unreserve(rdev->r600_blit.shader_obj);
 517         if (r) {
 518                 dev_err(rdev->dev, "(%d) pin blit object failed\n", r);
 519                 return r;
 520         }
 521         rdev->mc.active_vram_size = rdev->mc.real_vram_size;
 522         return 0;
 523 }
 524
 525 void evergreen_blit_fini(struct radeon_device *rdev)
 526 {
 527         int r;
 528
 529         rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
 530         if (rdev->r600_blit.shader_obj == NULL)
 531                 return;
 532         /* If we can't reserve the bo, unref should be enough to destroy
 533          * it when it becomes idle.
 534          */
 535         r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
 536         if (!r) {
 537                 radeon_bo_unpin(rdev->r600_blit.shader_obj);
 538                 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
 539         }
 540         radeon_bo_unref(&rdev->r600_blit.shader_obj);
 541 }
 542
 543 static int evergreen_vb_ib_get(struct radeon_device *rdev)
 544 {
 545         int r;
 546         r = radeon_ib_get(rdev, &rdev->r600_blit.vb_ib);
 547         if (r) {
 548                 DRM_ERROR("failed to get IB for vertex buffer\n");
 549                 return r;
 550         }
 551
 552         rdev->r600_blit.vb_total = 64*1024;
 553         rdev->r600_blit.vb_used = 0;
 554         return 0;
 555 }
 556
 557 static void evergreen_vb_ib_put(struct radeon_device *rdev)
 558 {
 559         radeon_fence_emit(rdev, rdev->r600_blit.vb_ib->fence);
 560         radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
 561 }
 562
 563 int evergreen_blit_prepare_copy(struct radeon_device *rdev, int size_bytes)
 564 {
 565         int r;
 566         int ring_size, line_size;
 567         int max_size;
 568         /* loops of emits + fence emit possible */
 569         int dwords_per_loop = 74, num_loops;
 570
 571         r = evergreen_vb_ib_get(rdev);
 572         if (r)
 573                 return r;
 574
 575         /* 8 bpp vs 32 bpp for xfer unit */
 576         if (size_bytes & 3)
 577                 line_size = 8192;
 578         else
 579                 line_size = 8192 * 4;
 580
 581         max_size = 8192 * line_size;
 582
 583         /* major loops cover the max size transfer */
 584         num_loops = ((size_bytes + max_size) / max_size);
 585         /* minor loops cover the extra non aligned bits */
 586         num_loops += ((size_bytes % line_size) ? 1 : 0);
 587         /* calculate number of loops correctly */
 588         ring_size = num_loops * dwords_per_loop;
 589         /* set default  + shaders */
 590         ring_size += 46; /* shaders + def state */
 591         ring_size += 10; /* fence emit for VB IB */
 592         ring_size += 5; /* done copy */
 593         ring_size += 10; /* fence emit for done copy */
 594         r = radeon_ring_lock(rdev, ring_size);
 595         if (r)
 596                 return r;
 597
 598         set_default_state(rdev); /* 30 */
 599         set_shaders(rdev); /* 16 */
 600         return 0;
 601 }
 602
 603 void evergreen_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence)
 604 {
 605         int r;
 606
 607         if (rdev->r600_blit.vb_ib)
 608                 evergreen_vb_ib_put(rdev);
 609
 610         if (fence)
 611                 r = radeon_fence_emit(rdev, fence);
 612
 613         radeon_ring_unlock_commit(rdev);
 614 }
 615
 616 void evergreen_kms_blit_copy(struct radeon_device *rdev,
 617                              u64 src_gpu_addr, u64 dst_gpu_addr,
 618                              int size_bytes)
 619 {
 620         int max_bytes;
 621         u64 vb_gpu_addr;
 622         u32 *vb;
 623
 624         DRM_DEBUG("emitting copy %16llx %16llx %d %d\n", src_gpu_addr, dst_gpu_addr,
 625                   size_bytes, rdev->r600_blit.vb_used);
 626         vb = (u32 *)(rdev->r600_blit.vb_ib->ptr + rdev->r600_blit.vb_used);
 627         if ((size_bytes & 3) || (src_gpu_addr & 3) || (dst_gpu_addr & 3)) {
 628                 max_bytes = 8192;
 629
 630                 while (size_bytes) {
 631                         int cur_size = size_bytes;
 632                         int src_x = src_gpu_addr & 255;
 633                         int dst_x = dst_gpu_addr & 255;
 634                         int h = 1;
 635                         src_gpu_addr = src_gpu_addr & ~255ULL;
 636                         dst_gpu_addr = dst_gpu_addr & ~255ULL;
 637
 638                         if (!src_x && !dst_x) {
 639                                 h = (cur_size / max_bytes);
 640                                 if (h > 8192)
 641                                         h = 8192;
 642                                 if (h == 0)
 643                                         h = 1;
 644                                 else
 645                                         cur_size = max_bytes;
 646                         } else {
 647                                 if (cur_size > max_bytes)
 648                                         cur_size = max_bytes;
 649                                 if (cur_size > (max_bytes - dst_x))
 650                                         cur_size = (max_bytes - dst_x);
 651                                 if (cur_size > (max_bytes - src_x))
 652                                         cur_size = (max_bytes - src_x);
 653                         }
 654
 655                         if ((rdev->r600_blit.vb_used + 48) > rdev->r600_blit.vb_total) {
 656                                 WARN_ON(1);
 657                         }
 658
 659                         vb[0] = i2f(dst_x);
 660                         vb[1] = 0;
 661                         vb[2] = i2f(src_x);
 662                         vb[3] = 0;
 663
 664                         vb[4] = i2f(dst_x);
 665                         vb[5] = i2f(h);
 666                         vb[6] = i2f(src_x);
 667                         vb[7] = i2f(h);
 668
 669                         vb[8] = i2f(dst_x + cur_size);
 670                         vb[9] = i2f(h);
 671                         vb[10] = i2f(src_x + cur_size);
 672                         vb[11] = i2f(h);
 673
 674                         /* src 10 */
 675                         set_tex_resource(rdev, FMT_8,
 676                                          src_x + cur_size, h, src_x + cur_size,
 677                                          src_gpu_addr);
 678
 679                         /* 5 */
 680                         cp_set_surface_sync(rdev,
 681                                             PACKET3_TC_ACTION_ENA, (src_x + cur_size * h), src_gpu_addr);
 682
 683
 684                         /* dst 17 */
 685                         set_render_target(rdev, COLOR_8,
 686                                           dst_x + cur_size, h,
 687                                           dst_gpu_addr);
 688
 689                         /* scissors 12 */
 690                         set_scissors(rdev, dst_x, 0, dst_x + cur_size, h);
 691
 692                         /* 15 */
 693                         vb_gpu_addr = rdev->r600_blit.vb_ib->gpu_addr + rdev->r600_blit.vb_used;
 694                         set_vtx_resource(rdev, vb_gpu_addr);
 695
 696                         /* draw 10 */
 697                         draw_auto(rdev);
 698
 699                         /* 5 */
 700                         cp_set_surface_sync(rdev,
 701                                             PACKET3_CB_ACTION_ENA | PACKET3_CB0_DEST_BASE_ENA,
 702                                             cur_size * h, dst_gpu_addr);
 703
 704                         vb += 12;
 705                         rdev->r600_blit.vb_used += 12 * 4;
 706
 707                         src_gpu_addr += cur_size * h;
 708                         dst_gpu_addr += cur_size * h;
 709                         size_bytes -= cur_size * h;
 710                 }
 711         } else {
 712                 max_bytes = 8192 * 4;
 713
 714                 while (size_bytes) {
 715                         int cur_size = size_bytes;
 716                         int src_x = (src_gpu_addr & 255);
 717                         int dst_x = (dst_gpu_addr & 255);
 718                         int h = 1;
 719                         src_gpu_addr = src_gpu_addr & ~255ULL;
 720                         dst_gpu_addr = dst_gpu_addr & ~255ULL;
 721
 722                         if (!src_x && !dst_x) {
 723                                 h = (cur_size / max_bytes);
 724                                 if (h > 8192)
 725                                         h = 8192;
 726                                 if (h == 0)
 727                                         h = 1;
 728                                 else
 729                                         cur_size = max_bytes;
 730                         } else {
 731                                 if (cur_size > max_bytes)
 732                                         cur_size = max_bytes;
 733                                 if (cur_size > (max_bytes - dst_x))
 734                                         cur_size = (max_bytes - dst_x);
 735                                 if (cur_size > (max_bytes - src_x))
 736                                         cur_size = (max_bytes - src_x);
 737                         }
 738
 739                         if ((rdev->r600_blit.vb_used + 48) > rdev->r600_blit.vb_total) {
 740                                 WARN_ON(1);
 741                         }
 742
 743                         vb[0] = i2f(dst_x / 4);
 744                         vb[1] = 0;
 745                         vb[2] = i2f(src_x / 4);
 746                         vb[3] = 0;
 747
 748                         vb[4] = i2f(dst_x / 4);
 749                         vb[5] = i2f(h);
 750                         vb[6] = i2f(src_x / 4);
 751                         vb[7] = i2f(h);
 752
 753                         vb[8] = i2f((dst_x + cur_size) / 4);
 754                         vb[9] = i2f(h);
 755                         vb[10] = i2f((src_x + cur_size) / 4);
 756                         vb[11] = i2f(h);
 757
 758                         /* src 10 */
 759                         set_tex_resource(rdev, FMT_8_8_8_8,
 760                                          (src_x + cur_size) / 4,
 761                                          h, (src_x + cur_size) / 4,
 762                                          src_gpu_addr);
 763                         /* 5 */
 764                         cp_set_surface_sync(rdev,
 765                                             PACKET3_TC_ACTION_ENA, (src_x + cur_size * h), src_gpu_addr);
 766
 767                         /* dst 17 */
 768                         set_render_target(rdev, COLOR_8_8_8_8,
 769                                           (dst_x + cur_size) / 4, h,
 770                                           dst_gpu_addr);
 771
 772                         /* scissors 12  */
 773                         set_scissors(rdev, (dst_x / 4), 0, (dst_x + cur_size / 4), h);
 774
 775                         /* Vertex buffer setup 15 */
 776                         vb_gpu_addr = rdev->r600_blit.vb_ib->gpu_addr + rdev->r600_blit.vb_used;
 777                         set_vtx_resource(rdev, vb_gpu_addr);
 778
 779                         /* draw 10 */
 780                         draw_auto(rdev);
 781
 782                         /* 5 */
 783                         cp_set_surface_sync(rdev,
 784                                             PACKET3_CB_ACTION_ENA | PACKET3_CB0_DEST_BASE_ENA,
 785                                             cur_size * h, dst_gpu_addr);
 786
 787                         /* 74 ring dwords per loop */
 788                         vb += 12;
 789                         rdev->r600_blit.vb_used += 12 * 4;
 790
 791                         src_gpu_addr += cur_size * h;
 792                         dst_gpu_addr += cur_size * h;
 793                         size_bytes -= cur_size * h;
 794                 }
 795         }
 796 }
 797