Pileus Git - ~andy/linux/blob - drivers/gpu/drm/radeon/cik.c

   1 /*
   2  * Copyright 2012 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24 #include <linux/firmware.h>
  25 #include <linux/slab.h>
  26 #include <linux/module.h>
  27 #include "drmP.h"
  28 #include "radeon.h"
  29 #include "radeon_asic.h"
  30 #include "cikd.h"
  31 #include "atom.h"
  32 #include "cik_blit_shaders.h"
  33 #include "radeon_ucode.h"
  34 #include "clearstate_ci.h"
  35
  36 MODULE_FIRMWARE("radeon/BONAIRE_pfp.bin");
  37 MODULE_FIRMWARE("radeon/BONAIRE_me.bin");
  38 MODULE_FIRMWARE("radeon/BONAIRE_ce.bin");
  39 MODULE_FIRMWARE("radeon/BONAIRE_mec.bin");
  40 MODULE_FIRMWARE("radeon/BONAIRE_mc.bin");
  41 MODULE_FIRMWARE("radeon/BONAIRE_rlc.bin");
  42 MODULE_FIRMWARE("radeon/BONAIRE_sdma.bin");
  43 MODULE_FIRMWARE("radeon/BONAIRE_smc.bin");
  44 MODULE_FIRMWARE("radeon/HAWAII_pfp.bin");
  45 MODULE_FIRMWARE("radeon/HAWAII_me.bin");
  46 MODULE_FIRMWARE("radeon/HAWAII_ce.bin");
  47 MODULE_FIRMWARE("radeon/HAWAII_mec.bin");
  48 MODULE_FIRMWARE("radeon/HAWAII_mc.bin");
  49 MODULE_FIRMWARE("radeon/HAWAII_rlc.bin");
  50 MODULE_FIRMWARE("radeon/HAWAII_sdma.bin");
  51 MODULE_FIRMWARE("radeon/HAWAII_smc.bin");
  52 MODULE_FIRMWARE("radeon/KAVERI_pfp.bin");
  53 MODULE_FIRMWARE("radeon/KAVERI_me.bin");
  54 MODULE_FIRMWARE("radeon/KAVERI_ce.bin");
  55 MODULE_FIRMWARE("radeon/KAVERI_mec.bin");
  56 MODULE_FIRMWARE("radeon/KAVERI_rlc.bin");
  57 MODULE_FIRMWARE("radeon/KAVERI_sdma.bin");
  58 MODULE_FIRMWARE("radeon/KABINI_pfp.bin");
  59 MODULE_FIRMWARE("radeon/KABINI_me.bin");
  60 MODULE_FIRMWARE("radeon/KABINI_ce.bin");
  61 MODULE_FIRMWARE("radeon/KABINI_mec.bin");
  62 MODULE_FIRMWARE("radeon/KABINI_rlc.bin");
  63 MODULE_FIRMWARE("radeon/KABINI_sdma.bin");
  64
  65 extern int r600_ih_ring_alloc(struct radeon_device *rdev);
  66 extern void r600_ih_ring_fini(struct radeon_device *rdev);
  67 extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save);
  68 extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save);
  69 extern bool evergreen_is_display_hung(struct radeon_device *rdev);
  70 extern void sumo_rlc_fini(struct radeon_device *rdev);
  71 extern int sumo_rlc_init(struct radeon_device *rdev);
  72 extern void si_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
  73 extern void si_rlc_reset(struct radeon_device *rdev);
  74 extern void si_init_uvd_internal_cg(struct radeon_device *rdev);
  75 extern int cik_sdma_resume(struct radeon_device *rdev);
  76 extern void cik_sdma_enable(struct radeon_device *rdev, bool enable);
  77 extern void cik_sdma_fini(struct radeon_device *rdev);
  78 static void cik_rlc_stop(struct radeon_device *rdev);
  79 static void cik_pcie_gen3_enable(struct radeon_device *rdev);
  80 static void cik_program_aspm(struct radeon_device *rdev);
  81 static void cik_init_pg(struct radeon_device *rdev);
  82 static void cik_init_cg(struct radeon_device *rdev);
  83 static void cik_fini_pg(struct radeon_device *rdev);
  84 static void cik_fini_cg(struct radeon_device *rdev);
  85 static void cik_enable_gui_idle_interrupt(struct radeon_device *rdev,
  86                                           bool enable);
  87
  88 /* get temperature in millidegrees */
  89 int ci_get_temp(struct radeon_device *rdev)
  90 {
  91         u32 temp;
  92         int actual_temp = 0;
  93
  94         temp = (RREG32_SMC(CG_MULT_THERMAL_STATUS) & CTF_TEMP_MASK) >>
  95                 CTF_TEMP_SHIFT;
  96
  97         if (temp & 0x200)
  98                 actual_temp = 255;
  99         else
 100                 actual_temp = temp & 0x1ff;
 101
 102         actual_temp = actual_temp * 1000;
 103
 104         return actual_temp;
 105 }
 106
 107 /* get temperature in millidegrees */
 108 int kv_get_temp(struct radeon_device *rdev)
 109 {
 110         u32 temp;
 111         int actual_temp = 0;
 112
 113         temp = RREG32_SMC(0xC0300E0C);
 114
 115         if (temp)
 116                 actual_temp = (temp / 8) - 49;
 117         else
 118                 actual_temp = 0;
 119
 120         actual_temp = actual_temp * 1000;
 121
 122         return actual_temp;
 123 }
 124
 125 /*
 126  * Indirect registers accessor
 127  */
 128 u32 cik_pciep_rreg(struct radeon_device *rdev, u32 reg)
 129 {
 130         unsigned long flags;
 131         u32 r;
 132
 133         spin_lock_irqsave(&rdev->pciep_idx_lock, flags);
 134         WREG32(PCIE_INDEX, reg);
 135         (void)RREG32(PCIE_INDEX);
 136         r = RREG32(PCIE_DATA);
 137         spin_unlock_irqrestore(&rdev->pciep_idx_lock, flags);
 138         return r;
 139 }
 140
 141 void cik_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
 142 {
 143         unsigned long flags;
 144
 145         spin_lock_irqsave(&rdev->pciep_idx_lock, flags);
 146         WREG32(PCIE_INDEX, reg);
 147         (void)RREG32(PCIE_INDEX);
 148         WREG32(PCIE_DATA, v);
 149         (void)RREG32(PCIE_DATA);
 150         spin_unlock_irqrestore(&rdev->pciep_idx_lock, flags);
 151 }
 152
 153 static const u32 spectre_rlc_save_restore_register_list[] =
 154 {
 155         (0x0e00 << 16) | (0xc12c >> 2),
 156         0x00000000,
 157         (0x0e00 << 16) | (0xc140 >> 2),
 158         0x00000000,
 159         (0x0e00 << 16) | (0xc150 >> 2),
 160         0x00000000,
 161         (0x0e00 << 16) | (0xc15c >> 2),
 162         0x00000000,
 163         (0x0e00 << 16) | (0xc168 >> 2),
 164         0x00000000,
 165         (0x0e00 << 16) | (0xc170 >> 2),
 166         0x00000000,
 167         (0x0e00 << 16) | (0xc178 >> 2),
 168         0x00000000,
 169         (0x0e00 << 16) | (0xc204 >> 2),
 170         0x00000000,
 171         (0x0e00 << 16) | (0xc2b4 >> 2),
 172         0x00000000,
 173         (0x0e00 << 16) | (0xc2b8 >> 2),
 174         0x00000000,
 175         (0x0e00 << 16) | (0xc2bc >> 2),
 176         0x00000000,
 177         (0x0e00 << 16) | (0xc2c0 >> 2),
 178         0x00000000,
 179         (0x0e00 << 16) | (0x8228 >> 2),
 180         0x00000000,
 181         (0x0e00 << 16) | (0x829c >> 2),
 182         0x00000000,
 183         (0x0e00 << 16) | (0x869c >> 2),
 184         0x00000000,
 185         (0x0600 << 16) | (0x98f4 >> 2),
 186         0x00000000,
 187         (0x0e00 << 16) | (0x98f8 >> 2),
 188         0x00000000,
 189         (0x0e00 << 16) | (0x9900 >> 2),
 190         0x00000000,
 191         (0x0e00 << 16) | (0xc260 >> 2),
 192         0x00000000,
 193         (0x0e00 << 16) | (0x90e8 >> 2),
 194         0x00000000,
 195         (0x0e00 << 16) | (0x3c000 >> 2),
 196         0x00000000,
 197         (0x0e00 << 16) | (0x3c00c >> 2),
 198         0x00000000,
 199         (0x0e00 << 16) | (0x8c1c >> 2),
 200         0x00000000,
 201         (0x0e00 << 16) | (0x9700 >> 2),
 202         0x00000000,
 203         (0x0e00 << 16) | (0xcd20 >> 2),
 204         0x00000000,
 205         (0x4e00 << 16) | (0xcd20 >> 2),
 206         0x00000000,
 207         (0x5e00 << 16) | (0xcd20 >> 2),
 208         0x00000000,
 209         (0x6e00 << 16) | (0xcd20 >> 2),
 210         0x00000000,
 211         (0x7e00 << 16) | (0xcd20 >> 2),
 212         0x00000000,
 213         (0x8e00 << 16) | (0xcd20 >> 2),
 214         0x00000000,
 215         (0x9e00 << 16) | (0xcd20 >> 2),
 216         0x00000000,
 217         (0xae00 << 16) | (0xcd20 >> 2),
 218         0x00000000,
 219         (0xbe00 << 16) | (0xcd20 >> 2),
 220         0x00000000,
 221         (0x0e00 << 16) | (0x89bc >> 2),
 222         0x00000000,
 223         (0x0e00 << 16) | (0x8900 >> 2),
 224         0x00000000,
 225         0x3,
 226         (0x0e00 << 16) | (0xc130 >> 2),
 227         0x00000000,
 228         (0x0e00 << 16) | (0xc134 >> 2),
 229         0x00000000,
 230         (0x0e00 << 16) | (0xc1fc >> 2),
 231         0x00000000,
 232         (0x0e00 << 16) | (0xc208 >> 2),
 233         0x00000000,
 234         (0x0e00 << 16) | (0xc264 >> 2),
 235         0x00000000,
 236         (0x0e00 << 16) | (0xc268 >> 2),
 237         0x00000000,
 238         (0x0e00 << 16) | (0xc26c >> 2),
 239         0x00000000,
 240         (0x0e00 << 16) | (0xc270 >> 2),
 241         0x00000000,
 242         (0x0e00 << 16) | (0xc274 >> 2),
 243         0x00000000,
 244         (0x0e00 << 16) | (0xc278 >> 2),
 245         0x00000000,
 246         (0x0e00 << 16) | (0xc27c >> 2),
 247         0x00000000,
 248         (0x0e00 << 16) | (0xc280 >> 2),
 249         0x00000000,
 250         (0x0e00 << 16) | (0xc284 >> 2),
 251         0x00000000,
 252         (0x0e00 << 16) | (0xc288 >> 2),
 253         0x00000000,
 254         (0x0e00 << 16) | (0xc28c >> 2),
 255         0x00000000,
 256         (0x0e00 << 16) | (0xc290 >> 2),
 257         0x00000000,
 258         (0x0e00 << 16) | (0xc294 >> 2),
 259         0x00000000,
 260         (0x0e00 << 16) | (0xc298 >> 2),
 261         0x00000000,
 262         (0x0e00 << 16) | (0xc29c >> 2),
 263         0x00000000,
 264         (0x0e00 << 16) | (0xc2a0 >> 2),
 265         0x00000000,
 266         (0x0e00 << 16) | (0xc2a4 >> 2),
 267         0x00000000,
 268         (0x0e00 << 16) | (0xc2a8 >> 2),
 269         0x00000000,
 270         (0x0e00 << 16) | (0xc2ac  >> 2),
 271         0x00000000,
 272         (0x0e00 << 16) | (0xc2b0 >> 2),
 273         0x00000000,
 274         (0x0e00 << 16) | (0x301d0 >> 2),
 275         0x00000000,
 276         (0x0e00 << 16) | (0x30238 >> 2),
 277         0x00000000,
 278         (0x0e00 << 16) | (0x30250 >> 2),
 279         0x00000000,
 280         (0x0e00 << 16) | (0x30254 >> 2),
 281         0x00000000,
 282         (0x0e00 << 16) | (0x30258 >> 2),
 283         0x00000000,
 284         (0x0e00 << 16) | (0x3025c >> 2),
 285         0x00000000,
 286         (0x4e00 << 16) | (0xc900 >> 2),
 287         0x00000000,
 288         (0x5e00 << 16) | (0xc900 >> 2),
 289         0x00000000,
 290         (0x6e00 << 16) | (0xc900 >> 2),
 291         0x00000000,
 292         (0x7e00 << 16) | (0xc900 >> 2),
 293         0x00000000,
 294         (0x8e00 << 16) | (0xc900 >> 2),
 295         0x00000000,
 296         (0x9e00 << 16) | (0xc900 >> 2),
 297         0x00000000,
 298         (0xae00 << 16) | (0xc900 >> 2),
 299         0x00000000,
 300         (0xbe00 << 16) | (0xc900 >> 2),
 301         0x00000000,
 302         (0x4e00 << 16) | (0xc904 >> 2),
 303         0x00000000,
 304         (0x5e00 << 16) | (0xc904 >> 2),
 305         0x00000000,
 306         (0x6e00 << 16) | (0xc904 >> 2),
 307         0x00000000,
 308         (0x7e00 << 16) | (0xc904 >> 2),
 309         0x00000000,
 310         (0x8e00 << 16) | (0xc904 >> 2),
 311         0x00000000,
 312         (0x9e00 << 16) | (0xc904 >> 2),
 313         0x00000000,
 314         (0xae00 << 16) | (0xc904 >> 2),
 315         0x00000000,
 316         (0xbe00 << 16) | (0xc904 >> 2),
 317         0x00000000,
 318         (0x4e00 << 16) | (0xc908 >> 2),
 319         0x00000000,
 320         (0x5e00 << 16) | (0xc908 >> 2),
 321         0x00000000,
 322         (0x6e00 << 16) | (0xc908 >> 2),
 323         0x00000000,
 324         (0x7e00 << 16) | (0xc908 >> 2),
 325         0x00000000,
 326         (0x8e00 << 16) | (0xc908 >> 2),
 327         0x00000000,
 328         (0x9e00 << 16) | (0xc908 >> 2),
 329         0x00000000,
 330         (0xae00 << 16) | (0xc908 >> 2),
 331         0x00000000,
 332         (0xbe00 << 16) | (0xc908 >> 2),
 333         0x00000000,
 334         (0x4e00 << 16) | (0xc90c >> 2),
 335         0x00000000,
 336         (0x5e00 << 16) | (0xc90c >> 2),
 337         0x00000000,
 338         (0x6e00 << 16) | (0xc90c >> 2),
 339         0x00000000,
 340         (0x7e00 << 16) | (0xc90c >> 2),
 341         0x00000000,
 342         (0x8e00 << 16) | (0xc90c >> 2),
 343         0x00000000,
 344         (0x9e00 << 16) | (0xc90c >> 2),
 345         0x00000000,
 346         (0xae00 << 16) | (0xc90c >> 2),
 347         0x00000000,
 348         (0xbe00 << 16) | (0xc90c >> 2),
 349         0x00000000,
 350         (0x4e00 << 16) | (0xc910 >> 2),
 351         0x00000000,
 352         (0x5e00 << 16) | (0xc910 >> 2),
 353         0x00000000,
 354         (0x6e00 << 16) | (0xc910 >> 2),
 355         0x00000000,
 356         (0x7e00 << 16) | (0xc910 >> 2),
 357         0x00000000,
 358         (0x8e00 << 16) | (0xc910 >> 2),
 359         0x00000000,
 360         (0x9e00 << 16) | (0xc910 >> 2),
 361         0x00000000,
 362         (0xae00 << 16) | (0xc910 >> 2),
 363         0x00000000,
 364         (0xbe00 << 16) | (0xc910 >> 2),
 365         0x00000000,
 366         (0x0e00 << 16) | (0xc99c >> 2),
 367         0x00000000,
 368         (0x0e00 << 16) | (0x9834 >> 2),
 369         0x00000000,
 370         (0x0000 << 16) | (0x30f00 >> 2),
 371         0x00000000,
 372         (0x0001 << 16) | (0x30f00 >> 2),
 373         0x00000000,
 374         (0x0000 << 16) | (0x30f04 >> 2),
 375         0x00000000,
 376         (0x0001 << 16) | (0x30f04 >> 2),
 377         0x00000000,
 378         (0x0000 << 16) | (0x30f08 >> 2),
 379         0x00000000,
 380         (0x0001 << 16) | (0x30f08 >> 2),
 381         0x00000000,
 382         (0x0000 << 16) | (0x30f0c >> 2),
 383         0x00000000,
 384         (0x0001 << 16) | (0x30f0c >> 2),
 385         0x00000000,
 386         (0x0600 << 16) | (0x9b7c >> 2),
 387         0x00000000,
 388         (0x0e00 << 16) | (0x8a14 >> 2),
 389         0x00000000,
 390         (0x0e00 << 16) | (0x8a18 >> 2),
 391         0x00000000,
 392         (0x0600 << 16) | (0x30a00 >> 2),
 393         0x00000000,
 394         (0x0e00 << 16) | (0x8bf0 >> 2),
 395         0x00000000,
 396         (0x0e00 << 16) | (0x8bcc >> 2),
 397         0x00000000,
 398         (0x0e00 << 16) | (0x8b24 >> 2),
 399         0x00000000,
 400         (0x0e00 << 16) | (0x30a04 >> 2),
 401         0x00000000,
 402         (0x0600 << 16) | (0x30a10 >> 2),
 403         0x00000000,
 404         (0x0600 << 16) | (0x30a14 >> 2),
 405         0x00000000,
 406         (0x0600 << 16) | (0x30a18 >> 2),
 407         0x00000000,
 408         (0x0600 << 16) | (0x30a2c >> 2),
 409         0x00000000,
 410         (0x0e00 << 16) | (0xc700 >> 2),
 411         0x00000000,
 412         (0x0e00 << 16) | (0xc704 >> 2),
 413         0x00000000,
 414         (0x0e00 << 16) | (0xc708 >> 2),
 415         0x00000000,
 416         (0x0e00 << 16) | (0xc768 >> 2),
 417         0x00000000,
 418         (0x0400 << 16) | (0xc770 >> 2),
 419         0x00000000,
 420         (0x0400 << 16) | (0xc774 >> 2),
 421         0x00000000,
 422         (0x0400 << 16) | (0xc778 >> 2),
 423         0x00000000,
 424         (0x0400 << 16) | (0xc77c >> 2),
 425         0x00000000,
 426         (0x0400 << 16) | (0xc780 >> 2),
 427         0x00000000,
 428         (0x0400 << 16) | (0xc784 >> 2),
 429         0x00000000,
 430         (0x0400 << 16) | (0xc788 >> 2),
 431         0x00000000,
 432         (0x0400 << 16) | (0xc78c >> 2),
 433         0x00000000,
 434         (0x0400 << 16) | (0xc798 >> 2),
 435         0x00000000,
 436         (0x0400 << 16) | (0xc79c >> 2),
 437         0x00000000,
 438         (0x0400 << 16) | (0xc7a0 >> 2),
 439         0x00000000,
 440         (0x0400 << 16) | (0xc7a4 >> 2),
 441         0x00000000,
 442         (0x0400 << 16) | (0xc7a8 >> 2),
 443         0x00000000,
 444         (0x0400 << 16) | (0xc7ac >> 2),
 445         0x00000000,
 446         (0x0400 << 16) | (0xc7b0 >> 2),
 447         0x00000000,
 448         (0x0400 << 16) | (0xc7b4 >> 2),
 449         0x00000000,
 450         (0x0e00 << 16) | (0x9100 >> 2),
 451         0x00000000,
 452         (0x0e00 << 16) | (0x3c010 >> 2),
 453         0x00000000,
 454         (0x0e00 << 16) | (0x92a8 >> 2),
 455         0x00000000,
 456         (0x0e00 << 16) | (0x92ac >> 2),
 457         0x00000000,
 458         (0x0e00 << 16) | (0x92b4 >> 2),
 459         0x00000000,
 460         (0x0e00 << 16) | (0x92b8 >> 2),
 461         0x00000000,
 462         (0x0e00 << 16) | (0x92bc >> 2),
 463         0x00000000,
 464         (0x0e00 << 16) | (0x92c0 >> 2),
 465         0x00000000,
 466         (0x0e00 << 16) | (0x92c4 >> 2),
 467         0x00000000,
 468         (0x0e00 << 16) | (0x92c8 >> 2),
 469         0x00000000,
 470         (0x0e00 << 16) | (0x92cc >> 2),
 471         0x00000000,
 472         (0x0e00 << 16) | (0x92d0 >> 2),
 473         0x00000000,
 474         (0x0e00 << 16) | (0x8c00 >> 2),
 475         0x00000000,
 476         (0x0e00 << 16) | (0x8c04 >> 2),
 477         0x00000000,
 478         (0x0e00 << 16) | (0x8c20 >> 2),
 479         0x00000000,
 480         (0x0e00 << 16) | (0x8c38 >> 2),
 481         0x00000000,
 482         (0x0e00 << 16) | (0x8c3c >> 2),
 483         0x00000000,
 484         (0x0e00 << 16) | (0xae00 >> 2),
 485         0x00000000,
 486         (0x0e00 << 16) | (0x9604 >> 2),
 487         0x00000000,
 488         (0x0e00 << 16) | (0xac08 >> 2),
 489         0x00000000,
 490         (0x0e00 << 16) | (0xac0c >> 2),
 491         0x00000000,
 492         (0x0e00 << 16) | (0xac10 >> 2),
 493         0x00000000,
 494         (0x0e00 << 16) | (0xac14 >> 2),
 495         0x00000000,
 496         (0x0e00 << 16) | (0xac58 >> 2),
 497         0x00000000,
 498         (0x0e00 << 16) | (0xac68 >> 2),
 499         0x00000000,
 500         (0x0e00 << 16) | (0xac6c >> 2),
 501         0x00000000,
 502         (0x0e00 << 16) | (0xac70 >> 2),
 503         0x00000000,
 504         (0x0e00 << 16) | (0xac74 >> 2),
 505         0x00000000,
 506         (0x0e00 << 16) | (0xac78 >> 2),
 507         0x00000000,
 508         (0x0e00 << 16) | (0xac7c >> 2),
 509         0x00000000,
 510         (0x0e00 << 16) | (0xac80 >> 2),
 511         0x00000000,
 512         (0x0e00 << 16) | (0xac84 >> 2),
 513         0x00000000,
 514         (0x0e00 << 16) | (0xac88 >> 2),
 515         0x00000000,
 516         (0x0e00 << 16) | (0xac8c >> 2),
 517         0x00000000,
 518         (0x0e00 << 16) | (0x970c >> 2),
 519         0x00000000,
 520         (0x0e00 << 16) | (0x9714 >> 2),
 521         0x00000000,
 522         (0x0e00 << 16) | (0x9718 >> 2),
 523         0x00000000,
 524         (0x0e00 << 16) | (0x971c >> 2),
 525         0x00000000,
 526         (0x0e00 << 16) | (0x31068 >> 2),
 527         0x00000000,
 528         (0x4e00 << 16) | (0x31068 >> 2),
 529         0x00000000,
 530         (0x5e00 << 16) | (0x31068 >> 2),
 531         0x00000000,
 532         (0x6e00 << 16) | (0x31068 >> 2),
 533         0x00000000,
 534         (0x7e00 << 16) | (0x31068 >> 2),
 535         0x00000000,
 536         (0x8e00 << 16) | (0x31068 >> 2),
 537         0x00000000,
 538         (0x9e00 << 16) | (0x31068 >> 2),
 539         0x00000000,
 540         (0xae00 << 16) | (0x31068 >> 2),
 541         0x00000000,
 542         (0xbe00 << 16) | (0x31068 >> 2),
 543         0x00000000,
 544         (0x0e00 << 16) | (0xcd10 >> 2),
 545         0x00000000,
 546         (0x0e00 << 16) | (0xcd14 >> 2),
 547         0x00000000,
 548         (0x0e00 << 16) | (0x88b0 >> 2),
 549         0x00000000,
 550         (0x0e00 << 16) | (0x88b4 >> 2),
 551         0x00000000,
 552         (0x0e00 << 16) | (0x88b8 >> 2),
 553         0x00000000,
 554         (0x0e00 << 16) | (0x88bc >> 2),
 555         0x00000000,
 556         (0x0400 << 16) | (0x89c0 >> 2),
 557         0x00000000,
 558         (0x0e00 << 16) | (0x88c4 >> 2),
 559         0x00000000,
 560         (0x0e00 << 16) | (0x88c8 >> 2),
 561         0x00000000,
 562         (0x0e00 << 16) | (0x88d0 >> 2),
 563         0x00000000,
 564         (0x0e00 << 16) | (0x88d4 >> 2),
 565         0x00000000,
 566         (0x0e00 << 16) | (0x88d8 >> 2),
 567         0x00000000,
 568         (0x0e00 << 16) | (0x8980 >> 2),
 569         0x00000000,
 570         (0x0e00 << 16) | (0x30938 >> 2),
 571         0x00000000,
 572         (0x0e00 << 16) | (0x3093c >> 2),
 573         0x00000000,
 574         (0x0e00 << 16) | (0x30940 >> 2),
 575         0x00000000,
 576         (0x0e00 << 16) | (0x89a0 >> 2),
 577         0x00000000,
 578         (0x0e00 << 16) | (0x30900 >> 2),
 579         0x00000000,
 580         (0x0e00 << 16) | (0x30904 >> 2),
 581         0x00000000,
 582         (0x0e00 << 16) | (0x89b4 >> 2),
 583         0x00000000,
 584         (0x0e00 << 16) | (0x3c210 >> 2),
 585         0x00000000,
 586         (0x0e00 << 16) | (0x3c214 >> 2),
 587         0x00000000,
 588         (0x0e00 << 16) | (0x3c218 >> 2),
 589         0x00000000,
 590         (0x0e00 << 16) | (0x8904 >> 2),
 591         0x00000000,
 592         0x5,
 593         (0x0e00 << 16) | (0x8c28 >> 2),
 594         (0x0e00 << 16) | (0x8c2c >> 2),
 595         (0x0e00 << 16) | (0x8c30 >> 2),
 596         (0x0e00 << 16) | (0x8c34 >> 2),
 597         (0x0e00 << 16) | (0x9600 >> 2),
 598 };
 599
 600 static const u32 kalindi_rlc_save_restore_register_list[] =
 601 {
 602         (0x0e00 << 16) | (0xc12c >> 2),
 603         0x00000000,
 604         (0x0e00 << 16) | (0xc140 >> 2),
 605         0x00000000,
 606         (0x0e00 << 16) | (0xc150 >> 2),
 607         0x00000000,
 608         (0x0e00 << 16) | (0xc15c >> 2),
 609         0x00000000,
 610         (0x0e00 << 16) | (0xc168 >> 2),
 611         0x00000000,
 612         (0x0e00 << 16) | (0xc170 >> 2),
 613         0x00000000,
 614         (0x0e00 << 16) | (0xc204 >> 2),
 615         0x00000000,
 616         (0x0e00 << 16) | (0xc2b4 >> 2),
 617         0x00000000,
 618         (0x0e00 << 16) | (0xc2b8 >> 2),
 619         0x00000000,
 620         (0x0e00 << 16) | (0xc2bc >> 2),
 621         0x00000000,
 622         (0x0e00 << 16) | (0xc2c0 >> 2),
 623         0x00000000,
 624         (0x0e00 << 16) | (0x8228 >> 2),
 625         0x00000000,
 626         (0x0e00 << 16) | (0x829c >> 2),
 627         0x00000000,
 628         (0x0e00 << 16) | (0x869c >> 2),
 629         0x00000000,
 630         (0x0600 << 16) | (0x98f4 >> 2),
 631         0x00000000,
 632         (0x0e00 << 16) | (0x98f8 >> 2),
 633         0x00000000,
 634         (0x0e00 << 16) | (0x9900 >> 2),
 635         0x00000000,
 636         (0x0e00 << 16) | (0xc260 >> 2),
 637         0x00000000,
 638         (0x0e00 << 16) | (0x90e8 >> 2),
 639         0x00000000,
 640         (0x0e00 << 16) | (0x3c000 >> 2),
 641         0x00000000,
 642         (0x0e00 << 16) | (0x3c00c >> 2),
 643         0x00000000,
 644         (0x0e00 << 16) | (0x8c1c >> 2),
 645         0x00000000,
 646         (0x0e00 << 16) | (0x9700 >> 2),
 647         0x00000000,
 648         (0x0e00 << 16) | (0xcd20 >> 2),
 649         0x00000000,
 650         (0x4e00 << 16) | (0xcd20 >> 2),
 651         0x00000000,
 652         (0x5e00 << 16) | (0xcd20 >> 2),
 653         0x00000000,
 654         (0x6e00 << 16) | (0xcd20 >> 2),
 655         0x00000000,
 656         (0x7e00 << 16) | (0xcd20 >> 2),
 657         0x00000000,
 658         (0x0e00 << 16) | (0x89bc >> 2),
 659         0x00000000,
 660         (0x0e00 << 16) | (0x8900 >> 2),
 661         0x00000000,
 662         0x3,
 663         (0x0e00 << 16) | (0xc130 >> 2),
 664         0x00000000,
 665         (0x0e00 << 16) | (0xc134 >> 2),
 666         0x00000000,
 667         (0x0e00 << 16) | (0xc1fc >> 2),
 668         0x00000000,
 669         (0x0e00 << 16) | (0xc208 >> 2),
 670         0x00000000,
 671         (0x0e00 << 16) | (0xc264 >> 2),
 672         0x00000000,
 673         (0x0e00 << 16) | (0xc268 >> 2),
 674         0x00000000,
 675         (0x0e00 << 16) | (0xc26c >> 2),
 676         0x00000000,
 677         (0x0e00 << 16) | (0xc270 >> 2),
 678         0x00000000,
 679         (0x0e00 << 16) | (0xc274 >> 2),
 680         0x00000000,
 681         (0x0e00 << 16) | (0xc28c >> 2),
 682         0x00000000,
 683         (0x0e00 << 16) | (0xc290 >> 2),
 684         0x00000000,
 685         (0x0e00 << 16) | (0xc294 >> 2),
 686         0x00000000,
 687         (0x0e00 << 16) | (0xc298 >> 2),
 688         0x00000000,
 689         (0x0e00 << 16) | (0xc2a0 >> 2),
 690         0x00000000,
 691         (0x0e00 << 16) | (0xc2a4 >> 2),
 692         0x00000000,
 693         (0x0e00 << 16) | (0xc2a8 >> 2),
 694         0x00000000,
 695         (0x0e00 << 16) | (0xc2ac >> 2),
 696         0x00000000,
 697         (0x0e00 << 16) | (0x301d0 >> 2),
 698         0x00000000,
 699         (0x0e00 << 16) | (0x30238 >> 2),
 700         0x00000000,
 701         (0x0e00 << 16) | (0x30250 >> 2),
 702         0x00000000,
 703         (0x0e00 << 16) | (0x30254 >> 2),
 704         0x00000000,
 705         (0x0e00 << 16) | (0x30258 >> 2),
 706         0x00000000,
 707         (0x0e00 << 16) | (0x3025c >> 2),
 708         0x00000000,
 709         (0x4e00 << 16) | (0xc900 >> 2),
 710         0x00000000,
 711         (0x5e00 << 16) | (0xc900 >> 2),
 712         0x00000000,
 713         (0x6e00 << 16) | (0xc900 >> 2),
 714         0x00000000,
 715         (0x7e00 << 16) | (0xc900 >> 2),
 716         0x00000000,
 717         (0x4e00 << 16) | (0xc904 >> 2),
 718         0x00000000,
 719         (0x5e00 << 16) | (0xc904 >> 2),
 720         0x00000000,
 721         (0x6e00 << 16) | (0xc904 >> 2),
 722         0x00000000,
 723         (0x7e00 << 16) | (0xc904 >> 2),
 724         0x00000000,
 725         (0x4e00 << 16) | (0xc908 >> 2),
 726         0x00000000,
 727         (0x5e00 << 16) | (0xc908 >> 2),
 728         0x00000000,
 729         (0x6e00 << 16) | (0xc908 >> 2),
 730         0x00000000,
 731         (0x7e00 << 16) | (0xc908 >> 2),
 732         0x00000000,
 733         (0x4e00 << 16) | (0xc90c >> 2),
 734         0x00000000,
 735         (0x5e00 << 16) | (0xc90c >> 2),
 736         0x00000000,
 737         (0x6e00 << 16) | (0xc90c >> 2),
 738         0x00000000,
 739         (0x7e00 << 16) | (0xc90c >> 2),
 740         0x00000000,
 741         (0x4e00 << 16) | (0xc910 >> 2),
 742         0x00000000,
 743         (0x5e00 << 16) | (0xc910 >> 2),
 744         0x00000000,
 745         (0x6e00 << 16) | (0xc910 >> 2),
 746         0x00000000,
 747         (0x7e00 << 16) | (0xc910 >> 2),
 748         0x00000000,
 749         (0x0e00 << 16) | (0xc99c >> 2),
 750         0x00000000,
 751         (0x0e00 << 16) | (0x9834 >> 2),
 752         0x00000000,
 753         (0x0000 << 16) | (0x30f00 >> 2),
 754         0x00000000,
 755         (0x0000 << 16) | (0x30f04 >> 2),
 756         0x00000000,
 757         (0x0000 << 16) | (0x30f08 >> 2),
 758         0x00000000,
 759         (0x0000 << 16) | (0x30f0c >> 2),
 760         0x00000000,
 761         (0x0600 << 16) | (0x9b7c >> 2),
 762         0x00000000,
 763         (0x0e00 << 16) | (0x8a14 >> 2),
 764         0x00000000,
 765         (0x0e00 << 16) | (0x8a18 >> 2),
 766         0x00000000,
 767         (0x0600 << 16) | (0x30a00 >> 2),
 768         0x00000000,
 769         (0x0e00 << 16) | (0x8bf0 >> 2),
 770         0x00000000,
 771         (0x0e00 << 16) | (0x8bcc >> 2),
 772         0x00000000,
 773         (0x0e00 << 16) | (0x8b24 >> 2),
 774         0x00000000,
 775         (0x0e00 << 16) | (0x30a04 >> 2),
 776         0x00000000,
 777         (0x0600 << 16) | (0x30a10 >> 2),
 778         0x00000000,
 779         (0x0600 << 16) | (0x30a14 >> 2),
 780         0x00000000,
 781         (0x0600 << 16) | (0x30a18 >> 2),
 782         0x00000000,
 783         (0x0600 << 16) | (0x30a2c >> 2),
 784         0x00000000,
 785         (0x0e00 << 16) | (0xc700 >> 2),
 786         0x00000000,
 787         (0x0e00 << 16) | (0xc704 >> 2),
 788         0x00000000,
 789         (0x0e00 << 16) | (0xc708 >> 2),
 790         0x00000000,
 791         (0x0e00 << 16) | (0xc768 >> 2),
 792         0x00000000,
 793         (0x0400 << 16) | (0xc770 >> 2),
 794         0x00000000,
 795         (0x0400 << 16) | (0xc774 >> 2),
 796         0x00000000,
 797         (0x0400 << 16) | (0xc798 >> 2),
 798         0x00000000,
 799         (0x0400 << 16) | (0xc79c >> 2),
 800         0x00000000,
 801         (0x0e00 << 16) | (0x9100 >> 2),
 802         0x00000000,
 803         (0x0e00 << 16) | (0x3c010 >> 2),
 804         0x00000000,
 805         (0x0e00 << 16) | (0x8c00 >> 2),
 806         0x00000000,
 807         (0x0e00 << 16) | (0x8c04 >> 2),
 808         0x00000000,
 809         (0x0e00 << 16) | (0x8c20 >> 2),
 810         0x00000000,
 811         (0x0e00 << 16) | (0x8c38 >> 2),
 812         0x00000000,
 813         (0x0e00 << 16) | (0x8c3c >> 2),
 814         0x00000000,
 815         (0x0e00 << 16) | (0xae00 >> 2),
 816         0x00000000,
 817         (0x0e00 << 16) | (0x9604 >> 2),
 818         0x00000000,
 819         (0x0e00 << 16) | (0xac08 >> 2),
 820         0x00000000,
 821         (0x0e00 << 16) | (0xac0c >> 2),
 822         0x00000000,
 823         (0x0e00 << 16) | (0xac10 >> 2),
 824         0x00000000,
 825         (0x0e00 << 16) | (0xac14 >> 2),
 826         0x00000000,
 827         (0x0e00 << 16) | (0xac58 >> 2),
 828         0x00000000,
 829         (0x0e00 << 16) | (0xac68 >> 2),
 830         0x00000000,
 831         (0x0e00 << 16) | (0xac6c >> 2),
 832         0x00000000,
 833         (0x0e00 << 16) | (0xac70 >> 2),
 834         0x00000000,
 835         (0x0e00 << 16) | (0xac74 >> 2),
 836         0x00000000,
 837         (0x0e00 << 16) | (0xac78 >> 2),
 838         0x00000000,
 839         (0x0e00 << 16) | (0xac7c >> 2),
 840         0x00000000,
 841         (0x0e00 << 16) | (0xac80 >> 2),
 842         0x00000000,
 843         (0x0e00 << 16) | (0xac84 >> 2),
 844         0x00000000,
 845         (0x0e00 << 16) | (0xac88 >> 2),
 846         0x00000000,
 847         (0x0e00 << 16) | (0xac8c >> 2),
 848         0x00000000,
 849         (0x0e00 << 16) | (0x970c >> 2),
 850         0x00000000,
 851         (0x0e00 << 16) | (0x9714 >> 2),
 852         0x00000000,
 853         (0x0e00 << 16) | (0x9718 >> 2),
 854         0x00000000,
 855         (0x0e00 << 16) | (0x971c >> 2),
 856         0x00000000,
 857         (0x0e00 << 16) | (0x31068 >> 2),
 858         0x00000000,
 859         (0x4e00 << 16) | (0x31068 >> 2),
 860         0x00000000,
 861         (0x5e00 << 16) | (0x31068 >> 2),
 862         0x00000000,
 863         (0x6e00 << 16) | (0x31068 >> 2),
 864         0x00000000,
 865         (0x7e00 << 16) | (0x31068 >> 2),
 866         0x00000000,
 867         (0x0e00 << 16) | (0xcd10 >> 2),
 868         0x00000000,
 869         (0x0e00 << 16) | (0xcd14 >> 2),
 870         0x00000000,
 871         (0x0e00 << 16) | (0x88b0 >> 2),
 872         0x00000000,
 873         (0x0e00 << 16) | (0x88b4 >> 2),
 874         0x00000000,
 875         (0x0e00 << 16) | (0x88b8 >> 2),
 876         0x00000000,
 877         (0x0e00 << 16) | (0x88bc >> 2),
 878         0x00000000,
 879         (0x0400 << 16) | (0x89c0 >> 2),
 880         0x00000000,
 881         (0x0e00 << 16) | (0x88c4 >> 2),
 882         0x00000000,
 883         (0x0e00 << 16) | (0x88c8 >> 2),
 884         0x00000000,
 885         (0x0e00 << 16) | (0x88d0 >> 2),
 886         0x00000000,
 887         (0x0e00 << 16) | (0x88d4 >> 2),
 888         0x00000000,
 889         (0x0e00 << 16) | (0x88d8 >> 2),
 890         0x00000000,
 891         (0x0e00 << 16) | (0x8980 >> 2),
 892         0x00000000,
 893         (0x0e00 << 16) | (0x30938 >> 2),
 894         0x00000000,
 895         (0x0e00 << 16) | (0x3093c >> 2),
 896         0x00000000,
 897         (0x0e00 << 16) | (0x30940 >> 2),
 898         0x00000000,
 899         (0x0e00 << 16) | (0x89a0 >> 2),
 900         0x00000000,
 901         (0x0e00 << 16) | (0x30900 >> 2),
 902         0x00000000,
 903         (0x0e00 << 16) | (0x30904 >> 2),
 904         0x00000000,
 905         (0x0e00 << 16) | (0x89b4 >> 2),
 906         0x00000000,
 907         (0x0e00 << 16) | (0x3e1fc >> 2),
 908         0x00000000,
 909         (0x0e00 << 16) | (0x3c210 >> 2),
 910         0x00000000,
 911         (0x0e00 << 16) | (0x3c214 >> 2),
 912         0x00000000,
 913         (0x0e00 << 16) | (0x3c218 >> 2),
 914         0x00000000,
 915         (0x0e00 << 16) | (0x8904 >> 2),
 916         0x00000000,
 917         0x5,
 918         (0x0e00 << 16) | (0x8c28 >> 2),
 919         (0x0e00 << 16) | (0x8c2c >> 2),
 920         (0x0e00 << 16) | (0x8c30 >> 2),
 921         (0x0e00 << 16) | (0x8c34 >> 2),
 922         (0x0e00 << 16) | (0x9600 >> 2),
 923 };
 924
 925 static const u32 bonaire_golden_spm_registers[] =
 926 {
 927         0x30800, 0xe0ffffff, 0xe0000000
 928 };
 929
 930 static const u32 bonaire_golden_common_registers[] =
 931 {
 932         0xc770, 0xffffffff, 0x00000800,
 933         0xc774, 0xffffffff, 0x00000800,
 934         0xc798, 0xffffffff, 0x00007fbf,
 935         0xc79c, 0xffffffff, 0x00007faf
 936 };
 937
 938 static const u32 bonaire_golden_registers[] =
 939 {
 940         0x3354, 0x00000333, 0x00000333,
 941         0x3350, 0x000c0fc0, 0x00040200,
 942         0x9a10, 0x00010000, 0x00058208,
 943         0x3c000, 0xffff1fff, 0x00140000,
 944         0x3c200, 0xfdfc0fff, 0x00000100,
 945         0x3c234, 0x40000000, 0x40000200,
 946         0x9830, 0xffffffff, 0x00000000,
 947         0x9834, 0xf00fffff, 0x00000400,
 948         0x9838, 0x0002021c, 0x00020200,
 949         0xc78, 0x00000080, 0x00000000,
 950         0x5bb0, 0x000000f0, 0x00000070,
 951         0x5bc0, 0xf0311fff, 0x80300000,
 952         0x98f8, 0x73773777, 0x12010001,
 953         0x350c, 0x00810000, 0x408af000,
 954         0x7030, 0x31000111, 0x00000011,
 955         0x2f48, 0x73773777, 0x12010001,
 956         0x220c, 0x00007fb6, 0x0021a1b1,
 957         0x2210, 0x00007fb6, 0x002021b1,
 958         0x2180, 0x00007fb6, 0x00002191,
 959         0x2218, 0x00007fb6, 0x002121b1,
 960         0x221c, 0x00007fb6, 0x002021b1,
 961         0x21dc, 0x00007fb6, 0x00002191,
 962         0x21e0, 0x00007fb6, 0x00002191,
 963         0x3628, 0x0000003f, 0x0000000a,
 964         0x362c, 0x0000003f, 0x0000000a,
 965         0x2ae4, 0x00073ffe, 0x000022a2,
 966         0x240c, 0x000007ff, 0x00000000,
 967         0x8a14, 0xf000003f, 0x00000007,
 968         0x8bf0, 0x00002001, 0x00000001,
 969         0x8b24, 0xffffffff, 0x00ffffff,
 970         0x30a04, 0x0000ff0f, 0x00000000,
 971         0x28a4c, 0x07ffffff, 0x06000000,
 972         0x4d8, 0x00000fff, 0x00000100,
 973         0x3e78, 0x00000001, 0x00000002,
 974         0x9100, 0x03000000, 0x0362c688,
 975         0x8c00, 0x000000ff, 0x00000001,
 976         0xe40, 0x00001fff, 0x00001fff,
 977         0x9060, 0x0000007f, 0x00000020,
 978         0x9508, 0x00010000, 0x00010000,
 979         0xac14, 0x000003ff, 0x000000f3,
 980         0xac0c, 0xffffffff, 0x00001032
 981 };
 982
 983 static const u32 bonaire_mgcg_cgcg_init[] =
 984 {
 985         0xc420, 0xffffffff, 0xfffffffc,
 986         0x30800, 0xffffffff, 0xe0000000,
 987         0x3c2a0, 0xffffffff, 0x00000100,
 988         0x3c208, 0xffffffff, 0x00000100,
 989         0x3c2c0, 0xffffffff, 0xc0000100,
 990         0x3c2c8, 0xffffffff, 0xc0000100,
 991         0x3c2c4, 0xffffffff, 0xc0000100,
 992         0x55e4, 0xffffffff, 0x00600100,
 993         0x3c280, 0xffffffff, 0x00000100,
 994         0x3c214, 0xffffffff, 0x06000100,
 995         0x3c220, 0xffffffff, 0x00000100,
 996         0x3c218, 0xffffffff, 0x06000100,
 997         0x3c204, 0xffffffff, 0x00000100,
 998         0x3c2e0, 0xffffffff, 0x00000100,
 999         0x3c224, 0xffffffff, 0x00000100,
1000         0x3c200, 0xffffffff, 0x00000100,
1001         0x3c230, 0xffffffff, 0x00000100,
1002         0x3c234, 0xffffffff, 0x00000100,
1003         0x3c250, 0xffffffff, 0x00000100,
1004         0x3c254, 0xffffffff, 0x00000100,
1005         0x3c258, 0xffffffff, 0x00000100,
1006         0x3c25c, 0xffffffff, 0x00000100,
1007         0x3c260, 0xffffffff, 0x00000100,
1008         0x3c27c, 0xffffffff, 0x00000100,
1009         0x3c278, 0xffffffff, 0x00000100,
1010         0x3c210, 0xffffffff, 0x06000100,
1011         0x3c290, 0xffffffff, 0x00000100,
1012         0x3c274, 0xffffffff, 0x00000100,
1013         0x3c2b4, 0xffffffff, 0x00000100,
1014         0x3c2b0, 0xffffffff, 0x00000100,
1015         0x3c270, 0xffffffff, 0x00000100,
1016         0x30800, 0xffffffff, 0xe0000000,
1017         0x3c020, 0xffffffff, 0x00010000,
1018         0x3c024, 0xffffffff, 0x00030002,
1019         0x3c028, 0xffffffff, 0x00040007,
1020         0x3c02c, 0xffffffff, 0x00060005,
1021         0x3c030, 0xffffffff, 0x00090008,
1022         0x3c034, 0xffffffff, 0x00010000,
1023         0x3c038, 0xffffffff, 0x00030002,
1024         0x3c03c, 0xffffffff, 0x00040007,
1025         0x3c040, 0xffffffff, 0x00060005,
1026         0x3c044, 0xffffffff, 0x00090008,
1027         0x3c048, 0xffffffff, 0x00010000,
1028         0x3c04c, 0xffffffff, 0x00030002,
1029         0x3c050, 0xffffffff, 0x00040007,
1030         0x3c054, 0xffffffff, 0x00060005,
1031         0x3c058, 0xffffffff, 0x00090008,
1032         0x3c05c, 0xffffffff, 0x00010000,
1033         0x3c060, 0xffffffff, 0x00030002,
1034         0x3c064, 0xffffffff, 0x00040007,
1035         0x3c068, 0xffffffff, 0x00060005,
1036         0x3c06c, 0xffffffff, 0x00090008,
1037         0x3c070, 0xffffffff, 0x00010000,
1038         0x3c074, 0xffffffff, 0x00030002,
1039         0x3c078, 0xffffffff, 0x00040007,
1040         0x3c07c, 0xffffffff, 0x00060005,
1041         0x3c080, 0xffffffff, 0x00090008,
1042         0x3c084, 0xffffffff, 0x00010000,
1043         0x3c088, 0xffffffff, 0x00030002,
1044         0x3c08c, 0xffffffff, 0x00040007,
1045         0x3c090, 0xffffffff, 0x00060005,
1046         0x3c094, 0xffffffff, 0x00090008,
1047         0x3c098, 0xffffffff, 0x00010000,
1048         0x3c09c, 0xffffffff, 0x00030002,
1049         0x3c0a0, 0xffffffff, 0x00040007,
1050         0x3c0a4, 0xffffffff, 0x00060005,
1051         0x3c0a8, 0xffffffff, 0x00090008,
1052         0x3c000, 0xffffffff, 0x96e00200,
1053         0x8708, 0xffffffff, 0x00900100,
1054         0xc424, 0xffffffff, 0x0020003f,
1055         0x38, 0xffffffff, 0x0140001c,
1056         0x3c, 0x000f0000, 0x000f0000,
1057         0x220, 0xffffffff, 0xC060000C,
1058         0x224, 0xc0000fff, 0x00000100,
1059         0xf90, 0xffffffff, 0x00000100,
1060         0xf98, 0x00000101, 0x00000000,
1061         0x20a8, 0xffffffff, 0x00000104,
1062         0x55e4, 0xff000fff, 0x00000100,
1063         0x30cc, 0xc0000fff, 0x00000104,
1064         0xc1e4, 0x00000001, 0x00000001,
1065         0xd00c, 0xff000ff0, 0x00000100,
1066         0xd80c, 0xff000ff0, 0x00000100
1067 };
1068
1069 static const u32 spectre_golden_spm_registers[] =
1070 {
1071         0x30800, 0xe0ffffff, 0xe0000000
1072 };
1073
1074 static const u32 spectre_golden_common_registers[] =
1075 {
1076         0xc770, 0xffffffff, 0x00000800,
1077         0xc774, 0xffffffff, 0x00000800,
1078         0xc798, 0xffffffff, 0x00007fbf,
1079         0xc79c, 0xffffffff, 0x00007faf
1080 };
1081
1082 static const u32 spectre_golden_registers[] =
1083 {
1084         0x3c000, 0xffff1fff, 0x96940200,
1085         0x3c00c, 0xffff0001, 0xff000000,
1086         0x3c200, 0xfffc0fff, 0x00000100,
1087         0x6ed8, 0x00010101, 0x00010000,
1088         0x9834, 0xf00fffff, 0x00000400,
1089         0x9838, 0xfffffffc, 0x00020200,
1090         0x5bb0, 0x000000f0, 0x00000070,
1091         0x5bc0, 0xf0311fff, 0x80300000,
1092         0x98f8, 0x73773777, 0x12010001,
1093         0x9b7c, 0x00ff0000, 0x00fc0000,
1094         0x2f48, 0x73773777, 0x12010001,
1095         0x8a14, 0xf000003f, 0x00000007,
1096         0x8b24, 0xffffffff, 0x00ffffff,
1097         0x28350, 0x3f3f3fff, 0x00000082,
1098         0x28355, 0x0000003f, 0x00000000,
1099         0x3e78, 0x00000001, 0x00000002,
1100         0x913c, 0xffff03df, 0x00000004,
1101         0xc768, 0x00000008, 0x00000008,
1102         0x8c00, 0x000008ff, 0x00000800,
1103         0x9508, 0x00010000, 0x00010000,
1104         0xac0c, 0xffffffff, 0x54763210,
1105         0x214f8, 0x01ff01ff, 0x00000002,
1106         0x21498, 0x007ff800, 0x00200000,
1107         0x2015c, 0xffffffff, 0x00000f40,
1108         0x30934, 0xffffffff, 0x00000001
1109 };
1110
1111 static const u32 spectre_mgcg_cgcg_init[] =
1112 {
1113         0xc420, 0xffffffff, 0xfffffffc,
1114         0x30800, 0xffffffff, 0xe0000000,
1115         0x3c2a0, 0xffffffff, 0x00000100,
1116         0x3c208, 0xffffffff, 0x00000100,
1117         0x3c2c0, 0xffffffff, 0x00000100,
1118         0x3c2c8, 0xffffffff, 0x00000100,
1119         0x3c2c4, 0xffffffff, 0x00000100,
1120         0x55e4, 0xffffffff, 0x00600100,
1121         0x3c280, 0xffffffff, 0x00000100,
1122         0x3c214, 0xffffffff, 0x06000100,
1123         0x3c220, 0xffffffff, 0x00000100,
1124         0x3c218, 0xffffffff, 0x06000100,
1125         0x3c204, 0xffffffff, 0x00000100,
1126         0x3c2e0, 0xffffffff, 0x00000100,
1127         0x3c224, 0xffffffff, 0x00000100,
1128         0x3c200, 0xffffffff, 0x00000100,
1129         0x3c230, 0xffffffff, 0x00000100,
1130         0x3c234, 0xffffffff, 0x00000100,
1131         0x3c250, 0xffffffff, 0x00000100,
1132         0x3c254, 0xffffffff, 0x00000100,
1133         0x3c258, 0xffffffff, 0x00000100,
1134         0x3c25c, 0xffffffff, 0x00000100,
1135         0x3c260, 0xffffffff, 0x00000100,
1136         0x3c27c, 0xffffffff, 0x00000100,
1137         0x3c278, 0xffffffff, 0x00000100,
1138         0x3c210, 0xffffffff, 0x06000100,
1139         0x3c290, 0xffffffff, 0x00000100,
1140         0x3c274, 0xffffffff, 0x00000100,
1141         0x3c2b4, 0xffffffff, 0x00000100,
1142         0x3c2b0, 0xffffffff, 0x00000100,
1143         0x3c270, 0xffffffff, 0x00000100,
1144         0x30800, 0xffffffff, 0xe0000000,
1145         0x3c020, 0xffffffff, 0x00010000,
1146         0x3c024, 0xffffffff, 0x00030002,
1147         0x3c028, 0xffffffff, 0x00040007,
1148         0x3c02c, 0xffffffff, 0x00060005,
1149         0x3c030, 0xffffffff, 0x00090008,
1150         0x3c034, 0xffffffff, 0x00010000,
1151         0x3c038, 0xffffffff, 0x00030002,
1152         0x3c03c, 0xffffffff, 0x00040007,
1153         0x3c040, 0xffffffff, 0x00060005,
1154         0x3c044, 0xffffffff, 0x00090008,
1155         0x3c048, 0xffffffff, 0x00010000,
1156         0x3c04c, 0xffffffff, 0x00030002,
1157         0x3c050, 0xffffffff, 0x00040007,
1158         0x3c054, 0xffffffff, 0x00060005,
1159         0x3c058, 0xffffffff, 0x00090008,
1160         0x3c05c, 0xffffffff, 0x00010000,
1161         0x3c060, 0xffffffff, 0x00030002,
1162         0x3c064, 0xffffffff, 0x00040007,
1163         0x3c068, 0xffffffff, 0x00060005,
1164         0x3c06c, 0xffffffff, 0x00090008,
1165         0x3c070, 0xffffffff, 0x00010000,
1166         0x3c074, 0xffffffff, 0x00030002,
1167         0x3c078, 0xffffffff, 0x00040007,
1168         0x3c07c, 0xffffffff, 0x00060005,
1169         0x3c080, 0xffffffff, 0x00090008,
1170         0x3c084, 0xffffffff, 0x00010000,
1171         0x3c088, 0xffffffff, 0x00030002,
1172         0x3c08c, 0xffffffff, 0x00040007,
1173         0x3c090, 0xffffffff, 0x00060005,
1174         0x3c094, 0xffffffff, 0x00090008,
1175         0x3c098, 0xffffffff, 0x00010000,
1176         0x3c09c, 0xffffffff, 0x00030002,
1177         0x3c0a0, 0xffffffff, 0x00040007,
1178         0x3c0a4, 0xffffffff, 0x00060005,
1179         0x3c0a8, 0xffffffff, 0x00090008,
1180         0x3c0ac, 0xffffffff, 0x00010000,
1181         0x3c0b0, 0xffffffff, 0x00030002,
1182         0x3c0b4, 0xffffffff, 0x00040007,
1183         0x3c0b8, 0xffffffff, 0x00060005,
1184         0x3c0bc, 0xffffffff, 0x00090008,
1185         0x3c000, 0xffffffff, 0x96e00200,
1186         0x8708, 0xffffffff, 0x00900100,
1187         0xc424, 0xffffffff, 0x0020003f,
1188         0x38, 0xffffffff, 0x0140001c,
1189         0x3c, 0x000f0000, 0x000f0000,
1190         0x220, 0xffffffff, 0xC060000C,
1191         0x224, 0xc0000fff, 0x00000100,
1192         0xf90, 0xffffffff, 0x00000100,
1193         0xf98, 0x00000101, 0x00000000,
1194         0x20a8, 0xffffffff, 0x00000104,
1195         0x55e4, 0xff000fff, 0x00000100,
1196         0x30cc, 0xc0000fff, 0x00000104,
1197         0xc1e4, 0x00000001, 0x00000001,
1198         0xd00c, 0xff000ff0, 0x00000100,
1199         0xd80c, 0xff000ff0, 0x00000100
1200 };
1201
1202 static const u32 kalindi_golden_spm_registers[] =
1203 {
1204         0x30800, 0xe0ffffff, 0xe0000000
1205 };
1206
1207 static const u32 kalindi_golden_common_registers[] =
1208 {
1209         0xc770, 0xffffffff, 0x00000800,
1210         0xc774, 0xffffffff, 0x00000800,
1211         0xc798, 0xffffffff, 0x00007fbf,
1212         0xc79c, 0xffffffff, 0x00007faf
1213 };
1214
1215 static const u32 kalindi_golden_registers[] =
1216 {
1217         0x3c000, 0xffffdfff, 0x6e944040,
1218         0x55e4, 0xff607fff, 0xfc000100,
1219         0x3c220, 0xff000fff, 0x00000100,
1220         0x3c224, 0xff000fff, 0x00000100,
1221         0x3c200, 0xfffc0fff, 0x00000100,
1222         0x6ed8, 0x00010101, 0x00010000,
1223         0x9830, 0xffffffff, 0x00000000,
1224         0x9834, 0xf00fffff, 0x00000400,
1225         0x5bb0, 0x000000f0, 0x00000070,
1226         0x5bc0, 0xf0311fff, 0x80300000,
1227         0x98f8, 0x73773777, 0x12010001,
1228         0x98fc, 0xffffffff, 0x00000010,
1229         0x9b7c, 0x00ff0000, 0x00fc0000,
1230         0x8030, 0x00001f0f, 0x0000100a,
1231         0x2f48, 0x73773777, 0x12010001,
1232         0x2408, 0x000fffff, 0x000c007f,
1233         0x8a14, 0xf000003f, 0x00000007,
1234         0x8b24, 0x3fff3fff, 0x00ffcfff,
1235         0x30a04, 0x0000ff0f, 0x00000000,
1236         0x28a4c, 0x07ffffff, 0x06000000,
1237         0x4d8, 0x00000fff, 0x00000100,
1238         0x3e78, 0x00000001, 0x00000002,
1239         0xc768, 0x00000008, 0x00000008,
1240         0x8c00, 0x000000ff, 0x00000003,
1241         0x214f8, 0x01ff01ff, 0x00000002,
1242         0x21498, 0x007ff800, 0x00200000,
1243         0x2015c, 0xffffffff, 0x00000f40,
1244         0x88c4, 0x001f3ae3, 0x00000082,
1245         0x88d4, 0x0000001f, 0x00000010,
1246         0x30934, 0xffffffff, 0x00000000
1247 };
1248
1249 static const u32 kalindi_mgcg_cgcg_init[] =
1250 {
1251         0xc420, 0xffffffff, 0xfffffffc,
1252         0x30800, 0xffffffff, 0xe0000000,
1253         0x3c2a0, 0xffffffff, 0x00000100,
1254         0x3c208, 0xffffffff, 0x00000100,
1255         0x3c2c0, 0xffffffff, 0x00000100,
1256         0x3c2c8, 0xffffffff, 0x00000100,
1257         0x3c2c4, 0xffffffff, 0x00000100,
1258         0x55e4, 0xffffffff, 0x00600100,
1259         0x3c280, 0xffffffff, 0x00000100,
1260         0x3c214, 0xffffffff, 0x06000100,
1261         0x3c220, 0xffffffff, 0x00000100,
1262         0x3c218, 0xffffffff, 0x06000100,
1263         0x3c204, 0xffffffff, 0x00000100,
1264         0x3c2e0, 0xffffffff, 0x00000100,
1265         0x3c224, 0xffffffff, 0x00000100,
1266         0x3c200, 0xffffffff, 0x00000100,
1267         0x3c230, 0xffffffff, 0x00000100,
1268         0x3c234, 0xffffffff, 0x00000100,
1269         0x3c250, 0xffffffff, 0x00000100,
1270         0x3c254, 0xffffffff, 0x00000100,
1271         0x3c258, 0xffffffff, 0x00000100,
1272         0x3c25c, 0xffffffff, 0x00000100,
1273         0x3c260, 0xffffffff, 0x00000100,
1274         0x3c27c, 0xffffffff, 0x00000100,
1275         0x3c278, 0xffffffff, 0x00000100,
1276         0x3c210, 0xffffffff, 0x06000100,
1277         0x3c290, 0xffffffff, 0x00000100,
1278         0x3c274, 0xffffffff, 0x00000100,
1279         0x3c2b4, 0xffffffff, 0x00000100,
1280         0x3c2b0, 0xffffffff, 0x00000100,
1281         0x3c270, 0xffffffff, 0x00000100,
1282         0x30800, 0xffffffff, 0xe0000000,
1283         0x3c020, 0xffffffff, 0x00010000,
1284         0x3c024, 0xffffffff, 0x00030002,
1285         0x3c028, 0xffffffff, 0x00040007,
1286         0x3c02c, 0xffffffff, 0x00060005,
1287         0x3c030, 0xffffffff, 0x00090008,
1288         0x3c034, 0xffffffff, 0x00010000,
1289         0x3c038, 0xffffffff, 0x00030002,
1290         0x3c03c, 0xffffffff, 0x00040007,
1291         0x3c040, 0xffffffff, 0x00060005,
1292         0x3c044, 0xffffffff, 0x00090008,
1293         0x3c000, 0xffffffff, 0x96e00200,
1294         0x8708, 0xffffffff, 0x00900100,
1295         0xc424, 0xffffffff, 0x0020003f,
1296         0x38, 0xffffffff, 0x0140001c,
1297         0x3c, 0x000f0000, 0x000f0000,
1298         0x220, 0xffffffff, 0xC060000C,
1299         0x224, 0xc0000fff, 0x00000100,
1300         0x20a8, 0xffffffff, 0x00000104,
1301         0x55e4, 0xff000fff, 0x00000100,
1302         0x30cc, 0xc0000fff, 0x00000104,
1303         0xc1e4, 0x00000001, 0x00000001,
1304         0xd00c, 0xff000ff0, 0x00000100,
1305         0xd80c, 0xff000ff0, 0x00000100
1306 };
1307
1308 static const u32 hawaii_golden_spm_registers[] =
1309 {
1310         0x30800, 0xe0ffffff, 0xe0000000
1311 };
1312
1313 static const u32 hawaii_golden_common_registers[] =
1314 {
1315         0x30800, 0xffffffff, 0xe0000000,
1316         0x28350, 0xffffffff, 0x3a00161a,
1317         0x28354, 0xffffffff, 0x0000002e,
1318         0x9a10, 0xffffffff, 0x00018208,
1319         0x98f8, 0xffffffff, 0x12011003
1320 };
1321
1322 static const u32 hawaii_golden_registers[] =
1323 {
1324         0x3354, 0x00000333, 0x00000333,
1325         0x9a10, 0x00010000, 0x00058208,
1326         0x9830, 0xffffffff, 0x00000000,
1327         0x9834, 0xf00fffff, 0x00000400,
1328         0x9838, 0x0002021c, 0x00020200,
1329         0xc78, 0x00000080, 0x00000000,
1330         0x5bb0, 0x000000f0, 0x00000070,
1331         0x5bc0, 0xf0311fff, 0x80300000,
1332         0x350c, 0x00810000, 0x408af000,
1333         0x7030, 0x31000111, 0x00000011,
1334         0x2f48, 0x73773777, 0x12010001,
1335         0x2120, 0x0000007f, 0x0000001b,
1336         0x21dc, 0x00007fb6, 0x00002191,
1337         0x3628, 0x0000003f, 0x0000000a,
1338         0x362c, 0x0000003f, 0x0000000a,
1339         0x2ae4, 0x00073ffe, 0x000022a2,
1340         0x240c, 0x000007ff, 0x00000000,
1341         0x8bf0, 0x00002001, 0x00000001,
1342         0x8b24, 0xffffffff, 0x00ffffff,
1343         0x30a04, 0x0000ff0f, 0x00000000,
1344         0x28a4c, 0x07ffffff, 0x06000000,
1345         0x3e78, 0x00000001, 0x00000002,
1346         0xc768, 0x00000008, 0x00000008,
1347         0xc770, 0x00000f00, 0x00000800,
1348         0xc774, 0x00000f00, 0x00000800,
1349         0xc798, 0x00ffffff, 0x00ff7fbf,
1350         0xc79c, 0x00ffffff, 0x00ff7faf,
1351         0x8c00, 0x000000ff, 0x00000800,
1352         0xe40, 0x00001fff, 0x00001fff,
1353         0x9060, 0x0000007f, 0x00000020,
1354         0x9508, 0x00010000, 0x00010000,
1355         0xae00, 0x00100000, 0x000ff07c,
1356         0xac14, 0x000003ff, 0x0000000f,
1357         0xac10, 0xffffffff, 0x7564fdec,
1358         0xac0c, 0xffffffff, 0x3120b9a8,
1359         0xac08, 0x20000000, 0x0f9c0000
1360 };
1361
1362 static const u32 hawaii_mgcg_cgcg_init[] =
1363 {
1364         0xc420, 0xffffffff, 0xfffffffd,
1365         0x30800, 0xffffffff, 0xe0000000,
1366         0x3c2a0, 0xffffffff, 0x00000100,
1367         0x3c208, 0xffffffff, 0x00000100,
1368         0x3c2c0, 0xffffffff, 0x00000100,
1369         0x3c2c8, 0xffffffff, 0x00000100,
1370         0x3c2c4, 0xffffffff, 0x00000100,
1371         0x55e4, 0xffffffff, 0x00200100,
1372         0x3c280, 0xffffffff, 0x00000100,
1373         0x3c214, 0xffffffff, 0x06000100,
1374         0x3c220, 0xffffffff, 0x00000100,
1375         0x3c218, 0xffffffff, 0x06000100,
1376         0x3c204, 0xffffffff, 0x00000100,
1377         0x3c2e0, 0xffffffff, 0x00000100,
1378         0x3c224, 0xffffffff, 0x00000100,
1379         0x3c200, 0xffffffff, 0x00000100,
1380         0x3c230, 0xffffffff, 0x00000100,
1381         0x3c234, 0xffffffff, 0x00000100,
1382         0x3c250, 0xffffffff, 0x00000100,
1383         0x3c254, 0xffffffff, 0x00000100,
1384         0x3c258, 0xffffffff, 0x00000100,
1385         0x3c25c, 0xffffffff, 0x00000100,
1386         0x3c260, 0xffffffff, 0x00000100,
1387         0x3c27c, 0xffffffff, 0x00000100,
1388         0x3c278, 0xffffffff, 0x00000100,
1389         0x3c210, 0xffffffff, 0x06000100,
1390         0x3c290, 0xffffffff, 0x00000100,
1391         0x3c274, 0xffffffff, 0x00000100,
1392         0x3c2b4, 0xffffffff, 0x00000100,
1393         0x3c2b0, 0xffffffff, 0x00000100,
1394         0x3c270, 0xffffffff, 0x00000100,
1395         0x30800, 0xffffffff, 0xe0000000,
1396         0x3c020, 0xffffffff, 0x00010000,
1397         0x3c024, 0xffffffff, 0x00030002,
1398         0x3c028, 0xffffffff, 0x00040007,
1399         0x3c02c, 0xffffffff, 0x00060005,
1400         0x3c030, 0xffffffff, 0x00090008,
1401         0x3c034, 0xffffffff, 0x00010000,
1402         0x3c038, 0xffffffff, 0x00030002,
1403         0x3c03c, 0xffffffff, 0x00040007,
1404         0x3c040, 0xffffffff, 0x00060005,
1405         0x3c044, 0xffffffff, 0x00090008,
1406         0x3c048, 0xffffffff, 0x00010000,
1407         0x3c04c, 0xffffffff, 0x00030002,
1408         0x3c050, 0xffffffff, 0x00040007,
1409         0x3c054, 0xffffffff, 0x00060005,
1410         0x3c058, 0xffffffff, 0x00090008,
1411         0x3c05c, 0xffffffff, 0x00010000,
1412         0x3c060, 0xffffffff, 0x00030002,
1413         0x3c064, 0xffffffff, 0x00040007,
1414         0x3c068, 0xffffffff, 0x00060005,
1415         0x3c06c, 0xffffffff, 0x00090008,
1416         0x3c070, 0xffffffff, 0x00010000,
1417         0x3c074, 0xffffffff, 0x00030002,
1418         0x3c078, 0xffffffff, 0x00040007,
1419         0x3c07c, 0xffffffff, 0x00060005,
1420         0x3c080, 0xffffffff, 0x00090008,
1421         0x3c084, 0xffffffff, 0x00010000,
1422         0x3c088, 0xffffffff, 0x00030002,
1423         0x3c08c, 0xffffffff, 0x00040007,
1424         0x3c090, 0xffffffff, 0x00060005,
1425         0x3c094, 0xffffffff, 0x00090008,
1426         0x3c098, 0xffffffff, 0x00010000,
1427         0x3c09c, 0xffffffff, 0x00030002,
1428         0x3c0a0, 0xffffffff, 0x00040007,
1429         0x3c0a4, 0xffffffff, 0x00060005,
1430         0x3c0a8, 0xffffffff, 0x00090008,
1431         0x3c0ac, 0xffffffff, 0x00010000,
1432         0x3c0b0, 0xffffffff, 0x00030002,
1433         0x3c0b4, 0xffffffff, 0x00040007,
1434         0x3c0b8, 0xffffffff, 0x00060005,
1435         0x3c0bc, 0xffffffff, 0x00090008,
1436         0x3c0c0, 0xffffffff, 0x00010000,
1437         0x3c0c4, 0xffffffff, 0x00030002,
1438         0x3c0c8, 0xffffffff, 0x00040007,
1439         0x3c0cc, 0xffffffff, 0x00060005,
1440         0x3c0d0, 0xffffffff, 0x00090008,
1441         0x3c0d4, 0xffffffff, 0x00010000,
1442         0x3c0d8, 0xffffffff, 0x00030002,
1443         0x3c0dc, 0xffffffff, 0x00040007,
1444         0x3c0e0, 0xffffffff, 0x00060005,
1445         0x3c0e4, 0xffffffff, 0x00090008,
1446         0x3c0e8, 0xffffffff, 0x00010000,
1447         0x3c0ec, 0xffffffff, 0x00030002,
1448         0x3c0f0, 0xffffffff, 0x00040007,
1449         0x3c0f4, 0xffffffff, 0x00060005,
1450         0x3c0f8, 0xffffffff, 0x00090008,
1451         0xc318, 0xffffffff, 0x00020200,
1452         0x3350, 0xffffffff, 0x00000200,
1453         0x15c0, 0xffffffff, 0x00000400,
1454         0x55e8, 0xffffffff, 0x00000000,
1455         0x2f50, 0xffffffff, 0x00000902,
1456         0x3c000, 0xffffffff, 0x96940200,
1457         0x8708, 0xffffffff, 0x00900100,
1458         0xc424, 0xffffffff, 0x0020003f,
1459         0x38, 0xffffffff, 0x0140001c,
1460         0x3c, 0x000f0000, 0x000f0000,
1461         0x220, 0xffffffff, 0xc060000c,
1462         0x224, 0xc0000fff, 0x00000100,
1463         0xf90, 0xffffffff, 0x00000100,
1464         0xf98, 0x00000101, 0x00000000,
1465         0x20a8, 0xffffffff, 0x00000104,
1466         0x55e4, 0xff000fff, 0x00000100,
1467         0x30cc, 0xc0000fff, 0x00000104,
1468         0xc1e4, 0x00000001, 0x00000001,
1469         0xd00c, 0xff000ff0, 0x00000100,
1470         0xd80c, 0xff000ff0, 0x00000100
1471 };
1472
1473 static void cik_init_golden_registers(struct radeon_device *rdev)
1474 {
1475         switch (rdev->family) {
1476         case CHIP_BONAIRE:
1477                 radeon_program_register_sequence(rdev,
1478                                                  bonaire_mgcg_cgcg_init,
1479                                                  (const u32)ARRAY_SIZE(bonaire_mgcg_cgcg_init));
1480                 radeon_program_register_sequence(rdev,
1481                                                  bonaire_golden_registers,
1482                                                  (const u32)ARRAY_SIZE(bonaire_golden_registers));
1483                 radeon_program_register_sequence(rdev,
1484                                                  bonaire_golden_common_registers,
1485                                                  (const u32)ARRAY_SIZE(bonaire_golden_common_registers));
1486                 radeon_program_register_sequence(rdev,
1487                                                  bonaire_golden_spm_registers,
1488                                                  (const u32)ARRAY_SIZE(bonaire_golden_spm_registers));
1489                 break;
1490         case CHIP_KABINI:
1491                 radeon_program_register_sequence(rdev,
1492                                                  kalindi_mgcg_cgcg_init,
1493                                                  (const u32)ARRAY_SIZE(kalindi_mgcg_cgcg_init));
1494                 radeon_program_register_sequence(rdev,
1495                                                  kalindi_golden_registers,
1496                                                  (const u32)ARRAY_SIZE(kalindi_golden_registers));
1497                 radeon_program_register_sequence(rdev,
1498                                                  kalindi_golden_common_registers,
1499                                                  (const u32)ARRAY_SIZE(kalindi_golden_common_registers));
1500                 radeon_program_register_sequence(rdev,
1501                                                  kalindi_golden_spm_registers,
1502                                                  (const u32)ARRAY_SIZE(kalindi_golden_spm_registers));
1503                 break;
1504         case CHIP_KAVERI:
1505                 radeon_program_register_sequence(rdev,
1506                                                  spectre_mgcg_cgcg_init,
1507                                                  (const u32)ARRAY_SIZE(spectre_mgcg_cgcg_init));
1508                 radeon_program_register_sequence(rdev,
1509                                                  spectre_golden_registers,
1510                                                  (const u32)ARRAY_SIZE(spectre_golden_registers));
1511                 radeon_program_register_sequence(rdev,
1512                                                  spectre_golden_common_registers,
1513                                                  (const u32)ARRAY_SIZE(spectre_golden_common_registers));
1514                 radeon_program_register_sequence(rdev,
1515                                                  spectre_golden_spm_registers,
1516                                                  (const u32)ARRAY_SIZE(spectre_golden_spm_registers));
1517                 break;
1518         case CHIP_HAWAII:
1519                 radeon_program_register_sequence(rdev,
1520                                                  hawaii_mgcg_cgcg_init,
1521                                                  (const u32)ARRAY_SIZE(hawaii_mgcg_cgcg_init));
1522                 radeon_program_register_sequence(rdev,
1523                                                  hawaii_golden_registers,
1524                                                  (const u32)ARRAY_SIZE(hawaii_golden_registers));
1525                 radeon_program_register_sequence(rdev,
1526                                                  hawaii_golden_common_registers,
1527                                                  (const u32)ARRAY_SIZE(hawaii_golden_common_registers));
1528                 radeon_program_register_sequence(rdev,
1529                                                  hawaii_golden_spm_registers,
1530                                                  (const u32)ARRAY_SIZE(hawaii_golden_spm_registers));
1531                 break;
1532         default:
1533                 break;
1534         }
1535 }
1536
1537 /**
1538  * cik_get_xclk - get the xclk
1539  *
1540  * @rdev: radeon_device pointer
1541  *
1542  * Returns the reference clock used by the gfx engine
1543  * (CIK).
1544  */
1545 u32 cik_get_xclk(struct radeon_device *rdev)
1546 {
1547         u32 reference_clock = rdev->clock.spll.reference_freq;
1548
1549         if (rdev->flags & RADEON_IS_IGP) {
1550                 if (RREG32_SMC(GENERAL_PWRMGT) & GPU_COUNTER_CLK)
1551                         return reference_clock / 2;
1552         } else {
1553                 if (RREG32_SMC(CG_CLKPIN_CNTL) & XTALIN_DIVIDE)
1554                         return reference_clock / 4;
1555         }
1556         return reference_clock;
1557 }
1558
1559 /**
1560  * cik_mm_rdoorbell - read a doorbell dword
1561  *
1562  * @rdev: radeon_device pointer
1563  * @index: doorbell index
1564  *
1565  * Returns the value in the doorbell aperture at the
1566  * requested doorbell index (CIK).
1567  */
1568 u32 cik_mm_rdoorbell(struct radeon_device *rdev, u32 index)
1569 {
1570         if (index < rdev->doorbell.num_doorbells) {
1571                 return readl(rdev->doorbell.ptr + index);
1572         } else {
1573                 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
1574                 return 0;
1575         }
1576 }
1577
1578 /**
1579  * cik_mm_wdoorbell - write a doorbell dword
1580  *
1581  * @rdev: radeon_device pointer
1582  * @index: doorbell index
1583  * @v: value to write
1584  *
1585  * Writes @v to the doorbell aperture at the
1586  * requested doorbell index (CIK).
1587  */
1588 void cik_mm_wdoorbell(struct radeon_device *rdev, u32 index, u32 v)
1589 {
1590         if (index < rdev->doorbell.num_doorbells) {
1591                 writel(v, rdev->doorbell.ptr + index);
1592         } else {
1593                 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
1594         }
1595 }
1596
1597 #define BONAIRE_IO_MC_REGS_SIZE 36
1598
1599 static const u32 bonaire_io_mc_regs[BONAIRE_IO_MC_REGS_SIZE][2] =
1600 {
1601         {0x00000070, 0x04400000},
1602         {0x00000071, 0x80c01803},
1603         {0x00000072, 0x00004004},
1604         {0x00000073, 0x00000100},
1605         {0x00000074, 0x00ff0000},
1606         {0x00000075, 0x34000000},
1607         {0x00000076, 0x08000014},
1608         {0x00000077, 0x00cc08ec},
1609         {0x00000078, 0x00000400},
1610         {0x00000079, 0x00000000},
1611         {0x0000007a, 0x04090000},
1612         {0x0000007c, 0x00000000},
1613         {0x0000007e, 0x4408a8e8},
1614         {0x0000007f, 0x00000304},
1615         {0x00000080, 0x00000000},
1616         {0x00000082, 0x00000001},
1617         {0x00000083, 0x00000002},
1618         {0x00000084, 0xf3e4f400},
1619         {0x00000085, 0x052024e3},
1620         {0x00000087, 0x00000000},
1621         {0x00000088, 0x01000000},
1622         {0x0000008a, 0x1c0a0000},
1623         {0x0000008b, 0xff010000},
1624         {0x0000008d, 0xffffefff},
1625         {0x0000008e, 0xfff3efff},
1626         {0x0000008f, 0xfff3efbf},
1627         {0x00000092, 0xf7ffffff},
1628         {0x00000093, 0xffffff7f},
1629         {0x00000095, 0x00101101},
1630         {0x00000096, 0x00000fff},
1631         {0x00000097, 0x00116fff},
1632         {0x00000098, 0x60010000},
1633         {0x00000099, 0x10010000},
1634         {0x0000009a, 0x00006000},
1635         {0x0000009b, 0x00001000},
1636         {0x0000009f, 0x00b48000}
1637 };
1638
1639 #define HAWAII_IO_MC_REGS_SIZE 22
1640
1641 static const u32 hawaii_io_mc_regs[HAWAII_IO_MC_REGS_SIZE][2] =
1642 {
1643         {0x0000007d, 0x40000000},
1644         {0x0000007e, 0x40180304},
1645         {0x0000007f, 0x0000ff00},
1646         {0x00000081, 0x00000000},
1647         {0x00000083, 0x00000800},
1648         {0x00000086, 0x00000000},
1649         {0x00000087, 0x00000100},
1650         {0x00000088, 0x00020100},
1651         {0x00000089, 0x00000000},
1652         {0x0000008b, 0x00040000},
1653         {0x0000008c, 0x00000100},
1654         {0x0000008e, 0xff010000},
1655         {0x00000090, 0xffffefff},
1656         {0x00000091, 0xfff3efff},
1657         {0x00000092, 0xfff3efbf},
1658         {0x00000093, 0xf7ffffff},
1659         {0x00000094, 0xffffff7f},
1660         {0x00000095, 0x00000fff},
1661         {0x00000096, 0x00116fff},
1662         {0x00000097, 0x60010000},
1663         {0x00000098, 0x10010000},
1664         {0x0000009f, 0x00c79000}
1665 };
1666
1667
1668 /**
1669  * cik_srbm_select - select specific register instances
1670  *
1671  * @rdev: radeon_device pointer
1672  * @me: selected ME (micro engine)
1673  * @pipe: pipe
1674  * @queue: queue
1675  * @vmid: VMID
1676  *
1677  * Switches the currently active registers instances.  Some
1678  * registers are instanced per VMID, others are instanced per
1679  * me/pipe/queue combination.
1680  */
1681 static void cik_srbm_select(struct radeon_device *rdev,
1682                             u32 me, u32 pipe, u32 queue, u32 vmid)
1683 {
1684         u32 srbm_gfx_cntl = (PIPEID(pipe & 0x3) |
1685                              MEID(me & 0x3) |
1686                              VMID(vmid & 0xf) |
1687                              QUEUEID(queue & 0x7));
1688         WREG32(SRBM_GFX_CNTL, srbm_gfx_cntl);
1689 }
1690
1691 /* ucode loading */
1692 /**
1693  * ci_mc_load_microcode - load MC ucode into the hw
1694  *
1695  * @rdev: radeon_device pointer
1696  *
1697  * Load the GDDR MC ucode into the hw (CIK).
1698  * Returns 0 on success, error on failure.
1699  */
1700 int ci_mc_load_microcode(struct radeon_device *rdev)
1701 {
1702         const __be32 *fw_data;
1703         u32 running, blackout = 0;
1704         u32 *io_mc_regs;
1705         int i, ucode_size, regs_size;
1706
1707         if (!rdev->mc_fw)
1708                 return -EINVAL;
1709
1710         switch (rdev->family) {
1711         case CHIP_BONAIRE:
1712                 io_mc_regs = (u32 *)&bonaire_io_mc_regs;
1713                 ucode_size = CIK_MC_UCODE_SIZE;
1714                 regs_size = BONAIRE_IO_MC_REGS_SIZE;
1715                 break;
1716         case CHIP_HAWAII:
1717                 io_mc_regs = (u32 *)&hawaii_io_mc_regs;
1718                 ucode_size = HAWAII_MC_UCODE_SIZE;
1719                 regs_size = HAWAII_IO_MC_REGS_SIZE;
1720                 break;
1721         default:
1722                 return -EINVAL;
1723         }
1724
1725         running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
1726
1727         if (running == 0) {
1728                 if (running) {
1729                         blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
1730                         WREG32(MC_SHARED_BLACKOUT_CNTL, blackout | 1);
1731                 }
1732
1733                 /* reset the engine and set to writable */
1734                 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
1735                 WREG32(MC_SEQ_SUP_CNTL, 0x00000010);
1736
1737                 /* load mc io regs */
1738                 for (i = 0; i < regs_size; i++) {
1739                         WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);
1740                         WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);
1741                 }
1742                 /* load the MC ucode */
1743                 fw_data = (const __be32 *)rdev->mc_fw->data;
1744                 for (i = 0; i < ucode_size; i++)
1745                         WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));
1746
1747                 /* put the engine back into the active state */
1748                 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
1749                 WREG32(MC_SEQ_SUP_CNTL, 0x00000004);
1750                 WREG32(MC_SEQ_SUP_CNTL, 0x00000001);
1751
1752                 /* wait for training to complete */
1753                 for (i = 0; i < rdev->usec_timeout; i++) {
1754                         if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D0)
1755                                 break;
1756                         udelay(1);
1757                 }
1758                 for (i = 0; i < rdev->usec_timeout; i++) {
1759                         if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D1)
1760                                 break;
1761                         udelay(1);
1762                 }
1763
1764                 if (running)
1765                         WREG32(MC_SHARED_BLACKOUT_CNTL, blackout);
1766         }
1767
1768         return 0;
1769 }
1770
1771 /**
1772  * cik_init_microcode - load ucode images from disk
1773  *
1774  * @rdev: radeon_device pointer
1775  *
1776  * Use the firmware interface to load the ucode images into
1777  * the driver (not loaded into hw).
1778  * Returns 0 on success, error on failure.
1779  */
1780 static int cik_init_microcode(struct radeon_device *rdev)
1781 {
1782         const char *chip_name;
1783         size_t pfp_req_size, me_req_size, ce_req_size,
1784                 mec_req_size, rlc_req_size, mc_req_size = 0,
1785                 sdma_req_size, smc_req_size = 0;
1786         char fw_name[30];
1787         int err;
1788
1789         DRM_DEBUG("\n");
1790
1791         switch (rdev->family) {
1792         case CHIP_BONAIRE:
1793                 chip_name = "BONAIRE";
1794                 pfp_req_size = CIK_PFP_UCODE_SIZE * 4;
1795                 me_req_size = CIK_ME_UCODE_SIZE * 4;
1796                 ce_req_size = CIK_CE_UCODE_SIZE * 4;
1797                 mec_req_size = CIK_MEC_UCODE_SIZE * 4;
1798                 rlc_req_size = BONAIRE_RLC_UCODE_SIZE * 4;
1799                 mc_req_size = CIK_MC_UCODE_SIZE * 4;
1800                 sdma_req_size = CIK_SDMA_UCODE_SIZE * 4;
1801                 smc_req_size = ALIGN(BONAIRE_SMC_UCODE_SIZE, 4);
1802                 break;
1803         case CHIP_HAWAII:
1804                 chip_name = "HAWAII";
1805                 pfp_req_size = CIK_PFP_UCODE_SIZE * 4;
1806                 me_req_size = CIK_ME_UCODE_SIZE * 4;
1807                 ce_req_size = CIK_CE_UCODE_SIZE * 4;
1808                 mec_req_size = CIK_MEC_UCODE_SIZE * 4;
1809                 rlc_req_size = BONAIRE_RLC_UCODE_SIZE * 4;
1810                 mc_req_size = HAWAII_MC_UCODE_SIZE * 4;
1811                 sdma_req_size = CIK_SDMA_UCODE_SIZE * 4;
1812                 smc_req_size = ALIGN(HAWAII_SMC_UCODE_SIZE, 4);
1813                 break;
1814         case CHIP_KAVERI:
1815                 chip_name = "KAVERI";
1816                 pfp_req_size = CIK_PFP_UCODE_SIZE * 4;
1817                 me_req_size = CIK_ME_UCODE_SIZE * 4;
1818                 ce_req_size = CIK_CE_UCODE_SIZE * 4;
1819                 mec_req_size = CIK_MEC_UCODE_SIZE * 4;
1820                 rlc_req_size = KV_RLC_UCODE_SIZE * 4;
1821                 sdma_req_size = CIK_SDMA_UCODE_SIZE * 4;
1822                 break;
1823         case CHIP_KABINI:
1824                 chip_name = "KABINI";
1825                 pfp_req_size = CIK_PFP_UCODE_SIZE * 4;
1826                 me_req_size = CIK_ME_UCODE_SIZE * 4;
1827                 ce_req_size = CIK_CE_UCODE_SIZE * 4;
1828                 mec_req_size = CIK_MEC_UCODE_SIZE * 4;
1829                 rlc_req_size = KB_RLC_UCODE_SIZE * 4;
1830                 sdma_req_size = CIK_SDMA_UCODE_SIZE * 4;
1831                 break;
1832         default: BUG();
1833         }
1834
1835         DRM_INFO("Loading %s Microcode\n", chip_name);
1836
1837         snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
1838         err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev);
1839         if (err)
1840                 goto out;
1841         if (rdev->pfp_fw->size != pfp_req_size) {
1842                 printk(KERN_ERR
1843                        "cik_cp: Bogus length %zu in firmware \"%s\"\n",
1844                        rdev->pfp_fw->size, fw_name);
1845                 err = -EINVAL;
1846                 goto out;
1847         }
1848
1849         snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
1850         err = request_firmware(&rdev->me_fw, fw_name, rdev->dev);
1851         if (err)
1852                 goto out;
1853         if (rdev->me_fw->size != me_req_size) {
1854                 printk(KERN_ERR
1855                        "cik_cp: Bogus length %zu in firmware \"%s\"\n",
1856                        rdev->me_fw->size, fw_name);
1857                 err = -EINVAL;
1858         }
1859
1860         snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name);
1861         err = request_firmware(&rdev->ce_fw, fw_name, rdev->dev);
1862         if (err)
1863                 goto out;
1864         if (rdev->ce_fw->size != ce_req_size) {
1865                 printk(KERN_ERR
1866                        "cik_cp: Bogus length %zu in firmware \"%s\"\n",
1867                        rdev->ce_fw->size, fw_name);
1868                 err = -EINVAL;
1869         }
1870
1871         snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec.bin", chip_name);
1872         err = request_firmware(&rdev->mec_fw, fw_name, rdev->dev);
1873         if (err)
1874                 goto out;
1875         if (rdev->mec_fw->size != mec_req_size) {
1876                 printk(KERN_ERR
1877                        "cik_cp: Bogus length %zu in firmware \"%s\"\n",
1878                        rdev->mec_fw->size, fw_name);
1879                 err = -EINVAL;
1880         }
1881
1882         snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", chip_name);
1883         err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev);
1884         if (err)
1885                 goto out;
1886         if (rdev->rlc_fw->size != rlc_req_size) {
1887                 printk(KERN_ERR
1888                        "cik_rlc: Bogus length %zu in firmware \"%s\"\n",
1889                        rdev->rlc_fw->size, fw_name);
1890                 err = -EINVAL;
1891         }
1892
1893         snprintf(fw_name, sizeof(fw_name), "radeon/%s_sdma.bin", chip_name);
1894         err = request_firmware(&rdev->sdma_fw, fw_name, rdev->dev);
1895         if (err)
1896                 goto out;
1897         if (rdev->sdma_fw->size != sdma_req_size) {
1898                 printk(KERN_ERR
1899                        "cik_sdma: Bogus length %zu in firmware \"%s\"\n",
1900                        rdev->sdma_fw->size, fw_name);
1901                 err = -EINVAL;
1902         }
1903
1904         /* No SMC, MC ucode on APUs */
1905         if (!(rdev->flags & RADEON_IS_IGP)) {
1906                 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
1907                 err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev);
1908                 if (err)
1909                         goto out;
1910                 if (rdev->mc_fw->size != mc_req_size) {
1911                         printk(KERN_ERR
1912                                "cik_mc: Bogus length %zu in firmware \"%s\"\n",
1913                                rdev->mc_fw->size, fw_name);
1914                         err = -EINVAL;
1915                 }
1916
1917                 snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", chip_name);
1918                 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev);
1919                 if (err) {
1920                         printk(KERN_ERR
1921                                "smc: error loading firmware \"%s\"\n",
1922                                fw_name);
1923                         release_firmware(rdev->smc_fw);
1924                         rdev->smc_fw = NULL;
1925                         err = 0;
1926                 } else if (rdev->smc_fw->size != smc_req_size) {
1927                         printk(KERN_ERR
1928                                "cik_smc: Bogus length %zu in firmware \"%s\"\n",
1929                                rdev->smc_fw->size, fw_name);
1930                         err = -EINVAL;
1931                 }
1932         }
1933
1934 out:
1935         if (err) {
1936                 if (err != -EINVAL)
1937                         printk(KERN_ERR
1938                                "cik_cp: Failed to load firmware \"%s\"\n",
1939                                fw_name);
1940                 release_firmware(rdev->pfp_fw);
1941                 rdev->pfp_fw = NULL;
1942                 release_firmware(rdev->me_fw);
1943                 rdev->me_fw = NULL;
1944                 release_firmware(rdev->ce_fw);
1945                 rdev->ce_fw = NULL;
1946                 release_firmware(rdev->rlc_fw);
1947                 rdev->rlc_fw = NULL;
1948                 release_firmware(rdev->mc_fw);
1949                 rdev->mc_fw = NULL;
1950                 release_firmware(rdev->smc_fw);
1951                 rdev->smc_fw = NULL;
1952         }
1953         return err;
1954 }
1955
1956 /*
1957  * Core functions
1958  */
1959 /**
1960  * cik_tiling_mode_table_init - init the hw tiling table
1961  *
1962  * @rdev: radeon_device pointer
1963  *
1964  * Starting with SI, the tiling setup is done globally in a
1965  * set of 32 tiling modes.  Rather than selecting each set of
1966  * parameters per surface as on older asics, we just select
1967  * which index in the tiling table we want to use, and the
1968  * surface uses those parameters (CIK).
1969  */
1970 static void cik_tiling_mode_table_init(struct radeon_device *rdev)
1971 {
1972         const u32 num_tile_mode_states = 32;
1973         const u32 num_secondary_tile_mode_states = 16;
1974         u32 reg_offset, gb_tile_moden, split_equal_to_row_size;
1975         u32 num_pipe_configs;
1976         u32 num_rbs = rdev->config.cik.max_backends_per_se *
1977                 rdev->config.cik.max_shader_engines;
1978
1979         switch (rdev->config.cik.mem_row_size_in_kb) {
1980         case 1:
1981                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
1982                 break;
1983         case 2:
1984         default:
1985                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
1986                 break;
1987         case 4:
1988                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
1989                 break;
1990         }
1991
1992         num_pipe_configs = rdev->config.cik.max_tile_pipes;
1993         if (num_pipe_configs > 8)
1994                 num_pipe_configs = 16;
1995
1996         if (num_pipe_configs == 16) {
1997                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
1998                         switch (reg_offset) {
1999                         case 0:
2000                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2001                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2002                                                  PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2003                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
2004                                 break;
2005                         case 1:
2006                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2007                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2008                                                  PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2009                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
2010                                 break;
2011                         case 2:
2012                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2013                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2014                                                  PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2015                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
2016                                 break;
2017                         case 3:
2018                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2019                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2020                                                  PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2021                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
2022                                 break;
2023                         case 4:
2024                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2025                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2026                                                  PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2027                                                  TILE_SPLIT(split_equal_to_row_size));
2028                                 break;
2029                         case 5:
2030                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2031                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2032                                 break;
2033                         case 6:
2034                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2035                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2036                                                  PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2037                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
2038                                 break;
2039                         case 7:
2040                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2041                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2042                                                  PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2043                                                  TILE_SPLIT(split_equal_to_row_size));
2044                                 break;
2045                         case 8:
2046                                 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2047                                                  PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16));
2048                                 break;
2049                         case 9:
2050                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2051                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
2052                                 break;
2053                         case 10:
2054                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2055                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2056                                                  PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2057                                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2058                                 break;
2059                         case 11:
2060                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2061                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2062                                                  PIPE_CONFIG(ADDR_SURF_P16_32x32_8x16) |
2063                                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2064                                 break;
2065                         case 12:
2066                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2067                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2068                                                  PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2069                                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2070                                 break;
2071                         case 13:
2072                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2073                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
2074                                 break;
2075                         case 14:
2076                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2077                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2078                                                  PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2079                                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2080                                 break;
2081                         case 16:
2082                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2083                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2084                                                  PIPE_CONFIG(ADDR_SURF_P16_32x32_8x16) |
2085                                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2086                                 break;
2087                         case 17:
2088                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2089                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2090                                                  PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2091                                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2092                                 break;
2093                         case 27:
2094                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2095                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
2096                                 break;
2097                         case 28:
2098                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2099                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2100                                                  PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2101                                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2102                                 break;
2103                         case 29:
2104                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2105                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2106                                                  PIPE_CONFIG(ADDR_SURF_P16_32x32_8x16) |
2107                                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2108                                 break;
2109                         case 30:
2110                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2111                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2112                                                  PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
2113                                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2114                                 break;
2115                         default:
2116                                 gb_tile_moden = 0;
2117                                 break;
2118                         }
2119                         rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden;
2120                         WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
2121                 }
2122                 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
2123                         switch (reg_offset) {
2124                         case 0:
2125                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2126                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2127                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2128                                                  NUM_BANKS(ADDR_SURF_16_BANK));
2129                                 break;
2130                         case 1:
2131                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2132                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2133                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2134                                                  NUM_BANKS(ADDR_SURF_16_BANK));
2135                                 break;
2136                         case 2:
2137                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2138                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2139                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2140                                                  NUM_BANKS(ADDR_SURF_16_BANK));
2141                                 break;
2142                         case 3:
2143                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2144                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2145                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2146                                                  NUM_BANKS(ADDR_SURF_16_BANK));
2147                                 break;
2148                         case 4:
2149                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2150                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2151                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2152                                                  NUM_BANKS(ADDR_SURF_8_BANK));
2153                                 break;
2154                         case 5:
2155                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2156                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2157                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2158                                                  NUM_BANKS(ADDR_SURF_4_BANK));
2159                                 break;
2160                         case 6:
2161                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2162                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2163                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2164                                                  NUM_BANKS(ADDR_SURF_2_BANK));
2165                                 break;
2166                         case 8:
2167                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2168                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2169                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2170                                                  NUM_BANKS(ADDR_SURF_16_BANK));
2171                                 break;
2172                         case 9:
2173                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2174                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2175                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2176                                                  NUM_BANKS(ADDR_SURF_16_BANK));
2177                                 break;
2178                         case 10:
2179                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2180                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2181                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2182                                                  NUM_BANKS(ADDR_SURF_16_BANK));
2183                                 break;
2184                         case 11:
2185                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2186                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2187                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2188                                                  NUM_BANKS(ADDR_SURF_8_BANK));
2189                                 break;
2190                         case 12:
2191                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2192                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2193                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2194                                                  NUM_BANKS(ADDR_SURF_4_BANK));
2195                                 break;
2196                         case 13:
2197                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2198                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2199                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2200                                                  NUM_BANKS(ADDR_SURF_2_BANK));
2201                                 break;
2202                         case 14:
2203                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2204                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2205                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2206                                                  NUM_BANKS(ADDR_SURF_2_BANK));
2207                                 break;
2208                         default:
2209                                 gb_tile_moden = 0;
2210                                 break;
2211                         }
2212                         WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden);
2213                 }
2214         } else if (num_pipe_configs == 8) {
2215                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
2216                         switch (reg_offset) {
2217                         case 0:
2218                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2219                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2220                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2221                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
2222                                 break;
2223                         case 1:
2224                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2225                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2226                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2227                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
2228                                 break;
2229                         case 2:
2230                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2231                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2232                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2233                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
2234                                 break;
2235                         case 3:
2236                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2237                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2238                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2239                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
2240                                 break;
2241                         case 4:
2242                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2243                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2244                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2245                                                  TILE_SPLIT(split_equal_to_row_size));
2246                                 break;
2247                         case 5:
2248                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2249                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2250                                 break;
2251                         case 6:
2252                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2253                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2254                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2255                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
2256                                 break;
2257                         case 7:
2258                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2259                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2260                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2261                                                  TILE_SPLIT(split_equal_to_row_size));
2262                                 break;
2263                         case 8:
2264                                 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2265                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16));
2266                                 break;
2267                         case 9:
2268                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2269                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
2270                                 break;
2271                         case 10:
2272                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2273                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2274                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2275                                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2276                                 break;
2277                         case 11:
2278                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2279                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2280                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2281                                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2282                                 break;
2283                         case 12:
2284                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2285                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2286                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2287                                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2288                                 break;
2289                         case 13:
2290                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2291                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
2292                                 break;
2293                         case 14:
2294                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2295                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2296                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2297                                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2298                                 break;
2299                         case 16:
2300                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2301                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2302                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2303                                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2304                                 break;
2305                         case 17:
2306                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2307                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2308                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2309                                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2310                                 break;
2311                         case 27:
2312                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2313                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
2314                                 break;
2315                         case 28:
2316                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2317                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2318                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2319                                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2320                                 break;
2321                         case 29:
2322                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2323                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2324                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
2325                                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2326                                 break;
2327                         case 30:
2328                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2329                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2330                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
2331                                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2332                                 break;
2333                         default:
2334                                 gb_tile_moden = 0;
2335                                 break;
2336                         }
2337                         rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden;
2338                         WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
2339                 }
2340                 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
2341                         switch (reg_offset) {
2342                         case 0:
2343                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2344                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2345                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2346                                                  NUM_BANKS(ADDR_SURF_16_BANK));
2347                                 break;
2348                         case 1:
2349                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2350                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2351                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2352                                                  NUM_BANKS(ADDR_SURF_16_BANK));
2353                                 break;
2354                         case 2:
2355                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2356                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2357                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2358                                                  NUM_BANKS(ADDR_SURF_16_BANK));
2359                                 break;
2360                         case 3:
2361                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2362                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2363                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2364                                                  NUM_BANKS(ADDR_SURF_16_BANK));
2365                                 break;
2366                         case 4:
2367                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2368                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2369                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2370                                                  NUM_BANKS(ADDR_SURF_8_BANK));
2371                                 break;
2372                         case 5:
2373                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2374                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2375                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2376                                                  NUM_BANKS(ADDR_SURF_4_BANK));
2377                                 break;
2378                         case 6:
2379                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2380                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2381                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2382                                                  NUM_BANKS(ADDR_SURF_2_BANK));
2383                                 break;
2384                         case 8:
2385                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2386                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2387                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2388                                                  NUM_BANKS(ADDR_SURF_16_BANK));
2389                                 break;
2390                         case 9:
2391                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2392                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2393                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2394                                                  NUM_BANKS(ADDR_SURF_16_BANK));
2395                                 break;
2396                         case 10:
2397                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2398                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2399                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2400                                                  NUM_BANKS(ADDR_SURF_16_BANK));
2401                                 break;
2402                         case 11:
2403                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2404                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2405                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2406                                                  NUM_BANKS(ADDR_SURF_16_BANK));
2407                                 break;
2408                         case 12:
2409                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2410                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2411                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2412                                                  NUM_BANKS(ADDR_SURF_8_BANK));
2413                                 break;
2414                         case 13:
2415                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2416                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2417                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2418                                                  NUM_BANKS(ADDR_SURF_4_BANK));
2419                                 break;
2420                         case 14:
2421                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2422                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2423                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2424                                                  NUM_BANKS(ADDR_SURF_2_BANK));
2425                                 break;
2426                         default:
2427                                 gb_tile_moden = 0;
2428                                 break;
2429                         }
2430                         rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden;
2431                         WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden);
2432                 }
2433         } else if (num_pipe_configs == 4) {
2434                 if (num_rbs == 4) {
2435                         for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
2436                                 switch (reg_offset) {
2437                                 case 0:
2438                                         gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2439                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2440                                                          PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2441                                                          TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
2442                                         break;
2443                                 case 1:
2444                                         gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2445                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2446                                                          PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2447                                                          TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
2448                                         break;
2449                                 case 2:
2450                                         gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2451                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2452                                                          PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2453                                                          TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
2454                                         break;
2455                                 case 3:
2456                                         gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2457                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2458                                                          PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2459                                                          TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
2460                                         break;
2461                                 case 4:
2462                                         gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2463                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2464                                                          PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2465                                                          TILE_SPLIT(split_equal_to_row_size));
2466                                         break;
2467                                 case 5:
2468                                         gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2469                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2470                                         break;
2471                                 case 6:
2472                                         gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2473                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2474                                                          PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2475                                                          TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
2476                                         break;
2477                                 case 7:
2478                                         gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2479                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2480                                                          PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2481                                                          TILE_SPLIT(split_equal_to_row_size));
2482                                         break;
2483                                 case 8:
2484                                         gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2485                                                          PIPE_CONFIG(ADDR_SURF_P4_16x16));
2486                                         break;
2487                                 case 9:
2488                                         gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2489                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
2490                                         break;
2491                                 case 10:
2492                                         gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2493                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2494                                                          PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2495                                                          SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2496                                         break;
2497                                 case 11:
2498                                         gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2499                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2500                                                          PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2501                                                          SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2502                                         break;
2503                                 case 12:
2504                                         gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2505                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2506                                                          PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2507                                                          SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2508                                         break;
2509                                 case 13:
2510                                         gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2511                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
2512                                         break;
2513                                 case 14:
2514                                         gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2515                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2516                                                          PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2517                                                          SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2518                                         break;
2519                                 case 16:
2520                                         gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2521                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2522                                                          PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2523                                                          SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2524                                         break;
2525                                 case 17:
2526                                         gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2527                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2528                                                          PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2529                                                          SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2530                                         break;
2531                                 case 27:
2532                                         gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2533                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
2534                                         break;
2535                                 case 28:
2536                                         gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2537                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2538                                                          PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2539                                                          SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2540                                         break;
2541                                 case 29:
2542                                         gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2543                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2544                                                          PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2545                                                          SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2546                                         break;
2547                                 case 30:
2548                                         gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2549                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2550                                                          PIPE_CONFIG(ADDR_SURF_P4_16x16) |
2551                                                          SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2552                                         break;
2553                                 default:
2554                                         gb_tile_moden = 0;
2555                                         break;
2556                                 }
2557                                 rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden;
2558                                 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
2559                         }
2560                 } else if (num_rbs < 4) {
2561                         for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
2562                                 switch (reg_offset) {
2563                                 case 0:
2564                                         gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2565                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2566                                                          PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2567                                                          TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
2568                                         break;
2569                                 case 1:
2570                                         gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2571                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2572                                                          PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2573                                                          TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
2574                                         break;
2575                                 case 2:
2576                                         gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2577                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2578                                                          PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2579                                                          TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
2580                                         break;
2581                                 case 3:
2582                                         gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2583                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2584                                                          PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2585                                                          TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
2586                                         break;
2587                                 case 4:
2588                                         gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2589                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2590                                                          PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2591                                                          TILE_SPLIT(split_equal_to_row_size));
2592                                         break;
2593                                 case 5:
2594                                         gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2595                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2596                                         break;
2597                                 case 6:
2598                                         gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2599                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2600                                                          PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2601                                                          TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
2602                                         break;
2603                                 case 7:
2604                                         gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2605                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2606                                                          PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2607                                                          TILE_SPLIT(split_equal_to_row_size));
2608                                         break;
2609                                 case 8:
2610                                         gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
2611                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16));
2612                                         break;
2613                                 case 9:
2614                                         gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2615                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
2616                                         break;
2617                                 case 10:
2618                                         gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2619                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2620                                                          PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2621                                                          SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2622                                         break;
2623                                 case 11:
2624                                         gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2625                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2626                                                          PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2627                                                          SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2628                                         break;
2629                                 case 12:
2630                                         gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2631                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2632                                                          PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2633                                                          SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2634                                         break;
2635                                 case 13:
2636                                         gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2637                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
2638                                         break;
2639                                 case 14:
2640                                         gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2641                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2642                                                          PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2643                                                          SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2644                                         break;
2645                                 case 16:
2646                                         gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2647                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2648                                                          PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2649                                                          SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2650                                         break;
2651                                 case 17:
2652                                         gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2653                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2654                                                          PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2655                                                          SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2656                                         break;
2657                                 case 27:
2658                                         gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2659                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
2660                                         break;
2661                                 case 28:
2662                                         gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2663                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2664                                                          PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2665                                                          SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2666                                         break;
2667                                 case 29:
2668                                         gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2669                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2670                                                          PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2671                                                          SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2672                                         break;
2673                                 case 30:
2674                                         gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2675                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2676                                                          PIPE_CONFIG(ADDR_SURF_P4_8x16) |
2677                                                          SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2678                                         break;
2679                                 default:
2680                                         gb_tile_moden = 0;
2681                                         break;
2682                                 }
2683                                 rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden;
2684                                 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
2685                         }
2686                 }
2687                 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
2688                         switch (reg_offset) {
2689                         case 0:
2690                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2691                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2692                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2693                                                  NUM_BANKS(ADDR_SURF_16_BANK));
2694                                 break;
2695                         case 1:
2696                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2697                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2698                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2699                                                  NUM_BANKS(ADDR_SURF_16_BANK));
2700                                 break;
2701                         case 2:
2702                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2703                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2704                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2705                                                  NUM_BANKS(ADDR_SURF_16_BANK));
2706                                 break;
2707                         case 3:
2708                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2709                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2710                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2711                                                  NUM_BANKS(ADDR_SURF_16_BANK));
2712                                 break;
2713                         case 4:
2714                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2715                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2716                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2717                                                  NUM_BANKS(ADDR_SURF_16_BANK));
2718                                 break;
2719                         case 5:
2720                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2721                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2722                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2723                                                  NUM_BANKS(ADDR_SURF_8_BANK));
2724                                 break;
2725                         case 6:
2726                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2727                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2728                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2729                                                  NUM_BANKS(ADDR_SURF_4_BANK));
2730                                 break;
2731                         case 8:
2732                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2733                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2734                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2735                                                  NUM_BANKS(ADDR_SURF_16_BANK));
2736                                 break;
2737                         case 9:
2738                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2739                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2740                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2741                                                  NUM_BANKS(ADDR_SURF_16_BANK));
2742                                 break;
2743                         case 10:
2744                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2745                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2746                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2747                                                  NUM_BANKS(ADDR_SURF_16_BANK));
2748                                 break;
2749                         case 11:
2750                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2751                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2752                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2753                                                  NUM_BANKS(ADDR_SURF_16_BANK));
2754                                 break;
2755                         case 12:
2756                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2757                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2758                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2759                                                  NUM_BANKS(ADDR_SURF_16_BANK));
2760                                 break;
2761                         case 13:
2762                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2763                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2764                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2765                                                  NUM_BANKS(ADDR_SURF_8_BANK));
2766                                 break;
2767                         case 14:
2768                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2769                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2770                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
2771                                                  NUM_BANKS(ADDR_SURF_4_BANK));
2772                                 break;
2773                         default:
2774                                 gb_tile_moden = 0;
2775                                 break;
2776                         }
2777                         rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden;
2778                         WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden);
2779                 }
2780         } else if (num_pipe_configs == 2) {
2781                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
2782                         switch (reg_offset) {
2783                         case 0:
2784                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2785                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2786                                                  PIPE_CONFIG(ADDR_SURF_P2) |
2787                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
2788                                 break;
2789                         case 1:
2790                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2791                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2792                                                  PIPE_CONFIG(ADDR_SURF_P2) |
2793                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
2794                                 break;
2795                         case 2:
2796                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2797                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2798                                                  PIPE_CONFIG(ADDR_SURF_P2) |
2799                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
2800                                 break;
2801                         case 3:
2802                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2803                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2804                                                  PIPE_CONFIG(ADDR_SURF_P2) |
2805                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
2806                                 break;
2807                         case 4:
2808                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2809                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2810                                                  PIPE_CONFIG(ADDR_SURF_P2) |
2811                                                  TILE_SPLIT(split_equal_to_row_size));
2812                                 break;
2813                         case 5:
2814                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2815                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
2816                                 break;
2817                         case 6:
2818                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2819                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2820                                                  PIPE_CONFIG(ADDR_SURF_P2) |
2821                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
2822                                 break;
2823                         case 7:
2824                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2825                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
2826                                                  PIPE_CONFIG(ADDR_SURF_P2) |
2827                                                  TILE_SPLIT(split_equal_to_row_size));
2828                                 break;
2829                         case 8:
2830                                 gb_tile_moden = ARRAY_MODE(ARRAY_LINEAR_ALIGNED);
2831                                 break;
2832                         case 9:
2833                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2834                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
2835                                 break;
2836                         case 10:
2837                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2838                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2839                                                  PIPE_CONFIG(ADDR_SURF_P2) |
2840                                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2841                                 break;
2842                         case 11:
2843                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2844                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2845                                                  PIPE_CONFIG(ADDR_SURF_P2) |
2846                                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2847                                 break;
2848                         case 12:
2849                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2850                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
2851                                                  PIPE_CONFIG(ADDR_SURF_P2) |
2852                                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2853                                 break;
2854                         case 13:
2855                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2856                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
2857                                 break;
2858                         case 14:
2859                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
2860                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2861                                                  PIPE_CONFIG(ADDR_SURF_P2) |
2862                                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2863                                 break;
2864                         case 16:
2865                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2866                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2867                                                  PIPE_CONFIG(ADDR_SURF_P2) |
2868                                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2869                                 break;
2870                         case 17:
2871                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2872                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
2873                                                  PIPE_CONFIG(ADDR_SURF_P2) |
2874                                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2875                                 break;
2876                         case 27:
2877                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
2878                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
2879                                 break;
2880                         case 28:
2881                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2882                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2883                                                  PIPE_CONFIG(ADDR_SURF_P2) |
2884                                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2885                                 break;
2886                         case 29:
2887                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
2888                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2889                                                  PIPE_CONFIG(ADDR_SURF_P2) |
2890                                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2891                                 break;
2892                         case 30:
2893                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
2894                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
2895                                                  PIPE_CONFIG(ADDR_SURF_P2) |
2896                                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
2897                                 break;
2898                         default:
2899                                 gb_tile_moden = 0;
2900                                 break;
2901                         }
2902                         rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden;
2903                         WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
2904                 }
2905                 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
2906                         switch (reg_offset) {
2907                         case 0:
2908                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2909                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2910                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2911                                                  NUM_BANKS(ADDR_SURF_16_BANK));
2912                                 break;
2913                         case 1:
2914                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2915                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2916                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2917                                                  NUM_BANKS(ADDR_SURF_16_BANK));
2918                                 break;
2919                         case 2:
2920                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2921                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2922                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2923                                                  NUM_BANKS(ADDR_SURF_16_BANK));
2924                                 break;
2925                         case 3:
2926                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2927                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2928                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2929                                                  NUM_BANKS(ADDR_SURF_16_BANK));
2930                                 break;
2931                         case 4:
2932                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2933                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2934                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2935                                                  NUM_BANKS(ADDR_SURF_16_BANK));
2936                                 break;
2937                         case 5:
2938                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2939                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2940                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2941                                                  NUM_BANKS(ADDR_SURF_16_BANK));
2942                                 break;
2943                         case 6:
2944                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2945                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2946                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2947                                                  NUM_BANKS(ADDR_SURF_8_BANK));
2948                                 break;
2949                         case 8:
2950                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2951                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
2952                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2953                                                  NUM_BANKS(ADDR_SURF_16_BANK));
2954                                 break;
2955                         case 9:
2956                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
2957                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2958                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2959                                                  NUM_BANKS(ADDR_SURF_16_BANK));
2960                                 break;
2961                         case 10:
2962                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2963                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
2964                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2965                                                  NUM_BANKS(ADDR_SURF_16_BANK));
2966                                 break;
2967                         case 11:
2968                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
2969                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2970                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2971                                                  NUM_BANKS(ADDR_SURF_16_BANK));
2972                                 break;
2973                         case 12:
2974                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2975                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
2976                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2977                                                  NUM_BANKS(ADDR_SURF_16_BANK));
2978                                 break;
2979                         case 13:
2980                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2981                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2982                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
2983                                                  NUM_BANKS(ADDR_SURF_16_BANK));
2984                                 break;
2985                         case 14:
2986                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
2987                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
2988                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
2989                                                  NUM_BANKS(ADDR_SURF_8_BANK));
2990                                 break;
2991                         default:
2992                                 gb_tile_moden = 0;
2993                                 break;
2994                         }
2995                         rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden;
2996                         WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden);
2997                 }
2998         } else
2999                 DRM_ERROR("unknown num pipe config: 0x%x\n", num_pipe_configs);
3000 }
3001
3002 /**
3003  * cik_select_se_sh - select which SE, SH to address
3004  *
3005  * @rdev: radeon_device pointer
3006  * @se_num: shader engine to address
3007  * @sh_num: sh block to address
3008  *
3009  * Select which SE, SH combinations to address. Certain
3010  * registers are instanced per SE or SH.  0xffffffff means
3011  * broadcast to all SEs or SHs (CIK).
3012  */
3013 static void cik_select_se_sh(struct radeon_device *rdev,
3014                              u32 se_num, u32 sh_num)
3015 {
3016         u32 data = INSTANCE_BROADCAST_WRITES;
3017
3018         if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
3019                 data |= SH_BROADCAST_WRITES | SE_BROADCAST_WRITES;
3020         else if (se_num == 0xffffffff)
3021                 data |= SE_BROADCAST_WRITES | SH_INDEX(sh_num);
3022         else if (sh_num == 0xffffffff)
3023                 data |= SH_BROADCAST_WRITES | SE_INDEX(se_num);
3024         else
3025                 data |= SH_INDEX(sh_num) | SE_INDEX(se_num);
3026         WREG32(GRBM_GFX_INDEX, data);
3027 }
3028
3029 /**
3030  * cik_create_bitmask - create a bitmask
3031  *
3032  * @bit_width: length of the mask
3033  *
3034  * create a variable length bit mask (CIK).
3035  * Returns the bitmask.
3036  */
3037 static u32 cik_create_bitmask(u32 bit_width)
3038 {
3039         u32 i, mask = 0;
3040
3041         for (i = 0; i < bit_width; i++) {
3042                 mask <<= 1;
3043                 mask |= 1;
3044         }
3045         return mask;
3046 }
3047
3048 /**
3049  * cik_select_se_sh - select which SE, SH to address
3050  *
3051  * @rdev: radeon_device pointer
3052  * @max_rb_num: max RBs (render backends) for the asic
3053  * @se_num: number of SEs (shader engines) for the asic
3054  * @sh_per_se: number of SH blocks per SE for the asic
3055  *
3056  * Calculates the bitmask of disabled RBs (CIK).
3057  * Returns the disabled RB bitmask.
3058  */
3059 static u32 cik_get_rb_disabled(struct radeon_device *rdev,
3060                               u32 max_rb_num_per_se,
3061                               u32 sh_per_se)
3062 {
3063         u32 data, mask;
3064
3065         data = RREG32(CC_RB_BACKEND_DISABLE);
3066         if (data & 1)
3067                 data &= BACKEND_DISABLE_MASK;
3068         else
3069                 data = 0;
3070         data |= RREG32(GC_USER_RB_BACKEND_DISABLE);
3071
3072         data >>= BACKEND_DISABLE_SHIFT;
3073
3074         mask = cik_create_bitmask(max_rb_num_per_se / sh_per_se);
3075
3076         return data & mask;
3077 }
3078
3079 /**
3080  * cik_setup_rb - setup the RBs on the asic
3081  *
3082  * @rdev: radeon_device pointer
3083  * @se_num: number of SEs (shader engines) for the asic
3084  * @sh_per_se: number of SH blocks per SE for the asic
3085  * @max_rb_num: max RBs (render backends) for the asic
3086  *
3087  * Configures per-SE/SH RB registers (CIK).
3088  */
3089 static void cik_setup_rb(struct radeon_device *rdev,
3090                          u32 se_num, u32 sh_per_se,
3091                          u32 max_rb_num_per_se)
3092 {
3093         int i, j;
3094         u32 data, mask;
3095         u32 disabled_rbs = 0;
3096         u32 enabled_rbs = 0;
3097
3098         for (i = 0; i < se_num; i++) {
3099                 for (j = 0; j < sh_per_se; j++) {
3100                         cik_select_se_sh(rdev, i, j);
3101                         data = cik_get_rb_disabled(rdev, max_rb_num_per_se, sh_per_se);
3102                         if (rdev->family == CHIP_HAWAII)
3103                                 disabled_rbs |= data << ((i * sh_per_se + j) * HAWAII_RB_BITMAP_WIDTH_PER_SH);
3104                         else
3105                                 disabled_rbs |= data << ((i * sh_per_se + j) * CIK_RB_BITMAP_WIDTH_PER_SH);
3106                 }
3107         }
3108         cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
3109
3110         mask = 1;
3111         for (i = 0; i < max_rb_num_per_se * se_num; i++) {
3112                 if (!(disabled_rbs & mask))
3113                         enabled_rbs |= mask;
3114                 mask <<= 1;
3115         }
3116
3117         rdev->config.cik.backend_enable_mask = enabled_rbs;
3118
3119         for (i = 0; i < se_num; i++) {
3120                 cik_select_se_sh(rdev, i, 0xffffffff);
3121                 data = 0;
3122                 for (j = 0; j < sh_per_se; j++) {
3123                         switch (enabled_rbs & 3) {
3124                         case 0:
3125                                 if (j == 0)
3126                                         data |= PKR_MAP(RASTER_CONFIG_RB_MAP_3);
3127                                 else
3128                                         data |= PKR_MAP(RASTER_CONFIG_RB_MAP_0);
3129                                 break;
3130                         case 1:
3131                                 data |= (RASTER_CONFIG_RB_MAP_0 << (i * sh_per_se + j) * 2);
3132                                 break;
3133                         case 2:
3134                                 data |= (RASTER_CONFIG_RB_MAP_3 << (i * sh_per_se + j) * 2);
3135                                 break;
3136                         case 3:
3137                         default:
3138                                 data |= (RASTER_CONFIG_RB_MAP_2 << (i * sh_per_se + j) * 2);
3139                                 break;
3140                         }
3141                         enabled_rbs >>= 2;
3142                 }
3143                 WREG32(PA_SC_RASTER_CONFIG, data);
3144         }
3145         cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
3146 }
3147
3148 /**
3149  * cik_gpu_init - setup the 3D engine
3150  *
3151  * @rdev: radeon_device pointer
3152  *
3153  * Configures the 3D engine and tiling configuration
3154  * registers so that the 3D engine is usable.
3155  */
3156 static void cik_gpu_init(struct radeon_device *rdev)
3157 {
3158         u32 gb_addr_config = RREG32(GB_ADDR_CONFIG);
3159         u32 mc_shared_chmap, mc_arb_ramcfg;
3160         u32 hdp_host_path_cntl;
3161         u32 tmp;
3162         int i, j;
3163
3164         switch (rdev->family) {
3165         case CHIP_BONAIRE:
3166                 rdev->config.cik.max_shader_engines = 2;
3167                 rdev->config.cik.max_tile_pipes = 4;
3168                 rdev->config.cik.max_cu_per_sh = 7;
3169                 rdev->config.cik.max_sh_per_se = 1;
3170                 rdev->config.cik.max_backends_per_se = 2;
3171                 rdev->config.cik.max_texture_channel_caches = 4;
3172                 rdev->config.cik.max_gprs = 256;
3173                 rdev->config.cik.max_gs_threads = 32;
3174                 rdev->config.cik.max_hw_contexts = 8;
3175
3176                 rdev->config.cik.sc_prim_fifo_size_frontend = 0x20;
3177                 rdev->config.cik.sc_prim_fifo_size_backend = 0x100;
3178                 rdev->config.cik.sc_hiz_tile_fifo_size = 0x30;
3179                 rdev->config.cik.sc_earlyz_tile_fifo_size = 0x130;
3180                 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
3181                 break;
3182         case CHIP_HAWAII:
3183                 rdev->config.cik.max_shader_engines = 4;
3184                 rdev->config.cik.max_tile_pipes = 16;
3185                 rdev->config.cik.max_cu_per_sh = 11;
3186                 rdev->config.cik.max_sh_per_se = 1;
3187                 rdev->config.cik.max_backends_per_se = 4;
3188                 rdev->config.cik.max_texture_channel_caches = 16;
3189                 rdev->config.cik.max_gprs = 256;
3190                 rdev->config.cik.max_gs_threads = 32;
3191                 rdev->config.cik.max_hw_contexts = 8;
3192
3193                 rdev->config.cik.sc_prim_fifo_size_frontend = 0x20;
3194                 rdev->config.cik.sc_prim_fifo_size_backend = 0x100;
3195                 rdev->config.cik.sc_hiz_tile_fifo_size = 0x30;
3196                 rdev->config.cik.sc_earlyz_tile_fifo_size = 0x130;
3197                 gb_addr_config = HAWAII_GB_ADDR_CONFIG_GOLDEN;
3198                 break;
3199         case CHIP_KAVERI:
3200                 rdev->config.cik.max_shader_engines = 1;
3201                 rdev->config.cik.max_tile_pipes = 4;
3202                 if ((rdev->pdev->device == 0x1304) ||
3203                     (rdev->pdev->device == 0x1305) ||
3204                     (rdev->pdev->device == 0x130C) ||
3205                     (rdev->pdev->device == 0x130F) ||
3206                     (rdev->pdev->device == 0x1310) ||
3207                     (rdev->pdev->device == 0x1311) ||
3208                     (rdev->pdev->device == 0x131C)) {
3209                         rdev->config.cik.max_cu_per_sh = 8;
3210                         rdev->config.cik.max_backends_per_se = 2;
3211                 } else if ((rdev->pdev->device == 0x1309) ||
3212                            (rdev->pdev->device == 0x130A) ||
3213                            (rdev->pdev->device == 0x130D) ||
3214                            (rdev->pdev->device == 0x1313) ||
3215                            (rdev->pdev->device == 0x131D)) {
3216                         rdev->config.cik.max_cu_per_sh = 6;
3217                         rdev->config.cik.max_backends_per_se = 2;
3218                 } else if ((rdev->pdev->device == 0x1306) ||
3219                            (rdev->pdev->device == 0x1307) ||
3220                            (rdev->pdev->device == 0x130B) ||
3221                            (rdev->pdev->device == 0x130E) ||
3222                            (rdev->pdev->device == 0x1315) ||
3223                            (rdev->pdev->device == 0x131B)) {
3224                         rdev->config.cik.max_cu_per_sh = 4;
3225                         rdev->config.cik.max_backends_per_se = 1;
3226                 } else {
3227                         rdev->config.cik.max_cu_per_sh = 3;
3228                         rdev->config.cik.max_backends_per_se = 1;
3229                 }
3230                 rdev->config.cik.max_sh_per_se = 1;
3231                 rdev->config.cik.max_texture_channel_caches = 4;
3232                 rdev->config.cik.max_gprs = 256;
3233                 rdev->config.cik.max_gs_threads = 16;
3234                 rdev->config.cik.max_hw_contexts = 8;
3235
3236                 rdev->config.cik.sc_prim_fifo_size_frontend = 0x20;
3237                 rdev->config.cik.sc_prim_fifo_size_backend = 0x100;
3238                 rdev->config.cik.sc_hiz_tile_fifo_size = 0x30;
3239                 rdev->config.cik.sc_earlyz_tile_fifo_size = 0x130;
3240                 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
3241                 break;
3242         case CHIP_KABINI:
3243         default:
3244                 rdev->config.cik.max_shader_engines = 1;
3245                 rdev->config.cik.max_tile_pipes = 2;
3246                 rdev->config.cik.max_cu_per_sh = 2;
3247                 rdev->config.cik.max_sh_per_se = 1;
3248                 rdev->config.cik.max_backends_per_se = 1;
3249                 rdev->config.cik.max_texture_channel_caches = 2;
3250                 rdev->config.cik.max_gprs = 256;
3251                 rdev->config.cik.max_gs_threads = 16;
3252                 rdev->config.cik.max_hw_contexts = 8;
3253
3254                 rdev->config.cik.sc_prim_fifo_size_frontend = 0x20;
3255                 rdev->config.cik.sc_prim_fifo_size_backend = 0x100;
3256                 rdev->config.cik.sc_hiz_tile_fifo_size = 0x30;
3257                 rdev->config.cik.sc_earlyz_tile_fifo_size = 0x130;
3258                 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
3259                 break;
3260         }
3261
3262         /* Initialize HDP */
3263         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
3264                 WREG32((0x2c14 + j), 0x00000000);
3265                 WREG32((0x2c18 + j), 0x00000000);
3266                 WREG32((0x2c1c + j), 0x00000000);
3267                 WREG32((0x2c20 + j), 0x00000000);
3268                 WREG32((0x2c24 + j), 0x00000000);
3269         }
3270
3271         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
3272
3273         WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN);
3274
3275         mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
3276         mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
3277
3278         rdev->config.cik.num_tile_pipes = rdev->config.cik.max_tile_pipes;
3279         rdev->config.cik.mem_max_burst_length_bytes = 256;
3280         tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
3281         rdev->config.cik.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
3282         if (rdev->config.cik.mem_row_size_in_kb > 4)
3283                 rdev->config.cik.mem_row_size_in_kb = 4;
3284         /* XXX use MC settings? */
3285         rdev->config.cik.shader_engine_tile_size = 32;
3286         rdev->config.cik.num_gpus = 1;
3287         rdev->config.cik.multi_gpu_tile_size = 64;
3288
3289         /* fix up row size */
3290         gb_addr_config &= ~ROW_SIZE_MASK;
3291         switch (rdev->config.cik.mem_row_size_in_kb) {
3292         case 1:
3293         default:
3294                 gb_addr_config |= ROW_SIZE(0);
3295                 break;
3296         case 2:
3297                 gb_addr_config |= ROW_SIZE(1);
3298                 break;
3299         case 4:
3300                 gb_addr_config |= ROW_SIZE(2);
3301                 break;
3302         }
3303
3304         /* setup tiling info dword.  gb_addr_config is not adequate since it does
3305          * not have bank info, so create a custom tiling dword.
3306          * bits 3:0   num_pipes
3307          * bits 7:4   num_banks
3308          * bits 11:8  group_size
3309          * bits 15:12 row_size
3310          */
3311         rdev->config.cik.tile_config = 0;
3312         switch (rdev->config.cik.num_tile_pipes) {
3313         case 1:
3314                 rdev->config.cik.tile_config |= (0 << 0);
3315                 break;
3316         case 2:
3317                 rdev->config.cik.tile_config |= (1 << 0);
3318                 break;
3319         case 4:
3320                 rdev->config.cik.tile_config |= (2 << 0);
3321                 break;
3322         case 8:
3323         default:
3324                 /* XXX what about 12? */
3325                 rdev->config.cik.tile_config |= (3 << 0);
3326                 break;
3327         }
3328         rdev->config.cik.tile_config |=
3329                 ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4;
3330         rdev->config.cik.tile_config |=
3331                 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
3332         rdev->config.cik.tile_config |=
3333                 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;
3334
3335         WREG32(GB_ADDR_CONFIG, gb_addr_config);
3336         WREG32(HDP_ADDR_CONFIG, gb_addr_config);
3337         WREG32(DMIF_ADDR_CALC, gb_addr_config);
3338         WREG32(SDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET, gb_addr_config & 0x70);
3339         WREG32(SDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET, gb_addr_config & 0x70);
3340         WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config);
3341         WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
3342         WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
3343
3344         cik_tiling_mode_table_init(rdev);
3345
3346         cik_setup_rb(rdev, rdev->config.cik.max_shader_engines,
3347                      rdev->config.cik.max_sh_per_se,
3348                      rdev->config.cik.max_backends_per_se);
3349
3350         /* set HW defaults for 3D engine */
3351         WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
3352
3353         WREG32(SX_DEBUG_1, 0x20);
3354
3355         WREG32(TA_CNTL_AUX, 0x00010000);
3356
3357         tmp = RREG32(SPI_CONFIG_CNTL);
3358         tmp |= 0x03000000;
3359         WREG32(SPI_CONFIG_CNTL, tmp);
3360
3361         WREG32(SQ_CONFIG, 1);
3362
3363         WREG32(DB_DEBUG, 0);
3364
3365         tmp = RREG32(DB_DEBUG2) & ~0xf00fffff;
3366         tmp |= 0x00000400;
3367         WREG32(DB_DEBUG2, tmp);
3368
3369         tmp = RREG32(DB_DEBUG3) & ~0x0002021c;
3370         tmp |= 0x00020200;
3371         WREG32(DB_DEBUG3, tmp);
3372
3373         tmp = RREG32(CB_HW_CONTROL) & ~0x00010000;
3374         tmp |= 0x00018208;
3375         WREG32(CB_HW_CONTROL, tmp);
3376
3377         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
3378
3379         WREG32(PA_SC_FIFO_SIZE, (SC_FRONTEND_PRIM_FIFO_SIZE(rdev->config.cik.sc_prim_fifo_size_frontend) |
3380                                  SC_BACKEND_PRIM_FIFO_SIZE(rdev->config.cik.sc_prim_fifo_size_backend) |
3381                                  SC_HIZ_TILE_FIFO_SIZE(rdev->config.cik.sc_hiz_tile_fifo_size) |
3382                                  SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.cik.sc_earlyz_tile_fifo_size)));
3383
3384         WREG32(VGT_NUM_INSTANCES, 1);
3385
3386         WREG32(CP_PERFMON_CNTL, 0);
3387
3388         WREG32(SQ_CONFIG, 0);
3389
3390         WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
3391                                           FORCE_EOV_MAX_REZ_CNT(255)));
3392
3393         WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |
3394                AUTO_INVLD_EN(ES_AND_GS_AUTO));
3395
3396         WREG32(VGT_GS_VERTEX_REUSE, 16);
3397         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
3398
3399         tmp = RREG32(HDP_MISC_CNTL);
3400         tmp |= HDP_FLUSH_INVALIDATE_CACHE;
3401         WREG32(HDP_MISC_CNTL, tmp);
3402
3403         hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
3404         WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
3405
3406         WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
3407         WREG32(PA_SC_ENHANCE, ENABLE_PA_SC_OUT_OF_ORDER);
3408
3409         udelay(50);
3410 }
3411
3412 /*
3413  * GPU scratch registers helpers function.
3414  */
3415 /**
3416  * cik_scratch_init - setup driver info for CP scratch regs
3417  *
3418  * @rdev: radeon_device pointer
3419  *
3420  * Set up the number and offset of the CP scratch registers.
3421  * NOTE: use of CP scratch registers is a legacy inferface and
3422  * is not used by default on newer asics (r6xx+).  On newer asics,
3423  * memory buffers are used for fences rather than scratch regs.
3424  */
3425 static void cik_scratch_init(struct radeon_device *rdev)
3426 {
3427         int i;
3428
3429         rdev->scratch.num_reg = 7;
3430         rdev->scratch.reg_base = SCRATCH_REG0;
3431         for (i = 0; i < rdev->scratch.num_reg; i++) {
3432                 rdev->scratch.free[i] = true;
3433                 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
3434         }
3435 }
3436
3437 /**
3438  * cik_ring_test - basic gfx ring test
3439  *
3440  * @rdev: radeon_device pointer
3441  * @ring: radeon_ring structure holding ring information
3442  *
3443  * Allocate a scratch register and write to it using the gfx ring (CIK).
3444  * Provides a basic gfx ring test to verify that the ring is working.
3445  * Used by cik_cp_gfx_resume();
3446  * Returns 0 on success, error on failure.
3447  */
3448 int cik_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
3449 {
3450         uint32_t scratch;
3451         uint32_t tmp = 0;
3452         unsigned i;
3453         int r;
3454
3455         r = radeon_scratch_get(rdev, &scratch);
3456         if (r) {
3457                 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3458                 return r;
3459         }
3460         WREG32(scratch, 0xCAFEDEAD);
3461         r = radeon_ring_lock(rdev, ring, 3);
3462         if (r) {
3463                 DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", ring->idx, r);
3464                 radeon_scratch_free(rdev, scratch);
3465                 return r;
3466         }
3467         radeon_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
3468         radeon_ring_write(ring, ((scratch - PACKET3_SET_UCONFIG_REG_START) >> 2));
3469         radeon_ring_write(ring, 0xDEADBEEF);
3470         radeon_ring_unlock_commit(rdev, ring);
3471
3472         for (i = 0; i < rdev->usec_timeout; i++) {
3473                 tmp = RREG32(scratch);
3474                 if (tmp == 0xDEADBEEF)
3475                         break;
3476                 DRM_UDELAY(1);
3477         }
3478         if (i < rdev->usec_timeout) {
3479                 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
3480         } else {
3481                 DRM_ERROR("radeon: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
3482                           ring->idx, scratch, tmp);
3483                 r = -EINVAL;
3484         }
3485         radeon_scratch_free(rdev, scratch);
3486         return r;
3487 }
3488
3489 /**
3490  * cik_hdp_flush_cp_ring_emit - emit an hdp flush on the cp
3491  *
3492  * @rdev: radeon_device pointer
3493  * @ridx: radeon ring index
3494  *
3495  * Emits an hdp flush on the cp.
3496  */
3497 static void cik_hdp_flush_cp_ring_emit(struct radeon_device *rdev,
3498                                        int ridx)
3499 {
3500         struct radeon_ring *ring = &rdev->ring[ridx];
3501         u32 ref_and_mask;
3502
3503         switch (ring->idx) {
3504         case CAYMAN_RING_TYPE_CP1_INDEX:
3505         case CAYMAN_RING_TYPE_CP2_INDEX:
3506         default:
3507                 switch (ring->me) {
3508                 case 0:
3509                         ref_and_mask = CP2 << ring->pipe;
3510                         break;
3511                 case 1:
3512                         ref_and_mask = CP6 << ring->pipe;
3513                         break;
3514                 default:
3515                         return;
3516                 }
3517                 break;
3518         case RADEON_RING_TYPE_GFX_INDEX:
3519                 ref_and_mask = CP0;
3520                 break;
3521         }
3522
3523         radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3524         radeon_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */
3525                                  WAIT_REG_MEM_FUNCTION(3) |  /* == */
3526                                  WAIT_REG_MEM_ENGINE(1)));   /* pfp */
3527         radeon_ring_write(ring, GPU_HDP_FLUSH_REQ >> 2);
3528         radeon_ring_write(ring, GPU_HDP_FLUSH_DONE >> 2);
3529         radeon_ring_write(ring, ref_and_mask);
3530         radeon_ring_write(ring, ref_and_mask);
3531         radeon_ring_write(ring, 0x20); /* poll interval */
3532 }
3533
3534 /**
3535  * cik_fence_gfx_ring_emit - emit a fence on the gfx ring
3536  *
3537  * @rdev: radeon_device pointer
3538  * @fence: radeon fence object
3539  *
3540  * Emits a fence sequnce number on the gfx ring and flushes
3541  * GPU caches.
3542  */
3543 void cik_fence_gfx_ring_emit(struct radeon_device *rdev,
3544                              struct radeon_fence *fence)
3545 {
3546         struct radeon_ring *ring = &rdev->ring[fence->ring];
3547         u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
3548
3549         /* EVENT_WRITE_EOP - flush caches, send int */
3550         radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
3551         radeon_ring_write(ring, (EOP_TCL1_ACTION_EN |
3552                                  EOP_TC_ACTION_EN |
3553                                  EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
3554                                  EVENT_INDEX(5)));
3555         radeon_ring_write(ring, addr & 0xfffffffc);
3556         radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) | DATA_SEL(1) | INT_SEL(2));
3557         radeon_ring_write(ring, fence->seq);
3558         radeon_ring_write(ring, 0);
3559         /* HDP flush */
3560         cik_hdp_flush_cp_ring_emit(rdev, fence->ring);
3561 }
3562
3563 /**
3564  * cik_fence_compute_ring_emit - emit a fence on the compute ring
3565  *
3566  * @rdev: radeon_device pointer
3567  * @fence: radeon fence object
3568  *
3569  * Emits a fence sequnce number on the compute ring and flushes
3570  * GPU caches.
3571  */
3572 void cik_fence_compute_ring_emit(struct radeon_device *rdev,
3573                                  struct radeon_fence *fence)
3574 {
3575         struct radeon_ring *ring = &rdev->ring[fence->ring];
3576         u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
3577
3578         /* RELEASE_MEM - flush caches, send int */
3579         radeon_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5));
3580         radeon_ring_write(ring, (EOP_TCL1_ACTION_EN |
3581                                  EOP_TC_ACTION_EN |
3582                                  EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
3583                                  EVENT_INDEX(5)));
3584         radeon_ring_write(ring, DATA_SEL(1) | INT_SEL(2));
3585         radeon_ring_write(ring, addr & 0xfffffffc);
3586         radeon_ring_write(ring, upper_32_bits(addr));
3587         radeon_ring_write(ring, fence->seq);
3588         radeon_ring_write(ring, 0);
3589         /* HDP flush */
3590         cik_hdp_flush_cp_ring_emit(rdev, fence->ring);
3591 }
3592
3593 bool cik_semaphore_ring_emit(struct radeon_device *rdev,
3594                              struct radeon_ring *ring,
3595                              struct radeon_semaphore *semaphore,
3596                              bool emit_wait)
3597 {
3598         uint64_t addr = semaphore->gpu_addr;
3599         unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL;
3600
3601         radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1));
3602         radeon_ring_write(ring, addr & 0xffffffff);
3603         radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) | sel);
3604
3605         return true;
3606 }
3607
3608 /**
3609  * cik_copy_cpdma - copy pages using the CP DMA engine
3610  *
3611  * @rdev: radeon_device pointer
3612  * @src_offset: src GPU address
3613  * @dst_offset: dst GPU address
3614  * @num_gpu_pages: number of GPU pages to xfer
3615  * @fence: radeon fence object
3616  *
3617  * Copy GPU paging using the CP DMA engine (CIK+).
3618  * Used by the radeon ttm implementation to move pages if
3619  * registered as the asic copy callback.
3620  */
3621 int cik_copy_cpdma(struct radeon_device *rdev,
3622                    uint64_t src_offset, uint64_t dst_offset,
3623                    unsigned num_gpu_pages,
3624                    struct radeon_fence **fence)
3625 {
3626         struct radeon_semaphore *sem = NULL;
3627         int ring_index = rdev->asic->copy.blit_ring_index;
3628         struct radeon_ring *ring = &rdev->ring[ring_index];
3629         u32 size_in_bytes, cur_size_in_bytes, control;
3630         int i, num_loops;
3631         int r = 0;
3632
3633         r = radeon_semaphore_create(rdev, &sem);
3634         if (r) {
3635                 DRM_ERROR("radeon: moving bo (%d).\n", r);
3636                 return r;
3637         }
3638
3639         size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT);
3640         num_loops = DIV_ROUND_UP(size_in_bytes, 0x1fffff);
3641         r = radeon_ring_lock(rdev, ring, num_loops * 7 + 18);
3642         if (r) {
3643                 DRM_ERROR("radeon: moving bo (%d).\n", r);
3644                 radeon_semaphore_free(rdev, &sem, NULL);
3645                 return r;
3646         }
3647
3648         radeon_semaphore_sync_to(sem, *fence);
3649         radeon_semaphore_sync_rings(rdev, sem, ring->idx);
3650
3651         for (i = 0; i < num_loops; i++) {
3652                 cur_size_in_bytes = size_in_bytes;
3653                 if (cur_size_in_bytes > 0x1fffff)
3654                         cur_size_in_bytes = 0x1fffff;
3655                 size_in_bytes -= cur_size_in_bytes;
3656                 control = 0;
3657                 if (size_in_bytes == 0)
3658                         control |= PACKET3_DMA_DATA_CP_SYNC;
3659                 radeon_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5));
3660                 radeon_ring_write(ring, control);
3661                 radeon_ring_write(ring, lower_32_bits(src_offset));
3662                 radeon_ring_write(ring, upper_32_bits(src_offset));
3663                 radeon_ring_write(ring, lower_32_bits(dst_offset));
3664                 radeon_ring_write(ring, upper_32_bits(dst_offset));
3665                 radeon_ring_write(ring, cur_size_in_bytes);
3666                 src_offset += cur_size_in_bytes;
3667                 dst_offset += cur_size_in_bytes;
3668         }
3669
3670         r = radeon_fence_emit(rdev, fence, ring->idx);
3671         if (r) {
3672                 radeon_ring_unlock_undo(rdev, ring);
3673                 return r;
3674         }
3675
3676         radeon_ring_unlock_commit(rdev, ring);
3677         radeon_semaphore_free(rdev, &sem, *fence);
3678
3679         return r;
3680 }
3681
3682 /*
3683  * IB stuff
3684  */
3685 /**
3686  * cik_ring_ib_execute - emit an IB (Indirect Buffer) on the gfx ring
3687  *
3688  * @rdev: radeon_device pointer
3689  * @ib: radeon indirect buffer object
3690  *
3691  * Emits an DE (drawing engine) or CE (constant engine) IB
3692  * on the gfx ring.  IBs are usually generated by userspace
3693  * acceleration drivers and submitted to the kernel for
3694  * sheduling on the ring.  This function schedules the IB
3695  * on the gfx ring for execution by the GPU.
3696  */
3697 void cik_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3698 {
3699         struct radeon_ring *ring = &rdev->ring[ib->ring];
3700         u32 header, control = INDIRECT_BUFFER_VALID;
3701
3702         if (ib->is_const_ib) {
3703                 /* set switch buffer packet before const IB */
3704                 radeon_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
3705                 radeon_ring_write(ring, 0);
3706
3707                 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
3708         } else {
3709                 u32 next_rptr;
3710                 if (ring->rptr_save_reg) {
3711                         next_rptr = ring->wptr + 3 + 4;
3712                         radeon_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
3713                         radeon_ring_write(ring, ((ring->rptr_save_reg -
3714                                                   PACKET3_SET_UCONFIG_REG_START) >> 2));
3715                         radeon_ring_write(ring, next_rptr);
3716                 } else if (rdev->wb.enabled) {
3717                         next_rptr = ring->wptr + 5 + 4;
3718                         radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3719                         radeon_ring_write(ring, WRITE_DATA_DST_SEL(1));
3720                         radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
3721                         radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
3722                         radeon_ring_write(ring, next_rptr);
3723                 }
3724
3725                 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
3726         }
3727
3728         control |= ib->length_dw |
3729                 (ib->vm ? (ib->vm->id << 24) : 0);
3730
3731         radeon_ring_write(ring, header);
3732         radeon_ring_write(ring,
3733 #ifdef __BIG_ENDIAN
3734                           (2 << 0) |
3735 #endif
3736                           (ib->gpu_addr & 0xFFFFFFFC));
3737         radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
3738         radeon_ring_write(ring, control);
3739 }
3740
3741 /**
3742  * cik_ib_test - basic gfx ring IB test
3743  *
3744  * @rdev: radeon_device pointer
3745  * @ring: radeon_ring structure holding ring information
3746  *
3747  * Allocate an IB and execute it on the gfx ring (CIK).
3748  * Provides a basic gfx ring test to verify that IBs are working.
3749  * Returns 0 on success, error on failure.
3750  */
3751 int cik_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3752 {
3753         struct radeon_ib ib;
3754         uint32_t scratch;
3755         uint32_t tmp = 0;
3756         unsigned i;
3757         int r;
3758
3759         r = radeon_scratch_get(rdev, &scratch);
3760         if (r) {
3761                 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3762                 return r;
3763         }
3764         WREG32(scratch, 0xCAFEDEAD);
3765         r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
3766         if (r) {
3767                 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
3768                 radeon_scratch_free(rdev, scratch);
3769                 return r;
3770         }
3771         ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
3772         ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START) >> 2);
3773         ib.ptr[2] = 0xDEADBEEF;
3774         ib.length_dw = 3;
3775         r = radeon_ib_schedule(rdev, &ib, NULL);
3776         if (r) {
3777                 radeon_scratch_free(rdev, scratch);
3778                 radeon_ib_free(rdev, &ib);
3779                 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
3780                 return r;
3781         }
3782         r = radeon_fence_wait(ib.fence, false);
3783         if (r) {
3784                 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
3785                 radeon_scratch_free(rdev, scratch);
3786                 radeon_ib_free(rdev, &ib);
3787                 return r;
3788         }
3789         for (i = 0; i < rdev->usec_timeout; i++) {
3790                 tmp = RREG32(scratch);
3791                 if (tmp == 0xDEADBEEF)
3792                         break;
3793                 DRM_UDELAY(1);
3794         }
3795         if (i < rdev->usec_timeout) {
3796                 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i);
3797         } else {
3798                 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3799                           scratch, tmp);
3800                 r = -EINVAL;
3801         }
3802         radeon_scratch_free(rdev, scratch);
3803         radeon_ib_free(rdev, &ib);
3804         return r;
3805 }
3806
3807 /*
3808  * CP.
3809  * On CIK, gfx and compute now have independant command processors.
3810  *
3811  * GFX
3812  * Gfx consists of a single ring and can process both gfx jobs and
3813  * compute jobs.  The gfx CP consists of three microengines (ME):
3814  * PFP - Pre-Fetch Parser
3815  * ME - Micro Engine
3816  * CE - Constant Engine
3817  * The PFP and ME make up what is considered the Drawing Engine (DE).
3818  * The CE is an asynchronous engine used for updating buffer desciptors
3819  * used by the DE so that they can be loaded into cache in parallel
3820  * while the DE is processing state update packets.
3821  *
3822  * Compute
3823  * The compute CP consists of two microengines (ME):
3824  * MEC1 - Compute MicroEngine 1
3825  * MEC2 - Compute MicroEngine 2
3826  * Each MEC supports 4 compute pipes and each pipe supports 8 queues.
3827  * The queues are exposed to userspace and are programmed directly
3828  * by the compute runtime.
3829  */
3830 /**
3831  * cik_cp_gfx_enable - enable/disable the gfx CP MEs
3832  *
3833  * @rdev: radeon_device pointer
3834  * @enable: enable or disable the MEs
3835  *
3836  * Halts or unhalts the gfx MEs.
3837  */
3838 static void cik_cp_gfx_enable(struct radeon_device *rdev, bool enable)
3839 {
3840         if (enable)
3841                 WREG32(CP_ME_CNTL, 0);
3842         else {
3843                 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT));
3844                 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
3845         }
3846         udelay(50);
3847 }
3848
3849 /**
3850  * cik_cp_gfx_load_microcode - load the gfx CP ME ucode
3851  *
3852  * @rdev: radeon_device pointer
3853  *
3854  * Loads the gfx PFP, ME, and CE ucode.
3855  * Returns 0 for success, -EINVAL if the ucode is not available.
3856  */
3857 static int cik_cp_gfx_load_microcode(struct radeon_device *rdev)
3858 {
3859         const __be32 *fw_data;
3860         int i;
3861
3862         if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw)
3863                 return -EINVAL;
3864
3865         cik_cp_gfx_enable(rdev, false);
3866
3867         /* PFP */
3868         fw_data = (const __be32 *)rdev->pfp_fw->data;
3869         WREG32(CP_PFP_UCODE_ADDR, 0);
3870         for (i = 0; i < CIK_PFP_UCODE_SIZE; i++)
3871                 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
3872         WREG32(CP_PFP_UCODE_ADDR, 0);
3873
3874         /* CE */
3875         fw_data = (const __be32 *)rdev->ce_fw->data;
3876         WREG32(CP_CE_UCODE_ADDR, 0);
3877         for (i = 0; i < CIK_CE_UCODE_SIZE; i++)
3878                 WREG32(CP_CE_UCODE_DATA, be32_to_cpup(fw_data++));
3879         WREG32(CP_CE_UCODE_ADDR, 0);
3880
3881         /* ME */
3882         fw_data = (const __be32 *)rdev->me_fw->data;
3883         WREG32(CP_ME_RAM_WADDR, 0);
3884         for (i = 0; i < CIK_ME_UCODE_SIZE; i++)
3885                 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
3886         WREG32(CP_ME_RAM_WADDR, 0);
3887
3888         WREG32(CP_PFP_UCODE_ADDR, 0);
3889         WREG32(CP_CE_UCODE_ADDR, 0);
3890         WREG32(CP_ME_RAM_WADDR, 0);
3891         WREG32(CP_ME_RAM_RADDR, 0);
3892         return 0;
3893 }
3894
3895 /**
3896  * cik_cp_gfx_start - start the gfx ring
3897  *
3898  * @rdev: radeon_device pointer
3899  *
3900  * Enables the ring and loads the clear state context and other
3901  * packets required to init the ring.
3902  * Returns 0 for success, error for failure.
3903  */
3904 static int cik_cp_gfx_start(struct radeon_device *rdev)
3905 {
3906         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3907         int r, i;
3908
3909         /* init the CP */
3910         WREG32(CP_MAX_CONTEXT, rdev->config.cik.max_hw_contexts - 1);
3911         WREG32(CP_ENDIAN_SWAP, 0);
3912         WREG32(CP_DEVICE_ID, 1);
3913
3914         cik_cp_gfx_enable(rdev, true);
3915
3916         r = radeon_ring_lock(rdev, ring, cik_default_size + 17);
3917         if (r) {
3918                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3919                 return r;
3920         }
3921
3922         /* init the CE partitions.  CE only used for gfx on CIK */
3923         radeon_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
3924         radeon_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
3925         radeon_ring_write(ring, 0xc000);
3926         radeon_ring_write(ring, 0xc000);
3927
3928         /* setup clear context state */
3929         radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3930         radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
3931
3932         radeon_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
3933         radeon_ring_write(ring, 0x80000000);
3934         radeon_ring_write(ring, 0x80000000);
3935
3936         for (i = 0; i < cik_default_size; i++)
3937                 radeon_ring_write(ring, cik_default_state[i]);
3938
3939         radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3940         radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
3941
3942         /* set clear context state */
3943         radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
3944         radeon_ring_write(ring, 0);
3945
3946         radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
3947         radeon_ring_write(ring, 0x00000316);
3948         radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
3949         radeon_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */
3950
3951         radeon_ring_unlock_commit(rdev, ring);
3952
3953         return 0;
3954 }
3955
3956 /**
3957  * cik_cp_gfx_fini - stop the gfx ring
3958  *
3959  * @rdev: radeon_device pointer
3960  *
3961  * Stop the gfx ring and tear down the driver ring
3962  * info.
3963  */
3964 static void cik_cp_gfx_fini(struct radeon_device *rdev)
3965 {
3966         cik_cp_gfx_enable(rdev, false);
3967         radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
3968 }
3969
3970 /**
3971  * cik_cp_gfx_resume - setup the gfx ring buffer registers
3972  *
3973  * @rdev: radeon_device pointer
3974  *
3975  * Program the location and size of the gfx ring buffer
3976  * and test it to make sure it's working.
3977  * Returns 0 for success, error for failure.
3978  */
3979 static int cik_cp_gfx_resume(struct radeon_device *rdev)
3980 {
3981         struct radeon_ring *ring;
3982         u32 tmp;
3983         u32 rb_bufsz;
3984         u64 rb_addr;
3985         int r;
3986
3987         WREG32(CP_SEM_WAIT_TIMER, 0x0);
3988         if (rdev->family != CHIP_HAWAII)
3989                 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
3990
3991         /* Set the write pointer delay */
3992         WREG32(CP_RB_WPTR_DELAY, 0);
3993
3994         /* set the RB to use vmid 0 */
3995         WREG32(CP_RB_VMID, 0);
3996
3997         WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
3998
3999         /* ring 0 - compute and gfx */
4000         /* Set ring buffer size */
4001         ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
4002         rb_bufsz = order_base_2(ring->ring_size / 8);
4003         tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
4004 #ifdef __BIG_ENDIAN
4005         tmp |= BUF_SWAP_32BIT;
4006 #endif
4007         WREG32(CP_RB0_CNTL, tmp);
4008
4009         /* Initialize the ring buffer's read and write pointers */
4010         WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA);
4011         ring->wptr = 0;
4012         WREG32(CP_RB0_WPTR, ring->wptr);
4013
4014         /* set the wb address wether it's enabled or not */
4015         WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);
4016         WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
4017
4018         /* scratch register shadowing is no longer supported */
4019         WREG32(SCRATCH_UMSK, 0);
4020
4021         if (!rdev->wb.enabled)
4022                 tmp |= RB_NO_UPDATE;
4023
4024         mdelay(1);
4025         WREG32(CP_RB0_CNTL, tmp);
4026
4027         rb_addr = ring->gpu_addr >> 8;
4028         WREG32(CP_RB0_BASE, rb_addr);
4029         WREG32(CP_RB0_BASE_HI, upper_32_bits(rb_addr));
4030
4031         ring->rptr = RREG32(CP_RB0_RPTR);
4032
4033         /* start the ring */
4034         cik_cp_gfx_start(rdev);
4035         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true;
4036         r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
4037         if (r) {
4038                 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
4039                 return r;
4040         }
4041         return 0;
4042 }
4043
4044 u32 cik_gfx_get_rptr(struct radeon_device *rdev,
4045                      struct radeon_ring *ring)
4046 {
4047         u32 rptr;
4048
4049         if (rdev->wb.enabled)
4050                 rptr = rdev->wb.wb[ring->rptr_offs/4];
4051         else
4052                 rptr = RREG32(CP_RB0_RPTR);
4053
4054         return rptr;
4055 }
4056
4057 u32 cik_gfx_get_wptr(struct radeon_device *rdev,
4058                      struct radeon_ring *ring)
4059 {
4060         u32 wptr;
4061
4062         wptr = RREG32(CP_RB0_WPTR);
4063
4064         return wptr;
4065 }
4066
4067 void cik_gfx_set_wptr(struct radeon_device *rdev,
4068                       struct radeon_ring *ring)
4069 {
4070         WREG32(CP_RB0_WPTR, ring->wptr);
4071         (void)RREG32(CP_RB0_WPTR);
4072 }
4073
4074 u32 cik_compute_get_rptr(struct radeon_device *rdev,
4075                          struct radeon_ring *ring)
4076 {
4077         u32 rptr;
4078
4079         if (rdev->wb.enabled) {
4080                 rptr = rdev->wb.wb[ring->rptr_offs/4];
4081         } else {
4082                 mutex_lock(&rdev->srbm_mutex);
4083                 cik_srbm_select(rdev, ring->me, ring->pipe, ring->queue, 0);
4084                 rptr = RREG32(CP_HQD_PQ_RPTR);
4085                 cik_srbm_select(rdev, 0, 0, 0, 0);
4086                 mutex_unlock(&rdev->srbm_mutex);
4087         }
4088
4089         return rptr;
4090 }
4091
4092 u32 cik_compute_get_wptr(struct radeon_device *rdev,
4093                          struct radeon_ring *ring)
4094 {
4095         u32 wptr;
4096
4097         if (rdev->wb.enabled) {
4098                 /* XXX check if swapping is necessary on BE */
4099                 wptr = rdev->wb.wb[ring->wptr_offs/4];
4100         } else {
4101                 mutex_lock(&rdev->srbm_mutex);
4102                 cik_srbm_select(rdev, ring->me, ring->pipe, ring->queue, 0);
4103                 wptr = RREG32(CP_HQD_PQ_WPTR);
4104                 cik_srbm_select(rdev, 0, 0, 0, 0);
4105                 mutex_unlock(&rdev->srbm_mutex);
4106         }
4107
4108         return wptr;
4109 }
4110
4111 void cik_compute_set_wptr(struct radeon_device *rdev,
4112                           struct radeon_ring *ring)
4113 {
4114         /* XXX check if swapping is necessary on BE */
4115         rdev->wb.wb[ring->wptr_offs/4] = ring->wptr;
4116         WDOORBELL32(ring->doorbell_index, ring->wptr);
4117 }
4118
4119 /**
4120  * cik_cp_compute_enable - enable/disable the compute CP MEs
4121  *
4122  * @rdev: radeon_device pointer
4123  * @enable: enable or disable the MEs
4124  *
4125  * Halts or unhalts the compute MEs.
4126  */
4127 static void cik_cp_compute_enable(struct radeon_device *rdev, bool enable)
4128 {
4129         if (enable)
4130                 WREG32(CP_MEC_CNTL, 0);
4131         else
4132                 WREG32(CP_MEC_CNTL, (MEC_ME1_HALT | MEC_ME2_HALT));
4133         udelay(50);
4134 }
4135
4136 /**
4137  * cik_cp_compute_load_microcode - load the compute CP ME ucode
4138  *
4139  * @rdev: radeon_device pointer
4140  *
4141  * Loads the compute MEC1&2 ucode.
4142  * Returns 0 for success, -EINVAL if the ucode is not available.
4143  */
4144 static int cik_cp_compute_load_microcode(struct radeon_device *rdev)
4145 {
4146         const __be32 *fw_data;
4147         int i;
4148
4149         if (!rdev->mec_fw)
4150                 return -EINVAL;
4151
4152         cik_cp_compute_enable(rdev, false);
4153
4154         /* MEC1 */
4155         fw_data = (const __be32 *)rdev->mec_fw->data;
4156         WREG32(CP_MEC_ME1_UCODE_ADDR, 0);
4157         for (i = 0; i < CIK_MEC_UCODE_SIZE; i++)
4158                 WREG32(CP_MEC_ME1_UCODE_DATA, be32_to_cpup(fw_data++));
4159         WREG32(CP_MEC_ME1_UCODE_ADDR, 0);
4160
4161         if (rdev->family == CHIP_KAVERI) {
4162                 /* MEC2 */
4163                 fw_data = (const __be32 *)rdev->mec_fw->data;
4164                 WREG32(CP_MEC_ME2_UCODE_ADDR, 0);
4165                 for (i = 0; i < CIK_MEC_UCODE_SIZE; i++)
4166                         WREG32(CP_MEC_ME2_UCODE_DATA, be32_to_cpup(fw_data++));
4167                 WREG32(CP_MEC_ME2_UCODE_ADDR, 0);
4168         }
4169
4170         return 0;
4171 }
4172
4173 /**
4174  * cik_cp_compute_start - start the compute queues
4175  *
4176  * @rdev: radeon_device pointer
4177  *
4178  * Enable the compute queues.
4179  * Returns 0 for success, error for failure.
4180  */
4181 static int cik_cp_compute_start(struct radeon_device *rdev)
4182 {
4183         cik_cp_compute_enable(rdev, true);
4184
4185         return 0;
4186 }
4187
4188 /**
4189  * cik_cp_compute_fini - stop the compute queues
4190  *
4191  * @rdev: radeon_device pointer
4192  *
4193  * Stop the compute queues and tear down the driver queue
4194  * info.
4195  */
4196 static void cik_cp_compute_fini(struct radeon_device *rdev)
4197 {
4198         int i, idx, r;
4199
4200         cik_cp_compute_enable(rdev, false);
4201
4202         for (i = 0; i < 2; i++) {
4203                 if (i == 0)
4204                         idx = CAYMAN_RING_TYPE_CP1_INDEX;
4205                 else
4206                         idx = CAYMAN_RING_TYPE_CP2_INDEX;
4207
4208                 if (rdev->ring[idx].mqd_obj) {
4209                         r = radeon_bo_reserve(rdev->ring[idx].mqd_obj, false);
4210                         if (unlikely(r != 0))
4211                                 dev_warn(rdev->dev, "(%d) reserve MQD bo failed\n", r);
4212
4213                         radeon_bo_unpin(rdev->ring[idx].mqd_obj);
4214                         radeon_bo_unreserve(rdev->ring[idx].mqd_obj);
4215
4216                         radeon_bo_unref(&rdev->ring[idx].mqd_obj);
4217                         rdev->ring[idx].mqd_obj = NULL;
4218                 }
4219         }
4220 }
4221
4222 static void cik_mec_fini(struct radeon_device *rdev)
4223 {
4224         int r;
4225
4226         if (rdev->mec.hpd_eop_obj) {
4227                 r = radeon_bo_reserve(rdev->mec.hpd_eop_obj, false);
4228                 if (unlikely(r != 0))
4229                         dev_warn(rdev->dev, "(%d) reserve HPD EOP bo failed\n", r);
4230                 radeon_bo_unpin(rdev->mec.hpd_eop_obj);
4231                 radeon_bo_unreserve(rdev->mec.hpd_eop_obj);
4232
4233                 radeon_bo_unref(&rdev->mec.hpd_eop_obj);
4234                 rdev->mec.hpd_eop_obj = NULL;
4235         }
4236 }
4237
4238 #define MEC_HPD_SIZE 2048
4239
4240 static int cik_mec_init(struct radeon_device *rdev)
4241 {
4242         int r;
4243         u32 *hpd;
4244
4245         /*
4246          * KV:    2 MEC, 4 Pipes/MEC, 8 Queues/Pipe - 64 Queues total
4247          * CI/KB: 1 MEC, 4 Pipes/MEC, 8 Queues/Pipe - 32 Queues total
4248          */
4249         if (rdev->family == CHIP_KAVERI)
4250                 rdev->mec.num_mec = 2;
4251         else
4252                 rdev->mec.num_mec = 1;
4253         rdev->mec.num_pipe = 4;
4254         rdev->mec.num_queue = rdev->mec.num_mec * rdev->mec.num_pipe * 8;
4255
4256         if (rdev->mec.hpd_eop_obj == NULL) {
4257                 r = radeon_bo_create(rdev,
4258                                      rdev->mec.num_mec *rdev->mec.num_pipe * MEC_HPD_SIZE * 2,
4259                                      PAGE_SIZE, true,
4260                                      RADEON_GEM_DOMAIN_GTT, NULL,
4261                                      &rdev->mec.hpd_eop_obj);
4262                 if (r) {
4263                         dev_warn(rdev->dev, "(%d) create HDP EOP bo failed\n", r);
4264                         return r;
4265                 }
4266         }
4267
4268         r = radeon_bo_reserve(rdev->mec.hpd_eop_obj, false);
4269         if (unlikely(r != 0)) {
4270                 cik_mec_fini(rdev);
4271                 return r;
4272         }
4273         r = radeon_bo_pin(rdev->mec.hpd_eop_obj, RADEON_GEM_DOMAIN_GTT,
4274                           &rdev->mec.hpd_eop_gpu_addr);
4275         if (r) {
4276                 dev_warn(rdev->dev, "(%d) pin HDP EOP bo failed\n", r);
4277                 cik_mec_fini(rdev);
4278                 return r;
4279         }
4280         r = radeon_bo_kmap(rdev->mec.hpd_eop_obj, (void **)&hpd);
4281         if (r) {
4282                 dev_warn(rdev->dev, "(%d) map HDP EOP bo failed\n", r);
4283                 cik_mec_fini(rdev);
4284                 return r;
4285         }
4286
4287         /* clear memory.  Not sure if this is required or not */
4288         memset(hpd, 0, rdev->mec.num_mec *rdev->mec.num_pipe * MEC_HPD_SIZE * 2);
4289
4290         radeon_bo_kunmap(rdev->mec.hpd_eop_obj);
4291         radeon_bo_unreserve(rdev->mec.hpd_eop_obj);
4292
4293         return 0;
4294 }
4295
4296 struct hqd_registers
4297 {
4298         u32 cp_mqd_base_addr;
4299         u32 cp_mqd_base_addr_hi;
4300         u32 cp_hqd_active;
4301         u32 cp_hqd_vmid;
4302         u32 cp_hqd_persistent_state;
4303         u32 cp_hqd_pipe_priority;
4304         u32 cp_hqd_queue_priority;
4305         u32 cp_hqd_quantum;
4306         u32 cp_hqd_pq_base;
4307         u32 cp_hqd_pq_base_hi;
4308         u32 cp_hqd_pq_rptr;
4309         u32 cp_hqd_pq_rptr_report_addr;
4310         u32 cp_hqd_pq_rptr_report_addr_hi;
4311         u32 cp_hqd_pq_wptr_poll_addr;
4312         u32 cp_hqd_pq_wptr_poll_addr_hi;
4313         u32 cp_hqd_pq_doorbell_control;
4314         u32 cp_hqd_pq_wptr;
4315         u32 cp_hqd_pq_control;
4316         u32 cp_hqd_ib_base_addr;
4317         u32 cp_hqd_ib_base_addr_hi;
4318         u32 cp_hqd_ib_rptr;
4319         u32 cp_hqd_ib_control;
4320         u32 cp_hqd_iq_timer;
4321         u32 cp_hqd_iq_rptr;
4322         u32 cp_hqd_dequeue_request;
4323         u32 cp_hqd_dma_offload;
4324         u32 cp_hqd_sema_cmd;
4325         u32 cp_hqd_msg_type;
4326         u32 cp_hqd_atomic0_preop_lo;
4327         u32 cp_hqd_atomic0_preop_hi;
4328         u32 cp_hqd_atomic1_preop_lo;
4329         u32 cp_hqd_atomic1_preop_hi;
4330         u32 cp_hqd_hq_scheduler0;
4331         u32 cp_hqd_hq_scheduler1;
4332         u32 cp_mqd_control;
4333 };
4334
4335 struct bonaire_mqd
4336 {
4337         u32 header;
4338         u32 dispatch_initiator;
4339         u32 dimensions[3];
4340         u32 start_idx[3];
4341         u32 num_threads[3];
4342         u32 pipeline_stat_enable;
4343         u32 perf_counter_enable;
4344         u32 pgm[2];
4345         u32 tba[2];
4346         u32 tma[2];
4347         u32 pgm_rsrc[2];
4348         u32 vmid;
4349         u32 resource_limits;
4350         u32 static_thread_mgmt01[2];
4351         u32 tmp_ring_size;
4352         u32 static_thread_mgmt23[2];
4353         u32 restart[3];
4354         u32 thread_trace_enable;
4355         u32 reserved1;
4356         u32 user_data[16];
4357         u32 vgtcs_invoke_count[2];
4358         struct hqd_registers queue_state;
4359         u32 dequeue_cntr;
4360         u32 interrupt_queue[64];
4361 };
4362
4363 /**
4364  * cik_cp_compute_resume - setup the compute queue registers
4365  *
4366  * @rdev: radeon_device pointer
4367  *
4368  * Program the compute queues and test them to make sure they
4369  * are working.
4370  * Returns 0 for success, error for failure.
4371  */
4372 static int cik_cp_compute_resume(struct radeon_device *rdev)
4373 {
4374         int r, i, idx;
4375         u32 tmp;
4376         bool use_doorbell = true;
4377         u64 hqd_gpu_addr;
4378         u64 mqd_gpu_addr;
4379         u64 eop_gpu_addr;
4380         u64 wb_gpu_addr;
4381         u32 *buf;
4382         struct bonaire_mqd *mqd;
4383
4384         r = cik_cp_compute_start(rdev);
4385         if (r)
4386                 return r;
4387
4388         /* fix up chicken bits */
4389         tmp = RREG32(CP_CPF_DEBUG);
4390         tmp |= (1 << 23);
4391         WREG32(CP_CPF_DEBUG, tmp);
4392
4393         /* init the pipes */
4394         mutex_lock(&rdev->srbm_mutex);
4395         for (i = 0; i < (rdev->mec.num_pipe * rdev->mec.num_mec); i++) {
4396                 int me = (i < 4) ? 1 : 2;
4397                 int pipe = (i < 4) ? i : (i - 4);
4398
4399                 eop_gpu_addr = rdev->mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE * 2);
4400
4401                 cik_srbm_select(rdev, me, pipe, 0, 0);
4402
4403                 /* write the EOP addr */
4404                 WREG32(CP_HPD_EOP_BASE_ADDR, eop_gpu_addr >> 8);
4405                 WREG32(CP_HPD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr) >> 8);
4406
4407                 /* set the VMID assigned */
4408                 WREG32(CP_HPD_EOP_VMID, 0);
4409
4410                 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
4411                 tmp = RREG32(CP_HPD_EOP_CONTROL);
4412                 tmp &= ~EOP_SIZE_MASK;
4413                 tmp |= order_base_2(MEC_HPD_SIZE / 8);
4414                 WREG32(CP_HPD_EOP_CONTROL, tmp);
4415         }
4416         cik_srbm_select(rdev, 0, 0, 0, 0);
4417         mutex_unlock(&rdev->srbm_mutex);
4418
4419         /* init the queues.  Just two for now. */
4420         for (i = 0; i < 2; i++) {
4421                 if (i == 0)
4422                         idx = CAYMAN_RING_TYPE_CP1_INDEX;
4423                 else
4424                         idx = CAYMAN_RING_TYPE_CP2_INDEX;
4425
4426                 if (rdev->ring[idx].mqd_obj == NULL) {
4427                         r = radeon_bo_create(rdev,
4428                                              sizeof(struct bonaire_mqd),
4429                                              PAGE_SIZE, true,
4430                                              RADEON_GEM_DOMAIN_GTT, NULL,
4431                                              &rdev->ring[idx].mqd_obj);
4432                         if (r) {
4433                                 dev_warn(rdev->dev, "(%d) create MQD bo failed\n", r);
4434                                 return r;
4435                         }
4436                 }
4437
4438                 r = radeon_bo_reserve(rdev->ring[idx].mqd_obj, false);
4439                 if (unlikely(r != 0)) {
4440                         cik_cp_compute_fini(rdev);
4441                         return r;
4442                 }
4443                 r = radeon_bo_pin(rdev->ring[idx].mqd_obj, RADEON_GEM_DOMAIN_GTT,
4444                                   &mqd_gpu_addr);
4445                 if (r) {
4446                         dev_warn(rdev->dev, "(%d) pin MQD bo failed\n", r);
4447                         cik_cp_compute_fini(rdev);
4448                         return r;
4449                 }
4450                 r = radeon_bo_kmap(rdev->ring[idx].mqd_obj, (void **)&buf);
4451                 if (r) {
4452                         dev_warn(rdev->dev, "(%d) map MQD bo failed\n", r);
4453                         cik_cp_compute_fini(rdev);
4454                         return r;
4455                 }
4456
4457                 /* init the mqd struct */
4458                 memset(buf, 0, sizeof(struct bonaire_mqd));
4459
4460                 mqd = (struct bonaire_mqd *)buf;
4461                 mqd->header = 0xC0310800;
4462                 mqd->static_thread_mgmt01[0] = 0xffffffff;
4463                 mqd->static_thread_mgmt01[1] = 0xffffffff;
4464                 mqd->static_thread_mgmt23[0] = 0xffffffff;
4465                 mqd->static_thread_mgmt23[1] = 0xffffffff;
4466
4467                 mutex_lock(&rdev->srbm_mutex);
4468                 cik_srbm_select(rdev, rdev->ring[idx].me,
4469                                 rdev->ring[idx].pipe,
4470                                 rdev->ring[idx].queue, 0);
4471
4472                 /* disable wptr polling */
4473                 tmp = RREG32(CP_PQ_WPTR_POLL_CNTL);
4474                 tmp &= ~WPTR_POLL_EN;
4475                 WREG32(CP_PQ_WPTR_POLL_CNTL, tmp);
4476
4477                 /* enable doorbell? */
4478                 mqd->queue_state.cp_hqd_pq_doorbell_control =
4479                         RREG32(CP_HQD_PQ_DOORBELL_CONTROL);
4480                 if (use_doorbell)
4481                         mqd->queue_state.cp_hqd_pq_doorbell_control |= DOORBELL_EN;
4482                 else
4483                         mqd->queue_state.cp_hqd_pq_doorbell_control &= ~DOORBELL_EN;
4484                 WREG32(CP_HQD_PQ_DOORBELL_CONTROL,
4485                        mqd->queue_state.cp_hqd_pq_doorbell_control);
4486
4487                 /* disable the queue if it's active */
4488                 mqd->queue_state.cp_hqd_dequeue_request = 0;
4489                 mqd->queue_state.cp_hqd_pq_rptr = 0;
4490                 mqd->queue_state.cp_hqd_pq_wptr= 0;
4491                 if (RREG32(CP_HQD_ACTIVE) & 1) {
4492                         WREG32(CP_HQD_DEQUEUE_REQUEST, 1);
4493                         for (i = 0; i < rdev->usec_timeout; i++) {
4494                                 if (!(RREG32(CP_HQD_ACTIVE) & 1))
4495                                         break;
4496                                 udelay(1);
4497                         }
4498                         WREG32(CP_HQD_DEQUEUE_REQUEST, mqd->queue_state.cp_hqd_dequeue_request);
4499                         WREG32(CP_HQD_PQ_RPTR, mqd->queue_state.cp_hqd_pq_rptr);
4500                         WREG32(CP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr);
4501                 }
4502
4503                 /* set the pointer to the MQD */
4504                 mqd->queue_state.cp_mqd_base_addr = mqd_gpu_addr & 0xfffffffc;
4505                 mqd->queue_state.cp_mqd_base_addr_hi = upper_32_bits(mqd_gpu_addr);
4506                 WREG32(CP_MQD_BASE_ADDR, mqd->queue_state.cp_mqd_base_addr);
4507                 WREG32(CP_MQD_BASE_ADDR_HI, mqd->queue_state.cp_mqd_base_addr_hi);
4508                 /* set MQD vmid to 0 */
4509                 mqd->queue_state.cp_mqd_control = RREG32(CP_MQD_CONTROL);
4510                 mqd->queue_state.cp_mqd_control &= ~MQD_VMID_MASK;
4511                 WREG32(CP_MQD_CONTROL, mqd->queue_state.cp_mqd_control);
4512
4513                 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
4514                 hqd_gpu_addr = rdev->ring[idx].gpu_addr >> 8;
4515                 mqd->queue_state.cp_hqd_pq_base = hqd_gpu_addr;
4516                 mqd->queue_state.cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
4517                 WREG32(CP_HQD_PQ_BASE, mqd->queue_state.cp_hqd_pq_base);
4518                 WREG32(CP_HQD_PQ_BASE_HI, mqd->queue_state.cp_hqd_pq_base_hi);
4519
4520                 /* set up the HQD, this is similar to CP_RB0_CNTL */
4521                 mqd->queue_state.cp_hqd_pq_control = RREG32(CP_HQD_PQ_CONTROL);
4522                 mqd->queue_state.cp_hqd_pq_control &=
4523                         ~(QUEUE_SIZE_MASK | RPTR_BLOCK_SIZE_MASK);
4524
4525                 mqd->queue_state.cp_hqd_pq_control |=
4526                         order_base_2(rdev->ring[idx].ring_size / 8);
4527                 mqd->queue_state.cp_hqd_pq_control |=
4528                         (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8);
4529 #ifdef __BIG_ENDIAN
4530                 mqd->queue_state.cp_hqd_pq_control |= BUF_SWAP_32BIT;
4531 #endif
4532                 mqd->queue_state.cp_hqd_pq_control &=
4533                         ~(UNORD_DISPATCH | ROQ_PQ_IB_FLIP | PQ_VOLATILE);
4534                 mqd->queue_state.cp_hqd_pq_control |=
4535                         PRIV_STATE | KMD_QUEUE; /* assuming kernel queue control */
4536                 WREG32(CP_HQD_PQ_CONTROL, mqd->queue_state.cp_hqd_pq_control);
4537
4538                 /* only used if CP_PQ_WPTR_POLL_CNTL.WPTR_POLL_EN=1 */
4539                 if (i == 0)
4540                         wb_gpu_addr = rdev->wb.gpu_addr + CIK_WB_CP1_WPTR_OFFSET;
4541                 else
4542                         wb_gpu_addr = rdev->wb.gpu_addr + CIK_WB_CP2_WPTR_OFFSET;
4543                 mqd->queue_state.cp_hqd_pq_wptr_poll_addr = wb_gpu_addr & 0xfffffffc;
4544                 mqd->queue_state.cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
4545                 WREG32(CP_HQD_PQ_WPTR_POLL_ADDR, mqd->queue_state.cp_hqd_pq_wptr_poll_addr);
4546                 WREG32(CP_HQD_PQ_WPTR_POLL_ADDR_HI,
4547                        mqd->queue_state.cp_hqd_pq_wptr_poll_addr_hi);
4548
4549                 /* set the wb address wether it's enabled or not */
4550                 if (i == 0)
4551                         wb_gpu_addr = rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET;
4552                 else
4553                         wb_gpu_addr = rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET;
4554                 mqd->queue_state.cp_hqd_pq_rptr_report_addr = wb_gpu_addr & 0xfffffffc;
4555                 mqd->queue_state.cp_hqd_pq_rptr_report_addr_hi =
4556                         upper_32_bits(wb_gpu_addr) & 0xffff;
4557                 WREG32(CP_HQD_PQ_RPTR_REPORT_ADDR,
4558                        mqd->queue_state.cp_hqd_pq_rptr_report_addr);
4559                 WREG32(CP_HQD_PQ_RPTR_REPORT_ADDR_HI,
4560                        mqd->queue_state.cp_hqd_pq_rptr_report_addr_hi);
4561
4562                 /* enable the doorbell if requested */
4563                 if (use_doorbell) {
4564                         mqd->queue_state.cp_hqd_pq_doorbell_control =
4565                                 RREG32(CP_HQD_PQ_DOORBELL_CONTROL);
4566                         mqd->queue_state.cp_hqd_pq_doorbell_control &= ~DOORBELL_OFFSET_MASK;
4567                         mqd->queue_state.cp_hqd_pq_doorbell_control |=
4568                                 DOORBELL_OFFSET(rdev->ring[idx].doorbell_index);
4569                         mqd->queue_state.cp_hqd_pq_doorbell_control |= DOORBELL_EN;
4570                         mqd->queue_state.cp_hqd_pq_doorbell_control &=
4571                                 ~(DOORBELL_SOURCE | DOORBELL_HIT);
4572
4573                 } else {
4574                         mqd->queue_state.cp_hqd_pq_doorbell_control = 0;
4575                 }
4576                 WREG32(CP_HQD_PQ_DOORBELL_CONTROL,
4577                        mqd->queue_state.cp_hqd_pq_doorbell_control);
4578
4579                 /* read and write pointers, similar to CP_RB0_WPTR/_RPTR */
4580                 rdev->ring[idx].wptr = 0;
4581                 mqd->queue_state.cp_hqd_pq_wptr = rdev->ring[idx].wptr;
4582                 WREG32(CP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr);
4583                 rdev->ring[idx].rptr = RREG32(CP_HQD_PQ_RPTR);
4584                 mqd->queue_state.cp_hqd_pq_rptr = rdev->ring[idx].rptr;
4585
4586                 /* set the vmid for the queue */
4587                 mqd->queue_state.cp_hqd_vmid = 0;
4588                 WREG32(CP_HQD_VMID, mqd->queue_state.cp_hqd_vmid);
4589
4590                 /* activate the queue */
4591                 mqd->queue_state.cp_hqd_active = 1;
4592                 WREG32(CP_HQD_ACTIVE, mqd->queue_state.cp_hqd_active);
4593
4594                 cik_srbm_select(rdev, 0, 0, 0, 0);
4595                 mutex_unlock(&rdev->srbm_mutex);
4596
4597                 radeon_bo_kunmap(rdev->ring[idx].mqd_obj);
4598                 radeon_bo_unreserve(rdev->ring[idx].mqd_obj);
4599
4600                 rdev->ring[idx].ready = true;
4601                 r = radeon_ring_test(rdev, idx, &rdev->ring[idx]);
4602                 if (r)
4603                         rdev->ring[idx].ready = false;
4604         }
4605
4606         return 0;
4607 }
4608
4609 static void cik_cp_enable(struct radeon_device *rdev, bool enable)
4610 {
4611         cik_cp_gfx_enable(rdev, enable);
4612         cik_cp_compute_enable(rdev, enable);
4613 }
4614
4615 static int cik_cp_load_microcode(struct radeon_device *rdev)
4616 {
4617         int r;
4618
4619         r = cik_cp_gfx_load_microcode(rdev);
4620         if (r)
4621                 return r;
4622         r = cik_cp_compute_load_microcode(rdev);
4623         if (r)
4624                 return r;
4625
4626         return 0;
4627 }
4628
4629 static void cik_cp_fini(struct radeon_device *rdev)
4630 {
4631         cik_cp_gfx_fini(rdev);
4632         cik_cp_compute_fini(rdev);
4633 }
4634
4635 static int cik_cp_resume(struct radeon_device *rdev)
4636 {
4637         int r;
4638
4639         cik_enable_gui_idle_interrupt(rdev, false);
4640
4641         r = cik_cp_load_microcode(rdev);
4642         if (r)
4643                 return r;
4644
4645         r = cik_cp_gfx_resume(rdev);
4646         if (r)
4647                 return r;
4648         r = cik_cp_compute_resume(rdev);
4649         if (r)
4650                 return r;
4651
4652         cik_enable_gui_idle_interrupt(rdev, true);
4653
4654         return 0;
4655 }
4656
4657 static void cik_print_gpu_status_regs(struct radeon_device *rdev)
4658 {
4659         dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",
4660                 RREG32(GRBM_STATUS));
4661         dev_info(rdev->dev, "  GRBM_STATUS2=0x%08X\n",
4662                 RREG32(GRBM_STATUS2));
4663         dev_info(rdev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
4664                 RREG32(GRBM_STATUS_SE0));
4665         dev_info(rdev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
4666                 RREG32(GRBM_STATUS_SE1));
4667         dev_info(rdev->dev, "  GRBM_STATUS_SE2=0x%08X\n",
4668                 RREG32(GRBM_STATUS_SE2));
4669         dev_info(rdev->dev, "  GRBM_STATUS_SE3=0x%08X\n",
4670                 RREG32(GRBM_STATUS_SE3));
4671         dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
4672                 RREG32(SRBM_STATUS));
4673         dev_info(rdev->dev, "  SRBM_STATUS2=0x%08X\n",
4674                 RREG32(SRBM_STATUS2));
4675         dev_info(rdev->dev, "  SDMA0_STATUS_REG   = 0x%08X\n",
4676                 RREG32(SDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET));
4677         dev_info(rdev->dev, "  SDMA1_STATUS_REG   = 0x%08X\n",
4678                  RREG32(SDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET));
4679         dev_info(rdev->dev, "  CP_STAT = 0x%08x\n", RREG32(CP_STAT));
4680         dev_info(rdev->dev, "  CP_STALLED_STAT1 = 0x%08x\n",
4681                  RREG32(CP_STALLED_STAT1));
4682         dev_info(rdev->dev, "  CP_STALLED_STAT2 = 0x%08x\n",
4683                  RREG32(CP_STALLED_STAT2));
4684         dev_info(rdev->dev, "  CP_STALLED_STAT3 = 0x%08x\n",
4685                  RREG32(CP_STALLED_STAT3));
4686         dev_info(rdev->dev, "  CP_CPF_BUSY_STAT = 0x%08x\n",
4687                  RREG32(CP_CPF_BUSY_STAT));
4688         dev_info(rdev->dev, "  CP_CPF_STALLED_STAT1 = 0x%08x\n",
4689                  RREG32(CP_CPF_STALLED_STAT1));
4690         dev_info(rdev->dev, "  CP_CPF_STATUS = 0x%08x\n", RREG32(CP_CPF_STATUS));
4691         dev_info(rdev->dev, "  CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(CP_CPC_BUSY_STAT));
4692         dev_info(rdev->dev, "  CP_CPC_STALLED_STAT1 = 0x%08x\n",
4693                  RREG32(CP_CPC_STALLED_STAT1));
4694         dev_info(rdev->dev, "  CP_CPC_STATUS = 0x%08x\n", RREG32(CP_CPC_STATUS));
4695 }
4696
4697 /**
4698  * cik_gpu_check_soft_reset - check which blocks are busy
4699  *
4700  * @rdev: radeon_device pointer
4701  *
4702  * Check which blocks are busy and return the relevant reset
4703  * mask to be used by cik_gpu_soft_reset().
4704  * Returns a mask of the blocks to be reset.
4705  */
4706 u32 cik_gpu_check_soft_reset(struct radeon_device *rdev)
4707 {
4708         u32 reset_mask = 0;
4709         u32 tmp;
4710
4711         /* GRBM_STATUS */
4712         tmp = RREG32(GRBM_STATUS);
4713         if (tmp & (PA_BUSY | SC_BUSY |
4714                    BCI_BUSY | SX_BUSY |
4715                    TA_BUSY | VGT_BUSY |
4716                    DB_BUSY | CB_BUSY |
4717                    GDS_BUSY | SPI_BUSY |
4718                    IA_BUSY | IA_BUSY_NO_DMA))
4719                 reset_mask |= RADEON_RESET_GFX;
4720
4721         if (tmp & (CP_BUSY | CP_COHERENCY_BUSY))
4722                 reset_mask |= RADEON_RESET_CP;
4723
4724         /* GRBM_STATUS2 */
4725         tmp = RREG32(GRBM_STATUS2);
4726         if (tmp & RLC_BUSY)
4727                 reset_mask |= RADEON_RESET_RLC;
4728
4729         /* SDMA0_STATUS_REG */
4730         tmp = RREG32(SDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET);
4731         if (!(tmp & SDMA_IDLE))
4732                 reset_mask |= RADEON_RESET_DMA;
4733
4734         /* SDMA1_STATUS_REG */
4735         tmp = RREG32(SDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET);
4736         if (!(tmp & SDMA_IDLE))
4737                 reset_mask |= RADEON_RESET_DMA1;
4738
4739         /* SRBM_STATUS2 */
4740         tmp = RREG32(SRBM_STATUS2);
4741         if (tmp & SDMA_BUSY)
4742                 reset_mask |= RADEON_RESET_DMA;
4743
4744         if (tmp & SDMA1_BUSY)
4745                 reset_mask |= RADEON_RESET_DMA1;
4746
4747         /* SRBM_STATUS */
4748         tmp = RREG32(SRBM_STATUS);
4749
4750         if (tmp & IH_BUSY)
4751                 reset_mask |= RADEON_RESET_IH;
4752
4753         if (tmp & SEM_BUSY)
4754                 reset_mask |= RADEON_RESET_SEM;
4755
4756         if (tmp & GRBM_RQ_PENDING)
4757                 reset_mask |= RADEON_RESET_GRBM;
4758
4759         if (tmp & VMC_BUSY)
4760                 reset_mask |= RADEON_RESET_VMC;
4761
4762         if (tmp & (MCB_BUSY | MCB_NON_DISPLAY_BUSY |
4763                    MCC_BUSY | MCD_BUSY))
4764                 reset_mask |= RADEON_RESET_MC;
4765
4766         if (evergreen_is_display_hung(rdev))
4767                 reset_mask |= RADEON_RESET_DISPLAY;
4768
4769         /* Skip MC reset as it's mostly likely not hung, just busy */
4770         if (reset_mask & RADEON_RESET_MC) {
4771                 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);
4772                 reset_mask &= ~RADEON_RESET_MC;
4773         }
4774
4775         return reset_mask;
4776 }
4777
4778 /**
4779  * cik_gpu_soft_reset - soft reset GPU
4780  *
4781  * @rdev: radeon_device pointer
4782  * @reset_mask: mask of which blocks to reset
4783  *
4784  * Soft reset the blocks specified in @reset_mask.
4785  */
4786 static void cik_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
4787 {
4788         struct evergreen_mc_save save;
4789         u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
4790         u32 tmp;
4791
4792         if (reset_mask == 0)
4793                 return;
4794
4795         dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
4796
4797         cik_print_gpu_status_regs(rdev);
4798         dev_info(rdev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
4799                  RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR));
4800         dev_info(rdev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
4801                  RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS));
4802
4803         /* disable CG/PG */
4804         cik_fini_pg(rdev);
4805         cik_fini_cg(rdev);
4806
4807         /* stop the rlc */
4808         cik_rlc_stop(rdev);
4809
4810         /* Disable GFX parsing/prefetching */
4811         WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);
4812
4813         /* Disable MEC parsing/prefetching */
4814         WREG32(CP_MEC_CNTL, MEC_ME1_HALT | MEC_ME2_HALT);
4815
4816         if (reset_mask & RADEON_RESET_DMA) {
4817                 /* sdma0 */
4818                 tmp = RREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET);
4819                 tmp |= SDMA_HALT;
4820                 WREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET, tmp);
4821         }
4822         if (reset_mask & RADEON_RESET_DMA1) {
4823                 /* sdma1 */
4824                 tmp = RREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET);
4825                 tmp |= SDMA_HALT;
4826                 WREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET, tmp);
4827         }
4828
4829         evergreen_mc_stop(rdev, &save);
4830         if (evergreen_mc_wait_for_idle(rdev)) {
4831                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
4832         }
4833
4834         if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE | RADEON_RESET_CP))
4835                 grbm_soft_reset = SOFT_RESET_CP | SOFT_RESET_GFX;
4836
4837         if (reset_mask & RADEON_RESET_CP) {
4838                 grbm_soft_reset |= SOFT_RESET_CP;
4839
4840                 srbm_soft_reset |= SOFT_RESET_GRBM;
4841         }
4842
4843         if (reset_mask & RADEON_RESET_DMA)
4844                 srbm_soft_reset |= SOFT_RESET_SDMA;
4845
4846         if (reset_mask & RADEON_RESET_DMA1)
4847                 srbm_soft_reset |= SOFT_RESET_SDMA1;
4848
4849         if (reset_mask & RADEON_RESET_DISPLAY)
4850                 srbm_soft_reset |= SOFT_RESET_DC;
4851
4852         if (reset_mask & RADEON_RESET_RLC)
4853                 grbm_soft_reset |= SOFT_RESET_RLC;
4854
4855         if (reset_mask & RADEON_RESET_SEM)
4856                 srbm_soft_reset |= SOFT_RESET_SEM;
4857
4858         if (reset_mask & RADEON_RESET_IH)
4859                 srbm_soft_reset |= SOFT_RESET_IH;
4860
4861         if (reset_mask & RADEON_RESET_GRBM)
4862                 srbm_soft_reset |= SOFT_RESET_GRBM;
4863
4864         if (reset_mask & RADEON_RESET_VMC)
4865                 srbm_soft_reset |= SOFT_RESET_VMC;
4866
4867         if (!(rdev->flags & RADEON_IS_IGP)) {
4868                 if (reset_mask & RADEON_RESET_MC)
4869                         srbm_soft_reset |= SOFT_RESET_MC;
4870         }
4871
4872         if (grbm_soft_reset) {
4873                 tmp = RREG32(GRBM_SOFT_RESET);
4874                 tmp |= grbm_soft_reset;
4875                 dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
4876                 WREG32(GRBM_SOFT_RESET, tmp);
4877                 tmp = RREG32(GRBM_SOFT_RESET);
4878
4879                 udelay(50);
4880
4881                 tmp &= ~grbm_soft_reset;
4882                 WREG32(GRBM_SOFT_RESET, tmp);
4883                 tmp = RREG32(GRBM_SOFT_RESET);
4884         }
4885
4886         if (srbm_soft_reset) {
4887                 tmp = RREG32(SRBM_SOFT_RESET);
4888                 tmp |= srbm_soft_reset;
4889                 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
4890                 WREG32(SRBM_SOFT_RESET, tmp);
4891                 tmp = RREG32(SRBM_SOFT_RESET);
4892
4893                 udelay(50);
4894
4895                 tmp &= ~srbm_soft_reset;
4896                 WREG32(SRBM_SOFT_RESET, tmp);
4897                 tmp = RREG32(SRBM_SOFT_RESET);
4898         }
4899
4900         /* Wait a little for things to settle down */
4901         udelay(50);
4902
4903         evergreen_mc_resume(rdev, &save);
4904         udelay(50);
4905
4906         cik_print_gpu_status_regs(rdev);
4907 }
4908
4909 struct kv_reset_save_regs {
4910         u32 gmcon_reng_execute;
4911         u32 gmcon_misc;
4912         u32 gmcon_misc3;
4913 };
4914
4915 static void kv_save_regs_for_reset(struct radeon_device *rdev,
4916                                    struct kv_reset_save_regs *save)
4917 {
4918         save->gmcon_reng_execute = RREG32(GMCON_RENG_EXECUTE);
4919         save->gmcon_misc = RREG32(GMCON_MISC);
4920         save->gmcon_misc3 = RREG32(GMCON_MISC3);
4921
4922         WREG32(GMCON_RENG_EXECUTE, save->gmcon_reng_execute & ~RENG_EXECUTE_ON_PWR_UP);
4923         WREG32(GMCON_MISC, save->gmcon_misc & ~(RENG_EXECUTE_ON_REG_UPDATE |
4924                                                 STCTRL_STUTTER_EN));
4925 }
4926
4927 static void kv_restore_regs_for_reset(struct radeon_device *rdev,
4928                                       struct kv_reset_save_regs *save)
4929 {
4930         int i;
4931
4932         WREG32(GMCON_PGFSM_WRITE, 0);
4933         WREG32(GMCON_PGFSM_CONFIG, 0x200010ff);
4934
4935         for (i = 0; i < 5; i++)
4936                 WREG32(GMCON_PGFSM_WRITE, 0);
4937
4938         WREG32(GMCON_PGFSM_WRITE, 0);
4939         WREG32(GMCON_PGFSM_CONFIG, 0x300010ff);
4940
4941         for (i = 0; i < 5; i++)
4942                 WREG32(GMCON_PGFSM_WRITE, 0);
4943
4944         WREG32(GMCON_PGFSM_WRITE, 0x210000);
4945         WREG32(GMCON_PGFSM_CONFIG, 0xa00010ff);
4946
4947         for (i = 0; i < 5; i++)
4948                 WREG32(GMCON_PGFSM_WRITE, 0);
4949
4950         WREG32(GMCON_PGFSM_WRITE, 0x21003);
4951         WREG32(GMCON_PGFSM_CONFIG, 0xb00010ff);
4952
4953         for (i = 0; i < 5; i++)
4954                 WREG32(GMCON_PGFSM_WRITE, 0);
4955
4956         WREG32(GMCON_PGFSM_WRITE, 0x2b00);
4957         WREG32(GMCON_PGFSM_CONFIG, 0xc00010ff);
4958
4959         for (i = 0; i < 5; i++)
4960                 WREG32(GMCON_PGFSM_WRITE, 0);
4961
4962         WREG32(GMCON_PGFSM_WRITE, 0);
4963         WREG32(GMCON_PGFSM_CONFIG, 0xd00010ff);
4964
4965         for (i = 0; i < 5; i++)
4966                 WREG32(GMCON_PGFSM_WRITE, 0);
4967
4968         WREG32(GMCON_PGFSM_WRITE, 0x420000);
4969         WREG32(GMCON_PGFSM_CONFIG, 0x100010ff);
4970
4971         for (i = 0; i < 5; i++)
4972                 WREG32(GMCON_PGFSM_WRITE, 0);
4973
4974         WREG32(GMCON_PGFSM_WRITE, 0x120202);
4975         WREG32(GMCON_PGFSM_CONFIG, 0x500010ff);
4976
4977         for (i = 0; i < 5; i++)
4978                 WREG32(GMCON_PGFSM_WRITE, 0);
4979
4980         WREG32(GMCON_PGFSM_WRITE, 0x3e3e36);
4981         WREG32(GMCON_PGFSM_CONFIG, 0x600010ff);
4982
4983         for (i = 0; i < 5; i++)
4984                 WREG32(GMCON_PGFSM_WRITE, 0);
4985
4986         WREG32(GMCON_PGFSM_WRITE, 0x373f3e);
4987         WREG32(GMCON_PGFSM_CONFIG, 0x700010ff);
4988
4989         for (i = 0; i < 5; i++)
4990                 WREG32(GMCON_PGFSM_WRITE, 0);
4991
4992         WREG32(GMCON_PGFSM_WRITE, 0x3e1332);
4993         WREG32(GMCON_PGFSM_CONFIG, 0xe00010ff);
4994
4995         WREG32(GMCON_MISC3, save->gmcon_misc3);
4996         WREG32(GMCON_MISC, save->gmcon_misc);
4997         WREG32(GMCON_RENG_EXECUTE, save->gmcon_reng_execute);
4998 }
4999
5000 static void cik_gpu_pci_config_reset(struct radeon_device *rdev)
5001 {
5002         struct evergreen_mc_save save;
5003         struct kv_reset_save_regs kv_save = { 0 };
5004         u32 tmp, i;
5005
5006         dev_info(rdev->dev, "GPU pci config reset\n");
5007
5008         /* disable dpm? */
5009
5010         /* disable cg/pg */
5011         cik_fini_pg(rdev);
5012         cik_fini_cg(rdev);
5013
5014         /* Disable GFX parsing/prefetching */
5015         WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);
5016
5017         /* Disable MEC parsing/prefetching */
5018         WREG32(CP_MEC_CNTL, MEC_ME1_HALT | MEC_ME2_HALT);
5019
5020         /* sdma0 */
5021         tmp = RREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET);
5022         tmp |= SDMA_HALT;
5023         WREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET, tmp);
5024         /* sdma1 */
5025         tmp = RREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET);
5026         tmp |= SDMA_HALT;
5027         WREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET, tmp);
5028         /* XXX other engines? */
5029
5030         /* halt the rlc, disable cp internal ints */
5031         cik_rlc_stop(rdev);
5032
5033         udelay(50);
5034
5035         /* disable mem access */
5036         evergreen_mc_stop(rdev, &save);
5037         if (evergreen_mc_wait_for_idle(rdev)) {
5038                 dev_warn(rdev->dev, "Wait for MC idle timed out !\n");
5039         }
5040
5041         if (rdev->flags & RADEON_IS_IGP)
5042                 kv_save_regs_for_reset(rdev, &kv_save);
5043
5044         /* disable BM */
5045         pci_clear_master(rdev->pdev);
5046         /* reset */
5047         radeon_pci_config_reset(rdev);
5048
5049         udelay(100);
5050
5051         /* wait for asic to come out of reset */
5052         for (i = 0; i < rdev->usec_timeout; i++) {
5053                 if (RREG32(CONFIG_MEMSIZE) != 0xffffffff)
5054                         break;
5055                 udelay(1);
5056         }
5057
5058         /* does asic init need to be run first??? */
5059         if (rdev->flags & RADEON_IS_IGP)
5060                 kv_restore_regs_for_reset(rdev, &kv_save);
5061 }
5062
5063 /**
5064  * cik_asic_reset - soft reset GPU
5065  *
5066  * @rdev: radeon_device pointer
5067  *
5068  * Look up which blocks are hung and attempt
5069  * to reset them.
5070  * Returns 0 for success.
5071  */
5072 int cik_asic_reset(struct radeon_device *rdev)
5073 {
5074         u32 reset_mask;
5075
5076         reset_mask = cik_gpu_check_soft_reset(rdev);
5077
5078         if (reset_mask)
5079                 r600_set_bios_scratch_engine_hung(rdev, true);
5080
5081         /* try soft reset */
5082         cik_gpu_soft_reset(rdev, reset_mask);
5083
5084         reset_mask = cik_gpu_check_soft_reset(rdev);
5085
5086         /* try pci config reset */
5087         if (reset_mask && radeon_hard_reset)
5088                 cik_gpu_pci_config_reset(rdev);
5089
5090         reset_mask = cik_gpu_check_soft_reset(rdev);
5091
5092         if (!reset_mask)
5093                 r600_set_bios_scratch_engine_hung(rdev, false);
5094
5095         return 0;
5096 }
5097
5098 /**
5099  * cik_gfx_is_lockup - check if the 3D engine is locked up
5100  *
5101  * @rdev: radeon_device pointer
5102  * @ring: radeon_ring structure holding ring information
5103  *
5104  * Check if the 3D engine is locked up (CIK).
5105  * Returns true if the engine is locked, false if not.
5106  */
5107 bool cik_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
5108 {
5109         u32 reset_mask = cik_gpu_check_soft_reset(rdev);
5110
5111         if (!(reset_mask & (RADEON_RESET_GFX |
5112                             RADEON_RESET_COMPUTE |
5113                             RADEON_RESET_CP))) {
5114                 radeon_ring_lockup_update(ring);
5115                 return false;
5116         }
5117         /* force CP activities */
5118         radeon_ring_force_activity(rdev, ring);
5119         return radeon_ring_test_lockup(rdev, ring);
5120 }
5121
5122 /* MC */
5123 /**
5124  * cik_mc_program - program the GPU memory controller
5125  *
5126  * @rdev: radeon_device pointer
5127  *
5128  * Set the location of vram, gart, and AGP in the GPU's
5129  * physical address space (CIK).
5130  */
5131 static void cik_mc_program(struct radeon_device *rdev)
5132 {
5133         struct evergreen_mc_save save;
5134         u32 tmp;
5135         int i, j;
5136
5137         /* Initialize HDP */
5138         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
5139                 WREG32((0x2c14 + j), 0x00000000);
5140                 WREG32((0x2c18 + j), 0x00000000);
5141                 WREG32((0x2c1c + j), 0x00000000);
5142                 WREG32((0x2c20 + j), 0x00000000);
5143                 WREG32((0x2c24 + j), 0x00000000);
5144         }
5145         WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
5146
5147         evergreen_mc_stop(rdev, &save);
5148         if (radeon_mc_wait_for_idle(rdev)) {
5149                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
5150         }
5151         /* Lockout access through VGA aperture*/
5152         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
5153         /* Update configuration */
5154         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
5155                rdev->mc.vram_start >> 12);
5156         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
5157                rdev->mc.vram_end >> 12);
5158         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
5159                rdev->vram_scratch.gpu_addr >> 12);
5160         tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
5161         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
5162         WREG32(MC_VM_FB_LOCATION, tmp);
5163         /* XXX double check these! */
5164         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
5165         WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
5166         WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
5167         WREG32(MC_VM_AGP_BASE, 0);
5168         WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
5169         WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
5170         if (radeon_mc_wait_for_idle(rdev)) {
5171                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
5172         }
5173         evergreen_mc_resume(rdev, &save);
5174         /* we need to own VRAM, so turn off the VGA renderer here
5175          * to stop it overwriting our objects */
5176         rv515_vga_render_disable(rdev);
5177 }
5178
5179 /**
5180  * cik_mc_init - initialize the memory controller driver params
5181  *
5182  * @rdev: radeon_device pointer
5183  *
5184  * Look up the amount of vram, vram width, and decide how to place
5185  * vram and gart within the GPU's physical address space (CIK).
5186  * Returns 0 for success.
5187  */
5188 static int cik_mc_init(struct radeon_device *rdev)
5189 {
5190         u32 tmp;
5191         int chansize, numchan;
5192
5193         /* Get VRAM informations */
5194         rdev->mc.vram_is_ddr = true;
5195         tmp = RREG32(MC_ARB_RAMCFG);
5196         if (tmp & CHANSIZE_MASK) {
5197                 chansize = 64;
5198         } else {
5199                 chansize = 32;
5200         }
5201         tmp = RREG32(MC_SHARED_CHMAP);
5202         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
5203         case 0:
5204         default:
5205                 numchan = 1;
5206                 break;
5207         case 1:
5208                 numchan = 2;
5209                 break;
5210         case 2:
5211                 numchan = 4;
5212                 break;
5213         case 3:
5214                 numchan = 8;
5215                 break;
5216         case 4:
5217                 numchan = 3;
5218                 break;
5219         case 5:
5220                 numchan = 6;
5221                 break;
5222         case 6:
5223                 numchan = 10;
5224                 break;
5225         case 7:
5226                 numchan = 12;
5227                 break;
5228         case 8:
5229                 numchan = 16;
5230                 break;
5231         }
5232         rdev->mc.vram_width = numchan * chansize;
5233         /* Could aper size report 0 ? */
5234         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
5235         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
5236         /* size in MB on si */
5237         rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL;
5238         rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL;
5239         rdev->mc.visible_vram_size = rdev->mc.aper_size;
5240         si_vram_gtt_location(rdev, &rdev->mc);
5241         radeon_update_bandwidth_info(rdev);
5242
5243         return 0;
5244 }
5245
5246 /*
5247  * GART
5248  * VMID 0 is the physical GPU addresses as used by the kernel.
5249  * VMIDs 1-15 are used for userspace clients and are handled
5250  * by the radeon vm/hsa code.
5251  */
5252 /**
5253  * cik_pcie_gart_tlb_flush - gart tlb flush callback
5254  *
5255  * @rdev: radeon_device pointer
5256  *
5257  * Flush the TLB for the VMID 0 page table (CIK).
5258  */
5259 void cik_pcie_gart_tlb_flush(struct radeon_device *rdev)
5260 {
5261         /* flush hdp cache */
5262         WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0);
5263
5264         /* bits 0-15 are the VM contexts0-15 */
5265         WREG32(VM_INVALIDATE_REQUEST, 0x1);
5266 }
5267
5268 /**
5269  * cik_pcie_gart_enable - gart enable
5270  *
5271  * @rdev: radeon_device pointer
5272  *
5273  * This sets up the TLBs, programs the page tables for VMID0,
5274  * sets up the hw for VMIDs 1-15 which are allocated on
5275  * demand, and sets up the global locations for the LDS, GDS,
5276  * and GPUVM for FSA64 clients (CIK).
5277  * Returns 0 for success, errors for failure.
5278  */
5279 static int cik_pcie_gart_enable(struct radeon_device *rdev)
5280 {
5281         int r, i;
5282
5283         if (rdev->gart.robj == NULL) {
5284                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
5285                 return -EINVAL;
5286         }
5287         r = radeon_gart_table_vram_pin(rdev);
5288         if (r)
5289                 return r;
5290         radeon_gart_restore(rdev);
5291         /* Setup TLB control */
5292         WREG32(MC_VM_MX_L1_TLB_CNTL,
5293                (0xA << 7) |
5294                ENABLE_L1_TLB |
5295                SYSTEM_ACCESS_MODE_NOT_IN_SYS |
5296                ENABLE_ADVANCED_DRIVER_MODEL |
5297                SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
5298         /* Setup L2 cache */
5299         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |
5300                ENABLE_L2_FRAGMENT_PROCESSING |
5301                ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
5302                ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
5303                EFFECTIVE_L2_QUEUE_SIZE(7) |
5304                CONTEXT1_IDENTITY_ACCESS_MODE(1));
5305         WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE);
5306         WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
5307                L2_CACHE_BIGK_FRAGMENT_SIZE(6));
5308         /* setup context0 */
5309         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
5310         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
5311         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
5312         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
5313                         (u32)(rdev->dummy_page.addr >> 12));
5314         WREG32(VM_CONTEXT0_CNTL2, 0);
5315         WREG32(VM_CONTEXT0_CNTL, (ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
5316                                   RANGE_PROTECTION_FAULT_ENABLE_DEFAULT));
5317
5318         WREG32(0x15D4, 0);
5319         WREG32(0x15D8, 0);
5320         WREG32(0x15DC, 0);
5321
5322         /* empty context1-15 */
5323         /* FIXME start with 4G, once using 2 level pt switch to full
5324          * vm size space
5325          */
5326         /* set vm size, must be a multiple of 4 */
5327         WREG32(VM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
5328         WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, rdev->vm_manager.max_pfn);
5329         for (i = 1; i < 16; i++) {
5330                 if (i < 8)
5331                         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
5332                                rdev->gart.table_addr >> 12);
5333                 else
5334                         WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2),
5335                                rdev->gart.table_addr >> 12);
5336         }
5337
5338         /* enable context1-15 */
5339         WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
5340                (u32)(rdev->dummy_page.addr >> 12));
5341         WREG32(VM_CONTEXT1_CNTL2, 4);
5342         WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) |
5343                                 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
5344                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT |
5345                                 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
5346                                 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT |
5347                                 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT |
5348                                 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT |
5349                                 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT |
5350                                 VALID_PROTECTION_FAULT_ENABLE_DEFAULT |
5351                                 READ_PROTECTION_FAULT_ENABLE_INTERRUPT |
5352                                 READ_PROTECTION_FAULT_ENABLE_DEFAULT |
5353                                 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT |
5354                                 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT);
5355
5356         if (rdev->family == CHIP_KAVERI) {
5357                 u32 tmp = RREG32(CHUB_CONTROL);
5358                 tmp &= ~BYPASS_VM;
5359                 WREG32(CHUB_CONTROL, tmp);
5360         }
5361
5362         /* XXX SH_MEM regs */
5363         /* where to put LDS, scratch, GPUVM in FSA64 space */
5364         mutex_lock(&rdev->srbm_mutex);
5365         for (i = 0; i < 16; i++) {
5366                 cik_srbm_select(rdev, 0, 0, 0, i);
5367                 /* CP and shaders */
5368                 WREG32(SH_MEM_CONFIG, 0);
5369                 WREG32(SH_MEM_APE1_BASE, 1);
5370                 WREG32(SH_MEM_APE1_LIMIT, 0);
5371                 WREG32(SH_MEM_BASES, 0);
5372                 /* SDMA GFX */
5373                 WREG32(SDMA0_GFX_VIRTUAL_ADDR + SDMA0_REGISTER_OFFSET, 0);
5374                 WREG32(SDMA0_GFX_APE1_CNTL + SDMA0_REGISTER_OFFSET, 0);
5375                 WREG32(SDMA0_GFX_VIRTUAL_ADDR + SDMA1_REGISTER_OFFSET, 0);
5376                 WREG32(SDMA0_GFX_APE1_CNTL + SDMA1_REGISTER_OFFSET, 0);
5377                 /* XXX SDMA RLC - todo */
5378         }
5379         cik_srbm_select(rdev, 0, 0, 0, 0);
5380         mutex_unlock(&rdev->srbm_mutex);
5381
5382         cik_pcie_gart_tlb_flush(rdev);
5383         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
5384                  (unsigned)(rdev->mc.gtt_size >> 20),
5385                  (unsigned long long)rdev->gart.table_addr);
5386         rdev->gart.ready = true;
5387         return 0;
5388 }
5389
5390 /**
5391  * cik_pcie_gart_disable - gart disable
5392  *
5393  * @rdev: radeon_device pointer
5394  *
5395  * This disables all VM page table (CIK).
5396  */
5397 static void cik_pcie_gart_disable(struct radeon_device *rdev)
5398 {
5399         /* Disable all tables */
5400         WREG32(VM_CONTEXT0_CNTL, 0);
5401         WREG32(VM_CONTEXT1_CNTL, 0);
5402         /* Setup TLB control */
5403         WREG32(MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE_NOT_IN_SYS |
5404                SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
5405         /* Setup L2 cache */
5406         WREG32(VM_L2_CNTL,
5407                ENABLE_L2_FRAGMENT_PROCESSING |
5408                ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
5409                ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
5410                EFFECTIVE_L2_QUEUE_SIZE(7) |
5411                CONTEXT1_IDENTITY_ACCESS_MODE(1));
5412         WREG32(VM_L2_CNTL2, 0);
5413         WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
5414                L2_CACHE_BIGK_FRAGMENT_SIZE(6));
5415         radeon_gart_table_vram_unpin(rdev);
5416 }
5417
5418 /**
5419  * cik_pcie_gart_fini - vm fini callback
5420  *
5421  * @rdev: radeon_device pointer
5422  *
5423  * Tears down the driver GART/VM setup (CIK).
5424  */
5425 static void cik_pcie_gart_fini(struct radeon_device *rdev)
5426 {
5427         cik_pcie_gart_disable(rdev);
5428         radeon_gart_table_vram_free(rdev);
5429         radeon_gart_fini(rdev);
5430 }
5431
5432 /* vm parser */
5433 /**
5434  * cik_ib_parse - vm ib_parse callback
5435  *
5436  * @rdev: radeon_device pointer
5437  * @ib: indirect buffer pointer
5438  *
5439  * CIK uses hw IB checking so this is a nop (CIK).
5440  */
5441 int cik_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib)
5442 {
5443         return 0;
5444 }
5445
5446 /*
5447  * vm
5448  * VMID 0 is the physical GPU addresses as used by the kernel.
5449  * VMIDs 1-15 are used for userspace clients and are handled
5450  * by the radeon vm/hsa code.
5451  */
5452 /**
5453  * cik_vm_init - cik vm init callback
5454  *
5455  * @rdev: radeon_device pointer
5456  *
5457  * Inits cik specific vm parameters (number of VMs, base of vram for
5458  * VMIDs 1-15) (CIK).
5459  * Returns 0 for success.
5460  */
5461 int cik_vm_init(struct radeon_device *rdev)
5462 {
5463         /* number of VMs */
5464         rdev->vm_manager.nvm = 16;
5465         /* base offset of vram pages */
5466         if (rdev->flags & RADEON_IS_IGP) {
5467                 u64 tmp = RREG32(MC_VM_FB_OFFSET);
5468                 tmp <<= 22;
5469                 rdev->vm_manager.vram_base_offset = tmp;
5470         } else
5471                 rdev->vm_manager.vram_base_offset = 0;
5472
5473         return 0;
5474 }
5475
5476 /**
5477  * cik_vm_fini - cik vm fini callback
5478  *
5479  * @rdev: radeon_device pointer
5480  *
5481  * Tear down any asic specific VM setup (CIK).
5482  */
5483 void cik_vm_fini(struct radeon_device *rdev)
5484 {
5485 }
5486
5487 /**
5488  * cik_vm_decode_fault - print human readable fault info
5489  *
5490  * @rdev: radeon_device pointer
5491  * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
5492  * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
5493  *
5494  * Print human readable fault information (CIK).
5495  */
5496 static void cik_vm_decode_fault(struct radeon_device *rdev,
5497                                 u32 status, u32 addr, u32 mc_client)
5498 {
5499         u32 mc_id;
5500         u32 vmid = (status & FAULT_VMID_MASK) >> FAULT_VMID_SHIFT;
5501         u32 protections = (status & PROTECTIONS_MASK) >> PROTECTIONS_SHIFT;
5502         char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
5503                 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
5504
5505         if (rdev->family == CHIP_HAWAII)
5506                 mc_id = (status & HAWAII_MEMORY_CLIENT_ID_MASK) >> MEMORY_CLIENT_ID_SHIFT;
5507         else
5508                 mc_id = (status & MEMORY_CLIENT_ID_MASK) >> MEMORY_CLIENT_ID_SHIFT;
5509
5510         printk("VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
5511                protections, vmid, addr,
5512                (status & MEMORY_CLIENT_RW_MASK) ? "write" : "read",
5513                block, mc_client, mc_id);
5514 }
5515
5516 /**
5517  * cik_vm_flush - cik vm flush using the CP
5518  *
5519  * @rdev: radeon_device pointer
5520  *
5521  * Update the page table base and flush the VM TLB
5522  * using the CP (CIK).
5523  */
5524 void cik_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
5525 {
5526         struct radeon_ring *ring = &rdev->ring[ridx];
5527
5528         if (vm == NULL)
5529                 return;
5530
5531         radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5532         radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5533                                  WRITE_DATA_DST_SEL(0)));
5534         if (vm->id < 8) {
5535                 radeon_ring_write(ring,
5536                                   (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2)) >> 2);
5537         } else {
5538                 radeon_ring_write(ring,
5539                                   (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm->id - 8) << 2)) >> 2);
5540         }
5541         radeon_ring_write(ring, 0);
5542         radeon_ring_write(ring, vm->pd_gpu_addr >> 12);
5543
5544         /* update SH_MEM_* regs */
5545         radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5546         radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5547                                  WRITE_DATA_DST_SEL(0)));
5548         radeon_ring_write(ring, SRBM_GFX_CNTL >> 2);
5549         radeon_ring_write(ring, 0);
5550         radeon_ring_write(ring, VMID(vm->id));
5551
5552         radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 6));
5553         radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5554                                  WRITE_DATA_DST_SEL(0)));
5555         radeon_ring_write(ring, SH_MEM_BASES >> 2);
5556         radeon_ring_write(ring, 0);
5557
5558         radeon_ring_write(ring, 0); /* SH_MEM_BASES */
5559         radeon_ring_write(ring, 0); /* SH_MEM_CONFIG */
5560         radeon_ring_write(ring, 1); /* SH_MEM_APE1_BASE */
5561         radeon_ring_write(ring, 0); /* SH_MEM_APE1_LIMIT */
5562
5563         radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5564         radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5565                                  WRITE_DATA_DST_SEL(0)));
5566         radeon_ring_write(ring, SRBM_GFX_CNTL >> 2);
5567         radeon_ring_write(ring, 0);
5568         radeon_ring_write(ring, VMID(0));
5569
5570         /* HDP flush */
5571         cik_hdp_flush_cp_ring_emit(rdev, ridx);
5572
5573         /* bits 0-15 are the VM contexts0-15 */
5574         radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5575         radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5576                                  WRITE_DATA_DST_SEL(0)));
5577         radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2);
5578         radeon_ring_write(ring, 0);
5579         radeon_ring_write(ring, 1 << vm->id);
5580
5581         /* compute doesn't have PFP */
5582         if (ridx == RADEON_RING_TYPE_GFX_INDEX) {
5583                 /* sync PFP to ME, otherwise we might get invalid PFP reads */
5584                 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
5585                 radeon_ring_write(ring, 0x0);
5586         }
5587 }
5588
5589 /*
5590  * RLC
5591  * The RLC is a multi-purpose microengine that handles a
5592  * variety of functions, the most important of which is
5593  * the interrupt controller.
5594  */
5595 static void cik_enable_gui_idle_interrupt(struct radeon_device *rdev,
5596                                           bool enable)
5597 {
5598         u32 tmp = RREG32(CP_INT_CNTL_RING0);
5599
5600         if (enable)
5601                 tmp |= (CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
5602         else
5603                 tmp &= ~(CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
5604         WREG32(CP_INT_CNTL_RING0, tmp);
5605 }
5606
5607 static void cik_enable_lbpw(struct radeon_device *rdev, bool enable)
5608 {
5609         u32 tmp;
5610
5611         tmp = RREG32(RLC_LB_CNTL);
5612         if (enable)
5613                 tmp |= LOAD_BALANCE_ENABLE;
5614         else
5615                 tmp &= ~LOAD_BALANCE_ENABLE;
5616         WREG32(RLC_LB_CNTL, tmp);
5617 }
5618
5619 static void cik_wait_for_rlc_serdes(struct radeon_device *rdev)
5620 {
5621         u32 i, j, k;
5622         u32 mask;
5623
5624         for (i = 0; i < rdev->config.cik.max_shader_engines; i++) {
5625                 for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) {
5626                         cik_select_se_sh(rdev, i, j);
5627                         for (k = 0; k < rdev->usec_timeout; k++) {
5628                                 if (RREG32(RLC_SERDES_CU_MASTER_BUSY) == 0)
5629                                         break;
5630                                 udelay(1);
5631                         }
5632                 }
5633         }
5634         cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
5635
5636         mask = SE_MASTER_BUSY_MASK | GC_MASTER_BUSY | TC0_MASTER_BUSY | TC1_MASTER_BUSY;
5637         for (k = 0; k < rdev->usec_timeout; k++) {
5638                 if ((RREG32(RLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
5639                         break;
5640                 udelay(1);
5641         }
5642 }
5643
5644 static void cik_update_rlc(struct radeon_device *rdev, u32 rlc)
5645 {
5646         u32 tmp;
5647
5648         tmp = RREG32(RLC_CNTL);
5649         if (tmp != rlc)
5650                 WREG32(RLC_CNTL, rlc);
5651 }
5652
5653 static u32 cik_halt_rlc(struct radeon_device *rdev)
5654 {
5655         u32 data, orig;
5656
5657         orig = data = RREG32(RLC_CNTL);
5658
5659         if (data & RLC_ENABLE) {
5660                 u32 i;
5661
5662                 data &= ~RLC_ENABLE;
5663                 WREG32(RLC_CNTL, data);
5664
5665                 for (i = 0; i < rdev->usec_timeout; i++) {
5666                         if ((RREG32(RLC_GPM_STAT) & RLC_GPM_BUSY) == 0)
5667                                 break;
5668                         udelay(1);
5669                 }
5670
5671                 cik_wait_for_rlc_serdes(rdev);
5672         }
5673
5674         return orig;
5675 }
5676
5677 void cik_enter_rlc_safe_mode(struct radeon_device *rdev)
5678 {
5679         u32 tmp, i, mask;
5680
5681         tmp = REQ | MESSAGE(MSG_ENTER_RLC_SAFE_MODE);
5682         WREG32(RLC_GPR_REG2, tmp);
5683
5684         mask = GFX_POWER_STATUS | GFX_CLOCK_STATUS;
5685         for (i = 0; i < rdev->usec_timeout; i++) {
5686                 if ((RREG32(RLC_GPM_STAT) & mask) == mask)
5687                         break;
5688                 udelay(1);
5689         }
5690
5691         for (i = 0; i < rdev->usec_timeout; i++) {
5692                 if ((RREG32(RLC_GPR_REG2) & REQ) == 0)
5693                         break;
5694                 udelay(1);
5695         }
5696 }
5697
5698 void cik_exit_rlc_safe_mode(struct radeon_device *rdev)
5699 {
5700         u32 tmp;
5701
5702         tmp = REQ | MESSAGE(MSG_EXIT_RLC_SAFE_MODE);
5703         WREG32(RLC_GPR_REG2, tmp);
5704 }
5705
5706 /**
5707  * cik_rlc_stop - stop the RLC ME
5708  *
5709  * @rdev: radeon_device pointer
5710  *
5711  * Halt the RLC ME (MicroEngine) (CIK).
5712  */
5713 static void cik_rlc_stop(struct radeon_device *rdev)
5714 {
5715         WREG32(RLC_CNTL, 0);
5716
5717         cik_enable_gui_idle_interrupt(rdev, false);
5718
5719         cik_wait_for_rlc_serdes(rdev);
5720 }
5721
5722 /**
5723  * cik_rlc_start - start the RLC ME
5724  *
5725  * @rdev: radeon_device pointer
5726  *
5727  * Unhalt the RLC ME (MicroEngine) (CIK).
5728  */
5729 static void cik_rlc_start(struct radeon_device *rdev)
5730 {
5731         WREG32(RLC_CNTL, RLC_ENABLE);
5732
5733         cik_enable_gui_idle_interrupt(rdev, true);
5734
5735         udelay(50);
5736 }
5737
5738 /**
5739  * cik_rlc_resume - setup the RLC hw
5740  *
5741  * @rdev: radeon_device pointer
5742  *
5743  * Initialize the RLC registers, load the ucode,
5744  * and start the RLC (CIK).
5745  * Returns 0 for success, -EINVAL if the ucode is not available.
5746  */
5747 static int cik_rlc_resume(struct radeon_device *rdev)
5748 {
5749         u32 i, size, tmp;
5750         const __be32 *fw_data;
5751
5752         if (!rdev->rlc_fw)
5753                 return -EINVAL;
5754
5755         switch (rdev->family) {
5756         case CHIP_BONAIRE:
5757         case CHIP_HAWAII:
5758         default:
5759                 size = BONAIRE_RLC_UCODE_SIZE;
5760                 break;
5761         case CHIP_KAVERI:
5762                 size = KV_RLC_UCODE_SIZE;
5763                 break;
5764         case CHIP_KABINI:
5765                 size = KB_RLC_UCODE_SIZE;
5766                 break;
5767         }
5768
5769         cik_rlc_stop(rdev);
5770
5771         /* disable CG */
5772         tmp = RREG32(RLC_CGCG_CGLS_CTRL) & 0xfffffffc;
5773         WREG32(RLC_CGCG_CGLS_CTRL, tmp);
5774
5775         si_rlc_reset(rdev);
5776
5777         cik_init_pg(rdev);
5778
5779         cik_init_cg(rdev);
5780
5781         WREG32(RLC_LB_CNTR_INIT, 0);
5782         WREG32(RLC_LB_CNTR_MAX, 0x00008000);
5783
5784         cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
5785         WREG32(RLC_LB_INIT_CU_MASK, 0xffffffff);
5786         WREG32(RLC_LB_PARAMS, 0x00600408);
5787         WREG32(RLC_LB_CNTL, 0x80000004);
5788
5789         WREG32(RLC_MC_CNTL, 0);
5790         WREG32(RLC_UCODE_CNTL, 0);
5791
5792         fw_data = (const __be32 *)rdev->rlc_fw->data;
5793                 WREG32(RLC_GPM_UCODE_ADDR, 0);
5794         for (i = 0; i < size; i++)
5795                 WREG32(RLC_GPM_UCODE_DATA, be32_to_cpup(fw_data++));
5796         WREG32(RLC_GPM_UCODE_ADDR, 0);
5797
5798         /* XXX - find out what chips support lbpw */
5799         cik_enable_lbpw(rdev, false);
5800
5801         if (rdev->family == CHIP_BONAIRE)
5802                 WREG32(RLC_DRIVER_DMA_STATUS, 0);
5803
5804         cik_rlc_start(rdev);
5805
5806         return 0;
5807 }
5808
5809 static void cik_enable_cgcg(struct radeon_device *rdev, bool enable)
5810 {
5811         u32 data, orig, tmp, tmp2;
5812
5813         orig = data = RREG32(RLC_CGCG_CGLS_CTRL);
5814
5815         if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_CGCG)) {
5816                 cik_enable_gui_idle_interrupt(rdev, true);
5817
5818                 tmp = cik_halt_rlc(rdev);
5819
5820                 cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
5821                 WREG32(RLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
5822                 WREG32(RLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
5823                 tmp2 = BPM_ADDR_MASK | CGCG_OVERRIDE_0 | CGLS_ENABLE;
5824                 WREG32(RLC_SERDES_WR_CTRL, tmp2);
5825
5826                 cik_update_rlc(rdev, tmp);
5827
5828                 data |= CGCG_EN | CGLS_EN;
5829         } else {
5830                 cik_enable_gui_idle_interrupt(rdev, false);
5831
5832                 RREG32(CB_CGTT_SCLK_CTRL);
5833                 RREG32(CB_CGTT_SCLK_CTRL);
5834                 RREG32(CB_CGTT_SCLK_CTRL);
5835                 RREG32(CB_CGTT_SCLK_CTRL);
5836
5837                 data &= ~(CGCG_EN | CGLS_EN);
5838         }
5839
5840         if (orig != data)
5841                 WREG32(RLC_CGCG_CGLS_CTRL, data);
5842
5843 }
5844
5845 static void cik_enable_mgcg(struct radeon_device *rdev, bool enable)
5846 {
5847         u32 data, orig, tmp = 0;
5848
5849         if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_MGCG)) {
5850                 if (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_MGLS) {
5851                         if (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_CP_LS) {
5852                                 orig = data = RREG32(CP_MEM_SLP_CNTL);
5853                                 data |= CP_MEM_LS_EN;
5854                                 if (orig != data)
5855                                         WREG32(CP_MEM_SLP_CNTL, data);
5856                         }
5857                 }
5858
5859                 orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE);
5860                 data &= 0xfffffffd;
5861                 if (orig != data)
5862                         WREG32(RLC_CGTT_MGCG_OVERRIDE, data);
5863
5864                 tmp = cik_halt_rlc(rdev);
5865
5866                 cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
5867                 WREG32(RLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
5868                 WREG32(RLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
5869                 data = BPM_ADDR_MASK | MGCG_OVERRIDE_0;
5870                 WREG32(RLC_SERDES_WR_CTRL, data);
5871
5872                 cik_update_rlc(rdev, tmp);
5873
5874                 if (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_CGTS) {
5875                         orig = data = RREG32(CGTS_SM_CTRL_REG);
5876                         data &= ~SM_MODE_MASK;
5877                         data |= SM_MODE(0x2);
5878                         data |= SM_MODE_ENABLE;
5879                         data &= ~CGTS_OVERRIDE;
5880                         if ((rdev->cg_flags & RADEON_CG_SUPPORT_GFX_MGLS) &&
5881                             (rdev->cg_flags & RADEON_CG_SUPPORT_GFX_CGTS_LS))
5882                                 data &= ~CGTS_LS_OVERRIDE;
5883                         data &= ~ON_MONITOR_ADD_MASK;
5884                         data |= ON_MONITOR_ADD_EN;
5885                         data |= ON_MONITOR_ADD(0x96);
5886                         if (orig != data)
5887                                 WREG32(CGTS_SM_CTRL_REG, data);
5888                 }
5889         } else {
5890                 orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE);
5891                 data |= 0x00000002;
5892                 if (orig != data)
5893                         WREG32(RLC_CGTT_MGCG_OVERRIDE, data);
5894
5895                 data = RREG32(RLC_MEM_SLP_CNTL);
5896                 if (data & RLC_MEM_LS_EN) {
5897                         data &= ~RLC_MEM_LS_EN;
5898                         WREG32(RLC_MEM_SLP_CNTL, data);
5899                 }
5900
5901                 data = RREG32(CP_MEM_SLP_CNTL);
5902                 if (data & CP_MEM_LS_EN) {
5903                         data &= ~CP_MEM_LS_EN;
5904                         WREG32(CP_MEM_SLP_CNTL, data);
5905                 }
5906
5907                 orig = data = RREG32(CGTS_SM_CTRL_REG);
5908                 data |= CGTS_OVERRIDE | CGTS_LS_OVERRIDE;
5909                 if (orig != data)
5910                         WREG32(CGTS_SM_CTRL_REG, data);
5911
5912                 tmp = cik_halt_rlc(rdev);
5913
5914                 cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
5915                 WREG32(RLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff);
5916                 WREG32(RLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff);
5917                 data = BPM_ADDR_MASK | MGCG_OVERRIDE_1;
5918                 WREG32(RLC_SERDES_WR_CTRL, data);
5919
5920                 cik_update_rlc(rdev, tmp);
5921         }
5922 }
5923
5924 static const u32 mc_cg_registers[] =
5925 {
5926         MC_HUB_MISC_HUB_CG,
5927         MC_HUB_MISC_SIP_CG,
5928         MC_HUB_MISC_VM_CG,
5929         MC_XPB_CLK_GAT,
5930         ATC_MISC_CG,
5931         MC_CITF_MISC_WR_CG,
5932         MC_CITF_MISC_RD_CG,
5933         MC_CITF_MISC_VM_CG,
5934         VM_L2_CG,
5935 };
5936
5937 static void cik_enable_mc_ls(struct radeon_device *rdev,
5938                              bool enable)
5939 {
5940         int i;
5941         u32 orig, data;
5942
5943         for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
5944                 orig = data = RREG32(mc_cg_registers[i]);
5945                 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_MC_LS))
5946                         data |= MC_LS_ENABLE;
5947                 else
5948                         data &= ~MC_LS_ENABLE;
5949                 if (data != orig)
5950                         WREG32(mc_cg_registers[i], data);
5951         }
5952 }
5953
5954 static void cik_enable_mc_mgcg(struct radeon_device *rdev,
5955                                bool enable)
5956 {
5957         int i;
5958         u32 orig, data;
5959
5960         for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
5961                 orig = data = RREG32(mc_cg_registers[i]);
5962                 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_MC_MGCG))
5963                         data |= MC_CG_ENABLE;
5964                 else
5965                         data &= ~MC_CG_ENABLE;
5966                 if (data != orig)
5967                         WREG32(mc_cg_registers[i], data);
5968         }
5969 }
5970
5971 static void cik_enable_sdma_mgcg(struct radeon_device *rdev,
5972                                  bool enable)
5973 {
5974         u32 orig, data;
5975
5976         if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_SDMA_MGCG)) {
5977                 WREG32(SDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, 0x00000100);
5978                 WREG32(SDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100);
5979         } else {
5980                 orig = data = RREG32(SDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET);
5981                 data |= 0xff000000;
5982                 if (data != orig)
5983                         WREG32(SDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, data);
5984
5985                 orig = data = RREG32(SDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET);
5986                 data |= 0xff000000;
5987                 if (data != orig)
5988                         WREG32(SDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, data);
5989         }
5990 }
5991
5992 static void cik_enable_sdma_mgls(struct radeon_device *rdev,
5993                                  bool enable)
5994 {
5995         u32 orig, data;
5996
5997         if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_SDMA_LS)) {
5998                 orig = data = RREG32(SDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
5999                 data |= 0x100;
6000                 if (orig != data)
6001                         WREG32(SDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
6002
6003                 orig = data = RREG32(SDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
6004                 data |= 0x100;
6005                 if (orig != data)
6006                         WREG32(SDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);
6007         } else {
6008                 orig = data = RREG32(SDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET);
6009                 data &= ~0x100;
6010                 if (orig != data)
6011                         WREG32(SDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data);
6012
6013                 orig = data = RREG32(SDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);
6014                 data &= ~0x100;
6015                 if (orig != data)
6016                         WREG32(SDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);
6017         }
6018 }
6019
6020 static void cik_enable_uvd_mgcg(struct radeon_device *rdev,
6021                                 bool enable)
6022 {
6023         u32 orig, data;
6024
6025         if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_UVD_MGCG)) {
6026                 data = RREG32_UVD_CTX(UVD_CGC_MEM_CTRL);
6027                 data = 0xfff;
6028                 WREG32_UVD_CTX(UVD_CGC_MEM_CTRL, data);
6029
6030                 orig = data = RREG32(UVD_CGC_CTRL);
6031                 data |= DCM;
6032                 if (orig != data)
6033                         WREG32(UVD_CGC_CTRL, data);
6034         } else {
6035                 data = RREG32_UVD_CTX(UVD_CGC_MEM_CTRL);
6036                 data &= ~0xfff;
6037                 WREG32_UVD_CTX(UVD_CGC_MEM_CTRL, data);
6038
6039                 orig = data = RREG32(UVD_CGC_CTRL);
6040                 data &= ~DCM;
6041                 if (orig != data)
6042                         WREG32(UVD_CGC_CTRL, data);
6043         }
6044 }
6045
6046 static void cik_enable_bif_mgls(struct radeon_device *rdev,
6047                                bool enable)
6048 {
6049         u32 orig, data;
6050
6051         orig = data = RREG32_PCIE_PORT(PCIE_CNTL2);
6052
6053         if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_BIF_LS))
6054                 data |= SLV_MEM_LS_EN | MST_MEM_LS_EN |
6055                         REPLAY_MEM_LS_EN | SLV_MEM_AGGRESSIVE_LS_EN;
6056         else
6057                 data &= ~(SLV_MEM_LS_EN | MST_MEM_LS_EN |
6058                           REPLAY_MEM_LS_EN | SLV_MEM_AGGRESSIVE_LS_EN);
6059
6060         if (orig != data)
6061                 WREG32_PCIE_PORT(PCIE_CNTL2, data);
6062 }
6063
6064 static void cik_enable_hdp_mgcg(struct radeon_device *rdev,
6065                                 bool enable)
6066 {
6067         u32 orig, data;
6068
6069         orig = data = RREG32(HDP_HOST_PATH_CNTL);
6070
6071         if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_HDP_MGCG))
6072                 data &= ~CLOCK_GATING_DIS;
6073         else
6074                 data |= CLOCK_GATING_DIS;
6075
6076         if (orig != data)
6077                 WREG32(HDP_HOST_PATH_CNTL, data);
6078 }
6079
6080 static void cik_enable_hdp_ls(struct radeon_device *rdev,
6081                               bool enable)
6082 {
6083         u32 orig, data;
6084
6085         orig = data = RREG32(HDP_MEM_POWER_LS);
6086
6087         if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_HDP_LS))
6088                 data |= HDP_LS_ENABLE;
6089         else
6090                 data &= ~HDP_LS_ENABLE;
6091
6092         if (orig != data)
6093                 WREG32(HDP_MEM_POWER_LS, data);
6094 }
6095
6096 void cik_update_cg(struct radeon_device *rdev,
6097                    u32 block, bool enable)
6098 {
6099
6100         if (block & RADEON_CG_BLOCK_GFX) {
6101                 cik_enable_gui_idle_interrupt(rdev, false);
6102                 /* order matters! */
6103                 if (enable) {
6104                         cik_enable_mgcg(rdev, true);
6105                         cik_enable_cgcg(rdev, true);
6106                 } else {
6107                         cik_enable_cgcg(rdev, false);
6108                         cik_enable_mgcg(rdev, false);
6109                 }
6110                 cik_enable_gui_idle_interrupt(rdev, true);
6111         }
6112
6113         if (block & RADEON_CG_BLOCK_MC) {
6114                 if (!(rdev->flags & RADEON_IS_IGP)) {
6115                         cik_enable_mc_mgcg(rdev, enable);
6116                         cik_enable_mc_ls(rdev, enable);
6117                 }
6118         }
6119
6120         if (block & RADEON_CG_BLOCK_SDMA) {
6121                 cik_enable_sdma_mgcg(rdev, enable);
6122                 cik_enable_sdma_mgls(rdev, enable);
6123         }
6124
6125         if (block & RADEON_CG_BLOCK_BIF) {
6126                 cik_enable_bif_mgls(rdev, enable);
6127         }
6128
6129         if (block & RADEON_CG_BLOCK_UVD) {
6130                 if (rdev->has_uvd)
6131                         cik_enable_uvd_mgcg(rdev, enable);
6132         }
6133
6134         if (block & RADEON_CG_BLOCK_HDP) {
6135                 cik_enable_hdp_mgcg(rdev, enable);
6136                 cik_enable_hdp_ls(rdev, enable);
6137         }
6138 }
6139
6140 static void cik_init_cg(struct radeon_device *rdev)
6141 {
6142
6143         cik_update_cg(rdev, RADEON_CG_BLOCK_GFX, true);
6144
6145         if (rdev->has_uvd)
6146                 si_init_uvd_internal_cg(rdev);
6147
6148         cik_update_cg(rdev, (RADEON_CG_BLOCK_MC |
6149                              RADEON_CG_BLOCK_SDMA |
6150                              RADEON_CG_BLOCK_BIF |
6151                              RADEON_CG_BLOCK_UVD |
6152                              RADEON_CG_BLOCK_HDP), true);
6153 }
6154
6155 static void cik_fini_cg(struct radeon_device *rdev)
6156 {
6157         cik_update_cg(rdev, (RADEON_CG_BLOCK_MC |
6158                              RADEON_CG_BLOCK_SDMA |
6159                              RADEON_CG_BLOCK_BIF |
6160                              RADEON_CG_BLOCK_UVD |
6161                              RADEON_CG_BLOCK_HDP), false);
6162
6163         cik_update_cg(rdev, RADEON_CG_BLOCK_GFX, false);
6164 }
6165
6166 static void cik_enable_sck_slowdown_on_pu(struct radeon_device *rdev,
6167                                           bool enable)
6168 {
6169         u32 data, orig;
6170
6171         orig = data = RREG32(RLC_PG_CNTL);
6172         if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_RLC_SMU_HS))
6173                 data |= SMU_CLK_SLOWDOWN_ON_PU_ENABLE;
6174         else
6175                 data &= ~SMU_CLK_SLOWDOWN_ON_PU_ENABLE;
6176         if (orig != data)
6177                 WREG32(RLC_PG_CNTL, data);
6178 }
6179
6180 static void cik_enable_sck_slowdown_on_pd(struct radeon_device *rdev,
6181                                           bool enable)
6182 {
6183         u32 data, orig;
6184
6185         orig = data = RREG32(RLC_PG_CNTL);
6186         if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_RLC_SMU_HS))
6187                 data |= SMU_CLK_SLOWDOWN_ON_PD_ENABLE;
6188         else
6189                 data &= ~SMU_CLK_SLOWDOWN_ON_PD_ENABLE;
6190         if (orig != data)
6191                 WREG32(RLC_PG_CNTL, data);
6192 }
6193
6194 static void cik_enable_cp_pg(struct radeon_device *rdev, bool enable)
6195 {
6196         u32 data, orig;
6197
6198         orig = data = RREG32(RLC_PG_CNTL);
6199         if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_CP))
6200                 data &= ~DISABLE_CP_PG;
6201         else
6202                 data |= DISABLE_CP_PG;
6203         if (orig != data)
6204                 WREG32(RLC_PG_CNTL, data);
6205 }
6206
6207 static void cik_enable_gds_pg(struct radeon_device *rdev, bool enable)
6208 {
6209         u32 data, orig;
6210
6211         orig = data = RREG32(RLC_PG_CNTL);
6212         if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_GDS))
6213                 data &= ~DISABLE_GDS_PG;
6214         else
6215                 data |= DISABLE_GDS_PG;
6216         if (orig != data)
6217                 WREG32(RLC_PG_CNTL, data);
6218 }
6219
6220 #define CP_ME_TABLE_SIZE    96
6221 #define CP_ME_TABLE_OFFSET  2048
6222 #define CP_MEC_TABLE_OFFSET 4096
6223
6224 void cik_init_cp_pg_table(struct radeon_device *rdev)
6225 {
6226         const __be32 *fw_data;
6227         volatile u32 *dst_ptr;
6228         int me, i, max_me = 4;
6229         u32 bo_offset = 0;
6230         u32 table_offset;
6231
6232         if (rdev->family == CHIP_KAVERI)
6233                 max_me = 5;
6234
6235         if (rdev->rlc.cp_table_ptr == NULL)
6236                 return;
6237
6238         /* write the cp table buffer */
6239         dst_ptr = rdev->rlc.cp_table_ptr;
6240         for (me = 0; me < max_me; me++) {
6241                 if (me == 0) {
6242                         fw_data = (const __be32 *)rdev->ce_fw->data;
6243                         table_offset = CP_ME_TABLE_OFFSET;
6244                 } else if (me == 1) {
6245                         fw_data = (const __be32 *)rdev->pfp_fw->data;
6246                         table_offset = CP_ME_TABLE_OFFSET;
6247                 } else if (me == 2) {
6248                         fw_data = (const __be32 *)rdev->me_fw->data;
6249                         table_offset = CP_ME_TABLE_OFFSET;
6250                 } else {
6251                         fw_data = (const __be32 *)rdev->mec_fw->data;
6252                         table_offset = CP_MEC_TABLE_OFFSET;
6253                 }
6254
6255                 for (i = 0; i < CP_ME_TABLE_SIZE; i ++) {
6256                         dst_ptr[bo_offset + i] = cpu_to_le32(be32_to_cpu(fw_data[table_offset + i]));
6257                 }
6258                 bo_offset += CP_ME_TABLE_SIZE;
6259         }
6260 }
6261
6262 static void cik_enable_gfx_cgpg(struct radeon_device *rdev,
6263                                 bool enable)
6264 {
6265         u32 data, orig;
6266
6267         if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_PG)) {
6268                 orig = data = RREG32(RLC_PG_CNTL);
6269                 data |= GFX_PG_ENABLE;
6270                 if (orig != data)
6271                         WREG32(RLC_PG_CNTL, data);
6272
6273                 orig = data = RREG32(RLC_AUTO_PG_CTRL);
6274                 data |= AUTO_PG_EN;
6275                 if (orig != data)
6276                         WREG32(RLC_AUTO_PG_CTRL, data);
6277         } else {
6278                 orig = data = RREG32(RLC_PG_CNTL);
6279                 data &= ~GFX_PG_ENABLE;
6280                 if (orig != data)
6281                         WREG32(RLC_PG_CNTL, data);
6282
6283                 orig = data = RREG32(RLC_AUTO_PG_CTRL);
6284                 data &= ~AUTO_PG_EN;
6285                 if (orig != data)
6286                         WREG32(RLC_AUTO_PG_CTRL, data);
6287
6288                 data = RREG32(DB_RENDER_CONTROL);
6289         }
6290 }
6291
6292 static u32 cik_get_cu_active_bitmap(struct radeon_device *rdev, u32 se, u32 sh)
6293 {
6294         u32 mask = 0, tmp, tmp1;
6295         int i;
6296
6297         cik_select_se_sh(rdev, se, sh);
6298         tmp = RREG32(CC_GC_SHADER_ARRAY_CONFIG);
6299         tmp1 = RREG32(GC_USER_SHADER_ARRAY_CONFIG);
6300         cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
6301
6302         tmp &= 0xffff0000;
6303
6304         tmp |= tmp1;
6305         tmp >>= 16;
6306
6307         for (i = 0; i < rdev->config.cik.max_cu_per_sh; i ++) {
6308                 mask <<= 1;
6309                 mask |= 1;
6310         }
6311
6312         return (~tmp) & mask;
6313 }
6314
6315 static void cik_init_ao_cu_mask(struct radeon_device *rdev)
6316 {
6317         u32 i, j, k, active_cu_number = 0;
6318         u32 mask, counter, cu_bitmap;
6319         u32 tmp = 0;
6320
6321         for (i = 0; i < rdev->config.cik.max_shader_engines; i++) {
6322                 for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) {
6323                         mask = 1;
6324                         cu_bitmap = 0;
6325                         counter = 0;
6326                         for (k = 0; k < rdev->config.cik.max_cu_per_sh; k ++) {
6327                                 if (cik_get_cu_active_bitmap(rdev, i, j) & mask) {
6328                                         if (counter < 2)
6329                                                 cu_bitmap |= mask;
6330                                         counter ++;
6331                                 }
6332                                 mask <<= 1;
6333                         }
6334
6335                         active_cu_number += counter;
6336                         tmp |= (cu_bitmap << (i * 16 + j * 8));
6337                 }
6338         }
6339
6340         WREG32(RLC_PG_AO_CU_MASK, tmp);
6341
6342         tmp = RREG32(RLC_MAX_PG_CU);
6343         tmp &= ~MAX_PU_CU_MASK;
6344         tmp |= MAX_PU_CU(active_cu_number);
6345         WREG32(RLC_MAX_PG_CU, tmp);
6346 }
6347
6348 static void cik_enable_gfx_static_mgpg(struct radeon_device *rdev,
6349                                        bool enable)
6350 {
6351         u32 data, orig;
6352
6353         orig = data = RREG32(RLC_PG_CNTL);
6354         if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_SMG))
6355                 data |= STATIC_PER_CU_PG_ENABLE;
6356         else
6357                 data &= ~STATIC_PER_CU_PG_ENABLE;
6358         if (orig != data)
6359                 WREG32(RLC_PG_CNTL, data);
6360 }
6361
6362 static void cik_enable_gfx_dynamic_mgpg(struct radeon_device *rdev,
6363                                         bool enable)
6364 {
6365         u32 data, orig;
6366
6367         orig = data = RREG32(RLC_PG_CNTL);
6368         if (enable && (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_DMG))
6369                 data |= DYN_PER_CU_PG_ENABLE;
6370         else
6371                 data &= ~DYN_PER_CU_PG_ENABLE;
6372         if (orig != data)
6373                 WREG32(RLC_PG_CNTL, data);
6374 }
6375
6376 #define RLC_SAVE_AND_RESTORE_STARTING_OFFSET 0x90
6377 #define RLC_CLEAR_STATE_DESCRIPTOR_OFFSET    0x3D
6378
6379 static void cik_init_gfx_cgpg(struct radeon_device *rdev)
6380 {
6381         u32 data, orig;
6382         u32 i;
6383
6384         if (rdev->rlc.cs_data) {
6385                 WREG32(RLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET);
6386                 WREG32(RLC_GPM_SCRATCH_DATA, upper_32_bits(rdev->rlc.clear_state_gpu_addr));
6387                 WREG32(RLC_GPM_SCRATCH_DATA, lower_32_bits(rdev->rlc.clear_state_gpu_addr));
6388                 WREG32(RLC_GPM_SCRATCH_DATA, rdev->rlc.clear_state_size);
6389         } else {
6390                 WREG32(RLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET);
6391                 for (i = 0; i < 3; i++)
6392                         WREG32(RLC_GPM_SCRATCH_DATA, 0);
6393         }
6394         if (rdev->rlc.reg_list) {
6395                 WREG32(RLC_GPM_SCRATCH_ADDR, RLC_SAVE_AND_RESTORE_STARTING_OFFSET);
6396                 for (i = 0; i < rdev->rlc.reg_list_size; i++)
6397                         WREG32(RLC_GPM_SCRATCH_DATA, rdev->rlc.reg_list[i]);
6398         }
6399
6400         orig = data = RREG32(RLC_PG_CNTL);
6401         data |= GFX_PG_SRC;
6402         if (orig != data)
6403                 WREG32(RLC_PG_CNTL, data);
6404
6405         WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8);
6406         WREG32(RLC_CP_TABLE_RESTORE, rdev->rlc.cp_table_gpu_addr >> 8);
6407
6408         data = RREG32(CP_RB_WPTR_POLL_CNTL);
6409         data &= ~IDLE_POLL_COUNT_MASK;
6410         data |= IDLE_POLL_COUNT(0x60);
6411         WREG32(CP_RB_WPTR_POLL_CNTL, data);
6412
6413         data = 0x10101010;
6414         WREG32(RLC_PG_DELAY, data);
6415
6416         data = RREG32(RLC_PG_DELAY_2);
6417         data &= ~0xff;
6418         data |= 0x3;
6419         WREG32(RLC_PG_DELAY_2, data);
6420
6421         data = RREG32(RLC_AUTO_PG_CTRL);
6422         data &= ~GRBM_REG_SGIT_MASK;
6423         data |= GRBM_REG_SGIT(0x700);
6424         WREG32(RLC_AUTO_PG_CTRL, data);
6425
6426 }
6427
6428 static void cik_update_gfx_pg(struct radeon_device *rdev, bool enable)
6429 {
6430         cik_enable_gfx_cgpg(rdev, enable);
6431         cik_enable_gfx_static_mgpg(rdev, enable);
6432         cik_enable_gfx_dynamic_mgpg(rdev, enable);
6433 }
6434
6435 u32 cik_get_csb_size(struct radeon_device *rdev)
6436 {
6437         u32 count = 0;
6438         const struct cs_section_def *sect = NULL;
6439         const struct cs_extent_def *ext = NULL;
6440
6441         if (rdev->rlc.cs_data == NULL)
6442                 return 0;
6443
6444         /* begin clear state */
6445         count += 2;
6446         /* context control state */
6447         count += 3;
6448
6449         for (sect = rdev->rlc.cs_data; sect->section != NULL; ++sect) {
6450                 for (ext = sect->section; ext->extent != NULL; ++ext) {
6451                         if (sect->id == SECT_CONTEXT)
6452                                 count += 2 + ext->reg_count;
6453                         else
6454                                 return 0;
6455                 }
6456         }
6457         /* pa_sc_raster_config/pa_sc_raster_config1 */
6458         count += 4;
6459         /* end clear state */
6460         count += 2;
6461         /* clear state */
6462         count += 2;
6463
6464         return count;
6465 }
6466
6467 void cik_get_csb_buffer(struct radeon_device *rdev, volatile u32 *buffer)
6468 {
6469         u32 count = 0, i;
6470         const struct cs_section_def *sect = NULL;
6471         const struct cs_extent_def *ext = NULL;
6472
6473         if (rdev->rlc.cs_data == NULL)
6474                 return;
6475         if (buffer == NULL)
6476                 return;
6477
6478         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
6479         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
6480
6481         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
6482         buffer[count++] = cpu_to_le32(0x80000000);
6483         buffer[count++] = cpu_to_le32(0x80000000);
6484
6485         for (sect = rdev->rlc.cs_data; sect->section != NULL; ++sect) {
6486                 for (ext = sect->section; ext->extent != NULL; ++ext) {
6487                         if (sect->id == SECT_CONTEXT) {
6488                                 buffer[count++] =
6489                                         cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
6490                                 buffer[count++] = cpu_to_le32(ext->reg_index - 0xa000);
6491                                 for (i = 0; i < ext->reg_count; i++)
6492                                         buffer[count++] = cpu_to_le32(ext->extent[i]);
6493                         } else {
6494                                 return;
6495                         }
6496                 }
6497         }
6498
6499         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 2));
6500         buffer[count++] = cpu_to_le32(PA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
6501         switch (rdev->family) {
6502         case CHIP_BONAIRE:
6503                 buffer[count++] = cpu_to_le32(0x16000012);
6504                 buffer[count++] = cpu_to_le32(0x00000000);
6505                 break;
6506         case CHIP_KAVERI:
6507                 buffer[count++] = cpu_to_le32(0x00000000); /* XXX */
6508                 buffer[count++] = cpu_to_le32(0x00000000);
6509                 break;
6510         case CHIP_KABINI:
6511                 buffer[count++] = cpu_to_le32(0x00000000); /* XXX */
6512                 buffer[count++] = cpu_to_le32(0x00000000);
6513                 break;
6514         case CHIP_HAWAII:
6515                 buffer[count++] = 0x3a00161a;
6516                 buffer[count++] = 0x0000002e;
6517                 break;
6518         default:
6519                 buffer[count++] = cpu_to_le32(0x00000000);
6520                 buffer[count++] = cpu_to_le32(0x00000000);
6521                 break;
6522         }
6523
6524         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
6525         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
6526
6527         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
6528         buffer[count++] = cpu_to_le32(0);
6529 }
6530
6531 static void cik_init_pg(struct radeon_device *rdev)
6532 {
6533         if (rdev->pg_flags) {
6534                 cik_enable_sck_slowdown_on_pu(rdev, true);
6535                 cik_enable_sck_slowdown_on_pd(rdev, true);
6536                 if (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_PG) {
6537                         cik_init_gfx_cgpg(rdev);
6538                         cik_enable_cp_pg(rdev, true);
6539                         cik_enable_gds_pg(rdev, true);
6540                 }
6541                 cik_init_ao_cu_mask(rdev);
6542                 cik_update_gfx_pg(rdev, true);
6543         }
6544 }
6545
6546 static void cik_fini_pg(struct radeon_device *rdev)
6547 {
6548         if (rdev->pg_flags) {
6549                 cik_update_gfx_pg(rdev, false);
6550                 if (rdev->pg_flags & RADEON_PG_SUPPORT_GFX_PG) {
6551                         cik_enable_cp_pg(rdev, false);
6552                         cik_enable_gds_pg(rdev, false);
6553                 }
6554         }
6555 }
6556
6557 /*
6558  * Interrupts
6559  * Starting with r6xx, interrupts are handled via a ring buffer.
6560  * Ring buffers are areas of GPU accessible memory that the GPU
6561  * writes interrupt vectors into and the host reads vectors out of.
6562  * There is a rptr (read pointer) that determines where the
6563  * host is currently reading, and a wptr (write pointer)
6564  * which determines where the GPU has written.  When the
6565  * pointers are equal, the ring is idle.  When the GPU
6566  * writes vectors to the ring buffer, it increments the
6567  * wptr.  When there is an interrupt, the host then starts
6568  * fetching commands and processing them until the pointers are
6569  * equal again at which point it updates the rptr.
6570  */
6571
6572 /**
6573  * cik_enable_interrupts - Enable the interrupt ring buffer
6574  *
6575  * @rdev: radeon_device pointer
6576  *
6577  * Enable the interrupt ring buffer (CIK).
6578  */
6579 static void cik_enable_interrupts(struct radeon_device *rdev)
6580 {
6581         u32 ih_cntl = RREG32(IH_CNTL);
6582         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
6583
6584         ih_cntl |= ENABLE_INTR;
6585         ih_rb_cntl |= IH_RB_ENABLE;
6586         WREG32(IH_CNTL, ih_cntl);
6587         WREG32(IH_RB_CNTL, ih_rb_cntl);
6588         rdev->ih.enabled = true;
6589 }
6590
6591 /**
6592  * cik_disable_interrupts - Disable the interrupt ring buffer
6593  *
6594  * @rdev: radeon_device pointer
6595  *
6596  * Disable the interrupt ring buffer (CIK).
6597  */
6598 static void cik_disable_interrupts(struct radeon_device *rdev)
6599 {
6600         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
6601         u32 ih_cntl = RREG32(IH_CNTL);
6602
6603         ih_rb_cntl &= ~IH_RB_ENABLE;
6604         ih_cntl &= ~ENABLE_INTR;
6605         WREG32(IH_RB_CNTL, ih_rb_cntl);
6606         WREG32(IH_CNTL, ih_cntl);
6607         /* set rptr, wptr to 0 */
6608         WREG32(IH_RB_RPTR, 0);
6609         WREG32(IH_RB_WPTR, 0);
6610         rdev->ih.enabled = false;
6611         rdev->ih.rptr = 0;
6612 }
6613
6614 /**
6615  * cik_disable_interrupt_state - Disable all interrupt sources
6616  *
6617  * @rdev: radeon_device pointer
6618  *
6619  * Clear all interrupt enable bits used by the driver (CIK).
6620  */
6621 static void cik_disable_interrupt_state(struct radeon_device *rdev)
6622 {
6623         u32 tmp;
6624
6625         /* gfx ring */
6626         tmp = RREG32(CP_INT_CNTL_RING0) &
6627                 (CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
6628         WREG32(CP_INT_CNTL_RING0, tmp);
6629         /* sdma */
6630         tmp = RREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;
6631         WREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET, tmp);
6632         tmp = RREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
6633         WREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET, tmp);
6634         /* compute queues */
6635         WREG32(CP_ME1_PIPE0_INT_CNTL, 0);
6636         WREG32(CP_ME1_PIPE1_INT_CNTL, 0);
6637         WREG32(CP_ME1_PIPE2_INT_CNTL, 0);
6638         WREG32(CP_ME1_PIPE3_INT_CNTL, 0);
6639         WREG32(CP_ME2_PIPE0_INT_CNTL, 0);
6640         WREG32(CP_ME2_PIPE1_INT_CNTL, 0);
6641         WREG32(CP_ME2_PIPE2_INT_CNTL, 0);
6642         WREG32(CP_ME2_PIPE3_INT_CNTL, 0);
6643         /* grbm */
6644         WREG32(GRBM_INT_CNTL, 0);
6645         /* vline/vblank, etc. */
6646         WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
6647         WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
6648         if (rdev->num_crtc >= 4) {
6649                 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
6650                 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
6651         }
6652         if (rdev->num_crtc >= 6) {
6653                 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
6654                 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
6655         }
6656
6657         /* dac hotplug */
6658         WREG32(DAC_AUTODETECT_INT_CONTROL, 0);
6659
6660         /* digital hotplug */
6661         tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
6662         WREG32(DC_HPD1_INT_CONTROL, tmp);
6663         tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
6664         WREG32(DC_HPD2_INT_CONTROL, tmp);
6665         tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
6666         WREG32(DC_HPD3_INT_CONTROL, tmp);
6667         tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
6668         WREG32(DC_HPD4_INT_CONTROL, tmp);
6669         tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
6670         WREG32(DC_HPD5_INT_CONTROL, tmp);
6671         tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
6672         WREG32(DC_HPD6_INT_CONTROL, tmp);
6673
6674 }
6675
6676 /**
6677  * cik_irq_init - init and enable the interrupt ring
6678  *
6679  * @rdev: radeon_device pointer
6680  *
6681  * Allocate a ring buffer for the interrupt controller,
6682  * enable the RLC, disable interrupts, enable the IH
6683  * ring buffer and enable it (CIK).
6684  * Called at device load and reume.
6685  * Returns 0 for success, errors for failure.
6686  */
6687 static int cik_irq_init(struct radeon_device *rdev)
6688 {
6689         int ret = 0;
6690         int rb_bufsz;
6691         u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
6692
6693         /* allocate ring */
6694         ret = r600_ih_ring_alloc(rdev);
6695         if (ret)
6696                 return ret;
6697
6698         /* disable irqs */
6699         cik_disable_interrupts(rdev);
6700
6701         /* init rlc */
6702         ret = cik_rlc_resume(rdev);
6703         if (ret) {
6704                 r600_ih_ring_fini(rdev);
6705                 return ret;
6706         }
6707
6708         /* setup interrupt control */
6709         /* XXX this should actually be a bus address, not an MC address. same on older asics */
6710         WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
6711         interrupt_cntl = RREG32(INTERRUPT_CNTL);
6712         /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
6713          * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
6714          */
6715         interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
6716         /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
6717         interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
6718         WREG32(INTERRUPT_CNTL, interrupt_cntl);
6719
6720         WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
6721         rb_bufsz = order_base_2(rdev->ih.ring_size / 4);
6722
6723         ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
6724                       IH_WPTR_OVERFLOW_CLEAR |
6725                       (rb_bufsz << 1));
6726
6727         if (rdev->wb.enabled)
6728                 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;
6729
6730         /* set the writeback address whether it's enabled or not */
6731         WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
6732         WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
6733
6734         WREG32(IH_RB_CNTL, ih_rb_cntl);
6735
6736         /* set rptr, wptr to 0 */
6737         WREG32(IH_RB_RPTR, 0);
6738         WREG32(IH_RB_WPTR, 0);
6739
6740         /* Default settings for IH_CNTL (disabled at first) */
6741         ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10) | MC_VMID(0);
6742         /* RPTR_REARM only works if msi's are enabled */
6743         if (rdev->msi_enabled)
6744                 ih_cntl |= RPTR_REARM;
6745         WREG32(IH_CNTL, ih_cntl);
6746
6747         /* force the active interrupt state to all disabled */
6748         cik_disable_interrupt_state(rdev);
6749
6750         pci_set_master(rdev->pdev);
6751
6752         /* enable irqs */
6753         cik_enable_interrupts(rdev);
6754
6755         return ret;
6756 }
6757
6758 /**
6759  * cik_irq_set - enable/disable interrupt sources
6760  *
6761  * @rdev: radeon_device pointer
6762  *
6763  * Enable interrupt sources on the GPU (vblanks, hpd,
6764  * etc.) (CIK).
6765  * Returns 0 for success, errors for failure.
6766  */
6767 int cik_irq_set(struct radeon_device *rdev)
6768 {
6769         u32 cp_int_cntl;
6770         u32 cp_m1p0, cp_m1p1, cp_m1p2, cp_m1p3;
6771         u32 cp_m2p0, cp_m2p1, cp_m2p2, cp_m2p3;
6772         u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
6773         u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
6774         u32 grbm_int_cntl = 0;
6775         u32 dma_cntl, dma_cntl1;
6776         u32 thermal_int;
6777
6778         if (!rdev->irq.installed) {
6779                 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
6780                 return -EINVAL;
6781         }
6782         /* don't enable anything if the ih is disabled */
6783         if (!rdev->ih.enabled) {
6784                 cik_disable_interrupts(rdev);
6785                 /* force the active interrupt state to all disabled */
6786                 cik_disable_interrupt_state(rdev);
6787                 return 0;
6788         }
6789
6790         cp_int_cntl = RREG32(CP_INT_CNTL_RING0) &
6791                 (CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
6792         cp_int_cntl |= PRIV_INSTR_INT_ENABLE | PRIV_REG_INT_ENABLE;
6793
6794         hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
6795         hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
6796         hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
6797         hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
6798         hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
6799         hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
6800
6801         dma_cntl = RREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;
6802         dma_cntl1 = RREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
6803
6804         cp_m1p0 = RREG32(CP_ME1_PIPE0_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
6805         cp_m1p1 = RREG32(CP_ME1_PIPE1_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
6806         cp_m1p2 = RREG32(CP_ME1_PIPE2_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
6807         cp_m1p3 = RREG32(CP_ME1_PIPE3_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
6808         cp_m2p0 = RREG32(CP_ME2_PIPE0_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
6809         cp_m2p1 = RREG32(CP_ME2_PIPE1_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
6810         cp_m2p2 = RREG32(CP_ME2_PIPE2_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
6811         cp_m2p3 = RREG32(CP_ME2_PIPE3_INT_CNTL) & ~TIME_STAMP_INT_ENABLE;
6812
6813         if (rdev->flags & RADEON_IS_IGP)
6814                 thermal_int = RREG32_SMC(CG_THERMAL_INT_CTRL) &
6815                         ~(THERM_INTH_MASK | THERM_INTL_MASK);
6816         else
6817                 thermal_int = RREG32_SMC(CG_THERMAL_INT) &
6818                         ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
6819
6820         /* enable CP interrupts on all rings */
6821         if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
6822                 DRM_DEBUG("cik_irq_set: sw int gfx\n");
6823                 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
6824         }
6825         if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP1_INDEX])) {
6826                 struct radeon_ring *ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
6827                 DRM_DEBUG("si_irq_set: sw int cp1\n");
6828                 if (ring->me == 1) {
6829                         switch (ring->pipe) {
6830                         case 0:
6831                                 cp_m1p0 |= TIME_STAMP_INT_ENABLE;
6832                                 break;
6833                         case 1:
6834                                 cp_m1p1 |= TIME_STAMP_INT_ENABLE;
6835                                 break;
6836                         case 2:
6837                                 cp_m1p2 |= TIME_STAMP_INT_ENABLE;
6838                                 break;
6839                         case 3:
6840                                 cp_m1p2 |= TIME_STAMP_INT_ENABLE;
6841                                 break;
6842                         default:
6843                                 DRM_DEBUG("si_irq_set: sw int cp1 invalid pipe %d\n", ring->pipe);
6844                                 break;
6845                         }
6846                 } else if (ring->me == 2) {
6847                         switch (ring->pipe) {
6848                         case 0:
6849                                 cp_m2p0 |= TIME_STAMP_INT_ENABLE;
6850                                 break;
6851                         case 1:
6852                                 cp_m2p1 |= TIME_STAMP_INT_ENABLE;
6853                                 break;
6854                         case 2:
6855                                 cp_m2p2 |= TIME_STAMP_INT_ENABLE;
6856                                 break;
6857                         case 3:
6858                                 cp_m2p2 |= TIME_STAMP_INT_ENABLE;
6859                                 break;
6860                         default:
6861                                 DRM_DEBUG("si_irq_set: sw int cp1 invalid pipe %d\n", ring->pipe);
6862                                 break;
6863                         }
6864                 } else {
6865                         DRM_DEBUG("si_irq_set: sw int cp1 invalid me %d\n", ring->me);
6866                 }
6867         }
6868         if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP2_INDEX])) {
6869                 struct radeon_ring *ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
6870                 DRM_DEBUG("si_irq_set: sw int cp2\n");
6871                 if (ring->me == 1) {
6872                         switch (ring->pipe) {
6873                         case 0:
6874                                 cp_m1p0 |= TIME_STAMP_INT_ENABLE;
6875                                 break;
6876                         case 1:
6877                                 cp_m1p1 |= TIME_STAMP_INT_ENABLE;
6878                                 break;
6879                         case 2:
6880                                 cp_m1p2 |= TIME_STAMP_INT_ENABLE;
6881                                 break;
6882                         case 3:
6883                                 cp_m1p2 |= TIME_STAMP_INT_ENABLE;
6884                                 break;
6885                         default:
6886                                 DRM_DEBUG("si_irq_set: sw int cp2 invalid pipe %d\n", ring->pipe);
6887                                 break;
6888                         }
6889                 } else if (ring->me == 2) {
6890                         switch (ring->pipe) {
6891                         case 0:
6892                                 cp_m2p0 |= TIME_STAMP_INT_ENABLE;
6893                                 break;
6894                         case 1:
6895                                 cp_m2p1 |= TIME_STAMP_INT_ENABLE;
6896                                 break;
6897                         case 2:
6898                                 cp_m2p2 |= TIME_STAMP_INT_ENABLE;
6899                                 break;
6900                         case 3:
6901                                 cp_m2p2 |= TIME_STAMP_INT_ENABLE;
6902                                 break;
6903                         default:
6904                                 DRM_DEBUG("si_irq_set: sw int cp2 invalid pipe %d\n", ring->pipe);
6905                                 break;
6906                         }
6907                 } else {
6908                         DRM_DEBUG("si_irq_set: sw int cp2 invalid me %d\n", ring->me);
6909                 }
6910         }
6911
6912         if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) {
6913                 DRM_DEBUG("cik_irq_set: sw int dma\n");
6914                 dma_cntl |= TRAP_ENABLE;
6915         }
6916
6917         if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_DMA1_INDEX])) {
6918                 DRM_DEBUG("cik_irq_set: sw int dma1\n");
6919                 dma_cntl1 |= TRAP_ENABLE;
6920         }
6921
6922         if (rdev->irq.crtc_vblank_int[0] ||
6923             atomic_read(&rdev->irq.pflip[0])) {
6924                 DRM_DEBUG("cik_irq_set: vblank 0\n");
6925                 crtc1 |= VBLANK_INTERRUPT_MASK;
6926         }
6927         if (rdev->irq.crtc_vblank_int[1] ||
6928             atomic_read(&rdev->irq.pflip[1])) {
6929                 DRM_DEBUG("cik_irq_set: vblank 1\n");
6930                 crtc2 |= VBLANK_INTERRUPT_MASK;
6931         }
6932         if (rdev->irq.crtc_vblank_int[2] ||
6933             atomic_read(&rdev->irq.pflip[2])) {
6934                 DRM_DEBUG("cik_irq_set: vblank 2\n");
6935                 crtc3 |= VBLANK_INTERRUPT_MASK;
6936         }
6937         if (rdev->irq.crtc_vblank_int[3] ||
6938             atomic_read(&rdev->irq.pflip[3])) {
6939                 DRM_DEBUG("cik_irq_set: vblank 3\n");
6940                 crtc4 |= VBLANK_INTERRUPT_MASK;
6941         }
6942         if (rdev->irq.crtc_vblank_int[4] ||
6943             atomic_read(&rdev->irq.pflip[4])) {
6944                 DRM_DEBUG("cik_irq_set: vblank 4\n");
6945                 crtc5 |= VBLANK_INTERRUPT_MASK;
6946         }
6947         if (rdev->irq.crtc_vblank_int[5] ||
6948             atomic_read(&rdev->irq.pflip[5])) {
6949                 DRM_DEBUG("cik_irq_set: vblank 5\n");
6950                 crtc6 |= VBLANK_INTERRUPT_MASK;
6951         }
6952         if (rdev->irq.hpd[0]) {
6953                 DRM_DEBUG("cik_irq_set: hpd 1\n");
6954                 hpd1 |= DC_HPDx_INT_EN;
6955         }
6956         if (rdev->irq.hpd[1]) {
6957                 DRM_DEBUG("cik_irq_set: hpd 2\n");
6958                 hpd2 |= DC_HPDx_INT_EN;
6959         }
6960         if (rdev->irq.hpd[2]) {
6961                 DRM_DEBUG("cik_irq_set: hpd 3\n");
6962                 hpd3 |= DC_HPDx_INT_EN;
6963         }
6964         if (rdev->irq.hpd[3]) {
6965                 DRM_DEBUG("cik_irq_set: hpd 4\n");
6966                 hpd4 |= DC_HPDx_INT_EN;
6967         }
6968         if (rdev->irq.hpd[4]) {
6969                 DRM_DEBUG("cik_irq_set: hpd 5\n");
6970                 hpd5 |= DC_HPDx_INT_EN;
6971         }
6972         if (rdev->irq.hpd[5]) {
6973                 DRM_DEBUG("cik_irq_set: hpd 6\n");
6974                 hpd6 |= DC_HPDx_INT_EN;
6975         }
6976
6977         if (rdev->irq.dpm_thermal) {
6978                 DRM_DEBUG("dpm thermal\n");
6979                 if (rdev->flags & RADEON_IS_IGP)
6980                         thermal_int |= THERM_INTH_MASK | THERM_INTL_MASK;
6981                 else
6982                         thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
6983         }
6984
6985         WREG32(CP_INT_CNTL_RING0, cp_int_cntl);
6986
6987         WREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET, dma_cntl);
6988         WREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET, dma_cntl1);
6989
6990         WREG32(CP_ME1_PIPE0_INT_CNTL, cp_m1p0);
6991         WREG32(CP_ME1_PIPE1_INT_CNTL, cp_m1p1);
6992         WREG32(CP_ME1_PIPE2_INT_CNTL, cp_m1p2);
6993         WREG32(CP_ME1_PIPE3_INT_CNTL, cp_m1p3);
6994         WREG32(CP_ME2_PIPE0_INT_CNTL, cp_m2p0);
6995         WREG32(CP_ME2_PIPE1_INT_CNTL, cp_m2p1);
6996         WREG32(CP_ME2_PIPE2_INT_CNTL, cp_m2p2);
6997         WREG32(CP_ME2_PIPE3_INT_CNTL, cp_m2p3);
6998
6999         WREG32(GRBM_INT_CNTL, grbm_int_cntl);
7000
7001         WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
7002         WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
7003         if (rdev->num_crtc >= 4) {
7004                 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
7005                 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
7006         }
7007         if (rdev->num_crtc >= 6) {
7008                 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
7009                 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
7010         }
7011
7012         WREG32(DC_HPD1_INT_CONTROL, hpd1);
7013         WREG32(DC_HPD2_INT_CONTROL, hpd2);
7014         WREG32(DC_HPD3_INT_CONTROL, hpd3);
7015         WREG32(DC_HPD4_INT_CONTROL, hpd4);
7016         WREG32(DC_HPD5_INT_CONTROL, hpd5);
7017         WREG32(DC_HPD6_INT_CONTROL, hpd6);
7018
7019         if (rdev->flags & RADEON_IS_IGP)
7020                 WREG32_SMC(CG_THERMAL_INT_CTRL, thermal_int);
7021         else
7022                 WREG32_SMC(CG_THERMAL_INT, thermal_int);
7023
7024         return 0;
7025 }
7026
7027 /**
7028  * cik_irq_ack - ack interrupt sources
7029  *
7030  * @rdev: radeon_device pointer
7031  *
7032  * Ack interrupt sources on the GPU (vblanks, hpd,
7033  * etc.) (CIK).  Certain interrupts sources are sw
7034  * generated and do not require an explicit ack.
7035  */
7036 static inline void cik_irq_ack(struct radeon_device *rdev)
7037 {
7038         u32 tmp;
7039
7040         rdev->irq.stat_regs.cik.disp_int = RREG32(DISP_INTERRUPT_STATUS);
7041         rdev->irq.stat_regs.cik.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
7042         rdev->irq.stat_regs.cik.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
7043         rdev->irq.stat_regs.cik.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
7044         rdev->irq.stat_regs.cik.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
7045         rdev->irq.stat_regs.cik.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
7046         rdev->irq.stat_regs.cik.disp_int_cont6 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE6);
7047
7048         if (rdev->irq.stat_regs.cik.disp_int & LB_D1_VBLANK_INTERRUPT)
7049                 WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
7050         if (rdev->irq.stat_regs.cik.disp_int & LB_D1_VLINE_INTERRUPT)
7051                 WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
7052         if (rdev->irq.stat_regs.cik.disp_int_cont & LB_D2_VBLANK_INTERRUPT)
7053                 WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
7054         if (rdev->irq.stat_regs.cik.disp_int_cont & LB_D2_VLINE_INTERRUPT)
7055                 WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
7056
7057         if (rdev->num_crtc >= 4) {
7058                 if (rdev->irq.stat_regs.cik.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
7059                         WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
7060                 if (rdev->irq.stat_regs.cik.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
7061                         WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
7062                 if (rdev->irq.stat_regs.cik.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
7063                         WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
7064                 if (rdev->irq.stat_regs.cik.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
7065                         WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
7066         }
7067
7068         if (rdev->num_crtc >= 6) {
7069                 if (rdev->irq.stat_regs.cik.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
7070                         WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
7071                 if (rdev->irq.stat_regs.cik.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
7072                         WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
7073                 if (rdev->irq.stat_regs.cik.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
7074                         WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
7075                 if (rdev->irq.stat_regs.cik.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
7076                         WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
7077         }
7078
7079         if (rdev->irq.stat_regs.cik.disp_int & DC_HPD1_INTERRUPT) {
7080                 tmp = RREG32(DC_HPD1_INT_CONTROL);
7081                 tmp |= DC_HPDx_INT_ACK;
7082                 WREG32(DC_HPD1_INT_CONTROL, tmp);
7083         }
7084         if (rdev->irq.stat_regs.cik.disp_int_cont & DC_HPD2_INTERRUPT) {
7085                 tmp = RREG32(DC_HPD2_INT_CONTROL);
7086                 tmp |= DC_HPDx_INT_ACK;
7087                 WREG32(DC_HPD2_INT_CONTROL, tmp);
7088         }
7089         if (rdev->irq.stat_regs.cik.disp_int_cont2 & DC_HPD3_INTERRUPT) {
7090                 tmp = RREG32(DC_HPD3_INT_CONTROL);
7091                 tmp |= DC_HPDx_INT_ACK;
7092                 WREG32(DC_HPD3_INT_CONTROL, tmp);
7093         }
7094         if (rdev->irq.stat_regs.cik.disp_int_cont3 & DC_HPD4_INTERRUPT) {
7095                 tmp = RREG32(DC_HPD4_INT_CONTROL);
7096                 tmp |= DC_HPDx_INT_ACK;
7097                 WREG32(DC_HPD4_INT_CONTROL, tmp);
7098         }
7099         if (rdev->irq.stat_regs.cik.disp_int_cont4 & DC_HPD5_INTERRUPT) {
7100                 tmp = RREG32(DC_HPD5_INT_CONTROL);
7101                 tmp |= DC_HPDx_INT_ACK;
7102                 WREG32(DC_HPD5_INT_CONTROL, tmp);
7103         }
7104         if (rdev->irq.stat_regs.cik.disp_int_cont5 & DC_HPD6_INTERRUPT) {
7105                 tmp = RREG32(DC_HPD5_INT_CONTROL);
7106                 tmp |= DC_HPDx_INT_ACK;
7107                 WREG32(DC_HPD6_INT_CONTROL, tmp);
7108         }
7109 }
7110
7111 /**
7112  * cik_irq_disable - disable interrupts
7113  *
7114  * @rdev: radeon_device pointer
7115  *
7116  * Disable interrupts on the hw (CIK).
7117  */
7118 static void cik_irq_disable(struct radeon_device *rdev)
7119 {
7120         cik_disable_interrupts(rdev);
7121         /* Wait and acknowledge irq */
7122         mdelay(1);
7123         cik_irq_ack(rdev);
7124         cik_disable_interrupt_state(rdev);
7125 }
7126
7127 /**
7128  * cik_irq_disable - disable interrupts for suspend
7129  *
7130  * @rdev: radeon_device pointer
7131  *
7132  * Disable interrupts and stop the RLC (CIK).
7133  * Used for suspend.
7134  */
7135 static void cik_irq_suspend(struct radeon_device *rdev)
7136 {
7137         cik_irq_disable(rdev);
7138         cik_rlc_stop(rdev);
7139 }
7140
7141 /**
7142  * cik_irq_fini - tear down interrupt support
7143  *
7144  * @rdev: radeon_device pointer
7145  *
7146  * Disable interrupts on the hw and free the IH ring
7147  * buffer (CIK).
7148  * Used for driver unload.
7149  */
7150 static void cik_irq_fini(struct radeon_device *rdev)
7151 {
7152         cik_irq_suspend(rdev);
7153         r600_ih_ring_fini(rdev);
7154 }
7155
7156 /**
7157  * cik_get_ih_wptr - get the IH ring buffer wptr
7158  *
7159  * @rdev: radeon_device pointer
7160  *
7161  * Get the IH ring buffer wptr from either the register
7162  * or the writeback memory buffer (CIK).  Also check for
7163  * ring buffer overflow and deal with it.
7164  * Used by cik_irq_process().
7165  * Returns the value of the wptr.
7166  */
7167 static inline u32 cik_get_ih_wptr(struct radeon_device *rdev)
7168 {
7169         u32 wptr, tmp;
7170
7171         if (rdev->wb.enabled)
7172                 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
7173         else
7174                 wptr = RREG32(IH_RB_WPTR);
7175
7176         if (wptr & RB_OVERFLOW) {
7177                 /* When a ring buffer overflow happen start parsing interrupt
7178                  * from the last not overwritten vector (wptr + 16). Hopefully
7179                  * this should allow us to catchup.
7180                  */
7181                 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
7182                         wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
7183                 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
7184                 tmp = RREG32(IH_RB_CNTL);
7185                 tmp |= IH_WPTR_OVERFLOW_CLEAR;
7186                 WREG32(IH_RB_CNTL, tmp);
7187         }
7188         return (wptr & rdev->ih.ptr_mask);
7189 }
7190
7191 /*        CIK IV Ring
7192  * Each IV ring entry is 128 bits:
7193  * [7:0]    - interrupt source id
7194  * [31:8]   - reserved
7195  * [59:32]  - interrupt source data
7196  * [63:60]  - reserved
7197  * [71:64]  - RINGID
7198  *            CP:
7199  *            ME_ID [1:0], PIPE_ID[1:0], QUEUE_ID[2:0]
7200  *            QUEUE_ID - for compute, which of the 8 queues owned by the dispatcher
7201  *                     - for gfx, hw shader state (0=PS...5=LS, 6=CS)
7202  *            ME_ID - 0 = gfx, 1 = first 4 CS pipes, 2 = second 4 CS pipes
7203  *            PIPE_ID - ME0 0=3D
7204  *                    - ME1&2 compute dispatcher (4 pipes each)
7205  *            SDMA:
7206  *            INSTANCE_ID [1:0], QUEUE_ID[1:0]
7207  *            INSTANCE_ID - 0 = sdma0, 1 = sdma1
7208  *            QUEUE_ID - 0 = gfx, 1 = rlc0, 2 = rlc1
7209  * [79:72]  - VMID
7210  * [95:80]  - PASID
7211  * [127:96] - reserved
7212  */
7213 /**
7214  * cik_irq_process - interrupt handler
7215  *
7216  * @rdev: radeon_device pointer
7217  *
7218  * Interrupt hander (CIK).  Walk the IH ring,
7219  * ack interrupts and schedule work to handle
7220  * interrupt events.
7221  * Returns irq process return code.
7222  */
7223 int cik_irq_process(struct radeon_device *rdev)
7224 {
7225         struct radeon_ring *cp1_ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
7226         struct radeon_ring *cp2_ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
7227         u32 wptr;
7228         u32 rptr;
7229         u32 src_id, src_data, ring_id;
7230         u8 me_id, pipe_id, queue_id;
7231         u32 ring_index;
7232         bool queue_hotplug = false;
7233         bool queue_reset = false;
7234         u32 addr, status, mc_client;
7235         bool queue_thermal = false;
7236
7237         if (!rdev->ih.enabled || rdev->shutdown)
7238                 return IRQ_NONE;
7239
7240         wptr = cik_get_ih_wptr(rdev);
7241
7242 restart_ih:
7243         /* is somebody else already processing irqs? */
7244         if (atomic_xchg(&rdev->ih.lock, 1))
7245                 return IRQ_NONE;
7246
7247         rptr = rdev->ih.rptr;
7248         DRM_DEBUG("cik_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
7249
7250         /* Order reading of wptr vs. reading of IH ring data */
7251         rmb();
7252
7253         /* display interrupts */
7254         cik_irq_ack(rdev);
7255
7256         while (rptr != wptr) {
7257                 /* wptr/rptr are in bytes! */
7258                 ring_index = rptr / 4;
7259                 src_id =  le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
7260                 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
7261                 ring_id = le32_to_cpu(rdev->ih.ring[ring_index + 2]) & 0xff;
7262
7263                 switch (src_id) {
7264                 case 1: /* D1 vblank/vline */
7265                         switch (src_data) {
7266                         case 0: /* D1 vblank */
7267                                 if (rdev->irq.stat_regs.cik.disp_int & LB_D1_VBLANK_INTERRUPT) {
7268                                         if (rdev->irq.crtc_vblank_int[0]) {
7269                                                 drm_handle_vblank(rdev->ddev, 0);
7270                                                 rdev->pm.vblank_sync = true;
7271                                                 wake_up(&rdev->irq.vblank_queue);
7272                                         }
7273                                         if (atomic_read(&rdev->irq.pflip[0]))
7274                                                 radeon_crtc_handle_flip(rdev, 0);
7275                                         rdev->irq.stat_regs.cik.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
7276                                         DRM_DEBUG("IH: D1 vblank\n");
7277                                 }
7278                                 break;
7279                         case 1: /* D1 vline */
7280                                 if (rdev->irq.stat_regs.cik.disp_int & LB_D1_VLINE_INTERRUPT) {
7281                                         rdev->irq.stat_regs.cik.disp_int &= ~LB_D1_VLINE_INTERRUPT;
7282                                         DRM_DEBUG("IH: D1 vline\n");
7283                                 }
7284                                 break;
7285                         default:
7286                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
7287                                 break;
7288                         }
7289                         break;
7290                 case 2: /* D2 vblank/vline */
7291                         switch (src_data) {
7292                         case 0: /* D2 vblank */
7293                                 if (rdev->irq.stat_regs.cik.disp_int_cont & LB_D2_VBLANK_INTERRUPT) {
7294                                         if (rdev->irq.crtc_vblank_int[1]) {
7295                                                 drm_handle_vblank(rdev->ddev, 1);
7296                                                 rdev->pm.vblank_sync = true;
7297                                                 wake_up(&rdev->irq.vblank_queue);
7298                                         }
7299                                         if (atomic_read(&rdev->irq.pflip[1]))
7300                                                 radeon_crtc_handle_flip(rdev, 1);
7301                                         rdev->irq.stat_regs.cik.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
7302                                         DRM_DEBUG("IH: D2 vblank\n");
7303                                 }
7304                                 break;
7305                         case 1: /* D2 vline */
7306                                 if (rdev->irq.stat_regs.cik.disp_int_cont & LB_D2_VLINE_INTERRUPT) {
7307                                         rdev->irq.stat_regs.cik.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
7308                                         DRM_DEBUG("IH: D2 vline\n");
7309                                 }
7310                                 break;
7311                         default:
7312                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
7313                                 break;
7314                         }
7315                         break;
7316                 case 3: /* D3 vblank/vline */
7317                         switch (src_data) {
7318                         case 0: /* D3 vblank */
7319                                 if (rdev->irq.stat_regs.cik.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) {
7320                                         if (rdev->irq.crtc_vblank_int[2]) {
7321                                                 drm_handle_vblank(rdev->ddev, 2);
7322                                                 rdev->pm.vblank_sync = true;
7323                                                 wake_up(&rdev->irq.vblank_queue);
7324                                         }
7325                                         if (atomic_read(&rdev->irq.pflip[2]))
7326                                                 radeon_crtc_handle_flip(rdev, 2);
7327                                         rdev->irq.stat_regs.cik.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
7328                                         DRM_DEBUG("IH: D3 vblank\n");
7329                                 }
7330                                 break;
7331                         case 1: /* D3 vline */
7332                                 if (rdev->irq.stat_regs.cik.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) {
7333                                         rdev->irq.stat_regs.cik.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
7334                                         DRM_DEBUG("IH: D3 vline\n");
7335                                 }
7336                                 break;
7337                         default:
7338                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
7339                                 break;
7340                         }
7341                         break;
7342                 case 4: /* D4 vblank/vline */
7343                         switch (src_data) {
7344                         case 0: /* D4 vblank */
7345                                 if (rdev->irq.stat_regs.cik.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) {
7346                                         if (rdev->irq.crtc_vblank_int[3]) {
7347                                                 drm_handle_vblank(rdev->ddev, 3);
7348                                                 rdev->pm.vblank_sync = true;
7349                                                 wake_up(&rdev->irq.vblank_queue);
7350                                         }
7351                                         if (atomic_read(&rdev->irq.pflip[3]))
7352                                                 radeon_crtc_handle_flip(rdev, 3);
7353                                         rdev->irq.stat_regs.cik.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
7354                                         DRM_DEBUG("IH: D4 vblank\n");
7355                                 }
7356                                 break;
7357                         case 1: /* D4 vline */
7358                                 if (rdev->irq.stat_regs.cik.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) {
7359                                         rdev->irq.stat_regs.cik.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
7360                                         DRM_DEBUG("IH: D4 vline\n");
7361                                 }
7362                                 break;
7363                         default:
7364                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
7365                                 break;
7366                         }
7367                         break;
7368                 case 5: /* D5 vblank/vline */
7369                         switch (src_data) {
7370                         case 0: /* D5 vblank */
7371                                 if (rdev->irq.stat_regs.cik.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) {
7372                                         if (rdev->irq.crtc_vblank_int[4]) {
7373                                                 drm_handle_vblank(rdev->ddev, 4);
7374                                                 rdev->pm.vblank_sync = true;
7375                                                 wake_up(&rdev->irq.vblank_queue);
7376                                         }
7377                                         if (atomic_read(&rdev->irq.pflip[4]))
7378                                                 radeon_crtc_handle_flip(rdev, 4);
7379                                         rdev->irq.stat_regs.cik.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
7380                                         DRM_DEBUG("IH: D5 vblank\n");
7381                                 }
7382                                 break;
7383                         case 1: /* D5 vline */
7384                                 if (rdev->irq.stat_regs.cik.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) {
7385                                         rdev->irq.stat_regs.cik.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
7386                                         DRM_DEBUG("IH: D5 vline\n");
7387                                 }
7388                                 break;
7389                         default:
7390                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
7391                                 break;
7392                         }
7393                         break;
7394                 case 6: /* D6 vblank/vline */
7395                         switch (src_data) {
7396                         case 0: /* D6 vblank */
7397                                 if (rdev->irq.stat_regs.cik.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) {
7398                                         if (rdev->irq.crtc_vblank_int[5]) {
7399                                                 drm_handle_vblank(rdev->ddev, 5);
7400                                                 rdev->pm.vblank_sync = true;
7401                                                 wake_up(&rdev->irq.vblank_queue);
7402                                         }
7403                                         if (atomic_read(&rdev->irq.pflip[5]))
7404                                                 radeon_crtc_handle_flip(rdev, 5);
7405                                         rdev->irq.stat_regs.cik.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
7406                                         DRM_DEBUG("IH: D6 vblank\n");
7407                                 }
7408                                 break;
7409                         case 1: /* D6 vline */
7410                                 if (rdev->irq.stat_regs.cik.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) {
7411                                         rdev->irq.stat_regs.cik.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
7412                                         DRM_DEBUG("IH: D6 vline\n");
7413                                 }
7414                                 break;
7415                         default:
7416                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
7417                                 break;
7418                         }
7419                         break;
7420                 case 42: /* HPD hotplug */
7421                         switch (src_data) {
7422                         case 0:
7423                                 if (rdev->irq.stat_regs.cik.disp_int & DC_HPD1_INTERRUPT) {
7424                                         rdev->irq.stat_regs.cik.disp_int &= ~DC_HPD1_INTERRUPT;
7425                                         queue_hotplug = true;
7426                                         DRM_DEBUG("IH: HPD1\n");
7427                                 }
7428                                 break;
7429                         case 1:
7430                                 if (rdev->irq.stat_regs.cik.disp_int_cont & DC_HPD2_INTERRUPT) {
7431                                         rdev->irq.stat_regs.cik.disp_int_cont &= ~DC_HPD2_INTERRUPT;
7432                                         queue_hotplug = true;
7433                                         DRM_DEBUG("IH: HPD2\n");
7434                                 }
7435                                 break;
7436                         case 2:
7437                                 if (rdev->irq.stat_regs.cik.disp_int_cont2 & DC_HPD3_INTERRUPT) {
7438                                         rdev->irq.stat_regs.cik.disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
7439                                         queue_hotplug = true;
7440                                         DRM_DEBUG("IH: HPD3\n");
7441                                 }
7442                                 break;
7443                         case 3:
7444                                 if (rdev->irq.stat_regs.cik.disp_int_cont3 & DC_HPD4_INTERRUPT) {
7445                                         rdev->irq.stat_regs.cik.disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
7446                                         queue_hotplug = true;
7447                                         DRM_DEBUG("IH: HPD4\n");
7448                                 }
7449                                 break;
7450                         case 4:
7451                                 if (rdev->irq.stat_regs.cik.disp_int_cont4 & DC_HPD5_INTERRUPT) {
7452                                         rdev->irq.stat_regs.cik.disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
7453                                         queue_hotplug = true;
7454                                         DRM_DEBUG("IH: HPD5\n");
7455                                 }
7456                                 break;
7457                         case 5:
7458                                 if (rdev->irq.stat_regs.cik.disp_int_cont5 & DC_HPD6_INTERRUPT) {
7459                                         rdev->irq.stat_regs.cik.disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
7460                                         queue_hotplug = true;
7461                                         DRM_DEBUG("IH: HPD6\n");
7462                                 }
7463                                 break;
7464                         default:
7465                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
7466                                 break;
7467                         }
7468                         break;
7469                 case 124: /* UVD */
7470                         DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data);
7471                         radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX);
7472                         break;
7473                 case 146:
7474                 case 147:
7475                         addr = RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR);
7476                         status = RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS);
7477                         mc_client = RREG32(VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);
7478                         dev_err(rdev->dev, "GPU fault detected: %d 0x%08x\n", src_id, src_data);
7479                         dev_err(rdev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
7480                                 addr);
7481                         dev_err(rdev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
7482                                 status);
7483                         cik_vm_decode_fault(rdev, status, addr, mc_client);
7484                         /* reset addr and status */
7485                         WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1);
7486                         break;
7487                 case 176: /* GFX RB CP_INT */
7488                 case 177: /* GFX IB CP_INT */
7489                         radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
7490                         break;
7491                 case 181: /* CP EOP event */
7492                         DRM_DEBUG("IH: CP EOP\n");
7493                         /* XXX check the bitfield order! */
7494                         me_id = (ring_id & 0x60) >> 5;
7495                         pipe_id = (ring_id & 0x18) >> 3;
7496                         queue_id = (ring_id & 0x7) >> 0;
7497                         switch (me_id) {
7498                         case 0:
7499                                 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
7500                                 break;
7501                         case 1:
7502                         case 2:
7503                                 if ((cp1_ring->me == me_id) & (cp1_ring->pipe == pipe_id))
7504                                         radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
7505                                 if ((cp2_ring->me == me_id) & (cp2_ring->pipe == pipe_id))
7506                                         radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
7507                                 break;
7508                         }
7509                         break;
7510                 case 184: /* CP Privileged reg access */
7511                         DRM_ERROR("Illegal register access in command stream\n");
7512                         /* XXX check the bitfield order! */
7513                         me_id = (ring_id & 0x60) >> 5;
7514                         pipe_id = (ring_id & 0x18) >> 3;
7515                         queue_id = (ring_id & 0x7) >> 0;
7516                         switch (me_id) {
7517                         case 0:
7518                                 /* This results in a full GPU reset, but all we need to do is soft
7519                                  * reset the CP for gfx
7520                                  */
7521                                 queue_reset = true;
7522                                 break;
7523                         case 1:
7524                                 /* XXX compute */
7525                                 queue_reset = true;
7526                                 break;
7527                         case 2:
7528                                 /* XXX compute */
7529                                 queue_reset = true;
7530                                 break;
7531                         }
7532                         break;
7533                 case 185: /* CP Privileged inst */
7534                         DRM_ERROR("Illegal instruction in command stream\n");
7535                         /* XXX check the bitfield order! */
7536                         me_id = (ring_id & 0x60) >> 5;
7537                         pipe_id = (ring_id & 0x18) >> 3;
7538                         queue_id = (ring_id & 0x7) >> 0;
7539                         switch (me_id) {
7540                         case 0:
7541                                 /* This results in a full GPU reset, but all we need to do is soft
7542                                  * reset the CP for gfx
7543                                  */
7544                                 queue_reset = true;
7545                                 break;
7546                         case 1:
7547                                 /* XXX compute */
7548                                 queue_reset = true;
7549                                 break;
7550                         case 2:
7551                                 /* XXX compute */
7552                                 queue_reset = true;
7553                                 break;
7554                         }
7555                         break;
7556                 case 224: /* SDMA trap event */
7557                         /* XXX check the bitfield order! */
7558                         me_id = (ring_id & 0x3) >> 0;
7559                         queue_id = (ring_id & 0xc) >> 2;
7560                         DRM_DEBUG("IH: SDMA trap\n");
7561                         switch (me_id) {
7562                         case 0:
7563                                 switch (queue_id) {
7564                                 case 0:
7565                                         radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX);
7566                                         break;
7567                                 case 1:
7568                                         /* XXX compute */
7569                                         break;
7570                                 case 2:
7571                                         /* XXX compute */
7572                                         break;
7573                                 }
7574                                 break;
7575                         case 1:
7576                                 switch (queue_id) {
7577                                 case 0:
7578                                         radeon_fence_process(rdev, CAYMAN_RING_TYPE_DMA1_INDEX);
7579                                         break;
7580                                 case 1:
7581                                         /* XXX compute */
7582                                         break;
7583                                 case 2:
7584                                         /* XXX compute */
7585                                         break;
7586                                 }
7587                                 break;
7588                         }
7589                         break;
7590                 case 230: /* thermal low to high */
7591                         DRM_DEBUG("IH: thermal low to high\n");
7592                         rdev->pm.dpm.thermal.high_to_low = false;
7593                         queue_thermal = true;
7594                         break;
7595                 case 231: /* thermal high to low */
7596                         DRM_DEBUG("IH: thermal high to low\n");
7597                         rdev->pm.dpm.thermal.high_to_low = true;
7598                         queue_thermal = true;
7599                         break;
7600                 case 233: /* GUI IDLE */
7601                         DRM_DEBUG("IH: GUI idle\n");
7602                         break;
7603                 case 241: /* SDMA Privileged inst */
7604                 case 247: /* SDMA Privileged inst */
7605                         DRM_ERROR("Illegal instruction in SDMA command stream\n");
7606                         /* XXX check the bitfield order! */
7607                         me_id = (ring_id & 0x3) >> 0;
7608                         queue_id = (ring_id & 0xc) >> 2;
7609                         switch (me_id) {
7610                         case 0:
7611                                 switch (queue_id) {
7612                                 case 0:
7613                                         queue_reset = true;
7614                                         break;
7615                                 case 1:
7616                                         /* XXX compute */
7617                                         queue_reset = true;
7618                                         break;
7619                                 case 2:
7620                                         /* XXX compute */
7621                                         queue_reset = true;
7622                                         break;
7623                                 }
7624                                 break;
7625                         case 1:
7626                                 switch (queue_id) {
7627                                 case 0:
7628                                         queue_reset = true;
7629                                         break;
7630                                 case 1:
7631                                         /* XXX compute */
7632                                         queue_reset = true;
7633                                         break;
7634                                 case 2:
7635                                         /* XXX compute */
7636                                         queue_reset = true;
7637                                         break;
7638                                 }
7639                                 break;
7640                         }
7641                         break;
7642                 default:
7643                         DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
7644                         break;
7645                 }
7646
7647                 /* wptr/rptr are in bytes! */
7648                 rptr += 16;
7649                 rptr &= rdev->ih.ptr_mask;
7650         }
7651         if (queue_hotplug)
7652                 schedule_work(&rdev->hotplug_work);
7653         if (queue_reset)
7654                 schedule_work(&rdev->reset_work);
7655         if (queue_thermal)
7656                 schedule_work(&rdev->pm.dpm.thermal.work);
7657         rdev->ih.rptr = rptr;
7658         WREG32(IH_RB_RPTR, rdev->ih.rptr);
7659         atomic_set(&rdev->ih.lock, 0);
7660
7661         /* make sure wptr hasn't changed while processing */
7662         wptr = cik_get_ih_wptr(rdev);
7663         if (wptr != rptr)
7664                 goto restart_ih;
7665
7666         return IRQ_HANDLED;
7667 }
7668
7669 /*
7670  * startup/shutdown callbacks
7671  */
7672 /**
7673  * cik_startup - program the asic to a functional state
7674  *
7675  * @rdev: radeon_device pointer
7676  *
7677  * Programs the asic to a functional state (CIK).
7678  * Called by cik_init() and cik_resume().
7679  * Returns 0 for success, error for failure.
7680  */
7681 static int cik_startup(struct radeon_device *rdev)
7682 {
7683         struct radeon_ring *ring;
7684         int r;
7685
7686         /* enable pcie gen2/3 link */
7687         cik_pcie_gen3_enable(rdev);
7688         /* enable aspm */
7689         cik_program_aspm(rdev);
7690
7691         /* scratch needs to be initialized before MC */
7692         r = r600_vram_scratch_init(rdev);
7693         if (r)
7694                 return r;
7695
7696         cik_mc_program(rdev);
7697
7698         if (!(rdev->flags & RADEON_IS_IGP) && !rdev->pm.dpm_enabled) {
7699                 r = ci_mc_load_microcode(rdev);
7700                 if (r) {
7701                         DRM_ERROR("Failed to load MC firmware!\n");
7702                         return r;
7703                 }
7704         }
7705
7706         r = cik_pcie_gart_enable(rdev);
7707         if (r)
7708                 return r;
7709         cik_gpu_init(rdev);
7710
7711         /* allocate rlc buffers */
7712         if (rdev->flags & RADEON_IS_IGP) {
7713                 if (rdev->family == CHIP_KAVERI) {
7714                         rdev->rlc.reg_list = spectre_rlc_save_restore_register_list;
7715                         rdev->rlc.reg_list_size =
7716                                 (u32)ARRAY_SIZE(spectre_rlc_save_restore_register_list);
7717                 } else {
7718                         rdev->rlc.reg_list = kalindi_rlc_save_restore_register_list;
7719                         rdev->rlc.reg_list_size =
7720                                 (u32)ARRAY_SIZE(kalindi_rlc_save_restore_register_list);
7721                 }
7722         }
7723         rdev->rlc.cs_data = ci_cs_data;
7724         rdev->rlc.cp_table_size = CP_ME_TABLE_SIZE * 5 * 4;
7725         r = sumo_rlc_init(rdev);
7726         if (r) {
7727                 DRM_ERROR("Failed to init rlc BOs!\n");
7728                 return r;
7729         }
7730
7731         /* allocate wb buffer */
7732         r = radeon_wb_init(rdev);
7733         if (r)
7734                 return r;
7735
7736         /* allocate mec buffers */
7737         r = cik_mec_init(rdev);
7738         if (r) {
7739                 DRM_ERROR("Failed to init MEC BOs!\n");
7740                 return r;
7741         }
7742
7743         r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
7744         if (r) {
7745                 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
7746                 return r;
7747         }
7748
7749         r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
7750         if (r) {
7751                 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
7752                 return r;
7753         }
7754
7755         r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
7756         if (r) {
7757                 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
7758                 return r;
7759         }
7760
7761         r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
7762         if (r) {
7763                 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
7764                 return r;
7765         }
7766
7767         r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_DMA1_INDEX);
7768         if (r) {
7769                 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
7770                 return r;
7771         }
7772
7773         r = radeon_uvd_resume(rdev);
7774         if (!r) {
7775                 r = uvd_v4_2_resume(rdev);
7776                 if (!r) {
7777                         r = radeon_fence_driver_start_ring(rdev,
7778                                                            R600_RING_TYPE_UVD_INDEX);
7779                         if (r)
7780                                 dev_err(rdev->dev, "UVD fences init error (%d).\n", r);
7781                 }
7782         }
7783         if (r)
7784                 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
7785
7786         /* Enable IRQ */
7787         if (!rdev->irq.installed) {
7788                 r = radeon_irq_kms_init(rdev);
7789                 if (r)
7790                         return r;
7791         }
7792
7793         r = cik_irq_init(rdev);
7794         if (r) {
7795                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
7796                 radeon_irq_kms_fini(rdev);
7797                 return r;
7798         }
7799         cik_irq_set(rdev);
7800
7801         ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
7802         r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
7803                              PACKET3(PACKET3_NOP, 0x3FFF));
7804         if (r)
7805                 return r;
7806
7807         /* set up the compute queues */
7808         /* type-2 packets are deprecated on MEC, use type-3 instead */
7809         ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
7810         r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP1_RPTR_OFFSET,
7811                              PACKET3(PACKET3_NOP, 0x3FFF));
7812         if (r)
7813                 return r;
7814         ring->me = 1; /* first MEC */
7815         ring->pipe = 0; /* first pipe */
7816         ring->queue = 0; /* first queue */
7817         ring->wptr_offs = CIK_WB_CP1_WPTR_OFFSET;
7818
7819         /* type-2 packets are deprecated on MEC, use type-3 instead */
7820         ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
7821         r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP2_RPTR_OFFSET,
7822                              PACKET3(PACKET3_NOP, 0x3FFF));
7823         if (r)
7824                 return r;
7825         /* dGPU only have 1 MEC */
7826         ring->me = 1; /* first MEC */
7827         ring->pipe = 0; /* first pipe */
7828         ring->queue = 1; /* second queue */
7829         ring->wptr_offs = CIK_WB_CP2_WPTR_OFFSET;
7830
7831         ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
7832         r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
7833                              SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0));
7834         if (r)
7835                 return r;
7836
7837         ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
7838         r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET,
7839                              SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0));
7840         if (r)
7841                 return r;
7842
7843         r = cik_cp_resume(rdev);
7844         if (r)
7845                 return r;
7846
7847         r = cik_sdma_resume(rdev);
7848         if (r)
7849                 return r;
7850
7851         ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
7852         if (ring->ring_size) {
7853                 r = radeon_ring_init(rdev, ring, ring->ring_size, 0,
7854                                      RADEON_CP_PACKET2);
7855                 if (!r)
7856                         r = uvd_v1_0_init(rdev);
7857                 if (r)
7858                         DRM_ERROR("radeon: failed initializing UVD (%d).\n", r);
7859         }
7860
7861         r = radeon_ib_pool_init(rdev);
7862         if (r) {
7863                 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
7864                 return r;
7865         }
7866
7867         r = radeon_vm_manager_init(rdev);
7868         if (r) {
7869                 dev_err(rdev->dev, "vm manager initialization failed (%d).\n", r);
7870                 return r;
7871         }
7872
7873         r = dce6_audio_init(rdev);
7874         if (r)
7875                 return r;
7876
7877         return 0;
7878 }
7879
7880 /**
7881  * cik_resume - resume the asic to a functional state
7882  *
7883  * @rdev: radeon_device pointer
7884  *
7885  * Programs the asic to a functional state (CIK).
7886  * Called at resume.
7887  * Returns 0 for success, error for failure.
7888  */
7889 int cik_resume(struct radeon_device *rdev)
7890 {
7891         int r;
7892
7893         /* post card */
7894         atom_asic_init(rdev->mode_info.atom_context);
7895
7896         /* init golden registers */
7897         cik_init_golden_registers(rdev);
7898
7899         radeon_pm_resume(rdev);
7900
7901         rdev->accel_working = true;
7902         r = cik_startup(rdev);
7903         if (r) {
7904                 DRM_ERROR("cik startup failed on resume\n");
7905                 rdev->accel_working = false;
7906                 return r;
7907         }
7908
7909         return r;
7910
7911 }
7912
7913 /**
7914  * cik_suspend - suspend the asic
7915  *
7916  * @rdev: radeon_device pointer
7917  *
7918  * Bring the chip into a state suitable for suspend (CIK).
7919  * Called at suspend.
7920  * Returns 0 for success.
7921  */
7922 int cik_suspend(struct radeon_device *rdev)
7923 {
7924         radeon_pm_suspend(rdev);
7925         dce6_audio_fini(rdev);
7926         radeon_vm_manager_fini(rdev);
7927         cik_cp_enable(rdev, false);
7928         cik_sdma_enable(rdev, false);
7929         uvd_v1_0_fini(rdev);
7930         radeon_uvd_suspend(rdev);
7931         cik_fini_pg(rdev);
7932         cik_fini_cg(rdev);
7933         cik_irq_suspend(rdev);
7934         radeon_wb_disable(rdev);
7935         cik_pcie_gart_disable(rdev);
7936         return 0;
7937 }
7938
7939 /* Plan is to move initialization in that function and use
7940  * helper function so that radeon_device_init pretty much
7941  * do nothing more than calling asic specific function. This
7942  * should also allow to remove a bunch of callback function
7943  * like vram_info.
7944  */
7945 /**
7946  * cik_init - asic specific driver and hw init
7947  *
7948  * @rdev: radeon_device pointer
7949  *
7950  * Setup asic specific driver variables and program the hw
7951  * to a functional state (CIK).
7952  * Called at driver startup.
7953  * Returns 0 for success, errors for failure.
7954  */
7955 int cik_init(struct radeon_device *rdev)
7956 {
7957         struct radeon_ring *ring;
7958         int r;
7959
7960         /* Read BIOS */
7961         if (!radeon_get_bios(rdev)) {
7962                 if (ASIC_IS_AVIVO(rdev))
7963                         return -EINVAL;
7964         }
7965         /* Must be an ATOMBIOS */
7966         if (!rdev->is_atom_bios) {
7967                 dev_err(rdev->dev, "Expecting atombios for cayman GPU\n");
7968                 return -EINVAL;
7969         }
7970         r = radeon_atombios_init(rdev);
7971         if (r)
7972                 return r;
7973
7974         /* Post card if necessary */
7975         if (!radeon_card_posted(rdev)) {
7976                 if (!rdev->bios) {
7977                         dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
7978                         return -EINVAL;
7979                 }
7980                 DRM_INFO("GPU not posted. posting now...\n");
7981                 atom_asic_init(rdev->mode_info.atom_context);
7982         }
7983         /* init golden registers */
7984         cik_init_golden_registers(rdev);
7985         /* Initialize scratch registers */
7986         cik_scratch_init(rdev);
7987         /* Initialize surface registers */
7988         radeon_surface_init(rdev);
7989         /* Initialize clocks */
7990         radeon_get_clock_info(rdev->ddev);
7991
7992         /* Fence driver */
7993         r = radeon_fence_driver_init(rdev);
7994         if (r)
7995                 return r;
7996
7997         /* initialize memory controller */
7998         r = cik_mc_init(rdev);
7999         if (r)
8000                 return r;
8001         /* Memory manager */
8002         r = radeon_bo_init(rdev);
8003         if (r)
8004                 return r;
8005
8006         if (rdev->flags & RADEON_IS_IGP) {
8007                 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw ||
8008                     !rdev->mec_fw || !rdev->sdma_fw || !rdev->rlc_fw) {
8009                         r = cik_init_microcode(rdev);
8010                         if (r) {
8011                                 DRM_ERROR("Failed to load firmware!\n");
8012                                 return r;
8013                         }
8014                 }
8015         } else {
8016                 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw ||
8017                     !rdev->mec_fw || !rdev->sdma_fw || !rdev->rlc_fw ||
8018                     !rdev->mc_fw) {
8019                         r = cik_init_microcode(rdev);
8020                         if (r) {
8021                                 DRM_ERROR("Failed to load firmware!\n");
8022                                 return r;
8023                         }
8024                 }
8025         }
8026
8027         /* Initialize power management */
8028         radeon_pm_init(rdev);
8029
8030         ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
8031         ring->ring_obj = NULL;
8032         r600_ring_init(rdev, ring, 1024 * 1024);
8033
8034         ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
8035         ring->ring_obj = NULL;
8036         r600_ring_init(rdev, ring, 1024 * 1024);
8037         r = radeon_doorbell_get(rdev, &ring->doorbell_index);
8038         if (r)
8039                 return r;
8040
8041         ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
8042         ring->ring_obj = NULL;
8043         r600_ring_init(rdev, ring, 1024 * 1024);
8044         r = radeon_doorbell_get(rdev, &ring->doorbell_index);
8045         if (r)
8046                 return r;
8047
8048         ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
8049         ring->ring_obj = NULL;
8050         r600_ring_init(rdev, ring, 256 * 1024);
8051
8052         ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
8053         ring->ring_obj = NULL;
8054         r600_ring_init(rdev, ring, 256 * 1024);
8055
8056         r = radeon_uvd_init(rdev);
8057         if (!r) {
8058                 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
8059                 ring->ring_obj = NULL;
8060                 r600_ring_init(rdev, ring, 4096);
8061         }
8062
8063         rdev->ih.ring_obj = NULL;
8064         r600_ih_ring_init(rdev, 64 * 1024);
8065
8066         r = r600_pcie_gart_init(rdev);
8067         if (r)
8068                 return r;
8069
8070         rdev->accel_working = true;
8071         r = cik_startup(rdev);
8072         if (r) {
8073                 dev_err(rdev->dev, "disabling GPU acceleration\n");
8074                 cik_cp_fini(rdev);
8075                 cik_sdma_fini(rdev);
8076                 cik_irq_fini(rdev);
8077                 sumo_rlc_fini(rdev);
8078                 cik_mec_fini(rdev);
8079                 radeon_wb_fini(rdev);
8080                 radeon_ib_pool_fini(rdev);
8081                 radeon_vm_manager_fini(rdev);
8082                 radeon_irq_kms_fini(rdev);
8083                 cik_pcie_gart_fini(rdev);
8084                 rdev->accel_working = false;
8085         }
8086
8087         /* Don't start up if the MC ucode is missing.
8088          * The default clocks and voltages before the MC ucode
8089          * is loaded are not suffient for advanced operations.
8090          */
8091         if (!rdev->mc_fw && !(rdev->flags & RADEON_IS_IGP)) {
8092                 DRM_ERROR("radeon: MC ucode required for NI+.\n");
8093                 return -EINVAL;
8094         }
8095
8096         return 0;
8097 }
8098
8099 /**
8100  * cik_fini - asic specific driver and hw fini
8101  *
8102  * @rdev: radeon_device pointer
8103  *
8104  * Tear down the asic specific driver variables and program the hw
8105  * to an idle state (CIK).
8106  * Called at driver unload.
8107  */
8108 void cik_fini(struct radeon_device *rdev)
8109 {
8110         radeon_pm_fini(rdev);
8111         cik_cp_fini(rdev);
8112         cik_sdma_fini(rdev);
8113         cik_fini_pg(rdev);
8114         cik_fini_cg(rdev);
8115         cik_irq_fini(rdev);
8116         sumo_rlc_fini(rdev);
8117         cik_mec_fini(rdev);
8118         radeon_wb_fini(rdev);
8119         radeon_vm_manager_fini(rdev);
8120         radeon_ib_pool_fini(rdev);
8121         radeon_irq_kms_fini(rdev);
8122         uvd_v1_0_fini(rdev);
8123         radeon_uvd_fini(rdev);
8124         cik_pcie_gart_fini(rdev);
8125         r600_vram_scratch_fini(rdev);
8126         radeon_gem_fini(rdev);
8127         radeon_fence_driver_fini(rdev);
8128         radeon_bo_fini(rdev);
8129         radeon_atombios_fini(rdev);
8130         kfree(rdev->bios);
8131         rdev->bios = NULL;
8132 }
8133
8134 void dce8_program_fmt(struct drm_encoder *encoder)
8135 {
8136         struct drm_device *dev = encoder->dev;
8137         struct radeon_device *rdev = dev->dev_private;
8138         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
8139         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
8140         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
8141         int bpc = 0;
8142         u32 tmp = 0;
8143         enum radeon_connector_dither dither = RADEON_FMT_DITHER_DISABLE;
8144
8145         if (connector) {
8146                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
8147                 bpc = radeon_get_monitor_bpc(connector);
8148                 dither = radeon_connector->dither;
8149         }
8150
8151         /* LVDS/eDP FMT is set up by atom */
8152         if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
8153                 return;
8154
8155         /* not needed for analog */
8156         if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
8157             (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
8158                 return;
8159
8160         if (bpc == 0)
8161                 return;
8162
8163         switch (bpc) {
8164         case 6:
8165                 if (dither == RADEON_FMT_DITHER_ENABLE)
8166                         /* XXX sort out optimal dither settings */
8167                         tmp |= (FMT_FRAME_RANDOM_ENABLE | FMT_HIGHPASS_RANDOM_ENABLE |
8168                                 FMT_SPATIAL_DITHER_EN | FMT_SPATIAL_DITHER_DEPTH(0));
8169                 else
8170                         tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH(0));
8171                 break;
8172         case 8:
8173                 if (dither == RADEON_FMT_DITHER_ENABLE)
8174                         /* XXX sort out optimal dither settings */
8175                         tmp |= (FMT_FRAME_RANDOM_ENABLE | FMT_HIGHPASS_RANDOM_ENABLE |
8176                                 FMT_RGB_RANDOM_ENABLE |
8177                                 FMT_SPATIAL_DITHER_EN | FMT_SPATIAL_DITHER_DEPTH(1));
8178                 else
8179                         tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH(1));
8180                 break;
8181         case 10:
8182                 if (dither == RADEON_FMT_DITHER_ENABLE)
8183                         /* XXX sort out optimal dither settings */
8184                         tmp |= (FMT_FRAME_RANDOM_ENABLE | FMT_HIGHPASS_RANDOM_ENABLE |
8185                                 FMT_RGB_RANDOM_ENABLE |
8186                                 FMT_SPATIAL_DITHER_EN | FMT_SPATIAL_DITHER_DEPTH(2));
8187                 else
8188                         tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH(2));
8189                 break;
8190         default:
8191                 /* not needed */
8192                 break;
8193         }
8194
8195         WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp);
8196 }
8197
8198 /* display watermark setup */
8199 /**
8200  * dce8_line_buffer_adjust - Set up the line buffer
8201  *
8202  * @rdev: radeon_device pointer
8203  * @radeon_crtc: the selected display controller
8204  * @mode: the current display mode on the selected display
8205  * controller
8206  *
8207  * Setup up the line buffer allocation for
8208  * the selected display controller (CIK).
8209  * Returns the line buffer size in pixels.
8210  */
8211 static u32 dce8_line_buffer_adjust(struct radeon_device *rdev,
8212                                    struct radeon_crtc *radeon_crtc,
8213                                    struct drm_display_mode *mode)
8214 {
8215         u32 tmp, buffer_alloc, i;
8216         u32 pipe_offset = radeon_crtc->crtc_id * 0x20;
8217         /*
8218          * Line Buffer Setup
8219          * There are 6 line buffers, one for each display controllers.
8220          * There are 3 partitions per LB. Select the number of partitions
8221          * to enable based on the display width.  For display widths larger
8222          * than 4096, you need use to use 2 display controllers and combine
8223          * them using the stereo blender.
8224          */
8225         if (radeon_crtc->base.enabled && mode) {
8226                 if (mode->crtc_hdisplay < 1920) {
8227                         tmp = 1;
8228                         buffer_alloc = 2;
8229                 } else if (mode->crtc_hdisplay < 2560) {
8230                         tmp = 2;
8231                         buffer_alloc = 2;
8232                 } else if (mode->crtc_hdisplay < 4096) {
8233                         tmp = 0;
8234                         buffer_alloc = (rdev->flags & RADEON_IS_IGP) ? 2 : 4;
8235                 } else {
8236                         DRM_DEBUG_KMS("Mode too big for LB!\n");
8237                         tmp = 0;
8238                         buffer_alloc = (rdev->flags & RADEON_IS_IGP) ? 2 : 4;
8239                 }
8240         } else {
8241                 tmp = 1;
8242                 buffer_alloc = 0;
8243         }
8244
8245         WREG32(LB_MEMORY_CTRL + radeon_crtc->crtc_offset,
8246                LB_MEMORY_CONFIG(tmp) | LB_MEMORY_SIZE(0x6B0));
8247
8248         WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
8249                DMIF_BUFFERS_ALLOCATED(buffer_alloc));
8250         for (i = 0; i < rdev->usec_timeout; i++) {
8251                 if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
8252                     DMIF_BUFFERS_ALLOCATED_COMPLETED)
8253                         break;
8254                 udelay(1);
8255         }
8256
8257         if (radeon_crtc->base.enabled && mode) {
8258                 switch (tmp) {
8259                 case 0:
8260                 default:
8261                         return 4096 * 2;
8262                 case 1:
8263                         return 1920 * 2;
8264                 case 2:
8265                         return 2560 * 2;
8266                 }
8267         }
8268
8269         /* controller not enabled, so no lb used */
8270         return 0;
8271 }
8272
8273 /**
8274  * cik_get_number_of_dram_channels - get the number of dram channels
8275  *
8276  * @rdev: radeon_device pointer
8277  *
8278  * Look up the number of video ram channels (CIK).
8279  * Used for display watermark bandwidth calculations
8280  * Returns the number of dram channels
8281  */
8282 static u32 cik_get_number_of_dram_channels(struct radeon_device *rdev)
8283 {
8284         u32 tmp = RREG32(MC_SHARED_CHMAP);
8285
8286         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
8287         case 0:
8288         default:
8289                 return 1;
8290         case 1:
8291                 return 2;
8292         case 2:
8293                 return 4;
8294         case 3:
8295                 return 8;
8296         case 4:
8297                 return 3;
8298         case 5:
8299                 return 6;
8300         case 6:
8301                 return 10;
8302         case 7:
8303                 return 12;
8304         case 8:
8305                 return 16;
8306         }
8307 }
8308
8309 struct dce8_wm_params {
8310         u32 dram_channels; /* number of dram channels */
8311         u32 yclk;          /* bandwidth per dram data pin in kHz */
8312         u32 sclk;          /* engine clock in kHz */
8313         u32 disp_clk;      /* display clock in kHz */
8314         u32 src_width;     /* viewport width */
8315         u32 active_time;   /* active display time in ns */
8316         u32 blank_time;    /* blank time in ns */
8317         bool interlaced;    /* mode is interlaced */
8318         fixed20_12 vsc;    /* vertical scale ratio */
8319         u32 num_heads;     /* number of active crtcs */
8320         u32 bytes_per_pixel; /* bytes per pixel display + overlay */
8321         u32 lb_size;       /* line buffer allocated to pipe */
8322         u32 vtaps;         /* vertical scaler taps */
8323 };
8324
8325 /**
8326  * dce8_dram_bandwidth - get the dram bandwidth
8327  *
8328  * @wm: watermark calculation data
8329  *
8330  * Calculate the raw dram bandwidth (CIK).
8331  * Used for display watermark bandwidth calculations
8332  * Returns the dram bandwidth in MBytes/s
8333  */
8334 static u32 dce8_dram_bandwidth(struct dce8_wm_params *wm)
8335 {
8336         /* Calculate raw DRAM Bandwidth */
8337         fixed20_12 dram_efficiency; /* 0.7 */
8338         fixed20_12 yclk, dram_channels, bandwidth;
8339         fixed20_12 a;
8340
8341         a.full = dfixed_const(1000);
8342         yclk.full = dfixed_const(wm->yclk);
8343         yclk.full = dfixed_div(yclk, a);
8344         dram_channels.full = dfixed_const(wm->dram_channels * 4);
8345         a.full = dfixed_const(10);
8346         dram_efficiency.full = dfixed_const(7);
8347         dram_efficiency.full = dfixed_div(dram_efficiency, a);
8348         bandwidth.full = dfixed_mul(dram_channels, yclk);
8349         bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
8350
8351         return dfixed_trunc(bandwidth);
8352 }
8353
8354 /**
8355  * dce8_dram_bandwidth_for_display - get the dram bandwidth for display
8356  *
8357  * @wm: watermark calculation data
8358  *
8359  * Calculate the dram bandwidth used for display (CIK).
8360  * Used for display watermark bandwidth calculations
8361  * Returns the dram bandwidth for display in MBytes/s
8362  */
8363 static u32 dce8_dram_bandwidth_for_display(struct dce8_wm_params *wm)
8364 {
8365         /* Calculate DRAM Bandwidth and the part allocated to display. */
8366         fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
8367         fixed20_12 yclk, dram_channels, bandwidth;
8368         fixed20_12 a;
8369
8370         a.full = dfixed_const(1000);
8371         yclk.full = dfixed_const(wm->yclk);
8372         yclk.full = dfixed_div(yclk, a);
8373         dram_channels.full = dfixed_const(wm->dram_channels * 4);
8374         a.full = dfixed_const(10);
8375         disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
8376         disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
8377         bandwidth.full = dfixed_mul(dram_channels, yclk);
8378         bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
8379
8380         return dfixed_trunc(bandwidth);
8381 }
8382
8383 /**
8384  * dce8_data_return_bandwidth - get the data return bandwidth
8385  *
8386  * @wm: watermark calculation data
8387  *
8388  * Calculate the data return bandwidth used for display (CIK).
8389  * Used for display watermark bandwidth calculations
8390  * Returns the data return bandwidth in MBytes/s
8391  */
8392 static u32 dce8_data_return_bandwidth(struct dce8_wm_params *wm)
8393 {
8394         /* Calculate the display Data return Bandwidth */
8395         fixed20_12 return_efficiency; /* 0.8 */
8396         fixed20_12 sclk, bandwidth;
8397         fixed20_12 a;
8398
8399         a.full = dfixed_const(1000);
8400         sclk.full = dfixed_const(wm->sclk);
8401         sclk.full = dfixed_div(sclk, a);
8402         a.full = dfixed_const(10);
8403         return_efficiency.full = dfixed_const(8);
8404         return_efficiency.full = dfixed_div(return_efficiency, a);
8405         a.full = dfixed_const(32);
8406         bandwidth.full = dfixed_mul(a, sclk);
8407         bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
8408
8409         return dfixed_trunc(bandwidth);
8410 }
8411
8412 /**
8413  * dce8_dmif_request_bandwidth - get the dmif bandwidth
8414  *
8415  * @wm: watermark calculation data
8416  *
8417  * Calculate the dmif bandwidth used for display (CIK).
8418  * Used for display watermark bandwidth calculations
8419  * Returns the dmif bandwidth in MBytes/s
8420  */
8421 static u32 dce8_dmif_request_bandwidth(struct dce8_wm_params *wm)
8422 {
8423         /* Calculate the DMIF Request Bandwidth */
8424         fixed20_12 disp_clk_request_efficiency; /* 0.8 */
8425         fixed20_12 disp_clk, bandwidth;
8426         fixed20_12 a, b;
8427
8428         a.full = dfixed_const(1000);
8429         disp_clk.full = dfixed_const(wm->disp_clk);
8430         disp_clk.full = dfixed_div(disp_clk, a);
8431         a.full = dfixed_const(32);
8432         b.full = dfixed_mul(a, disp_clk);
8433
8434         a.full = dfixed_const(10);
8435         disp_clk_request_efficiency.full = dfixed_const(8);
8436         disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
8437
8438         bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
8439
8440         return dfixed_trunc(bandwidth);
8441 }
8442
8443 /**
8444  * dce8_available_bandwidth - get the min available bandwidth
8445  *
8446  * @wm: watermark calculation data
8447  *
8448  * Calculate the min available bandwidth used for display (CIK).
8449  * Used for display watermark bandwidth calculations
8450  * Returns the min available bandwidth in MBytes/s
8451  */
8452 static u32 dce8_available_bandwidth(struct dce8_wm_params *wm)
8453 {
8454         /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
8455         u32 dram_bandwidth = dce8_dram_bandwidth(wm);
8456         u32 data_return_bandwidth = dce8_data_return_bandwidth(wm);
8457         u32 dmif_req_bandwidth = dce8_dmif_request_bandwidth(wm);
8458
8459         return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
8460 }
8461
8462 /**
8463  * dce8_average_bandwidth - get the average available bandwidth
8464  *
8465  * @wm: watermark calculation data
8466  *
8467  * Calculate the average available bandwidth used for display (CIK).
8468  * Used for display watermark bandwidth calculations
8469  * Returns the average available bandwidth in MBytes/s
8470  */
8471 static u32 dce8_average_bandwidth(struct dce8_wm_params *wm)
8472 {
8473         /* Calculate the display mode Average Bandwidth
8474          * DisplayMode should contain the source and destination dimensions,
8475          * timing, etc.
8476          */
8477         fixed20_12 bpp;
8478         fixed20_12 line_time;
8479         fixed20_12 src_width;
8480         fixed20_12 bandwidth;
8481         fixed20_12 a;
8482
8483         a.full = dfixed_const(1000);
8484         line_time.full = dfixed_const(wm->active_time + wm->blank_time);
8485         line_time.full = dfixed_div(line_time, a);
8486         bpp.full = dfixed_const(wm->bytes_per_pixel);
8487         src_width.full = dfixed_const(wm->src_width);
8488         bandwidth.full = dfixed_mul(src_width, bpp);
8489         bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
8490         bandwidth.full = dfixed_div(bandwidth, line_time);
8491
8492         return dfixed_trunc(bandwidth);
8493 }
8494
8495 /**
8496  * dce8_latency_watermark - get the latency watermark
8497  *
8498  * @wm: watermark calculation data
8499  *
8500  * Calculate the latency watermark (CIK).
8501  * Used for display watermark bandwidth calculations
8502  * Returns the latency watermark in ns
8503  */
8504 static u32 dce8_latency_watermark(struct dce8_wm_params *wm)
8505 {
8506         /* First calculate the latency in ns */
8507         u32 mc_latency = 2000; /* 2000 ns. */
8508         u32 available_bandwidth = dce8_available_bandwidth(wm);
8509         u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
8510         u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
8511         u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
8512         u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
8513                 (wm->num_heads * cursor_line_pair_return_time);
8514         u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
8515         u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
8516         u32 tmp, dmif_size = 12288;
8517         fixed20_12 a, b, c;
8518
8519         if (wm->num_heads == 0)
8520                 return 0;
8521
8522         a.full = dfixed_const(2);
8523         b.full = dfixed_const(1);
8524         if ((wm->vsc.full > a.full) ||
8525             ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
8526             (wm->vtaps >= 5) ||
8527             ((wm->vsc.full >= a.full) && wm->interlaced))
8528                 max_src_lines_per_dst_line = 4;
8529         else
8530                 max_src_lines_per_dst_line = 2;
8531
8532         a.full = dfixed_const(available_bandwidth);
8533         b.full = dfixed_const(wm->num_heads);
8534         a.full = dfixed_div(a, b);
8535
8536         b.full = dfixed_const(mc_latency + 512);
8537         c.full = dfixed_const(wm->disp_clk);
8538         b.full = dfixed_div(b, c);
8539
8540         c.full = dfixed_const(dmif_size);
8541         b.full = dfixed_div(c, b);
8542
8543         tmp = min(dfixed_trunc(a), dfixed_trunc(b));
8544
8545         b.full = dfixed_const(1000);
8546         c.full = dfixed_const(wm->disp_clk);
8547         b.full = dfixed_div(c, b);
8548         c.full = dfixed_const(wm->bytes_per_pixel);
8549         b.full = dfixed_mul(b, c);
8550
8551         lb_fill_bw = min(tmp, dfixed_trunc(b));
8552
8553         a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
8554         b.full = dfixed_const(1000);
8555         c.full = dfixed_const(lb_fill_bw);
8556         b.full = dfixed_div(c, b);
8557         a.full = dfixed_div(a, b);
8558         line_fill_time = dfixed_trunc(a);
8559
8560         if (line_fill_time < wm->active_time)
8561                 return latency;
8562         else
8563                 return latency + (line_fill_time - wm->active_time);
8564
8565 }
8566
8567 /**
8568  * dce8_average_bandwidth_vs_dram_bandwidth_for_display - check
8569  * average and available dram bandwidth
8570  *
8571  * @wm: watermark calculation data
8572  *
8573  * Check if the display average bandwidth fits in the display
8574  * dram bandwidth (CIK).
8575  * Used for display watermark bandwidth calculations
8576  * Returns true if the display fits, false if not.
8577  */
8578 static bool dce8_average_bandwidth_vs_dram_bandwidth_for_display(struct dce8_wm_params *wm)
8579 {
8580         if (dce8_average_bandwidth(wm) <=
8581             (dce8_dram_bandwidth_for_display(wm) / wm->num_heads))
8582                 return true;
8583         else
8584                 return false;
8585 }
8586
8587 /**
8588  * dce8_average_bandwidth_vs_available_bandwidth - check
8589  * average and available bandwidth
8590  *
8591  * @wm: watermark calculation data
8592  *
8593  * Check if the display average bandwidth fits in the display
8594  * available bandwidth (CIK).
8595  * Used for display watermark bandwidth calculations
8596  * Returns true if the display fits, false if not.
8597  */
8598 static bool dce8_average_bandwidth_vs_available_bandwidth(struct dce8_wm_params *wm)
8599 {
8600         if (dce8_average_bandwidth(wm) <=
8601             (dce8_available_bandwidth(wm) / wm->num_heads))
8602                 return true;
8603         else
8604                 return false;
8605 }
8606
8607 /**
8608  * dce8_check_latency_hiding - check latency hiding
8609  *
8610  * @wm: watermark calculation data
8611  *
8612  * Check latency hiding (CIK).
8613  * Used for display watermark bandwidth calculations
8614  * Returns true if the display fits, false if not.
8615  */
8616 static bool dce8_check_latency_hiding(struct dce8_wm_params *wm)
8617 {
8618         u32 lb_partitions = wm->lb_size / wm->src_width;
8619         u32 line_time = wm->active_time + wm->blank_time;
8620         u32 latency_tolerant_lines;
8621         u32 latency_hiding;
8622         fixed20_12 a;
8623
8624         a.full = dfixed_const(1);
8625         if (wm->vsc.full > a.full)
8626                 latency_tolerant_lines = 1;
8627         else {
8628                 if (lb_partitions <= (wm->vtaps + 1))
8629                         latency_tolerant_lines = 1;
8630                 else
8631                         latency_tolerant_lines = 2;
8632         }
8633
8634         latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
8635
8636         if (dce8_latency_watermark(wm) <= latency_hiding)
8637                 return true;
8638         else
8639                 return false;
8640 }
8641
8642 /**
8643  * dce8_program_watermarks - program display watermarks
8644  *
8645  * @rdev: radeon_device pointer
8646  * @radeon_crtc: the selected display controller
8647  * @lb_size: line buffer size
8648  * @num_heads: number of display controllers in use
8649  *
8650  * Calculate and program the display watermarks for the
8651  * selected display controller (CIK).
8652  */
8653 static void dce8_program_watermarks(struct radeon_device *rdev,
8654                                     struct radeon_crtc *radeon_crtc,
8655                                     u32 lb_size, u32 num_heads)
8656 {
8657         struct drm_display_mode *mode = &radeon_crtc->base.mode;
8658         struct dce8_wm_params wm_low, wm_high;
8659         u32 pixel_period;
8660         u32 line_time = 0;
8661         u32 latency_watermark_a = 0, latency_watermark_b = 0;
8662         u32 tmp, wm_mask;
8663
8664         if (radeon_crtc->base.enabled && num_heads && mode) {
8665                 pixel_period = 1000000 / (u32)mode->clock;
8666                 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
8667
8668                 /* watermark for high clocks */
8669                 if ((rdev->pm.pm_method == PM_METHOD_DPM) &&
8670                     rdev->pm.dpm_enabled) {
8671                         wm_high.yclk =
8672                                 radeon_dpm_get_mclk(rdev, false) * 10;
8673                         wm_high.sclk =
8674                                 radeon_dpm_get_sclk(rdev, false) * 10;
8675                 } else {
8676                         wm_high.yclk = rdev->pm.current_mclk * 10;
8677                         wm_high.sclk = rdev->pm.current_sclk * 10;
8678                 }
8679
8680                 wm_high.disp_clk = mode->clock;
8681                 wm_high.src_width = mode->crtc_hdisplay;
8682                 wm_high.active_time = mode->crtc_hdisplay * pixel_period;
8683                 wm_high.blank_time = line_time - wm_high.active_time;
8684                 wm_high.interlaced = false;
8685                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
8686                         wm_high.interlaced = true;
8687                 wm_high.vsc = radeon_crtc->vsc;
8688                 wm_high.vtaps = 1;
8689                 if (radeon_crtc->rmx_type != RMX_OFF)
8690                         wm_high.vtaps = 2;
8691                 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
8692                 wm_high.lb_size = lb_size;
8693                 wm_high.dram_channels = cik_get_number_of_dram_channels(rdev);
8694                 wm_high.num_heads = num_heads;
8695
8696                 /* set for high clocks */
8697                 latency_watermark_a = min(dce8_latency_watermark(&wm_high), (u32)65535);
8698
8699                 /* possibly force display priority to high */
8700                 /* should really do this at mode validation time... */
8701                 if (!dce8_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
8702                     !dce8_average_bandwidth_vs_available_bandwidth(&wm_high) ||
8703                     !dce8_check_latency_hiding(&wm_high) ||
8704                     (rdev->disp_priority == 2)) {
8705                         DRM_DEBUG_KMS("force priority to high\n");
8706                 }
8707
8708                 /* watermark for low clocks */
8709                 if ((rdev->pm.pm_method == PM_METHOD_DPM) &&
8710                     rdev->pm.dpm_enabled) {
8711                         wm_low.yclk =
8712                                 radeon_dpm_get_mclk(rdev, true) * 10;
8713                         wm_low.sclk =
8714                                 radeon_dpm_get_sclk(rdev, true) * 10;
8715                 } else {
8716                         wm_low.yclk = rdev->pm.current_mclk * 10;
8717                         wm_low.sclk = rdev->pm.current_sclk * 10;
8718                 }
8719
8720                 wm_low.disp_clk = mode->clock;
8721                 wm_low.src_width = mode->crtc_hdisplay;
8722                 wm_low.active_time = mode->crtc_hdisplay * pixel_period;
8723                 wm_low.blank_time = line_time - wm_low.active_time;
8724                 wm_low.interlaced = false;
8725                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
8726                         wm_low.interlaced = true;
8727                 wm_low.vsc = radeon_crtc->vsc;
8728                 wm_low.vtaps = 1;
8729                 if (radeon_crtc->rmx_type != RMX_OFF)
8730                         wm_low.vtaps = 2;
8731                 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
8732                 wm_low.lb_size = lb_size;
8733                 wm_low.dram_channels = cik_get_number_of_dram_channels(rdev);
8734                 wm_low.num_heads = num_heads;
8735
8736                 /* set for low clocks */
8737                 latency_watermark_b = min(dce8_latency_watermark(&wm_low), (u32)65535);
8738
8739                 /* possibly force display priority to high */
8740                 /* should really do this at mode validation time... */
8741                 if (!dce8_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
8742                     !dce8_average_bandwidth_vs_available_bandwidth(&wm_low) ||
8743                     !dce8_check_latency_hiding(&wm_low) ||
8744                     (rdev->disp_priority == 2)) {
8745                         DRM_DEBUG_KMS("force priority to high\n");
8746                 }
8747         }
8748
8749         /* select wm A */
8750         wm_mask = RREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset);
8751         tmp = wm_mask;
8752         tmp &= ~LATENCY_WATERMARK_MASK(3);
8753         tmp |= LATENCY_WATERMARK_MASK(1);
8754         WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, tmp);
8755         WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,
8756                (LATENCY_LOW_WATERMARK(latency_watermark_a) |
8757                 LATENCY_HIGH_WATERMARK(line_time)));
8758         /* select wm B */
8759         tmp = RREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset);
8760         tmp &= ~LATENCY_WATERMARK_MASK(3);
8761         tmp |= LATENCY_WATERMARK_MASK(2);
8762         WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, tmp);
8763         WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset,
8764                (LATENCY_LOW_WATERMARK(latency_watermark_b) |
8765                 LATENCY_HIGH_WATERMARK(line_time)));
8766         /* restore original selection */
8767         WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, wm_mask);
8768
8769         /* save values for DPM */
8770         radeon_crtc->line_time = line_time;
8771         radeon_crtc->wm_high = latency_watermark_a;
8772         radeon_crtc->wm_low = latency_watermark_b;
8773 }
8774
8775 /**
8776  * dce8_bandwidth_update - program display watermarks
8777  *
8778  * @rdev: radeon_device pointer
8779  *
8780  * Calculate and program the display watermarks and line
8781  * buffer allocation (CIK).
8782  */
8783 void dce8_bandwidth_update(struct radeon_device *rdev)
8784 {
8785         struct drm_display_mode *mode = NULL;
8786         u32 num_heads = 0, lb_size;
8787         int i;
8788
8789         radeon_update_display_priority(rdev);
8790
8791         for (i = 0; i < rdev->num_crtc; i++) {
8792                 if (rdev->mode_info.crtcs[i]->base.enabled)
8793                         num_heads++;
8794         }
8795         for (i = 0; i < rdev->num_crtc; i++) {
8796                 mode = &rdev->mode_info.crtcs[i]->base.mode;
8797                 lb_size = dce8_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode);
8798                 dce8_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads);
8799         }
8800 }
8801
8802 /**
8803  * cik_get_gpu_clock_counter - return GPU clock counter snapshot
8804  *
8805  * @rdev: radeon_device pointer
8806  *
8807  * Fetches a GPU clock counter snapshot (SI).
8808  * Returns the 64 bit clock counter snapshot.
8809  */
8810 uint64_t cik_get_gpu_clock_counter(struct radeon_device *rdev)
8811 {
8812         uint64_t clock;
8813
8814         mutex_lock(&rdev->gpu_clock_mutex);
8815         WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1);
8816         clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) |
8817                 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
8818         mutex_unlock(&rdev->gpu_clock_mutex);
8819         return clock;
8820 }
8821
8822 static int cik_set_uvd_clock(struct radeon_device *rdev, u32 clock,
8823                               u32 cntl_reg, u32 status_reg)
8824 {
8825         int r, i;
8826         struct atom_clock_dividers dividers;
8827         uint32_t tmp;
8828
8829         r = radeon_atom_get_clock_dividers(rdev, COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
8830                                            clock, false, &dividers);
8831         if (r)
8832                 return r;
8833
8834         tmp = RREG32_SMC(cntl_reg);
8835         tmp &= ~(DCLK_DIR_CNTL_EN|DCLK_DIVIDER_MASK);
8836         tmp |= dividers.post_divider;
8837         WREG32_SMC(cntl_reg, tmp);
8838
8839         for (i = 0; i < 100; i++) {
8840                 if (RREG32_SMC(status_reg) & DCLK_STATUS)
8841                         break;
8842                 mdelay(10);
8843         }
8844         if (i == 100)
8845                 return -ETIMEDOUT;
8846
8847         return 0;
8848 }
8849
8850 int cik_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
8851 {
8852         int r = 0;
8853
8854         r = cik_set_uvd_clock(rdev, vclk, CG_VCLK_CNTL, CG_VCLK_STATUS);
8855         if (r)
8856                 return r;
8857
8858         r = cik_set_uvd_clock(rdev, dclk, CG_DCLK_CNTL, CG_DCLK_STATUS);
8859         return r;
8860 }
8861
8862 static void cik_pcie_gen3_enable(struct radeon_device *rdev)
8863 {
8864         struct pci_dev *root = rdev->pdev->bus->self;
8865         int bridge_pos, gpu_pos;
8866         u32 speed_cntl, mask, current_data_rate;
8867         int ret, i;
8868         u16 tmp16;
8869
8870         if (radeon_pcie_gen2 == 0)
8871                 return;
8872
8873         if (rdev->flags & RADEON_IS_IGP)
8874                 return;
8875
8876         if (!(rdev->flags & RADEON_IS_PCIE))
8877                 return;
8878
8879         ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
8880         if (ret != 0)
8881                 return;
8882
8883         if (!(mask & (DRM_PCIE_SPEED_50 | DRM_PCIE_SPEED_80)))
8884                 return;
8885
8886         speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
8887         current_data_rate = (speed_cntl & LC_CURRENT_DATA_RATE_MASK) >>
8888                 LC_CURRENT_DATA_RATE_SHIFT;
8889         if (mask & DRM_PCIE_SPEED_80) {
8890                 if (current_data_rate == 2) {
8891                         DRM_INFO("PCIE gen 3 link speeds already enabled\n");
8892                         return;
8893                 }
8894                 DRM_INFO("enabling PCIE gen 3 link speeds, disable with radeon.pcie_gen2=0\n");
8895         } else if (mask & DRM_PCIE_SPEED_50) {
8896                 if (current_data_rate == 1) {
8897                         DRM_INFO("PCIE gen 2 link speeds already enabled\n");
8898                         return;
8899                 }
8900                 DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
8901         }
8902
8903         bridge_pos = pci_pcie_cap(root);
8904         if (!bridge_pos)
8905                 return;
8906
8907         gpu_pos = pci_pcie_cap(rdev->pdev);
8908         if (!gpu_pos)
8909                 return;
8910
8911         if (mask & DRM_PCIE_SPEED_80) {
8912                 /* re-try equalization if gen3 is not already enabled */
8913                 if (current_data_rate != 2) {
8914                         u16 bridge_cfg, gpu_cfg;
8915                         u16 bridge_cfg2, gpu_cfg2;
8916                         u32 max_lw, current_lw, tmp;
8917
8918                         pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg);
8919                         pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg);
8920
8921                         tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD;
8922                         pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16);
8923
8924                         tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD;
8925                         pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);
8926
8927                         tmp = RREG32_PCIE_PORT(PCIE_LC_STATUS1);
8928                         max_lw = (tmp & LC_DETECTED_LINK_WIDTH_MASK) >> LC_DETECTED_LINK_WIDTH_SHIFT;
8929                         current_lw = (tmp & LC_OPERATING_LINK_WIDTH_MASK) >> LC_OPERATING_LINK_WIDTH_SHIFT;
8930
8931                         if (current_lw < max_lw) {
8932                                 tmp = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
8933                                 if (tmp & LC_RENEGOTIATION_SUPPORT) {
8934                                         tmp &= ~(LC_LINK_WIDTH_MASK | LC_UPCONFIGURE_DIS);
8935                                         tmp |= (max_lw << LC_LINK_WIDTH_SHIFT);
8936                                         tmp |= LC_UPCONFIGURE_SUPPORT | LC_RENEGOTIATE_EN | LC_RECONFIG_NOW;
8937                                         WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, tmp);
8938                                 }
8939                         }
8940
8941                         for (i = 0; i < 10; i++) {
8942                                 /* check status */
8943                                 pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_DEVSTA, &tmp16);
8944                                 if (tmp16 & PCI_EXP_DEVSTA_TRPND)
8945                                         break;
8946
8947                                 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg);
8948                                 pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg);
8949
8950                                 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &bridge_cfg2);
8951                                 pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &gpu_cfg2);
8952
8953                                 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
8954                                 tmp |= LC_SET_QUIESCE;
8955                                 WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
8956
8957                                 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
8958                                 tmp |= LC_REDO_EQ;
8959                                 WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
8960
8961                                 mdelay(100);
8962
8963                                 /* linkctl */
8964                                 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &tmp16);
8965                                 tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
8966                                 tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD);
8967                                 pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16);
8968
8969                                 pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, &tmp16);
8970                                 tmp16 &= ~PCI_EXP_LNKCTL_HAWD;
8971                                 tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD);
8972                                 pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);
8973
8974                                 /* linkctl2 */
8975                                 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16);
8976                                 tmp16 &= ~((1 << 4) | (7 << 9));
8977                                 tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 9)));
8978                                 pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16);
8979
8980                                 pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
8981                                 tmp16 &= ~((1 << 4) | (7 << 9));
8982                                 tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 9)));
8983                                 pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
8984
8985                                 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
8986                                 tmp &= ~LC_SET_QUIESCE;
8987                                 WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp);
8988                         }
8989                 }
8990         }
8991
8992         /* set the link speed */
8993         speed_cntl |= LC_FORCE_EN_SW_SPEED_CHANGE | LC_FORCE_DIS_HW_SPEED_CHANGE;
8994         speed_cntl &= ~LC_FORCE_DIS_SW_SPEED_CHANGE;
8995         WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
8996
8997         pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
8998         tmp16 &= ~0xf;
8999         if (mask & DRM_PCIE_SPEED_80)
9000                 tmp16 |= 3; /* gen3 */
9001         else if (mask & DRM_PCIE_SPEED_50)
9002                 tmp16 |= 2; /* gen2 */
9003         else
9004                 tmp16 |= 1; /* gen1 */
9005         pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
9006
9007         speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
9008         speed_cntl |= LC_INITIATE_LINK_SPEED_CHANGE;
9009         WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
9010
9011         for (i = 0; i < rdev->usec_timeout; i++) {
9012                 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
9013                 if ((speed_cntl & LC_INITIATE_LINK_SPEED_CHANGE) == 0)
9014                         break;
9015                 udelay(1);
9016         }
9017 }
9018
9019 static void cik_program_aspm(struct radeon_device *rdev)
9020 {
9021         u32 data, orig;
9022         bool disable_l0s = false, disable_l1 = false, disable_plloff_in_l1 = false;
9023         bool disable_clkreq = false;
9024
9025         if (radeon_aspm == 0)
9026                 return;
9027
9028         /* XXX double check IGPs */
9029         if (rdev->flags & RADEON_IS_IGP)
9030                 return;
9031
9032         if (!(rdev->flags & RADEON_IS_PCIE))
9033                 return;
9034
9035         orig = data = RREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL);
9036         data &= ~LC_XMIT_N_FTS_MASK;
9037         data |= LC_XMIT_N_FTS(0x24) | LC_XMIT_N_FTS_OVERRIDE_EN;
9038         if (orig != data)
9039                 WREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL, data);
9040
9041         orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL3);
9042         data |= LC_GO_TO_RECOVERY;
9043         if (orig != data)
9044                 WREG32_PCIE_PORT(PCIE_LC_CNTL3, data);
9045
9046         orig = data = RREG32_PCIE_PORT(PCIE_P_CNTL);
9047         data |= P_IGNORE_EDB_ERR;
9048         if (orig != data)
9049                 WREG32_PCIE_PORT(PCIE_P_CNTL, data);
9050
9051         orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL);
9052         data &= ~(LC_L0S_INACTIVITY_MASK | LC_L1_INACTIVITY_MASK);
9053         data |= LC_PMI_TO_L1_DIS;
9054         if (!disable_l0s)
9055                 data |= LC_L0S_INACTIVITY(7);
9056
9057         if (!disable_l1) {
9058                 data |= LC_L1_INACTIVITY(7);
9059                 data &= ~LC_PMI_TO_L1_DIS;
9060                 if (orig != data)
9061                         WREG32_PCIE_PORT(PCIE_LC_CNTL, data);
9062
9063                 if (!disable_plloff_in_l1) {
9064                         bool clk_req_support;
9065
9066                         orig = data = RREG32_PCIE_PORT(PB0_PIF_PWRDOWN_0);
9067                         data &= ~(PLL_POWER_STATE_IN_OFF_0_MASK | PLL_POWER_STATE_IN_TXS2_0_MASK);
9068                         data |= PLL_POWER_STATE_IN_OFF_0(7) | PLL_POWER_STATE_IN_TXS2_0(7);
9069                         if (orig != data)
9070                                 WREG32_PCIE_PORT(PB0_PIF_PWRDOWN_0, data);
9071
9072                         orig = data = RREG32_PCIE_PORT(PB0_PIF_PWRDOWN_1);
9073                         data &= ~(PLL_POWER_STATE_IN_OFF_1_MASK | PLL_POWER_STATE_IN_TXS2_1_MASK);
9074                         data |= PLL_POWER_STATE_IN_OFF_1(7) | PLL_POWER_STATE_IN_TXS2_1(7);
9075                         if (orig != data)
9076                                 WREG32_PCIE_PORT(PB0_PIF_PWRDOWN_1, data);
9077
9078                         orig = data = RREG32_PCIE_PORT(PB1_PIF_PWRDOWN_0);
9079                         data &= ~(PLL_POWER_STATE_IN_OFF_0_MASK | PLL_POWER_STATE_IN_TXS2_0_MASK);
9080                         data |= PLL_POWER_STATE_IN_OFF_0(7) | PLL_POWER_STATE_IN_TXS2_0(7);
9081                         if (orig != data)
9082                                 WREG32_PCIE_PORT(PB1_PIF_PWRDOWN_0, data);
9083
9084                         orig = data = RREG32_PCIE_PORT(PB1_PIF_PWRDOWN_1);
9085                         data &= ~(PLL_POWER_STATE_IN_OFF_1_MASK | PLL_POWER_STATE_IN_TXS2_1_MASK);
9086                         data |= PLL_POWER_STATE_IN_OFF_1(7) | PLL_POWER_STATE_IN_TXS2_1(7);
9087                         if (orig != data)
9088                                 WREG32_PCIE_PORT(PB1_PIF_PWRDOWN_1, data);
9089
9090                         orig = data = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
9091                         data &= ~LC_DYN_LANES_PWR_STATE_MASK;
9092                         data |= LC_DYN_LANES_PWR_STATE(3);
9093                         if (orig != data)
9094                                 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, data);
9095
9096                         if (!disable_clkreq) {
9097                                 struct pci_dev *root = rdev->pdev->bus->self;
9098                                 u32 lnkcap;
9099
9100                                 clk_req_support = false;
9101                                 pcie_capability_read_dword(root, PCI_EXP_LNKCAP, &lnkcap);
9102                                 if (lnkcap & PCI_EXP_LNKCAP_CLKPM)
9103                                         clk_req_support = true;
9104                         } else {
9105                                 clk_req_support = false;
9106                         }
9107
9108                         if (clk_req_support) {
9109                                 orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL2);
9110                                 data |= LC_ALLOW_PDWN_IN_L1 | LC_ALLOW_PDWN_IN_L23;
9111                                 if (orig != data)
9112                                         WREG32_PCIE_PORT(PCIE_LC_CNTL2, data);
9113
9114                                 orig = data = RREG32_SMC(THM_CLK_CNTL);
9115                                 data &= ~(CMON_CLK_SEL_MASK | TMON_CLK_SEL_MASK);
9116                                 data |= CMON_CLK_SEL(1) | TMON_CLK_SEL(1);
9117                                 if (orig != data)
9118                                         WREG32_SMC(THM_CLK_CNTL, data);
9119
9120                                 orig = data = RREG32_SMC(MISC_CLK_CTRL);
9121                                 data &= ~(DEEP_SLEEP_CLK_SEL_MASK | ZCLK_SEL_MASK);
9122                                 data |= DEEP_SLEEP_CLK_SEL(1) | ZCLK_SEL(1);
9123                                 if (orig != data)
9124                                         WREG32_SMC(MISC_CLK_CTRL, data);
9125
9126                                 orig = data = RREG32_SMC(CG_CLKPIN_CNTL);
9127                                 data &= ~BCLK_AS_XCLK;
9128                                 if (orig != data)
9129                                         WREG32_SMC(CG_CLKPIN_CNTL, data);
9130
9131                                 orig = data = RREG32_SMC(CG_CLKPIN_CNTL_2);
9132                                 data &= ~FORCE_BIF_REFCLK_EN;
9133                                 if (orig != data)
9134                                         WREG32_SMC(CG_CLKPIN_CNTL_2, data);
9135
9136                                 orig = data = RREG32_SMC(MPLL_BYPASSCLK_SEL);
9137                                 data &= ~MPLL_CLKOUT_SEL_MASK;
9138                                 data |= MPLL_CLKOUT_SEL(4);
9139                                 if (orig != data)
9140                                         WREG32_SMC(MPLL_BYPASSCLK_SEL, data);
9141                         }
9142                 }
9143         } else {
9144                 if (orig != data)
9145                         WREG32_PCIE_PORT(PCIE_LC_CNTL, data);
9146         }
9147
9148         orig = data = RREG32_PCIE_PORT(PCIE_CNTL2);
9149         data |= SLV_MEM_LS_EN | MST_MEM_LS_EN | REPLAY_MEM_LS_EN;
9150         if (orig != data)
9151                 WREG32_PCIE_PORT(PCIE_CNTL2, data);
9152
9153         if (!disable_l0s) {
9154                 data = RREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL);
9155                 if((data & LC_N_FTS_MASK) == LC_N_FTS_MASK) {
9156                         data = RREG32_PCIE_PORT(PCIE_LC_STATUS1);
9157                         if ((data & LC_REVERSE_XMIT) && (data & LC_REVERSE_RCVR)) {
9158                                 orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL);
9159                                 data &= ~LC_L0S_INACTIVITY_MASK;
9160                                 if (orig != data)
9161                                         WREG32_PCIE_PORT(PCIE_LC_CNTL, data);
9162                         }
9163                 }
9164         }
9165 }