2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include <drm/drm_crtc_helper.h>
28 #include <drm/radeon_drm.h>
29 #include <drm/drm_fixed.h>
32 #include "atom-bits.h"
34 static void atombios_overscan_setup(struct drm_crtc *crtc,
35 struct drm_display_mode *mode,
36 struct drm_display_mode *adjusted_mode)
38 struct drm_device *dev = crtc->dev;
39 struct radeon_device *rdev = dev->dev_private;
40 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
41 SET_CRTC_OVERSCAN_PS_ALLOCATION args;
42 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan);
45 memset(&args, 0, sizeof(args));
47 args.ucCRTC = radeon_crtc->crtc_id;
49 switch (radeon_crtc->rmx_type) {
51 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
52 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
53 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
54 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
57 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay;
58 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay;
61 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
62 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
64 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
65 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
70 args.usOverscanRight = cpu_to_le16(radeon_crtc->h_border);
71 args.usOverscanLeft = cpu_to_le16(radeon_crtc->h_border);
72 args.usOverscanBottom = cpu_to_le16(radeon_crtc->v_border);
73 args.usOverscanTop = cpu_to_le16(radeon_crtc->v_border);
76 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
79 static void atombios_scaler_setup(struct drm_crtc *crtc)
81 struct drm_device *dev = crtc->dev;
82 struct radeon_device *rdev = dev->dev_private;
83 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
84 ENABLE_SCALER_PS_ALLOCATION args;
85 int index = GetIndexIntoMasterTable(COMMAND, EnableScaler);
86 struct radeon_encoder *radeon_encoder =
87 to_radeon_encoder(radeon_crtc->encoder);
88 /* fixme - fill in enc_priv for atom dac */
89 enum radeon_tv_std tv_std = TV_STD_NTSC;
90 bool is_tv = false, is_cv = false;
92 if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id)
95 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
96 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
97 tv_std = tv_dac->tv_std;
101 memset(&args, 0, sizeof(args));
103 args.ucScaler = radeon_crtc->crtc_id;
109 args.ucTVStandard = ATOM_TV_NTSC;
112 args.ucTVStandard = ATOM_TV_PAL;
115 args.ucTVStandard = ATOM_TV_PALM;
118 args.ucTVStandard = ATOM_TV_PAL60;
121 args.ucTVStandard = ATOM_TV_NTSCJ;
123 case TV_STD_SCART_PAL:
124 args.ucTVStandard = ATOM_TV_PAL; /* ??? */
127 args.ucTVStandard = ATOM_TV_SECAM;
130 args.ucTVStandard = ATOM_TV_PALCN;
133 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
135 args.ucTVStandard = ATOM_TV_CV;
136 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
138 switch (radeon_crtc->rmx_type) {
140 args.ucEnable = ATOM_SCALER_EXPANSION;
143 args.ucEnable = ATOM_SCALER_CENTER;
146 args.ucEnable = ATOM_SCALER_EXPANSION;
149 if (ASIC_IS_AVIVO(rdev))
150 args.ucEnable = ATOM_SCALER_DISABLE;
152 args.ucEnable = ATOM_SCALER_CENTER;
156 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
158 && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) {
159 atom_rv515_force_tv_scaler(rdev, radeon_crtc);
163 static void atombios_lock_crtc(struct drm_crtc *crtc, int lock)
165 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
166 struct drm_device *dev = crtc->dev;
167 struct radeon_device *rdev = dev->dev_private;
169 GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters);
170 ENABLE_CRTC_PS_ALLOCATION args;
172 memset(&args, 0, sizeof(args));
174 args.ucCRTC = radeon_crtc->crtc_id;
175 args.ucEnable = lock;
177 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
180 static void atombios_enable_crtc(struct drm_crtc *crtc, int state)
182 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
183 struct drm_device *dev = crtc->dev;
184 struct radeon_device *rdev = dev->dev_private;
185 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
186 ENABLE_CRTC_PS_ALLOCATION args;
188 memset(&args, 0, sizeof(args));
190 args.ucCRTC = radeon_crtc->crtc_id;
191 args.ucEnable = state;
193 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
196 static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state)
198 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
199 struct drm_device *dev = crtc->dev;
200 struct radeon_device *rdev = dev->dev_private;
201 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq);
202 ENABLE_CRTC_PS_ALLOCATION args;
204 memset(&args, 0, sizeof(args));
206 args.ucCRTC = radeon_crtc->crtc_id;
207 args.ucEnable = state;
209 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
212 static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
214 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
215 struct drm_device *dev = crtc->dev;
216 struct radeon_device *rdev = dev->dev_private;
217 int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
218 BLANK_CRTC_PS_ALLOCATION args;
220 memset(&args, 0, sizeof(args));
222 args.ucCRTC = radeon_crtc->crtc_id;
223 args.ucBlanking = state;
225 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
228 static void atombios_powergate_crtc(struct drm_crtc *crtc, int state)
230 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
231 struct drm_device *dev = crtc->dev;
232 struct radeon_device *rdev = dev->dev_private;
233 int index = GetIndexIntoMasterTable(COMMAND, EnableDispPowerGating);
234 ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 args;
236 memset(&args, 0, sizeof(args));
238 args.ucDispPipeId = radeon_crtc->crtc_id;
239 args.ucEnable = state;
241 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
244 void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
246 struct drm_device *dev = crtc->dev;
247 struct radeon_device *rdev = dev->dev_private;
248 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
251 case DRM_MODE_DPMS_ON:
252 radeon_crtc->enabled = true;
253 /* adjust pm to dpms changes BEFORE enabling crtcs */
254 radeon_pm_compute_clocks(rdev);
255 atombios_enable_crtc(crtc, ATOM_ENABLE);
256 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
257 atombios_enable_crtc_memreq(crtc, ATOM_ENABLE);
258 atombios_blank_crtc(crtc, ATOM_DISABLE);
259 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
260 radeon_crtc_load_lut(crtc);
262 case DRM_MODE_DPMS_STANDBY:
263 case DRM_MODE_DPMS_SUSPEND:
264 case DRM_MODE_DPMS_OFF:
265 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
266 if (radeon_crtc->enabled)
267 atombios_blank_crtc(crtc, ATOM_ENABLE);
268 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
269 atombios_enable_crtc_memreq(crtc, ATOM_DISABLE);
270 atombios_enable_crtc(crtc, ATOM_DISABLE);
271 radeon_crtc->enabled = false;
272 /* adjust pm to dpms changes AFTER disabling crtcs */
273 radeon_pm_compute_clocks(rdev);
279 atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
280 struct drm_display_mode *mode)
282 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
283 struct drm_device *dev = crtc->dev;
284 struct radeon_device *rdev = dev->dev_private;
285 SET_CRTC_USING_DTD_TIMING_PARAMETERS args;
286 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming);
289 memset(&args, 0, sizeof(args));
290 args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2));
291 args.usH_Blanking_Time =
292 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2));
293 args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2));
294 args.usV_Blanking_Time =
295 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2));
296 args.usH_SyncOffset =
297 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border);
299 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
300 args.usV_SyncOffset =
301 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border);
303 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
304 args.ucH_Border = radeon_crtc->h_border;
305 args.ucV_Border = radeon_crtc->v_border;
307 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
308 misc |= ATOM_VSYNC_POLARITY;
309 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
310 misc |= ATOM_HSYNC_POLARITY;
311 if (mode->flags & DRM_MODE_FLAG_CSYNC)
312 misc |= ATOM_COMPOSITESYNC;
313 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
314 misc |= ATOM_INTERLACE;
315 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
316 misc |= ATOM_DOUBLE_CLOCK_MODE;
318 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
319 args.ucCRTC = radeon_crtc->crtc_id;
321 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
324 static void atombios_crtc_set_timing(struct drm_crtc *crtc,
325 struct drm_display_mode *mode)
327 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
328 struct drm_device *dev = crtc->dev;
329 struct radeon_device *rdev = dev->dev_private;
330 SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args;
331 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
334 memset(&args, 0, sizeof(args));
335 args.usH_Total = cpu_to_le16(mode->crtc_htotal);
336 args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay);
337 args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start);
339 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
340 args.usV_Total = cpu_to_le16(mode->crtc_vtotal);
341 args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay);
342 args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start);
344 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
346 args.ucOverscanRight = radeon_crtc->h_border;
347 args.ucOverscanLeft = radeon_crtc->h_border;
348 args.ucOverscanBottom = radeon_crtc->v_border;
349 args.ucOverscanTop = radeon_crtc->v_border;
351 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
352 misc |= ATOM_VSYNC_POLARITY;
353 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
354 misc |= ATOM_HSYNC_POLARITY;
355 if (mode->flags & DRM_MODE_FLAG_CSYNC)
356 misc |= ATOM_COMPOSITESYNC;
357 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
358 misc |= ATOM_INTERLACE;
359 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
360 misc |= ATOM_DOUBLE_CLOCK_MODE;
362 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
363 args.ucCRTC = radeon_crtc->crtc_id;
365 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
368 static void atombios_disable_ss(struct radeon_device *rdev, int pll_id)
372 if (ASIC_IS_DCE4(rdev)) {
375 ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL);
376 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
377 WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl);
380 ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL);
381 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
382 WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl);
385 case ATOM_PPLL_INVALID:
388 } else if (ASIC_IS_AVIVO(rdev)) {
391 ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL);
393 WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl);
396 ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL);
398 WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl);
401 case ATOM_PPLL_INVALID:
408 union atom_enable_ss {
409 ENABLE_LVDS_SS_PARAMETERS lvds_ss;
410 ENABLE_LVDS_SS_PARAMETERS_V2 lvds_ss_2;
411 ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1;
412 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2;
413 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3;
416 static void atombios_crtc_program_ss(struct radeon_device *rdev,
420 struct radeon_atom_ss *ss)
423 int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL);
424 union atom_enable_ss args;
427 for (i = 0; i < rdev->num_crtc; i++) {
428 if (rdev->mode_info.crtcs[i] &&
429 rdev->mode_info.crtcs[i]->enabled &&
431 pll_id == rdev->mode_info.crtcs[i]->pll_id) {
432 /* one other crtc is using this pll don't turn
433 * off spread spectrum as it might turn off
434 * display on active crtc
441 memset(&args, 0, sizeof(args));
443 if (ASIC_IS_DCE5(rdev)) {
444 args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0);
445 args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
448 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL;
451 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL;
454 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL;
456 case ATOM_PPLL_INVALID:
459 args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
460 args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step);
461 args.v3.ucEnable = enable;
462 if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK) || ASIC_IS_DCE61(rdev))
463 args.v3.ucEnable = ATOM_DISABLE;
464 } else if (ASIC_IS_DCE4(rdev)) {
465 args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
466 args.v2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
469 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P1PLL;
472 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P2PLL;
475 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_DCPLL;
477 case ATOM_PPLL_INVALID:
480 args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
481 args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step);
482 args.v2.ucEnable = enable;
483 if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK) || ASIC_IS_DCE41(rdev))
484 args.v2.ucEnable = ATOM_DISABLE;
485 } else if (ASIC_IS_DCE3(rdev)) {
486 args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
487 args.v1.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
488 args.v1.ucSpreadSpectrumStep = ss->step;
489 args.v1.ucSpreadSpectrumDelay = ss->delay;
490 args.v1.ucSpreadSpectrumRange = ss->range;
491 args.v1.ucPpll = pll_id;
492 args.v1.ucEnable = enable;
493 } else if (ASIC_IS_AVIVO(rdev)) {
494 if ((enable == ATOM_DISABLE) || (ss->percentage == 0) ||
495 (ss->type & ATOM_EXTERNAL_SS_MASK)) {
496 atombios_disable_ss(rdev, pll_id);
499 args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
500 args.lvds_ss_2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
501 args.lvds_ss_2.ucSpreadSpectrumStep = ss->step;
502 args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay;
503 args.lvds_ss_2.ucSpreadSpectrumRange = ss->range;
504 args.lvds_ss_2.ucEnable = enable;
506 if ((enable == ATOM_DISABLE) || (ss->percentage == 0) ||
507 (ss->type & ATOM_EXTERNAL_SS_MASK)) {
508 atombios_disable_ss(rdev, pll_id);
511 args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
512 args.lvds_ss.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
513 args.lvds_ss.ucSpreadSpectrumStepSize_Delay = (ss->step & 3) << 2;
514 args.lvds_ss.ucSpreadSpectrumStepSize_Delay |= (ss->delay & 7) << 4;
515 args.lvds_ss.ucEnable = enable;
517 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
520 union adjust_pixel_clock {
521 ADJUST_DISPLAY_PLL_PS_ALLOCATION v1;
522 ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3;
525 static u32 atombios_adjust_pll(struct drm_crtc *crtc,
526 struct drm_display_mode *mode)
528 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
529 struct drm_device *dev = crtc->dev;
530 struct radeon_device *rdev = dev->dev_private;
531 struct drm_encoder *encoder = radeon_crtc->encoder;
532 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
533 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
534 u32 adjusted_clock = mode->clock;
535 int encoder_mode = atombios_get_encoder_mode(encoder);
536 u32 dp_clock = mode->clock;
537 int bpc = radeon_get_monitor_bpc(connector);
538 bool is_duallink = radeon_dig_monitor_is_duallink(encoder, mode->clock);
540 /* reset the pll flags */
541 radeon_crtc->pll_flags = 0;
543 if (ASIC_IS_AVIVO(rdev)) {
544 if ((rdev->family == CHIP_RS600) ||
545 (rdev->family == CHIP_RS690) ||
546 (rdev->family == CHIP_RS740))
547 radeon_crtc->pll_flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/
548 RADEON_PLL_PREFER_CLOSEST_LOWER);
550 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */
551 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
553 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
555 if (rdev->family < CHIP_RV770)
556 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP;
557 /* use frac fb div on APUs */
558 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev) || ASIC_IS_DCE8(rdev))
559 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
560 /* use frac fb div on RS780/RS880 */
561 if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880))
562 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
563 if (ASIC_IS_DCE32(rdev) && mode->clock > 165000)
564 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
566 radeon_crtc->pll_flags |= RADEON_PLL_LEGACY;
568 if (mode->clock > 200000) /* range limits??? */
569 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
571 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
574 if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
575 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) {
577 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
578 struct radeon_connector_atom_dig *dig_connector =
579 radeon_connector->con_priv;
581 dp_clock = dig_connector->dp_clock;
585 /* use recommended ref_div for ss */
586 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
587 if (radeon_crtc->ss_enabled) {
588 if (radeon_crtc->ss.refdiv) {
589 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;
590 radeon_crtc->pll_reference_div = radeon_crtc->ss.refdiv;
591 if (ASIC_IS_AVIVO(rdev))
592 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
597 if (ASIC_IS_AVIVO(rdev)) {
598 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
599 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
600 adjusted_clock = mode->clock * 2;
601 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
602 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_CLOSEST_LOWER;
603 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
604 radeon_crtc->pll_flags |= RADEON_PLL_IS_LCD;
606 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
607 radeon_crtc->pll_flags |= RADEON_PLL_NO_ODD_POST_DIV;
608 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS)
609 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;
612 /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock
613 * accordingly based on the encoder/transmitter to work around
614 * special hw requirements.
616 if (ASIC_IS_DCE3(rdev)) {
617 union adjust_pixel_clock args;
621 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
622 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
624 return adjusted_clock;
626 memset(&args, 0, sizeof(args));
633 args.v1.usPixelClock = cpu_to_le16(mode->clock / 10);
634 args.v1.ucTransmitterID = radeon_encoder->encoder_id;
635 args.v1.ucEncodeMode = encoder_mode;
636 if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage)
638 ADJUST_DISPLAY_CONFIG_SS_ENABLE;
640 atom_execute_table(rdev->mode_info.atom_context,
641 index, (uint32_t *)&args);
642 adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10;
645 args.v3.sInput.usPixelClock = cpu_to_le16(mode->clock / 10);
646 args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id;
647 args.v3.sInput.ucEncodeMode = encoder_mode;
648 args.v3.sInput.ucDispPllConfig = 0;
649 if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage)
650 args.v3.sInput.ucDispPllConfig |=
651 DISPPLL_CONFIG_SS_ENABLE;
652 if (ENCODER_MODE_IS_DP(encoder_mode)) {
653 args.v3.sInput.ucDispPllConfig |=
654 DISPPLL_CONFIG_COHERENT_MODE;
656 args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
657 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
658 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
659 if (encoder_mode == ATOM_ENCODER_MODE_HDMI)
660 /* deep color support */
661 args.v3.sInput.usPixelClock =
662 cpu_to_le16((mode->clock * bpc / 8) / 10);
663 if (dig->coherent_mode)
664 args.v3.sInput.ucDispPllConfig |=
665 DISPPLL_CONFIG_COHERENT_MODE;
667 args.v3.sInput.ucDispPllConfig |=
668 DISPPLL_CONFIG_DUAL_LINK;
670 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
671 ENCODER_OBJECT_ID_NONE)
672 args.v3.sInput.ucExtTransmitterID =
673 radeon_encoder_get_dp_bridge_encoder_id(encoder);
675 args.v3.sInput.ucExtTransmitterID = 0;
677 atom_execute_table(rdev->mode_info.atom_context,
678 index, (uint32_t *)&args);
679 adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10;
680 if (args.v3.sOutput.ucRefDiv) {
681 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
682 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;
683 radeon_crtc->pll_reference_div = args.v3.sOutput.ucRefDiv;
685 if (args.v3.sOutput.ucPostDiv) {
686 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
687 radeon_crtc->pll_flags |= RADEON_PLL_USE_POST_DIV;
688 radeon_crtc->pll_post_div = args.v3.sOutput.ucPostDiv;
692 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
693 return adjusted_clock;
697 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
698 return adjusted_clock;
701 return adjusted_clock;
704 union set_pixel_clock {
705 SET_PIXEL_CLOCK_PS_ALLOCATION base;
706 PIXEL_CLOCK_PARAMETERS v1;
707 PIXEL_CLOCK_PARAMETERS_V2 v2;
708 PIXEL_CLOCK_PARAMETERS_V3 v3;
709 PIXEL_CLOCK_PARAMETERS_V5 v5;
710 PIXEL_CLOCK_PARAMETERS_V6 v6;
713 /* on DCE5, make sure the voltage is high enough to support the
716 static void atombios_crtc_set_disp_eng_pll(struct radeon_device *rdev,
721 union set_pixel_clock args;
723 memset(&args, 0, sizeof(args));
725 index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
726 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
734 /* if the default dcpll clock is specified,
735 * SetPixelClock provides the dividers
737 args.v5.ucCRTC = ATOM_CRTC_INVALID;
738 args.v5.usPixelClock = cpu_to_le16(dispclk);
739 args.v5.ucPpll = ATOM_DCPLL;
742 /* if the default dcpll clock is specified,
743 * SetPixelClock provides the dividers
745 args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk);
746 if (ASIC_IS_DCE61(rdev) || ASIC_IS_DCE8(rdev))
747 args.v6.ucPpll = ATOM_EXT_PLL1;
748 else if (ASIC_IS_DCE6(rdev))
749 args.v6.ucPpll = ATOM_PPLL0;
751 args.v6.ucPpll = ATOM_DCPLL;
754 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
759 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
762 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
765 static void atombios_crtc_program_pll(struct drm_crtc *crtc,
777 struct radeon_atom_ss *ss)
779 struct drm_device *dev = crtc->dev;
780 struct radeon_device *rdev = dev->dev_private;
782 int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
783 union set_pixel_clock args;
785 memset(&args, 0, sizeof(args));
787 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
795 if (clock == ATOM_DISABLE)
797 args.v1.usPixelClock = cpu_to_le16(clock / 10);
798 args.v1.usRefDiv = cpu_to_le16(ref_div);
799 args.v1.usFbDiv = cpu_to_le16(fb_div);
800 args.v1.ucFracFbDiv = frac_fb_div;
801 args.v1.ucPostDiv = post_div;
802 args.v1.ucPpll = pll_id;
803 args.v1.ucCRTC = crtc_id;
804 args.v1.ucRefDivSrc = 1;
807 args.v2.usPixelClock = cpu_to_le16(clock / 10);
808 args.v2.usRefDiv = cpu_to_le16(ref_div);
809 args.v2.usFbDiv = cpu_to_le16(fb_div);
810 args.v2.ucFracFbDiv = frac_fb_div;
811 args.v2.ucPostDiv = post_div;
812 args.v2.ucPpll = pll_id;
813 args.v2.ucCRTC = crtc_id;
814 args.v2.ucRefDivSrc = 1;
817 args.v3.usPixelClock = cpu_to_le16(clock / 10);
818 args.v3.usRefDiv = cpu_to_le16(ref_div);
819 args.v3.usFbDiv = cpu_to_le16(fb_div);
820 args.v3.ucFracFbDiv = frac_fb_div;
821 args.v3.ucPostDiv = post_div;
822 args.v3.ucPpll = pll_id;
823 if (crtc_id == ATOM_CRTC2)
824 args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2;
826 args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1;
827 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
828 args.v3.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC;
829 args.v3.ucTransmitterId = encoder_id;
830 args.v3.ucEncoderMode = encoder_mode;
833 args.v5.ucCRTC = crtc_id;
834 args.v5.usPixelClock = cpu_to_le16(clock / 10);
835 args.v5.ucRefDiv = ref_div;
836 args.v5.usFbDiv = cpu_to_le16(fb_div);
837 args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
838 args.v5.ucPostDiv = post_div;
839 args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */
840 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
841 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC;
845 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP;
848 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP;
851 args.v5.ucTransmitterID = encoder_id;
852 args.v5.ucEncoderMode = encoder_mode;
853 args.v5.ucPpll = pll_id;
856 args.v6.ulDispEngClkFreq = cpu_to_le32(crtc_id << 24 | clock / 10);
857 args.v6.ucRefDiv = ref_div;
858 args.v6.usFbDiv = cpu_to_le16(fb_div);
859 args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
860 args.v6.ucPostDiv = post_div;
861 args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */
862 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
863 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC;
867 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP;
870 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP;
873 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP;
876 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP;
879 args.v6.ucTransmitterID = encoder_id;
880 args.v6.ucEncoderMode = encoder_mode;
881 args.v6.ucPpll = pll_id;
884 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
889 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
893 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
896 static bool atombios_crtc_prepare_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
898 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
899 struct drm_device *dev = crtc->dev;
900 struct radeon_device *rdev = dev->dev_private;
901 struct radeon_encoder *radeon_encoder =
902 to_radeon_encoder(radeon_crtc->encoder);
903 int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder);
905 radeon_crtc->bpc = 8;
906 radeon_crtc->ss_enabled = false;
908 if ((radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
909 (radeon_encoder_get_dp_bridge_encoder_id(radeon_crtc->encoder) != ENCODER_OBJECT_ID_NONE)) {
910 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
911 struct drm_connector *connector =
912 radeon_get_connector_for_encoder(radeon_crtc->encoder);
913 struct radeon_connector *radeon_connector =
914 to_radeon_connector(connector);
915 struct radeon_connector_atom_dig *dig_connector =
916 radeon_connector->con_priv;
918 radeon_crtc->bpc = radeon_get_monitor_bpc(connector);
920 switch (encoder_mode) {
921 case ATOM_ENCODER_MODE_DP_MST:
922 case ATOM_ENCODER_MODE_DP:
924 dp_clock = dig_connector->dp_clock / 10;
925 if (ASIC_IS_DCE4(rdev))
926 radeon_crtc->ss_enabled =
927 radeon_atombios_get_asic_ss_info(rdev, &radeon_crtc->ss,
928 ASIC_INTERNAL_SS_ON_DP,
931 if (dp_clock == 16200) {
932 radeon_crtc->ss_enabled =
933 radeon_atombios_get_ppll_ss_info(rdev,
936 if (!radeon_crtc->ss_enabled)
937 radeon_crtc->ss_enabled =
938 radeon_atombios_get_ppll_ss_info(rdev,
942 radeon_crtc->ss_enabled =
943 radeon_atombios_get_ppll_ss_info(rdev,
948 case ATOM_ENCODER_MODE_LVDS:
949 if (ASIC_IS_DCE4(rdev))
950 radeon_crtc->ss_enabled =
951 radeon_atombios_get_asic_ss_info(rdev,
956 radeon_crtc->ss_enabled =
957 radeon_atombios_get_ppll_ss_info(rdev,
961 case ATOM_ENCODER_MODE_DVI:
962 if (ASIC_IS_DCE4(rdev))
963 radeon_crtc->ss_enabled =
964 radeon_atombios_get_asic_ss_info(rdev,
966 ASIC_INTERNAL_SS_ON_TMDS,
969 case ATOM_ENCODER_MODE_HDMI:
970 if (ASIC_IS_DCE4(rdev))
971 radeon_crtc->ss_enabled =
972 radeon_atombios_get_asic_ss_info(rdev,
974 ASIC_INTERNAL_SS_ON_HDMI,
982 /* adjust pixel clock as needed */
983 radeon_crtc->adjusted_clock = atombios_adjust_pll(crtc, mode);
988 static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
990 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
991 struct drm_device *dev = crtc->dev;
992 struct radeon_device *rdev = dev->dev_private;
993 struct radeon_encoder *radeon_encoder =
994 to_radeon_encoder(radeon_crtc->encoder);
995 u32 pll_clock = mode->clock;
996 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
997 struct radeon_pll *pll;
998 int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder);
1000 switch (radeon_crtc->pll_id) {
1002 pll = &rdev->clock.p1pll;
1005 pll = &rdev->clock.p2pll;
1008 case ATOM_PPLL_INVALID:
1010 pll = &rdev->clock.dcpll;
1014 /* update pll params */
1015 pll->flags = radeon_crtc->pll_flags;
1016 pll->reference_div = radeon_crtc->pll_reference_div;
1017 pll->post_div = radeon_crtc->pll_post_div;
1019 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1020 /* TV seems to prefer the legacy algo on some boards */
1021 radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock,
1022 &fb_div, &frac_fb_div, &ref_div, &post_div);
1023 else if (ASIC_IS_AVIVO(rdev))
1024 radeon_compute_pll_avivo(pll, radeon_crtc->adjusted_clock, &pll_clock,
1025 &fb_div, &frac_fb_div, &ref_div, &post_div);
1027 radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock,
1028 &fb_div, &frac_fb_div, &ref_div, &post_div);
1030 atombios_crtc_program_ss(rdev, ATOM_DISABLE, radeon_crtc->pll_id,
1031 radeon_crtc->crtc_id, &radeon_crtc->ss);
1033 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
1034 encoder_mode, radeon_encoder->encoder_id, mode->clock,
1035 ref_div, fb_div, frac_fb_div, post_div,
1036 radeon_crtc->bpc, radeon_crtc->ss_enabled, &radeon_crtc->ss);
1038 if (radeon_crtc->ss_enabled) {
1039 /* calculate ss amount and step size */
1040 if (ASIC_IS_DCE4(rdev)) {
1042 u32 amount = (((fb_div * 10) + frac_fb_div) * radeon_crtc->ss.percentage) / 10000;
1043 radeon_crtc->ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK;
1044 radeon_crtc->ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) &
1045 ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK;
1046 if (radeon_crtc->ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD)
1047 step_size = (4 * amount * ref_div * (radeon_crtc->ss.rate * 2048)) /
1048 (125 * 25 * pll->reference_freq / 100);
1050 step_size = (2 * amount * ref_div * (radeon_crtc->ss.rate * 2048)) /
1051 (125 * 25 * pll->reference_freq / 100);
1052 radeon_crtc->ss.step = step_size;
1055 atombios_crtc_program_ss(rdev, ATOM_ENABLE, radeon_crtc->pll_id,
1056 radeon_crtc->crtc_id, &radeon_crtc->ss);
1060 static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
1061 struct drm_framebuffer *fb,
1062 int x, int y, int atomic)
1064 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1065 struct drm_device *dev = crtc->dev;
1066 struct radeon_device *rdev = dev->dev_private;
1067 struct radeon_framebuffer *radeon_fb;
1068 struct drm_framebuffer *target_fb;
1069 struct drm_gem_object *obj;
1070 struct radeon_bo *rbo;
1071 uint64_t fb_location;
1072 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
1073 unsigned bankw, bankh, mtaspect, tile_split;
1074 u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE);
1075 u32 tmp, viewport_w, viewport_h;
1079 if (!atomic && !crtc->fb) {
1080 DRM_DEBUG_KMS("No FB bound\n");
1085 radeon_fb = to_radeon_framebuffer(fb);
1089 radeon_fb = to_radeon_framebuffer(crtc->fb);
1090 target_fb = crtc->fb;
1093 /* If atomic, assume fb object is pinned & idle & fenced and
1094 * just update base pointers
1096 obj = radeon_fb->obj;
1097 rbo = gem_to_radeon_bo(obj);
1098 r = radeon_bo_reserve(rbo, false);
1099 if (unlikely(r != 0))
1103 fb_location = radeon_bo_gpu_offset(rbo);
1105 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1106 if (unlikely(r != 0)) {
1107 radeon_bo_unreserve(rbo);
1112 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1113 radeon_bo_unreserve(rbo);
1115 switch (target_fb->bits_per_pixel) {
1117 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) |
1118 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED));
1121 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1122 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555));
1125 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1126 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565));
1128 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1133 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1134 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888));
1136 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
1140 DRM_ERROR("Unsupported screen depth %d\n",
1141 target_fb->bits_per_pixel);
1145 if (tiling_flags & RADEON_TILING_MACRO) {
1146 if (rdev->family >= CHIP_BONAIRE)
1147 tmp = rdev->config.cik.tile_config;
1148 else if (rdev->family >= CHIP_TAHITI)
1149 tmp = rdev->config.si.tile_config;
1150 else if (rdev->family >= CHIP_CAYMAN)
1151 tmp = rdev->config.cayman.tile_config;
1153 tmp = rdev->config.evergreen.tile_config;
1155 switch ((tmp & 0xf0) >> 4) {
1156 case 0: /* 4 banks */
1157 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_4_BANK);
1159 case 1: /* 8 banks */
1161 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_8_BANK);
1163 case 2: /* 16 banks */
1164 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_16_BANK);
1168 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1);
1170 evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split);
1171 fb_format |= EVERGREEN_GRPH_TILE_SPLIT(tile_split);
1172 fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw);
1173 fb_format |= EVERGREEN_GRPH_BANK_HEIGHT(bankh);
1174 fb_format |= EVERGREEN_GRPH_MACRO_TILE_ASPECT(mtaspect);
1175 if (rdev->family >= CHIP_BONAIRE) {
1176 /* XXX need to know more about the surface tiling mode */
1177 fb_format |= CIK_GRPH_MICRO_TILE_MODE(CIK_DISPLAY_MICRO_TILING);
1179 } else if (tiling_flags & RADEON_TILING_MICRO)
1180 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
1182 if (rdev->family >= CHIP_BONAIRE) {
1183 u32 num_pipe_configs = rdev->config.cik.max_tile_pipes;
1184 u32 num_rb = rdev->config.cik.max_backends_per_se;
1185 if (num_pipe_configs > 8)
1186 num_pipe_configs = 8;
1187 if (num_pipe_configs == 8)
1188 fb_format |= CIK_GRPH_PIPE_CONFIG(CIK_ADDR_SURF_P8_32x32_16x16);
1189 else if (num_pipe_configs == 4) {
1191 fb_format |= CIK_GRPH_PIPE_CONFIG(CIK_ADDR_SURF_P4_16x16);
1192 else if (num_rb < 4)
1193 fb_format |= CIK_GRPH_PIPE_CONFIG(CIK_ADDR_SURF_P4_8x16);
1194 } else if (num_pipe_configs == 2)
1195 fb_format |= CIK_GRPH_PIPE_CONFIG(CIK_ADDR_SURF_P2);
1196 } else if ((rdev->family == CHIP_TAHITI) ||
1197 (rdev->family == CHIP_PITCAIRN))
1198 fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P8_32x32_8x16);
1199 else if ((rdev->family == CHIP_VERDE) ||
1200 (rdev->family == CHIP_OLAND) ||
1201 (rdev->family == CHIP_HAINAN)) /* for completeness. HAINAN has no display hw */
1202 fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P4_8x16);
1204 switch (radeon_crtc->crtc_id) {
1206 WREG32(AVIVO_D1VGA_CONTROL, 0);
1209 WREG32(AVIVO_D2VGA_CONTROL, 0);
1212 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
1215 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
1218 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
1221 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
1227 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1228 upper_32_bits(fb_location));
1229 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1230 upper_32_bits(fb_location));
1231 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1232 (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1233 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1234 (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1235 WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1236 WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
1238 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1239 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1240 WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0);
1241 WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1242 WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1243 WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
1245 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
1246 WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1247 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1249 if (rdev->family >= CHIP_BONAIRE)
1250 WREG32(CIK_LB_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1253 WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1257 WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset,
1259 viewport_w = crtc->mode.hdisplay;
1260 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1261 WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1262 (viewport_w << 16) | viewport_h);
1264 /* pageflip setup */
1265 /* make sure flip is at vb rather than hb */
1266 tmp = RREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
1267 tmp &= ~EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN;
1268 WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);
1270 /* set pageflip to happen anywhere in vblank interval */
1271 WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);
1273 if (!atomic && fb && fb != crtc->fb) {
1274 radeon_fb = to_radeon_framebuffer(fb);
1275 rbo = gem_to_radeon_bo(radeon_fb->obj);
1276 r = radeon_bo_reserve(rbo, false);
1277 if (unlikely(r != 0))
1279 radeon_bo_unpin(rbo);
1280 radeon_bo_unreserve(rbo);
1283 /* Bytes per pixel may have changed */
1284 radeon_bandwidth_update(rdev);
1289 static int avivo_crtc_do_set_base(struct drm_crtc *crtc,
1290 struct drm_framebuffer *fb,
1291 int x, int y, int atomic)
1293 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1294 struct drm_device *dev = crtc->dev;
1295 struct radeon_device *rdev = dev->dev_private;
1296 struct radeon_framebuffer *radeon_fb;
1297 struct drm_gem_object *obj;
1298 struct radeon_bo *rbo;
1299 struct drm_framebuffer *target_fb;
1300 uint64_t fb_location;
1301 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
1302 u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE;
1303 u32 tmp, viewport_w, viewport_h;
1307 if (!atomic && !crtc->fb) {
1308 DRM_DEBUG_KMS("No FB bound\n");
1313 radeon_fb = to_radeon_framebuffer(fb);
1317 radeon_fb = to_radeon_framebuffer(crtc->fb);
1318 target_fb = crtc->fb;
1321 obj = radeon_fb->obj;
1322 rbo = gem_to_radeon_bo(obj);
1323 r = radeon_bo_reserve(rbo, false);
1324 if (unlikely(r != 0))
1327 /* If atomic, assume fb object is pinned & idle & fenced and
1328 * just update base pointers
1331 fb_location = radeon_bo_gpu_offset(rbo);
1333 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1334 if (unlikely(r != 0)) {
1335 radeon_bo_unreserve(rbo);
1339 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1340 radeon_bo_unreserve(rbo);
1342 switch (target_fb->bits_per_pixel) {
1345 AVIVO_D1GRPH_CONTROL_DEPTH_8BPP |
1346 AVIVO_D1GRPH_CONTROL_8BPP_INDEXED;
1350 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1351 AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
1355 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1356 AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
1358 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;
1364 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
1365 AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
1367 fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT;
1371 DRM_ERROR("Unsupported screen depth %d\n",
1372 target_fb->bits_per_pixel);
1376 if (rdev->family >= CHIP_R600) {
1377 if (tiling_flags & RADEON_TILING_MACRO)
1378 fb_format |= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1;
1379 else if (tiling_flags & RADEON_TILING_MICRO)
1380 fb_format |= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1;
1382 if (tiling_flags & RADEON_TILING_MACRO)
1383 fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
1385 if (tiling_flags & RADEON_TILING_MICRO)
1386 fb_format |= AVIVO_D1GRPH_TILED;
1389 if (radeon_crtc->crtc_id == 0)
1390 WREG32(AVIVO_D1VGA_CONTROL, 0);
1392 WREG32(AVIVO_D2VGA_CONTROL, 0);
1394 if (rdev->family >= CHIP_RV770) {
1395 if (radeon_crtc->crtc_id) {
1396 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1397 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1399 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1400 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1403 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1405 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS +
1406 radeon_crtc->crtc_offset, (u32) fb_location);
1407 WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1408 if (rdev->family >= CHIP_R600)
1409 WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
1411 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1412 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1413 WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
1414 WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1415 WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1416 WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
1418 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
1419 WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1420 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1422 WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1426 WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,
1428 viewport_w = crtc->mode.hdisplay;
1429 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1430 WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1431 (viewport_w << 16) | viewport_h);
1433 /* pageflip setup */
1434 /* make sure flip is at vb rather than hb */
1435 tmp = RREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
1436 tmp &= ~AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN;
1437 WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);
1439 /* set pageflip to happen anywhere in vblank interval */
1440 WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);
1442 if (!atomic && fb && fb != crtc->fb) {
1443 radeon_fb = to_radeon_framebuffer(fb);
1444 rbo = gem_to_radeon_bo(radeon_fb->obj);
1445 r = radeon_bo_reserve(rbo, false);
1446 if (unlikely(r != 0))
1448 radeon_bo_unpin(rbo);
1449 radeon_bo_unreserve(rbo);
1452 /* Bytes per pixel may have changed */
1453 radeon_bandwidth_update(rdev);
1458 int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
1459 struct drm_framebuffer *old_fb)
1461 struct drm_device *dev = crtc->dev;
1462 struct radeon_device *rdev = dev->dev_private;
1464 if (ASIC_IS_DCE4(rdev))
1465 return dce4_crtc_do_set_base(crtc, old_fb, x, y, 0);
1466 else if (ASIC_IS_AVIVO(rdev))
1467 return avivo_crtc_do_set_base(crtc, old_fb, x, y, 0);
1469 return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0);
1472 int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
1473 struct drm_framebuffer *fb,
1474 int x, int y, enum mode_set_atomic state)
1476 struct drm_device *dev = crtc->dev;
1477 struct radeon_device *rdev = dev->dev_private;
1479 if (ASIC_IS_DCE4(rdev))
1480 return dce4_crtc_do_set_base(crtc, fb, x, y, 1);
1481 else if (ASIC_IS_AVIVO(rdev))
1482 return avivo_crtc_do_set_base(crtc, fb, x, y, 1);
1484 return radeon_crtc_do_set_base(crtc, fb, x, y, 1);
1487 /* properly set additional regs when using atombios */
1488 static void radeon_legacy_atom_fixup(struct drm_crtc *crtc)
1490 struct drm_device *dev = crtc->dev;
1491 struct radeon_device *rdev = dev->dev_private;
1492 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1493 u32 disp_merge_cntl;
1495 switch (radeon_crtc->crtc_id) {
1497 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
1498 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
1499 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
1502 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
1503 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
1504 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
1505 WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
1506 WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
1512 * radeon_get_pll_use_mask - look up a mask of which pplls are in use
1516 * Returns the mask of which PPLLs (Pixel PLLs) are in use.
1518 static u32 radeon_get_pll_use_mask(struct drm_crtc *crtc)
1520 struct drm_device *dev = crtc->dev;
1521 struct drm_crtc *test_crtc;
1522 struct radeon_crtc *test_radeon_crtc;
1525 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1526 if (crtc == test_crtc)
1529 test_radeon_crtc = to_radeon_crtc(test_crtc);
1530 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
1531 pll_in_use |= (1 << test_radeon_crtc->pll_id);
1537 * radeon_get_shared_dp_ppll - return the PPLL used by another crtc for DP
1541 * Returns the PPLL (Pixel PLL) used by another crtc/encoder which is
1542 * also in DP mode. For DP, a single PPLL can be used for all DP
1545 static int radeon_get_shared_dp_ppll(struct drm_crtc *crtc)
1547 struct drm_device *dev = crtc->dev;
1548 struct drm_crtc *test_crtc;
1549 struct radeon_crtc *test_radeon_crtc;
1551 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1552 if (crtc == test_crtc)
1554 test_radeon_crtc = to_radeon_crtc(test_crtc);
1555 if (test_radeon_crtc->encoder &&
1556 ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) {
1557 /* for DP use the same PLL for all */
1558 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
1559 return test_radeon_crtc->pll_id;
1562 return ATOM_PPLL_INVALID;
1566 * radeon_get_shared_nondp_ppll - return the PPLL used by another non-DP crtc
1569 * @encoder: drm encoder
1571 * Returns the PPLL (Pixel PLL) used by another non-DP crtc/encoder which can
1572 * be shared (i.e., same clock).
1574 static int radeon_get_shared_nondp_ppll(struct drm_crtc *crtc)
1576 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1577 struct drm_device *dev = crtc->dev;
1578 struct drm_crtc *test_crtc;
1579 struct radeon_crtc *test_radeon_crtc;
1580 u32 adjusted_clock, test_adjusted_clock;
1582 adjusted_clock = radeon_crtc->adjusted_clock;
1584 if (adjusted_clock == 0)
1585 return ATOM_PPLL_INVALID;
1587 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1588 if (crtc == test_crtc)
1590 test_radeon_crtc = to_radeon_crtc(test_crtc);
1591 if (test_radeon_crtc->encoder &&
1592 !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) {
1593 /* check if we are already driving this connector with another crtc */
1594 if (test_radeon_crtc->connector == radeon_crtc->connector) {
1595 /* if we are, return that pll */
1596 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
1597 return test_radeon_crtc->pll_id;
1599 /* for non-DP check the clock */
1600 test_adjusted_clock = test_radeon_crtc->adjusted_clock;
1601 if ((crtc->mode.clock == test_crtc->mode.clock) &&
1602 (adjusted_clock == test_adjusted_clock) &&
1603 (radeon_crtc->ss_enabled == test_radeon_crtc->ss_enabled) &&
1604 (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID))
1605 return test_radeon_crtc->pll_id;
1608 return ATOM_PPLL_INVALID;
1612 * radeon_atom_pick_pll - Allocate a PPLL for use by the crtc.
1616 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
1617 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
1618 * monitors a dedicated PPLL must be used. If a particular board has
1619 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
1620 * as there is no need to program the PLL itself. If we are not able to
1621 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
1622 * avoid messing up an existing monitor.
1624 * Asic specific PLL information
1628 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
1630 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1633 * - PPLL2 is only available to UNIPHYA (both DP and non-DP)
1634 * - PPLL0, PPLL1 are available for UNIPHYB/C/D/E/F (both DP and non-DP)
1637 * - PPLL0 is available to all UNIPHY (DP only)
1638 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1641 * - DCPLL is available to all UNIPHY (DP only)
1642 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1645 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1648 static int radeon_atom_pick_pll(struct drm_crtc *crtc)
1650 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1651 struct drm_device *dev = crtc->dev;
1652 struct radeon_device *rdev = dev->dev_private;
1653 struct radeon_encoder *radeon_encoder =
1654 to_radeon_encoder(radeon_crtc->encoder);
1658 if (ASIC_IS_DCE8(rdev)) {
1659 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
1660 if (rdev->clock.dp_extclk)
1661 /* skip PPLL programming if using ext clock */
1662 return ATOM_PPLL_INVALID;
1664 /* use the same PPLL for all DP monitors */
1665 pll = radeon_get_shared_dp_ppll(crtc);
1666 if (pll != ATOM_PPLL_INVALID)
1670 /* use the same PPLL for all monitors with the same clock */
1671 pll = radeon_get_shared_nondp_ppll(crtc);
1672 if (pll != ATOM_PPLL_INVALID)
1675 /* otherwise, pick one of the plls */
1676 if ((rdev->family == CHIP_KAVERI) ||
1677 (rdev->family == CHIP_KABINI)) {
1678 /* KB/KV has PPLL1 and PPLL2 */
1679 pll_in_use = radeon_get_pll_use_mask(crtc);
1680 if (!(pll_in_use & (1 << ATOM_PPLL2)))
1682 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1684 DRM_ERROR("unable to allocate a PPLL\n");
1685 return ATOM_PPLL_INVALID;
1687 /* CI has PPLL0, PPLL1, and PPLL2 */
1688 pll_in_use = radeon_get_pll_use_mask(crtc);
1689 if (!(pll_in_use & (1 << ATOM_PPLL2)))
1691 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1693 if (!(pll_in_use & (1 << ATOM_PPLL0)))
1695 DRM_ERROR("unable to allocate a PPLL\n");
1696 return ATOM_PPLL_INVALID;
1698 } else if (ASIC_IS_DCE61(rdev)) {
1699 struct radeon_encoder_atom_dig *dig =
1700 radeon_encoder->enc_priv;
1702 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY) &&
1703 (dig->linkb == false))
1704 /* UNIPHY A uses PPLL2 */
1706 else if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
1707 /* UNIPHY B/C/D/E/F */
1708 if (rdev->clock.dp_extclk)
1709 /* skip PPLL programming if using ext clock */
1710 return ATOM_PPLL_INVALID;
1712 /* use the same PPLL for all DP monitors */
1713 pll = radeon_get_shared_dp_ppll(crtc);
1714 if (pll != ATOM_PPLL_INVALID)
1718 /* use the same PPLL for all monitors with the same clock */
1719 pll = radeon_get_shared_nondp_ppll(crtc);
1720 if (pll != ATOM_PPLL_INVALID)
1723 /* UNIPHY B/C/D/E/F */
1724 pll_in_use = radeon_get_pll_use_mask(crtc);
1725 if (!(pll_in_use & (1 << ATOM_PPLL0)))
1727 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1729 DRM_ERROR("unable to allocate a PPLL\n");
1730 return ATOM_PPLL_INVALID;
1731 } else if (ASIC_IS_DCE4(rdev)) {
1732 /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock,
1733 * depending on the asic:
1734 * DCE4: PPLL or ext clock
1735 * DCE5: PPLL, DCPLL, or ext clock
1736 * DCE6: PPLL, PPLL0, or ext clock
1738 * Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip
1739 * PPLL/DCPLL programming and only program the DP DTO for the
1740 * crtc virtual pixel clock.
1742 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
1743 if (rdev->clock.dp_extclk)
1744 /* skip PPLL programming if using ext clock */
1745 return ATOM_PPLL_INVALID;
1746 else if (ASIC_IS_DCE6(rdev))
1747 /* use PPLL0 for all DP */
1749 else if (ASIC_IS_DCE5(rdev))
1750 /* use DCPLL for all DP */
1753 /* use the same PPLL for all DP monitors */
1754 pll = radeon_get_shared_dp_ppll(crtc);
1755 if (pll != ATOM_PPLL_INVALID)
1758 } else if (!ASIC_IS_DCE41(rdev)) { /* Don't share PLLs on DCE4.1 chips */
1759 /* use the same PPLL for all monitors with the same clock */
1760 pll = radeon_get_shared_nondp_ppll(crtc);
1761 if (pll != ATOM_PPLL_INVALID)
1764 /* all other cases */
1765 pll_in_use = radeon_get_pll_use_mask(crtc);
1766 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1768 if (!(pll_in_use & (1 << ATOM_PPLL2)))
1770 DRM_ERROR("unable to allocate a PPLL\n");
1771 return ATOM_PPLL_INVALID;
1773 /* on pre-R5xx asics, the crtc to pll mapping is hardcoded */
1774 /* some atombios (observed in some DCE2/DCE3) code have a bug,
1775 * the matching btw pll and crtc is done through
1776 * PCLK_CRTC[1|2]_CNTL (0x480/0x484) but atombios code use the
1777 * pll (1 or 2) to select which register to write. ie if using
1778 * pll1 it will use PCLK_CRTC1_CNTL (0x480) and if using pll2
1779 * it will use PCLK_CRTC2_CNTL (0x484), it then use crtc id to
1780 * choose which value to write. Which is reverse order from
1781 * register logic. So only case that works is when pllid is
1782 * same as crtcid or when both pll and crtc are enabled and
1783 * both use same clock.
1785 * So just return crtc id as if crtc and pll were hard linked
1786 * together even if they aren't
1788 return radeon_crtc->crtc_id;
1792 void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev)
1794 /* always set DCPLL */
1795 if (ASIC_IS_DCE6(rdev))
1796 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk);
1797 else if (ASIC_IS_DCE4(rdev)) {
1798 struct radeon_atom_ss ss;
1799 bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss,
1800 ASIC_INTERNAL_SS_ON_DCPLL,
1801 rdev->clock.default_dispclk);
1803 atombios_crtc_program_ss(rdev, ATOM_DISABLE, ATOM_DCPLL, -1, &ss);
1804 /* XXX: DCE5, make sure voltage, dispclk is high enough */
1805 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk);
1807 atombios_crtc_program_ss(rdev, ATOM_ENABLE, ATOM_DCPLL, -1, &ss);
1812 int atombios_crtc_mode_set(struct drm_crtc *crtc,
1813 struct drm_display_mode *mode,
1814 struct drm_display_mode *adjusted_mode,
1815 int x, int y, struct drm_framebuffer *old_fb)
1817 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1818 struct drm_device *dev = crtc->dev;
1819 struct radeon_device *rdev = dev->dev_private;
1820 struct radeon_encoder *radeon_encoder =
1821 to_radeon_encoder(radeon_crtc->encoder);
1822 bool is_tvcv = false;
1824 if (radeon_encoder->active_device &
1825 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1828 atombios_crtc_set_pll(crtc, adjusted_mode);
1830 if (ASIC_IS_DCE4(rdev))
1831 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1832 else if (ASIC_IS_AVIVO(rdev)) {
1834 atombios_crtc_set_timing(crtc, adjusted_mode);
1836 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1838 atombios_crtc_set_timing(crtc, adjusted_mode);
1839 if (radeon_crtc->crtc_id == 0)
1840 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1841 radeon_legacy_atom_fixup(crtc);
1843 atombios_crtc_set_base(crtc, x, y, old_fb);
1844 atombios_overscan_setup(crtc, mode, adjusted_mode);
1845 atombios_scaler_setup(crtc);
1846 /* update the hw version fpr dpm */
1847 radeon_crtc->hw_mode = *adjusted_mode;
1852 static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
1853 const struct drm_display_mode *mode,
1854 struct drm_display_mode *adjusted_mode)
1856 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1857 struct drm_device *dev = crtc->dev;
1858 struct drm_encoder *encoder;
1860 /* assign the encoder to the radeon crtc to avoid repeated lookups later */
1861 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1862 if (encoder->crtc == crtc) {
1863 radeon_crtc->encoder = encoder;
1864 radeon_crtc->connector = radeon_get_connector_for_encoder(encoder);
1868 if ((radeon_crtc->encoder == NULL) || (radeon_crtc->connector == NULL)) {
1869 radeon_crtc->encoder = NULL;
1870 radeon_crtc->connector = NULL;
1873 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
1875 if (!atombios_crtc_prepare_pll(crtc, adjusted_mode))
1878 radeon_crtc->pll_id = radeon_atom_pick_pll(crtc);
1879 /* if we can't get a PPLL for a non-DP encoder, fail */
1880 if ((radeon_crtc->pll_id == ATOM_PPLL_INVALID) &&
1881 !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder)))
1887 static void atombios_crtc_prepare(struct drm_crtc *crtc)
1889 struct drm_device *dev = crtc->dev;
1890 struct radeon_device *rdev = dev->dev_private;
1892 /* disable crtc pair power gating before programming */
1893 if (ASIC_IS_DCE6(rdev))
1894 atombios_powergate_crtc(crtc, ATOM_DISABLE);
1896 atombios_lock_crtc(crtc, ATOM_ENABLE);
1897 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1900 static void atombios_crtc_commit(struct drm_crtc *crtc)
1902 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
1903 atombios_lock_crtc(crtc, ATOM_DISABLE);
1906 static void atombios_crtc_disable(struct drm_crtc *crtc)
1908 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1909 struct drm_device *dev = crtc->dev;
1910 struct radeon_device *rdev = dev->dev_private;
1911 struct radeon_atom_ss ss;
1914 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1917 struct radeon_framebuffer *radeon_fb;
1918 struct radeon_bo *rbo;
1920 radeon_fb = to_radeon_framebuffer(crtc->fb);
1921 rbo = gem_to_radeon_bo(radeon_fb->obj);
1922 r = radeon_bo_reserve(rbo, false);
1924 DRM_ERROR("failed to reserve rbo before unpin\n");
1926 radeon_bo_unpin(rbo);
1927 radeon_bo_unreserve(rbo);
1930 /* disable the GRPH */
1931 if (ASIC_IS_DCE4(rdev))
1932 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 0);
1933 else if (ASIC_IS_AVIVO(rdev))
1934 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 0);
1936 if (ASIC_IS_DCE6(rdev))
1937 atombios_powergate_crtc(crtc, ATOM_ENABLE);
1939 for (i = 0; i < rdev->num_crtc; i++) {
1940 if (rdev->mode_info.crtcs[i] &&
1941 rdev->mode_info.crtcs[i]->enabled &&
1942 i != radeon_crtc->crtc_id &&
1943 radeon_crtc->pll_id == rdev->mode_info.crtcs[i]->pll_id) {
1944 /* one other crtc is using this pll don't turn
1951 switch (radeon_crtc->pll_id) {
1954 /* disable the ppll */
1955 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
1956 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
1959 /* disable the ppll */
1960 if ((rdev->family == CHIP_ARUBA) ||
1961 (rdev->family == CHIP_BONAIRE) ||
1962 (rdev->family == CHIP_HAWAII))
1963 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
1964 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
1970 radeon_crtc->pll_id = ATOM_PPLL_INVALID;
1971 radeon_crtc->adjusted_clock = 0;
1972 radeon_crtc->encoder = NULL;
1973 radeon_crtc->connector = NULL;
1976 static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
1977 .dpms = atombios_crtc_dpms,
1978 .mode_fixup = atombios_crtc_mode_fixup,
1979 .mode_set = atombios_crtc_mode_set,
1980 .mode_set_base = atombios_crtc_set_base,
1981 .mode_set_base_atomic = atombios_crtc_set_base_atomic,
1982 .prepare = atombios_crtc_prepare,
1983 .commit = atombios_crtc_commit,
1984 .load_lut = radeon_crtc_load_lut,
1985 .disable = atombios_crtc_disable,
1988 void radeon_atombios_init_crtc(struct drm_device *dev,
1989 struct radeon_crtc *radeon_crtc)
1991 struct radeon_device *rdev = dev->dev_private;
1993 if (ASIC_IS_DCE4(rdev)) {
1994 switch (radeon_crtc->crtc_id) {
1997 radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET;
2000 radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET;
2003 radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET;
2006 radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET;
2009 radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET;
2012 radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET;
2016 if (radeon_crtc->crtc_id == 1)
2017 radeon_crtc->crtc_offset =
2018 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
2020 radeon_crtc->crtc_offset = 0;
2022 radeon_crtc->pll_id = ATOM_PPLL_INVALID;
2023 radeon_crtc->adjusted_clock = 0;
2024 radeon_crtc->encoder = NULL;
2025 radeon_crtc->connector = NULL;
2026 drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);