Pileus Git - ~andy/linux/blob - drivers/gpu/drm/nouveau/nvd0_display.c

   1 /*
   2  * Copyright 2011 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <linux/dma-mapping.h>
  26
  27 #include "drmP.h"
  28 #include "drm_crtc_helper.h"
  29
  30 #include "nouveau_drv.h"
  31 #include "nouveau_connector.h"
  32 #include "nouveau_encoder.h"
  33 #include "nouveau_crtc.h"
  34 #include "nouveau_fb.h"
  35 #include "nouveau_fence.h"
  36 #include "nv50_display.h"
  37
  38 #define EVO_DMA_NR 9
  39
  40 #define EVO_MASTER  (0x00)
  41 #define EVO_FLIP(c) (0x01 + (c))
  42 #define EVO_OVLY(c) (0x05 + (c))
  43 #define EVO_OIMM(c) (0x09 + (c))
  44 #define EVO_CURS(c) (0x0d + (c))
  45
  46 /* offsets in shared sync bo of various structures */
  47 #define EVO_SYNC(c, o) ((c) * 0x0100 + (o))
  48 #define EVO_MAST_NTFY     EVO_SYNC(  0, 0x00)
  49 #define EVO_FLIP_SEM0(c)  EVO_SYNC((c), 0x00)
  50 #define EVO_FLIP_SEM1(c)  EVO_SYNC((c), 0x10)
  51
  52 struct evo {
  53         int idx;
  54         dma_addr_t handle;
  55         u32 *ptr;
  56         struct {
  57                 u32 offset;
  58                 u16 value;
  59         } sem;
  60 };
  61
  62 struct nvd0_display {
  63         struct nouveau_gpuobj *mem;
  64         struct nouveau_bo *sync;
  65         struct evo evo[9];
  66
  67         struct tasklet_struct tasklet;
  68         u32 modeset;
  69 };
  70
  71 static struct nvd0_display *
  72 nvd0_display(struct drm_device *dev)
  73 {
  74         struct drm_nouveau_private *dev_priv = dev->dev_private;
  75         return dev_priv->engine.display.priv;
  76 }
  77
  78 static struct drm_crtc *
  79 nvd0_display_crtc_get(struct drm_encoder *encoder)
  80 {
  81         return nouveau_encoder(encoder)->crtc;
  82 }
  83
  84 /******************************************************************************
  85  * EVO channel helpers
  86  *****************************************************************************/
  87 static inline int
  88 evo_icmd(struct drm_device *dev, int id, u32 mthd, u32 data)
  89 {
  90         int ret = 0;
  91         nv_mask(dev, 0x610700 + (id * 0x10), 0x00000001, 0x00000001);
  92         nv_wr32(dev, 0x610704 + (id * 0x10), data);
  93         nv_mask(dev, 0x610704 + (id * 0x10), 0x80000ffc, 0x80000000 | mthd);
  94         if (!nv_wait(dev, 0x610704 + (id * 0x10), 0x80000000, 0x00000000))
  95                 ret = -EBUSY;
  96         nv_mask(dev, 0x610700 + (id * 0x10), 0x00000001, 0x00000000);
  97         return ret;
  98 }
  99
 100 static u32 *
 101 evo_wait(struct drm_device *dev, int id, int nr)
 102 {
 103         struct nvd0_display *disp = nvd0_display(dev);
 104         u32 put = nv_rd32(dev, 0x640000 + (id * 0x1000)) / 4;
 105
 106         if (put + nr >= (PAGE_SIZE / 4)) {
 107                 disp->evo[id].ptr[put] = 0x20000000;
 108
 109                 nv_wr32(dev, 0x640000 + (id * 0x1000), 0x00000000);
 110                 if (!nv_wait(dev, 0x640004 + (id * 0x1000), ~0, 0x00000000)) {
 111                         NV_ERROR(dev, "evo %d dma stalled\n", id);
 112                         return NULL;
 113                 }
 114
 115                 put = 0;
 116         }
 117
 118         return disp->evo[id].ptr + put;
 119 }
 120
 121 static void
 122 evo_kick(u32 *push, struct drm_device *dev, int id)
 123 {
 124         struct nvd0_display *disp = nvd0_display(dev);
 125
 126         nv_wr32(dev, 0x640000 + (id * 0x1000), (push - disp->evo[id].ptr) << 2);
 127 }
 128
 129 #define evo_mthd(p,m,s) *((p)++) = (((s) << 18) | (m))
 130 #define evo_data(p,d)   *((p)++) = (d)
 131
 132 static int
 133 evo_init_dma(struct drm_device *dev, int ch)
 134 {
 135         struct nvd0_display *disp = nvd0_display(dev);
 136         u32 flags;
 137
 138         flags = 0x00000000;
 139         if (ch == EVO_MASTER)
 140                 flags |= 0x01000000;
 141
 142         nv_wr32(dev, 0x610494 + (ch * 0x0010), (disp->evo[ch].handle >> 8) | 3);
 143         nv_wr32(dev, 0x610498 + (ch * 0x0010), 0x00010000);
 144         nv_wr32(dev, 0x61049c + (ch * 0x0010), 0x00000001);
 145         nv_mask(dev, 0x610490 + (ch * 0x0010), 0x00000010, 0x00000010);
 146         nv_wr32(dev, 0x640000 + (ch * 0x1000), 0x00000000);
 147         nv_wr32(dev, 0x610490 + (ch * 0x0010), 0x00000013 | flags);
 148         if (!nv_wait(dev, 0x610490 + (ch * 0x0010), 0x80000000, 0x00000000)) {
 149                 NV_ERROR(dev, "PDISP: ch%d 0x%08x\n", ch,
 150                               nv_rd32(dev, 0x610490 + (ch * 0x0010)));
 151                 return -EBUSY;
 152         }
 153
 154         nv_mask(dev, 0x610090, (1 << ch), (1 << ch));
 155         nv_mask(dev, 0x6100a0, (1 << ch), (1 << ch));
 156         return 0;
 157 }
 158
 159 static void
 160 evo_fini_dma(struct drm_device *dev, int ch)
 161 {
 162         if (!(nv_rd32(dev, 0x610490 + (ch * 0x0010)) & 0x00000010))
 163                 return;
 164
 165         nv_mask(dev, 0x610490 + (ch * 0x0010), 0x00000010, 0x00000000);
 166         nv_mask(dev, 0x610490 + (ch * 0x0010), 0x00000003, 0x00000000);
 167         nv_wait(dev, 0x610490 + (ch * 0x0010), 0x80000000, 0x00000000);
 168         nv_mask(dev, 0x610090, (1 << ch), 0x00000000);
 169         nv_mask(dev, 0x6100a0, (1 << ch), 0x00000000);
 170 }
 171
 172 static inline void
 173 evo_piow(struct drm_device *dev, int ch, u16 mthd, u32 data)
 174 {
 175         nv_wr32(dev, 0x640000 + (ch * 0x1000) + mthd, data);
 176 }
 177
 178 static int
 179 evo_init_pio(struct drm_device *dev, int ch)
 180 {
 181         nv_wr32(dev, 0x610490 + (ch * 0x0010), 0x00000001);
 182         if (!nv_wait(dev, 0x610490 + (ch * 0x0010), 0x00010000, 0x00010000)) {
 183                 NV_ERROR(dev, "PDISP: ch%d 0x%08x\n", ch,
 184                               nv_rd32(dev, 0x610490 + (ch * 0x0010)));
 185                 return -EBUSY;
 186         }
 187
 188         nv_mask(dev, 0x610090, (1 << ch), (1 << ch));
 189         nv_mask(dev, 0x6100a0, (1 << ch), (1 << ch));
 190         return 0;
 191 }
 192
 193 static void
 194 evo_fini_pio(struct drm_device *dev, int ch)
 195 {
 196         if (!(nv_rd32(dev, 0x610490 + (ch * 0x0010)) & 0x00000001))
 197                 return;
 198
 199         nv_mask(dev, 0x610490 + (ch * 0x0010), 0x00000010, 0x00000010);
 200         nv_mask(dev, 0x610490 + (ch * 0x0010), 0x00000001, 0x00000000);
 201         nv_wait(dev, 0x610490 + (ch * 0x0010), 0x00010000, 0x00000000);
 202         nv_mask(dev, 0x610090, (1 << ch), 0x00000000);
 203         nv_mask(dev, 0x6100a0, (1 << ch), 0x00000000);
 204 }
 205
 206 static bool
 207 evo_sync_wait(void *data)
 208 {
 209         return nouveau_bo_rd32(data, EVO_MAST_NTFY) != 0x00000000;
 210 }
 211
 212 static int
 213 evo_sync(struct drm_device *dev, int ch)
 214 {
 215         struct nvd0_display *disp = nvd0_display(dev);
 216         u32 *push = evo_wait(dev, ch, 8);
 217         if (push) {
 218                 nouveau_bo_wr32(disp->sync, EVO_MAST_NTFY, 0x00000000);
 219                 evo_mthd(push, 0x0084, 1);
 220                 evo_data(push, 0x80000000 | EVO_MAST_NTFY);
 221                 evo_mthd(push, 0x0080, 2);
 222                 evo_data(push, 0x00000000);
 223                 evo_data(push, 0x00000000);
 224                 evo_kick(push, dev, ch);
 225                 if (nv_wait_cb(dev, evo_sync_wait, disp->sync))
 226                         return 0;
 227         }
 228
 229         return -EBUSY;
 230 }
 231
 232 /******************************************************************************
 233  * Page flipping channel
 234  *****************************************************************************/
 235 struct nouveau_bo *
 236 nvd0_display_crtc_sema(struct drm_device *dev, int crtc)
 237 {
 238         return nvd0_display(dev)->sync;
 239 }
 240
 241 void
 242 nvd0_display_flip_stop(struct drm_crtc *crtc)
 243 {
 244         struct nvd0_display *disp = nvd0_display(crtc->dev);
 245         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 246         struct evo *evo = &disp->evo[EVO_FLIP(nv_crtc->index)];
 247         u32 *push;
 248
 249         push = evo_wait(crtc->dev, evo->idx, 8);
 250         if (push) {
 251                 evo_mthd(push, 0x0084, 1);
 252                 evo_data(push, 0x00000000);
 253                 evo_mthd(push, 0x0094, 1);
 254                 evo_data(push, 0x00000000);
 255                 evo_mthd(push, 0x00c0, 1);
 256                 evo_data(push, 0x00000000);
 257                 evo_mthd(push, 0x0080, 1);
 258                 evo_data(push, 0x00000000);
 259                 evo_kick(push, crtc->dev, evo->idx);
 260         }
 261 }
 262
 263 int
 264 nvd0_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb,
 265                        struct nouveau_channel *chan, u32 swap_interval)
 266 {
 267         struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb);
 268         struct nvd0_display *disp = nvd0_display(crtc->dev);
 269         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 270         struct evo *evo = &disp->evo[EVO_FLIP(nv_crtc->index)];
 271         u64 offset;
 272         u32 *push;
 273         int ret;
 274
 275         swap_interval <<= 4;
 276         if (swap_interval == 0)
 277                 swap_interval |= 0x100;
 278
 279         push = evo_wait(crtc->dev, evo->idx, 128);
 280         if (unlikely(push == NULL))
 281                 return -EBUSY;
 282
 283         /* synchronise with the rendering channel, if necessary */
 284         if (likely(chan)) {
 285                 ret = RING_SPACE(chan, 10);
 286                 if (ret)
 287                         return ret;
 288
 289
 290                 offset  = nvc0_fence_crtc(chan, nv_crtc->index);
 291                 offset += evo->sem.offset;
 292
 293                 BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
 294                 OUT_RING  (chan, upper_32_bits(offset));
 295                 OUT_RING  (chan, lower_32_bits(offset));
 296                 OUT_RING  (chan, 0xf00d0000 | evo->sem.value);
 297                 OUT_RING  (chan, 0x1002);
 298                 BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
 299                 OUT_RING  (chan, upper_32_bits(offset));
 300                 OUT_RING  (chan, lower_32_bits(offset ^ 0x10));
 301                 OUT_RING  (chan, 0x74b1e000);
 302                 OUT_RING  (chan, 0x1001);
 303                 FIRE_RING (chan);
 304         } else {
 305                 nouveau_bo_wr32(disp->sync, evo->sem.offset / 4,
 306                                 0xf00d0000 | evo->sem.value);
 307                 evo_sync(crtc->dev, EVO_MASTER);
 308         }
 309
 310         /* queue the flip */
 311         evo_mthd(push, 0x0100, 1);
 312         evo_data(push, 0xfffe0000);
 313         evo_mthd(push, 0x0084, 1);
 314         evo_data(push, swap_interval);
 315         if (!(swap_interval & 0x00000100)) {
 316                 evo_mthd(push, 0x00e0, 1);
 317                 evo_data(push, 0x40000000);
 318         }
 319         evo_mthd(push, 0x0088, 4);
 320         evo_data(push, evo->sem.offset);
 321         evo_data(push, 0xf00d0000 | evo->sem.value);
 322         evo_data(push, 0x74b1e000);
 323         evo_data(push, NvEvoSync);
 324         evo_mthd(push, 0x00a0, 2);
 325         evo_data(push, 0x00000000);
 326         evo_data(push, 0x00000000);
 327         evo_mthd(push, 0x00c0, 1);
 328         evo_data(push, nv_fb->r_dma);
 329         evo_mthd(push, 0x0110, 2);
 330         evo_data(push, 0x00000000);
 331         evo_data(push, 0x00000000);
 332         evo_mthd(push, 0x0400, 5);
 333         evo_data(push, nv_fb->nvbo->bo.offset >> 8);
 334         evo_data(push, 0);
 335         evo_data(push, (fb->height << 16) | fb->width);
 336         evo_data(push, nv_fb->r_pitch);
 337         evo_data(push, nv_fb->r_format);
 338         evo_mthd(push, 0x0080, 1);
 339         evo_data(push, 0x00000000);
 340         evo_kick(push, crtc->dev, evo->idx);
 341
 342         evo->sem.offset ^= 0x10;
 343         evo->sem.value++;
 344         return 0;
 345 }
 346
 347 /******************************************************************************
 348  * CRTC
 349  *****************************************************************************/
 350 static int
 351 nvd0_crtc_set_dither(struct nouveau_crtc *nv_crtc, bool update)
 352 {
 353         struct drm_nouveau_private *dev_priv = nv_crtc->base.dev->dev_private;
 354         struct drm_device *dev = nv_crtc->base.dev;
 355         struct nouveau_connector *nv_connector;
 356         struct drm_connector *connector;
 357         u32 *push, mode = 0x00;
 358         u32 mthd;
 359
 360         nv_connector = nouveau_crtc_connector_get(nv_crtc);
 361         connector = &nv_connector->base;
 362         if (nv_connector->dithering_mode == DITHERING_MODE_AUTO) {
 363                 if (nv_crtc->base.fb->depth > connector->display_info.bpc * 3)
 364                         mode = DITHERING_MODE_DYNAMIC2X2;
 365         } else {
 366                 mode = nv_connector->dithering_mode;
 367         }
 368
 369         if (nv_connector->dithering_depth == DITHERING_DEPTH_AUTO) {
 370                 if (connector->display_info.bpc >= 8)
 371                         mode |= DITHERING_DEPTH_8BPC;
 372         } else {
 373                 mode |= nv_connector->dithering_depth;
 374         }
 375
 376         if (dev_priv->card_type < NV_E0)
 377                 mthd = 0x0490 + (nv_crtc->index * 0x0300);
 378         else
 379                 mthd = 0x04a0 + (nv_crtc->index * 0x0300);
 380
 381         push = evo_wait(dev, EVO_MASTER, 4);
 382         if (push) {
 383                 evo_mthd(push, mthd, 1);
 384                 evo_data(push, mode);
 385                 if (update) {
 386                         evo_mthd(push, 0x0080, 1);
 387                         evo_data(push, 0x00000000);
 388                 }
 389                 evo_kick(push, dev, EVO_MASTER);
 390         }
 391
 392         return 0;
 393 }
 394
 395 static int
 396 nvd0_crtc_set_scale(struct nouveau_crtc *nv_crtc, bool update)
 397 {
 398         struct drm_display_mode *omode, *umode = &nv_crtc->base.mode;
 399         struct drm_device *dev = nv_crtc->base.dev;
 400         struct drm_crtc *crtc = &nv_crtc->base;
 401         struct nouveau_connector *nv_connector;
 402         int mode = DRM_MODE_SCALE_NONE;
 403         u32 oX, oY, *push;
 404
 405         /* start off at the resolution we programmed the crtc for, this
 406          * effectively handles NONE/FULL scaling
 407          */
 408         nv_connector = nouveau_crtc_connector_get(nv_crtc);
 409         if (nv_connector && nv_connector->native_mode)
 410                 mode = nv_connector->scaling_mode;
 411
 412         if (mode != DRM_MODE_SCALE_NONE)
 413                 omode = nv_connector->native_mode;
 414         else
 415                 omode = umode;
 416
 417         oX = omode->hdisplay;
 418         oY = omode->vdisplay;
 419         if (omode->flags & DRM_MODE_FLAG_DBLSCAN)
 420                 oY *= 2;
 421
 422         /* add overscan compensation if necessary, will keep the aspect
 423          * ratio the same as the backend mode unless overridden by the
 424          * user setting both hborder and vborder properties.
 425          */
 426         if (nv_connector && ( nv_connector->underscan == UNDERSCAN_ON ||
 427                              (nv_connector->underscan == UNDERSCAN_AUTO &&
 428                               nv_connector->edid &&
 429                               drm_detect_hdmi_monitor(nv_connector->edid)))) {
 430                 u32 bX = nv_connector->underscan_hborder;
 431                 u32 bY = nv_connector->underscan_vborder;
 432                 u32 aspect = (oY << 19) / oX;
 433
 434                 if (bX) {
 435                         oX -= (bX * 2);
 436                         if (bY) oY -= (bY * 2);
 437                         else    oY  = ((oX * aspect) + (aspect / 2)) >> 19;
 438                 } else {
 439                         oX -= (oX >> 4) + 32;
 440                         if (bY) oY -= (bY * 2);
 441                         else    oY  = ((oX * aspect) + (aspect / 2)) >> 19;
 442                 }
 443         }
 444
 445         /* handle CENTER/ASPECT scaling, taking into account the areas
 446          * removed already for overscan compensation
 447          */
 448         switch (mode) {
 449         case DRM_MODE_SCALE_CENTER:
 450                 oX = min((u32)umode->hdisplay, oX);
 451                 oY = min((u32)umode->vdisplay, oY);
 452                 /* fall-through */
 453         case DRM_MODE_SCALE_ASPECT:
 454                 if (oY < oX) {
 455                         u32 aspect = (umode->hdisplay << 19) / umode->vdisplay;
 456                         oX = ((oY * aspect) + (aspect / 2)) >> 19;
 457                 } else {
 458                         u32 aspect = (umode->vdisplay << 19) / umode->hdisplay;
 459                         oY = ((oX * aspect) + (aspect / 2)) >> 19;
 460                 }
 461                 break;
 462         default:
 463                 break;
 464         }
 465
 466         push = evo_wait(dev, EVO_MASTER, 8);
 467         if (push) {
 468                 evo_mthd(push, 0x04c0 + (nv_crtc->index * 0x300), 3);
 469                 evo_data(push, (oY << 16) | oX);
 470                 evo_data(push, (oY << 16) | oX);
 471                 evo_data(push, (oY << 16) | oX);
 472                 evo_mthd(push, 0x0494 + (nv_crtc->index * 0x300), 1);
 473                 evo_data(push, 0x00000000);
 474                 evo_mthd(push, 0x04b8 + (nv_crtc->index * 0x300), 1);
 475                 evo_data(push, (umode->vdisplay << 16) | umode->hdisplay);
 476                 evo_kick(push, dev, EVO_MASTER);
 477                 if (update) {
 478                         nvd0_display_flip_stop(crtc);
 479                         nvd0_display_flip_next(crtc, crtc->fb, NULL, 1);
 480                 }
 481         }
 482
 483         return 0;
 484 }
 485
 486 static int
 487 nvd0_crtc_set_image(struct nouveau_crtc *nv_crtc, struct drm_framebuffer *fb,
 488                     int x, int y, bool update)
 489 {
 490         struct nouveau_framebuffer *nvfb = nouveau_framebuffer(fb);
 491         u32 *push;
 492
 493         push = evo_wait(fb->dev, EVO_MASTER, 16);
 494         if (push) {
 495                 evo_mthd(push, 0x0460 + (nv_crtc->index * 0x300), 1);
 496                 evo_data(push, nvfb->nvbo->bo.offset >> 8);
 497                 evo_mthd(push, 0x0468 + (nv_crtc->index * 0x300), 4);
 498                 evo_data(push, (fb->height << 16) | fb->width);
 499                 evo_data(push, nvfb->r_pitch);
 500                 evo_data(push, nvfb->r_format);
 501                 evo_data(push, nvfb->r_dma);
 502                 evo_mthd(push, 0x04b0 + (nv_crtc->index * 0x300), 1);
 503                 evo_data(push, (y << 16) | x);
 504                 if (update) {
 505                         evo_mthd(push, 0x0080, 1);
 506                         evo_data(push, 0x00000000);
 507                 }
 508                 evo_kick(push, fb->dev, EVO_MASTER);
 509         }
 510
 511         nv_crtc->fb.tile_flags = nvfb->r_dma;
 512         return 0;
 513 }
 514
 515 static void
 516 nvd0_crtc_cursor_show(struct nouveau_crtc *nv_crtc, bool show, bool update)
 517 {
 518         struct drm_device *dev = nv_crtc->base.dev;
 519         u32 *push = evo_wait(dev, EVO_MASTER, 16);
 520         if (push) {
 521                 if (show) {
 522                         evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 2);
 523                         evo_data(push, 0x85000000);
 524                         evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8);
 525                         evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1);
 526                         evo_data(push, NvEvoVRAM);
 527                 } else {
 528                         evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 1);
 529                         evo_data(push, 0x05000000);
 530                         evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1);
 531                         evo_data(push, 0x00000000);
 532                 }
 533
 534                 if (update) {
 535                         evo_mthd(push, 0x0080, 1);
 536                         evo_data(push, 0x00000000);
 537                 }
 538
 539                 evo_kick(push, dev, EVO_MASTER);
 540         }
 541 }
 542
 543 static void
 544 nvd0_crtc_dpms(struct drm_crtc *crtc, int mode)
 545 {
 546 }
 547
 548 static void
 549 nvd0_crtc_prepare(struct drm_crtc *crtc)
 550 {
 551         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 552         u32 *push;
 553
 554         nvd0_display_flip_stop(crtc);
 555
 556         push = evo_wait(crtc->dev, EVO_MASTER, 2);
 557         if (push) {
 558                 evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1);
 559                 evo_data(push, 0x00000000);
 560                 evo_mthd(push, 0x0440 + (nv_crtc->index * 0x300), 1);
 561                 evo_data(push, 0x03000000);
 562                 evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1);
 563                 evo_data(push, 0x00000000);
 564                 evo_kick(push, crtc->dev, EVO_MASTER);
 565         }
 566
 567         nvd0_crtc_cursor_show(nv_crtc, false, false);
 568 }
 569
 570 static void
 571 nvd0_crtc_commit(struct drm_crtc *crtc)
 572 {
 573         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 574         u32 *push;
 575
 576         push = evo_wait(crtc->dev, EVO_MASTER, 32);
 577         if (push) {
 578                 evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1);
 579                 evo_data(push, nv_crtc->fb.tile_flags);
 580                 evo_mthd(push, 0x0440 + (nv_crtc->index * 0x300), 4);
 581                 evo_data(push, 0x83000000);
 582                 evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8);
 583                 evo_data(push, 0x00000000);
 584                 evo_data(push, 0x00000000);
 585                 evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1);
 586                 evo_data(push, NvEvoVRAM);
 587                 evo_mthd(push, 0x0430 + (nv_crtc->index * 0x300), 1);
 588                 evo_data(push, 0xffffff00);
 589                 evo_kick(push, crtc->dev, EVO_MASTER);
 590         }
 591
 592         nvd0_crtc_cursor_show(nv_crtc, nv_crtc->cursor.visible, true);
 593         nvd0_display_flip_next(crtc, crtc->fb, NULL, 1);
 594 }
 595
 596 static bool
 597 nvd0_crtc_mode_fixup(struct drm_crtc *crtc, const struct drm_display_mode *mode,
 598                      struct drm_display_mode *adjusted_mode)
 599 {
 600         return true;
 601 }
 602
 603 static int
 604 nvd0_crtc_swap_fbs(struct drm_crtc *crtc, struct drm_framebuffer *old_fb)
 605 {
 606         struct nouveau_framebuffer *nvfb = nouveau_framebuffer(crtc->fb);
 607         int ret;
 608
 609         ret = nouveau_bo_pin(nvfb->nvbo, TTM_PL_FLAG_VRAM);
 610         if (ret)
 611                 return ret;
 612
 613         if (old_fb) {
 614                 nvfb = nouveau_framebuffer(old_fb);
 615                 nouveau_bo_unpin(nvfb->nvbo);
 616         }
 617
 618         return 0;
 619 }
 620
 621 static int
 622 nvd0_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *umode,
 623                    struct drm_display_mode *mode, int x, int y,
 624                    struct drm_framebuffer *old_fb)
 625 {
 626         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 627         struct nouveau_connector *nv_connector;
 628         u32 ilace = (mode->flags & DRM_MODE_FLAG_INTERLACE) ? 2 : 1;
 629         u32 vscan = (mode->flags & DRM_MODE_FLAG_DBLSCAN) ? 2 : 1;
 630         u32 hactive, hsynce, hbackp, hfrontp, hblanke, hblanks;
 631         u32 vactive, vsynce, vbackp, vfrontp, vblanke, vblanks;
 632         u32 vblan2e = 0, vblan2s = 1;
 633         u32 *push;
 634         int ret;
 635
 636         hactive = mode->htotal;
 637         hsynce  = mode->hsync_end - mode->hsync_start - 1;
 638         hbackp  = mode->htotal - mode->hsync_end;
 639         hblanke = hsynce + hbackp;
 640         hfrontp = mode->hsync_start - mode->hdisplay;
 641         hblanks = mode->htotal - hfrontp - 1;
 642
 643         vactive = mode->vtotal * vscan / ilace;
 644         vsynce  = ((mode->vsync_end - mode->vsync_start) * vscan / ilace) - 1;
 645         vbackp  = (mode->vtotal - mode->vsync_end) * vscan / ilace;
 646         vblanke = vsynce + vbackp;
 647         vfrontp = (mode->vsync_start - mode->vdisplay) * vscan / ilace;
 648         vblanks = vactive - vfrontp - 1;
 649         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
 650                 vblan2e = vactive + vsynce + vbackp;
 651                 vblan2s = vblan2e + (mode->vdisplay * vscan / ilace);
 652                 vactive = (vactive * 2) + 1;
 653         }
 654
 655         ret = nvd0_crtc_swap_fbs(crtc, old_fb);
 656         if (ret)
 657                 return ret;
 658
 659         push = evo_wait(crtc->dev, EVO_MASTER, 64);
 660         if (push) {
 661                 evo_mthd(push, 0x0410 + (nv_crtc->index * 0x300), 6);
 662                 evo_data(push, 0x00000000);
 663                 evo_data(push, (vactive << 16) | hactive);
 664                 evo_data(push, ( vsynce << 16) | hsynce);
 665                 evo_data(push, (vblanke << 16) | hblanke);
 666                 evo_data(push, (vblanks << 16) | hblanks);
 667                 evo_data(push, (vblan2e << 16) | vblan2s);
 668                 evo_mthd(push, 0x042c + (nv_crtc->index * 0x300), 1);
 669                 evo_data(push, 0x00000000); /* ??? */
 670                 evo_mthd(push, 0x0450 + (nv_crtc->index * 0x300), 3);
 671                 evo_data(push, mode->clock * 1000);
 672                 evo_data(push, 0x00200000); /* ??? */
 673                 evo_data(push, mode->clock * 1000);
 674                 evo_mthd(push, 0x04d0 + (nv_crtc->index * 0x300), 2);
 675                 evo_data(push, 0x00000311);
 676                 evo_data(push, 0x00000100);
 677                 evo_kick(push, crtc->dev, EVO_MASTER);
 678         }
 679
 680         nv_connector = nouveau_crtc_connector_get(nv_crtc);
 681         nvd0_crtc_set_dither(nv_crtc, false);
 682         nvd0_crtc_set_scale(nv_crtc, false);
 683         nvd0_crtc_set_image(nv_crtc, crtc->fb, x, y, false);
 684         return 0;
 685 }
 686
 687 static int
 688 nvd0_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
 689                         struct drm_framebuffer *old_fb)
 690 {
 691         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 692         int ret;
 693
 694         if (!crtc->fb) {
 695                 NV_DEBUG_KMS(crtc->dev, "No FB bound\n");
 696                 return 0;
 697         }
 698
 699         ret = nvd0_crtc_swap_fbs(crtc, old_fb);
 700         if (ret)
 701                 return ret;
 702
 703         nvd0_display_flip_stop(crtc);
 704         nvd0_crtc_set_image(nv_crtc, crtc->fb, x, y, true);
 705         nvd0_display_flip_next(crtc, crtc->fb, NULL, 1);
 706         return 0;
 707 }
 708
 709 static int
 710 nvd0_crtc_mode_set_base_atomic(struct drm_crtc *crtc,
 711                                struct drm_framebuffer *fb, int x, int y,
 712                                enum mode_set_atomic state)
 713 {
 714         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 715         nvd0_display_flip_stop(crtc);
 716         nvd0_crtc_set_image(nv_crtc, fb, x, y, true);
 717         return 0;
 718 }
 719
 720 static void
 721 nvd0_crtc_lut_load(struct drm_crtc *crtc)
 722 {
 723         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 724         void __iomem *lut = nvbo_kmap_obj_iovirtual(nv_crtc->lut.nvbo);
 725         int i;
 726
 727         for (i = 0; i < 256; i++) {
 728                 writew(0x6000 + (nv_crtc->lut.r[i] >> 2), lut + (i * 0x20) + 0);
 729                 writew(0x6000 + (nv_crtc->lut.g[i] >> 2), lut + (i * 0x20) + 2);
 730                 writew(0x6000 + (nv_crtc->lut.b[i] >> 2), lut + (i * 0x20) + 4);
 731         }
 732 }
 733
 734 static int
 735 nvd0_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
 736                      uint32_t handle, uint32_t width, uint32_t height)
 737 {
 738         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 739         struct drm_device *dev = crtc->dev;
 740         struct drm_gem_object *gem;
 741         struct nouveau_bo *nvbo;
 742         bool visible = (handle != 0);
 743         int i, ret = 0;
 744
 745         if (visible) {
 746                 if (width != 64 || height != 64)
 747                         return -EINVAL;
 748
 749                 gem = drm_gem_object_lookup(dev, file_priv, handle);
 750                 if (unlikely(!gem))
 751                         return -ENOENT;
 752                 nvbo = nouveau_gem_object(gem);
 753
 754                 ret = nouveau_bo_map(nvbo);
 755                 if (ret == 0) {
 756                         for (i = 0; i < 64 * 64; i++) {
 757                                 u32 v = nouveau_bo_rd32(nvbo, i);
 758                                 nouveau_bo_wr32(nv_crtc->cursor.nvbo, i, v);
 759                         }
 760                         nouveau_bo_unmap(nvbo);
 761                 }
 762
 763                 drm_gem_object_unreference_unlocked(gem);
 764         }
 765
 766         if (visible != nv_crtc->cursor.visible) {
 767                 nvd0_crtc_cursor_show(nv_crtc, visible, true);
 768                 nv_crtc->cursor.visible = visible;
 769         }
 770
 771         return ret;
 772 }
 773
 774 static int
 775 nvd0_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
 776 {
 777         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 778         int ch = EVO_CURS(nv_crtc->index);
 779
 780         evo_piow(crtc->dev, ch, 0x0084, (y << 16) | (x & 0xffff));
 781         evo_piow(crtc->dev, ch, 0x0080, 0x00000000);
 782         return 0;
 783 }
 784
 785 static void
 786 nvd0_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
 787                     uint32_t start, uint32_t size)
 788 {
 789         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 790         u32 end = max(start + size, (u32)256);
 791         u32 i;
 792
 793         for (i = start; i < end; i++) {
 794                 nv_crtc->lut.r[i] = r[i];
 795                 nv_crtc->lut.g[i] = g[i];
 796                 nv_crtc->lut.b[i] = b[i];
 797         }
 798
 799         nvd0_crtc_lut_load(crtc);
 800 }
 801
 802 static void
 803 nvd0_crtc_destroy(struct drm_crtc *crtc)
 804 {
 805         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 806         nouveau_bo_unmap(nv_crtc->cursor.nvbo);
 807         nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo);
 808         nouveau_bo_unmap(nv_crtc->lut.nvbo);
 809         nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo);
 810         drm_crtc_cleanup(crtc);
 811         kfree(crtc);
 812 }
 813
 814 static const struct drm_crtc_helper_funcs nvd0_crtc_hfunc = {
 815         .dpms = nvd0_crtc_dpms,
 816         .prepare = nvd0_crtc_prepare,
 817         .commit = nvd0_crtc_commit,
 818         .mode_fixup = nvd0_crtc_mode_fixup,
 819         .mode_set = nvd0_crtc_mode_set,
 820         .mode_set_base = nvd0_crtc_mode_set_base,
 821         .mode_set_base_atomic = nvd0_crtc_mode_set_base_atomic,
 822         .load_lut = nvd0_crtc_lut_load,
 823 };
 824
 825 static const struct drm_crtc_funcs nvd0_crtc_func = {
 826         .cursor_set = nvd0_crtc_cursor_set,
 827         .cursor_move = nvd0_crtc_cursor_move,
 828         .gamma_set = nvd0_crtc_gamma_set,
 829         .set_config = drm_crtc_helper_set_config,
 830         .destroy = nvd0_crtc_destroy,
 831         .page_flip = nouveau_crtc_page_flip,
 832 };
 833
 834 static void
 835 nvd0_cursor_set_pos(struct nouveau_crtc *nv_crtc, int x, int y)
 836 {
 837 }
 838
 839 static void
 840 nvd0_cursor_set_offset(struct nouveau_crtc *nv_crtc, uint32_t offset)
 841 {
 842 }
 843
 844 static int
 845 nvd0_crtc_create(struct drm_device *dev, int index)
 846 {
 847         struct nouveau_crtc *nv_crtc;
 848         struct drm_crtc *crtc;
 849         int ret, i;
 850
 851         nv_crtc = kzalloc(sizeof(*nv_crtc), GFP_KERNEL);
 852         if (!nv_crtc)
 853                 return -ENOMEM;
 854
 855         nv_crtc->index = index;
 856         nv_crtc->set_dither = nvd0_crtc_set_dither;
 857         nv_crtc->set_scale = nvd0_crtc_set_scale;
 858         nv_crtc->cursor.set_offset = nvd0_cursor_set_offset;
 859         nv_crtc->cursor.set_pos = nvd0_cursor_set_pos;
 860         for (i = 0; i < 256; i++) {
 861                 nv_crtc->lut.r[i] = i << 8;
 862                 nv_crtc->lut.g[i] = i << 8;
 863                 nv_crtc->lut.b[i] = i << 8;
 864         }
 865
 866         crtc = &nv_crtc->base;
 867         drm_crtc_init(dev, crtc, &nvd0_crtc_func);
 868         drm_crtc_helper_add(crtc, &nvd0_crtc_hfunc);
 869         drm_mode_crtc_set_gamma_size(crtc, 256);
 870
 871         ret = nouveau_bo_new(dev, 64 * 64 * 4, 0x100, TTM_PL_FLAG_VRAM,
 872                              0, 0x0000, NULL, &nv_crtc->cursor.nvbo);
 873         if (!ret) {
 874                 ret = nouveau_bo_pin(nv_crtc->cursor.nvbo, TTM_PL_FLAG_VRAM);
 875                 if (!ret)
 876                         ret = nouveau_bo_map(nv_crtc->cursor.nvbo);
 877                 if (ret)
 878                         nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo);
 879         }
 880
 881         if (ret)
 882                 goto out;
 883
 884         ret = nouveau_bo_new(dev, 8192, 0x100, TTM_PL_FLAG_VRAM,
 885                              0, 0x0000, NULL, &nv_crtc->lut.nvbo);
 886         if (!ret) {
 887                 ret = nouveau_bo_pin(nv_crtc->lut.nvbo, TTM_PL_FLAG_VRAM);
 888                 if (!ret)
 889                         ret = nouveau_bo_map(nv_crtc->lut.nvbo);
 890                 if (ret)
 891                         nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo);
 892         }
 893
 894         if (ret)
 895                 goto out;
 896
 897         nvd0_crtc_lut_load(crtc);
 898
 899 out:
 900         if (ret)
 901                 nvd0_crtc_destroy(crtc);
 902         return ret;
 903 }
 904
 905 /******************************************************************************
 906  * DAC
 907  *****************************************************************************/
 908 static void
 909 nvd0_dac_dpms(struct drm_encoder *encoder, int mode)
 910 {
 911         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 912         struct drm_device *dev = encoder->dev;
 913         int or = nv_encoder->or;
 914         u32 dpms_ctrl;
 915
 916         dpms_ctrl = 0x80000000;
 917         if (mode == DRM_MODE_DPMS_STANDBY || mode == DRM_MODE_DPMS_OFF)
 918                 dpms_ctrl |= 0x00000001;
 919         if (mode == DRM_MODE_DPMS_SUSPEND || mode == DRM_MODE_DPMS_OFF)
 920                 dpms_ctrl |= 0x00000004;
 921
 922         nv_wait(dev, 0x61a004 + (or * 0x0800), 0x80000000, 0x00000000);
 923         nv_mask(dev, 0x61a004 + (or * 0x0800), 0xc000007f, dpms_ctrl);
 924         nv_wait(dev, 0x61a004 + (or * 0x0800), 0x80000000, 0x00000000);
 925 }
 926
 927 static bool
 928 nvd0_dac_mode_fixup(struct drm_encoder *encoder,
 929                     const struct drm_display_mode *mode,
 930                     struct drm_display_mode *adjusted_mode)
 931 {
 932         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 933         struct nouveau_connector *nv_connector;
 934
 935         nv_connector = nouveau_encoder_connector_get(nv_encoder);
 936         if (nv_connector && nv_connector->native_mode) {
 937                 if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) {
 938                         int id = adjusted_mode->base.id;
 939                         *adjusted_mode = *nv_connector->native_mode;
 940                         adjusted_mode->base.id = id;
 941                 }
 942         }
 943
 944         return true;
 945 }
 946
 947 static void
 948 nvd0_dac_commit(struct drm_encoder *encoder)
 949 {
 950 }
 951
 952 static void
 953 nvd0_dac_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
 954                   struct drm_display_mode *adjusted_mode)
 955 {
 956         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 957         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
 958         u32 syncs, magic, *push;
 959
 960         syncs = 0x00000001;
 961         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 962                 syncs |= 0x00000008;
 963         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 964                 syncs |= 0x00000010;
 965
 966         magic = 0x31ec6000 | (nv_crtc->index << 25);
 967         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 968                 magic |= 0x00000001;
 969
 970         nvd0_dac_dpms(encoder, DRM_MODE_DPMS_ON);
 971
 972         push = evo_wait(encoder->dev, EVO_MASTER, 8);
 973         if (push) {
 974                 evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2);
 975                 evo_data(push, syncs);
 976                 evo_data(push, magic);
 977                 evo_mthd(push, 0x0180 + (nv_encoder->or * 0x020), 2);
 978                 evo_data(push, 1 << nv_crtc->index);
 979                 evo_data(push, 0x00ff);
 980                 evo_kick(push, encoder->dev, EVO_MASTER);
 981         }
 982
 983         nv_encoder->crtc = encoder->crtc;
 984 }
 985
 986 static void
 987 nvd0_dac_disconnect(struct drm_encoder *encoder)
 988 {
 989         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 990         struct drm_device *dev = encoder->dev;
 991         u32 *push;
 992
 993         if (nv_encoder->crtc) {
 994                 nvd0_crtc_prepare(nv_encoder->crtc);
 995
 996                 push = evo_wait(dev, EVO_MASTER, 4);
 997                 if (push) {
 998                         evo_mthd(push, 0x0180 + (nv_encoder->or * 0x20), 1);
 999                         evo_data(push, 0x00000000);
1000                         evo_mthd(push, 0x0080, 1);
1001                         evo_data(push, 0x00000000);
1002                         evo_kick(push, dev, EVO_MASTER);
1003                 }
1004
1005                 nv_encoder->crtc = NULL;
1006         }
1007 }
1008
1009 static enum drm_connector_status
1010 nvd0_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1011 {
1012         enum drm_connector_status status = connector_status_disconnected;
1013         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1014         struct drm_device *dev = encoder->dev;
1015         int or = nv_encoder->or;
1016         u32 load;
1017
1018         nv_wr32(dev, 0x61a00c + (or * 0x800), 0x00100000);
1019         udelay(9500);
1020         nv_wr32(dev, 0x61a00c + (or * 0x800), 0x80000000);
1021
1022         load = nv_rd32(dev, 0x61a00c + (or * 0x800));
1023         if ((load & 0x38000000) == 0x38000000)
1024                 status = connector_status_connected;
1025
1026         nv_wr32(dev, 0x61a00c + (or * 0x800), 0x00000000);
1027         return status;
1028 }
1029
1030 static void
1031 nvd0_dac_destroy(struct drm_encoder *encoder)
1032 {
1033         drm_encoder_cleanup(encoder);
1034         kfree(encoder);
1035 }
1036
1037 static const struct drm_encoder_helper_funcs nvd0_dac_hfunc = {
1038         .dpms = nvd0_dac_dpms,
1039         .mode_fixup = nvd0_dac_mode_fixup,
1040         .prepare = nvd0_dac_disconnect,
1041         .commit = nvd0_dac_commit,
1042         .mode_set = nvd0_dac_mode_set,
1043         .disable = nvd0_dac_disconnect,
1044         .get_crtc = nvd0_display_crtc_get,
1045         .detect = nvd0_dac_detect
1046 };
1047
1048 static const struct drm_encoder_funcs nvd0_dac_func = {
1049         .destroy = nvd0_dac_destroy,
1050 };
1051
1052 static int
1053 nvd0_dac_create(struct drm_connector *connector, struct dcb_output *dcbe)
1054 {
1055         struct drm_device *dev = connector->dev;
1056         struct nouveau_encoder *nv_encoder;
1057         struct drm_encoder *encoder;
1058
1059         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1060         if (!nv_encoder)
1061                 return -ENOMEM;
1062         nv_encoder->dcb = dcbe;
1063         nv_encoder->or = ffs(dcbe->or) - 1;
1064
1065         encoder = to_drm_encoder(nv_encoder);
1066         encoder->possible_crtcs = dcbe->heads;
1067         encoder->possible_clones = 0;
1068         drm_encoder_init(dev, encoder, &nvd0_dac_func, DRM_MODE_ENCODER_DAC);
1069         drm_encoder_helper_add(encoder, &nvd0_dac_hfunc);
1070
1071         drm_mode_connector_attach_encoder(connector, encoder);
1072         return 0;
1073 }
1074
1075 /******************************************************************************
1076  * Audio
1077  *****************************************************************************/
1078 static void
1079 nvd0_audio_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode)
1080 {
1081         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1082         struct nouveau_connector *nv_connector;
1083         struct drm_device *dev = encoder->dev;
1084         int i, or = nv_encoder->or * 0x30;
1085
1086         nv_connector = nouveau_encoder_connector_get(nv_encoder);
1087         if (!drm_detect_monitor_audio(nv_connector->edid))
1088                 return;
1089
1090         nv_mask(dev, 0x10ec10 + or, 0x80000003, 0x80000001);
1091
1092         drm_edid_to_eld(&nv_connector->base, nv_connector->edid);
1093         if (nv_connector->base.eld[0]) {
1094                 u8 *eld = nv_connector->base.eld;
1095
1096                 for (i = 0; i < eld[2] * 4; i++)
1097                         nv_wr32(dev, 0x10ec00 + or, (i << 8) | eld[i]);
1098                 for (i = eld[2] * 4; i < 0x60; i++)
1099                         nv_wr32(dev, 0x10ec00 + or, (i << 8) | 0x00);
1100
1101                 nv_mask(dev, 0x10ec10 + or, 0x80000002, 0x80000002);
1102         }
1103 }
1104
1105 static void
1106 nvd0_audio_disconnect(struct drm_encoder *encoder)
1107 {
1108         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1109         struct drm_device *dev = encoder->dev;
1110         int or = nv_encoder->or * 0x30;
1111
1112         nv_mask(dev, 0x10ec10 + or, 0x80000003, 0x80000000);
1113 }
1114
1115 /******************************************************************************
1116  * HDMI
1117  *****************************************************************************/
1118 static void
1119 nvd0_hdmi_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode)
1120 {
1121         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1122         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1123         struct nouveau_connector *nv_connector;
1124         struct drm_device *dev = encoder->dev;
1125         int head = nv_crtc->index * 0x800;
1126         u32 rekey = 56; /* binary driver, and tegra constant */
1127         u32 max_ac_packet;
1128
1129         nv_connector = nouveau_encoder_connector_get(nv_encoder);
1130         if (!drm_detect_hdmi_monitor(nv_connector->edid))
1131                 return;
1132
1133         max_ac_packet  = mode->htotal - mode->hdisplay;
1134         max_ac_packet -= rekey;
1135         max_ac_packet -= 18; /* constant from tegra */
1136         max_ac_packet /= 32;
1137
1138         /* AVI InfoFrame */
1139         nv_mask(dev, 0x616714 + head, 0x00000001, 0x00000000);
1140         nv_wr32(dev, 0x61671c + head, 0x000d0282);
1141         nv_wr32(dev, 0x616720 + head, 0x0000006f);
1142         nv_wr32(dev, 0x616724 + head, 0x00000000);
1143         nv_wr32(dev, 0x616728 + head, 0x00000000);
1144         nv_wr32(dev, 0x61672c + head, 0x00000000);
1145         nv_mask(dev, 0x616714 + head, 0x00000001, 0x00000001);
1146
1147         /* ??? InfoFrame? */
1148         nv_mask(dev, 0x6167a4 + head, 0x00000001, 0x00000000);
1149         nv_wr32(dev, 0x6167ac + head, 0x00000010);
1150         nv_mask(dev, 0x6167a4 + head, 0x00000001, 0x00000001);
1151
1152         /* HDMI_CTRL */
1153         nv_mask(dev, 0x616798 + head, 0x401f007f, 0x40000000 | rekey |
1154                                                   max_ac_packet << 16);
1155
1156         /* NFI, audio doesn't work without it though.. */
1157         nv_mask(dev, 0x616548 + head, 0x00000070, 0x00000000);
1158
1159         nvd0_audio_mode_set(encoder, mode);
1160 }
1161
1162 static void
1163 nvd0_hdmi_disconnect(struct drm_encoder *encoder)
1164 {
1165         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1166         struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc);
1167         struct drm_device *dev = encoder->dev;
1168         int head = nv_crtc->index * 0x800;
1169
1170         nvd0_audio_disconnect(encoder);
1171
1172         nv_mask(dev, 0x616798 + head, 0x40000000, 0x00000000);
1173         nv_mask(dev, 0x6167a4 + head, 0x00000001, 0x00000000);
1174         nv_mask(dev, 0x616714 + head, 0x00000001, 0x00000000);
1175 }
1176
1177 /******************************************************************************
1178  * SOR
1179  *****************************************************************************/
1180 static inline u32
1181 nvd0_sor_dp_lane_map(struct drm_device *dev, struct dcb_output *dcb, u8 lane)
1182 {
1183         static const u8 nvd0[] = { 16, 8, 0, 24 };
1184         return nvd0[lane];
1185 }
1186
1187 static void
1188 nvd0_sor_dp_train_set(struct drm_device *dev, struct dcb_output *dcb, u8 pattern)
1189 {
1190         const u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1);
1191         const u32 loff = (or * 0x800) + (link * 0x80);
1192         nv_mask(dev, 0x61c110 + loff, 0x0f0f0f0f, 0x01010101 * pattern);
1193 }
1194
1195 static void
1196 nvd0_sor_dp_train_adj(struct drm_device *dev, struct dcb_output *dcb,
1197                       u8 lane, u8 swing, u8 preem)
1198 {
1199         const u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1);
1200         const u32 loff = (or * 0x800) + (link * 0x80);
1201         u32 shift = nvd0_sor_dp_lane_map(dev, dcb, lane);
1202         u32 mask = 0x000000ff << shift;
1203         u8 *table, *entry, *config = NULL;
1204
1205         switch (swing) {
1206         case 0: preem += 0; break;
1207         case 1: preem += 4; break;
1208         case 2: preem += 7; break;
1209         case 3: preem += 9; break;
1210         }
1211
1212         table = nouveau_dp_bios_data(dev, dcb, &entry);
1213         if (table) {
1214                 if (table[0] == 0x30) {
1215                         config  = entry + table[4];
1216                         config += table[5] * preem;
1217                 } else
1218                 if (table[0] == 0x40) {
1219                         config  = table + table[1];
1220                         config += table[2] * table[3];
1221                         config += table[6] * preem;
1222                 }
1223         }
1224
1225         if (!config) {
1226                 NV_ERROR(dev, "PDISP: unsupported DP table for chipset\n");
1227                 return;
1228         }
1229
1230         nv_mask(dev, 0x61c118 + loff, mask, config[1] << shift);
1231         nv_mask(dev, 0x61c120 + loff, mask, config[2] << shift);
1232         nv_mask(dev, 0x61c130 + loff, 0x0000ff00, config[3] << 8);
1233         nv_mask(dev, 0x61c13c + loff, 0x00000000, 0x00000000);
1234 }
1235
1236 static void
1237 nvd0_sor_dp_link_set(struct drm_device *dev, struct dcb_output *dcb, int crtc,
1238                      int link_nr, u32 link_bw, bool enhframe)
1239 {
1240         const u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1);
1241         const u32 loff = (or * 0x800) + (link * 0x80);
1242         const u32 soff = (or * 0x800);
1243         u32 dpctrl = nv_rd32(dev, 0x61c10c + loff) & ~0x001f4000;
1244         u32 clksor = nv_rd32(dev, 0x612300 + soff) & ~0x007c0000;
1245         u32 script = 0x0000, lane_mask = 0;
1246         u8 *table, *entry;
1247         int i;
1248
1249         link_bw /= 27000;
1250
1251         table = nouveau_dp_bios_data(dev, dcb, &entry);
1252         if (table) {
1253                 if      (table[0] == 0x30) entry = ROMPTR(dev, entry[10]);
1254                 else if (table[0] == 0x40) entry = ROMPTR(dev, entry[9]);
1255                 else                       entry = NULL;
1256
1257                 while (entry) {
1258                         if (entry[0] >= link_bw)
1259                                 break;
1260                         entry += 3;
1261                 }
1262
1263                 nouveau_bios_run_init_table(dev, script, dcb, crtc);
1264         }
1265
1266         clksor |= link_bw << 18;
1267         dpctrl |= ((1 << link_nr) - 1) << 16;
1268         if (enhframe)
1269                 dpctrl |= 0x00004000;
1270
1271         for (i = 0; i < link_nr; i++)
1272                 lane_mask |= 1 << (nvd0_sor_dp_lane_map(dev, dcb, i) >> 3);
1273
1274         nv_wr32(dev, 0x612300 + soff, clksor);
1275         nv_wr32(dev, 0x61c10c + loff, dpctrl);
1276         nv_mask(dev, 0x61c130 + loff, 0x0000000f, lane_mask);
1277 }
1278
1279 static void
1280 nvd0_sor_dp_link_get(struct drm_device *dev, struct dcb_output *dcb,
1281                      u32 *link_nr, u32 *link_bw)
1282 {
1283         const u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1);
1284         const u32 loff = (or * 0x800) + (link * 0x80);
1285         const u32 soff = (or * 0x800);
1286         u32 dpctrl = nv_rd32(dev, 0x61c10c + loff) & 0x000f0000;
1287         u32 clksor = nv_rd32(dev, 0x612300 + soff);
1288
1289         if      (dpctrl > 0x00030000) *link_nr = 4;
1290         else if (dpctrl > 0x00010000) *link_nr = 2;
1291         else                          *link_nr = 1;
1292
1293         *link_bw  = (clksor & 0x007c0000) >> 18;
1294         *link_bw *= 27000;
1295 }
1296
1297 static void
1298 nvd0_sor_dp_calc_tu(struct drm_device *dev, struct dcb_output *dcb,
1299                     u32 crtc, u32 datarate)
1300 {
1301         const u32 symbol = 100000;
1302         const u32 TU = 64;
1303         u32 link_nr, link_bw;
1304         u64 ratio, value;
1305
1306         nvd0_sor_dp_link_get(dev, dcb, &link_nr, &link_bw);
1307
1308         ratio  = datarate;
1309         ratio *= symbol;
1310         do_div(ratio, link_nr * link_bw);
1311
1312         value  = (symbol - ratio) * TU;
1313         value *= ratio;
1314         do_div(value, symbol);
1315         do_div(value, symbol);
1316
1317         value += 5;
1318         value |= 0x08000000;
1319
1320         nv_wr32(dev, 0x616610 + (crtc * 0x800), value);
1321 }
1322
1323 static void
1324 nvd0_sor_dpms(struct drm_encoder *encoder, int mode)
1325 {
1326         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1327         struct drm_device *dev = encoder->dev;
1328         struct drm_encoder *partner;
1329         int or = nv_encoder->or;
1330         u32 dpms_ctrl;
1331
1332         nv_encoder->last_dpms = mode;
1333
1334         list_for_each_entry(partner, &dev->mode_config.encoder_list, head) {
1335                 struct nouveau_encoder *nv_partner = nouveau_encoder(partner);
1336
1337                 if (partner->encoder_type != DRM_MODE_ENCODER_TMDS)
1338                         continue;
1339
1340                 if (nv_partner != nv_encoder &&
1341                     nv_partner->dcb->or == nv_encoder->dcb->or) {
1342                         if (nv_partner->last_dpms == DRM_MODE_DPMS_ON)
1343                                 return;
1344                         break;
1345                 }
1346         }
1347
1348         dpms_ctrl  = (mode == DRM_MODE_DPMS_ON);
1349         dpms_ctrl |= 0x80000000;
1350
1351         nv_wait(dev, 0x61c004 + (or * 0x0800), 0x80000000, 0x00000000);
1352         nv_mask(dev, 0x61c004 + (or * 0x0800), 0x80000001, dpms_ctrl);
1353         nv_wait(dev, 0x61c004 + (or * 0x0800), 0x80000000, 0x00000000);
1354         nv_wait(dev, 0x61c030 + (or * 0x0800), 0x10000000, 0x00000000);
1355
1356         if (nv_encoder->dcb->type == DCB_OUTPUT_DP) {
1357                 struct dp_train_func func = {
1358                         .link_set = nvd0_sor_dp_link_set,
1359                         .train_set = nvd0_sor_dp_train_set,
1360                         .train_adj = nvd0_sor_dp_train_adj
1361                 };
1362
1363                 nouveau_dp_dpms(encoder, mode, nv_encoder->dp.datarate, &func);
1364         }
1365 }
1366
1367 static bool
1368 nvd0_sor_mode_fixup(struct drm_encoder *encoder,
1369                     const struct drm_display_mode *mode,
1370                     struct drm_display_mode *adjusted_mode)
1371 {
1372         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1373         struct nouveau_connector *nv_connector;
1374
1375         nv_connector = nouveau_encoder_connector_get(nv_encoder);
1376         if (nv_connector && nv_connector->native_mode) {
1377                 if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) {
1378                         int id = adjusted_mode->base.id;
1379                         *adjusted_mode = *nv_connector->native_mode;
1380                         adjusted_mode->base.id = id;
1381                 }
1382         }
1383
1384         return true;
1385 }
1386
1387 static void
1388 nvd0_sor_disconnect(struct drm_encoder *encoder)
1389 {
1390         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1391         struct drm_device *dev = encoder->dev;
1392         u32 *push;
1393
1394         if (nv_encoder->crtc) {
1395                 nvd0_crtc_prepare(nv_encoder->crtc);
1396
1397                 push = evo_wait(dev, EVO_MASTER, 4);
1398                 if (push) {
1399                         evo_mthd(push, 0x0200 + (nv_encoder->or * 0x20), 1);
1400                         evo_data(push, 0x00000000);
1401                         evo_mthd(push, 0x0080, 1);
1402                         evo_data(push, 0x00000000);
1403                         evo_kick(push, dev, EVO_MASTER);
1404                 }
1405
1406                 nvd0_hdmi_disconnect(encoder);
1407
1408                 nv_encoder->crtc = NULL;
1409                 nv_encoder->last_dpms = DRM_MODE_DPMS_OFF;
1410         }
1411 }
1412
1413 static void
1414 nvd0_sor_prepare(struct drm_encoder *encoder)
1415 {
1416         nvd0_sor_disconnect(encoder);
1417         if (nouveau_encoder(encoder)->dcb->type == DCB_OUTPUT_DP)
1418                 evo_sync(encoder->dev, EVO_MASTER);
1419 }
1420
1421 static void
1422 nvd0_sor_commit(struct drm_encoder *encoder)
1423 {
1424 }
1425
1426 static void
1427 nvd0_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *umode,
1428                   struct drm_display_mode *mode)
1429 {
1430         struct drm_device *dev = encoder->dev;
1431         struct drm_nouveau_private *dev_priv = dev->dev_private;
1432         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1433         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1434         struct nouveau_connector *nv_connector;
1435         struct nvbios *bios = &dev_priv->vbios;
1436         u32 mode_ctrl = (1 << nv_crtc->index);
1437         u32 syncs, magic, *push;
1438         u32 or_config;
1439
1440         syncs = 0x00000001;
1441         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1442                 syncs |= 0x00000008;
1443         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1444                 syncs |= 0x00000010;
1445
1446         magic = 0x31ec6000 | (nv_crtc->index << 25);
1447         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1448                 magic |= 0x00000001;
1449
1450         nv_connector = nouveau_encoder_connector_get(nv_encoder);
1451         switch (nv_encoder->dcb->type) {
1452         case DCB_OUTPUT_TMDS:
1453                 if (nv_encoder->dcb->sorconf.link & 1) {
1454                         if (mode->clock < 165000)
1455                                 mode_ctrl |= 0x00000100;
1456                         else
1457                                 mode_ctrl |= 0x00000500;
1458                 } else {
1459                         mode_ctrl |= 0x00000200;
1460                 }
1461
1462                 or_config = (mode_ctrl & 0x00000f00) >> 8;
1463                 if (mode->clock >= 165000)
1464                         or_config |= 0x0100;
1465
1466                 nvd0_hdmi_mode_set(encoder, mode);
1467                 break;
1468         case DCB_OUTPUT_LVDS:
1469                 or_config = (mode_ctrl & 0x00000f00) >> 8;
1470                 if (bios->fp_no_ddc) {
1471                         if (bios->fp.dual_link)
1472                                 or_config |= 0x0100;
1473                         if (bios->fp.if_is_24bit)
1474                                 or_config |= 0x0200;
1475                 } else {
1476                         if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
1477                                 if (((u8 *)nv_connector->edid)[121] == 2)
1478                                         or_config |= 0x0100;
1479                         } else
1480                         if (mode->clock >= bios->fp.duallink_transition_clk) {
1481                                 or_config |= 0x0100;
1482                         }
1483
1484                         if (or_config & 0x0100) {
1485                                 if (bios->fp.strapless_is_24bit & 2)
1486                                         or_config |= 0x0200;
1487                         } else {
1488                                 if (bios->fp.strapless_is_24bit & 1)
1489                                         or_config |= 0x0200;
1490                         }
1491
1492                         if (nv_connector->base.display_info.bpc == 8)
1493                                 or_config |= 0x0200;
1494
1495                 }
1496                 break;
1497         case DCB_OUTPUT_DP:
1498                 if (nv_connector->base.display_info.bpc == 6) {
1499                         nv_encoder->dp.datarate = mode->clock * 18 / 8;
1500                         syncs |= 0x00000002 << 6;
1501                 } else {
1502                         nv_encoder->dp.datarate = mode->clock * 24 / 8;
1503                         syncs |= 0x00000005 << 6;
1504                 }
1505
1506                 if (nv_encoder->dcb->sorconf.link & 1)
1507                         mode_ctrl |= 0x00000800;
1508                 else
1509                         mode_ctrl |= 0x00000900;
1510
1511                 or_config = (mode_ctrl & 0x00000f00) >> 8;
1512                 break;
1513         default:
1514                 BUG_ON(1);
1515                 break;
1516         }
1517
1518         nvd0_sor_dpms(encoder, DRM_MODE_DPMS_ON);
1519
1520         if (nv_encoder->dcb->type == DCB_OUTPUT_DP) {
1521                 nvd0_sor_dp_calc_tu(dev, nv_encoder->dcb, nv_crtc->index,
1522                                          nv_encoder->dp.datarate);
1523         }
1524
1525         push = evo_wait(dev, EVO_MASTER, 8);
1526         if (push) {
1527                 evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2);
1528                 evo_data(push, syncs);
1529                 evo_data(push, magic);
1530                 evo_mthd(push, 0x0200 + (nv_encoder->or * 0x020), 2);
1531                 evo_data(push, mode_ctrl);
1532                 evo_data(push, or_config);
1533                 evo_kick(push, dev, EVO_MASTER);
1534         }
1535
1536         nv_encoder->crtc = encoder->crtc;
1537 }
1538
1539 static void
1540 nvd0_sor_destroy(struct drm_encoder *encoder)
1541 {
1542         drm_encoder_cleanup(encoder);
1543         kfree(encoder);
1544 }
1545
1546 static const struct drm_encoder_helper_funcs nvd0_sor_hfunc = {
1547         .dpms = nvd0_sor_dpms,
1548         .mode_fixup = nvd0_sor_mode_fixup,
1549         .prepare = nvd0_sor_prepare,
1550         .commit = nvd0_sor_commit,
1551         .mode_set = nvd0_sor_mode_set,
1552         .disable = nvd0_sor_disconnect,
1553         .get_crtc = nvd0_display_crtc_get,
1554 };
1555
1556 static const struct drm_encoder_funcs nvd0_sor_func = {
1557         .destroy = nvd0_sor_destroy,
1558 };
1559
1560 static int
1561 nvd0_sor_create(struct drm_connector *connector, struct dcb_output *dcbe)
1562 {
1563         struct drm_device *dev = connector->dev;
1564         struct nouveau_encoder *nv_encoder;
1565         struct drm_encoder *encoder;
1566
1567         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1568         if (!nv_encoder)
1569                 return -ENOMEM;
1570         nv_encoder->dcb = dcbe;
1571         nv_encoder->or = ffs(dcbe->or) - 1;
1572         nv_encoder->last_dpms = DRM_MODE_DPMS_OFF;
1573
1574         encoder = to_drm_encoder(nv_encoder);
1575         encoder->possible_crtcs = dcbe->heads;
1576         encoder->possible_clones = 0;
1577         drm_encoder_init(dev, encoder, &nvd0_sor_func, DRM_MODE_ENCODER_TMDS);
1578         drm_encoder_helper_add(encoder, &nvd0_sor_hfunc);
1579
1580         drm_mode_connector_attach_encoder(connector, encoder);
1581         return 0;
1582 }
1583
1584 /******************************************************************************
1585  * IRQ
1586  *****************************************************************************/
1587 static struct dcb_output *
1588 lookup_dcb(struct drm_device *dev, int id, u32 mc)
1589 {
1590         struct drm_nouveau_private *dev_priv = dev->dev_private;
1591         int type, or, i, link = -1;
1592
1593         if (id < 4) {
1594                 type = DCB_OUTPUT_ANALOG;
1595                 or   = id;
1596         } else {
1597                 switch (mc & 0x00000f00) {
1598                 case 0x00000000: link = 0; type = DCB_OUTPUT_LVDS; break;
1599                 case 0x00000100: link = 0; type = DCB_OUTPUT_TMDS; break;
1600                 case 0x00000200: link = 1; type = DCB_OUTPUT_TMDS; break;
1601                 case 0x00000500: link = 0; type = DCB_OUTPUT_TMDS; break;
1602                 case 0x00000800: link = 0; type = DCB_OUTPUT_DP; break;
1603                 case 0x00000900: link = 1; type = DCB_OUTPUT_DP; break;
1604                 default:
1605                         NV_ERROR(dev, "PDISP: unknown SOR mc 0x%08x\n", mc);
1606                         return NULL;
1607                 }
1608
1609                 or = id - 4;
1610         }
1611
1612         for (i = 0; i < dev_priv->vbios.dcb.entries; i++) {
1613                 struct dcb_output *dcb = &dev_priv->vbios.dcb.entry[i];
1614                 if (dcb->type == type && (dcb->or & (1 << or)) &&
1615                     (link < 0 || link == !(dcb->sorconf.link & 1)))
1616                         return dcb;
1617         }
1618
1619         NV_ERROR(dev, "PDISP: DCB for %d/0x%08x not found\n", id, mc);
1620         return NULL;
1621 }
1622
1623 static void
1624 nvd0_display_unk1_handler(struct drm_device *dev, u32 crtc, u32 mask)
1625 {
1626         struct dcb_output *dcb;
1627         int i;
1628
1629         for (i = 0; mask && i < 8; i++) {
1630                 u32 mcc = nv_rd32(dev, 0x640180 + (i * 0x20));
1631                 if (!(mcc & (1 << crtc)))
1632                         continue;
1633
1634                 dcb = lookup_dcb(dev, i, mcc);
1635                 if (!dcb)
1636                         continue;
1637
1638                 nouveau_bios_run_display_table(dev, 0x0000, -1, dcb, crtc);
1639         }
1640
1641         nv_wr32(dev, 0x6101d4, 0x00000000);
1642         nv_wr32(dev, 0x6109d4, 0x00000000);
1643         nv_wr32(dev, 0x6101d0, 0x80000000);
1644 }
1645
1646 static void
1647 nvd0_display_unk2_handler(struct drm_device *dev, u32 crtc, u32 mask)
1648 {
1649         struct dcb_output *dcb;
1650         u32 or, tmp, pclk;
1651         int i;
1652
1653         for (i = 0; mask && i < 8; i++) {
1654                 u32 mcc = nv_rd32(dev, 0x640180 + (i * 0x20));
1655                 if (!(mcc & (1 << crtc)))
1656                         continue;
1657
1658                 dcb = lookup_dcb(dev, i, mcc);
1659                 if (!dcb)
1660                         continue;
1661
1662                 nouveau_bios_run_display_table(dev, 0x0000, -2, dcb, crtc);
1663         }
1664
1665         pclk = nv_rd32(dev, 0x660450 + (crtc * 0x300)) / 1000;
1666         NV_DEBUG_KMS(dev, "PDISP: crtc %d pclk %d mask 0x%08x\n",
1667                           crtc, pclk, mask);
1668         if (pclk && (mask & 0x00010000)) {
1669                 nv50_crtc_set_clock(dev, crtc, pclk);
1670         }
1671
1672         for (i = 0; mask && i < 8; i++) {
1673                 u32 mcp = nv_rd32(dev, 0x660180 + (i * 0x20));
1674                 u32 cfg = nv_rd32(dev, 0x660184 + (i * 0x20));
1675                 if (!(mcp & (1 << crtc)))
1676                         continue;
1677
1678                 dcb = lookup_dcb(dev, i, mcp);
1679                 if (!dcb)
1680                         continue;
1681                 or = ffs(dcb->or) - 1;
1682
1683                 nouveau_bios_run_display_table(dev, cfg, pclk, dcb, crtc);
1684
1685                 nv_wr32(dev, 0x612200 + (crtc * 0x800), 0x00000000);
1686                 switch (dcb->type) {
1687                 case DCB_OUTPUT_ANALOG:
1688                         nv_wr32(dev, 0x612280 + (or * 0x800), 0x00000000);
1689                         break;
1690                 case DCB_OUTPUT_TMDS:
1691                 case DCB_OUTPUT_LVDS:
1692                 case DCB_OUTPUT_DP:
1693                         if (cfg & 0x00000100)
1694                                 tmp = 0x00000101;
1695                         else
1696                                 tmp = 0x00000000;
1697
1698                         nv_mask(dev, 0x612300 + (or * 0x800), 0x00000707, tmp);
1699                         break;
1700                 default:
1701                         break;
1702                 }
1703
1704                 break;
1705         }
1706
1707         nv_wr32(dev, 0x6101d4, 0x00000000);
1708         nv_wr32(dev, 0x6109d4, 0x00000000);
1709         nv_wr32(dev, 0x6101d0, 0x80000000);
1710 }
1711
1712 static void
1713 nvd0_display_unk4_handler(struct drm_device *dev, u32 crtc, u32 mask)
1714 {
1715         struct dcb_output *dcb;
1716         int pclk, i;
1717
1718         pclk = nv_rd32(dev, 0x660450 + (crtc * 0x300)) / 1000;
1719
1720         for (i = 0; mask && i < 8; i++) {
1721                 u32 mcp = nv_rd32(dev, 0x660180 + (i * 0x20));
1722                 u32 cfg = nv_rd32(dev, 0x660184 + (i * 0x20));
1723                 if (!(mcp & (1 << crtc)))
1724                         continue;
1725
1726                 dcb = lookup_dcb(dev, i, mcp);
1727                 if (!dcb)
1728                         continue;
1729
1730                 nouveau_bios_run_display_table(dev, cfg, -pclk, dcb, crtc);
1731         }
1732
1733         nv_wr32(dev, 0x6101d4, 0x00000000);
1734         nv_wr32(dev, 0x6109d4, 0x00000000);
1735         nv_wr32(dev, 0x6101d0, 0x80000000);
1736 }
1737
1738 static void
1739 nvd0_display_bh(unsigned long data)
1740 {
1741         struct drm_device *dev = (struct drm_device *)data;
1742         struct nvd0_display *disp = nvd0_display(dev);
1743         u32 mask = 0, crtc = ~0;
1744         int i;
1745
1746         if (drm_debug & (DRM_UT_DRIVER | DRM_UT_KMS)) {
1747                 NV_INFO(dev, "PDISP: modeset req %d\n", disp->modeset);
1748                 NV_INFO(dev, " STAT: 0x%08x 0x%08x 0x%08x\n",
1749                          nv_rd32(dev, 0x6101d0),
1750                          nv_rd32(dev, 0x6101d4), nv_rd32(dev, 0x6109d4));
1751                 for (i = 0; i < 8; i++) {
1752                         NV_INFO(dev, " %s%d: 0x%08x 0x%08x\n",
1753                                 i < 4 ? "DAC" : "SOR", i,
1754                                 nv_rd32(dev, 0x640180 + (i * 0x20)),
1755                                 nv_rd32(dev, 0x660180 + (i * 0x20)));
1756                 }
1757         }
1758
1759         while (!mask && ++crtc < dev->mode_config.num_crtc)
1760                 mask = nv_rd32(dev, 0x6101d4 + (crtc * 0x800));
1761
1762         if (disp->modeset & 0x00000001)
1763                 nvd0_display_unk1_handler(dev, crtc, mask);
1764         if (disp->modeset & 0x00000002)
1765                 nvd0_display_unk2_handler(dev, crtc, mask);
1766         if (disp->modeset & 0x00000004)
1767                 nvd0_display_unk4_handler(dev, crtc, mask);
1768 }
1769
1770 static void
1771 nvd0_display_intr(struct drm_device *dev)
1772 {
1773         struct nvd0_display *disp = nvd0_display(dev);
1774         u32 intr = nv_rd32(dev, 0x610088);
1775         int i;
1776
1777         if (intr & 0x00000001) {
1778                 u32 stat = nv_rd32(dev, 0x61008c);
1779                 nv_wr32(dev, 0x61008c, stat);
1780                 intr &= ~0x00000001;
1781         }
1782
1783         if (intr & 0x00000002) {
1784                 u32 stat = nv_rd32(dev, 0x61009c);
1785                 int chid = ffs(stat) - 1;
1786                 if (chid >= 0) {
1787                         u32 mthd = nv_rd32(dev, 0x6101f0 + (chid * 12));
1788                         u32 data = nv_rd32(dev, 0x6101f4 + (chid * 12));
1789                         u32 unkn = nv_rd32(dev, 0x6101f8 + (chid * 12));
1790
1791                         NV_INFO(dev, "EvoCh: chid %d mthd 0x%04x data 0x%08x "
1792                                      "0x%08x 0x%08x\n",
1793                                 chid, (mthd & 0x0000ffc), data, mthd, unkn);
1794                         nv_wr32(dev, 0x61009c, (1 << chid));
1795                         nv_wr32(dev, 0x6101f0 + (chid * 12), 0x90000000);
1796                 }
1797
1798                 intr &= ~0x00000002;
1799         }
1800
1801         if (intr & 0x00100000) {
1802                 u32 stat = nv_rd32(dev, 0x6100ac);
1803
1804                 if (stat & 0x00000007) {
1805                         disp->modeset = stat;
1806                         tasklet_schedule(&disp->tasklet);
1807
1808                         nv_wr32(dev, 0x6100ac, (stat & 0x00000007));
1809                         stat &= ~0x00000007;
1810                 }
1811
1812                 if (stat) {
1813                         NV_INFO(dev, "PDISP: unknown intr24 0x%08x\n", stat);
1814                         nv_wr32(dev, 0x6100ac, stat);
1815                 }
1816
1817                 intr &= ~0x00100000;
1818         }
1819
1820         intr &= ~0x0f000000; /* vblank, handled in core */
1821         if (intr)
1822                 NV_INFO(dev, "PDISP: unknown intr 0x%08x\n", intr);
1823 }
1824
1825 /******************************************************************************
1826  * Init
1827  *****************************************************************************/
1828 void
1829 nvd0_display_fini(struct drm_device *dev)
1830 {
1831         int i;
1832
1833         /* fini cursors + overlays + flips */
1834         for (i = 1; i >= 0; i--) {
1835                 evo_fini_pio(dev, EVO_CURS(i));
1836                 evo_fini_pio(dev, EVO_OIMM(i));
1837                 evo_fini_dma(dev, EVO_OVLY(i));
1838                 evo_fini_dma(dev, EVO_FLIP(i));
1839         }
1840
1841         /* fini master */
1842         evo_fini_dma(dev, EVO_MASTER);
1843 }
1844
1845 int
1846 nvd0_display_init(struct drm_device *dev)
1847 {
1848         struct nvd0_display *disp = nvd0_display(dev);
1849         int ret, i;
1850         u32 *push;
1851
1852         if (nv_rd32(dev, 0x6100ac) & 0x00000100) {
1853                 nv_wr32(dev, 0x6100ac, 0x00000100);
1854                 nv_mask(dev, 0x6194e8, 0x00000001, 0x00000000);
1855                 if (!nv_wait(dev, 0x6194e8, 0x00000002, 0x00000000)) {
1856                         NV_ERROR(dev, "PDISP: 0x6194e8 0x%08x\n",
1857                                  nv_rd32(dev, 0x6194e8));
1858                         return -EBUSY;
1859                 }
1860         }
1861
1862         /* nfi what these are exactly, i do know that SOR_MODE_CTRL won't
1863          * work at all unless you do the SOR part below.
1864          */
1865         for (i = 0; i < 3; i++) {
1866                 u32 dac = nv_rd32(dev, 0x61a000 + (i * 0x800));
1867                 nv_wr32(dev, 0x6101c0 + (i * 0x800), dac);
1868         }
1869
1870         for (i = 0; i < 4; i++) {
1871                 u32 sor = nv_rd32(dev, 0x61c000 + (i * 0x800));
1872                 nv_wr32(dev, 0x6301c4 + (i * 0x800), sor);
1873         }
1874
1875         for (i = 0; i < dev->mode_config.num_crtc; i++) {
1876                 u32 crtc0 = nv_rd32(dev, 0x616104 + (i * 0x800));
1877                 u32 crtc1 = nv_rd32(dev, 0x616108 + (i * 0x800));
1878                 u32 crtc2 = nv_rd32(dev, 0x61610c + (i * 0x800));
1879                 nv_wr32(dev, 0x6101b4 + (i * 0x800), crtc0);
1880                 nv_wr32(dev, 0x6101b8 + (i * 0x800), crtc1);
1881                 nv_wr32(dev, 0x6101bc + (i * 0x800), crtc2);
1882         }
1883
1884         /* point at our hash table / objects, enable interrupts */
1885         nv_wr32(dev, 0x610010, (disp->mem->addr >> 8) | 9);
1886         nv_mask(dev, 0x6100b0, 0x00000307, 0x00000307);
1887
1888         /* init master */
1889         ret = evo_init_dma(dev, EVO_MASTER);
1890         if (ret)
1891                 goto error;
1892
1893         /* init flips + overlays + cursors */
1894         for (i = 0; i < dev->mode_config.num_crtc; i++) {
1895                 if ((ret = evo_init_dma(dev, EVO_FLIP(i))) ||
1896                     (ret = evo_init_dma(dev, EVO_OVLY(i))) ||
1897                     (ret = evo_init_pio(dev, EVO_OIMM(i))) ||
1898                     (ret = evo_init_pio(dev, EVO_CURS(i))))
1899                         goto error;
1900         }
1901
1902         push = evo_wait(dev, EVO_MASTER, 32);
1903         if (!push) {
1904                 ret = -EBUSY;
1905                 goto error;
1906         }
1907         evo_mthd(push, 0x0088, 1);
1908         evo_data(push, NvEvoSync);
1909         evo_mthd(push, 0x0084, 1);
1910         evo_data(push, 0x00000000);
1911         evo_mthd(push, 0x0084, 1);
1912         evo_data(push, 0x80000000);
1913         evo_mthd(push, 0x008c, 1);
1914         evo_data(push, 0x00000000);
1915         evo_kick(push, dev, EVO_MASTER);
1916
1917 error:
1918         if (ret)
1919                 nvd0_display_fini(dev);
1920         return ret;
1921 }
1922
1923 void
1924 nvd0_display_destroy(struct drm_device *dev)
1925 {
1926         struct drm_nouveau_private *dev_priv = dev->dev_private;
1927         struct nvd0_display *disp = nvd0_display(dev);
1928         struct pci_dev *pdev = dev->pdev;
1929         int i;
1930
1931         for (i = 0; i < EVO_DMA_NR; i++) {
1932                 struct evo *evo = &disp->evo[i];
1933                 pci_free_consistent(pdev, PAGE_SIZE, evo->ptr, evo->handle);
1934         }
1935
1936         nouveau_gpuobj_ref(NULL, &disp->mem);
1937         nouveau_bo_unmap(disp->sync);
1938         nouveau_bo_ref(NULL, &disp->sync);
1939         nouveau_irq_unregister(dev, 26);
1940
1941         dev_priv->engine.display.priv = NULL;
1942         kfree(disp);
1943 }
1944
1945 int
1946 nvd0_display_create(struct drm_device *dev)
1947 {
1948         struct drm_nouveau_private *dev_priv = dev->dev_private;
1949         struct dcb_table *dcb = &dev_priv->vbios.dcb;
1950         struct drm_connector *connector, *tmp;
1951         struct pci_dev *pdev = dev->pdev;
1952         struct nvd0_display *disp;
1953         struct dcb_output *dcbe;
1954         int crtcs, ret, i;
1955
1956         disp = kzalloc(sizeof(*disp), GFP_KERNEL);
1957         if (!disp)
1958                 return -ENOMEM;
1959         dev_priv->engine.display.priv = disp;
1960
1961         /* create crtc objects to represent the hw heads */
1962         crtcs = nv_rd32(dev, 0x022448);
1963         for (i = 0; i < crtcs; i++) {
1964                 ret = nvd0_crtc_create(dev, i);
1965                 if (ret)
1966                         goto out;
1967         }
1968
1969         /* create encoder/connector objects based on VBIOS DCB table */
1970         for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) {
1971                 connector = nouveau_connector_create(dev, dcbe->connector);
1972                 if (IS_ERR(connector))
1973                         continue;
1974
1975                 if (dcbe->location != DCB_LOC_ON_CHIP) {
1976                         NV_WARN(dev, "skipping off-chip encoder %d/%d\n",
1977                                 dcbe->type, ffs(dcbe->or) - 1);
1978                         continue;
1979                 }
1980
1981                 switch (dcbe->type) {
1982                 case DCB_OUTPUT_TMDS:
1983                 case DCB_OUTPUT_LVDS:
1984                 case DCB_OUTPUT_DP:
1985                         nvd0_sor_create(connector, dcbe);
1986                         break;
1987                 case DCB_OUTPUT_ANALOG:
1988                         nvd0_dac_create(connector, dcbe);
1989                         break;
1990                 default:
1991                         NV_WARN(dev, "skipping unsupported encoder %d/%d\n",
1992                                 dcbe->type, ffs(dcbe->or) - 1);
1993                         continue;
1994                 }
1995         }
1996
1997         /* cull any connectors we created that don't have an encoder */
1998         list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) {
1999                 if (connector->encoder_ids[0])
2000                         continue;
2001
2002                 NV_WARN(dev, "%s has no encoders, removing\n",
2003                         drm_get_connector_name(connector));
2004                 connector->funcs->destroy(connector);
2005         }
2006
2007         /* setup interrupt handling */
2008         tasklet_init(&disp->tasklet, nvd0_display_bh, (unsigned long)dev);
2009         nouveau_irq_register(dev, 26, nvd0_display_intr);
2010
2011         /* small shared memory area we use for notifiers and semaphores */
2012         ret = nouveau_bo_new(dev, 4096, 0x1000, TTM_PL_FLAG_VRAM,
2013                              0, 0x0000, NULL, &disp->sync);
2014         if (!ret) {
2015                 ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM);
2016                 if (!ret)
2017                         ret = nouveau_bo_map(disp->sync);
2018                 if (ret)
2019                         nouveau_bo_ref(NULL, &disp->sync);
2020         }
2021
2022         if (ret)
2023                 goto out;
2024
2025         /* hash table and dma objects for the memory areas we care about */
2026         ret = nouveau_gpuobj_new(dev, NULL, 0x4000, 0x10000,
2027                                  NVOBJ_FLAG_ZERO_ALLOC, &disp->mem);
2028         if (ret)
2029                 goto out;
2030
2031         /* create evo dma channels */
2032         for (i = 0; i < EVO_DMA_NR; i++) {
2033                 struct evo *evo = &disp->evo[i];
2034                 u64 offset = disp->sync->bo.offset;
2035                 u32 dmao = 0x1000 + (i * 0x100);
2036                 u32 hash = 0x0000 + (i * 0x040);
2037
2038                 evo->idx = i;
2039                 evo->sem.offset = EVO_SYNC(evo->idx, 0x00);
2040                 evo->ptr = pci_alloc_consistent(pdev, PAGE_SIZE, &evo->handle);
2041                 if (!evo->ptr) {
2042                         ret = -ENOMEM;
2043                         goto out;
2044                 }
2045
2046                 nv_wo32(disp->mem, dmao + 0x00, 0x00000049);
2047                 nv_wo32(disp->mem, dmao + 0x04, (offset + 0x0000) >> 8);
2048                 nv_wo32(disp->mem, dmao + 0x08, (offset + 0x0fff) >> 8);
2049                 nv_wo32(disp->mem, dmao + 0x0c, 0x00000000);
2050                 nv_wo32(disp->mem, dmao + 0x10, 0x00000000);
2051                 nv_wo32(disp->mem, dmao + 0x14, 0x00000000);
2052                 nv_wo32(disp->mem, hash + 0x00, NvEvoSync);
2053                 nv_wo32(disp->mem, hash + 0x04, 0x00000001 | (i << 27) |
2054                                                 ((dmao + 0x00) << 9));
2055
2056                 nv_wo32(disp->mem, dmao + 0x20, 0x00000049);
2057                 nv_wo32(disp->mem, dmao + 0x24, 0x00000000);
2058                 nv_wo32(disp->mem, dmao + 0x28, (nvfb_vram_size(dev) - 1) >> 8);
2059                 nv_wo32(disp->mem, dmao + 0x2c, 0x00000000);
2060                 nv_wo32(disp->mem, dmao + 0x30, 0x00000000);
2061                 nv_wo32(disp->mem, dmao + 0x34, 0x00000000);
2062                 nv_wo32(disp->mem, hash + 0x08, NvEvoVRAM);
2063                 nv_wo32(disp->mem, hash + 0x0c, 0x00000001 | (i << 27) |
2064                                                 ((dmao + 0x20) << 9));
2065
2066                 nv_wo32(disp->mem, dmao + 0x40, 0x00000009);
2067                 nv_wo32(disp->mem, dmao + 0x44, 0x00000000);
2068                 nv_wo32(disp->mem, dmao + 0x48, (nvfb_vram_size(dev) - 1) >> 8);
2069                 nv_wo32(disp->mem, dmao + 0x4c, 0x00000000);
2070                 nv_wo32(disp->mem, dmao + 0x50, 0x00000000);
2071                 nv_wo32(disp->mem, dmao + 0x54, 0x00000000);
2072                 nv_wo32(disp->mem, hash + 0x10, NvEvoVRAM_LP);
2073                 nv_wo32(disp->mem, hash + 0x14, 0x00000001 | (i << 27) |
2074                                                 ((dmao + 0x40) << 9));
2075
2076                 nv_wo32(disp->mem, dmao + 0x60, 0x0fe00009);
2077                 nv_wo32(disp->mem, dmao + 0x64, 0x00000000);
2078                 nv_wo32(disp->mem, dmao + 0x68, (nvfb_vram_size(dev) - 1) >> 8);
2079                 nv_wo32(disp->mem, dmao + 0x6c, 0x00000000);
2080                 nv_wo32(disp->mem, dmao + 0x70, 0x00000000);
2081                 nv_wo32(disp->mem, dmao + 0x74, 0x00000000);
2082                 nv_wo32(disp->mem, hash + 0x18, NvEvoFB32);
2083                 nv_wo32(disp->mem, hash + 0x1c, 0x00000001 | (i << 27) |
2084                                                 ((dmao + 0x60) << 9));
2085         }
2086
2087         nvimem_flush(dev);
2088
2089 out:
2090         if (ret)
2091                 nvd0_display_destroy(dev);
2092         return ret;
2093 }