2 * Copyright 2010 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <linux/firmware.h>
26 #include <linux/module.h>
30 #include "nouveau_drv.h"
31 #include "nouveau_mm.h"
33 #include "nvc0_graph.h"
34 #include "nvc0_grhub.fuc.h"
35 #include "nvc0_grgpc.fuc.h"
38 nvc0_graph_ctxctl_debug_unit(struct drm_device *dev, u32 base)
40 NV_INFO(dev, "PGRAPH: %06x - done 0x%08x\n", base,
41 nv_rd32(dev, base + 0x400));
42 NV_INFO(dev, "PGRAPH: %06x - stat 0x%08x 0x%08x 0x%08x 0x%08x\n", base,
43 nv_rd32(dev, base + 0x800), nv_rd32(dev, base + 0x804),
44 nv_rd32(dev, base + 0x808), nv_rd32(dev, base + 0x80c));
45 NV_INFO(dev, "PGRAPH: %06x - stat 0x%08x 0x%08x 0x%08x 0x%08x\n", base,
46 nv_rd32(dev, base + 0x810), nv_rd32(dev, base + 0x814),
47 nv_rd32(dev, base + 0x818), nv_rd32(dev, base + 0x81c));
51 nvc0_graph_ctxctl_debug(struct drm_device *dev)
53 u32 gpcnr = nv_rd32(dev, 0x409604) & 0xffff;
56 nvc0_graph_ctxctl_debug_unit(dev, 0x409000);
57 for (gpc = 0; gpc < gpcnr; gpc++)
58 nvc0_graph_ctxctl_debug_unit(dev, 0x502000 + (gpc * 0x8000));
62 nvc0_graph_load_context(struct nouveau_channel *chan)
64 struct drm_device *dev = chan->dev;
66 nv_wr32(dev, 0x409840, 0x00000030);
67 nv_wr32(dev, 0x409500, 0x80000000 | chan->ramin->vinst >> 12);
68 nv_wr32(dev, 0x409504, 0x00000003);
69 if (!nv_wait(dev, 0x409800, 0x00000010, 0x00000010))
70 NV_ERROR(dev, "PGRAPH: load_ctx timeout\n");
76 nvc0_graph_unload_context_to(struct drm_device *dev, u64 chan)
78 nv_wr32(dev, 0x409840, 0x00000003);
79 nv_wr32(dev, 0x409500, 0x80000000 | chan >> 12);
80 nv_wr32(dev, 0x409504, 0x00000009);
81 if (!nv_wait(dev, 0x409800, 0x00000001, 0x00000000)) {
82 NV_ERROR(dev, "PGRAPH: unload_ctx timeout\n");
90 nvc0_graph_construct_context(struct nouveau_channel *chan)
92 struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
93 struct nvc0_graph_priv *priv = nv_engine(chan->dev, NVOBJ_ENGINE_GR);
94 struct nvc0_graph_chan *grch = chan->engctx[NVOBJ_ENGINE_GR];
95 struct drm_device *dev = chan->dev;
99 ctx = kmalloc(priv->grctx_size, GFP_KERNEL);
103 if (!nouveau_ctxfw) {
104 nv_wr32(dev, 0x409840, 0x80000000);
105 nv_wr32(dev, 0x409500, 0x80000000 | chan->ramin->vinst >> 12);
106 nv_wr32(dev, 0x409504, 0x00000001);
107 if (!nv_wait(dev, 0x409800, 0x80000000, 0x80000000)) {
108 NV_ERROR(dev, "PGRAPH: HUB_SET_CHAN timeout\n");
109 nvc0_graph_ctxctl_debug(dev);
114 nvc0_graph_load_context(chan);
116 nv_wo32(grch->grctx, 0x1c, 1);
117 nv_wo32(grch->grctx, 0x20, 0);
118 nv_wo32(grch->grctx, 0x28, 0);
119 nv_wo32(grch->grctx, 0x2c, 0);
120 dev_priv->engine.instmem.flush(dev);
123 ret = nvc0_grctx_generate(chan);
127 if (!nouveau_ctxfw) {
128 nv_wr32(dev, 0x409840, 0x80000000);
129 nv_wr32(dev, 0x409500, 0x80000000 | chan->ramin->vinst >> 12);
130 nv_wr32(dev, 0x409504, 0x00000002);
131 if (!nv_wait(dev, 0x409800, 0x80000000, 0x80000000)) {
132 NV_ERROR(dev, "PGRAPH: HUB_CTX_SAVE timeout\n");
133 nvc0_graph_ctxctl_debug(dev);
138 ret = nvc0_graph_unload_context_to(dev, chan->ramin->vinst);
143 for (i = 0; i < priv->grctx_size; i += 4)
144 ctx[i / 4] = nv_ro32(grch->grctx, i);
146 priv->grctx_vals = ctx;
155 nvc0_graph_create_context_mmio_list(struct nouveau_channel *chan)
157 struct nvc0_graph_priv *priv = nv_engine(chan->dev, NVOBJ_ENGINE_GR);
158 struct nvc0_graph_chan *grch = chan->engctx[NVOBJ_ENGINE_GR];
159 struct drm_device *dev = chan->dev;
160 struct drm_nouveau_private *dev_priv = dev->dev_private;
161 int i = 0, gpc, tp, ret;
163 ret = nouveau_gpuobj_new(dev, chan, 0x2000, 256, NVOBJ_FLAG_VM,
168 ret = nouveau_gpuobj_new(dev, chan, 0x8000, 256, NVOBJ_FLAG_VM,
173 ret = nouveau_gpuobj_new(dev, chan, 384 * 1024, 4096,
174 NVOBJ_FLAG_VM | NVOBJ_FLAG_VM_USER,
179 ret = nouveau_gpuobj_new(dev, chan, 0x1000, 0, NVOBJ_FLAG_VM,
185 nv_wo32(grch->mmio, i++ * 4, 0x00408004);
186 nv_wo32(grch->mmio, i++ * 4, grch->unk408004->linst >> 8);
187 nv_wo32(grch->mmio, i++ * 4, 0x00408008);
188 nv_wo32(grch->mmio, i++ * 4, 0x80000018);
190 nv_wo32(grch->mmio, i++ * 4, 0x0040800c);
191 nv_wo32(grch->mmio, i++ * 4, grch->unk40800c->linst >> 8);
192 nv_wo32(grch->mmio, i++ * 4, 0x00408010);
193 nv_wo32(grch->mmio, i++ * 4, 0x80000000);
195 nv_wo32(grch->mmio, i++ * 4, 0x00418810);
196 nv_wo32(grch->mmio, i++ * 4, 0x80000000 | grch->unk418810->linst >> 12);
197 nv_wo32(grch->mmio, i++ * 4, 0x00419848);
198 nv_wo32(grch->mmio, i++ * 4, 0x10000000 | grch->unk418810->linst >> 12);
200 nv_wo32(grch->mmio, i++ * 4, 0x00419004);
201 nv_wo32(grch->mmio, i++ * 4, grch->unk40800c->linst >> 8);
202 nv_wo32(grch->mmio, i++ * 4, 0x00419008);
203 nv_wo32(grch->mmio, i++ * 4, 0x00000000);
205 nv_wo32(grch->mmio, i++ * 4, 0x00418808);
206 nv_wo32(grch->mmio, i++ * 4, grch->unk408004->linst >> 8);
207 nv_wo32(grch->mmio, i++ * 4, 0x0041880c);
208 nv_wo32(grch->mmio, i++ * 4, 0x80000018);
210 if (dev_priv->chipset != 0xc1) {
211 u32 magic = 0x02180000;
212 nv_wo32(grch->mmio, i++ * 4, 0x00405830);
213 nv_wo32(grch->mmio, i++ * 4, magic);
214 for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
215 for (tp = 0; tp < priv->tp_nr[gpc]; tp++) {
216 u32 reg = TP_UNIT(gpc, tp, 0x520);
217 nv_wo32(grch->mmio, i++ * 4, reg);
218 nv_wo32(grch->mmio, i++ * 4, magic);
223 u32 magic = 0x02180000;
224 nv_wo32(grch->mmio, i++ * 4, 0x00405830);
225 nv_wo32(grch->mmio, i++ * 4, magic | 0x0000218);
226 nv_wo32(grch->mmio, i++ * 4, 0x004064c4);
227 nv_wo32(grch->mmio, i++ * 4, 0x0086ffff);
228 for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
229 for (tp = 0; tp < priv->tp_nr[gpc]; tp++) {
230 u32 reg = TP_UNIT(gpc, tp, 0x520);
231 nv_wo32(grch->mmio, i++ * 4, reg);
232 nv_wo32(grch->mmio, i++ * 4, (1 << 28) | magic);
235 for (tp = 0; tp < priv->tp_nr[gpc]; tp++) {
236 u32 reg = TP_UNIT(gpc, tp, 0x544);
237 nv_wo32(grch->mmio, i++ * 4, reg);
238 nv_wo32(grch->mmio, i++ * 4, magic);
244 grch->mmio_nr = i / 2;
249 nvc0_graph_context_new(struct nouveau_channel *chan, int engine)
251 struct drm_device *dev = chan->dev;
252 struct drm_nouveau_private *dev_priv = dev->dev_private;
253 struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
254 struct nvc0_graph_priv *priv = nv_engine(dev, engine);
255 struct nvc0_graph_chan *grch;
256 struct nouveau_gpuobj *grctx;
259 grch = kzalloc(sizeof(*grch), GFP_KERNEL);
262 chan->engctx[NVOBJ_ENGINE_GR] = grch;
264 ret = nouveau_gpuobj_new(dev, chan, priv->grctx_size, 256,
265 NVOBJ_FLAG_VM | NVOBJ_FLAG_ZERO_ALLOC,
271 ret = nvc0_graph_create_context_mmio_list(chan);
275 nv_wo32(chan->ramin, 0x0210, lower_32_bits(grctx->linst) | 4);
276 nv_wo32(chan->ramin, 0x0214, upper_32_bits(grctx->linst));
277 pinstmem->flush(dev);
279 if (!priv->grctx_vals) {
280 ret = nvc0_graph_construct_context(chan);
285 for (i = 0; i < priv->grctx_size; i += 4)
286 nv_wo32(grctx, i, priv->grctx_vals[i / 4]);
288 if (!nouveau_ctxfw) {
289 nv_wo32(grctx, 0x00, grch->mmio_nr);
290 nv_wo32(grctx, 0x04, grch->mmio->linst >> 8);
292 nv_wo32(grctx, 0xf4, 0);
293 nv_wo32(grctx, 0xf8, 0);
294 nv_wo32(grctx, 0x10, grch->mmio_nr);
295 nv_wo32(grctx, 0x14, lower_32_bits(grch->mmio->linst));
296 nv_wo32(grctx, 0x18, upper_32_bits(grch->mmio->linst));
297 nv_wo32(grctx, 0x1c, 1);
298 nv_wo32(grctx, 0x20, 0);
299 nv_wo32(grctx, 0x28, 0);
300 nv_wo32(grctx, 0x2c, 0);
302 pinstmem->flush(dev);
306 priv->base.context_del(chan, engine);
311 nvc0_graph_context_del(struct nouveau_channel *chan, int engine)
313 struct nvc0_graph_chan *grch = chan->engctx[engine];
315 nouveau_gpuobj_ref(NULL, &grch->mmio);
316 nouveau_gpuobj_ref(NULL, &grch->unk418810);
317 nouveau_gpuobj_ref(NULL, &grch->unk40800c);
318 nouveau_gpuobj_ref(NULL, &grch->unk408004);
319 nouveau_gpuobj_ref(NULL, &grch->grctx);
320 chan->engctx[engine] = NULL;
324 nvc0_graph_object_new(struct nouveau_channel *chan, int engine,
325 u32 handle, u16 class)
331 nvc0_graph_fini(struct drm_device *dev, int engine, bool suspend)
337 nvc0_graph_mthd_page_flip(struct nouveau_channel *chan,
338 u32 class, u32 mthd, u32 data)
340 nouveau_finish_page_flip(chan, NULL);
345 nvc0_graph_init_obj418880(struct drm_device *dev)
347 struct nvc0_graph_priv *priv = nv_engine(dev, NVOBJ_ENGINE_GR);
350 nv_wr32(dev, GPC_BCAST(0x0880), 0x00000000);
351 nv_wr32(dev, GPC_BCAST(0x08a4), 0x00000000);
352 for (i = 0; i < 4; i++)
353 nv_wr32(dev, GPC_BCAST(0x0888) + (i * 4), 0x00000000);
354 nv_wr32(dev, GPC_BCAST(0x08b4), priv->unk4188b4->vinst >> 8);
355 nv_wr32(dev, GPC_BCAST(0x08b8), priv->unk4188b8->vinst >> 8);
359 nvc0_graph_init_regs(struct drm_device *dev)
361 nv_wr32(dev, 0x400080, 0x003083c2);
362 nv_wr32(dev, 0x400088, 0x00006fe7);
363 nv_wr32(dev, 0x40008c, 0x00000000);
364 nv_wr32(dev, 0x400090, 0x00000030);
365 nv_wr32(dev, 0x40013c, 0x013901f7);
366 nv_wr32(dev, 0x400140, 0x00000100);
367 nv_wr32(dev, 0x400144, 0x00000000);
368 nv_wr32(dev, 0x400148, 0x00000110);
369 nv_wr32(dev, 0x400138, 0x00000000);
370 nv_wr32(dev, 0x400130, 0x00000000);
371 nv_wr32(dev, 0x400134, 0x00000000);
372 nv_wr32(dev, 0x400124, 0x00000002);
376 nvc0_graph_init_gpc_0(struct drm_device *dev)
378 struct nvc0_graph_priv *priv = nv_engine(dev, NVOBJ_ENGINE_GR);
379 const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, priv->tp_total);
380 u32 data[TP_MAX / 8];
385 * TP ROP UNKVAL(magic_not_rop_nr)
393 memset(data, 0x00, sizeof(data));
394 memcpy(tpnr, priv->tp_nr, sizeof(priv->tp_nr));
395 for (i = 0, gpc = -1; i < priv->tp_total; i++) {
397 gpc = (gpc + 1) % priv->gpc_nr;
398 } while (!tpnr[gpc]);
399 tpc = priv->tp_nr[gpc] - tpnr[gpc]--;
401 data[i / 8] |= tpc << ((i % 8) * 4);
404 nv_wr32(dev, GPC_BCAST(0x0980), data[0]);
405 nv_wr32(dev, GPC_BCAST(0x0984), data[1]);
406 nv_wr32(dev, GPC_BCAST(0x0988), data[2]);
407 nv_wr32(dev, GPC_BCAST(0x098c), data[3]);
409 for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
410 nv_wr32(dev, GPC_UNIT(gpc, 0x0914), priv->magic_not_rop_nr << 8 |
412 nv_wr32(dev, GPC_UNIT(gpc, 0x0910), 0x00040000 | priv->tp_total);
413 nv_wr32(dev, GPC_UNIT(gpc, 0x0918), magicgpc918);
416 nv_wr32(dev, GPC_BCAST(0x1bd4), magicgpc918);
417 nv_wr32(dev, GPC_BCAST(0x08ac), nv_rd32(dev, 0x100800));
421 nvc0_graph_init_units(struct drm_device *dev)
423 nv_wr32(dev, 0x409c24, 0x000f0000);
424 nv_wr32(dev, 0x404000, 0xc0000000); /* DISPATCH */
425 nv_wr32(dev, 0x404600, 0xc0000000); /* M2MF */
426 nv_wr32(dev, 0x408030, 0xc0000000);
427 nv_wr32(dev, 0x40601c, 0xc0000000);
428 nv_wr32(dev, 0x404490, 0xc0000000); /* MACRO */
429 nv_wr32(dev, 0x406018, 0xc0000000);
430 nv_wr32(dev, 0x405840, 0xc0000000);
431 nv_wr32(dev, 0x405844, 0x00ffffff);
432 nv_mask(dev, 0x419cc0, 0x00000008, 0x00000008);
433 nv_mask(dev, 0x419eb4, 0x00001000, 0x00001000);
437 nvc0_graph_init_gpc_1(struct drm_device *dev)
439 struct nvc0_graph_priv *priv = nv_engine(dev, NVOBJ_ENGINE_GR);
442 for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
443 nv_wr32(dev, GPC_UNIT(gpc, 0x0420), 0xc0000000);
444 nv_wr32(dev, GPC_UNIT(gpc, 0x0900), 0xc0000000);
445 nv_wr32(dev, GPC_UNIT(gpc, 0x1028), 0xc0000000);
446 nv_wr32(dev, GPC_UNIT(gpc, 0x0824), 0xc0000000);
447 for (tp = 0; tp < priv->tp_nr[gpc]; tp++) {
448 nv_wr32(dev, TP_UNIT(gpc, tp, 0x508), 0xffffffff);
449 nv_wr32(dev, TP_UNIT(gpc, tp, 0x50c), 0xffffffff);
450 nv_wr32(dev, TP_UNIT(gpc, tp, 0x224), 0xc0000000);
451 nv_wr32(dev, TP_UNIT(gpc, tp, 0x48c), 0xc0000000);
452 nv_wr32(dev, TP_UNIT(gpc, tp, 0x084), 0xc0000000);
453 nv_wr32(dev, TP_UNIT(gpc, tp, 0x644), 0x001ffffe);
454 nv_wr32(dev, TP_UNIT(gpc, tp, 0x64c), 0x0000000f);
456 nv_wr32(dev, GPC_UNIT(gpc, 0x2c90), 0xffffffff);
457 nv_wr32(dev, GPC_UNIT(gpc, 0x2c94), 0xffffffff);
462 nvc0_graph_init_rop(struct drm_device *dev)
464 struct nvc0_graph_priv *priv = nv_engine(dev, NVOBJ_ENGINE_GR);
467 for (rop = 0; rop < priv->rop_nr; rop++) {
468 nv_wr32(dev, ROP_UNIT(rop, 0x144), 0xc0000000);
469 nv_wr32(dev, ROP_UNIT(rop, 0x070), 0xc0000000);
470 nv_wr32(dev, ROP_UNIT(rop, 0x204), 0xffffffff);
471 nv_wr32(dev, ROP_UNIT(rop, 0x208), 0xffffffff);
476 nvc0_graph_init_fuc(struct drm_device *dev, u32 fuc_base,
477 struct nvc0_graph_fuc *code, struct nvc0_graph_fuc *data)
481 nv_wr32(dev, fuc_base + 0x01c0, 0x01000000);
482 for (i = 0; i < data->size / 4; i++)
483 nv_wr32(dev, fuc_base + 0x01c4, data->data[i]);
485 nv_wr32(dev, fuc_base + 0x0180, 0x01000000);
486 for (i = 0; i < code->size / 4; i++) {
488 nv_wr32(dev, fuc_base + 0x0188, i >> 6);
489 nv_wr32(dev, fuc_base + 0x0184, code->data[i]);
494 nvc0_graph_init_ctxctl(struct drm_device *dev)
496 struct drm_nouveau_private *dev_priv = dev->dev_private;
497 struct nvc0_graph_priv *priv = nv_engine(dev, NVOBJ_ENGINE_GR);
501 if (!nouveau_ctxfw) {
502 /* load HUB microcode */
503 r000260 = nv_mask(dev, 0x000260, 0x00000001, 0x00000000);
504 nv_wr32(dev, 0x4091c0, 0x01000000);
505 for (i = 0; i < sizeof(nvc0_grhub_data) / 4; i++)
506 nv_wr32(dev, 0x4091c4, nvc0_grhub_data[i]);
508 nv_wr32(dev, 0x409180, 0x01000000);
509 for (i = 0; i < sizeof(nvc0_grhub_code) / 4; i++) {
511 nv_wr32(dev, 0x409188, i >> 6);
512 nv_wr32(dev, 0x409184, nvc0_grhub_code[i]);
515 /* load GPC microcode */
516 nv_wr32(dev, 0x41a1c0, 0x01000000);
517 for (i = 0; i < sizeof(nvc0_grgpc_data) / 4; i++)
518 nv_wr32(dev, 0x41a1c4, nvc0_grgpc_data[i]);
520 nv_wr32(dev, 0x41a180, 0x01000000);
521 for (i = 0; i < sizeof(nvc0_grgpc_code) / 4; i++) {
523 nv_wr32(dev, 0x41a188, i >> 6);
524 nv_wr32(dev, 0x41a184, nvc0_grgpc_code[i]);
526 nv_wr32(dev, 0x000260, r000260);
528 /* start HUB ucode running, it'll init the GPCs */
529 nv_wr32(dev, 0x409800, dev_priv->chipset);
530 nv_wr32(dev, 0x40910c, 0x00000000);
531 nv_wr32(dev, 0x409100, 0x00000002);
532 if (!nv_wait(dev, 0x409800, 0x80000000, 0x80000000)) {
533 NV_ERROR(dev, "PGRAPH: HUB_INIT timed out\n");
534 nvc0_graph_ctxctl_debug(dev);
538 priv->grctx_size = nv_rd32(dev, 0x409804);
542 /* load fuc microcode */
543 r000260 = nv_mask(dev, 0x000260, 0x00000001, 0x00000000);
544 nvc0_graph_init_fuc(dev, 0x409000, &priv->fuc409c, &priv->fuc409d);
545 nvc0_graph_init_fuc(dev, 0x41a000, &priv->fuc41ac, &priv->fuc41ad);
546 nv_wr32(dev, 0x000260, r000260);
548 /* start both of them running */
549 nv_wr32(dev, 0x409840, 0xffffffff);
550 nv_wr32(dev, 0x41a10c, 0x00000000);
551 nv_wr32(dev, 0x40910c, 0x00000000);
552 nv_wr32(dev, 0x41a100, 0x00000002);
553 nv_wr32(dev, 0x409100, 0x00000002);
554 if (!nv_wait(dev, 0x409800, 0x00000001, 0x00000001))
555 NV_INFO(dev, "0x409800 wait failed\n");
557 nv_wr32(dev, 0x409840, 0xffffffff);
558 nv_wr32(dev, 0x409500, 0x7fffffff);
559 nv_wr32(dev, 0x409504, 0x00000021);
561 nv_wr32(dev, 0x409840, 0xffffffff);
562 nv_wr32(dev, 0x409500, 0x00000000);
563 nv_wr32(dev, 0x409504, 0x00000010);
564 if (!nv_wait_ne(dev, 0x409800, 0xffffffff, 0x00000000)) {
565 NV_ERROR(dev, "fuc09 req 0x10 timeout\n");
568 priv->grctx_size = nv_rd32(dev, 0x409800);
570 nv_wr32(dev, 0x409840, 0xffffffff);
571 nv_wr32(dev, 0x409500, 0x00000000);
572 nv_wr32(dev, 0x409504, 0x00000016);
573 if (!nv_wait_ne(dev, 0x409800, 0xffffffff, 0x00000000)) {
574 NV_ERROR(dev, "fuc09 req 0x16 timeout\n");
578 nv_wr32(dev, 0x409840, 0xffffffff);
579 nv_wr32(dev, 0x409500, 0x00000000);
580 nv_wr32(dev, 0x409504, 0x00000025);
581 if (!nv_wait_ne(dev, 0x409800, 0xffffffff, 0x00000000)) {
582 NV_ERROR(dev, "fuc09 req 0x25 timeout\n");
590 nvc0_graph_init(struct drm_device *dev, int engine)
594 nv_mask(dev, 0x000200, 0x18001000, 0x00000000);
595 nv_mask(dev, 0x000200, 0x18001000, 0x18001000);
597 nvc0_graph_init_obj418880(dev);
598 nvc0_graph_init_regs(dev);
599 /*nvc0_graph_init_unitplemented_magics(dev);*/
600 nvc0_graph_init_gpc_0(dev);
601 /*nvc0_graph_init_unitplemented_c242(dev);*/
603 nv_wr32(dev, 0x400500, 0x00010001);
604 nv_wr32(dev, 0x400100, 0xffffffff);
605 nv_wr32(dev, 0x40013c, 0xffffffff);
607 nvc0_graph_init_units(dev);
608 nvc0_graph_init_gpc_1(dev);
609 nvc0_graph_init_rop(dev);
611 nv_wr32(dev, 0x400108, 0xffffffff);
612 nv_wr32(dev, 0x400138, 0xffffffff);
613 nv_wr32(dev, 0x400118, 0xffffffff);
614 nv_wr32(dev, 0x400130, 0xffffffff);
615 nv_wr32(dev, 0x40011c, 0xffffffff);
616 nv_wr32(dev, 0x400134, 0xffffffff);
617 nv_wr32(dev, 0x400054, 0x34ce3464);
619 ret = nvc0_graph_init_ctxctl(dev);
627 nvc0_graph_isr_chid(struct drm_device *dev, u64 inst)
629 struct drm_nouveau_private *dev_priv = dev->dev_private;
630 struct nouveau_channel *chan;
634 spin_lock_irqsave(&dev_priv->channels.lock, flags);
635 for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
636 chan = dev_priv->channels.ptr[i];
637 if (!chan || !chan->ramin)
640 if (inst == chan->ramin->vinst)
643 spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
648 nvc0_graph_ctxctl_isr(struct drm_device *dev)
650 u32 ustat = nv_rd32(dev, 0x409c18);
652 if (ustat & 0x00000001)
653 NV_INFO(dev, "PGRAPH: CTXCTRL ucode error\n");
654 if (ustat & 0x00080000)
655 NV_INFO(dev, "PGRAPH: CTXCTRL watchdog timeout\n");
656 if (ustat & ~0x00080001)
657 NV_INFO(dev, "PGRAPH: CTXCTRL 0x%08x\n", ustat);
659 nvc0_graph_ctxctl_debug(dev);
660 nv_wr32(dev, 0x409c20, ustat);
664 nvc0_graph_isr(struct drm_device *dev)
666 u64 inst = (u64)(nv_rd32(dev, 0x409b00) & 0x0fffffff) << 12;
667 u32 chid = nvc0_graph_isr_chid(dev, inst);
668 u32 stat = nv_rd32(dev, 0x400100);
669 u32 addr = nv_rd32(dev, 0x400704);
670 u32 mthd = (addr & 0x00003ffc);
671 u32 subc = (addr & 0x00070000) >> 16;
672 u32 data = nv_rd32(dev, 0x400708);
673 u32 code = nv_rd32(dev, 0x400110);
674 u32 class = nv_rd32(dev, 0x404200 + (subc * 4));
676 if (stat & 0x00000010) {
677 if (nouveau_gpuobj_mthd_call2(dev, chid, class, mthd, data)) {
678 NV_INFO(dev, "PGRAPH: ILLEGAL_MTHD ch %d [0x%010llx] "
679 "subc %d class 0x%04x mthd 0x%04x "
681 chid, inst, subc, class, mthd, data);
683 nv_wr32(dev, 0x400100, 0x00000010);
687 if (stat & 0x00000020) {
688 NV_INFO(dev, "PGRAPH: ILLEGAL_CLASS ch %d [0x%010llx] subc %d "
689 "class 0x%04x mthd 0x%04x data 0x%08x\n",
690 chid, inst, subc, class, mthd, data);
691 nv_wr32(dev, 0x400100, 0x00000020);
695 if (stat & 0x00100000) {
696 NV_INFO(dev, "PGRAPH: DATA_ERROR [");
697 nouveau_enum_print(nv50_data_error_names, code);
698 printk("] ch %d [0x%010llx] subc %d class 0x%04x "
699 "mthd 0x%04x data 0x%08x\n",
700 chid, inst, subc, class, mthd, data);
701 nv_wr32(dev, 0x400100, 0x00100000);
705 if (stat & 0x00200000) {
706 u32 trap = nv_rd32(dev, 0x400108);
707 NV_INFO(dev, "PGRAPH: TRAP ch %d status 0x%08x\n", chid, trap);
708 nv_wr32(dev, 0x400108, trap);
709 nv_wr32(dev, 0x400100, 0x00200000);
713 if (stat & 0x00080000) {
714 nvc0_graph_ctxctl_isr(dev);
715 nv_wr32(dev, 0x400100, 0x00080000);
720 NV_INFO(dev, "PGRAPH: unknown stat 0x%08x\n", stat);
721 nv_wr32(dev, 0x400100, stat);
724 nv_wr32(dev, 0x400500, 0x00010001);
728 nvc0_graph_create_fw(struct drm_device *dev, const char *fwname,
729 struct nvc0_graph_fuc *fuc)
731 struct drm_nouveau_private *dev_priv = dev->dev_private;
732 const struct firmware *fw;
736 snprintf(f, sizeof(f), "nouveau/nv%02x_%s", dev_priv->chipset, fwname);
737 ret = request_firmware(&fw, f, &dev->pdev->dev);
739 snprintf(f, sizeof(f), "nouveau/%s", fwname);
740 ret = request_firmware(&fw, f, &dev->pdev->dev);
742 NV_ERROR(dev, "failed to load %s\n", fwname);
747 fuc->size = fw->size;
748 fuc->data = kmemdup(fw->data, fuc->size, GFP_KERNEL);
749 release_firmware(fw);
750 return (fuc->data != NULL) ? 0 : -ENOMEM;
754 nvc0_graph_destroy_fw(struct nvc0_graph_fuc *fuc)
763 nvc0_graph_destroy(struct drm_device *dev, int engine)
765 struct nvc0_graph_priv *priv = nv_engine(dev, engine);
768 nvc0_graph_destroy_fw(&priv->fuc409c);
769 nvc0_graph_destroy_fw(&priv->fuc409d);
770 nvc0_graph_destroy_fw(&priv->fuc41ac);
771 nvc0_graph_destroy_fw(&priv->fuc41ad);
774 nouveau_irq_unregister(dev, 12);
776 nouveau_gpuobj_ref(NULL, &priv->unk4188b8);
777 nouveau_gpuobj_ref(NULL, &priv->unk4188b4);
779 if (priv->grctx_vals)
780 kfree(priv->grctx_vals);
782 NVOBJ_ENGINE_DEL(dev, GR);
787 nvc0_graph_create(struct drm_device *dev)
789 struct drm_nouveau_private *dev_priv = dev->dev_private;
790 struct nvc0_graph_priv *priv;
794 fermi = nvc0_graph_class(dev);
796 NV_ERROR(dev, "PGRAPH: unsupported chipset, please report!\n");
800 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
804 priv->base.destroy = nvc0_graph_destroy;
805 priv->base.init = nvc0_graph_init;
806 priv->base.fini = nvc0_graph_fini;
807 priv->base.context_new = nvc0_graph_context_new;
808 priv->base.context_del = nvc0_graph_context_del;
809 priv->base.object_new = nvc0_graph_object_new;
811 NVOBJ_ENGINE_ADD(dev, GR, &priv->base);
812 nouveau_irq_register(dev, 12, nvc0_graph_isr);
815 NV_INFO(dev, "PGRAPH: using external firmware\n");
816 if (nvc0_graph_create_fw(dev, "fuc409c", &priv->fuc409c) ||
817 nvc0_graph_create_fw(dev, "fuc409d", &priv->fuc409d) ||
818 nvc0_graph_create_fw(dev, "fuc41ac", &priv->fuc41ac) ||
819 nvc0_graph_create_fw(dev, "fuc41ad", &priv->fuc41ad)) {
825 ret = nouveau_gpuobj_new(dev, NULL, 0x1000, 256, 0, &priv->unk4188b4);
829 ret = nouveau_gpuobj_new(dev, NULL, 0x1000, 256, 0, &priv->unk4188b8);
833 for (i = 0; i < 0x1000; i += 4) {
834 nv_wo32(priv->unk4188b4, i, 0x00000010);
835 nv_wo32(priv->unk4188b8, i, 0x00000010);
838 priv->gpc_nr = nv_rd32(dev, 0x409604) & 0x0000001f;
839 priv->rop_nr = (nv_rd32(dev, 0x409604) & 0x001f0000) >> 16;
840 for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
841 priv->tp_nr[gpc] = nv_rd32(dev, GPC_UNIT(gpc, 0x2608));
842 priv->tp_total += priv->tp_nr[gpc];
845 /*XXX: these need figuring out... */
846 switch (dev_priv->chipset) {
848 if (priv->tp_total == 11) { /* 465, 3/4/4/0, 4 */
849 priv->magic_not_rop_nr = 0x07;
851 if (priv->tp_total == 14) { /* 470, 3/3/4/4, 5 */
852 priv->magic_not_rop_nr = 0x05;
854 if (priv->tp_total == 15) { /* 480, 3/4/4/4, 6 */
855 priv->magic_not_rop_nr = 0x06;
858 case 0xc3: /* 450, 4/0/0/0, 2 */
859 priv->magic_not_rop_nr = 0x03;
861 case 0xc4: /* 460, 3/4/0/0, 4 */
862 priv->magic_not_rop_nr = 0x01;
864 case 0xc1: /* 2/0/0/0, 1 */
865 priv->magic_not_rop_nr = 0x01;
867 case 0xc8: /* 4/4/3/4, 5 */
868 priv->magic_not_rop_nr = 0x06;
870 case 0xce: /* 4/4/0/0, 4 */
871 priv->magic_not_rop_nr = 0x03;
873 case 0xcf: /* 4/0/0/0, 3 */
874 priv->magic_not_rop_nr = 0x03;
878 if (!priv->magic_not_rop_nr) {
879 NV_ERROR(dev, "PGRAPH: unknown config: %d/%d/%d/%d, %d\n",
880 priv->tp_nr[0], priv->tp_nr[1], priv->tp_nr[2],
881 priv->tp_nr[3], priv->rop_nr);
882 /* use 0xc3's values... */
883 priv->magic_not_rop_nr = 0x03;
886 NVOBJ_CLASS(dev, 0x902d, GR); /* 2D */
887 NVOBJ_CLASS(dev, 0x9039, GR); /* M2MF */
888 NVOBJ_MTHD (dev, 0x9039, 0x0500, nvc0_graph_mthd_page_flip);
889 NVOBJ_CLASS(dev, 0x9097, GR); /* 3D */
891 NVOBJ_CLASS(dev, 0x9197, GR); /* 3D (NVC1-) */
893 NVOBJ_CLASS(dev, 0x9297, GR); /* 3D (NVC8-) */
894 NVOBJ_CLASS(dev, 0x90c0, GR); /* COMPUTE */
898 nvc0_graph_destroy(dev, NVOBJ_ENGINE_GR);