2 * Copyright 2010 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include "nouveau_drv.h"
27 #include "nouveau_hw.h"
29 #include "nv50_display.h"
31 static void nv50_gpio_isr(struct drm_device *dev);
32 static void nv50_gpio_isr_bh(struct work_struct *work);
34 struct nv50_gpio_priv {
35 struct list_head handlers;
39 struct nv50_gpio_handler {
40 struct drm_device *dev;
41 struct list_head head;
42 struct work_struct work;
45 struct dcb_gpio_entry *gpio;
47 void (*handler)(void *data, int state);
52 nv50_gpio_location(struct dcb_gpio_entry *gpio, uint32_t *reg, uint32_t *shift)
54 const uint32_t nv50_gpio_reg[4] = { 0xe104, 0xe108, 0xe280, 0xe284 };
59 *reg = nv50_gpio_reg[gpio->line >> 3];
60 *shift = (gpio->line & 7) << 2;
65 nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag)
67 struct dcb_gpio_entry *gpio;
70 gpio = nouveau_bios_gpio_entry(dev, tag);
74 if (nv50_gpio_location(gpio, &r, &s))
77 v = nv_rd32(dev, r) >> (s + 2);
78 return ((v & 1) == (gpio->state[1] & 1));
82 nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state)
84 struct dcb_gpio_entry *gpio;
87 gpio = nouveau_bios_gpio_entry(dev, tag);
91 if (nv50_gpio_location(gpio, &r, &s))
94 v = nv_rd32(dev, r) & ~(0x3 << s);
95 v |= (gpio->state[state] ^ 2) << s;
101 nvd0_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag)
103 struct dcb_gpio_entry *gpio;
106 gpio = nouveau_bios_gpio_entry(dev, tag);
110 v = nv_rd32(dev, 0x00d610 + (gpio->line * 4));
112 return (!!v == (gpio->state[1] & 1));
116 nvd0_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state)
118 struct dcb_gpio_entry *gpio;
121 gpio = nouveau_bios_gpio_entry(dev, tag);
125 v = gpio->state[state] ^ 2;
127 nv_mask(dev, 0x00d610 + (gpio->line * 4), 0x00003000, v << 12);
132 nv50_gpio_irq_register(struct drm_device *dev, enum dcb_gpio_tag tag,
133 void (*handler)(void *, int), void *data)
135 struct drm_nouveau_private *dev_priv = dev->dev_private;
136 struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio;
137 struct nv50_gpio_priv *priv = pgpio->priv;
138 struct nv50_gpio_handler *gpioh;
139 struct dcb_gpio_entry *gpio;
142 gpio = nouveau_bios_gpio_entry(dev, tag);
146 gpioh = kzalloc(sizeof(*gpioh), GFP_KERNEL);
150 INIT_WORK(&gpioh->work, nv50_gpio_isr_bh);
153 gpioh->handler = handler;
156 spin_lock_irqsave(&priv->lock, flags);
157 list_add(&gpioh->head, &priv->handlers);
158 spin_unlock_irqrestore(&priv->lock, flags);
163 nv50_gpio_irq_unregister(struct drm_device *dev, enum dcb_gpio_tag tag,
164 void (*handler)(void *, int), void *data)
166 struct drm_nouveau_private *dev_priv = dev->dev_private;
167 struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio;
168 struct nv50_gpio_priv *priv = pgpio->priv;
169 struct nv50_gpio_handler *gpioh, *tmp;
170 struct dcb_gpio_entry *gpio;
174 gpio = nouveau_bios_gpio_entry(dev, tag);
178 spin_lock_irqsave(&priv->lock, flags);
179 list_for_each_entry_safe(gpioh, tmp, &priv->handlers, head) {
180 if (gpioh->gpio != gpio ||
181 gpioh->handler != handler ||
184 list_move(&gpioh->head, &tofree);
186 spin_unlock_irqrestore(&priv->lock, flags);
188 list_for_each_entry_safe(gpioh, tmp, &tofree, head) {
189 flush_work_sync(&gpioh->work);
195 nv50_gpio_irq_enable(struct drm_device *dev, enum dcb_gpio_tag tag, bool on)
197 struct dcb_gpio_entry *gpio;
200 gpio = nouveau_bios_gpio_entry(dev, tag);
204 reg = gpio->line < 16 ? 0xe050 : 0xe070;
205 mask = 0x00010001 << (gpio->line & 0xf);
207 nv_wr32(dev, reg + 4, mask);
208 reg = nv_mask(dev, reg + 0, mask, on ? mask : 0);
209 return (reg & mask) == mask;
213 nv50_gpio_create(struct drm_device *dev)
215 struct drm_nouveau_private *dev_priv = dev->dev_private;
216 struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio;
217 struct nv50_gpio_priv *priv;
219 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
223 INIT_LIST_HEAD(&priv->handlers);
224 spin_lock_init(&priv->lock);
230 nv50_gpio_destroy(struct drm_device *dev)
232 struct drm_nouveau_private *dev_priv = dev->dev_private;
233 struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio;
240 nv50_gpio_init(struct drm_device *dev)
242 struct drm_nouveau_private *dev_priv = dev->dev_private;
243 struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio;
247 ret = nv50_gpio_create(dev);
252 /* disable, and ack any pending gpio interrupts */
253 nv_wr32(dev, 0xe050, 0x00000000);
254 nv_wr32(dev, 0xe054, 0xffffffff);
255 if (dev_priv->chipset >= 0x90) {
256 nv_wr32(dev, 0xe070, 0x00000000);
257 nv_wr32(dev, 0xe074, 0xffffffff);
260 nouveau_irq_register(dev, 21, nv50_gpio_isr);
265 nv50_gpio_fini(struct drm_device *dev)
267 struct drm_nouveau_private *dev_priv = dev->dev_private;
269 nv_wr32(dev, 0xe050, 0x00000000);
270 if (dev_priv->chipset >= 0x90)
271 nv_wr32(dev, 0xe070, 0x00000000);
272 nouveau_irq_unregister(dev, 21);
274 nv50_gpio_destroy(dev);
278 nv50_gpio_isr_bh(struct work_struct *work)
280 struct nv50_gpio_handler *gpioh =
281 container_of(work, struct nv50_gpio_handler, work);
282 struct drm_nouveau_private *dev_priv = gpioh->dev->dev_private;
283 struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio;
284 struct nv50_gpio_priv *priv = pgpio->priv;
288 state = pgpio->get(gpioh->dev, gpioh->gpio->tag);
292 gpioh->handler(gpioh->data, state);
294 spin_lock_irqsave(&priv->lock, flags);
295 gpioh->inhibit = false;
296 spin_unlock_irqrestore(&priv->lock, flags);
300 nv50_gpio_isr(struct drm_device *dev)
302 struct drm_nouveau_private *dev_priv = dev->dev_private;
303 struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio;
304 struct nv50_gpio_priv *priv = pgpio->priv;
305 struct nv50_gpio_handler *gpioh;
306 u32 intr0, intr1 = 0;
309 intr0 = nv_rd32(dev, 0xe054) & nv_rd32(dev, 0xe050);
310 if (dev_priv->chipset >= 0x90)
311 intr1 = nv_rd32(dev, 0xe074) & nv_rd32(dev, 0xe070);
313 hi = (intr0 & 0x0000ffff) | (intr1 << 16);
314 lo = (intr0 >> 16) | (intr1 & 0xffff0000);
317 nv_wr32(dev, 0xe054, intr0);
318 if (dev_priv->chipset >= 0x90)
319 nv_wr32(dev, 0xe074, intr1);
321 spin_lock(&priv->lock);
322 list_for_each_entry(gpioh, &priv->handlers, head) {
323 if (!(ch & (1 << gpioh->gpio->line)))
328 gpioh->inhibit = true;
330 schedule_work(&gpioh->work);
332 spin_unlock(&priv->lock);