Pileus Git - ~andy/linux/blob - drivers/gpu/drm/nouveau/nv50_display.c

   1 /*
   2  * Copyright (C) 2008 Maarten Maathuis.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial
  15  * portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  21  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  22  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  */
  26
  27 #define NOUVEAU_DMA_DEBUG (nouveau_reg_debug & NOUVEAU_REG_DEBUG_EVO)
  28 #include "nv50_display.h"
  29 #include "nouveau_crtc.h"
  30 #include "nouveau_encoder.h"
  31 #include "nouveau_connector.h"
  32 #include "nouveau_fb.h"
  33 #include "nouveau_fbcon.h"
  34 #include <core/ramht.h>
  35 #include "drm_crtc_helper.h"
  36 #include "nouveau_fence.h"
  37
  38 static void nv50_display_isr(struct drm_device *);
  39 static void nv50_display_bh(unsigned long);
  40
  41 static inline int
  42 nv50_sor_nr(struct drm_device *dev)
  43 {
  44         struct drm_nouveau_private *dev_priv = dev->dev_private;
  45
  46         if (dev_priv->chipset  < 0x90 ||
  47             dev_priv->chipset == 0x92 ||
  48             dev_priv->chipset == 0xa0)
  49                 return 2;
  50
  51         return 4;
  52 }
  53
  54 u32
  55 nv50_display_active_crtcs(struct drm_device *dev)
  56 {
  57         struct drm_nouveau_private *dev_priv = dev->dev_private;
  58         u32 mask = 0;
  59         int i;
  60
  61         if (dev_priv->chipset  < 0x90 ||
  62             dev_priv->chipset == 0x92 ||
  63             dev_priv->chipset == 0xa0) {
  64                 for (i = 0; i < 2; i++)
  65                         mask |= nv_rd32(dev, NV50_PDISPLAY_SOR_MODE_CTRL_C(i));
  66         } else {
  67                 for (i = 0; i < 4; i++)
  68                         mask |= nv_rd32(dev, NV90_PDISPLAY_SOR_MODE_CTRL_C(i));
  69         }
  70
  71         for (i = 0; i < 3; i++)
  72                 mask |= nv_rd32(dev, NV50_PDISPLAY_DAC_MODE_CTRL_C(i));
  73
  74         return mask & 3;
  75 }
  76
  77 int
  78 nv50_display_early_init(struct drm_device *dev)
  79 {
  80         return 0;
  81 }
  82
  83 void
  84 nv50_display_late_takedown(struct drm_device *dev)
  85 {
  86 }
  87
  88 int
  89 nv50_display_sync(struct drm_device *dev)
  90 {
  91         struct nv50_display *disp = nv50_display(dev);
  92         struct nouveau_channel *evo = disp->master;
  93         u64 start;
  94         int ret;
  95
  96         ret = RING_SPACE(evo, 6);
  97         if (ret == 0) {
  98                 BEGIN_NV04(evo, 0, 0x0084, 1);
  99                 OUT_RING  (evo, 0x80000000);
 100                 BEGIN_NV04(evo, 0, 0x0080, 1);
 101                 OUT_RING  (evo, 0);
 102                 BEGIN_NV04(evo, 0, 0x0084, 1);
 103                 OUT_RING  (evo, 0x00000000);
 104
 105                 nv_wo32(disp->ntfy, 0x000, 0x00000000);
 106                 FIRE_RING (evo);
 107
 108                 start = nv_timer_read(dev);
 109                 do {
 110                         if (nv_ro32(disp->ntfy, 0x000))
 111                                 return 0;
 112                 } while (nv_timer_read(dev) - start < 2000000000ULL);
 113         }
 114
 115         return -EBUSY;
 116 }
 117
 118 int
 119 nv50_display_init(struct drm_device *dev)
 120 {
 121         struct nouveau_channel *evo;
 122         int ret, i;
 123         u32 val;
 124
 125         NV_DEBUG_KMS(dev, "\n");
 126
 127         nv_wr32(dev, 0x00610184, nv_rd32(dev, 0x00614004));
 128
 129         /*
 130          * I think the 0x006101XX range is some kind of main control area
 131          * that enables things.
 132          */
 133         /* CRTC? */
 134         for (i = 0; i < 2; i++) {
 135                 val = nv_rd32(dev, 0x00616100 + (i * 0x800));
 136                 nv_wr32(dev, 0x00610190 + (i * 0x10), val);
 137                 val = nv_rd32(dev, 0x00616104 + (i * 0x800));
 138                 nv_wr32(dev, 0x00610194 + (i * 0x10), val);
 139                 val = nv_rd32(dev, 0x00616108 + (i * 0x800));
 140                 nv_wr32(dev, 0x00610198 + (i * 0x10), val);
 141                 val = nv_rd32(dev, 0x0061610c + (i * 0x800));
 142                 nv_wr32(dev, 0x0061019c + (i * 0x10), val);
 143         }
 144
 145         /* DAC */
 146         for (i = 0; i < 3; i++) {
 147                 val = nv_rd32(dev, 0x0061a000 + (i * 0x800));
 148                 nv_wr32(dev, 0x006101d0 + (i * 0x04), val);
 149         }
 150
 151         /* SOR */
 152         for (i = 0; i < nv50_sor_nr(dev); i++) {
 153                 val = nv_rd32(dev, 0x0061c000 + (i * 0x800));
 154                 nv_wr32(dev, 0x006101e0 + (i * 0x04), val);
 155         }
 156
 157         /* EXT */
 158         for (i = 0; i < 3; i++) {
 159                 val = nv_rd32(dev, 0x0061e000 + (i * 0x800));
 160                 nv_wr32(dev, 0x006101f0 + (i * 0x04), val);
 161         }
 162
 163         for (i = 0; i < 3; i++) {
 164                 nv_wr32(dev, NV50_PDISPLAY_DAC_DPMS_CTRL(i), 0x00550000 |
 165                         NV50_PDISPLAY_DAC_DPMS_CTRL_PENDING);
 166                 nv_wr32(dev, NV50_PDISPLAY_DAC_CLK_CTRL1(i), 0x00000001);
 167         }
 168
 169         /* The precise purpose is unknown, i suspect it has something to do
 170          * with text mode.
 171          */
 172         if (nv_rd32(dev, NV50_PDISPLAY_INTR_1) & 0x100) {
 173                 nv_wr32(dev, NV50_PDISPLAY_INTR_1, 0x100);
 174                 nv_wr32(dev, 0x006194e8, nv_rd32(dev, 0x006194e8) & ~1);
 175                 if (!nv_wait(dev, 0x006194e8, 2, 0)) {
 176                         NV_ERROR(dev, "timeout: (0x6194e8 & 2) != 0\n");
 177                         NV_ERROR(dev, "0x6194e8 = 0x%08x\n",
 178                                                 nv_rd32(dev, 0x6194e8));
 179                         return -EBUSY;
 180                 }
 181         }
 182
 183         for (i = 0; i < 2; i++) {
 184                 nv_wr32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i), 0x2000);
 185                 if (!nv_wait(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
 186                              NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS, 0)) {
 187                         NV_ERROR(dev, "timeout: CURSOR_CTRL2_STATUS == 0\n");
 188                         NV_ERROR(dev, "CURSOR_CTRL2 = 0x%08x\n",
 189                                  nv_rd32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i)));
 190                         return -EBUSY;
 191                 }
 192
 193                 nv_wr32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
 194                         NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_ON);
 195                 if (!nv_wait(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
 196                              NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS,
 197                              NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS_ACTIVE)) {
 198                         NV_ERROR(dev, "timeout: "
 199                                       "CURSOR_CTRL2_STATUS_ACTIVE(%d)\n", i);
 200                         NV_ERROR(dev, "CURSOR_CTRL2(%d) = 0x%08x\n", i,
 201                                  nv_rd32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i)));
 202                         return -EBUSY;
 203                 }
 204         }
 205
 206         nv_wr32(dev, NV50_PDISPLAY_PIO_CTRL, 0x00000000);
 207         nv_mask(dev, NV50_PDISPLAY_INTR_0, 0x00000000, 0x00000000);
 208         nv_wr32(dev, NV50_PDISPLAY_INTR_EN_0, 0x00000000);
 209         nv_mask(dev, NV50_PDISPLAY_INTR_1, 0x00000000, 0x00000000);
 210         nv_wr32(dev, NV50_PDISPLAY_INTR_EN_1,
 211                      NV50_PDISPLAY_INTR_EN_1_CLK_UNK10 |
 212                      NV50_PDISPLAY_INTR_EN_1_CLK_UNK20 |
 213                      NV50_PDISPLAY_INTR_EN_1_CLK_UNK40);
 214
 215         ret = nv50_evo_init(dev);
 216         if (ret)
 217                 return ret;
 218         evo = nv50_display(dev)->master;
 219
 220         nv_wr32(dev, NV50_PDISPLAY_OBJECTS, (evo->ramin->addr >> 8) | 9);
 221
 222         ret = RING_SPACE(evo, 3);
 223         if (ret)
 224                 return ret;
 225         BEGIN_NV04(evo, 0, NV50_EVO_UNK84, 2);
 226         OUT_RING  (evo, NV50_EVO_UNK84_NOTIFY_DISABLED);
 227         OUT_RING  (evo, NvEvoSync);
 228
 229         return nv50_display_sync(dev);
 230 }
 231
 232 void
 233 nv50_display_fini(struct drm_device *dev)
 234 {
 235         struct nv50_display *disp = nv50_display(dev);
 236         struct nouveau_channel *evo = disp->master;
 237         struct drm_crtc *drm_crtc;
 238         int ret, i;
 239
 240         NV_DEBUG_KMS(dev, "\n");
 241
 242         list_for_each_entry(drm_crtc, &dev->mode_config.crtc_list, head) {
 243                 struct nouveau_crtc *crtc = nouveau_crtc(drm_crtc);
 244
 245                 nv50_crtc_blank(crtc, true);
 246         }
 247
 248         ret = RING_SPACE(evo, 2);
 249         if (ret == 0) {
 250                 BEGIN_NV04(evo, 0, NV50_EVO_UPDATE, 1);
 251                 OUT_RING(evo, 0);
 252         }
 253         FIRE_RING(evo);
 254
 255         /* Almost like ack'ing a vblank interrupt, maybe in the spirit of
 256          * cleaning up?
 257          */
 258         list_for_each_entry(drm_crtc, &dev->mode_config.crtc_list, head) {
 259                 struct nouveau_crtc *crtc = nouveau_crtc(drm_crtc);
 260                 uint32_t mask = NV50_PDISPLAY_INTR_1_VBLANK_CRTC_(crtc->index);
 261
 262                 if (!crtc->base.enabled)
 263                         continue;
 264
 265                 nv_wr32(dev, NV50_PDISPLAY_INTR_1, mask);
 266                 if (!nv_wait(dev, NV50_PDISPLAY_INTR_1, mask, mask)) {
 267                         NV_ERROR(dev, "timeout: (0x610024 & 0x%08x) == "
 268                                       "0x%08x\n", mask, mask);
 269                         NV_ERROR(dev, "0x610024 = 0x%08x\n",
 270                                  nv_rd32(dev, NV50_PDISPLAY_INTR_1));
 271                 }
 272         }
 273
 274         for (i = 0; i < 2; i++) {
 275                 nv_wr32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i), 0);
 276                 if (!nv_wait(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
 277                              NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS, 0)) {
 278                         NV_ERROR(dev, "timeout: CURSOR_CTRL2_STATUS == 0\n");
 279                         NV_ERROR(dev, "CURSOR_CTRL2 = 0x%08x\n",
 280                                  nv_rd32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i)));
 281                 }
 282         }
 283
 284         nv50_evo_fini(dev);
 285
 286         for (i = 0; i < 3; i++) {
 287                 if (!nv_wait(dev, NV50_PDISPLAY_SOR_DPMS_STATE(i),
 288                              NV50_PDISPLAY_SOR_DPMS_STATE_WAIT, 0)) {
 289                         NV_ERROR(dev, "timeout: SOR_DPMS_STATE_WAIT(%d) == 0\n", i);
 290                         NV_ERROR(dev, "SOR_DPMS_STATE(%d) = 0x%08x\n", i,
 291                                   nv_rd32(dev, NV50_PDISPLAY_SOR_DPMS_STATE(i)));
 292                 }
 293         }
 294
 295         /* disable interrupts. */
 296         nv_wr32(dev, NV50_PDISPLAY_INTR_EN_1, 0x00000000);
 297 }
 298
 299 int
 300 nv50_display_create(struct drm_device *dev)
 301 {
 302         struct drm_nouveau_private *dev_priv = dev->dev_private;
 303         struct dcb_table *dcb = &dev_priv->vbios.dcb;
 304         struct drm_connector *connector, *ct;
 305         struct nv50_display *priv;
 306         int ret, i;
 307
 308         NV_DEBUG_KMS(dev, "\n");
 309
 310         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 311         if (!priv)
 312                 return -ENOMEM;
 313         dev_priv->engine.display.priv = priv;
 314
 315         /* Create CRTC objects */
 316         for (i = 0; i < 2; i++) {
 317                 ret = nv50_crtc_create(dev, i);
 318                 if (ret)
 319                         return ret;
 320         }
 321
 322         /* We setup the encoders from the BIOS table */
 323         for (i = 0 ; i < dcb->entries; i++) {
 324                 struct dcb_output *entry = &dcb->entry[i];
 325
 326                 if (entry->location != DCB_LOC_ON_CHIP) {
 327                         NV_WARN(dev, "Off-chip encoder %d/%d unsupported\n",
 328                                 entry->type, ffs(entry->or) - 1);
 329                         continue;
 330                 }
 331
 332                 connector = nouveau_connector_create(dev, entry->connector);
 333                 if (IS_ERR(connector))
 334                         continue;
 335
 336                 switch (entry->type) {
 337                 case DCB_OUTPUT_TMDS:
 338                 case DCB_OUTPUT_LVDS:
 339                 case DCB_OUTPUT_DP:
 340                         nv50_sor_create(connector, entry);
 341                         break;
 342                 case DCB_OUTPUT_ANALOG:
 343                         nv50_dac_create(connector, entry);
 344                         break;
 345                 default:
 346                         NV_WARN(dev, "DCB encoder %d unknown\n", entry->type);
 347                         continue;
 348                 }
 349         }
 350
 351         list_for_each_entry_safe(connector, ct,
 352                                  &dev->mode_config.connector_list, head) {
 353                 if (!connector->encoder_ids[0]) {
 354                         NV_WARN(dev, "%s has no encoders, removing\n",
 355                                 drm_get_connector_name(connector));
 356                         connector->funcs->destroy(connector);
 357                 }
 358         }
 359
 360         tasklet_init(&priv->tasklet, nv50_display_bh, (unsigned long)dev);
 361         nouveau_irq_register(dev, 26, nv50_display_isr);
 362
 363         ret = nv50_evo_create(dev);
 364         if (ret) {
 365                 nv50_display_destroy(dev);
 366                 return ret;
 367         }
 368
 369         return 0;
 370 }
 371
 372 void
 373 nv50_display_destroy(struct drm_device *dev)
 374 {
 375         struct nv50_display *disp = nv50_display(dev);
 376
 377         NV_DEBUG_KMS(dev, "\n");
 378
 379         nv50_evo_destroy(dev);
 380         nouveau_irq_unregister(dev, 26);
 381         kfree(disp);
 382 }
 383
 384 void
 385 nv50_display_flip_stop(struct drm_crtc *crtc)
 386 {
 387         struct nv50_display *disp = nv50_display(crtc->dev);
 388         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 389         struct nv50_display_crtc *dispc = &disp->crtc[nv_crtc->index];
 390         struct nouveau_channel *evo = dispc->sync;
 391         int ret;
 392
 393         ret = RING_SPACE(evo, 8);
 394         if (ret) {
 395                 WARN_ON(1);
 396                 return;
 397         }
 398
 399         BEGIN_NV04(evo, 0, 0x0084, 1);
 400         OUT_RING  (evo, 0x00000000);
 401         BEGIN_NV04(evo, 0, 0x0094, 1);
 402         OUT_RING  (evo, 0x00000000);
 403         BEGIN_NV04(evo, 0, 0x00c0, 1);
 404         OUT_RING  (evo, 0x00000000);
 405         BEGIN_NV04(evo, 0, 0x0080, 1);
 406         OUT_RING  (evo, 0x00000000);
 407         FIRE_RING (evo);
 408 }
 409
 410 int
 411 nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb,
 412                        struct nouveau_channel *chan)
 413 {
 414         struct drm_nouveau_private *dev_priv = crtc->dev->dev_private;
 415         struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb);
 416         struct nv50_display *disp = nv50_display(crtc->dev);
 417         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 418         struct nv50_display_crtc *dispc = &disp->crtc[nv_crtc->index];
 419         struct nouveau_channel *evo = dispc->sync;
 420         int ret;
 421
 422         ret = RING_SPACE(evo, chan ? 25 : 27);
 423         if (unlikely(ret))
 424                 return ret;
 425
 426         /* synchronise with the rendering channel, if necessary */
 427         if (likely(chan)) {
 428                 ret = RING_SPACE(chan, 10);
 429                 if (ret) {
 430                         WIND_RING(evo);
 431                         return ret;
 432                 }
 433
 434                 if (dev_priv->chipset < 0xc0) {
 435                         BEGIN_NV04(chan, 0, 0x0060, 2);
 436                         OUT_RING  (chan, NvEvoSema0 + nv_crtc->index);
 437                         OUT_RING  (chan, dispc->sem.offset);
 438                         BEGIN_NV04(chan, 0, 0x006c, 1);
 439                         OUT_RING  (chan, 0xf00d0000 | dispc->sem.value);
 440                         BEGIN_NV04(chan, 0, 0x0064, 2);
 441                         OUT_RING  (chan, dispc->sem.offset ^ 0x10);
 442                         OUT_RING  (chan, 0x74b1e000);
 443                         BEGIN_NV04(chan, 0, 0x0060, 1);
 444                         if (dev_priv->chipset < 0x84)
 445                                 OUT_RING  (chan, NvSema);
 446                         else
 447                                 OUT_RING  (chan, chan->vram_handle);
 448                 } else {
 449                         u64 offset = nvc0_fence_crtc(chan, nv_crtc->index);
 450                         offset += dispc->sem.offset;
 451                         BEGIN_NVC0(chan, 0, 0x0010, 4);
 452                         OUT_RING  (chan, upper_32_bits(offset));
 453                         OUT_RING  (chan, lower_32_bits(offset));
 454                         OUT_RING  (chan, 0xf00d0000 | dispc->sem.value);
 455                         OUT_RING  (chan, 0x1002);
 456                         BEGIN_NVC0(chan, 0, 0x0010, 4);
 457                         OUT_RING  (chan, upper_32_bits(offset));
 458                         OUT_RING  (chan, lower_32_bits(offset ^ 0x10));
 459                         OUT_RING  (chan, 0x74b1e000);
 460                         OUT_RING  (chan, 0x1001);
 461                 }
 462                 FIRE_RING (chan);
 463         } else {
 464                 nouveau_bo_wr32(dispc->sem.bo, dispc->sem.offset / 4,
 465                                 0xf00d0000 | dispc->sem.value);
 466         }
 467
 468         /* queue the flip on the crtc's "display sync" channel */
 469         BEGIN_NV04(evo, 0, 0x0100, 1);
 470         OUT_RING  (evo, 0xfffe0000);
 471         if (chan) {
 472                 BEGIN_NV04(evo, 0, 0x0084, 1);
 473                 OUT_RING  (evo, 0x00000100);
 474         } else {
 475                 BEGIN_NV04(evo, 0, 0x0084, 1);
 476                 OUT_RING  (evo, 0x00000010);
 477                 /* allows gamma somehow, PDISP will bitch at you if
 478                  * you don't wait for vblank before changing this..
 479                  */
 480                 BEGIN_NV04(evo, 0, 0x00e0, 1);
 481                 OUT_RING  (evo, 0x40000000);
 482         }
 483         BEGIN_NV04(evo, 0, 0x0088, 4);
 484         OUT_RING  (evo, dispc->sem.offset);
 485         OUT_RING  (evo, 0xf00d0000 | dispc->sem.value);
 486         OUT_RING  (evo, 0x74b1e000);
 487         OUT_RING  (evo, NvEvoSync);
 488         BEGIN_NV04(evo, 0, 0x00a0, 2);
 489         OUT_RING  (evo, 0x00000000);
 490         OUT_RING  (evo, 0x00000000);
 491         BEGIN_NV04(evo, 0, 0x00c0, 1);
 492         OUT_RING  (evo, nv_fb->r_dma);
 493         BEGIN_NV04(evo, 0, 0x0110, 2);
 494         OUT_RING  (evo, 0x00000000);
 495         OUT_RING  (evo, 0x00000000);
 496         BEGIN_NV04(evo, 0, 0x0800, 5);
 497         OUT_RING  (evo, nv_fb->nvbo->bo.offset >> 8);
 498         OUT_RING  (evo, 0);
 499         OUT_RING  (evo, (fb->height << 16) | fb->width);
 500         OUT_RING  (evo, nv_fb->r_pitch);
 501         OUT_RING  (evo, nv_fb->r_format);
 502         BEGIN_NV04(evo, 0, 0x0080, 1);
 503         OUT_RING  (evo, 0x00000000);
 504         FIRE_RING (evo);
 505
 506         dispc->sem.offset ^= 0x10;
 507         dispc->sem.value++;
 508         return 0;
 509 }
 510
 511 static u16
 512 nv50_display_script_select(struct drm_device *dev, struct dcb_output *dcb,
 513                            u32 mc, int pxclk)
 514 {
 515         struct drm_nouveau_private *dev_priv = dev->dev_private;
 516         struct nouveau_connector *nv_connector = NULL;
 517         struct drm_encoder *encoder;
 518         struct nvbios *bios = &dev_priv->vbios;
 519         u32 script = 0, or;
 520
 521         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 522                 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 523
 524                 if (nv_encoder->dcb != dcb)
 525                         continue;
 526
 527                 nv_connector = nouveau_encoder_connector_get(nv_encoder);
 528                 break;
 529         }
 530
 531         or = ffs(dcb->or) - 1;
 532         switch (dcb->type) {
 533         case DCB_OUTPUT_LVDS:
 534                 script = (mc >> 8) & 0xf;
 535                 if (bios->fp_no_ddc) {
 536                         if (bios->fp.dual_link)
 537                                 script |= 0x0100;
 538                         if (bios->fp.if_is_24bit)
 539                                 script |= 0x0200;
 540                 } else {
 541                         /* determine number of lvds links */
 542                         if (nv_connector && nv_connector->edid &&
 543                             nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
 544                                 /* http://www.spwg.org */
 545                                 if (((u8 *)nv_connector->edid)[121] == 2)
 546                                         script |= 0x0100;
 547                         } else
 548                         if (pxclk >= bios->fp.duallink_transition_clk) {
 549                                 script |= 0x0100;
 550                         }
 551
 552                         /* determine panel depth */
 553                         if (script & 0x0100) {
 554                                 if (bios->fp.strapless_is_24bit & 2)
 555                                         script |= 0x0200;
 556                         } else {
 557                                 if (bios->fp.strapless_is_24bit & 1)
 558                                         script |= 0x0200;
 559                         }
 560
 561                         if (nv_connector && nv_connector->edid &&
 562                             (nv_connector->edid->revision >= 4) &&
 563                             (nv_connector->edid->input & 0x70) >= 0x20)
 564                                 script |= 0x0200;
 565                 }
 566
 567                 if (nouveau_uscript_lvds >= 0) {
 568                         NV_INFO(dev, "override script 0x%04x with 0x%04x "
 569                                      "for output LVDS-%d\n", script,
 570                                      nouveau_uscript_lvds, or);
 571                         script = nouveau_uscript_lvds;
 572                 }
 573                 break;
 574         case DCB_OUTPUT_TMDS:
 575                 script = (mc >> 8) & 0xf;
 576                 if (pxclk >= 165000)
 577                         script |= 0x0100;
 578
 579                 if (nouveau_uscript_tmds >= 0) {
 580                         NV_INFO(dev, "override script 0x%04x with 0x%04x "
 581                                      "for output TMDS-%d\n", script,
 582                                      nouveau_uscript_tmds, or);
 583                         script = nouveau_uscript_tmds;
 584                 }
 585                 break;
 586         case DCB_OUTPUT_DP:
 587                 script = (mc >> 8) & 0xf;
 588                 break;
 589         case DCB_OUTPUT_ANALOG:
 590                 script = 0xff;
 591                 break;
 592         default:
 593                 NV_ERROR(dev, "modeset on unsupported output type!\n");
 594                 break;
 595         }
 596
 597         return script;
 598 }
 599
 600 static void
 601 nv50_display_vblank_crtc_handler(struct drm_device *dev, int crtc)
 602 {
 603         struct drm_nouveau_private *dev_priv = dev->dev_private;
 604         struct nouveau_software_priv *psw = nv_engine(dev, NVOBJ_ENGINE_SW);
 605         struct nouveau_software_chan *pch, *tmp;
 606
 607         list_for_each_entry_safe(pch, tmp, &psw->vblank, vblank.list) {
 608                 if (pch->vblank.head != crtc)
 609                         continue;
 610
 611                 spin_lock(&psw->peephole_lock);
 612                 nv_wr32(dev, 0x001704, pch->vblank.channel);
 613                 nv_wr32(dev, 0x001710, 0x80000000 | pch->vblank.ctxdma);
 614                 if (dev_priv->chipset == 0x50) {
 615                         nv_wr32(dev, 0x001570, pch->vblank.offset);
 616                         nv_wr32(dev, 0x001574, pch->vblank.value);
 617                 } else {
 618                         nv_wr32(dev, 0x060010, pch->vblank.offset);
 619                         nv_wr32(dev, 0x060014, pch->vblank.value);
 620                 }
 621                 spin_unlock(&psw->peephole_lock);
 622
 623                 list_del(&pch->vblank.list);
 624                 drm_vblank_put(dev, crtc);
 625         }
 626
 627         drm_handle_vblank(dev, crtc);
 628 }
 629
 630 static void
 631 nv50_display_vblank_handler(struct drm_device *dev, uint32_t intr)
 632 {
 633         if (intr & NV50_PDISPLAY_INTR_1_VBLANK_CRTC_0)
 634                 nv50_display_vblank_crtc_handler(dev, 0);
 635
 636         if (intr & NV50_PDISPLAY_INTR_1_VBLANK_CRTC_1)
 637                 nv50_display_vblank_crtc_handler(dev, 1);
 638
 639         nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_VBLANK_CRTC);
 640 }
 641
 642 static void
 643 nv50_display_unk10_handler(struct drm_device *dev)
 644 {
 645         struct drm_nouveau_private *dev_priv = dev->dev_private;
 646         struct nv50_display *disp = nv50_display(dev);
 647         u32 unk30 = nv_rd32(dev, 0x610030), mc;
 648         int i, crtc, or = 0, type = DCB_OUTPUT_ANY;
 649
 650         NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
 651         disp->irq.dcb = NULL;
 652
 653         nv_wr32(dev, 0x619494, nv_rd32(dev, 0x619494) & ~8);
 654
 655         /* Determine which CRTC we're dealing with, only 1 ever will be
 656          * signalled at the same time with the current nouveau code.
 657          */
 658         crtc = ffs((unk30 & 0x00000060) >> 5) - 1;
 659         if (crtc < 0)
 660                 goto ack;
 661
 662         /* Nothing needs to be done for the encoder */
 663         crtc = ffs((unk30 & 0x00000180) >> 7) - 1;
 664         if (crtc < 0)
 665                 goto ack;
 666
 667         /* Find which encoder was connected to the CRTC */
 668         for (i = 0; type == DCB_OUTPUT_ANY && i < 3; i++) {
 669                 mc = nv_rd32(dev, NV50_PDISPLAY_DAC_MODE_CTRL_C(i));
 670                 NV_DEBUG_KMS(dev, "DAC-%d mc: 0x%08x\n", i, mc);
 671                 if (!(mc & (1 << crtc)))
 672                         continue;
 673
 674                 switch ((mc & 0x00000f00) >> 8) {
 675                 case 0: type = DCB_OUTPUT_ANALOG; break;
 676                 case 1: type = DCB_OUTPUT_TV; break;
 677                 default:
 678                         NV_ERROR(dev, "invalid mc, DAC-%d: 0x%08x\n", i, mc);
 679                         goto ack;
 680                 }
 681
 682                 or = i;
 683         }
 684
 685         for (i = 0; type == DCB_OUTPUT_ANY && i < nv50_sor_nr(dev); i++) {
 686                 if (dev_priv->chipset  < 0x90 ||
 687                     dev_priv->chipset == 0x92 ||
 688                     dev_priv->chipset == 0xa0)
 689                         mc = nv_rd32(dev, NV50_PDISPLAY_SOR_MODE_CTRL_C(i));
 690                 else
 691                         mc = nv_rd32(dev, NV90_PDISPLAY_SOR_MODE_CTRL_C(i));
 692
 693                 NV_DEBUG_KMS(dev, "SOR-%d mc: 0x%08x\n", i, mc);
 694                 if (!(mc & (1 << crtc)))
 695                         continue;
 696
 697                 switch ((mc & 0x00000f00) >> 8) {
 698                 case 0: type = DCB_OUTPUT_LVDS; break;
 699                 case 1: type = DCB_OUTPUT_TMDS; break;
 700                 case 2: type = DCB_OUTPUT_TMDS; break;
 701                 case 5: type = DCB_OUTPUT_TMDS; break;
 702                 case 8: type = DCB_OUTPUT_DP; break;
 703                 case 9: type = DCB_OUTPUT_DP; break;
 704                 default:
 705                         NV_ERROR(dev, "invalid mc, SOR-%d: 0x%08x\n", i, mc);
 706                         goto ack;
 707                 }
 708
 709                 or = i;
 710         }
 711
 712         /* There was no encoder to disable */
 713         if (type == DCB_OUTPUT_ANY)
 714                 goto ack;
 715
 716         /* Disable the encoder */
 717         for (i = 0; i < dev_priv->vbios.dcb.entries; i++) {
 718                 struct dcb_output *dcb = &dev_priv->vbios.dcb.entry[i];
 719
 720                 if (dcb->type == type && (dcb->or & (1 << or))) {
 721                         nouveau_bios_run_display_table(dev, 0, -1, dcb, -1);
 722                         disp->irq.dcb = dcb;
 723                         goto ack;
 724                 }
 725         }
 726
 727         NV_ERROR(dev, "no dcb for %d %d 0x%08x\n", or, type, mc);
 728 ack:
 729         nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK10);
 730         nv_wr32(dev, 0x610030, 0x80000000);
 731 }
 732
 733 static void
 734 nv50_display_unk20_handler(struct drm_device *dev)
 735 {
 736         struct drm_nouveau_private *dev_priv = dev->dev_private;
 737         struct nv50_display *disp = nv50_display(dev);
 738         u32 unk30 = nv_rd32(dev, 0x610030), tmp, pclk, script, mc = 0;
 739         struct dcb_output *dcb;
 740         int i, crtc, or = 0, type = DCB_OUTPUT_ANY;
 741
 742         NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
 743         dcb = disp->irq.dcb;
 744         if (dcb) {
 745                 nouveau_bios_run_display_table(dev, 0, -2, dcb, -1);
 746                 disp->irq.dcb = NULL;
 747         }
 748
 749         /* CRTC clock change requested? */
 750         crtc = ffs((unk30 & 0x00000600) >> 9) - 1;
 751         if (crtc >= 0) {
 752                 pclk  = nv_rd32(dev, NV50_PDISPLAY_CRTC_P(crtc, CLOCK));
 753                 pclk &= 0x003fffff;
 754                 if (pclk)
 755                         nv50_crtc_set_clock(dev, crtc, pclk);
 756
 757                 tmp = nv_rd32(dev, NV50_PDISPLAY_CRTC_CLK_CTRL2(crtc));
 758                 tmp &= ~0x000000f;
 759                 nv_wr32(dev, NV50_PDISPLAY_CRTC_CLK_CTRL2(crtc), tmp);
 760         }
 761
 762         /* Nothing needs to be done for the encoder */
 763         crtc = ffs((unk30 & 0x00000180) >> 7) - 1;
 764         if (crtc < 0)
 765                 goto ack;
 766         pclk  = nv_rd32(dev, NV50_PDISPLAY_CRTC_P(crtc, CLOCK)) & 0x003fffff;
 767
 768         /* Find which encoder is connected to the CRTC */
 769         for (i = 0; type == DCB_OUTPUT_ANY && i < 3; i++) {
 770                 mc = nv_rd32(dev, NV50_PDISPLAY_DAC_MODE_CTRL_P(i));
 771                 NV_DEBUG_KMS(dev, "DAC-%d mc: 0x%08x\n", i, mc);
 772                 if (!(mc & (1 << crtc)))
 773                         continue;
 774
 775                 switch ((mc & 0x00000f00) >> 8) {
 776                 case 0: type = DCB_OUTPUT_ANALOG; break;
 777                 case 1: type = DCB_OUTPUT_TV; break;
 778                 default:
 779                         NV_ERROR(dev, "invalid mc, DAC-%d: 0x%08x\n", i, mc);
 780                         goto ack;
 781                 }
 782
 783                 or = i;
 784         }
 785
 786         for (i = 0; type == DCB_OUTPUT_ANY && i < nv50_sor_nr(dev); i++) {
 787                 if (dev_priv->chipset  < 0x90 ||
 788                     dev_priv->chipset == 0x92 ||
 789                     dev_priv->chipset == 0xa0)
 790                         mc = nv_rd32(dev, NV50_PDISPLAY_SOR_MODE_CTRL_P(i));
 791                 else
 792                         mc = nv_rd32(dev, NV90_PDISPLAY_SOR_MODE_CTRL_P(i));
 793
 794                 NV_DEBUG_KMS(dev, "SOR-%d mc: 0x%08x\n", i, mc);
 795                 if (!(mc & (1 << crtc)))
 796                         continue;
 797
 798                 switch ((mc & 0x00000f00) >> 8) {
 799                 case 0: type = DCB_OUTPUT_LVDS; break;
 800                 case 1: type = DCB_OUTPUT_TMDS; break;
 801                 case 2: type = DCB_OUTPUT_TMDS; break;
 802                 case 5: type = DCB_OUTPUT_TMDS; break;
 803                 case 8: type = DCB_OUTPUT_DP; break;
 804                 case 9: type = DCB_OUTPUT_DP; break;
 805                 default:
 806                         NV_ERROR(dev, "invalid mc, SOR-%d: 0x%08x\n", i, mc);
 807                         goto ack;
 808                 }
 809
 810                 or = i;
 811         }
 812
 813         if (type == DCB_OUTPUT_ANY)
 814                 goto ack;
 815
 816         /* Enable the encoder */
 817         for (i = 0; i < dev_priv->vbios.dcb.entries; i++) {
 818                 dcb = &dev_priv->vbios.dcb.entry[i];
 819                 if (dcb->type == type && (dcb->or & (1 << or)))
 820                         break;
 821         }
 822
 823         if (i == dev_priv->vbios.dcb.entries) {
 824                 NV_ERROR(dev, "no dcb for %d %d 0x%08x\n", or, type, mc);
 825                 goto ack;
 826         }
 827
 828         script = nv50_display_script_select(dev, dcb, mc, pclk);
 829         nouveau_bios_run_display_table(dev, script, pclk, dcb, -1);
 830
 831         if (type == DCB_OUTPUT_DP) {
 832                 int link = !(dcb->dpconf.sor.link & 1);
 833                 if ((mc & 0x000f0000) == 0x00020000)
 834                         nv50_sor_dp_calc_tu(dev, or, link, pclk, 18);
 835                 else
 836                         nv50_sor_dp_calc_tu(dev, or, link, pclk, 24);
 837         }
 838
 839         if (dcb->type != DCB_OUTPUT_ANALOG) {
 840                 tmp = nv_rd32(dev, NV50_PDISPLAY_SOR_CLK_CTRL2(or));
 841                 tmp &= ~0x00000f0f;
 842                 if (script & 0x0100)
 843                         tmp |= 0x00000101;
 844                 nv_wr32(dev, NV50_PDISPLAY_SOR_CLK_CTRL2(or), tmp);
 845         } else {
 846                 nv_wr32(dev, NV50_PDISPLAY_DAC_CLK_CTRL2(or), 0);
 847         }
 848
 849         disp->irq.dcb = dcb;
 850         disp->irq.pclk = pclk;
 851         disp->irq.script = script;
 852
 853 ack:
 854         nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK20);
 855         nv_wr32(dev, 0x610030, 0x80000000);
 856 }
 857
 858 /* If programming a TMDS output on a SOR that can also be configured for
 859  * DisplayPort, make sure NV50_SOR_DP_CTRL_ENABLE is forced off.
 860  *
 861  * It looks like the VBIOS TMDS scripts make an attempt at this, however,
 862  * the VBIOS scripts on at least one board I have only switch it off on
 863  * link 0, causing a blank display if the output has previously been
 864  * programmed for DisplayPort.
 865  */
 866 static void
 867 nv50_display_unk40_dp_set_tmds(struct drm_device *dev, struct dcb_output *dcb)
 868 {
 869         int or = ffs(dcb->or) - 1, link = !(dcb->dpconf.sor.link & 1);
 870         struct drm_encoder *encoder;
 871         u32 tmp;
 872
 873         if (dcb->type != DCB_OUTPUT_TMDS)
 874                 return;
 875
 876         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 877                 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 878
 879                 if (nv_encoder->dcb->type == DCB_OUTPUT_DP &&
 880                     nv_encoder->dcb->or & (1 << or)) {
 881                         tmp  = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link));
 882                         tmp &= ~NV50_SOR_DP_CTRL_ENABLED;
 883                         nv_wr32(dev, NV50_SOR_DP_CTRL(or, link), tmp);
 884                         break;
 885                 }
 886         }
 887 }
 888
 889 static void
 890 nv50_display_unk40_handler(struct drm_device *dev)
 891 {
 892         struct nv50_display *disp = nv50_display(dev);
 893         struct dcb_output *dcb = disp->irq.dcb;
 894         u16 script = disp->irq.script;
 895         u32 unk30 = nv_rd32(dev, 0x610030), pclk = disp->irq.pclk;
 896
 897         NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
 898         disp->irq.dcb = NULL;
 899         if (!dcb)
 900                 goto ack;
 901
 902         nouveau_bios_run_display_table(dev, script, -pclk, dcb, -1);
 903         nv50_display_unk40_dp_set_tmds(dev, dcb);
 904
 905 ack:
 906         nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK40);
 907         nv_wr32(dev, 0x610030, 0x80000000);
 908         nv_wr32(dev, 0x619494, nv_rd32(dev, 0x619494) | 8);
 909 }
 910
 911 static void
 912 nv50_display_bh(unsigned long data)
 913 {
 914         struct drm_device *dev = (struct drm_device *)data;
 915
 916         for (;;) {
 917                 uint32_t intr0 = nv_rd32(dev, NV50_PDISPLAY_INTR_0);
 918                 uint32_t intr1 = nv_rd32(dev, NV50_PDISPLAY_INTR_1);
 919
 920                 NV_DEBUG_KMS(dev, "PDISPLAY_INTR_BH 0x%08x 0x%08x\n", intr0, intr1);
 921
 922                 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK10)
 923                         nv50_display_unk10_handler(dev);
 924                 else
 925                 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK20)
 926                         nv50_display_unk20_handler(dev);
 927                 else
 928                 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK40)
 929                         nv50_display_unk40_handler(dev);
 930                 else
 931                         break;
 932         }
 933
 934         nv_wr32(dev, NV03_PMC_INTR_EN_0, 1);
 935 }
 936
 937 static void
 938 nv50_display_error_handler(struct drm_device *dev)
 939 {
 940         u32 channels = (nv_rd32(dev, NV50_PDISPLAY_INTR_0) & 0x001f0000) >> 16;
 941         u32 addr, data;
 942         int chid;
 943
 944         for (chid = 0; chid < 5; chid++) {
 945                 if (!(channels & (1 << chid)))
 946                         continue;
 947
 948                 nv_wr32(dev, NV50_PDISPLAY_INTR_0, 0x00010000 << chid);
 949                 addr = nv_rd32(dev, NV50_PDISPLAY_TRAPPED_ADDR(chid));
 950                 data = nv_rd32(dev, NV50_PDISPLAY_TRAPPED_DATA(chid));
 951                 NV_ERROR(dev, "EvoCh %d Mthd 0x%04x Data 0x%08x "
 952                               "(0x%04x 0x%02x)\n", chid,
 953                          addr & 0xffc, data, addr >> 16, (addr >> 12) & 0xf);
 954
 955                 nv_wr32(dev, NV50_PDISPLAY_TRAPPED_ADDR(chid), 0x90000000);
 956         }
 957 }
 958
 959 static void
 960 nv50_display_isr(struct drm_device *dev)
 961 {
 962         struct nv50_display *disp = nv50_display(dev);
 963         uint32_t delayed = 0;
 964
 965         while (nv_rd32(dev, NV50_PMC_INTR_0) & NV50_PMC_INTR_0_DISPLAY) {
 966                 uint32_t intr0 = nv_rd32(dev, NV50_PDISPLAY_INTR_0);
 967                 uint32_t intr1 = nv_rd32(dev, NV50_PDISPLAY_INTR_1);
 968                 uint32_t clock;
 969
 970                 NV_DEBUG_KMS(dev, "PDISPLAY_INTR 0x%08x 0x%08x\n", intr0, intr1);
 971
 972                 if (!intr0 && !(intr1 & ~delayed))
 973                         break;
 974
 975                 if (intr0 & 0x001f0000) {
 976                         nv50_display_error_handler(dev);
 977                         intr0 &= ~0x001f0000;
 978                 }
 979
 980                 if (intr1 & NV50_PDISPLAY_INTR_1_VBLANK_CRTC) {
 981                         nv50_display_vblank_handler(dev, intr1);
 982                         intr1 &= ~NV50_PDISPLAY_INTR_1_VBLANK_CRTC;
 983                 }
 984
 985                 clock = (intr1 & (NV50_PDISPLAY_INTR_1_CLK_UNK10 |
 986                                   NV50_PDISPLAY_INTR_1_CLK_UNK20 |
 987                                   NV50_PDISPLAY_INTR_1_CLK_UNK40));
 988                 if (clock) {
 989                         nv_wr32(dev, NV03_PMC_INTR_EN_0, 0);
 990                         tasklet_schedule(&disp->tasklet);
 991                         delayed |= clock;
 992                         intr1 &= ~clock;
 993                 }
 994
 995                 if (intr0) {
 996                         NV_ERROR(dev, "unknown PDISPLAY_INTR_0: 0x%08x\n", intr0);
 997                         nv_wr32(dev, NV50_PDISPLAY_INTR_0, intr0);
 998                 }
 999
1000                 if (intr1) {
1001                         NV_ERROR(dev,
1002                                  "unknown PDISPLAY_INTR_1: 0x%08x\n", intr1);
1003                         nv_wr32(dev, NV50_PDISPLAY_INTR_1, intr1);
1004                 }
1005         }
1006 }