Pileus Git - ~andy/linux/blob - drivers/gpu/drm/nouveau/nv50_display.c

   1 /*
   2  * Copyright (C) 2008 Maarten Maathuis.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial
  15  * portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  21  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  22  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  */
  26
  27 #define NOUVEAU_DMA_DEBUG (nouveau_reg_debug & NOUVEAU_REG_DEBUG_EVO)
  28 #include "nv50_display.h"
  29 #include "nouveau_crtc.h"
  30 #include "nouveau_encoder.h"
  31 #include "nouveau_connector.h"
  32 #include "nouveau_fb.h"
  33 #include "nouveau_fbcon.h"
  34 #include <core/ramht.h>
  35 #include "nouveau_software.h"
  36 #include "drm_crtc_helper.h"
  37
  38 static void nv50_display_isr(struct drm_device *);
  39 static void nv50_display_bh(unsigned long);
  40
  41 static inline int
  42 nv50_sor_nr(struct drm_device *dev)
  43 {
  44         struct drm_nouveau_private *dev_priv = dev->dev_private;
  45
  46         if (dev_priv->chipset  < 0x90 ||
  47             dev_priv->chipset == 0x92 ||
  48             dev_priv->chipset == 0xa0)
  49                 return 2;
  50
  51         return 4;
  52 }
  53
  54 u32
  55 nv50_display_active_crtcs(struct drm_device *dev)
  56 {
  57         struct drm_nouveau_private *dev_priv = dev->dev_private;
  58         u32 mask = 0;
  59         int i;
  60
  61         if (dev_priv->chipset  < 0x90 ||
  62             dev_priv->chipset == 0x92 ||
  63             dev_priv->chipset == 0xa0) {
  64                 for (i = 0; i < 2; i++)
  65                         mask |= nv_rd32(dev, NV50_PDISPLAY_SOR_MODE_CTRL_C(i));
  66         } else {
  67                 for (i = 0; i < 4; i++)
  68                         mask |= nv_rd32(dev, NV90_PDISPLAY_SOR_MODE_CTRL_C(i));
  69         }
  70
  71         for (i = 0; i < 3; i++)
  72                 mask |= nv_rd32(dev, NV50_PDISPLAY_DAC_MODE_CTRL_C(i));
  73
  74         return mask & 3;
  75 }
  76
  77 int
  78 nv50_display_early_init(struct drm_device *dev)
  79 {
  80         return 0;
  81 }
  82
  83 void
  84 nv50_display_late_takedown(struct drm_device *dev)
  85 {
  86 }
  87
  88 int
  89 nv50_display_sync(struct drm_device *dev)
  90 {
  91         struct drm_nouveau_private *dev_priv = dev->dev_private;
  92         struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
  93         struct nv50_display *disp = nv50_display(dev);
  94         struct nouveau_channel *evo = disp->master;
  95         u64 start;
  96         int ret;
  97
  98         ret = RING_SPACE(evo, 6);
  99         if (ret == 0) {
 100                 BEGIN_NV04(evo, 0, 0x0084, 1);
 101                 OUT_RING  (evo, 0x80000000);
 102                 BEGIN_NV04(evo, 0, 0x0080, 1);
 103                 OUT_RING  (evo, 0);
 104                 BEGIN_NV04(evo, 0, 0x0084, 1);
 105                 OUT_RING  (evo, 0x00000000);
 106
 107                 nv_wo32(disp->ntfy, 0x000, 0x00000000);
 108                 FIRE_RING (evo);
 109
 110                 start = ptimer->read(dev);
 111                 do {
 112                         if (nv_ro32(disp->ntfy, 0x000))
 113                                 return 0;
 114                 } while (ptimer->read(dev) - start < 2000000000ULL);
 115         }
 116
 117         return -EBUSY;
 118 }
 119
 120 int
 121 nv50_display_init(struct drm_device *dev)
 122 {
 123         struct nouveau_channel *evo;
 124         int ret, i;
 125         u32 val;
 126
 127         NV_DEBUG_KMS(dev, "\n");
 128
 129         nv_wr32(dev, 0x00610184, nv_rd32(dev, 0x00614004));
 130
 131         /*
 132          * I think the 0x006101XX range is some kind of main control area
 133          * that enables things.
 134          */
 135         /* CRTC? */
 136         for (i = 0; i < 2; i++) {
 137                 val = nv_rd32(dev, 0x00616100 + (i * 0x800));
 138                 nv_wr32(dev, 0x00610190 + (i * 0x10), val);
 139                 val = nv_rd32(dev, 0x00616104 + (i * 0x800));
 140                 nv_wr32(dev, 0x00610194 + (i * 0x10), val);
 141                 val = nv_rd32(dev, 0x00616108 + (i * 0x800));
 142                 nv_wr32(dev, 0x00610198 + (i * 0x10), val);
 143                 val = nv_rd32(dev, 0x0061610c + (i * 0x800));
 144                 nv_wr32(dev, 0x0061019c + (i * 0x10), val);
 145         }
 146
 147         /* DAC */
 148         for (i = 0; i < 3; i++) {
 149                 val = nv_rd32(dev, 0x0061a000 + (i * 0x800));
 150                 nv_wr32(dev, 0x006101d0 + (i * 0x04), val);
 151         }
 152
 153         /* SOR */
 154         for (i = 0; i < nv50_sor_nr(dev); i++) {
 155                 val = nv_rd32(dev, 0x0061c000 + (i * 0x800));
 156                 nv_wr32(dev, 0x006101e0 + (i * 0x04), val);
 157         }
 158
 159         /* EXT */
 160         for (i = 0; i < 3; i++) {
 161                 val = nv_rd32(dev, 0x0061e000 + (i * 0x800));
 162                 nv_wr32(dev, 0x006101f0 + (i * 0x04), val);
 163         }
 164
 165         for (i = 0; i < 3; i++) {
 166                 nv_wr32(dev, NV50_PDISPLAY_DAC_DPMS_CTRL(i), 0x00550000 |
 167                         NV50_PDISPLAY_DAC_DPMS_CTRL_PENDING);
 168                 nv_wr32(dev, NV50_PDISPLAY_DAC_CLK_CTRL1(i), 0x00000001);
 169         }
 170
 171         /* The precise purpose is unknown, i suspect it has something to do
 172          * with text mode.
 173          */
 174         if (nv_rd32(dev, NV50_PDISPLAY_INTR_1) & 0x100) {
 175                 nv_wr32(dev, NV50_PDISPLAY_INTR_1, 0x100);
 176                 nv_wr32(dev, 0x006194e8, nv_rd32(dev, 0x006194e8) & ~1);
 177                 if (!nv_wait(dev, 0x006194e8, 2, 0)) {
 178                         NV_ERROR(dev, "timeout: (0x6194e8 & 2) != 0\n");
 179                         NV_ERROR(dev, "0x6194e8 = 0x%08x\n",
 180                                                 nv_rd32(dev, 0x6194e8));
 181                         return -EBUSY;
 182                 }
 183         }
 184
 185         for (i = 0; i < 2; i++) {
 186                 nv_wr32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i), 0x2000);
 187                 if (!nv_wait(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
 188                              NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS, 0)) {
 189                         NV_ERROR(dev, "timeout: CURSOR_CTRL2_STATUS == 0\n");
 190                         NV_ERROR(dev, "CURSOR_CTRL2 = 0x%08x\n",
 191                                  nv_rd32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i)));
 192                         return -EBUSY;
 193                 }
 194
 195                 nv_wr32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
 196                         NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_ON);
 197                 if (!nv_wait(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
 198                              NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS,
 199                              NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS_ACTIVE)) {
 200                         NV_ERROR(dev, "timeout: "
 201                                       "CURSOR_CTRL2_STATUS_ACTIVE(%d)\n", i);
 202                         NV_ERROR(dev, "CURSOR_CTRL2(%d) = 0x%08x\n", i,
 203                                  nv_rd32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i)));
 204                         return -EBUSY;
 205                 }
 206         }
 207
 208         nv_wr32(dev, NV50_PDISPLAY_PIO_CTRL, 0x00000000);
 209         nv_mask(dev, NV50_PDISPLAY_INTR_0, 0x00000000, 0x00000000);
 210         nv_wr32(dev, NV50_PDISPLAY_INTR_EN_0, 0x00000000);
 211         nv_mask(dev, NV50_PDISPLAY_INTR_1, 0x00000000, 0x00000000);
 212         nv_wr32(dev, NV50_PDISPLAY_INTR_EN_1,
 213                      NV50_PDISPLAY_INTR_EN_1_CLK_UNK10 |
 214                      NV50_PDISPLAY_INTR_EN_1_CLK_UNK20 |
 215                      NV50_PDISPLAY_INTR_EN_1_CLK_UNK40);
 216
 217         ret = nv50_evo_init(dev);
 218         if (ret)
 219                 return ret;
 220         evo = nv50_display(dev)->master;
 221
 222         nv_wr32(dev, NV50_PDISPLAY_OBJECTS, (evo->ramin->vinst >> 8) | 9);
 223
 224         ret = RING_SPACE(evo, 3);
 225         if (ret)
 226                 return ret;
 227         BEGIN_NV04(evo, 0, NV50_EVO_UNK84, 2);
 228         OUT_RING  (evo, NV50_EVO_UNK84_NOTIFY_DISABLED);
 229         OUT_RING  (evo, NvEvoSync);
 230
 231         return nv50_display_sync(dev);
 232 }
 233
 234 void
 235 nv50_display_fini(struct drm_device *dev)
 236 {
 237         struct nv50_display *disp = nv50_display(dev);
 238         struct nouveau_channel *evo = disp->master;
 239         struct drm_crtc *drm_crtc;
 240         int ret, i;
 241
 242         NV_DEBUG_KMS(dev, "\n");
 243
 244         list_for_each_entry(drm_crtc, &dev->mode_config.crtc_list, head) {
 245                 struct nouveau_crtc *crtc = nouveau_crtc(drm_crtc);
 246
 247                 nv50_crtc_blank(crtc, true);
 248         }
 249
 250         ret = RING_SPACE(evo, 2);
 251         if (ret == 0) {
 252                 BEGIN_NV04(evo, 0, NV50_EVO_UPDATE, 1);
 253                 OUT_RING(evo, 0);
 254         }
 255         FIRE_RING(evo);
 256
 257         /* Almost like ack'ing a vblank interrupt, maybe in the spirit of
 258          * cleaning up?
 259          */
 260         list_for_each_entry(drm_crtc, &dev->mode_config.crtc_list, head) {
 261                 struct nouveau_crtc *crtc = nouveau_crtc(drm_crtc);
 262                 uint32_t mask = NV50_PDISPLAY_INTR_1_VBLANK_CRTC_(crtc->index);
 263
 264                 if (!crtc->base.enabled)
 265                         continue;
 266
 267                 nv_wr32(dev, NV50_PDISPLAY_INTR_1, mask);
 268                 if (!nv_wait(dev, NV50_PDISPLAY_INTR_1, mask, mask)) {
 269                         NV_ERROR(dev, "timeout: (0x610024 & 0x%08x) == "
 270                                       "0x%08x\n", mask, mask);
 271                         NV_ERROR(dev, "0x610024 = 0x%08x\n",
 272                                  nv_rd32(dev, NV50_PDISPLAY_INTR_1));
 273                 }
 274         }
 275
 276         for (i = 0; i < 2; i++) {
 277                 nv_wr32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i), 0);
 278                 if (!nv_wait(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
 279                              NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS, 0)) {
 280                         NV_ERROR(dev, "timeout: CURSOR_CTRL2_STATUS == 0\n");
 281                         NV_ERROR(dev, "CURSOR_CTRL2 = 0x%08x\n",
 282                                  nv_rd32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i)));
 283                 }
 284         }
 285
 286         nv50_evo_fini(dev);
 287
 288         for (i = 0; i < 3; i++) {
 289                 if (!nv_wait(dev, NV50_PDISPLAY_SOR_DPMS_STATE(i),
 290                              NV50_PDISPLAY_SOR_DPMS_STATE_WAIT, 0)) {
 291                         NV_ERROR(dev, "timeout: SOR_DPMS_STATE_WAIT(%d) == 0\n", i);
 292                         NV_ERROR(dev, "SOR_DPMS_STATE(%d) = 0x%08x\n", i,
 293                                   nv_rd32(dev, NV50_PDISPLAY_SOR_DPMS_STATE(i)));
 294                 }
 295         }
 296
 297         /* disable interrupts. */
 298         nv_wr32(dev, NV50_PDISPLAY_INTR_EN_1, 0x00000000);
 299 }
 300
 301 int
 302 nv50_display_create(struct drm_device *dev)
 303 {
 304         struct drm_nouveau_private *dev_priv = dev->dev_private;
 305         struct dcb_table *dcb = &dev_priv->vbios.dcb;
 306         struct drm_connector *connector, *ct;
 307         struct nv50_display *priv;
 308         int ret, i;
 309
 310         NV_DEBUG_KMS(dev, "\n");
 311
 312         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 313         if (!priv)
 314                 return -ENOMEM;
 315         dev_priv->engine.display.priv = priv;
 316
 317         /* Create CRTC objects */
 318         for (i = 0; i < 2; i++) {
 319                 ret = nv50_crtc_create(dev, i);
 320                 if (ret)
 321                         return ret;
 322         }
 323
 324         /* We setup the encoders from the BIOS table */
 325         for (i = 0 ; i < dcb->entries; i++) {
 326                 struct dcb_output *entry = &dcb->entry[i];
 327
 328                 if (entry->location != DCB_LOC_ON_CHIP) {
 329                         NV_WARN(dev, "Off-chip encoder %d/%d unsupported\n",
 330                                 entry->type, ffs(entry->or) - 1);
 331                         continue;
 332                 }
 333
 334                 connector = nouveau_connector_create(dev, entry->connector);
 335                 if (IS_ERR(connector))
 336                         continue;
 337
 338                 switch (entry->type) {
 339                 case DCB_OUTPUT_TMDS:
 340                 case DCB_OUTPUT_LVDS:
 341                 case DCB_OUTPUT_DP:
 342                         nv50_sor_create(connector, entry);
 343                         break;
 344                 case DCB_OUTPUT_ANALOG:
 345                         nv50_dac_create(connector, entry);
 346                         break;
 347                 default:
 348                         NV_WARN(dev, "DCB encoder %d unknown\n", entry->type);
 349                         continue;
 350                 }
 351         }
 352
 353         list_for_each_entry_safe(connector, ct,
 354                                  &dev->mode_config.connector_list, head) {
 355                 if (!connector->encoder_ids[0]) {
 356                         NV_WARN(dev, "%s has no encoders, removing\n",
 357                                 drm_get_connector_name(connector));
 358                         connector->funcs->destroy(connector);
 359                 }
 360         }
 361
 362         tasklet_init(&priv->tasklet, nv50_display_bh, (unsigned long)dev);
 363         nouveau_irq_register(dev, 26, nv50_display_isr);
 364
 365         ret = nv50_evo_create(dev);
 366         if (ret) {
 367                 nv50_display_destroy(dev);
 368                 return ret;
 369         }
 370
 371         return 0;
 372 }
 373
 374 void
 375 nv50_display_destroy(struct drm_device *dev)
 376 {
 377         struct nv50_display *disp = nv50_display(dev);
 378
 379         NV_DEBUG_KMS(dev, "\n");
 380
 381         nv50_evo_destroy(dev);
 382         nouveau_irq_unregister(dev, 26);
 383         kfree(disp);
 384 }
 385
 386 void
 387 nv50_display_flip_stop(struct drm_crtc *crtc)
 388 {
 389         struct nv50_display *disp = nv50_display(crtc->dev);
 390         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 391         struct nv50_display_crtc *dispc = &disp->crtc[nv_crtc->index];
 392         struct nouveau_channel *evo = dispc->sync;
 393         int ret;
 394
 395         ret = RING_SPACE(evo, 8);
 396         if (ret) {
 397                 WARN_ON(1);
 398                 return;
 399         }
 400
 401         BEGIN_NV04(evo, 0, 0x0084, 1);
 402         OUT_RING  (evo, 0x00000000);
 403         BEGIN_NV04(evo, 0, 0x0094, 1);
 404         OUT_RING  (evo, 0x00000000);
 405         BEGIN_NV04(evo, 0, 0x00c0, 1);
 406         OUT_RING  (evo, 0x00000000);
 407         BEGIN_NV04(evo, 0, 0x0080, 1);
 408         OUT_RING  (evo, 0x00000000);
 409         FIRE_RING (evo);
 410 }
 411
 412 int
 413 nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb,
 414                        struct nouveau_channel *chan)
 415 {
 416         struct drm_nouveau_private *dev_priv = crtc->dev->dev_private;
 417         struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb);
 418         struct nv50_display *disp = nv50_display(crtc->dev);
 419         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 420         struct nv50_display_crtc *dispc = &disp->crtc[nv_crtc->index];
 421         struct nouveau_channel *evo = dispc->sync;
 422         int ret;
 423
 424         ret = RING_SPACE(evo, chan ? 25 : 27);
 425         if (unlikely(ret))
 426                 return ret;
 427
 428         /* synchronise with the rendering channel, if necessary */
 429         if (likely(chan)) {
 430                 ret = RING_SPACE(chan, 10);
 431                 if (ret) {
 432                         WIND_RING(evo);
 433                         return ret;
 434                 }
 435
 436                 if (dev_priv->chipset < 0xc0) {
 437                         BEGIN_NV04(chan, 0, 0x0060, 2);
 438                         OUT_RING  (chan, NvEvoSema0 + nv_crtc->index);
 439                         OUT_RING  (chan, dispc->sem.offset);
 440                         BEGIN_NV04(chan, 0, 0x006c, 1);
 441                         OUT_RING  (chan, 0xf00d0000 | dispc->sem.value);
 442                         BEGIN_NV04(chan, 0, 0x0064, 2);
 443                         OUT_RING  (chan, dispc->sem.offset ^ 0x10);
 444                         OUT_RING  (chan, 0x74b1e000);
 445                         BEGIN_NV04(chan, 0, 0x0060, 1);
 446                         if (dev_priv->chipset < 0x84)
 447                                 OUT_RING  (chan, NvSema);
 448                         else
 449                                 OUT_RING  (chan, chan->vram_handle);
 450                 } else {
 451                         u64 offset = nvc0_software_crtc(chan, nv_crtc->index);
 452                         offset += dispc->sem.offset;
 453                         BEGIN_NVC0(chan, 0, 0x0010, 4);
 454                         OUT_RING  (chan, upper_32_bits(offset));
 455                         OUT_RING  (chan, lower_32_bits(offset));
 456                         OUT_RING  (chan, 0xf00d0000 | dispc->sem.value);
 457                         OUT_RING  (chan, 0x1002);
 458                         BEGIN_NVC0(chan, 0, 0x0010, 4);
 459                         OUT_RING  (chan, upper_32_bits(offset));
 460                         OUT_RING  (chan, lower_32_bits(offset ^ 0x10));
 461                         OUT_RING  (chan, 0x74b1e000);
 462                         OUT_RING  (chan, 0x1001);
 463                 }
 464                 FIRE_RING (chan);
 465         } else {
 466                 nouveau_bo_wr32(dispc->sem.bo, dispc->sem.offset / 4,
 467                                 0xf00d0000 | dispc->sem.value);
 468         }
 469
 470         /* queue the flip on the crtc's "display sync" channel */
 471         BEGIN_NV04(evo, 0, 0x0100, 1);
 472         OUT_RING  (evo, 0xfffe0000);
 473         if (chan) {
 474                 BEGIN_NV04(evo, 0, 0x0084, 1);
 475                 OUT_RING  (evo, 0x00000100);
 476         } else {
 477                 BEGIN_NV04(evo, 0, 0x0084, 1);
 478                 OUT_RING  (evo, 0x00000010);
 479                 /* allows gamma somehow, PDISP will bitch at you if
 480                  * you don't wait for vblank before changing this..
 481                  */
 482                 BEGIN_NV04(evo, 0, 0x00e0, 1);
 483                 OUT_RING  (evo, 0x40000000);
 484         }
 485         BEGIN_NV04(evo, 0, 0x0088, 4);
 486         OUT_RING  (evo, dispc->sem.offset);
 487         OUT_RING  (evo, 0xf00d0000 | dispc->sem.value);
 488         OUT_RING  (evo, 0x74b1e000);
 489         OUT_RING  (evo, NvEvoSync);
 490         BEGIN_NV04(evo, 0, 0x00a0, 2);
 491         OUT_RING  (evo, 0x00000000);
 492         OUT_RING  (evo, 0x00000000);
 493         BEGIN_NV04(evo, 0, 0x00c0, 1);
 494         OUT_RING  (evo, nv_fb->r_dma);
 495         BEGIN_NV04(evo, 0, 0x0110, 2);
 496         OUT_RING  (evo, 0x00000000);
 497         OUT_RING  (evo, 0x00000000);
 498         BEGIN_NV04(evo, 0, 0x0800, 5);
 499         OUT_RING  (evo, nv_fb->nvbo->bo.offset >> 8);
 500         OUT_RING  (evo, 0);
 501         OUT_RING  (evo, (fb->height << 16) | fb->width);
 502         OUT_RING  (evo, nv_fb->r_pitch);
 503         OUT_RING  (evo, nv_fb->r_format);
 504         BEGIN_NV04(evo, 0, 0x0080, 1);
 505         OUT_RING  (evo, 0x00000000);
 506         FIRE_RING (evo);
 507
 508         dispc->sem.offset ^= 0x10;
 509         dispc->sem.value++;
 510         return 0;
 511 }
 512
 513 static u16
 514 nv50_display_script_select(struct drm_device *dev, struct dcb_output *dcb,
 515                            u32 mc, int pxclk)
 516 {
 517         struct drm_nouveau_private *dev_priv = dev->dev_private;
 518         struct nouveau_connector *nv_connector = NULL;
 519         struct drm_encoder *encoder;
 520         struct nvbios *bios = &dev_priv->vbios;
 521         u32 script = 0, or;
 522
 523         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 524                 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 525
 526                 if (nv_encoder->dcb != dcb)
 527                         continue;
 528
 529                 nv_connector = nouveau_encoder_connector_get(nv_encoder);
 530                 break;
 531         }
 532
 533         or = ffs(dcb->or) - 1;
 534         switch (dcb->type) {
 535         case DCB_OUTPUT_LVDS:
 536                 script = (mc >> 8) & 0xf;
 537                 if (bios->fp_no_ddc) {
 538                         if (bios->fp.dual_link)
 539                                 script |= 0x0100;
 540                         if (bios->fp.if_is_24bit)
 541                                 script |= 0x0200;
 542                 } else {
 543                         /* determine number of lvds links */
 544                         if (nv_connector && nv_connector->edid &&
 545                             nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
 546                                 /* http://www.spwg.org */
 547                                 if (((u8 *)nv_connector->edid)[121] == 2)
 548                                         script |= 0x0100;
 549                         } else
 550                         if (pxclk >= bios->fp.duallink_transition_clk) {
 551                                 script |= 0x0100;
 552                         }
 553
 554                         /* determine panel depth */
 555                         if (script & 0x0100) {
 556                                 if (bios->fp.strapless_is_24bit & 2)
 557                                         script |= 0x0200;
 558                         } else {
 559                                 if (bios->fp.strapless_is_24bit & 1)
 560                                         script |= 0x0200;
 561                         }
 562
 563                         if (nv_connector && nv_connector->edid &&
 564                             (nv_connector->edid->revision >= 4) &&
 565                             (nv_connector->edid->input & 0x70) >= 0x20)
 566                                 script |= 0x0200;
 567                 }
 568
 569                 if (nouveau_uscript_lvds >= 0) {
 570                         NV_INFO(dev, "override script 0x%04x with 0x%04x "
 571                                      "for output LVDS-%d\n", script,
 572                                      nouveau_uscript_lvds, or);
 573                         script = nouveau_uscript_lvds;
 574                 }
 575                 break;
 576         case DCB_OUTPUT_TMDS:
 577                 script = (mc >> 8) & 0xf;
 578                 if (pxclk >= 165000)
 579                         script |= 0x0100;
 580
 581                 if (nouveau_uscript_tmds >= 0) {
 582                         NV_INFO(dev, "override script 0x%04x with 0x%04x "
 583                                      "for output TMDS-%d\n", script,
 584                                      nouveau_uscript_tmds, or);
 585                         script = nouveau_uscript_tmds;
 586                 }
 587                 break;
 588         case DCB_OUTPUT_DP:
 589                 script = (mc >> 8) & 0xf;
 590                 break;
 591         case DCB_OUTPUT_ANALOG:
 592                 script = 0xff;
 593                 break;
 594         default:
 595                 NV_ERROR(dev, "modeset on unsupported output type!\n");
 596                 break;
 597         }
 598
 599         return script;
 600 }
 601
 602 static void
 603 nv50_display_vblank_crtc_handler(struct drm_device *dev, int crtc)
 604 {
 605         struct drm_nouveau_private *dev_priv = dev->dev_private;
 606         struct nouveau_software_priv *psw = nv_engine(dev, NVOBJ_ENGINE_SW);
 607         struct nouveau_software_chan *pch, *tmp;
 608
 609         list_for_each_entry_safe(pch, tmp, &psw->vblank, vblank.list) {
 610                 if (pch->vblank.head != crtc)
 611                         continue;
 612
 613                 spin_lock(&psw->peephole_lock);
 614                 nv_wr32(dev, 0x001704, pch->vblank.channel);
 615                 nv_wr32(dev, 0x001710, 0x80000000 | pch->vblank.ctxdma);
 616                 if (dev_priv->chipset == 0x50) {
 617                         nv_wr32(dev, 0x001570, pch->vblank.offset);
 618                         nv_wr32(dev, 0x001574, pch->vblank.value);
 619                 } else {
 620                         nv_wr32(dev, 0x060010, pch->vblank.offset);
 621                         nv_wr32(dev, 0x060014, pch->vblank.value);
 622                 }
 623                 spin_unlock(&psw->peephole_lock);
 624
 625                 list_del(&pch->vblank.list);
 626                 drm_vblank_put(dev, crtc);
 627         }
 628
 629         drm_handle_vblank(dev, crtc);
 630 }
 631
 632 static void
 633 nv50_display_vblank_handler(struct drm_device *dev, uint32_t intr)
 634 {
 635         if (intr & NV50_PDISPLAY_INTR_1_VBLANK_CRTC_0)
 636                 nv50_display_vblank_crtc_handler(dev, 0);
 637
 638         if (intr & NV50_PDISPLAY_INTR_1_VBLANK_CRTC_1)
 639                 nv50_display_vblank_crtc_handler(dev, 1);
 640
 641         nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_VBLANK_CRTC);
 642 }
 643
 644 static void
 645 nv50_display_unk10_handler(struct drm_device *dev)
 646 {
 647         struct drm_nouveau_private *dev_priv = dev->dev_private;
 648         struct nv50_display *disp = nv50_display(dev);
 649         u32 unk30 = nv_rd32(dev, 0x610030), mc;
 650         int i, crtc, or = 0, type = DCB_OUTPUT_ANY;
 651
 652         NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
 653         disp->irq.dcb = NULL;
 654
 655         nv_wr32(dev, 0x619494, nv_rd32(dev, 0x619494) & ~8);
 656
 657         /* Determine which CRTC we're dealing with, only 1 ever will be
 658          * signalled at the same time with the current nouveau code.
 659          */
 660         crtc = ffs((unk30 & 0x00000060) >> 5) - 1;
 661         if (crtc < 0)
 662                 goto ack;
 663
 664         /* Nothing needs to be done for the encoder */
 665         crtc = ffs((unk30 & 0x00000180) >> 7) - 1;
 666         if (crtc < 0)
 667                 goto ack;
 668
 669         /* Find which encoder was connected to the CRTC */
 670         for (i = 0; type == DCB_OUTPUT_ANY && i < 3; i++) {
 671                 mc = nv_rd32(dev, NV50_PDISPLAY_DAC_MODE_CTRL_C(i));
 672                 NV_DEBUG_KMS(dev, "DAC-%d mc: 0x%08x\n", i, mc);
 673                 if (!(mc & (1 << crtc)))
 674                         continue;
 675
 676                 switch ((mc & 0x00000f00) >> 8) {
 677                 case 0: type = DCB_OUTPUT_ANALOG; break;
 678                 case 1: type = DCB_OUTPUT_TV; break;
 679                 default:
 680                         NV_ERROR(dev, "invalid mc, DAC-%d: 0x%08x\n", i, mc);
 681                         goto ack;
 682                 }
 683
 684                 or = i;
 685         }
 686
 687         for (i = 0; type == DCB_OUTPUT_ANY && i < nv50_sor_nr(dev); i++) {
 688                 if (dev_priv->chipset  < 0x90 ||
 689                     dev_priv->chipset == 0x92 ||
 690                     dev_priv->chipset == 0xa0)
 691                         mc = nv_rd32(dev, NV50_PDISPLAY_SOR_MODE_CTRL_C(i));
 692                 else
 693                         mc = nv_rd32(dev, NV90_PDISPLAY_SOR_MODE_CTRL_C(i));
 694
 695                 NV_DEBUG_KMS(dev, "SOR-%d mc: 0x%08x\n", i, mc);
 696                 if (!(mc & (1 << crtc)))
 697                         continue;
 698
 699                 switch ((mc & 0x00000f00) >> 8) {
 700                 case 0: type = DCB_OUTPUT_LVDS; break;
 701                 case 1: type = DCB_OUTPUT_TMDS; break;
 702                 case 2: type = DCB_OUTPUT_TMDS; break;
 703                 case 5: type = DCB_OUTPUT_TMDS; break;
 704                 case 8: type = DCB_OUTPUT_DP; break;
 705                 case 9: type = DCB_OUTPUT_DP; break;
 706                 default:
 707                         NV_ERROR(dev, "invalid mc, SOR-%d: 0x%08x\n", i, mc);
 708                         goto ack;
 709                 }
 710
 711                 or = i;
 712         }
 713
 714         /* There was no encoder to disable */
 715         if (type == DCB_OUTPUT_ANY)
 716                 goto ack;
 717
 718         /* Disable the encoder */
 719         for (i = 0; i < dev_priv->vbios.dcb.entries; i++) {
 720                 struct dcb_output *dcb = &dev_priv->vbios.dcb.entry[i];
 721
 722                 if (dcb->type == type && (dcb->or & (1 << or))) {
 723                         nouveau_bios_run_display_table(dev, 0, -1, dcb, -1);
 724                         disp->irq.dcb = dcb;
 725                         goto ack;
 726                 }
 727         }
 728
 729         NV_ERROR(dev, "no dcb for %d %d 0x%08x\n", or, type, mc);
 730 ack:
 731         nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK10);
 732         nv_wr32(dev, 0x610030, 0x80000000);
 733 }
 734
 735 static void
 736 nv50_display_unk20_handler(struct drm_device *dev)
 737 {
 738         struct drm_nouveau_private *dev_priv = dev->dev_private;
 739         struct nv50_display *disp = nv50_display(dev);
 740         u32 unk30 = nv_rd32(dev, 0x610030), tmp, pclk, script, mc = 0;
 741         struct dcb_output *dcb;
 742         int i, crtc, or = 0, type = DCB_OUTPUT_ANY;
 743
 744         NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
 745         dcb = disp->irq.dcb;
 746         if (dcb) {
 747                 nouveau_bios_run_display_table(dev, 0, -2, dcb, -1);
 748                 disp->irq.dcb = NULL;
 749         }
 750
 751         /* CRTC clock change requested? */
 752         crtc = ffs((unk30 & 0x00000600) >> 9) - 1;
 753         if (crtc >= 0) {
 754                 pclk  = nv_rd32(dev, NV50_PDISPLAY_CRTC_P(crtc, CLOCK));
 755                 pclk &= 0x003fffff;
 756                 if (pclk)
 757                         nv50_crtc_set_clock(dev, crtc, pclk);
 758
 759                 tmp = nv_rd32(dev, NV50_PDISPLAY_CRTC_CLK_CTRL2(crtc));
 760                 tmp &= ~0x000000f;
 761                 nv_wr32(dev, NV50_PDISPLAY_CRTC_CLK_CTRL2(crtc), tmp);
 762         }
 763
 764         /* Nothing needs to be done for the encoder */
 765         crtc = ffs((unk30 & 0x00000180) >> 7) - 1;
 766         if (crtc < 0)
 767                 goto ack;
 768         pclk  = nv_rd32(dev, NV50_PDISPLAY_CRTC_P(crtc, CLOCK)) & 0x003fffff;
 769
 770         /* Find which encoder is connected to the CRTC */
 771         for (i = 0; type == DCB_OUTPUT_ANY && i < 3; i++) {
 772                 mc = nv_rd32(dev, NV50_PDISPLAY_DAC_MODE_CTRL_P(i));
 773                 NV_DEBUG_KMS(dev, "DAC-%d mc: 0x%08x\n", i, mc);
 774                 if (!(mc & (1 << crtc)))
 775                         continue;
 776
 777                 switch ((mc & 0x00000f00) >> 8) {
 778                 case 0: type = DCB_OUTPUT_ANALOG; break;
 779                 case 1: type = DCB_OUTPUT_TV; break;
 780                 default:
 781                         NV_ERROR(dev, "invalid mc, DAC-%d: 0x%08x\n", i, mc);
 782                         goto ack;
 783                 }
 784
 785                 or = i;
 786         }
 787
 788         for (i = 0; type == DCB_OUTPUT_ANY && i < nv50_sor_nr(dev); i++) {
 789                 if (dev_priv->chipset  < 0x90 ||
 790                     dev_priv->chipset == 0x92 ||
 791                     dev_priv->chipset == 0xa0)
 792                         mc = nv_rd32(dev, NV50_PDISPLAY_SOR_MODE_CTRL_P(i));
 793                 else
 794                         mc = nv_rd32(dev, NV90_PDISPLAY_SOR_MODE_CTRL_P(i));
 795
 796                 NV_DEBUG_KMS(dev, "SOR-%d mc: 0x%08x\n", i, mc);
 797                 if (!(mc & (1 << crtc)))
 798                         continue;
 799
 800                 switch ((mc & 0x00000f00) >> 8) {
 801                 case 0: type = DCB_OUTPUT_LVDS; break;
 802                 case 1: type = DCB_OUTPUT_TMDS; break;
 803                 case 2: type = DCB_OUTPUT_TMDS; break;
 804                 case 5: type = DCB_OUTPUT_TMDS; break;
 805                 case 8: type = DCB_OUTPUT_DP; break;
 806                 case 9: type = DCB_OUTPUT_DP; break;
 807                 default:
 808                         NV_ERROR(dev, "invalid mc, SOR-%d: 0x%08x\n", i, mc);
 809                         goto ack;
 810                 }
 811
 812                 or = i;
 813         }
 814
 815         if (type == DCB_OUTPUT_ANY)
 816                 goto ack;
 817
 818         /* Enable the encoder */
 819         for (i = 0; i < dev_priv->vbios.dcb.entries; i++) {
 820                 dcb = &dev_priv->vbios.dcb.entry[i];
 821                 if (dcb->type == type && (dcb->or & (1 << or)))
 822                         break;
 823         }
 824
 825         if (i == dev_priv->vbios.dcb.entries) {
 826                 NV_ERROR(dev, "no dcb for %d %d 0x%08x\n", or, type, mc);
 827                 goto ack;
 828         }
 829
 830         script = nv50_display_script_select(dev, dcb, mc, pclk);
 831         nouveau_bios_run_display_table(dev, script, pclk, dcb, -1);
 832
 833         if (type == DCB_OUTPUT_DP) {
 834                 int link = !(dcb->dpconf.sor.link & 1);
 835                 if ((mc & 0x000f0000) == 0x00020000)
 836                         nv50_sor_dp_calc_tu(dev, or, link, pclk, 18);
 837                 else
 838                         nv50_sor_dp_calc_tu(dev, or, link, pclk, 24);
 839         }
 840
 841         if (dcb->type != DCB_OUTPUT_ANALOG) {
 842                 tmp = nv_rd32(dev, NV50_PDISPLAY_SOR_CLK_CTRL2(or));
 843                 tmp &= ~0x00000f0f;
 844                 if (script & 0x0100)
 845                         tmp |= 0x00000101;
 846                 nv_wr32(dev, NV50_PDISPLAY_SOR_CLK_CTRL2(or), tmp);
 847         } else {
 848                 nv_wr32(dev, NV50_PDISPLAY_DAC_CLK_CTRL2(or), 0);
 849         }
 850
 851         disp->irq.dcb = dcb;
 852         disp->irq.pclk = pclk;
 853         disp->irq.script = script;
 854
 855 ack:
 856         nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK20);
 857         nv_wr32(dev, 0x610030, 0x80000000);
 858 }
 859
 860 /* If programming a TMDS output on a SOR that can also be configured for
 861  * DisplayPort, make sure NV50_SOR_DP_CTRL_ENABLE is forced off.
 862  *
 863  * It looks like the VBIOS TMDS scripts make an attempt at this, however,
 864  * the VBIOS scripts on at least one board I have only switch it off on
 865  * link 0, causing a blank display if the output has previously been
 866  * programmed for DisplayPort.
 867  */
 868 static void
 869 nv50_display_unk40_dp_set_tmds(struct drm_device *dev, struct dcb_output *dcb)
 870 {
 871         int or = ffs(dcb->or) - 1, link = !(dcb->dpconf.sor.link & 1);
 872         struct drm_encoder *encoder;
 873         u32 tmp;
 874
 875         if (dcb->type != DCB_OUTPUT_TMDS)
 876                 return;
 877
 878         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 879                 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 880
 881                 if (nv_encoder->dcb->type == DCB_OUTPUT_DP &&
 882                     nv_encoder->dcb->or & (1 << or)) {
 883                         tmp  = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link));
 884                         tmp &= ~NV50_SOR_DP_CTRL_ENABLED;
 885                         nv_wr32(dev, NV50_SOR_DP_CTRL(or, link), tmp);
 886                         break;
 887                 }
 888         }
 889 }
 890
 891 static void
 892 nv50_display_unk40_handler(struct drm_device *dev)
 893 {
 894         struct nv50_display *disp = nv50_display(dev);
 895         struct dcb_output *dcb = disp->irq.dcb;
 896         u16 script = disp->irq.script;
 897         u32 unk30 = nv_rd32(dev, 0x610030), pclk = disp->irq.pclk;
 898
 899         NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
 900         disp->irq.dcb = NULL;
 901         if (!dcb)
 902                 goto ack;
 903
 904         nouveau_bios_run_display_table(dev, script, -pclk, dcb, -1);
 905         nv50_display_unk40_dp_set_tmds(dev, dcb);
 906
 907 ack:
 908         nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK40);
 909         nv_wr32(dev, 0x610030, 0x80000000);
 910         nv_wr32(dev, 0x619494, nv_rd32(dev, 0x619494) | 8);
 911 }
 912
 913 static void
 914 nv50_display_bh(unsigned long data)
 915 {
 916         struct drm_device *dev = (struct drm_device *)data;
 917
 918         for (;;) {
 919                 uint32_t intr0 = nv_rd32(dev, NV50_PDISPLAY_INTR_0);
 920                 uint32_t intr1 = nv_rd32(dev, NV50_PDISPLAY_INTR_1);
 921
 922                 NV_DEBUG_KMS(dev, "PDISPLAY_INTR_BH 0x%08x 0x%08x\n", intr0, intr1);
 923
 924                 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK10)
 925                         nv50_display_unk10_handler(dev);
 926                 else
 927                 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK20)
 928                         nv50_display_unk20_handler(dev);
 929                 else
 930                 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK40)
 931                         nv50_display_unk40_handler(dev);
 932                 else
 933                         break;
 934         }
 935
 936         nv_wr32(dev, NV03_PMC_INTR_EN_0, 1);
 937 }
 938
 939 static void
 940 nv50_display_error_handler(struct drm_device *dev)
 941 {
 942         u32 channels = (nv_rd32(dev, NV50_PDISPLAY_INTR_0) & 0x001f0000) >> 16;
 943         u32 addr, data;
 944         int chid;
 945
 946         for (chid = 0; chid < 5; chid++) {
 947                 if (!(channels & (1 << chid)))
 948                         continue;
 949
 950                 nv_wr32(dev, NV50_PDISPLAY_INTR_0, 0x00010000 << chid);
 951                 addr = nv_rd32(dev, NV50_PDISPLAY_TRAPPED_ADDR(chid));
 952                 data = nv_rd32(dev, NV50_PDISPLAY_TRAPPED_DATA(chid));
 953                 NV_ERROR(dev, "EvoCh %d Mthd 0x%04x Data 0x%08x "
 954                               "(0x%04x 0x%02x)\n", chid,
 955                          addr & 0xffc, data, addr >> 16, (addr >> 12) & 0xf);
 956
 957                 nv_wr32(dev, NV50_PDISPLAY_TRAPPED_ADDR(chid), 0x90000000);
 958         }
 959 }
 960
 961 static void
 962 nv50_display_isr(struct drm_device *dev)
 963 {
 964         struct nv50_display *disp = nv50_display(dev);
 965         uint32_t delayed = 0;
 966
 967         while (nv_rd32(dev, NV50_PMC_INTR_0) & NV50_PMC_INTR_0_DISPLAY) {
 968                 uint32_t intr0 = nv_rd32(dev, NV50_PDISPLAY_INTR_0);
 969                 uint32_t intr1 = nv_rd32(dev, NV50_PDISPLAY_INTR_1);
 970                 uint32_t clock;
 971
 972                 NV_DEBUG_KMS(dev, "PDISPLAY_INTR 0x%08x 0x%08x\n", intr0, intr1);
 973
 974                 if (!intr0 && !(intr1 & ~delayed))
 975                         break;
 976
 977                 if (intr0 & 0x001f0000) {
 978                         nv50_display_error_handler(dev);
 979                         intr0 &= ~0x001f0000;
 980                 }
 981
 982                 if (intr1 & NV50_PDISPLAY_INTR_1_VBLANK_CRTC) {
 983                         nv50_display_vblank_handler(dev, intr1);
 984                         intr1 &= ~NV50_PDISPLAY_INTR_1_VBLANK_CRTC;
 985                 }
 986
 987                 clock = (intr1 & (NV50_PDISPLAY_INTR_1_CLK_UNK10 |
 988                                   NV50_PDISPLAY_INTR_1_CLK_UNK20 |
 989                                   NV50_PDISPLAY_INTR_1_CLK_UNK40));
 990                 if (clock) {
 991                         nv_wr32(dev, NV03_PMC_INTR_EN_0, 0);
 992                         tasklet_schedule(&disp->tasklet);
 993                         delayed |= clock;
 994                         intr1 &= ~clock;
 995                 }
 996
 997                 if (intr0) {
 998                         NV_ERROR(dev, "unknown PDISPLAY_INTR_0: 0x%08x\n", intr0);
 999                         nv_wr32(dev, NV50_PDISPLAY_INTR_0, intr0);
1000                 }
1001
1002                 if (intr1) {
1003                         NV_ERROR(dev,
1004                                  "unknown PDISPLAY_INTR_1: 0x%08x\n", intr1);
1005                         nv_wr32(dev, NV50_PDISPLAY_INTR_1, intr1);
1006                 }
1007         }
1008 }