Pileus Git - ~andy/linux/blob - drivers/gpu/drm/nouveau/nv50_display.c

   1         /*
   2  * Copyright 2011 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <linux/dma-mapping.h>
  26
  27 #include <drm/drmP.h>
  28 #include <drm/drm_crtc_helper.h>
  29
  30 #include "nouveau_drm.h"
  31 #include "nouveau_dma.h"
  32 #include "nouveau_gem.h"
  33 #include "nouveau_connector.h"
  34 #include "nouveau_encoder.h"
  35 #include "nouveau_crtc.h"
  36 #include "nouveau_fence.h"
  37 #include "nv50_display.h"
  38
  39 #include <core/client.h>
  40 #include <core/gpuobj.h>
  41 #include <core/class.h>
  42
  43 #include <subdev/timer.h>
  44 #include <subdev/bar.h>
  45 #include <subdev/fb.h>
  46 #include <subdev/i2c.h>
  47
  48 #define EVO_DMA_NR 9
  49
  50 #define EVO_MASTER  (0x00)
  51 #define EVO_FLIP(c) (0x01 + (c))
  52 #define EVO_OVLY(c) (0x05 + (c))
  53 #define EVO_OIMM(c) (0x09 + (c))
  54 #define EVO_CURS(c) (0x0d + (c))
  55
  56 /* offsets in shared sync bo of various structures */
  57 #define EVO_SYNC(c, o) ((c) * 0x0100 + (o))
  58 #define EVO_MAST_NTFY     EVO_SYNC(  0, 0x00)
  59 #define EVO_FLIP_SEM0(c)  EVO_SYNC((c), 0x00)
  60 #define EVO_FLIP_SEM1(c)  EVO_SYNC((c), 0x10)
  61
  62 #define EVO_CORE_HANDLE      (0xd1500000)
  63 #define EVO_CHAN_HANDLE(t,i) (0xd15c0000 | (((t) & 0x00ff) << 8) | (i))
  64 #define EVO_CHAN_OCLASS(t,c) ((nv_hclass(c) & 0xff00) | ((t) & 0x00ff))
  65 #define EVO_PUSH_HANDLE(t,i) (0xd15b0000 | (i) |                               \
  66                               (((NV50_DISP_##t##_CLASS) & 0x00ff) << 8))
  67
  68 /******************************************************************************
  69  * EVO channel
  70  *****************************************************************************/
  71
  72 struct nv50_chan {
  73         struct nouveau_object *user;
  74         u32 handle;
  75 };
  76
  77 static int
  78 nv50_chan_create(struct nouveau_object *core, u32 bclass, u8 head,
  79                  void *data, u32 size, struct nv50_chan *chan)
  80 {
  81         struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS);
  82         const u32 oclass = EVO_CHAN_OCLASS(bclass, core);
  83         const u32 handle = EVO_CHAN_HANDLE(bclass, head);
  84         int ret;
  85
  86         ret = nouveau_object_new(client, EVO_CORE_HANDLE, handle,
  87                                  oclass, data, size, &chan->user);
  88         if (ret)
  89                 return ret;
  90
  91         chan->handle = handle;
  92         return 0;
  93 }
  94
  95 static void
  96 nv50_chan_destroy(struct nouveau_object *core, struct nv50_chan *chan)
  97 {
  98         struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS);
  99         if (chan->handle)
 100                 nouveau_object_del(client, EVO_CORE_HANDLE, chan->handle);
 101 }
 102
 103 /******************************************************************************
 104  * PIO EVO channel
 105  *****************************************************************************/
 106
 107 struct nv50_pioc {
 108         struct nv50_chan base;
 109 };
 110
 111 static void
 112 nv50_pioc_destroy(struct nouveau_object *core, struct nv50_pioc *pioc)
 113 {
 114         nv50_chan_destroy(core, &pioc->base);
 115 }
 116
 117 static int
 118 nv50_pioc_create(struct nouveau_object *core, u32 bclass, u8 head,
 119                  void *data, u32 size, struct nv50_pioc *pioc)
 120 {
 121         return nv50_chan_create(core, bclass, head, data, size, &pioc->base);
 122 }
 123
 124 /******************************************************************************
 125  * DMA EVO channel
 126  *****************************************************************************/
 127
 128 struct nv50_dmac {
 129         struct nv50_chan base;
 130         dma_addr_t handle;
 131         u32 *ptr;
 132
 133         /* Protects against concurrent pushbuf access to this channel, lock is
 134          * grabbed by evo_wait (if the pushbuf reservation is successful) and
 135          * dropped again by evo_kick. */
 136         struct mutex lock;
 137 };
 138
 139 static void
 140 nv50_dmac_destroy(struct nouveau_object *core, struct nv50_dmac *dmac)
 141 {
 142         if (dmac->ptr) {
 143                 struct pci_dev *pdev = nv_device(core)->pdev;
 144                 pci_free_consistent(pdev, PAGE_SIZE, dmac->ptr, dmac->handle);
 145         }
 146
 147         nv50_chan_destroy(core, &dmac->base);
 148 }
 149
 150 static int
 151 nv50_dmac_create_fbdma(struct nouveau_object *core, u32 parent)
 152 {
 153         struct nouveau_fb *pfb = nouveau_fb(core);
 154         struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS);
 155         struct nouveau_object *object;
 156         int ret = nouveau_object_new(client, parent, NvEvoVRAM_LP,
 157                                      NV_DMA_IN_MEMORY_CLASS,
 158                                      &(struct nv_dma_class) {
 159                                         .flags = NV_DMA_TARGET_VRAM |
 160                                                  NV_DMA_ACCESS_RDWR,
 161                                         .start = 0,
 162                                         .limit = pfb->ram.size - 1,
 163                                         .conf0 = NV50_DMA_CONF0_ENABLE |
 164                                                  NV50_DMA_CONF0_PART_256,
 165                                      }, sizeof(struct nv_dma_class), &object);
 166         if (ret)
 167                 return ret;
 168
 169         ret = nouveau_object_new(client, parent, NvEvoFB16,
 170                                  NV_DMA_IN_MEMORY_CLASS,
 171                                  &(struct nv_dma_class) {
 172                                         .flags = NV_DMA_TARGET_VRAM |
 173                                                  NV_DMA_ACCESS_RDWR,
 174                                         .start = 0,
 175                                         .limit = pfb->ram.size - 1,
 176                                         .conf0 = NV50_DMA_CONF0_ENABLE | 0x70 |
 177                                                  NV50_DMA_CONF0_PART_256,
 178                                  }, sizeof(struct nv_dma_class), &object);
 179         if (ret)
 180                 return ret;
 181
 182         ret = nouveau_object_new(client, parent, NvEvoFB32,
 183                                  NV_DMA_IN_MEMORY_CLASS,
 184                                  &(struct nv_dma_class) {
 185                                         .flags = NV_DMA_TARGET_VRAM |
 186                                                  NV_DMA_ACCESS_RDWR,
 187                                         .start = 0,
 188                                         .limit = pfb->ram.size - 1,
 189                                         .conf0 = NV50_DMA_CONF0_ENABLE | 0x7a |
 190                                                  NV50_DMA_CONF0_PART_256,
 191                                  }, sizeof(struct nv_dma_class), &object);
 192         return ret;
 193 }
 194
 195 static int
 196 nvc0_dmac_create_fbdma(struct nouveau_object *core, u32 parent)
 197 {
 198         struct nouveau_fb *pfb = nouveau_fb(core);
 199         struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS);
 200         struct nouveau_object *object;
 201         int ret = nouveau_object_new(client, parent, NvEvoVRAM_LP,
 202                                      NV_DMA_IN_MEMORY_CLASS,
 203                                      &(struct nv_dma_class) {
 204                                         .flags = NV_DMA_TARGET_VRAM |
 205                                                  NV_DMA_ACCESS_RDWR,
 206                                         .start = 0,
 207                                         .limit = pfb->ram.size - 1,
 208                                         .conf0 = NVC0_DMA_CONF0_ENABLE,
 209                                      }, sizeof(struct nv_dma_class), &object);
 210         if (ret)
 211                 return ret;
 212
 213         ret = nouveau_object_new(client, parent, NvEvoFB16,
 214                                  NV_DMA_IN_MEMORY_CLASS,
 215                                  &(struct nv_dma_class) {
 216                                         .flags = NV_DMA_TARGET_VRAM |
 217                                                  NV_DMA_ACCESS_RDWR,
 218                                         .start = 0,
 219                                         .limit = pfb->ram.size - 1,
 220                                         .conf0 = NVC0_DMA_CONF0_ENABLE | 0xfe,
 221                                  }, sizeof(struct nv_dma_class), &object);
 222         if (ret)
 223                 return ret;
 224
 225         ret = nouveau_object_new(client, parent, NvEvoFB32,
 226                                  NV_DMA_IN_MEMORY_CLASS,
 227                                  &(struct nv_dma_class) {
 228                                         .flags = NV_DMA_TARGET_VRAM |
 229                                                  NV_DMA_ACCESS_RDWR,
 230                                         .start = 0,
 231                                         .limit = pfb->ram.size - 1,
 232                                         .conf0 = NVC0_DMA_CONF0_ENABLE | 0xfe,
 233                                  }, sizeof(struct nv_dma_class), &object);
 234         return ret;
 235 }
 236
 237 static int
 238 nvd0_dmac_create_fbdma(struct nouveau_object *core, u32 parent)
 239 {
 240         struct nouveau_fb *pfb = nouveau_fb(core);
 241         struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS);
 242         struct nouveau_object *object;
 243         int ret = nouveau_object_new(client, parent, NvEvoVRAM_LP,
 244                                      NV_DMA_IN_MEMORY_CLASS,
 245                                      &(struct nv_dma_class) {
 246                                         .flags = NV_DMA_TARGET_VRAM |
 247                                                  NV_DMA_ACCESS_RDWR,
 248                                         .start = 0,
 249                                         .limit = pfb->ram.size - 1,
 250                                         .conf0 = NVD0_DMA_CONF0_ENABLE |
 251                                                  NVD0_DMA_CONF0_PAGE_LP,
 252                                      }, sizeof(struct nv_dma_class), &object);
 253         if (ret)
 254                 return ret;
 255
 256         ret = nouveau_object_new(client, parent, NvEvoFB32,
 257                                  NV_DMA_IN_MEMORY_CLASS,
 258                                  &(struct nv_dma_class) {
 259                                         .flags = NV_DMA_TARGET_VRAM |
 260                                                  NV_DMA_ACCESS_RDWR,
 261                                         .start = 0,
 262                                         .limit = pfb->ram.size - 1,
 263                                         .conf0 = NVD0_DMA_CONF0_ENABLE | 0xfe |
 264                                                  NVD0_DMA_CONF0_PAGE_LP,
 265                                  }, sizeof(struct nv_dma_class), &object);
 266         return ret;
 267 }
 268
 269 static int
 270 nv50_dmac_create(struct nouveau_object *core, u32 bclass, u8 head,
 271                  void *data, u32 size, u64 syncbuf,
 272                  struct nv50_dmac *dmac)
 273 {
 274         struct nouveau_fb *pfb = nouveau_fb(core);
 275         struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS);
 276         struct nouveau_object *object;
 277         u32 pushbuf = *(u32 *)data;
 278         int ret;
 279
 280         mutex_init(&dmac->lock);
 281
 282         dmac->ptr = pci_alloc_consistent(nv_device(core)->pdev, PAGE_SIZE,
 283                                         &dmac->handle);
 284         if (!dmac->ptr)
 285                 return -ENOMEM;
 286
 287         ret = nouveau_object_new(client, NVDRM_DEVICE, pushbuf,
 288                                  NV_DMA_FROM_MEMORY_CLASS,
 289                                  &(struct nv_dma_class) {
 290                                         .flags = NV_DMA_TARGET_PCI_US |
 291                                                  NV_DMA_ACCESS_RD,
 292                                         .start = dmac->handle + 0x0000,
 293                                         .limit = dmac->handle + 0x0fff,
 294                                  }, sizeof(struct nv_dma_class), &object);
 295         if (ret)
 296                 return ret;
 297
 298         ret = nv50_chan_create(core, bclass, head, data, size, &dmac->base);
 299         if (ret)
 300                 return ret;
 301
 302         ret = nouveau_object_new(client, dmac->base.handle, NvEvoSync,
 303                                  NV_DMA_IN_MEMORY_CLASS,
 304                                  &(struct nv_dma_class) {
 305                                         .flags = NV_DMA_TARGET_VRAM |
 306                                                  NV_DMA_ACCESS_RDWR,
 307                                         .start = syncbuf + 0x0000,
 308                                         .limit = syncbuf + 0x0fff,
 309                                  }, sizeof(struct nv_dma_class), &object);
 310         if (ret)
 311                 return ret;
 312
 313         ret = nouveau_object_new(client, dmac->base.handle, NvEvoVRAM,
 314                                  NV_DMA_IN_MEMORY_CLASS,
 315                                  &(struct nv_dma_class) {
 316                                         .flags = NV_DMA_TARGET_VRAM |
 317                                                  NV_DMA_ACCESS_RDWR,
 318                                         .start = 0,
 319                                         .limit = pfb->ram.size - 1,
 320                                  }, sizeof(struct nv_dma_class), &object);
 321         if (ret)
 322                 return ret;
 323
 324         if (nv_device(core)->card_type < NV_C0)
 325                 ret = nv50_dmac_create_fbdma(core, dmac->base.handle);
 326         else
 327         if (nv_device(core)->card_type < NV_D0)
 328                 ret = nvc0_dmac_create_fbdma(core, dmac->base.handle);
 329         else
 330                 ret = nvd0_dmac_create_fbdma(core, dmac->base.handle);
 331         return ret;
 332 }
 333
 334 struct nv50_mast {
 335         struct nv50_dmac base;
 336 };
 337
 338 struct nv50_curs {
 339         struct nv50_pioc base;
 340 };
 341
 342 struct nv50_sync {
 343         struct nv50_dmac base;
 344         struct {
 345                 u32 offset;
 346                 u16 value;
 347         } sem;
 348 };
 349
 350 struct nv50_ovly {
 351         struct nv50_dmac base;
 352 };
 353
 354 struct nv50_oimm {
 355         struct nv50_pioc base;
 356 };
 357
 358 struct nv50_head {
 359         struct nouveau_crtc base;
 360         struct nv50_curs curs;
 361         struct nv50_sync sync;
 362         struct nv50_ovly ovly;
 363         struct nv50_oimm oimm;
 364 };
 365
 366 #define nv50_head(c) ((struct nv50_head *)nouveau_crtc(c))
 367 #define nv50_curs(c) (&nv50_head(c)->curs)
 368 #define nv50_sync(c) (&nv50_head(c)->sync)
 369 #define nv50_ovly(c) (&nv50_head(c)->ovly)
 370 #define nv50_oimm(c) (&nv50_head(c)->oimm)
 371 #define nv50_chan(c) (&(c)->base.base)
 372 #define nv50_vers(c) nv_mclass(nv50_chan(c)->user)
 373
 374 struct nv50_disp {
 375         struct nouveau_object *core;
 376         struct nv50_mast mast;
 377
 378         u32 modeset;
 379
 380         struct nouveau_bo *sync;
 381 };
 382
 383 static struct nv50_disp *
 384 nv50_disp(struct drm_device *dev)
 385 {
 386         return nouveau_display(dev)->priv;
 387 }
 388
 389 #define nv50_mast(d) (&nv50_disp(d)->mast)
 390
 391 static struct drm_crtc *
 392 nv50_display_crtc_get(struct drm_encoder *encoder)
 393 {
 394         return nouveau_encoder(encoder)->crtc;
 395 }
 396
 397 /******************************************************************************
 398  * EVO channel helpers
 399  *****************************************************************************/
 400 static u32 *
 401 evo_wait(void *evoc, int nr)
 402 {
 403         struct nv50_dmac *dmac = evoc;
 404         u32 put = nv_ro32(dmac->base.user, 0x0000) / 4;
 405
 406         mutex_lock(&dmac->lock);
 407         if (put + nr >= (PAGE_SIZE / 4) - 8) {
 408                 dmac->ptr[put] = 0x20000000;
 409
 410                 nv_wo32(dmac->base.user, 0x0000, 0x00000000);
 411                 if (!nv_wait(dmac->base.user, 0x0004, ~0, 0x00000000)) {
 412                         mutex_unlock(&dmac->lock);
 413                         NV_ERROR(dmac->base.user, "channel stalled\n");
 414                         return NULL;
 415                 }
 416
 417                 put = 0;
 418         }
 419
 420         return dmac->ptr + put;
 421 }
 422
 423 static void
 424 evo_kick(u32 *push, void *evoc)
 425 {
 426         struct nv50_dmac *dmac = evoc;
 427         nv_wo32(dmac->base.user, 0x0000, (push - dmac->ptr) << 2);
 428         mutex_unlock(&dmac->lock);
 429 }
 430
 431 #define evo_mthd(p,m,s) *((p)++) = (((s) << 18) | (m))
 432 #define evo_data(p,d)   *((p)++) = (d)
 433
 434 static bool
 435 evo_sync_wait(void *data)
 436 {
 437         if (nouveau_bo_rd32(data, EVO_MAST_NTFY) != 0x00000000)
 438                 return true;
 439         usleep_range(1, 2);
 440         return false;
 441 }
 442
 443 static int
 444 evo_sync(struct drm_device *dev)
 445 {
 446         struct nouveau_device *device = nouveau_dev(dev);
 447         struct nv50_disp *disp = nv50_disp(dev);
 448         struct nv50_mast *mast = nv50_mast(dev);
 449         u32 *push = evo_wait(mast, 8);
 450         if (push) {
 451                 nouveau_bo_wr32(disp->sync, EVO_MAST_NTFY, 0x00000000);
 452                 evo_mthd(push, 0x0084, 1);
 453                 evo_data(push, 0x80000000 | EVO_MAST_NTFY);
 454                 evo_mthd(push, 0x0080, 2);
 455                 evo_data(push, 0x00000000);
 456                 evo_data(push, 0x00000000);
 457                 evo_kick(push, mast);
 458                 if (nv_wait_cb(device, evo_sync_wait, disp->sync))
 459                         return 0;
 460         }
 461
 462         return -EBUSY;
 463 }
 464
 465 /******************************************************************************
 466  * Page flipping channel
 467  *****************************************************************************/
 468 struct nouveau_bo *
 469 nv50_display_crtc_sema(struct drm_device *dev, int crtc)
 470 {
 471         return nv50_disp(dev)->sync;
 472 }
 473
 474 void
 475 nv50_display_flip_stop(struct drm_crtc *crtc)
 476 {
 477         struct nv50_sync *sync = nv50_sync(crtc);
 478         u32 *push;
 479
 480         push = evo_wait(sync, 8);
 481         if (push) {
 482                 evo_mthd(push, 0x0084, 1);
 483                 evo_data(push, 0x00000000);
 484                 evo_mthd(push, 0x0094, 1);
 485                 evo_data(push, 0x00000000);
 486                 evo_mthd(push, 0x00c0, 1);
 487                 evo_data(push, 0x00000000);
 488                 evo_mthd(push, 0x0080, 1);
 489                 evo_data(push, 0x00000000);
 490                 evo_kick(push, sync);
 491         }
 492 }
 493
 494 int
 495 nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb,
 496                        struct nouveau_channel *chan, u32 swap_interval)
 497 {
 498         struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb);
 499         struct nv50_disp *disp = nv50_disp(crtc->dev);
 500         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 501         struct nv50_sync *sync = nv50_sync(crtc);
 502         u32 *push;
 503         int ret;
 504
 505         swap_interval <<= 4;
 506         if (swap_interval == 0)
 507                 swap_interval |= 0x100;
 508
 509         push = evo_wait(sync, 128);
 510         if (unlikely(push == NULL))
 511                 return -EBUSY;
 512
 513         /* synchronise with the rendering channel, if necessary */
 514         if (likely(chan)) {
 515                 ret = RING_SPACE(chan, 10);
 516                 if (ret)
 517                         return ret;
 518
 519                 if (nv_mclass(chan->object) < NV84_CHANNEL_IND_CLASS) {
 520                         BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 2);
 521                         OUT_RING  (chan, NvEvoSema0 + nv_crtc->index);
 522                         OUT_RING  (chan, sync->sem.offset);
 523                         BEGIN_NV04(chan, 0, NV11_SUBCHAN_SEMAPHORE_RELEASE, 1);
 524                         OUT_RING  (chan, 0xf00d0000 | sync->sem.value);
 525                         BEGIN_NV04(chan, 0, NV11_SUBCHAN_SEMAPHORE_OFFSET, 2);
 526                         OUT_RING  (chan, sync->sem.offset ^ 0x10);
 527                         OUT_RING  (chan, 0x74b1e000);
 528                         BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
 529                         OUT_RING  (chan, NvSema);
 530                 } else
 531                 if (nv_mclass(chan->object) < NVC0_CHANNEL_IND_CLASS) {
 532                         u64 offset = nv84_fence_crtc(chan, nv_crtc->index);
 533                         offset += sync->sem.offset;
 534
 535                         BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
 536                         OUT_RING  (chan, upper_32_bits(offset));
 537                         OUT_RING  (chan, lower_32_bits(offset));
 538                         OUT_RING  (chan, 0xf00d0000 | sync->sem.value);
 539                         OUT_RING  (chan, 0x00000002);
 540                         BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
 541                         OUT_RING  (chan, upper_32_bits(offset));
 542                         OUT_RING  (chan, lower_32_bits(offset ^ 0x10));
 543                         OUT_RING  (chan, 0x74b1e000);
 544                         OUT_RING  (chan, 0x00000001);
 545                 } else {
 546                         u64 offset = nv84_fence_crtc(chan, nv_crtc->index);
 547                         offset += sync->sem.offset;
 548
 549                         BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
 550                         OUT_RING  (chan, upper_32_bits(offset));
 551                         OUT_RING  (chan, lower_32_bits(offset));
 552                         OUT_RING  (chan, 0xf00d0000 | sync->sem.value);
 553                         OUT_RING  (chan, 0x00001002);
 554                         BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
 555                         OUT_RING  (chan, upper_32_bits(offset));
 556                         OUT_RING  (chan, lower_32_bits(offset ^ 0x10));
 557                         OUT_RING  (chan, 0x74b1e000);
 558                         OUT_RING  (chan, 0x00001001);
 559                 }
 560
 561                 FIRE_RING (chan);
 562         } else {
 563                 nouveau_bo_wr32(disp->sync, sync->sem.offset / 4,
 564                                 0xf00d0000 | sync->sem.value);
 565                 evo_sync(crtc->dev);
 566         }
 567
 568         /* queue the flip */
 569         evo_mthd(push, 0x0100, 1);
 570         evo_data(push, 0xfffe0000);
 571         evo_mthd(push, 0x0084, 1);
 572         evo_data(push, swap_interval);
 573         if (!(swap_interval & 0x00000100)) {
 574                 evo_mthd(push, 0x00e0, 1);
 575                 evo_data(push, 0x40000000);
 576         }
 577         evo_mthd(push, 0x0088, 4);
 578         evo_data(push, sync->sem.offset);
 579         evo_data(push, 0xf00d0000 | sync->sem.value);
 580         evo_data(push, 0x74b1e000);
 581         evo_data(push, NvEvoSync);
 582         evo_mthd(push, 0x00a0, 2);
 583         evo_data(push, 0x00000000);
 584         evo_data(push, 0x00000000);
 585         evo_mthd(push, 0x00c0, 1);
 586         evo_data(push, nv_fb->r_dma);
 587         evo_mthd(push, 0x0110, 2);
 588         evo_data(push, 0x00000000);
 589         evo_data(push, 0x00000000);
 590         if (nv50_vers(sync) < NVD0_DISP_SYNC_CLASS) {
 591                 evo_mthd(push, 0x0800, 5);
 592                 evo_data(push, nv_fb->nvbo->bo.offset >> 8);
 593                 evo_data(push, 0);
 594                 evo_data(push, (fb->height << 16) | fb->width);
 595                 evo_data(push, nv_fb->r_pitch);
 596                 evo_data(push, nv_fb->r_format);
 597         } else {
 598                 evo_mthd(push, 0x0400, 5);
 599                 evo_data(push, nv_fb->nvbo->bo.offset >> 8);
 600                 evo_data(push, 0);
 601                 evo_data(push, (fb->height << 16) | fb->width);
 602                 evo_data(push, nv_fb->r_pitch);
 603                 evo_data(push, nv_fb->r_format);
 604         }
 605         evo_mthd(push, 0x0080, 1);
 606         evo_data(push, 0x00000000);
 607         evo_kick(push, sync);
 608
 609         sync->sem.offset ^= 0x10;
 610         sync->sem.value++;
 611         return 0;
 612 }
 613
 614 /******************************************************************************
 615  * CRTC
 616  *****************************************************************************/
 617 static int
 618 nv50_crtc_set_dither(struct nouveau_crtc *nv_crtc, bool update)
 619 {
 620         struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
 621         struct nouveau_connector *nv_connector;
 622         struct drm_connector *connector;
 623         u32 *push, mode = 0x00;
 624
 625         nv_connector = nouveau_crtc_connector_get(nv_crtc);
 626         connector = &nv_connector->base;
 627         if (nv_connector->dithering_mode == DITHERING_MODE_AUTO) {
 628                 if (nv_crtc->base.fb->depth > connector->display_info.bpc * 3)
 629                         mode = DITHERING_MODE_DYNAMIC2X2;
 630         } else {
 631                 mode = nv_connector->dithering_mode;
 632         }
 633
 634         if (nv_connector->dithering_depth == DITHERING_DEPTH_AUTO) {
 635                 if (connector->display_info.bpc >= 8)
 636                         mode |= DITHERING_DEPTH_8BPC;
 637         } else {
 638                 mode |= nv_connector->dithering_depth;
 639         }
 640
 641         push = evo_wait(mast, 4);
 642         if (push) {
 643                 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
 644                         evo_mthd(push, 0x08a0 + (nv_crtc->index * 0x0400), 1);
 645                         evo_data(push, mode);
 646                 } else
 647                 if (nv50_vers(mast) < NVE0_DISP_MAST_CLASS) {
 648                         evo_mthd(push, 0x0490 + (nv_crtc->index * 0x0300), 1);
 649                         evo_data(push, mode);
 650                 } else {
 651                         evo_mthd(push, 0x04a0 + (nv_crtc->index * 0x0300), 1);
 652                         evo_data(push, mode);
 653                 }
 654
 655                 if (update) {
 656                         evo_mthd(push, 0x0080, 1);
 657                         evo_data(push, 0x00000000);
 658                 }
 659                 evo_kick(push, mast);
 660         }
 661
 662         return 0;
 663 }
 664
 665 static int
 666 nv50_crtc_set_scale(struct nouveau_crtc *nv_crtc, bool update)
 667 {
 668         struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
 669         struct drm_display_mode *omode, *umode = &nv_crtc->base.mode;
 670         struct drm_crtc *crtc = &nv_crtc->base;
 671         struct nouveau_connector *nv_connector;
 672         int mode = DRM_MODE_SCALE_NONE;
 673         u32 oX, oY, *push;
 674
 675         /* start off at the resolution we programmed the crtc for, this
 676          * effectively handles NONE/FULL scaling
 677          */
 678         nv_connector = nouveau_crtc_connector_get(nv_crtc);
 679         if (nv_connector && nv_connector->native_mode)
 680                 mode = nv_connector->scaling_mode;
 681
 682         if (mode != DRM_MODE_SCALE_NONE)
 683                 omode = nv_connector->native_mode;
 684         else
 685                 omode = umode;
 686
 687         oX = omode->hdisplay;
 688         oY = omode->vdisplay;
 689         if (omode->flags & DRM_MODE_FLAG_DBLSCAN)
 690                 oY *= 2;
 691
 692         /* add overscan compensation if necessary, will keep the aspect
 693          * ratio the same as the backend mode unless overridden by the
 694          * user setting both hborder and vborder properties.
 695          */
 696         if (nv_connector && ( nv_connector->underscan == UNDERSCAN_ON ||
 697                              (nv_connector->underscan == UNDERSCAN_AUTO &&
 698                               nv_connector->edid &&
 699                               drm_detect_hdmi_monitor(nv_connector->edid)))) {
 700                 u32 bX = nv_connector->underscan_hborder;
 701                 u32 bY = nv_connector->underscan_vborder;
 702                 u32 aspect = (oY << 19) / oX;
 703
 704                 if (bX) {
 705                         oX -= (bX * 2);
 706                         if (bY) oY -= (bY * 2);
 707                         else    oY  = ((oX * aspect) + (aspect / 2)) >> 19;
 708                 } else {
 709                         oX -= (oX >> 4) + 32;
 710                         if (bY) oY -= (bY * 2);
 711                         else    oY  = ((oX * aspect) + (aspect / 2)) >> 19;
 712                 }
 713         }
 714
 715         /* handle CENTER/ASPECT scaling, taking into account the areas
 716          * removed already for overscan compensation
 717          */
 718         switch (mode) {
 719         case DRM_MODE_SCALE_CENTER:
 720                 oX = min((u32)umode->hdisplay, oX);
 721                 oY = min((u32)umode->vdisplay, oY);
 722                 /* fall-through */
 723         case DRM_MODE_SCALE_ASPECT:
 724                 if (oY < oX) {
 725                         u32 aspect = (umode->hdisplay << 19) / umode->vdisplay;
 726                         oX = ((oY * aspect) + (aspect / 2)) >> 19;
 727                 } else {
 728                         u32 aspect = (umode->vdisplay << 19) / umode->hdisplay;
 729                         oY = ((oX * aspect) + (aspect / 2)) >> 19;
 730                 }
 731                 break;
 732         default:
 733                 break;
 734         }
 735
 736         push = evo_wait(mast, 8);
 737         if (push) {
 738                 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
 739                         /*XXX: SCALE_CTRL_ACTIVE??? */
 740                         evo_mthd(push, 0x08d8 + (nv_crtc->index * 0x400), 2);
 741                         evo_data(push, (oY << 16) | oX);
 742                         evo_data(push, (oY << 16) | oX);
 743                         evo_mthd(push, 0x08a4 + (nv_crtc->index * 0x400), 1);
 744                         evo_data(push, 0x00000000);
 745                         evo_mthd(push, 0x08c8 + (nv_crtc->index * 0x400), 1);
 746                         evo_data(push, umode->vdisplay << 16 | umode->hdisplay);
 747                 } else {
 748                         evo_mthd(push, 0x04c0 + (nv_crtc->index * 0x300), 3);
 749                         evo_data(push, (oY << 16) | oX);
 750                         evo_data(push, (oY << 16) | oX);
 751                         evo_data(push, (oY << 16) | oX);
 752                         evo_mthd(push, 0x0494 + (nv_crtc->index * 0x300), 1);
 753                         evo_data(push, 0x00000000);
 754                         evo_mthd(push, 0x04b8 + (nv_crtc->index * 0x300), 1);
 755                         evo_data(push, umode->vdisplay << 16 | umode->hdisplay);
 756                 }
 757
 758                 evo_kick(push, mast);
 759
 760                 if (update) {
 761                         nv50_display_flip_stop(crtc);
 762                         nv50_display_flip_next(crtc, crtc->fb, NULL, 1);
 763                 }
 764         }
 765
 766         return 0;
 767 }
 768
 769 static int
 770 nv50_crtc_set_color_vibrance(struct nouveau_crtc *nv_crtc, bool update)
 771 {
 772         struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
 773         u32 *push, hue, vib;
 774         int adj;
 775
 776         adj = (nv_crtc->color_vibrance > 0) ? 50 : 0;
 777         vib = ((nv_crtc->color_vibrance * 2047 + adj) / 100) & 0xfff;
 778         hue = ((nv_crtc->vibrant_hue * 2047) / 100) & 0xfff;
 779
 780         push = evo_wait(mast, 16);
 781         if (push) {
 782                 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
 783                         evo_mthd(push, 0x08a8 + (nv_crtc->index * 0x400), 1);
 784                         evo_data(push, (hue << 20) | (vib << 8));
 785                 } else {
 786                         evo_mthd(push, 0x0498 + (nv_crtc->index * 0x300), 1);
 787                         evo_data(push, (hue << 20) | (vib << 8));
 788                 }
 789
 790                 if (update) {
 791                         evo_mthd(push, 0x0080, 1);
 792                         evo_data(push, 0x00000000);
 793                 }
 794                 evo_kick(push, mast);
 795         }
 796
 797         return 0;
 798 }
 799
 800 static int
 801 nv50_crtc_set_image(struct nouveau_crtc *nv_crtc, struct drm_framebuffer *fb,
 802                     int x, int y, bool update)
 803 {
 804         struct nouveau_framebuffer *nvfb = nouveau_framebuffer(fb);
 805         struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
 806         u32 *push;
 807
 808         push = evo_wait(mast, 16);
 809         if (push) {
 810                 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
 811                         evo_mthd(push, 0x0860 + (nv_crtc->index * 0x400), 1);
 812                         evo_data(push, nvfb->nvbo->bo.offset >> 8);
 813                         evo_mthd(push, 0x0868 + (nv_crtc->index * 0x400), 3);
 814                         evo_data(push, (fb->height << 16) | fb->width);
 815                         evo_data(push, nvfb->r_pitch);
 816                         evo_data(push, nvfb->r_format);
 817                         evo_mthd(push, 0x08c0 + (nv_crtc->index * 0x400), 1);
 818                         evo_data(push, (y << 16) | x);
 819                         if (nv50_vers(mast) > NV50_DISP_MAST_CLASS) {
 820                                 evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
 821                                 evo_data(push, nvfb->r_dma);
 822                         }
 823                 } else {
 824                         evo_mthd(push, 0x0460 + (nv_crtc->index * 0x300), 1);
 825                         evo_data(push, nvfb->nvbo->bo.offset >> 8);
 826                         evo_mthd(push, 0x0468 + (nv_crtc->index * 0x300), 4);
 827                         evo_data(push, (fb->height << 16) | fb->width);
 828                         evo_data(push, nvfb->r_pitch);
 829                         evo_data(push, nvfb->r_format);
 830                         evo_data(push, nvfb->r_dma);
 831                         evo_mthd(push, 0x04b0 + (nv_crtc->index * 0x300), 1);
 832                         evo_data(push, (y << 16) | x);
 833                 }
 834
 835                 if (update) {
 836                         evo_mthd(push, 0x0080, 1);
 837                         evo_data(push, 0x00000000);
 838                 }
 839                 evo_kick(push, mast);
 840         }
 841
 842         nv_crtc->fb.tile_flags = nvfb->r_dma;
 843         return 0;
 844 }
 845
 846 static void
 847 nv50_crtc_cursor_show(struct nouveau_crtc *nv_crtc)
 848 {
 849         struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
 850         u32 *push = evo_wait(mast, 16);
 851         if (push) {
 852                 if (nv50_vers(mast) < NV84_DISP_MAST_CLASS) {
 853                         evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 2);
 854                         evo_data(push, 0x85000000);
 855                         evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8);
 856                 } else
 857                 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
 858                         evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 2);
 859                         evo_data(push, 0x85000000);
 860                         evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8);
 861                         evo_mthd(push, 0x089c + (nv_crtc->index * 0x400), 1);
 862                         evo_data(push, NvEvoVRAM);
 863                 } else {
 864                         evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 2);
 865                         evo_data(push, 0x85000000);
 866                         evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8);
 867                         evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1);
 868                         evo_data(push, NvEvoVRAM);
 869                 }
 870                 evo_kick(push, mast);
 871         }
 872 }
 873
 874 static void
 875 nv50_crtc_cursor_hide(struct nouveau_crtc *nv_crtc)
 876 {
 877         struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
 878         u32 *push = evo_wait(mast, 16);
 879         if (push) {
 880                 if (nv50_vers(mast) < NV84_DISP_MAST_CLASS) {
 881                         evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 1);
 882                         evo_data(push, 0x05000000);
 883                 } else
 884                 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
 885                         evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 1);
 886                         evo_data(push, 0x05000000);
 887                         evo_mthd(push, 0x089c + (nv_crtc->index * 0x400), 1);
 888                         evo_data(push, 0x00000000);
 889                 } else {
 890                         evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 1);
 891                         evo_data(push, 0x05000000);
 892                         evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1);
 893                         evo_data(push, 0x00000000);
 894                 }
 895                 evo_kick(push, mast);
 896         }
 897 }
 898
 899 static void
 900 nv50_crtc_cursor_show_hide(struct nouveau_crtc *nv_crtc, bool show, bool update)
 901 {
 902         struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
 903
 904         if (show)
 905                 nv50_crtc_cursor_show(nv_crtc);
 906         else
 907                 nv50_crtc_cursor_hide(nv_crtc);
 908
 909         if (update) {
 910                 u32 *push = evo_wait(mast, 2);
 911                 if (push) {
 912                         evo_mthd(push, 0x0080, 1);
 913                         evo_data(push, 0x00000000);
 914                         evo_kick(push, mast);
 915                 }
 916         }
 917 }
 918
 919 static void
 920 nv50_crtc_dpms(struct drm_crtc *crtc, int mode)
 921 {
 922 }
 923
 924 static void
 925 nv50_crtc_prepare(struct drm_crtc *crtc)
 926 {
 927         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 928         struct nv50_mast *mast = nv50_mast(crtc->dev);
 929         u32 *push;
 930
 931         nv50_display_flip_stop(crtc);
 932
 933         push = evo_wait(mast, 2);
 934         if (push) {
 935                 if (nv50_vers(mast) < NV84_DISP_MAST_CLASS) {
 936                         evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
 937                         evo_data(push, 0x00000000);
 938                         evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 1);
 939                         evo_data(push, 0x40000000);
 940                 } else
 941                 if (nv50_vers(mast) <  NVD0_DISP_MAST_CLASS) {
 942                         evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
 943                         evo_data(push, 0x00000000);
 944                         evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 1);
 945                         evo_data(push, 0x40000000);
 946                         evo_mthd(push, 0x085c + (nv_crtc->index * 0x400), 1);
 947                         evo_data(push, 0x00000000);
 948                 } else {
 949                         evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1);
 950                         evo_data(push, 0x00000000);
 951                         evo_mthd(push, 0x0440 + (nv_crtc->index * 0x300), 1);
 952                         evo_data(push, 0x03000000);
 953                         evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1);
 954                         evo_data(push, 0x00000000);
 955                 }
 956
 957                 evo_kick(push, mast);
 958         }
 959
 960         nv50_crtc_cursor_show_hide(nv_crtc, false, false);
 961 }
 962
 963 static void
 964 nv50_crtc_commit(struct drm_crtc *crtc)
 965 {
 966         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 967         struct nv50_mast *mast = nv50_mast(crtc->dev);
 968         u32 *push;
 969
 970         push = evo_wait(mast, 32);
 971         if (push) {
 972                 if (nv50_vers(mast) < NV84_DISP_MAST_CLASS) {
 973                         evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
 974                         evo_data(push, NvEvoVRAM_LP);
 975                         evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 2);
 976                         evo_data(push, 0xc0000000);
 977                         evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8);
 978                 } else
 979                 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
 980                         evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
 981                         evo_data(push, nv_crtc->fb.tile_flags);
 982                         evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 2);
 983                         evo_data(push, 0xc0000000);
 984                         evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8);
 985                         evo_mthd(push, 0x085c + (nv_crtc->index * 0x400), 1);
 986                         evo_data(push, NvEvoVRAM);
 987                 } else {
 988                         evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1);
 989                         evo_data(push, nv_crtc->fb.tile_flags);
 990                         evo_mthd(push, 0x0440 + (nv_crtc->index * 0x300), 4);
 991                         evo_data(push, 0x83000000);
 992                         evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8);
 993                         evo_data(push, 0x00000000);
 994                         evo_data(push, 0x00000000);
 995                         evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1);
 996                         evo_data(push, NvEvoVRAM);
 997                         evo_mthd(push, 0x0430 + (nv_crtc->index * 0x300), 1);
 998                         evo_data(push, 0xffffff00);
 999                 }
1000
1001                 evo_kick(push, mast);
1002         }
1003
1004         nv50_crtc_cursor_show_hide(nv_crtc, nv_crtc->cursor.visible, true);
1005         nv50_display_flip_next(crtc, crtc->fb, NULL, 1);
1006 }
1007
1008 static bool
1009 nv50_crtc_mode_fixup(struct drm_crtc *crtc, const struct drm_display_mode *mode,
1010                      struct drm_display_mode *adjusted_mode)
1011 {
1012         return true;
1013 }
1014
1015 static int
1016 nv50_crtc_swap_fbs(struct drm_crtc *crtc, struct drm_framebuffer *old_fb)
1017 {
1018         struct nouveau_framebuffer *nvfb = nouveau_framebuffer(crtc->fb);
1019         int ret;
1020
1021         ret = nouveau_bo_pin(nvfb->nvbo, TTM_PL_FLAG_VRAM);
1022         if (ret)
1023                 return ret;
1024
1025         if (old_fb) {
1026                 nvfb = nouveau_framebuffer(old_fb);
1027                 nouveau_bo_unpin(nvfb->nvbo);
1028         }
1029
1030         return 0;
1031 }
1032
1033 static int
1034 nv50_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *umode,
1035                    struct drm_display_mode *mode, int x, int y,
1036                    struct drm_framebuffer *old_fb)
1037 {
1038         struct nv50_mast *mast = nv50_mast(crtc->dev);
1039         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1040         struct nouveau_connector *nv_connector;
1041         u32 ilace = (mode->flags & DRM_MODE_FLAG_INTERLACE) ? 2 : 1;
1042         u32 vscan = (mode->flags & DRM_MODE_FLAG_DBLSCAN) ? 2 : 1;
1043         u32 hactive, hsynce, hbackp, hfrontp, hblanke, hblanks;
1044         u32 vactive, vsynce, vbackp, vfrontp, vblanke, vblanks;
1045         u32 vblan2e = 0, vblan2s = 1;
1046         u32 *push;
1047         int ret;
1048
1049         hactive = mode->htotal;
1050         hsynce  = mode->hsync_end - mode->hsync_start - 1;
1051         hbackp  = mode->htotal - mode->hsync_end;
1052         hblanke = hsynce + hbackp;
1053         hfrontp = mode->hsync_start - mode->hdisplay;
1054         hblanks = mode->htotal - hfrontp - 1;
1055
1056         vactive = mode->vtotal * vscan / ilace;
1057         vsynce  = ((mode->vsync_end - mode->vsync_start) * vscan / ilace) - 1;
1058         vbackp  = (mode->vtotal - mode->vsync_end) * vscan / ilace;
1059         vblanke = vsynce + vbackp;
1060         vfrontp = (mode->vsync_start - mode->vdisplay) * vscan / ilace;
1061         vblanks = vactive - vfrontp - 1;
1062         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1063                 vblan2e = vactive + vsynce + vbackp;
1064                 vblan2s = vblan2e + (mode->vdisplay * vscan / ilace);
1065                 vactive = (vactive * 2) + 1;
1066         }
1067
1068         ret = nv50_crtc_swap_fbs(crtc, old_fb);
1069         if (ret)
1070                 return ret;
1071
1072         push = evo_wait(mast, 64);
1073         if (push) {
1074                 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
1075                         evo_mthd(push, 0x0804 + (nv_crtc->index * 0x400), 2);
1076                         evo_data(push, 0x00800000 | mode->clock);
1077                         evo_data(push, (ilace == 2) ? 2 : 0);
1078                         evo_mthd(push, 0x0810 + (nv_crtc->index * 0x400), 6);
1079                         evo_data(push, 0x00000000);
1080                         evo_data(push, (vactive << 16) | hactive);
1081                         evo_data(push, ( vsynce << 16) | hsynce);
1082                         evo_data(push, (vblanke << 16) | hblanke);
1083                         evo_data(push, (vblanks << 16) | hblanks);
1084                         evo_data(push, (vblan2e << 16) | vblan2s);
1085                         evo_mthd(push, 0x082c + (nv_crtc->index * 0x400), 1);
1086                         evo_data(push, 0x00000000);
1087                         evo_mthd(push, 0x0900 + (nv_crtc->index * 0x400), 2);
1088                         evo_data(push, 0x00000311);
1089                         evo_data(push, 0x00000100);
1090                 } else {
1091                         evo_mthd(push, 0x0410 + (nv_crtc->index * 0x300), 6);
1092                         evo_data(push, 0x00000000);
1093                         evo_data(push, (vactive << 16) | hactive);
1094                         evo_data(push, ( vsynce << 16) | hsynce);
1095                         evo_data(push, (vblanke << 16) | hblanke);
1096                         evo_data(push, (vblanks << 16) | hblanks);
1097                         evo_data(push, (vblan2e << 16) | vblan2s);
1098                         evo_mthd(push, 0x042c + (nv_crtc->index * 0x300), 1);
1099                         evo_data(push, 0x00000000); /* ??? */
1100                         evo_mthd(push, 0x0450 + (nv_crtc->index * 0x300), 3);
1101                         evo_data(push, mode->clock * 1000);
1102                         evo_data(push, 0x00200000); /* ??? */
1103                         evo_data(push, mode->clock * 1000);
1104                         evo_mthd(push, 0x04d0 + (nv_crtc->index * 0x300), 2);
1105                         evo_data(push, 0x00000311);
1106                         evo_data(push, 0x00000100);
1107                 }
1108
1109                 evo_kick(push, mast);
1110         }
1111
1112         nv_connector = nouveau_crtc_connector_get(nv_crtc);
1113         nv50_crtc_set_dither(nv_crtc, false);
1114         nv50_crtc_set_scale(nv_crtc, false);
1115         nv50_crtc_set_color_vibrance(nv_crtc, false);
1116         nv50_crtc_set_image(nv_crtc, crtc->fb, x, y, false);
1117         return 0;
1118 }
1119
1120 static int
1121 nv50_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
1122                         struct drm_framebuffer *old_fb)
1123 {
1124         struct nouveau_drm *drm = nouveau_drm(crtc->dev);
1125         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1126         int ret;
1127
1128         if (!crtc->fb) {
1129                 NV_DEBUG(drm, "No FB bound\n");
1130                 return 0;
1131         }
1132
1133         ret = nv50_crtc_swap_fbs(crtc, old_fb);
1134         if (ret)
1135                 return ret;
1136
1137         nv50_display_flip_stop(crtc);
1138         nv50_crtc_set_image(nv_crtc, crtc->fb, x, y, true);
1139         nv50_display_flip_next(crtc, crtc->fb, NULL, 1);
1140         return 0;
1141 }
1142
1143 static int
1144 nv50_crtc_mode_set_base_atomic(struct drm_crtc *crtc,
1145                                struct drm_framebuffer *fb, int x, int y,
1146                                enum mode_set_atomic state)
1147 {
1148         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1149         nv50_display_flip_stop(crtc);
1150         nv50_crtc_set_image(nv_crtc, fb, x, y, true);
1151         return 0;
1152 }
1153
1154 static void
1155 nv50_crtc_lut_load(struct drm_crtc *crtc)
1156 {
1157         struct nv50_disp *disp = nv50_disp(crtc->dev);
1158         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1159         void __iomem *lut = nvbo_kmap_obj_iovirtual(nv_crtc->lut.nvbo);
1160         int i;
1161
1162         for (i = 0; i < 256; i++) {
1163                 u16 r = nv_crtc->lut.r[i] >> 2;
1164                 u16 g = nv_crtc->lut.g[i] >> 2;
1165                 u16 b = nv_crtc->lut.b[i] >> 2;
1166
1167                 if (nv_mclass(disp->core) < NVD0_DISP_CLASS) {
1168                         writew(r + 0x0000, lut + (i * 0x08) + 0);
1169                         writew(g + 0x0000, lut + (i * 0x08) + 2);
1170                         writew(b + 0x0000, lut + (i * 0x08) + 4);
1171                 } else {
1172                         writew(r + 0x6000, lut + (i * 0x20) + 0);
1173                         writew(g + 0x6000, lut + (i * 0x20) + 2);
1174                         writew(b + 0x6000, lut + (i * 0x20) + 4);
1175                 }
1176         }
1177 }
1178
1179 static int
1180 nv50_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
1181                      uint32_t handle, uint32_t width, uint32_t height)
1182 {
1183         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1184         struct drm_device *dev = crtc->dev;
1185         struct drm_gem_object *gem;
1186         struct nouveau_bo *nvbo;
1187         bool visible = (handle != 0);
1188         int i, ret = 0;
1189
1190         if (visible) {
1191                 if (width != 64 || height != 64)
1192                         return -EINVAL;
1193
1194                 gem = drm_gem_object_lookup(dev, file_priv, handle);
1195                 if (unlikely(!gem))
1196                         return -ENOENT;
1197                 nvbo = nouveau_gem_object(gem);
1198
1199                 ret = nouveau_bo_map(nvbo);
1200                 if (ret == 0) {
1201                         for (i = 0; i < 64 * 64; i++) {
1202                                 u32 v = nouveau_bo_rd32(nvbo, i);
1203                                 nouveau_bo_wr32(nv_crtc->cursor.nvbo, i, v);
1204                         }
1205                         nouveau_bo_unmap(nvbo);
1206                 }
1207
1208                 drm_gem_object_unreference_unlocked(gem);
1209         }
1210
1211         if (visible != nv_crtc->cursor.visible) {
1212                 nv50_crtc_cursor_show_hide(nv_crtc, visible, true);
1213                 nv_crtc->cursor.visible = visible;
1214         }
1215
1216         return ret;
1217 }
1218
1219 static int
1220 nv50_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
1221 {
1222         struct nv50_curs *curs = nv50_curs(crtc);
1223         struct nv50_chan *chan = nv50_chan(curs);
1224         nv_wo32(chan->user, 0x0084, (y << 16) | (x & 0xffff));
1225         nv_wo32(chan->user, 0x0080, 0x00000000);
1226         return 0;
1227 }
1228
1229 static void
1230 nv50_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
1231                     uint32_t start, uint32_t size)
1232 {
1233         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1234         u32 end = max(start + size, (u32)256);
1235         u32 i;
1236
1237         for (i = start; i < end; i++) {
1238                 nv_crtc->lut.r[i] = r[i];
1239                 nv_crtc->lut.g[i] = g[i];
1240                 nv_crtc->lut.b[i] = b[i];
1241         }
1242
1243         nv50_crtc_lut_load(crtc);
1244 }
1245
1246 static void
1247 nv50_crtc_destroy(struct drm_crtc *crtc)
1248 {
1249         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1250         struct nv50_disp *disp = nv50_disp(crtc->dev);
1251         struct nv50_head *head = nv50_head(crtc);
1252         nv50_dmac_destroy(disp->core, &head->ovly.base);
1253         nv50_pioc_destroy(disp->core, &head->oimm.base);
1254         nv50_dmac_destroy(disp->core, &head->sync.base);
1255         nv50_pioc_destroy(disp->core, &head->curs.base);
1256         nouveau_bo_unmap(nv_crtc->cursor.nvbo);
1257         if (nv_crtc->cursor.nvbo)
1258                 nouveau_bo_unpin(nv_crtc->cursor.nvbo);
1259         nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo);
1260         nouveau_bo_unmap(nv_crtc->lut.nvbo);
1261         if (nv_crtc->lut.nvbo)
1262                 nouveau_bo_unpin(nv_crtc->lut.nvbo);
1263         nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo);
1264         drm_crtc_cleanup(crtc);
1265         kfree(crtc);
1266 }
1267
1268 static const struct drm_crtc_helper_funcs nv50_crtc_hfunc = {
1269         .dpms = nv50_crtc_dpms,
1270         .prepare = nv50_crtc_prepare,
1271         .commit = nv50_crtc_commit,
1272         .mode_fixup = nv50_crtc_mode_fixup,
1273         .mode_set = nv50_crtc_mode_set,
1274         .mode_set_base = nv50_crtc_mode_set_base,
1275         .mode_set_base_atomic = nv50_crtc_mode_set_base_atomic,
1276         .load_lut = nv50_crtc_lut_load,
1277 };
1278
1279 static const struct drm_crtc_funcs nv50_crtc_func = {
1280         .cursor_set = nv50_crtc_cursor_set,
1281         .cursor_move = nv50_crtc_cursor_move,
1282         .gamma_set = nv50_crtc_gamma_set,
1283         .set_config = drm_crtc_helper_set_config,
1284         .destroy = nv50_crtc_destroy,
1285         .page_flip = nouveau_crtc_page_flip,
1286 };
1287
1288 static void
1289 nv50_cursor_set_pos(struct nouveau_crtc *nv_crtc, int x, int y)
1290 {
1291 }
1292
1293 static void
1294 nv50_cursor_set_offset(struct nouveau_crtc *nv_crtc, uint32_t offset)
1295 {
1296 }
1297
1298 static int
1299 nv50_crtc_create(struct drm_device *dev, struct nouveau_object *core, int index)
1300 {
1301         struct nv50_disp *disp = nv50_disp(dev);
1302         struct nv50_head *head;
1303         struct drm_crtc *crtc;
1304         int ret, i;
1305
1306         head = kzalloc(sizeof(*head), GFP_KERNEL);
1307         if (!head)
1308                 return -ENOMEM;
1309
1310         head->base.index = index;
1311         head->base.set_dither = nv50_crtc_set_dither;
1312         head->base.set_scale = nv50_crtc_set_scale;
1313         head->base.set_color_vibrance = nv50_crtc_set_color_vibrance;
1314         head->base.color_vibrance = 50;
1315         head->base.vibrant_hue = 0;
1316         head->base.cursor.set_offset = nv50_cursor_set_offset;
1317         head->base.cursor.set_pos = nv50_cursor_set_pos;
1318         for (i = 0; i < 256; i++) {
1319                 head->base.lut.r[i] = i << 8;
1320                 head->base.lut.g[i] = i << 8;
1321                 head->base.lut.b[i] = i << 8;
1322         }
1323
1324         crtc = &head->base.base;
1325         drm_crtc_init(dev, crtc, &nv50_crtc_func);
1326         drm_crtc_helper_add(crtc, &nv50_crtc_hfunc);
1327         drm_mode_crtc_set_gamma_size(crtc, 256);
1328
1329         ret = nouveau_bo_new(dev, 8192, 0x100, TTM_PL_FLAG_VRAM,
1330                              0, 0x0000, NULL, &head->base.lut.nvbo);
1331         if (!ret) {
1332                 ret = nouveau_bo_pin(head->base.lut.nvbo, TTM_PL_FLAG_VRAM);
1333                 if (!ret) {
1334                         ret = nouveau_bo_map(head->base.lut.nvbo);
1335                         if (ret)
1336                                 nouveau_bo_unpin(head->base.lut.nvbo);
1337                 }
1338                 if (ret)
1339                         nouveau_bo_ref(NULL, &head->base.lut.nvbo);
1340         }
1341
1342         if (ret)
1343                 goto out;
1344
1345         nv50_crtc_lut_load(crtc);
1346
1347         /* allocate cursor resources */
1348         ret = nv50_pioc_create(disp->core, NV50_DISP_CURS_CLASS, index,
1349                               &(struct nv50_display_curs_class) {
1350                                         .head = index,
1351                               }, sizeof(struct nv50_display_curs_class),
1352                               &head->curs.base);
1353         if (ret)
1354                 goto out;
1355
1356         ret = nouveau_bo_new(dev, 64 * 64 * 4, 0x100, TTM_PL_FLAG_VRAM,
1357                              0, 0x0000, NULL, &head->base.cursor.nvbo);
1358         if (!ret) {
1359                 ret = nouveau_bo_pin(head->base.cursor.nvbo, TTM_PL_FLAG_VRAM);
1360                 if (!ret) {
1361                         ret = nouveau_bo_map(head->base.cursor.nvbo);
1362                         if (ret)
1363                                 nouveau_bo_unpin(head->base.lut.nvbo);
1364                 }
1365                 if (ret)
1366                         nouveau_bo_ref(NULL, &head->base.cursor.nvbo);
1367         }
1368
1369         if (ret)
1370                 goto out;
1371
1372         /* allocate page flip / sync resources */
1373         ret = nv50_dmac_create(disp->core, NV50_DISP_SYNC_CLASS, index,
1374                               &(struct nv50_display_sync_class) {
1375                                         .pushbuf = EVO_PUSH_HANDLE(SYNC, index),
1376                                         .head = index,
1377                               }, sizeof(struct nv50_display_sync_class),
1378                               disp->sync->bo.offset, &head->sync.base);
1379         if (ret)
1380                 goto out;
1381
1382         head->sync.sem.offset = EVO_SYNC(1 + index, 0x00);
1383
1384         /* allocate overlay resources */
1385         ret = nv50_pioc_create(disp->core, NV50_DISP_OIMM_CLASS, index,
1386                               &(struct nv50_display_oimm_class) {
1387                                         .head = index,
1388                               }, sizeof(struct nv50_display_oimm_class),
1389                               &head->oimm.base);
1390         if (ret)
1391                 goto out;
1392
1393         ret = nv50_dmac_create(disp->core, NV50_DISP_OVLY_CLASS, index,
1394                               &(struct nv50_display_ovly_class) {
1395                                         .pushbuf = EVO_PUSH_HANDLE(OVLY, index),
1396                                         .head = index,
1397                               }, sizeof(struct nv50_display_ovly_class),
1398                               disp->sync->bo.offset, &head->ovly.base);
1399         if (ret)
1400                 goto out;
1401
1402 out:
1403         if (ret)
1404                 nv50_crtc_destroy(crtc);
1405         return ret;
1406 }
1407
1408 /******************************************************************************
1409  * DAC
1410  *****************************************************************************/
1411 static void
1412 nv50_dac_dpms(struct drm_encoder *encoder, int mode)
1413 {
1414         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1415         struct nv50_disp *disp = nv50_disp(encoder->dev);
1416         int or = nv_encoder->or;
1417         u32 dpms_ctrl;
1418
1419         dpms_ctrl = 0x00000000;
1420         if (mode == DRM_MODE_DPMS_STANDBY || mode == DRM_MODE_DPMS_OFF)
1421                 dpms_ctrl |= 0x00000001;
1422         if (mode == DRM_MODE_DPMS_SUSPEND || mode == DRM_MODE_DPMS_OFF)
1423                 dpms_ctrl |= 0x00000004;
1424
1425         nv_call(disp->core, NV50_DISP_DAC_PWR + or, dpms_ctrl);
1426 }
1427
1428 static bool
1429 nv50_dac_mode_fixup(struct drm_encoder *encoder,
1430                     const struct drm_display_mode *mode,
1431                     struct drm_display_mode *adjusted_mode)
1432 {
1433         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1434         struct nouveau_connector *nv_connector;
1435
1436         nv_connector = nouveau_encoder_connector_get(nv_encoder);
1437         if (nv_connector && nv_connector->native_mode) {
1438                 if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) {
1439                         int id = adjusted_mode->base.id;
1440                         *adjusted_mode = *nv_connector->native_mode;
1441                         adjusted_mode->base.id = id;
1442                 }
1443         }
1444
1445         return true;
1446 }
1447
1448 static void
1449 nv50_dac_commit(struct drm_encoder *encoder)
1450 {
1451 }
1452
1453 static void
1454 nv50_dac_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
1455                   struct drm_display_mode *adjusted_mode)
1456 {
1457         struct nv50_mast *mast = nv50_mast(encoder->dev);
1458         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1459         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1460         u32 *push;
1461
1462         nv50_dac_dpms(encoder, DRM_MODE_DPMS_ON);
1463
1464         push = evo_wait(mast, 8);
1465         if (push) {
1466                 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
1467                         u32 syncs = 0x00000000;
1468
1469                         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1470                                 syncs |= 0x00000001;
1471                         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1472                                 syncs |= 0x00000002;
1473
1474                         evo_mthd(push, 0x0400 + (nv_encoder->or * 0x080), 2);
1475                         evo_data(push, 1 << nv_crtc->index);
1476                         evo_data(push, syncs);
1477                 } else {
1478                         u32 magic = 0x31ec6000 | (nv_crtc->index << 25);
1479                         u32 syncs = 0x00000001;
1480
1481                         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1482                                 syncs |= 0x00000008;
1483                         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1484                                 syncs |= 0x00000010;
1485
1486                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1487                                 magic |= 0x00000001;
1488
1489                         evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2);
1490                         evo_data(push, syncs);
1491                         evo_data(push, magic);
1492                         evo_mthd(push, 0x0180 + (nv_encoder->or * 0x020), 1);
1493                         evo_data(push, 1 << nv_crtc->index);
1494                 }
1495
1496                 evo_kick(push, mast);
1497         }
1498
1499         nv_encoder->crtc = encoder->crtc;
1500 }
1501
1502 static void
1503 nv50_dac_disconnect(struct drm_encoder *encoder)
1504 {
1505         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1506         struct nv50_mast *mast = nv50_mast(encoder->dev);
1507         const int or = nv_encoder->or;
1508         u32 *push;
1509
1510         if (nv_encoder->crtc) {
1511                 nv50_crtc_prepare(nv_encoder->crtc);
1512
1513                 push = evo_wait(mast, 4);
1514                 if (push) {
1515                         if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
1516                                 evo_mthd(push, 0x0400 + (or * 0x080), 1);
1517                                 evo_data(push, 0x00000000);
1518                         } else {
1519                                 evo_mthd(push, 0x0180 + (or * 0x020), 1);
1520                                 evo_data(push, 0x00000000);
1521                         }
1522                         evo_kick(push, mast);
1523                 }
1524         }
1525
1526         nv_encoder->crtc = NULL;
1527 }
1528
1529 static enum drm_connector_status
1530 nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1531 {
1532         struct nv50_disp *disp = nv50_disp(encoder->dev);
1533         int ret, or = nouveau_encoder(encoder)->or;
1534         u32 load = 0;
1535
1536         ret = nv_exec(disp->core, NV50_DISP_DAC_LOAD + or, &load, sizeof(load));
1537         if (ret || load != 7)
1538                 return connector_status_disconnected;
1539
1540         return connector_status_connected;
1541 }
1542
1543 static void
1544 nv50_dac_destroy(struct drm_encoder *encoder)
1545 {
1546         drm_encoder_cleanup(encoder);
1547         kfree(encoder);
1548 }
1549
1550 static const struct drm_encoder_helper_funcs nv50_dac_hfunc = {
1551         .dpms = nv50_dac_dpms,
1552         .mode_fixup = nv50_dac_mode_fixup,
1553         .prepare = nv50_dac_disconnect,
1554         .commit = nv50_dac_commit,
1555         .mode_set = nv50_dac_mode_set,
1556         .disable = nv50_dac_disconnect,
1557         .get_crtc = nv50_display_crtc_get,
1558         .detect = nv50_dac_detect
1559 };
1560
1561 static const struct drm_encoder_funcs nv50_dac_func = {
1562         .destroy = nv50_dac_destroy,
1563 };
1564
1565 static int
1566 nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe)
1567 {
1568         struct nouveau_drm *drm = nouveau_drm(connector->dev);
1569         struct nouveau_i2c *i2c = nouveau_i2c(drm->device);
1570         struct nouveau_encoder *nv_encoder;
1571         struct drm_encoder *encoder;
1572         int type = DRM_MODE_ENCODER_DAC;
1573
1574         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1575         if (!nv_encoder)
1576                 return -ENOMEM;
1577         nv_encoder->dcb = dcbe;
1578         nv_encoder->or = ffs(dcbe->or) - 1;
1579         nv_encoder->i2c = i2c->find(i2c, dcbe->i2c_index);
1580
1581         encoder = to_drm_encoder(nv_encoder);
1582         encoder->possible_crtcs = dcbe->heads;
1583         encoder->possible_clones = 0;
1584         drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type);
1585         drm_encoder_helper_add(encoder, &nv50_dac_hfunc);
1586
1587         drm_mode_connector_attach_encoder(connector, encoder);
1588         return 0;
1589 }
1590
1591 /******************************************************************************
1592  * Audio
1593  *****************************************************************************/
1594 static void
1595 nv50_audio_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode)
1596 {
1597         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1598         struct nouveau_connector *nv_connector;
1599         struct nv50_disp *disp = nv50_disp(encoder->dev);
1600
1601         nv_connector = nouveau_encoder_connector_get(nv_encoder);
1602         if (!drm_detect_monitor_audio(nv_connector->edid))
1603                 return;
1604
1605         drm_edid_to_eld(&nv_connector->base, nv_connector->edid);
1606
1607         nv_exec(disp->core, NVA3_DISP_SOR_HDA_ELD + nv_encoder->or,
1608                             nv_connector->base.eld,
1609                             nv_connector->base.eld[2] * 4);
1610 }
1611
1612 static void
1613 nv50_audio_disconnect(struct drm_encoder *encoder)
1614 {
1615         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1616         struct nv50_disp *disp = nv50_disp(encoder->dev);
1617
1618         nv_exec(disp->core, NVA3_DISP_SOR_HDA_ELD + nv_encoder->or, NULL, 0);
1619 }
1620
1621 /******************************************************************************
1622  * HDMI
1623  *****************************************************************************/
1624 static void
1625 nv50_hdmi_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode)
1626 {
1627         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1628         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1629         struct nouveau_connector *nv_connector;
1630         struct nv50_disp *disp = nv50_disp(encoder->dev);
1631         const u32 moff = (nv_crtc->index << 3) | nv_encoder->or;
1632         u32 rekey = 56; /* binary driver, and tegra constant */
1633         u32 max_ac_packet;
1634
1635         nv_connector = nouveau_encoder_connector_get(nv_encoder);
1636         if (!drm_detect_hdmi_monitor(nv_connector->edid))
1637                 return;
1638
1639         max_ac_packet  = mode->htotal - mode->hdisplay;
1640         max_ac_packet -= rekey;
1641         max_ac_packet -= 18; /* constant from tegra */
1642         max_ac_packet /= 32;
1643
1644         nv_call(disp->core, NV84_DISP_SOR_HDMI_PWR + moff,
1645                             NV84_DISP_SOR_HDMI_PWR_STATE_ON |
1646                             (max_ac_packet << 16) | rekey);
1647
1648         nv50_audio_mode_set(encoder, mode);
1649 }
1650
1651 static void
1652 nv50_hdmi_disconnect(struct drm_encoder *encoder)
1653 {
1654         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1655         struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc);
1656         struct nv50_disp *disp = nv50_disp(encoder->dev);
1657         const u32 moff = (nv_crtc->index << 3) | nv_encoder->or;
1658
1659         nv50_audio_disconnect(encoder);
1660
1661         nv_call(disp->core, NV84_DISP_SOR_HDMI_PWR + moff, 0x00000000);
1662 }
1663
1664 /******************************************************************************
1665  * SOR
1666  *****************************************************************************/
1667 static void
1668 nv50_sor_dpms(struct drm_encoder *encoder, int mode)
1669 {
1670         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1671         struct drm_device *dev = encoder->dev;
1672         struct nv50_disp *disp = nv50_disp(dev);
1673         struct drm_encoder *partner;
1674         int or = nv_encoder->or;
1675
1676         nv_encoder->last_dpms = mode;
1677
1678         list_for_each_entry(partner, &dev->mode_config.encoder_list, head) {
1679                 struct nouveau_encoder *nv_partner = nouveau_encoder(partner);
1680
1681                 if (partner->encoder_type != DRM_MODE_ENCODER_TMDS)
1682                         continue;
1683
1684                 if (nv_partner != nv_encoder &&
1685                     nv_partner->dcb->or == nv_encoder->dcb->or) {
1686                         if (nv_partner->last_dpms == DRM_MODE_DPMS_ON)
1687                                 return;
1688                         break;
1689                 }
1690         }
1691
1692         nv_call(disp->core, NV50_DISP_SOR_PWR + or, (mode == DRM_MODE_DPMS_ON));
1693 }
1694
1695 static bool
1696 nv50_sor_mode_fixup(struct drm_encoder *encoder,
1697                     const struct drm_display_mode *mode,
1698                     struct drm_display_mode *adjusted_mode)
1699 {
1700         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1701         struct nouveau_connector *nv_connector;
1702
1703         nv_connector = nouveau_encoder_connector_get(nv_encoder);
1704         if (nv_connector && nv_connector->native_mode) {
1705                 if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) {
1706                         int id = adjusted_mode->base.id;
1707                         *adjusted_mode = *nv_connector->native_mode;
1708                         adjusted_mode->base.id = id;
1709                 }
1710         }
1711
1712         return true;
1713 }
1714
1715 static void
1716 nv50_sor_disconnect(struct drm_encoder *encoder)
1717 {
1718         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1719         struct nv50_mast *mast = nv50_mast(encoder->dev);
1720         const int or = nv_encoder->or;
1721         u32 *push;
1722
1723         if (nv_encoder->crtc) {
1724                 nv50_crtc_prepare(nv_encoder->crtc);
1725
1726                 push = evo_wait(mast, 4);
1727                 if (push) {
1728                         if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
1729                                 evo_mthd(push, 0x0600 + (or * 0x40), 1);
1730                                 evo_data(push, 0x00000000);
1731                         } else {
1732                                 evo_mthd(push, 0x0200 + (or * 0x20), 1);
1733                                 evo_data(push, 0x00000000);
1734                         }
1735                         evo_kick(push, mast);
1736                 }
1737
1738                 nv50_hdmi_disconnect(encoder);
1739         }
1740
1741         nv_encoder->last_dpms = DRM_MODE_DPMS_OFF;
1742         nv_encoder->crtc = NULL;
1743 }
1744
1745 static void
1746 nv50_sor_commit(struct drm_encoder *encoder)
1747 {
1748 }
1749
1750 static void
1751 nv50_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *umode,
1752                   struct drm_display_mode *mode)
1753 {
1754         struct nv50_disp *disp = nv50_disp(encoder->dev);
1755         struct nv50_mast *mast = nv50_mast(encoder->dev);
1756         struct drm_device *dev = encoder->dev;
1757         struct nouveau_drm *drm = nouveau_drm(dev);
1758         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1759         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1760         struct nouveau_connector *nv_connector;
1761         struct nvbios *bios = &drm->vbios;
1762         u32 *push, lvds = 0;
1763         u8 owner = 1 << nv_crtc->index;
1764         u8 proto = 0xf;
1765         u8 depth = 0x0;
1766
1767         nv_connector = nouveau_encoder_connector_get(nv_encoder);
1768         switch (nv_encoder->dcb->type) {
1769         case DCB_OUTPUT_TMDS:
1770                 if (nv_encoder->dcb->sorconf.link & 1) {
1771                         if (mode->clock < 165000)
1772                                 proto = 0x1;
1773                         else
1774                                 proto = 0x5;
1775                 } else {
1776                         proto = 0x2;
1777                 }
1778
1779                 nv50_hdmi_mode_set(encoder, mode);
1780                 break;
1781         case DCB_OUTPUT_LVDS:
1782                 proto = 0x0;
1783
1784                 if (bios->fp_no_ddc) {
1785                         if (bios->fp.dual_link)
1786                                 lvds |= 0x0100;
1787                         if (bios->fp.if_is_24bit)
1788                                 lvds |= 0x0200;
1789                 } else {
1790                         if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
1791                                 if (((u8 *)nv_connector->edid)[121] == 2)
1792                                         lvds |= 0x0100;
1793                         } else
1794                         if (mode->clock >= bios->fp.duallink_transition_clk) {
1795                                 lvds |= 0x0100;
1796                         }
1797
1798                         if (lvds & 0x0100) {
1799                                 if (bios->fp.strapless_is_24bit & 2)
1800                                         lvds |= 0x0200;
1801                         } else {
1802                                 if (bios->fp.strapless_is_24bit & 1)
1803                                         lvds |= 0x0200;
1804                         }
1805
1806                         if (nv_connector->base.display_info.bpc == 8)
1807                                 lvds |= 0x0200;
1808                 }
1809
1810                 nv_call(disp->core, NV50_DISP_SOR_LVDS_SCRIPT + nv_encoder->or, lvds);
1811                 break;
1812         case DCB_OUTPUT_DP:
1813                 if (nv_connector->base.display_info.bpc == 6) {
1814                         nv_encoder->dp.datarate = mode->clock * 18 / 8;
1815                         depth = 0x2;
1816                 } else
1817                 if (nv_connector->base.display_info.bpc == 8) {
1818                         nv_encoder->dp.datarate = mode->clock * 24 / 8;
1819                         depth = 0x5;
1820                 } else {
1821                         nv_encoder->dp.datarate = mode->clock * 30 / 8;
1822                         depth = 0x6;
1823                 }
1824
1825                 if (nv_encoder->dcb->sorconf.link & 1)
1826                         proto = 0x8;
1827                 else
1828                         proto = 0x9;
1829                 break;
1830         default:
1831                 BUG_ON(1);
1832                 break;
1833         }
1834
1835         nv50_sor_dpms(encoder, DRM_MODE_DPMS_ON);
1836
1837         push = evo_wait(nv50_mast(dev), 8);
1838         if (push) {
1839                 if (nv50_vers(mast) < NVD0_DISP_CLASS) {
1840                         u32 ctrl = (depth << 16) | (proto << 8) | owner;
1841                         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1842                                 ctrl |= 0x00001000;
1843                         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1844                                 ctrl |= 0x00002000;
1845                         evo_mthd(push, 0x0600 + (nv_encoder->or * 0x040), 1);
1846                         evo_data(push, ctrl);
1847                 } else {
1848                         u32 magic = 0x31ec6000 | (nv_crtc->index << 25);
1849                         u32 syncs = 0x00000001;
1850
1851                         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1852                                 syncs |= 0x00000008;
1853                         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1854                                 syncs |= 0x00000010;
1855
1856                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1857                                 magic |= 0x00000001;
1858
1859                         evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2);
1860                         evo_data(push, syncs | (depth << 6));
1861                         evo_data(push, magic);
1862                         evo_mthd(push, 0x0200 + (nv_encoder->or * 0x020), 1);
1863                         evo_data(push, owner | (proto << 8));
1864                 }
1865
1866                 evo_kick(push, mast);
1867         }
1868
1869         nv_encoder->crtc = encoder->crtc;
1870 }
1871
1872 static void
1873 nv50_sor_destroy(struct drm_encoder *encoder)
1874 {
1875         drm_encoder_cleanup(encoder);
1876         kfree(encoder);
1877 }
1878
1879 static const struct drm_encoder_helper_funcs nv50_sor_hfunc = {
1880         .dpms = nv50_sor_dpms,
1881         .mode_fixup = nv50_sor_mode_fixup,
1882         .prepare = nv50_sor_disconnect,
1883         .commit = nv50_sor_commit,
1884         .mode_set = nv50_sor_mode_set,
1885         .disable = nv50_sor_disconnect,
1886         .get_crtc = nv50_display_crtc_get,
1887 };
1888
1889 static const struct drm_encoder_funcs nv50_sor_func = {
1890         .destroy = nv50_sor_destroy,
1891 };
1892
1893 static int
1894 nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe)
1895 {
1896         struct nouveau_drm *drm = nouveau_drm(connector->dev);
1897         struct nouveau_i2c *i2c = nouveau_i2c(drm->device);
1898         struct nouveau_encoder *nv_encoder;
1899         struct drm_encoder *encoder;
1900         int type;
1901
1902         switch (dcbe->type) {
1903         case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break;
1904         case DCB_OUTPUT_TMDS:
1905         case DCB_OUTPUT_DP:
1906         default:
1907                 type = DRM_MODE_ENCODER_TMDS;
1908                 break;
1909         }
1910
1911         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1912         if (!nv_encoder)
1913                 return -ENOMEM;
1914         nv_encoder->dcb = dcbe;
1915         nv_encoder->or = ffs(dcbe->or) - 1;
1916         nv_encoder->i2c = i2c->find(i2c, dcbe->i2c_index);
1917         nv_encoder->last_dpms = DRM_MODE_DPMS_OFF;
1918
1919         encoder = to_drm_encoder(nv_encoder);
1920         encoder->possible_crtcs = dcbe->heads;
1921         encoder->possible_clones = 0;
1922         drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type);
1923         drm_encoder_helper_add(encoder, &nv50_sor_hfunc);
1924
1925         drm_mode_connector_attach_encoder(connector, encoder);
1926         return 0;
1927 }
1928
1929 /******************************************************************************
1930  * PIOR
1931  *****************************************************************************/
1932
1933 static void
1934 nv50_pior_dpms(struct drm_encoder *encoder, int mode)
1935 {
1936         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1937         struct nv50_disp *disp = nv50_disp(encoder->dev);
1938         u32 mthd = (nv_encoder->dcb->type << 12) | nv_encoder->or;
1939         u32 ctrl = (mode == DRM_MODE_DPMS_ON);
1940         nv_call(disp->core, NV50_DISP_PIOR_PWR + mthd, ctrl);
1941 }
1942
1943 static bool
1944 nv50_pior_mode_fixup(struct drm_encoder *encoder,
1945                      const struct drm_display_mode *mode,
1946                      struct drm_display_mode *adjusted_mode)
1947 {
1948         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1949         struct nouveau_connector *nv_connector;
1950
1951         nv_connector = nouveau_encoder_connector_get(nv_encoder);
1952         if (nv_connector && nv_connector->native_mode) {
1953                 if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) {
1954                         int id = adjusted_mode->base.id;
1955                         *adjusted_mode = *nv_connector->native_mode;
1956                         adjusted_mode->base.id = id;
1957                 }
1958         }
1959
1960         adjusted_mode->clock *= 2;
1961         return true;
1962 }
1963
1964 static void
1965 nv50_pior_commit(struct drm_encoder *encoder)
1966 {
1967 }
1968
1969 static void
1970 nv50_pior_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
1971                    struct drm_display_mode *adjusted_mode)
1972 {
1973         struct nv50_mast *mast = nv50_mast(encoder->dev);
1974         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1975         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1976         struct nouveau_connector *nv_connector;
1977         u8 owner = 1 << nv_crtc->index;
1978         u8 proto, depth;
1979         u32 *push;
1980
1981         nv_connector = nouveau_encoder_connector_get(nv_encoder);
1982         switch (nv_connector->base.display_info.bpc) {
1983         case 10: depth = 0x6; break;
1984         case  8: depth = 0x5; break;
1985         case  6: depth = 0x2; break;
1986         default: depth = 0x0; break;
1987         }
1988
1989         switch (nv_encoder->dcb->type) {
1990         case DCB_OUTPUT_TMDS:
1991         case DCB_OUTPUT_DP:
1992                 proto = 0x0;
1993                 break;
1994         default:
1995                 BUG_ON(1);
1996                 break;
1997         }
1998
1999         nv50_pior_dpms(encoder, DRM_MODE_DPMS_ON);
2000
2001         push = evo_wait(mast, 8);
2002         if (push) {
2003                 if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
2004                         u32 ctrl = (depth << 16) | (proto << 8) | owner;
2005                         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
2006                                 ctrl |= 0x00001000;
2007                         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
2008                                 ctrl |= 0x00002000;
2009                         evo_mthd(push, 0x0700 + (nv_encoder->or * 0x040), 1);
2010                         evo_data(push, ctrl);
2011                 }
2012
2013                 evo_kick(push, mast);
2014         }
2015
2016         nv_encoder->crtc = encoder->crtc;
2017 }
2018
2019 static void
2020 nv50_pior_disconnect(struct drm_encoder *encoder)
2021 {
2022         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2023         struct nv50_mast *mast = nv50_mast(encoder->dev);
2024         const int or = nv_encoder->or;
2025         u32 *push;
2026
2027         if (nv_encoder->crtc) {
2028                 nv50_crtc_prepare(nv_encoder->crtc);
2029
2030                 push = evo_wait(mast, 4);
2031                 if (push) {
2032                         if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) {
2033                                 evo_mthd(push, 0x0700 + (or * 0x040), 1);
2034                                 evo_data(push, 0x00000000);
2035                         }
2036                         evo_kick(push, mast);
2037                 }
2038         }
2039
2040         nv_encoder->crtc = NULL;
2041 }
2042
2043 static void
2044 nv50_pior_destroy(struct drm_encoder *encoder)
2045 {
2046         drm_encoder_cleanup(encoder);
2047         kfree(encoder);
2048 }
2049
2050 static const struct drm_encoder_helper_funcs nv50_pior_hfunc = {
2051         .dpms = nv50_pior_dpms,
2052         .mode_fixup = nv50_pior_mode_fixup,
2053         .prepare = nv50_pior_disconnect,
2054         .commit = nv50_pior_commit,
2055         .mode_set = nv50_pior_mode_set,
2056         .disable = nv50_pior_disconnect,
2057         .get_crtc = nv50_display_crtc_get,
2058 };
2059
2060 static const struct drm_encoder_funcs nv50_pior_func = {
2061         .destroy = nv50_pior_destroy,
2062 };
2063
2064 static int
2065 nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe)
2066 {
2067         struct nouveau_drm *drm = nouveau_drm(connector->dev);
2068         struct nouveau_i2c *i2c = nouveau_i2c(drm->device);
2069         struct nouveau_i2c_port *ddc = NULL;
2070         struct nouveau_encoder *nv_encoder;
2071         struct drm_encoder *encoder;
2072         int type;
2073
2074         switch (dcbe->type) {
2075         case DCB_OUTPUT_TMDS:
2076                 ddc  = i2c->find_type(i2c, NV_I2C_TYPE_EXTDDC(dcbe->extdev));
2077                 type = DRM_MODE_ENCODER_TMDS;
2078                 break;
2079         case DCB_OUTPUT_DP:
2080                 ddc  = i2c->find_type(i2c, NV_I2C_TYPE_EXTAUX(dcbe->extdev));
2081                 type = DRM_MODE_ENCODER_TMDS;
2082                 break;
2083         default:
2084                 return -ENODEV;
2085         }
2086
2087         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
2088         if (!nv_encoder)
2089                 return -ENOMEM;
2090         nv_encoder->dcb = dcbe;
2091         nv_encoder->or = ffs(dcbe->or) - 1;
2092         nv_encoder->i2c = ddc;
2093
2094         encoder = to_drm_encoder(nv_encoder);
2095         encoder->possible_crtcs = dcbe->heads;
2096         encoder->possible_clones = 0;
2097         drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type);
2098         drm_encoder_helper_add(encoder, &nv50_pior_hfunc);
2099
2100         drm_mode_connector_attach_encoder(connector, encoder);
2101         return 0;
2102 }
2103
2104 /******************************************************************************
2105  * Init
2106  *****************************************************************************/
2107 void
2108 nv50_display_fini(struct drm_device *dev)
2109 {
2110 }
2111
2112 int
2113 nv50_display_init(struct drm_device *dev)
2114 {
2115         u32 *push = evo_wait(nv50_mast(dev), 32);
2116         if (push) {
2117                 evo_mthd(push, 0x0088, 1);
2118                 evo_data(push, NvEvoSync);
2119                 evo_kick(push, nv50_mast(dev));
2120                 return 0;
2121         }
2122
2123         return -EBUSY;
2124 }
2125
2126 void
2127 nv50_display_destroy(struct drm_device *dev)
2128 {
2129         struct nv50_disp *disp = nv50_disp(dev);
2130
2131         nv50_dmac_destroy(disp->core, &disp->mast.base);
2132
2133         nouveau_bo_unmap(disp->sync);
2134         if (disp->sync)
2135                 nouveau_bo_unpin(disp->sync);
2136         nouveau_bo_ref(NULL, &disp->sync);
2137
2138         nouveau_display(dev)->priv = NULL;
2139         kfree(disp);
2140 }
2141
2142 int
2143 nv50_display_create(struct drm_device *dev)
2144 {
2145         static const u16 oclass[] = {
2146                 NVE0_DISP_CLASS,
2147                 NVD0_DISP_CLASS,
2148                 NVA3_DISP_CLASS,
2149                 NV94_DISP_CLASS,
2150                 NVA0_DISP_CLASS,
2151                 NV84_DISP_CLASS,
2152                 NV50_DISP_CLASS,
2153         };
2154         struct nouveau_device *device = nouveau_dev(dev);
2155         struct nouveau_drm *drm = nouveau_drm(dev);
2156         struct dcb_table *dcb = &drm->vbios.dcb;
2157         struct drm_connector *connector, *tmp;
2158         struct nv50_disp *disp;
2159         struct dcb_output *dcbe;
2160         int crtcs, ret, i;
2161
2162         disp = kzalloc(sizeof(*disp), GFP_KERNEL);
2163         if (!disp)
2164                 return -ENOMEM;
2165
2166         nouveau_display(dev)->priv = disp;
2167         nouveau_display(dev)->dtor = nv50_display_destroy;
2168         nouveau_display(dev)->init = nv50_display_init;
2169         nouveau_display(dev)->fini = nv50_display_fini;
2170
2171         /* small shared memory area we use for notifiers and semaphores */
2172         ret = nouveau_bo_new(dev, 4096, 0x1000, TTM_PL_FLAG_VRAM,
2173                              0, 0x0000, NULL, &disp->sync);
2174         if (!ret) {
2175                 ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM);
2176                 if (!ret) {
2177                         ret = nouveau_bo_map(disp->sync);
2178                         if (ret)
2179                                 nouveau_bo_unpin(disp->sync);
2180                 }
2181                 if (ret)
2182                         nouveau_bo_ref(NULL, &disp->sync);
2183         }
2184
2185         if (ret)
2186                 goto out;
2187
2188         /* attempt to allocate a supported evo display class */
2189         ret = -ENODEV;
2190         for (i = 0; ret && i < ARRAY_SIZE(oclass); i++) {
2191                 ret = nouveau_object_new(nv_object(drm), NVDRM_DEVICE,
2192                                          0xd1500000, oclass[i], NULL, 0,
2193                                          &disp->core);
2194         }
2195
2196         if (ret)
2197                 goto out;
2198
2199         /* allocate master evo channel */
2200         ret = nv50_dmac_create(disp->core, NV50_DISP_MAST_CLASS, 0,
2201                               &(struct nv50_display_mast_class) {
2202                                         .pushbuf = EVO_PUSH_HANDLE(MAST, 0),
2203                               }, sizeof(struct nv50_display_mast_class),
2204                               disp->sync->bo.offset, &disp->mast.base);
2205         if (ret)
2206                 goto out;
2207
2208         /* create crtc objects to represent the hw heads */
2209         if (nv_mclass(disp->core) >= NVD0_DISP_CLASS)
2210                 crtcs = nv_rd32(device, 0x022448);
2211         else
2212                 crtcs = 2;
2213
2214         for (i = 0; i < crtcs; i++) {
2215                 ret = nv50_crtc_create(dev, disp->core, i);
2216                 if (ret)
2217                         goto out;
2218         }
2219
2220         /* create encoder/connector objects based on VBIOS DCB table */
2221         for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) {
2222                 connector = nouveau_connector_create(dev, dcbe->connector);
2223                 if (IS_ERR(connector))
2224                         continue;
2225
2226                 if (dcbe->location == DCB_LOC_ON_CHIP) {
2227                         switch (dcbe->type) {
2228                         case DCB_OUTPUT_TMDS:
2229                         case DCB_OUTPUT_LVDS:
2230                         case DCB_OUTPUT_DP:
2231                                 ret = nv50_sor_create(connector, dcbe);
2232                                 break;
2233                         case DCB_OUTPUT_ANALOG:
2234                                 ret = nv50_dac_create(connector, dcbe);
2235                                 break;
2236                         default:
2237                                 ret = -ENODEV;
2238                                 break;
2239                         }
2240                 } else {
2241                         ret = nv50_pior_create(connector, dcbe);
2242                 }
2243
2244                 if (ret) {
2245                         NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n",
2246                                      dcbe->location, dcbe->type,
2247                                      ffs(dcbe->or) - 1, ret);
2248                 }
2249         }
2250
2251         /* cull any connectors we created that don't have an encoder */
2252         list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) {
2253                 if (connector->encoder_ids[0])
2254                         continue;
2255
2256                 NV_WARN(drm, "%s has no encoders, removing\n",
2257                         drm_get_connector_name(connector));
2258                 connector->funcs->destroy(connector);
2259         }
2260
2261 out:
2262         if (ret)
2263                 nv50_display_destroy(dev);
2264         return ret;
2265 }