Pileus Git - ~andy/linux/blob - drivers/gpu/drm/nouveau/nv17_tv.c

   1 /*
   2  * Copyright (C) 2009 Francisco Jerez.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial
  15  * portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  21  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  22  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  */
  26
  27 #include "drmP.h"
  28 #include "drm_crtc_helper.h"
  29 #include "nouveau_drv.h"
  30 #include "nouveau_encoder.h"
  31 #include "nouveau_connector.h"
  32 #include "nouveau_crtc.h"
  33 #include "nouveau_hw.h"
  34 #include "nv17_tv.h"
  35
  36 #include <subdev/bios/gpio.h>
  37
  38 static uint32_t nv42_tv_sample_load(struct drm_encoder *encoder)
  39 {
  40         struct drm_device *dev = encoder->dev;
  41         struct drm_nouveau_private *dev_priv = dev->dev_private;
  42         uint32_t testval, regoffset = nv04_dac_output_offset(encoder);
  43         uint32_t gpio0, gpio1, fp_htotal, fp_hsync_start, fp_hsync_end,
  44                 fp_control, test_ctrl, dacclk, ctv_14, ctv_1c, ctv_6c;
  45         uint32_t sample = 0;
  46         int head;
  47
  48 #define RGB_TEST_DATA(r, g, b) (r << 0 | g << 10 | b << 20)
  49         testval = RGB_TEST_DATA(0x82, 0xeb, 0x82);
  50         if (dev_priv->vbios.tvdactestval)
  51                 testval = dev_priv->vbios.tvdactestval;
  52
  53         dacclk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset);
  54         head = (dacclk & 0x100) >> 8;
  55
  56         /* Save the previous state. */
  57         gpio1 = nouveau_gpio_func_get(dev, DCB_GPIO_TVDAC1);
  58         gpio0 = nouveau_gpio_func_get(dev, DCB_GPIO_TVDAC0);
  59         fp_htotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL);
  60         fp_hsync_start = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START);
  61         fp_hsync_end = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END);
  62         fp_control = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL);
  63         test_ctrl = NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset);
  64         ctv_1c = NVReadRAMDAC(dev, head, 0x680c1c);
  65         ctv_14 = NVReadRAMDAC(dev, head, 0x680c14);
  66         ctv_6c = NVReadRAMDAC(dev, head, 0x680c6c);
  67
  68         /* Prepare the DAC for load detection.  */
  69         nouveau_gpio_func_set(dev, DCB_GPIO_TVDAC1, true);
  70         nouveau_gpio_func_set(dev, DCB_GPIO_TVDAC0, true);
  71
  72         NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL, 1343);
  73         NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START, 1047);
  74         NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END, 1183);
  75         NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL,
  76                       NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS |
  77                       NV_PRAMDAC_FP_TG_CONTROL_WIDTH_12 |
  78                       NV_PRAMDAC_FP_TG_CONTROL_READ_PROG |
  79                       NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS |
  80                       NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS);
  81
  82         NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset, 0);
  83
  84         NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset,
  85                       (dacclk & ~0xff) | 0x22);
  86         msleep(1);
  87         NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset,
  88                       (dacclk & ~0xff) | 0x21);
  89
  90         NVWriteRAMDAC(dev, head, 0x680c1c, 1 << 20);
  91         NVWriteRAMDAC(dev, head, 0x680c14, 4 << 16);
  92
  93         /* Sample pin 0x4 (usually S-video luma). */
  94         NVWriteRAMDAC(dev, head, 0x680c6c, testval >> 10 & 0x3ff);
  95         msleep(20);
  96         sample |= NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset)
  97                 & 0x4 << 28;
  98
  99         /* Sample the remaining pins. */
 100         NVWriteRAMDAC(dev, head, 0x680c6c, testval & 0x3ff);
 101         msleep(20);
 102         sample |= NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset)
 103                 & 0xa << 28;
 104
 105         /* Restore the previous state. */
 106         NVWriteRAMDAC(dev, head, 0x680c1c, ctv_1c);
 107         NVWriteRAMDAC(dev, head, 0x680c14, ctv_14);
 108         NVWriteRAMDAC(dev, head, 0x680c6c, ctv_6c);
 109         NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset, dacclk);
 110         NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset, test_ctrl);
 111         NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL, fp_control);
 112         NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END, fp_hsync_end);
 113         NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START, fp_hsync_start);
 114         NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL, fp_htotal);
 115         nouveau_gpio_func_set(dev, DCB_GPIO_TVDAC1, gpio1);
 116         nouveau_gpio_func_set(dev, DCB_GPIO_TVDAC0, gpio0);
 117
 118         return sample;
 119 }
 120
 121 static bool
 122 get_tv_detect_quirks(struct drm_device *dev, uint32_t *pin_mask)
 123 {
 124         /* Zotac FX5200 */
 125         if (nv_match_device(dev, 0x0322, 0x19da, 0x1035) ||
 126             nv_match_device(dev, 0x0322, 0x19da, 0x2035)) {
 127                 *pin_mask = 0xc;
 128                 return false;
 129         }
 130
 131         /* MSI nForce2 IGP */
 132         if (nv_match_device(dev, 0x01f0, 0x1462, 0x5710)) {
 133                 *pin_mask = 0xc;
 134                 return false;
 135         }
 136
 137         return true;
 138 }
 139
 140 static enum drm_connector_status
 141 nv17_tv_detect(struct drm_encoder *encoder, struct drm_connector *connector)
 142 {
 143         struct drm_device *dev = encoder->dev;
 144         struct drm_nouveau_private *dev_priv = dev->dev_private;
 145         struct drm_mode_config *conf = &dev->mode_config;
 146         struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder);
 147         struct dcb_output *dcb = tv_enc->base.dcb;
 148         bool reliable = get_tv_detect_quirks(dev, &tv_enc->pin_mask);
 149
 150         if (nv04_dac_in_use(encoder))
 151                 return connector_status_disconnected;
 152
 153         if (reliable) {
 154                 if (dev_priv->chipset == 0x42 ||
 155                     dev_priv->chipset == 0x43)
 156                         tv_enc->pin_mask =
 157                                 nv42_tv_sample_load(encoder) >> 28 & 0xe;
 158                 else
 159                         tv_enc->pin_mask =
 160                                 nv17_dac_sample_load(encoder) >> 28 & 0xe;
 161         }
 162
 163         switch (tv_enc->pin_mask) {
 164         case 0x2:
 165         case 0x4:
 166                 tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_Composite;
 167                 break;
 168         case 0xc:
 169                 tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_SVIDEO;
 170                 break;
 171         case 0xe:
 172                 if (dcb->tvconf.has_component_output)
 173                         tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_Component;
 174                 else
 175                         tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_SCART;
 176                 break;
 177         default:
 178                 tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_Unknown;
 179                 break;
 180         }
 181
 182         drm_connector_property_set_value(connector,
 183                                          conf->tv_subconnector_property,
 184                                          tv_enc->subconnector);
 185
 186         if (!reliable) {
 187                 return connector_status_unknown;
 188         } else if (tv_enc->subconnector) {
 189                 NV_INFO(dev, "Load detected on output %c\n",
 190                         '@' + ffs(dcb->or));
 191                 return connector_status_connected;
 192         } else {
 193                 return connector_status_disconnected;
 194         }
 195 }
 196
 197 static int nv17_tv_get_ld_modes(struct drm_encoder *encoder,
 198                                 struct drm_connector *connector)
 199 {
 200         struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
 201         const struct drm_display_mode *tv_mode;
 202         int n = 0;
 203
 204         for (tv_mode = nv17_tv_modes; tv_mode->hdisplay; tv_mode++) {
 205                 struct drm_display_mode *mode;
 206
 207                 mode = drm_mode_duplicate(encoder->dev, tv_mode);
 208
 209                 mode->clock = tv_norm->tv_enc_mode.vrefresh *
 210                         mode->htotal / 1000 *
 211                         mode->vtotal / 1000;
 212
 213                 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 214                         mode->clock *= 2;
 215
 216                 if (mode->hdisplay == tv_norm->tv_enc_mode.hdisplay &&
 217                     mode->vdisplay == tv_norm->tv_enc_mode.vdisplay)
 218                         mode->type |= DRM_MODE_TYPE_PREFERRED;
 219
 220                 drm_mode_probed_add(connector, mode);
 221                 n++;
 222         }
 223
 224         return n;
 225 }
 226
 227 static int nv17_tv_get_hd_modes(struct drm_encoder *encoder,
 228                                 struct drm_connector *connector)
 229 {
 230         struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
 231         struct drm_display_mode *output_mode = &tv_norm->ctv_enc_mode.mode;
 232         struct drm_display_mode *mode;
 233         const struct {
 234                 int hdisplay;
 235                 int vdisplay;
 236         } modes[] = {
 237                 { 640, 400 },
 238                 { 640, 480 },
 239                 { 720, 480 },
 240                 { 720, 576 },
 241                 { 800, 600 },
 242                 { 1024, 768 },
 243                 { 1280, 720 },
 244                 { 1280, 1024 },
 245                 { 1920, 1080 }
 246         };
 247         int i, n = 0;
 248
 249         for (i = 0; i < ARRAY_SIZE(modes); i++) {
 250                 if (modes[i].hdisplay > output_mode->hdisplay ||
 251                     modes[i].vdisplay > output_mode->vdisplay)
 252                         continue;
 253
 254                 if (modes[i].hdisplay == output_mode->hdisplay &&
 255                     modes[i].vdisplay == output_mode->vdisplay) {
 256                         mode = drm_mode_duplicate(encoder->dev, output_mode);
 257                         mode->type |= DRM_MODE_TYPE_PREFERRED;
 258
 259                 } else {
 260                         mode = drm_cvt_mode(encoder->dev, modes[i].hdisplay,
 261                                             modes[i].vdisplay, 60, false,
 262                                             (output_mode->flags &
 263                                              DRM_MODE_FLAG_INTERLACE), false);
 264                 }
 265
 266                 /* CVT modes are sometimes unsuitable... */
 267                 if (output_mode->hdisplay <= 720
 268                     || output_mode->hdisplay >= 1920) {
 269                         mode->htotal = output_mode->htotal;
 270                         mode->hsync_start = (mode->hdisplay + (mode->htotal
 271                                              - mode->hdisplay) * 9 / 10) & ~7;
 272                         mode->hsync_end = mode->hsync_start + 8;
 273                 }
 274
 275                 if (output_mode->vdisplay >= 1024) {
 276                         mode->vtotal = output_mode->vtotal;
 277                         mode->vsync_start = output_mode->vsync_start;
 278                         mode->vsync_end = output_mode->vsync_end;
 279                 }
 280
 281                 mode->type |= DRM_MODE_TYPE_DRIVER;
 282                 drm_mode_probed_add(connector, mode);
 283                 n++;
 284         }
 285
 286         return n;
 287 }
 288
 289 static int nv17_tv_get_modes(struct drm_encoder *encoder,
 290                              struct drm_connector *connector)
 291 {
 292         struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
 293
 294         if (tv_norm->kind == CTV_ENC_MODE)
 295                 return nv17_tv_get_hd_modes(encoder, connector);
 296         else
 297                 return nv17_tv_get_ld_modes(encoder, connector);
 298 }
 299
 300 static int nv17_tv_mode_valid(struct drm_encoder *encoder,
 301                               struct drm_display_mode *mode)
 302 {
 303         struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
 304
 305         if (tv_norm->kind == CTV_ENC_MODE) {
 306                 struct drm_display_mode *output_mode =
 307                                                 &tv_norm->ctv_enc_mode.mode;
 308
 309                 if (mode->clock > 400000)
 310                         return MODE_CLOCK_HIGH;
 311
 312                 if (mode->hdisplay > output_mode->hdisplay ||
 313                     mode->vdisplay > output_mode->vdisplay)
 314                         return MODE_BAD;
 315
 316                 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) !=
 317                     (output_mode->flags & DRM_MODE_FLAG_INTERLACE))
 318                         return MODE_NO_INTERLACE;
 319
 320                 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 321                         return MODE_NO_DBLESCAN;
 322
 323         } else {
 324                 const int vsync_tolerance = 600;
 325
 326                 if (mode->clock > 70000)
 327                         return MODE_CLOCK_HIGH;
 328
 329                 if (abs(drm_mode_vrefresh(mode) * 1000 -
 330                         tv_norm->tv_enc_mode.vrefresh) > vsync_tolerance)
 331                         return MODE_VSYNC;
 332
 333                 /* The encoder takes care of the actual interlacing */
 334                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 335                         return MODE_NO_INTERLACE;
 336         }
 337
 338         return MODE_OK;
 339 }
 340
 341 static bool nv17_tv_mode_fixup(struct drm_encoder *encoder,
 342                                const struct drm_display_mode *mode,
 343                                struct drm_display_mode *adjusted_mode)
 344 {
 345         struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
 346
 347         if (nv04_dac_in_use(encoder))
 348                 return false;
 349
 350         if (tv_norm->kind == CTV_ENC_MODE)
 351                 adjusted_mode->clock = tv_norm->ctv_enc_mode.mode.clock;
 352         else
 353                 adjusted_mode->clock = 90000;
 354
 355         return true;
 356 }
 357
 358 static void  nv17_tv_dpms(struct drm_encoder *encoder, int mode)
 359 {
 360         struct drm_device *dev = encoder->dev;
 361         struct nv17_tv_state *regs = &to_tv_enc(encoder)->state;
 362         struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
 363
 364         if (nouveau_encoder(encoder)->last_dpms == mode)
 365                 return;
 366         nouveau_encoder(encoder)->last_dpms = mode;
 367
 368         NV_INFO(dev, "Setting dpms mode %d on TV encoder (output %d)\n",
 369                  mode, nouveau_encoder(encoder)->dcb->index);
 370
 371         regs->ptv_200 &= ~1;
 372
 373         if (tv_norm->kind == CTV_ENC_MODE) {
 374                 nv04_dfp_update_fp_control(encoder, mode);
 375
 376         } else {
 377                 nv04_dfp_update_fp_control(encoder, DRM_MODE_DPMS_OFF);
 378
 379                 if (mode == DRM_MODE_DPMS_ON)
 380                         regs->ptv_200 |= 1;
 381         }
 382
 383         nv_load_ptv(dev, regs, 200);
 384
 385         nouveau_gpio_func_set(dev, DCB_GPIO_TVDAC1, mode == DRM_MODE_DPMS_ON);
 386         nouveau_gpio_func_set(dev, DCB_GPIO_TVDAC0, mode == DRM_MODE_DPMS_ON);
 387
 388         nv04_dac_update_dacclk(encoder, mode == DRM_MODE_DPMS_ON);
 389 }
 390
 391 static void nv17_tv_prepare(struct drm_encoder *encoder)
 392 {
 393         struct drm_device *dev = encoder->dev;
 394         struct drm_nouveau_private *dev_priv = dev->dev_private;
 395         struct drm_encoder_helper_funcs *helper = encoder->helper_private;
 396         struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
 397         int head = nouveau_crtc(encoder->crtc)->index;
 398         uint8_t *cr_lcd = &dev_priv->mode_reg.crtc_reg[head].CRTC[
 399                                                         NV_CIO_CRE_LCD__INDEX];
 400         uint32_t dacclk_off = NV_PRAMDAC_DACCLK +
 401                                         nv04_dac_output_offset(encoder);
 402         uint32_t dacclk;
 403
 404         helper->dpms(encoder, DRM_MODE_DPMS_OFF);
 405
 406         nv04_dfp_disable(dev, head);
 407
 408         /* Unbind any FP encoders from this head if we need the FP
 409          * stuff enabled. */
 410         if (tv_norm->kind == CTV_ENC_MODE) {
 411                 struct drm_encoder *enc;
 412
 413                 list_for_each_entry(enc, &dev->mode_config.encoder_list, head) {
 414                         struct dcb_output *dcb = nouveau_encoder(enc)->dcb;
 415
 416                         if ((dcb->type == DCB_OUTPUT_TMDS ||
 417                              dcb->type == DCB_OUTPUT_LVDS) &&
 418                              !enc->crtc &&
 419                              nv04_dfp_get_bound_head(dev, dcb) == head) {
 420                                 nv04_dfp_bind_head(dev, dcb, head ^ 1,
 421                                                 dev_priv->vbios.fp.dual_link);
 422                         }
 423                 }
 424
 425         }
 426
 427         if (tv_norm->kind == CTV_ENC_MODE)
 428                 *cr_lcd |= 0x1 | (head ? 0x0 : 0x8);
 429
 430         /* Set the DACCLK register */
 431         dacclk = (NVReadRAMDAC(dev, 0, dacclk_off) & ~0x30) | 0x1;
 432
 433         if (dev_priv->card_type == NV_40)
 434                 dacclk |= 0x1a << 16;
 435
 436         if (tv_norm->kind == CTV_ENC_MODE) {
 437                 dacclk |=  0x20;
 438
 439                 if (head)
 440                         dacclk |= 0x100;
 441                 else
 442                         dacclk &= ~0x100;
 443
 444         } else {
 445                 dacclk |= 0x10;
 446
 447         }
 448
 449         NVWriteRAMDAC(dev, 0, dacclk_off, dacclk);
 450 }
 451
 452 static void nv17_tv_mode_set(struct drm_encoder *encoder,
 453                              struct drm_display_mode *drm_mode,
 454                              struct drm_display_mode *adjusted_mode)
 455 {
 456         struct drm_device *dev = encoder->dev;
 457         struct drm_nouveau_private *dev_priv = dev->dev_private;
 458         int head = nouveau_crtc(encoder->crtc)->index;
 459         struct nv04_crtc_reg *regs = &dev_priv->mode_reg.crtc_reg[head];
 460         struct nv17_tv_state *tv_regs = &to_tv_enc(encoder)->state;
 461         struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
 462         int i;
 463
 464         regs->CRTC[NV_CIO_CRE_53] = 0x40; /* FP_HTIMING */
 465         regs->CRTC[NV_CIO_CRE_54] = 0; /* FP_VTIMING */
 466         regs->ramdac_630 = 0x2; /* turn off green mode (tv test pattern?) */
 467         regs->tv_setup = 1;
 468         regs->ramdac_8c0 = 0x0;
 469
 470         if (tv_norm->kind == TV_ENC_MODE) {
 471                 tv_regs->ptv_200 = 0x13111100;
 472                 if (head)
 473                         tv_regs->ptv_200 |= 0x10;
 474
 475                 tv_regs->ptv_20c = 0x808010;
 476                 tv_regs->ptv_304 = 0x2d00000;
 477                 tv_regs->ptv_600 = 0x0;
 478                 tv_regs->ptv_60c = 0x0;
 479                 tv_regs->ptv_610 = 0x1e00000;
 480
 481                 if (tv_norm->tv_enc_mode.vdisplay == 576) {
 482                         tv_regs->ptv_508 = 0x1200000;
 483                         tv_regs->ptv_614 = 0x33;
 484
 485                 } else if (tv_norm->tv_enc_mode.vdisplay == 480) {
 486                         tv_regs->ptv_508 = 0xf00000;
 487                         tv_regs->ptv_614 = 0x13;
 488                 }
 489
 490                 if (dev_priv->card_type >= NV_30) {
 491                         tv_regs->ptv_500 = 0xe8e0;
 492                         tv_regs->ptv_504 = 0x1710;
 493                         tv_regs->ptv_604 = 0x0;
 494                         tv_regs->ptv_608 = 0x0;
 495                 } else {
 496                         if (tv_norm->tv_enc_mode.vdisplay == 576) {
 497                                 tv_regs->ptv_604 = 0x20;
 498                                 tv_regs->ptv_608 = 0x10;
 499                                 tv_regs->ptv_500 = 0x19710;
 500                                 tv_regs->ptv_504 = 0x68f0;
 501
 502                         } else if (tv_norm->tv_enc_mode.vdisplay == 480) {
 503                                 tv_regs->ptv_604 = 0x10;
 504                                 tv_regs->ptv_608 = 0x20;
 505                                 tv_regs->ptv_500 = 0x4b90;
 506                                 tv_regs->ptv_504 = 0x1b480;
 507                         }
 508                 }
 509
 510                 for (i = 0; i < 0x40; i++)
 511                         tv_regs->tv_enc[i] = tv_norm->tv_enc_mode.tv_enc[i];
 512
 513         } else {
 514                 struct drm_display_mode *output_mode =
 515                                                 &tv_norm->ctv_enc_mode.mode;
 516
 517                 /* The registers in PRAMDAC+0xc00 control some timings and CSC
 518                  * parameters for the CTV encoder (It's only used for "HD" TV
 519                  * modes, I don't think I have enough working to guess what
 520                  * they exactly mean...), it's probably connected at the
 521                  * output of the FP encoder, but it also needs the analog
 522                  * encoder in its OR enabled and routed to the head it's
 523                  * using. It's enabled with the DACCLK register, bits [5:4].
 524                  */
 525                 for (i = 0; i < 38; i++)
 526                         regs->ctv_regs[i] = tv_norm->ctv_enc_mode.ctv_regs[i];
 527
 528                 regs->fp_horiz_regs[FP_DISPLAY_END] = output_mode->hdisplay - 1;
 529                 regs->fp_horiz_regs[FP_TOTAL] = output_mode->htotal - 1;
 530                 regs->fp_horiz_regs[FP_SYNC_START] =
 531                                                 output_mode->hsync_start - 1;
 532                 regs->fp_horiz_regs[FP_SYNC_END] = output_mode->hsync_end - 1;
 533                 regs->fp_horiz_regs[FP_CRTC] = output_mode->hdisplay +
 534                         max((output_mode->hdisplay-600)/40 - 1, 1);
 535
 536                 regs->fp_vert_regs[FP_DISPLAY_END] = output_mode->vdisplay - 1;
 537                 regs->fp_vert_regs[FP_TOTAL] = output_mode->vtotal - 1;
 538                 regs->fp_vert_regs[FP_SYNC_START] =
 539                                                 output_mode->vsync_start - 1;
 540                 regs->fp_vert_regs[FP_SYNC_END] = output_mode->vsync_end - 1;
 541                 regs->fp_vert_regs[FP_CRTC] = output_mode->vdisplay - 1;
 542
 543                 regs->fp_control = NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS |
 544                         NV_PRAMDAC_FP_TG_CONTROL_READ_PROG |
 545                         NV_PRAMDAC_FP_TG_CONTROL_WIDTH_12;
 546
 547                 if (output_mode->flags & DRM_MODE_FLAG_PVSYNC)
 548                         regs->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS;
 549                 if (output_mode->flags & DRM_MODE_FLAG_PHSYNC)
 550                         regs->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS;
 551
 552                 regs->fp_debug_0 = NV_PRAMDAC_FP_DEBUG_0_YWEIGHT_ROUND |
 553                         NV_PRAMDAC_FP_DEBUG_0_XWEIGHT_ROUND |
 554                         NV_PRAMDAC_FP_DEBUG_0_YINTERP_BILINEAR |
 555                         NV_PRAMDAC_FP_DEBUG_0_XINTERP_BILINEAR |
 556                         NV_RAMDAC_FP_DEBUG_0_TMDS_ENABLED |
 557                         NV_PRAMDAC_FP_DEBUG_0_YSCALE_ENABLE |
 558                         NV_PRAMDAC_FP_DEBUG_0_XSCALE_ENABLE;
 559
 560                 regs->fp_debug_2 = 0;
 561
 562                 regs->fp_margin_color = 0x801080;
 563
 564         }
 565 }
 566
 567 static void nv17_tv_commit(struct drm_encoder *encoder)
 568 {
 569         struct drm_device *dev = encoder->dev;
 570         struct drm_nouveau_private *dev_priv = dev->dev_private;
 571         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
 572         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 573         struct drm_encoder_helper_funcs *helper = encoder->helper_private;
 574
 575         if (get_tv_norm(encoder)->kind == TV_ENC_MODE) {
 576                 nv17_tv_update_rescaler(encoder);
 577                 nv17_tv_update_properties(encoder);
 578         } else {
 579                 nv17_ctv_update_rescaler(encoder);
 580         }
 581
 582         nv17_tv_state_load(dev, &to_tv_enc(encoder)->state);
 583
 584         /* This could use refinement for flatpanels, but it should work */
 585         if (dev_priv->chipset < 0x44)
 586                 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL +
 587                                         nv04_dac_output_offset(encoder),
 588                                         0xf0000000);
 589         else
 590                 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL +
 591                                         nv04_dac_output_offset(encoder),
 592                                         0x00100000);
 593
 594         helper->dpms(encoder, DRM_MODE_DPMS_ON);
 595
 596         NV_INFO(dev, "Output %s is running on CRTC %d using output %c\n",
 597                 drm_get_connector_name(
 598                         &nouveau_encoder_connector_get(nv_encoder)->base),
 599                 nv_crtc->index, '@' + ffs(nv_encoder->dcb->or));
 600 }
 601
 602 static void nv17_tv_save(struct drm_encoder *encoder)
 603 {
 604         struct drm_device *dev = encoder->dev;
 605         struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder);
 606
 607         nouveau_encoder(encoder)->restore.output =
 608                                         NVReadRAMDAC(dev, 0,
 609                                         NV_PRAMDAC_DACCLK +
 610                                         nv04_dac_output_offset(encoder));
 611
 612         nv17_tv_state_save(dev, &tv_enc->saved_state);
 613
 614         tv_enc->state.ptv_200 = tv_enc->saved_state.ptv_200;
 615 }
 616
 617 static void nv17_tv_restore(struct drm_encoder *encoder)
 618 {
 619         struct drm_device *dev = encoder->dev;
 620
 621         NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK +
 622                                 nv04_dac_output_offset(encoder),
 623                                 nouveau_encoder(encoder)->restore.output);
 624
 625         nv17_tv_state_load(dev, &to_tv_enc(encoder)->saved_state);
 626
 627         nouveau_encoder(encoder)->last_dpms = NV_DPMS_CLEARED;
 628 }
 629
 630 static int nv17_tv_create_resources(struct drm_encoder *encoder,
 631                                     struct drm_connector *connector)
 632 {
 633         struct drm_device *dev = encoder->dev;
 634         struct drm_mode_config *conf = &dev->mode_config;
 635         struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder);
 636         struct dcb_output *dcb = nouveau_encoder(encoder)->dcb;
 637         int num_tv_norms = dcb->tvconf.has_component_output ? NUM_TV_NORMS :
 638                                                         NUM_LD_TV_NORMS;
 639         int i;
 640
 641         if (nouveau_tv_norm) {
 642                 for (i = 0; i < num_tv_norms; i++) {
 643                         if (!strcmp(nv17_tv_norm_names[i], nouveau_tv_norm)) {
 644                                 tv_enc->tv_norm = i;
 645                                 break;
 646                         }
 647                 }
 648
 649                 if (i == num_tv_norms)
 650                         NV_WARN(dev, "Invalid TV norm setting \"%s\"\n",
 651                                 nouveau_tv_norm);
 652         }
 653
 654         drm_mode_create_tv_properties(dev, num_tv_norms, nv17_tv_norm_names);
 655
 656         drm_connector_attach_property(connector,
 657                                         conf->tv_select_subconnector_property,
 658                                         tv_enc->select_subconnector);
 659         drm_connector_attach_property(connector,
 660                                         conf->tv_subconnector_property,
 661                                         tv_enc->subconnector);
 662         drm_connector_attach_property(connector,
 663                                         conf->tv_mode_property,
 664                                         tv_enc->tv_norm);
 665         drm_connector_attach_property(connector,
 666                                         conf->tv_flicker_reduction_property,
 667                                         tv_enc->flicker);
 668         drm_connector_attach_property(connector,
 669                                         conf->tv_saturation_property,
 670                                         tv_enc->saturation);
 671         drm_connector_attach_property(connector,
 672                                         conf->tv_hue_property,
 673                                         tv_enc->hue);
 674         drm_connector_attach_property(connector,
 675                                         conf->tv_overscan_property,
 676                                         tv_enc->overscan);
 677
 678         return 0;
 679 }
 680
 681 static int nv17_tv_set_property(struct drm_encoder *encoder,
 682                                 struct drm_connector *connector,
 683                                 struct drm_property *property,
 684                                 uint64_t val)
 685 {
 686         struct drm_mode_config *conf = &encoder->dev->mode_config;
 687         struct drm_crtc *crtc = encoder->crtc;
 688         struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder);
 689         struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
 690         bool modes_changed = false;
 691
 692         if (property == conf->tv_overscan_property) {
 693                 tv_enc->overscan = val;
 694                 if (encoder->crtc) {
 695                         if (tv_norm->kind == CTV_ENC_MODE)
 696                                 nv17_ctv_update_rescaler(encoder);
 697                         else
 698                                 nv17_tv_update_rescaler(encoder);
 699                 }
 700
 701         } else if (property == conf->tv_saturation_property) {
 702                 if (tv_norm->kind != TV_ENC_MODE)
 703                         return -EINVAL;
 704
 705                 tv_enc->saturation = val;
 706                 nv17_tv_update_properties(encoder);
 707
 708         } else if (property == conf->tv_hue_property) {
 709                 if (tv_norm->kind != TV_ENC_MODE)
 710                         return -EINVAL;
 711
 712                 tv_enc->hue = val;
 713                 nv17_tv_update_properties(encoder);
 714
 715         } else if (property == conf->tv_flicker_reduction_property) {
 716                 if (tv_norm->kind != TV_ENC_MODE)
 717                         return -EINVAL;
 718
 719                 tv_enc->flicker = val;
 720                 if (encoder->crtc)
 721                         nv17_tv_update_rescaler(encoder);
 722
 723         } else if (property == conf->tv_mode_property) {
 724                 if (connector->dpms != DRM_MODE_DPMS_OFF)
 725                         return -EINVAL;
 726
 727                 tv_enc->tv_norm = val;
 728
 729                 modes_changed = true;
 730
 731         } else if (property == conf->tv_select_subconnector_property) {
 732                 if (tv_norm->kind != TV_ENC_MODE)
 733                         return -EINVAL;
 734
 735                 tv_enc->select_subconnector = val;
 736                 nv17_tv_update_properties(encoder);
 737
 738         } else {
 739                 return -EINVAL;
 740         }
 741
 742         if (modes_changed) {
 743                 drm_helper_probe_single_connector_modes(connector, 0, 0);
 744
 745                 /* Disable the crtc to ensure a full modeset is
 746                  * performed whenever it's turned on again. */
 747                 if (crtc) {
 748                         struct drm_mode_set modeset = {
 749                                 .crtc = crtc,
 750                         };
 751
 752                         crtc->funcs->set_config(&modeset);
 753                 }
 754         }
 755
 756         return 0;
 757 }
 758
 759 static void nv17_tv_destroy(struct drm_encoder *encoder)
 760 {
 761         struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder);
 762
 763         NV_DEBUG_KMS(encoder->dev, "\n");
 764
 765         drm_encoder_cleanup(encoder);
 766         kfree(tv_enc);
 767 }
 768
 769 static struct drm_encoder_helper_funcs nv17_tv_helper_funcs = {
 770         .dpms = nv17_tv_dpms,
 771         .save = nv17_tv_save,
 772         .restore = nv17_tv_restore,
 773         .mode_fixup = nv17_tv_mode_fixup,
 774         .prepare = nv17_tv_prepare,
 775         .commit = nv17_tv_commit,
 776         .mode_set = nv17_tv_mode_set,
 777         .detect = nv17_tv_detect,
 778 };
 779
 780 static struct drm_encoder_slave_funcs nv17_tv_slave_funcs = {
 781         .get_modes = nv17_tv_get_modes,
 782         .mode_valid = nv17_tv_mode_valid,
 783         .create_resources = nv17_tv_create_resources,
 784         .set_property = nv17_tv_set_property,
 785 };
 786
 787 static struct drm_encoder_funcs nv17_tv_funcs = {
 788         .destroy = nv17_tv_destroy,
 789 };
 790
 791 int
 792 nv17_tv_create(struct drm_connector *connector, struct dcb_output *entry)
 793 {
 794         struct drm_device *dev = connector->dev;
 795         struct drm_encoder *encoder;
 796         struct nv17_tv_encoder *tv_enc = NULL;
 797
 798         tv_enc = kzalloc(sizeof(*tv_enc), GFP_KERNEL);
 799         if (!tv_enc)
 800                 return -ENOMEM;
 801
 802         tv_enc->overscan = 50;
 803         tv_enc->flicker = 50;
 804         tv_enc->saturation = 50;
 805         tv_enc->hue = 0;
 806         tv_enc->tv_norm = TV_NORM_PAL;
 807         tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_Unknown;
 808         tv_enc->select_subconnector = DRM_MODE_SUBCONNECTOR_Automatic;
 809         tv_enc->pin_mask = 0;
 810
 811         encoder = to_drm_encoder(&tv_enc->base);
 812
 813         tv_enc->base.dcb = entry;
 814         tv_enc->base.or = ffs(entry->or) - 1;
 815
 816         drm_encoder_init(dev, encoder, &nv17_tv_funcs, DRM_MODE_ENCODER_TVDAC);
 817         drm_encoder_helper_add(encoder, &nv17_tv_helper_funcs);
 818         to_encoder_slave(encoder)->slave_funcs = &nv17_tv_slave_funcs;
 819
 820         encoder->possible_crtcs = entry->heads;
 821         encoder->possible_clones = 0;
 822
 823         nv17_tv_create_resources(encoder, connector);
 824         drm_mode_connector_attach_encoder(connector, encoder);
 825         return 0;
 826 }