Pileus Git - ~andy/linux/blob - drivers/gpu/drm/nouveau/nouveau_mem.c

   1 /*
   2  * Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   3  * Copyright 2005 Stephane Marchesin
   4  *
   5  * The Weather Channel (TM) funded Tungsten Graphics to develop the
   6  * initial release of the Radeon 8500 driver under the XFree86 license.
   7  * This notice must be preserved.
   8  *
   9  * Permission is hereby granted, free of charge, to any person obtaining a
  10  * copy of this software and associated documentation files (the "Software"),
  11  * to deal in the Software without restriction, including without limitation
  12  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  13  * and/or sell copies of the Software, and to permit persons to whom the
  14  * Software is furnished to do so, subject to the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the next
  17  * paragraph) shall be included in all copies or substantial portions of the
  18  * Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  21  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  23  * THE AUTHORS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  24  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  25  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  26  * DEALINGS IN THE SOFTWARE.
  27  *
  28  * Authors:
  29  *    Keith Whitwell <keith@tungstengraphics.com>
  30  */
  31
  32
  33 #include "drmP.h"
  34 #include "drm.h"
  35 #include "drm_sarea.h"
  36
  37 #include "nouveau_drv.h"
  38 #include "nouveau_pm.h"
  39 #include "nouveau_mm.h"
  40 #include "nouveau_vm.h"
  41
  42 /*
  43  * NV10-NV40 tiling helpers
  44  */
  45
  46 static void
  47 nv10_mem_update_tile_region(struct drm_device *dev,
  48                             struct nouveau_tile_reg *tile, uint32_t addr,
  49                             uint32_t size, uint32_t pitch, uint32_t flags)
  50 {
  51         struct drm_nouveau_private *dev_priv = dev->dev_private;
  52         struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
  53         struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
  54         int i = tile - dev_priv->tile.reg, j;
  55         unsigned long save;
  56
  57         nouveau_fence_unref(&tile->fence);
  58
  59         if (tile->pitch)
  60                 pfb->free_tile_region(dev, i);
  61
  62         if (pitch)
  63                 pfb->init_tile_region(dev, i, addr, size, pitch, flags);
  64
  65         spin_lock_irqsave(&dev_priv->context_switch_lock, save);
  66         pfifo->reassign(dev, false);
  67         pfifo->cache_pull(dev, false);
  68
  69         nouveau_wait_for_idle(dev);
  70
  71         pfb->set_tile_region(dev, i);
  72         for (j = 0; j < NVOBJ_ENGINE_NR; j++) {
  73                 if (dev_priv->eng[j] && dev_priv->eng[j]->set_tile_region)
  74                         dev_priv->eng[j]->set_tile_region(dev, i);
  75         }
  76
  77         pfifo->cache_pull(dev, true);
  78         pfifo->reassign(dev, true);
  79         spin_unlock_irqrestore(&dev_priv->context_switch_lock, save);
  80 }
  81
  82 static struct nouveau_tile_reg *
  83 nv10_mem_get_tile_region(struct drm_device *dev, int i)
  84 {
  85         struct drm_nouveau_private *dev_priv = dev->dev_private;
  86         struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];
  87
  88         spin_lock(&dev_priv->tile.lock);
  89
  90         if (!tile->used &&
  91             (!tile->fence || nouveau_fence_signalled(tile->fence)))
  92                 tile->used = true;
  93         else
  94                 tile = NULL;
  95
  96         spin_unlock(&dev_priv->tile.lock);
  97         return tile;
  98 }
  99
 100 void
 101 nv10_mem_put_tile_region(struct drm_device *dev, struct nouveau_tile_reg *tile,
 102                          struct nouveau_fence *fence)
 103 {
 104         struct drm_nouveau_private *dev_priv = dev->dev_private;
 105
 106         if (tile) {
 107                 spin_lock(&dev_priv->tile.lock);
 108                 if (fence) {
 109                         /* Mark it as pending. */
 110                         tile->fence = fence;
 111                         nouveau_fence_ref(fence);
 112                 }
 113
 114                 tile->used = false;
 115                 spin_unlock(&dev_priv->tile.lock);
 116         }
 117 }
 118
 119 struct nouveau_tile_reg *
 120 nv10_mem_set_tiling(struct drm_device *dev, uint32_t addr, uint32_t size,
 121                     uint32_t pitch, uint32_t flags)
 122 {
 123         struct drm_nouveau_private *dev_priv = dev->dev_private;
 124         struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
 125         struct nouveau_tile_reg *tile, *found = NULL;
 126         int i;
 127
 128         for (i = 0; i < pfb->num_tiles; i++) {
 129                 tile = nv10_mem_get_tile_region(dev, i);
 130
 131                 if (pitch && !found) {
 132                         found = tile;
 133                         continue;
 134
 135                 } else if (tile && tile->pitch) {
 136                         /* Kill an unused tile region. */
 137                         nv10_mem_update_tile_region(dev, tile, 0, 0, 0, 0);
 138                 }
 139
 140                 nv10_mem_put_tile_region(dev, tile, NULL);
 141         }
 142
 143         if (found)
 144                 nv10_mem_update_tile_region(dev, found, addr, size,
 145                                             pitch, flags);
 146         return found;
 147 }
 148
 149 /*
 150  * Cleanup everything
 151  */
 152 void
 153 nouveau_mem_vram_fini(struct drm_device *dev)
 154 {
 155         struct drm_nouveau_private *dev_priv = dev->dev_private;
 156
 157         nouveau_bo_ref(NULL, &dev_priv->vga_ram);
 158
 159         ttm_bo_device_release(&dev_priv->ttm.bdev);
 160
 161         nouveau_ttm_global_release(dev_priv);
 162
 163         if (dev_priv->fb_mtrr >= 0) {
 164                 drm_mtrr_del(dev_priv->fb_mtrr,
 165                              pci_resource_start(dev->pdev, 1),
 166                              pci_resource_len(dev->pdev, 1), DRM_MTRR_WC);
 167                 dev_priv->fb_mtrr = -1;
 168         }
 169 }
 170
 171 void
 172 nouveau_mem_gart_fini(struct drm_device *dev)
 173 {
 174         nouveau_sgdma_takedown(dev);
 175
 176         if (drm_core_has_AGP(dev) && dev->agp) {
 177                 struct drm_agp_mem *entry, *tempe;
 178
 179                 /* Remove AGP resources, but leave dev->agp
 180                    intact until drv_cleanup is called. */
 181                 list_for_each_entry_safe(entry, tempe, &dev->agp->memory, head) {
 182                         if (entry->bound)
 183                                 drm_unbind_agp(entry->memory);
 184                         drm_free_agp(entry->memory, entry->pages);
 185                         kfree(entry);
 186                 }
 187                 INIT_LIST_HEAD(&dev->agp->memory);
 188
 189                 if (dev->agp->acquired)
 190                         drm_agp_release(dev);
 191
 192                 dev->agp->acquired = 0;
 193                 dev->agp->enabled = 0;
 194         }
 195 }
 196
 197 static uint32_t
 198 nouveau_mem_detect_nv04(struct drm_device *dev)
 199 {
 200         uint32_t boot0 = nv_rd32(dev, NV04_PFB_BOOT_0);
 201
 202         if (boot0 & 0x00000100)
 203                 return (((boot0 >> 12) & 0xf) * 2 + 2) * 1024 * 1024;
 204
 205         switch (boot0 & NV04_PFB_BOOT_0_RAM_AMOUNT) {
 206         case NV04_PFB_BOOT_0_RAM_AMOUNT_32MB:
 207                 return 32 * 1024 * 1024;
 208         case NV04_PFB_BOOT_0_RAM_AMOUNT_16MB:
 209                 return 16 * 1024 * 1024;
 210         case NV04_PFB_BOOT_0_RAM_AMOUNT_8MB:
 211                 return 8 * 1024 * 1024;
 212         case NV04_PFB_BOOT_0_RAM_AMOUNT_4MB:
 213                 return 4 * 1024 * 1024;
 214         }
 215
 216         return 0;
 217 }
 218
 219 static uint32_t
 220 nouveau_mem_detect_nforce(struct drm_device *dev)
 221 {
 222         struct drm_nouveau_private *dev_priv = dev->dev_private;
 223         struct pci_dev *bridge;
 224         uint32_t mem;
 225
 226         bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 1));
 227         if (!bridge) {
 228                 NV_ERROR(dev, "no bridge device\n");
 229                 return 0;
 230         }
 231
 232         if (dev_priv->flags & NV_NFORCE) {
 233                 pci_read_config_dword(bridge, 0x7C, &mem);
 234                 return (uint64_t)(((mem >> 6) & 31) + 1)*1024*1024;
 235         } else
 236         if (dev_priv->flags & NV_NFORCE2) {
 237                 pci_read_config_dword(bridge, 0x84, &mem);
 238                 return (uint64_t)(((mem >> 4) & 127) + 1)*1024*1024;
 239         }
 240
 241         NV_ERROR(dev, "impossible!\n");
 242         return 0;
 243 }
 244
 245 int
 246 nouveau_mem_detect(struct drm_device *dev)
 247 {
 248         struct drm_nouveau_private *dev_priv = dev->dev_private;
 249
 250         if (dev_priv->card_type == NV_04) {
 251                 dev_priv->vram_size = nouveau_mem_detect_nv04(dev);
 252         } else
 253         if (dev_priv->flags & (NV_NFORCE | NV_NFORCE2)) {
 254                 dev_priv->vram_size = nouveau_mem_detect_nforce(dev);
 255         } else
 256         if (dev_priv->card_type < NV_50) {
 257                 dev_priv->vram_size  = nv_rd32(dev, NV04_PFB_FIFO_DATA);
 258                 dev_priv->vram_size &= NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK;
 259         }
 260
 261         if (dev_priv->vram_size)
 262                 return 0;
 263         return -ENOMEM;
 264 }
 265
 266 bool
 267 nouveau_mem_flags_valid(struct drm_device *dev, u32 tile_flags)
 268 {
 269         if (!(tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK))
 270                 return true;
 271
 272         return false;
 273 }
 274
 275 #if __OS_HAS_AGP
 276 static unsigned long
 277 get_agp_mode(struct drm_device *dev, unsigned long mode)
 278 {
 279         struct drm_nouveau_private *dev_priv = dev->dev_private;
 280
 281         /*
 282          * FW seems to be broken on nv18, it makes the card lock up
 283          * randomly.
 284          */
 285         if (dev_priv->chipset == 0x18)
 286                 mode &= ~PCI_AGP_COMMAND_FW;
 287
 288         /*
 289          * AGP mode set in the command line.
 290          */
 291         if (nouveau_agpmode > 0) {
 292                 bool agpv3 = mode & 0x8;
 293                 int rate = agpv3 ? nouveau_agpmode / 4 : nouveau_agpmode;
 294
 295                 mode = (mode & ~0x7) | (rate & 0x7);
 296         }
 297
 298         return mode;
 299 }
 300 #endif
 301
 302 int
 303 nouveau_mem_reset_agp(struct drm_device *dev)
 304 {
 305 #if __OS_HAS_AGP
 306         uint32_t saved_pci_nv_1, pmc_enable;
 307         int ret;
 308
 309         /* First of all, disable fast writes, otherwise if it's
 310          * already enabled in the AGP bridge and we disable the card's
 311          * AGP controller we might be locking ourselves out of it. */
 312         if ((nv_rd32(dev, NV04_PBUS_PCI_NV_19) |
 313              dev->agp->mode) & PCI_AGP_COMMAND_FW) {
 314                 struct drm_agp_info info;
 315                 struct drm_agp_mode mode;
 316
 317                 ret = drm_agp_info(dev, &info);
 318                 if (ret)
 319                         return ret;
 320
 321                 mode.mode = get_agp_mode(dev, info.mode) & ~PCI_AGP_COMMAND_FW;
 322                 ret = drm_agp_enable(dev, mode);
 323                 if (ret)
 324                         return ret;
 325         }
 326
 327         saved_pci_nv_1 = nv_rd32(dev, NV04_PBUS_PCI_NV_1);
 328
 329         /* clear busmaster bit */
 330         nv_wr32(dev, NV04_PBUS_PCI_NV_1, saved_pci_nv_1 & ~0x4);
 331         /* disable AGP */
 332         nv_wr32(dev, NV04_PBUS_PCI_NV_19, 0);
 333
 334         /* power cycle pgraph, if enabled */
 335         pmc_enable = nv_rd32(dev, NV03_PMC_ENABLE);
 336         if (pmc_enable & NV_PMC_ENABLE_PGRAPH) {
 337                 nv_wr32(dev, NV03_PMC_ENABLE,
 338                                 pmc_enable & ~NV_PMC_ENABLE_PGRAPH);
 339                 nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) |
 340                                 NV_PMC_ENABLE_PGRAPH);
 341         }
 342
 343         /* and restore (gives effect of resetting AGP) */
 344         nv_wr32(dev, NV04_PBUS_PCI_NV_1, saved_pci_nv_1);
 345 #endif
 346
 347         return 0;
 348 }
 349
 350 int
 351 nouveau_mem_init_agp(struct drm_device *dev)
 352 {
 353 #if __OS_HAS_AGP
 354         struct drm_nouveau_private *dev_priv = dev->dev_private;
 355         struct drm_agp_info info;
 356         struct drm_agp_mode mode;
 357         int ret;
 358
 359         if (!dev->agp->acquired) {
 360                 ret = drm_agp_acquire(dev);
 361                 if (ret) {
 362                         NV_ERROR(dev, "Unable to acquire AGP: %d\n", ret);
 363                         return ret;
 364                 }
 365         }
 366
 367         nouveau_mem_reset_agp(dev);
 368
 369         ret = drm_agp_info(dev, &info);
 370         if (ret) {
 371                 NV_ERROR(dev, "Unable to get AGP info: %d\n", ret);
 372                 return ret;
 373         }
 374
 375         /* see agp.h for the AGPSTAT_* modes available */
 376         mode.mode = get_agp_mode(dev, info.mode);
 377         ret = drm_agp_enable(dev, mode);
 378         if (ret) {
 379                 NV_ERROR(dev, "Unable to enable AGP: %d\n", ret);
 380                 return ret;
 381         }
 382
 383         dev_priv->gart_info.type        = NOUVEAU_GART_AGP;
 384         dev_priv->gart_info.aper_base   = info.aperture_base;
 385         dev_priv->gart_info.aper_size   = info.aperture_size;
 386 #endif
 387         return 0;
 388 }
 389
 390 int
 391 nouveau_mem_vram_init(struct drm_device *dev)
 392 {
 393         struct drm_nouveau_private *dev_priv = dev->dev_private;
 394         struct ttm_bo_device *bdev = &dev_priv->ttm.bdev;
 395         int ret, dma_bits;
 396
 397         dma_bits = 32;
 398         if (dev_priv->card_type >= NV_50) {
 399                 if (pci_dma_supported(dev->pdev, DMA_BIT_MASK(40)))
 400                         dma_bits = 40;
 401         } else
 402         if (drm_pci_device_is_pcie(dev) &&
 403             dev_priv->chipset  > 0x40 &&
 404             dev_priv->chipset != 0x45) {
 405                 if (pci_dma_supported(dev->pdev, DMA_BIT_MASK(39)))
 406                         dma_bits = 39;
 407         }
 408
 409         ret = pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(dma_bits));
 410         if (ret)
 411                 return ret;
 412
 413         dev_priv->fb_phys = pci_resource_start(dev->pdev, 1);
 414
 415         ret = nouveau_ttm_global_init(dev_priv);
 416         if (ret)
 417                 return ret;
 418
 419         ret = ttm_bo_device_init(&dev_priv->ttm.bdev,
 420                                  dev_priv->ttm.bo_global_ref.ref.object,
 421                                  &nouveau_bo_driver, DRM_FILE_PAGE_OFFSET,
 422                                  dma_bits <= 32 ? true : false);
 423         if (ret) {
 424                 NV_ERROR(dev, "Error initialising bo driver: %d\n", ret);
 425                 return ret;
 426         }
 427
 428         /* reserve space at end of VRAM for PRAMIN */
 429         if (dev_priv->card_type >= NV_50) {
 430                 dev_priv->ramin_rsvd_vram = 1 * 1024 * 1024;
 431         } else
 432         if (dev_priv->card_type >= NV_40) {
 433                 u32 vs = hweight8((nv_rd32(dev, 0x001540) & 0x0000ff00) >> 8);
 434                 u32 rsvd;
 435
 436                 /* estimate grctx size, the magics come from nv40_grctx.c */
 437                 if      (dev_priv->chipset == 0x40) rsvd = 0x6aa0 * vs;
 438                 else if (dev_priv->chipset  < 0x43) rsvd = 0x4f00 * vs;
 439                 else if (nv44_graph_class(dev))     rsvd = 0x4980 * vs;
 440                 else                                rsvd = 0x4a40 * vs;
 441                 rsvd += 16 * 1024;
 442                 rsvd *= dev_priv->engine.fifo.channels;
 443
 444                 /* pciegart table */
 445                 if (drm_pci_device_is_pcie(dev))
 446                         rsvd += 512 * 1024;
 447
 448                 /* object storage */
 449                 rsvd += 512 * 1024;
 450
 451                 dev_priv->ramin_rsvd_vram = round_up(rsvd, 4096);
 452         } else {
 453                 dev_priv->ramin_rsvd_vram = 512 * 1024;
 454         }
 455
 456         ret = dev_priv->engine.vram.init(dev);
 457         if (ret)
 458                 return ret;
 459
 460         NV_INFO(dev, "Detected %dMiB VRAM\n", (int)(dev_priv->vram_size >> 20));
 461         if (dev_priv->vram_sys_base) {
 462                 NV_INFO(dev, "Stolen system memory at: 0x%010llx\n",
 463                         dev_priv->vram_sys_base);
 464         }
 465
 466         dev_priv->fb_available_size = dev_priv->vram_size;
 467         dev_priv->fb_mappable_pages = dev_priv->fb_available_size;
 468         if (dev_priv->fb_mappable_pages > pci_resource_len(dev->pdev, 1))
 469                 dev_priv->fb_mappable_pages = pci_resource_len(dev->pdev, 1);
 470         dev_priv->fb_mappable_pages >>= PAGE_SHIFT;
 471
 472         dev_priv->fb_available_size -= dev_priv->ramin_rsvd_vram;
 473         dev_priv->fb_aper_free = dev_priv->fb_available_size;
 474
 475         /* mappable vram */
 476         ret = ttm_bo_init_mm(bdev, TTM_PL_VRAM,
 477                              dev_priv->fb_available_size >> PAGE_SHIFT);
 478         if (ret) {
 479                 NV_ERROR(dev, "Failed VRAM mm init: %d\n", ret);
 480                 return ret;
 481         }
 482
 483         if (dev_priv->card_type < NV_50) {
 484                 ret = nouveau_bo_new(dev, NULL, 256*1024, 0, TTM_PL_FLAG_VRAM,
 485                                      0, 0, &dev_priv->vga_ram);
 486                 if (ret == 0)
 487                         ret = nouveau_bo_pin(dev_priv->vga_ram,
 488                                              TTM_PL_FLAG_VRAM);
 489
 490                 if (ret) {
 491                         NV_WARN(dev, "failed to reserve VGA memory\n");
 492                         nouveau_bo_ref(NULL, &dev_priv->vga_ram);
 493                 }
 494         }
 495
 496         dev_priv->fb_mtrr = drm_mtrr_add(pci_resource_start(dev->pdev, 1),
 497                                          pci_resource_len(dev->pdev, 1),
 498                                          DRM_MTRR_WC);
 499         return 0;
 500 }
 501
 502 int
 503 nouveau_mem_gart_init(struct drm_device *dev)
 504 {
 505         struct drm_nouveau_private *dev_priv = dev->dev_private;
 506         struct ttm_bo_device *bdev = &dev_priv->ttm.bdev;
 507         int ret;
 508
 509         dev_priv->gart_info.type = NOUVEAU_GART_NONE;
 510
 511 #if !defined(__powerpc__) && !defined(__ia64__)
 512         if (drm_pci_device_is_agp(dev) && dev->agp && nouveau_agpmode) {
 513                 ret = nouveau_mem_init_agp(dev);
 514                 if (ret)
 515                         NV_ERROR(dev, "Error initialising AGP: %d\n", ret);
 516         }
 517 #endif
 518
 519         if (dev_priv->gart_info.type == NOUVEAU_GART_NONE) {
 520                 ret = nouveau_sgdma_init(dev);
 521                 if (ret) {
 522                         NV_ERROR(dev, "Error initialising PCI(E): %d\n", ret);
 523                         return ret;
 524                 }
 525         }
 526
 527         NV_INFO(dev, "%d MiB GART (aperture)\n",
 528                 (int)(dev_priv->gart_info.aper_size >> 20));
 529         dev_priv->gart_info.aper_free = dev_priv->gart_info.aper_size;
 530
 531         ret = ttm_bo_init_mm(bdev, TTM_PL_TT,
 532                              dev_priv->gart_info.aper_size >> PAGE_SHIFT);
 533         if (ret) {
 534                 NV_ERROR(dev, "Failed TT mm init: %d\n", ret);
 535                 return ret;
 536         }
 537
 538         return 0;
 539 }
 540
 541 void
 542 nouveau_mem_timing_init(struct drm_device *dev)
 543 {
 544         /* cards < NVC0 only */
 545         struct drm_nouveau_private *dev_priv = dev->dev_private;
 546         struct nouveau_pm_engine *pm = &dev_priv->engine.pm;
 547         struct nouveau_pm_memtimings *memtimings = &pm->memtimings;
 548         struct nvbios *bios = &dev_priv->vbios;
 549         struct bit_entry P;
 550         u8 tUNK_0, tUNK_1, tUNK_2;
 551         u8 tRP;         /* Byte 3 */
 552         u8 tRAS;        /* Byte 5 */
 553         u8 tRFC;        /* Byte 7 */
 554         u8 tRC;         /* Byte 9 */
 555         u8 tUNK_10, tUNK_11, tUNK_12, tUNK_13, tUNK_14;
 556         u8 tUNK_18, tUNK_19, tUNK_20, tUNK_21;
 557         u8 magic_number = 0; /* Yeah... sorry*/
 558         u8 *mem = NULL, *entry;
 559         int i, recordlen, entries;
 560
 561         if (bios->type == NVBIOS_BIT) {
 562                 if (bit_table(dev, 'P', &P))
 563                         return;
 564
 565                 if (P.version == 1)
 566                         mem = ROMPTR(bios, P.data[4]);
 567                 else
 568                 if (P.version == 2)
 569                         mem = ROMPTR(bios, P.data[8]);
 570                 else {
 571                         NV_WARN(dev, "unknown mem for BIT P %d\n", P.version);
 572                 }
 573         } else {
 574                 NV_DEBUG(dev, "BMP version too old for memory\n");
 575                 return;
 576         }
 577
 578         if (!mem) {
 579                 NV_DEBUG(dev, "memory timing table pointer invalid\n");
 580                 return;
 581         }
 582
 583         if (mem[0] != 0x10) {
 584                 NV_WARN(dev, "memory timing table 0x%02x unknown\n", mem[0]);
 585                 return;
 586         }
 587
 588         /* validate record length */
 589         entries   = mem[2];
 590         recordlen = mem[3];
 591         if (recordlen < 15) {
 592                 NV_ERROR(dev, "mem timing table length unknown: %d\n", mem[3]);
 593                 return;
 594         }
 595
 596         /* parse vbios entries into common format */
 597         memtimings->timing =
 598                 kcalloc(entries, sizeof(*memtimings->timing), GFP_KERNEL);
 599         if (!memtimings->timing)
 600                 return;
 601
 602         /* Get "some number" from the timing reg for NV_40 and NV_50
 603          * Used in calculations later */
 604         if (dev_priv->card_type >= NV_40 && dev_priv->chipset < 0x98) {
 605                 magic_number = (nv_rd32(dev, 0x100228) & 0x0f000000) >> 24;
 606         }
 607
 608         entry = mem + mem[1];
 609         for (i = 0; i < entries; i++, entry += recordlen) {
 610                 struct nouveau_pm_memtiming *timing = &pm->memtimings.timing[i];
 611                 if (entry[0] == 0)
 612                         continue;
 613
 614                 tUNK_18 = 1;
 615                 tUNK_19 = 1;
 616                 tUNK_20 = 0;
 617                 tUNK_21 = 0;
 618                 switch (min(recordlen, 22)) {
 619                 case 22:
 620                         tUNK_21 = entry[21];
 621                 case 21:
 622                         tUNK_20 = entry[20];
 623                 case 20:
 624                         tUNK_19 = entry[19];
 625                 case 19:
 626                         tUNK_18 = entry[18];
 627                 default:
 628                         tUNK_0  = entry[0];
 629                         tUNK_1  = entry[1];
 630                         tUNK_2  = entry[2];
 631                         tRP     = entry[3];
 632                         tRAS    = entry[5];
 633                         tRFC    = entry[7];
 634                         tRC     = entry[9];
 635                         tUNK_10 = entry[10];
 636                         tUNK_11 = entry[11];
 637                         tUNK_12 = entry[12];
 638                         tUNK_13 = entry[13];
 639                         tUNK_14 = entry[14];
 640                         break;
 641                 }
 642
 643                 timing->reg_100220 = (tRC << 24 | tRFC << 16 | tRAS << 8 | tRP);
 644
 645                 /* XXX: I don't trust the -1's and +1's... they must come
 646                  *      from somewhere! */
 647                 timing->reg_100224 = (tUNK_0 + tUNK_19 + 1 + magic_number) << 24 |
 648                                       max(tUNK_18, (u8) 1) << 16 |
 649                                       (tUNK_1 + tUNK_19 + 1 + magic_number) << 8;
 650                 if (dev_priv->chipset == 0xa8) {
 651                         timing->reg_100224 |= (tUNK_2 - 1);
 652                 } else {
 653                         timing->reg_100224 |= (tUNK_2 + 2 - magic_number);
 654                 }
 655
 656                 timing->reg_100228 = (tUNK_12 << 16 | tUNK_11 << 8 | tUNK_10);
 657                 if (dev_priv->chipset >= 0xa3 && dev_priv->chipset < 0xaa)
 658                         timing->reg_100228 |= (tUNK_19 - 1) << 24;
 659                 else
 660                         timing->reg_100228 |= magic_number << 24;
 661
 662                 if (dev_priv->card_type == NV_40) {
 663                         /* NV40: don't know what the rest of the regs are..
 664                          * And don't need to know either */
 665                         timing->reg_100228 |= 0x20200000;
 666                 } else if (dev_priv->card_type >= NV_50) {
 667                         if (dev_priv->chipset < 0x98 ||
 668                             (dev_priv->chipset == 0x98 &&
 669                              dev_priv->stepping <= 0xa1)) {
 670                                 timing->reg_10022c = (0x14 + tUNK_2) << 24 |
 671                                                      0x16 << 16 |
 672                                                      (tUNK_2 - 1) << 8 |
 673                                                      (tUNK_2 - 1);
 674                         } else {
 675                                 /* XXX: reg_10022c for recentish cards */
 676                                 timing->reg_10022c = tUNK_2 - 1;
 677                         }
 678
 679                         timing->reg_100230 = (tUNK_20 << 24 | tUNK_21 << 16 |
 680                                                   tUNK_13 << 8  | tUNK_13);
 681
 682                         timing->reg_100234 = (tRAS << 24 | tRC);
 683                         timing->reg_100234 += max(tUNK_10, tUNK_11) << 16;
 684
 685                         if (dev_priv->chipset < 0x98 ||
 686                             (dev_priv->chipset == 0x98 &&
 687                              dev_priv->stepping <= 0xa1)) {
 688                                 timing->reg_100234 |= (tUNK_2 + 2) << 8;
 689                         } else {
 690                                 /* XXX: +6? */
 691                                 timing->reg_100234 |= (tUNK_19 + 6) << 8;
 692                         }
 693
 694                         /* XXX; reg_100238
 695                          * reg_100238: 0x00?????? */
 696                         timing->reg_10023c = 0x202;
 697                         if (dev_priv->chipset < 0x98 ||
 698                             (dev_priv->chipset == 0x98 &&
 699                              dev_priv->stepping <= 0xa1)) {
 700                                 timing->reg_10023c |= 0x4000000 | (tUNK_2 - 1) << 16;
 701                         } else {
 702                                 /* XXX: reg_10023c
 703                                  * currently unknown
 704                                  * 10023c seen as 06xxxxxx, 0bxxxxxx or 0fxxxxxx */
 705                         }
 706
 707                         /* XXX: reg_100240? */
 708                 }
 709
 710                 NV_DEBUG(dev, "Entry %d: 220: %08x %08x %08x %08x\n", i,
 711                          timing->reg_100220, timing->reg_100224,
 712                          timing->reg_100228, timing->reg_10022c);
 713                 NV_DEBUG(dev, "         230: %08x %08x %08x %08x\n",
 714                          timing->reg_100230, timing->reg_100234,
 715                          timing->reg_100238, timing->reg_10023c);
 716                 NV_DEBUG(dev, "         240: %08x\n", timing->reg_100240);
 717         }
 718
 719         memtimings->nr_timing = entries;
 720         memtimings->supported = true;
 721 }
 722
 723 void
 724 nouveau_mem_timing_fini(struct drm_device *dev)
 725 {
 726         struct drm_nouveau_private *dev_priv = dev->dev_private;
 727         struct nouveau_pm_memtimings *mem = &dev_priv->engine.pm.memtimings;
 728
 729         kfree(mem->timing);
 730 }
 731
 732 static int
 733 nouveau_vram_manager_init(struct ttm_mem_type_manager *man, unsigned long p_size)
 734 {
 735         struct drm_nouveau_private *dev_priv = nouveau_bdev(man->bdev);
 736         struct nouveau_mm *mm;
 737         u64 size, block, rsvd;
 738         int ret;
 739
 740         rsvd  = (256 * 1024); /* vga memory */
 741         size  = (p_size << PAGE_SHIFT) - rsvd;
 742         block = dev_priv->vram_rblock_size;
 743
 744         ret = nouveau_mm_init(&mm, rsvd >> 12, size >> 12, block >> 12);
 745         if (ret)
 746                 return ret;
 747
 748         man->priv = mm;
 749         return 0;
 750 }
 751
 752 static int
 753 nouveau_vram_manager_fini(struct ttm_mem_type_manager *man)
 754 {
 755         struct nouveau_mm *mm = man->priv;
 756         int ret;
 757
 758         ret = nouveau_mm_fini(&mm);
 759         if (ret)
 760                 return ret;
 761
 762         man->priv = NULL;
 763         return 0;
 764 }
 765
 766 static void
 767 nouveau_vram_manager_del(struct ttm_mem_type_manager *man,
 768                          struct ttm_mem_reg *mem)
 769 {
 770         struct drm_nouveau_private *dev_priv = nouveau_bdev(man->bdev);
 771         struct nouveau_vram_engine *vram = &dev_priv->engine.vram;
 772         struct nouveau_mem *node = mem->mm_node;
 773         struct drm_device *dev = dev_priv->dev;
 774
 775         if (node->tmp_vma.node) {
 776                 nouveau_vm_unmap(&node->tmp_vma);
 777                 nouveau_vm_put(&node->tmp_vma);
 778         }
 779
 780         vram->put(dev, (struct nouveau_mem **)&mem->mm_node);
 781 }
 782
 783 static int
 784 nouveau_vram_manager_new(struct ttm_mem_type_manager *man,
 785                          struct ttm_buffer_object *bo,
 786                          struct ttm_placement *placement,
 787                          struct ttm_mem_reg *mem)
 788 {
 789         struct drm_nouveau_private *dev_priv = nouveau_bdev(man->bdev);
 790         struct nouveau_vram_engine *vram = &dev_priv->engine.vram;
 791         struct drm_device *dev = dev_priv->dev;
 792         struct nouveau_bo *nvbo = nouveau_bo(bo);
 793         struct nouveau_mem *node;
 794         u32 size_nc = 0;
 795         int ret;
 796
 797         if (nvbo->tile_flags & NOUVEAU_GEM_TILE_NONCONTIG)
 798                 size_nc = 1 << nvbo->vma.node->type;
 799
 800         ret = vram->get(dev, mem->num_pages << PAGE_SHIFT,
 801                         mem->page_alignment << PAGE_SHIFT, size_nc,
 802                         (nvbo->tile_flags >> 8) & 0x3ff, &node);
 803         if (ret) {
 804                 mem->mm_node = NULL;
 805                 return (ret == -ENOSPC) ? 0 : ret;
 806         }
 807
 808         node->page_shift = 12;
 809         if (nvbo->vma.node)
 810                 node->page_shift = nvbo->vma.node->type;
 811
 812         mem->mm_node = node;
 813         mem->start   = node->offset >> PAGE_SHIFT;
 814         return 0;
 815 }
 816
 817 void
 818 nouveau_vram_manager_debug(struct ttm_mem_type_manager *man, const char *prefix)
 819 {
 820         struct nouveau_mm *mm = man->priv;
 821         struct nouveau_mm_node *r;
 822         u32 total = 0, free = 0;
 823
 824         mutex_lock(&mm->mutex);
 825         list_for_each_entry(r, &mm->nodes, nl_entry) {
 826                 printk(KERN_DEBUG "%s %d: 0x%010llx 0x%010llx\n",
 827                        prefix, r->type, ((u64)r->offset << 12),
 828                        (((u64)r->offset + r->length) << 12));
 829
 830                 total += r->length;
 831                 if (!r->type)
 832                         free += r->length;
 833         }
 834         mutex_unlock(&mm->mutex);
 835
 836         printk(KERN_DEBUG "%s  total: 0x%010llx free: 0x%010llx\n",
 837                prefix, (u64)total << 12, (u64)free << 12);
 838         printk(KERN_DEBUG "%s  block: 0x%08x\n",
 839                prefix, mm->block_size << 12);
 840 }
 841
 842 const struct ttm_mem_type_manager_func nouveau_vram_manager = {
 843         nouveau_vram_manager_init,
 844         nouveau_vram_manager_fini,
 845         nouveau_vram_manager_new,
 846         nouveau_vram_manager_del,
 847         nouveau_vram_manager_debug
 848 };
 849
 850 static int
 851 nouveau_gart_manager_init(struct ttm_mem_type_manager *man, unsigned long psize)
 852 {
 853         return 0;
 854 }
 855
 856 static int
 857 nouveau_gart_manager_fini(struct ttm_mem_type_manager *man)
 858 {
 859         return 0;
 860 }
 861
 862 static void
 863 nouveau_gart_manager_del(struct ttm_mem_type_manager *man,
 864                          struct ttm_mem_reg *mem)
 865 {
 866         struct nouveau_mem *node = mem->mm_node;
 867
 868         if (node->tmp_vma.node) {
 869                 nouveau_vm_unmap(&node->tmp_vma);
 870                 nouveau_vm_put(&node->tmp_vma);
 871         }
 872         mem->mm_node = NULL;
 873 }
 874
 875 static int
 876 nouveau_gart_manager_new(struct ttm_mem_type_manager *man,
 877                          struct ttm_buffer_object *bo,
 878                          struct ttm_placement *placement,
 879                          struct ttm_mem_reg *mem)
 880 {
 881         struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
 882         struct nouveau_bo *nvbo = nouveau_bo(bo);
 883         struct nouveau_vma *vma = &nvbo->vma;
 884         struct nouveau_vm *vm = vma->vm;
 885         struct nouveau_mem *node;
 886         int ret;
 887
 888         if (unlikely((mem->num_pages << PAGE_SHIFT) >=
 889                      dev_priv->gart_info.aper_size))
 890                 return -ENOMEM;
 891
 892         node = kzalloc(sizeof(*node), GFP_KERNEL);
 893         if (!node)
 894                 return -ENOMEM;
 895
 896         /* This node must be for evicting large-paged VRAM
 897          * to system memory.  Due to a nv50 limitation of
 898          * not being able to mix large/small pages within
 899          * the same PDE, we need to create a temporary
 900          * small-paged VMA for the eviction.
 901          */
 902         if (vma->node->type != vm->spg_shift) {
 903                 ret = nouveau_vm_get(vm, (u64)vma->node->length << 12,
 904                                      vm->spg_shift, NV_MEM_ACCESS_RW,
 905                                      &node->tmp_vma);
 906                 if (ret) {
 907                         kfree(node);
 908                         return ret;
 909                 }
 910         }
 911
 912         node->page_shift = nvbo->vma.node->type;
 913         mem->mm_node = node;
 914         mem->start   = 0;
 915         return 0;
 916 }
 917
 918 void
 919 nouveau_gart_manager_debug(struct ttm_mem_type_manager *man, const char *prefix)
 920 {
 921 }
 922
 923 const struct ttm_mem_type_manager_func nouveau_gart_manager = {
 924         nouveau_gart_manager_init,
 925         nouveau_gart_manager_fini,
 926         nouveau_gart_manager_new,
 927         nouveau_gart_manager_del,
 928         nouveau_gart_manager_debug
 929 };