Pileus Git - ~andy/linux/blob - drivers/gpu/drm/nouveau/nouveau_bo.c

   1 /*
   2  * Copyright 2007 Dave Airlied
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  */
  24 /*
  25  * Authors: Dave Airlied <airlied@linux.ie>
  26  *          Ben Skeggs   <darktama@iinet.net.au>
  27  *          Jeremy Kolb  <jkolb@brandeis.edu>
  28  */
  29
  30 #include "drmP.h"
  31
  32 #include "nouveau_drm.h"
  33 #include "nouveau_drv.h"
  34 #include "nouveau_dma.h"
  35 #include "nouveau_mm.h"
  36 #include "nouveau_vm.h"
  37
  38 #include <linux/log2.h>
  39 #include <linux/slab.h>
  40
  41 static void
  42 nouveau_bo_del_ttm(struct ttm_buffer_object *bo)
  43 {
  44         struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
  45         struct drm_device *dev = dev_priv->dev;
  46         struct nouveau_bo *nvbo = nouveau_bo(bo);
  47
  48         if (unlikely(nvbo->gem))
  49                 DRM_ERROR("bo %p still attached to GEM object\n", bo);
  50
  51         nv10_mem_put_tile_region(dev, nvbo->tile, NULL);
  52         if (nvbo->vma.node) {
  53                 nouveau_vm_unmap(&nvbo->vma);
  54                 nouveau_vm_put(&nvbo->vma);
  55         }
  56         kfree(nvbo);
  57 }
  58
  59 static void
  60 nouveau_bo_fixup_align(struct nouveau_bo *nvbo, u32 flags,
  61                        int *align, int *size)
  62 {
  63         struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev);
  64
  65         if (dev_priv->card_type < NV_50) {
  66                 if (nvbo->tile_mode) {
  67                         if (dev_priv->chipset >= 0x40) {
  68                                 *align = 65536;
  69                                 *size = roundup(*size, 64 * nvbo->tile_mode);
  70
  71                         } else if (dev_priv->chipset >= 0x30) {
  72                                 *align = 32768;
  73                                 *size = roundup(*size, 64 * nvbo->tile_mode);
  74
  75                         } else if (dev_priv->chipset >= 0x20) {
  76                                 *align = 16384;
  77                                 *size = roundup(*size, 64 * nvbo->tile_mode);
  78
  79                         } else if (dev_priv->chipset >= 0x10) {
  80                                 *align = 16384;
  81                                 *size = roundup(*size, 32 * nvbo->tile_mode);
  82                         }
  83                 }
  84         } else {
  85                 *size = roundup(*size, (1 << nvbo->page_shift));
  86                 *align = max((1 <<  nvbo->page_shift), *align);
  87         }
  88
  89         *size = roundup(*size, PAGE_SIZE);
  90 }
  91
  92 int
  93 nouveau_bo_new(struct drm_device *dev, struct nouveau_channel *chan,
  94                int size, int align, uint32_t flags, uint32_t tile_mode,
  95                uint32_t tile_flags, struct nouveau_bo **pnvbo)
  96 {
  97         struct drm_nouveau_private *dev_priv = dev->dev_private;
  98         struct nouveau_bo *nvbo;
  99         int ret;
 100
 101         nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL);
 102         if (!nvbo)
 103                 return -ENOMEM;
 104         INIT_LIST_HEAD(&nvbo->head);
 105         INIT_LIST_HEAD(&nvbo->entry);
 106         nvbo->tile_mode = tile_mode;
 107         nvbo->tile_flags = tile_flags;
 108         nvbo->bo.bdev = &dev_priv->ttm.bdev;
 109
 110         nvbo->page_shift = 12;
 111         if (dev_priv->bar1_vm) {
 112                 if (!(flags & TTM_PL_FLAG_TT) && size > 256 * 1024)
 113                         nvbo->page_shift = dev_priv->bar1_vm->lpg_shift;
 114         }
 115
 116         nouveau_bo_fixup_align(nvbo, flags, &align, &size);
 117         align >>= PAGE_SHIFT;
 118
 119         if (dev_priv->chan_vm) {
 120                 ret = nouveau_vm_get(dev_priv->chan_vm, size, nvbo->page_shift,
 121                                      NV_MEM_ACCESS_RW, &nvbo->vma);
 122                 if (ret) {
 123                         kfree(nvbo);
 124                         return ret;
 125                 }
 126         }
 127
 128         nvbo->bo.mem.num_pages = size >> PAGE_SHIFT;
 129         nouveau_bo_placement_set(nvbo, flags, 0);
 130
 131         nvbo->channel = chan;
 132         ret = ttm_bo_init(&dev_priv->ttm.bdev, &nvbo->bo, size,
 133                           ttm_bo_type_device, &nvbo->placement, align, 0,
 134                           false, NULL, size, nouveau_bo_del_ttm);
 135         if (ret) {
 136                 /* ttm will call nouveau_bo_del_ttm if it fails.. */
 137                 return ret;
 138         }
 139         nvbo->channel = NULL;
 140
 141         if (nvbo->vma.node)
 142                 nvbo->bo.offset = nvbo->vma.offset;
 143         *pnvbo = nvbo;
 144         return 0;
 145 }
 146
 147 static void
 148 set_placement_list(uint32_t *pl, unsigned *n, uint32_t type, uint32_t flags)
 149 {
 150         *n = 0;
 151
 152         if (type & TTM_PL_FLAG_VRAM)
 153                 pl[(*n)++] = TTM_PL_FLAG_VRAM | flags;
 154         if (type & TTM_PL_FLAG_TT)
 155                 pl[(*n)++] = TTM_PL_FLAG_TT | flags;
 156         if (type & TTM_PL_FLAG_SYSTEM)
 157                 pl[(*n)++] = TTM_PL_FLAG_SYSTEM | flags;
 158 }
 159
 160 static void
 161 set_placement_range(struct nouveau_bo *nvbo, uint32_t type)
 162 {
 163         struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev);
 164         int vram_pages = dev_priv->vram_size >> PAGE_SHIFT;
 165
 166         if (dev_priv->card_type == NV_10 &&
 167             nvbo->tile_mode && (type & TTM_PL_FLAG_VRAM) &&
 168             nvbo->bo.mem.num_pages < vram_pages / 2) {
 169                 /*
 170                  * Make sure that the color and depth buffers are handled
 171                  * by independent memory controller units. Up to a 9x
 172                  * speed up when alpha-blending and depth-test are enabled
 173                  * at the same time.
 174                  */
 175                 if (nvbo->tile_flags & NOUVEAU_GEM_TILE_ZETA) {
 176                         nvbo->placement.fpfn = vram_pages / 2;
 177                         nvbo->placement.lpfn = ~0;
 178                 } else {
 179                         nvbo->placement.fpfn = 0;
 180                         nvbo->placement.lpfn = vram_pages / 2;
 181                 }
 182         }
 183 }
 184
 185 void
 186 nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t type, uint32_t busy)
 187 {
 188         struct ttm_placement *pl = &nvbo->placement;
 189         uint32_t flags = TTM_PL_MASK_CACHING |
 190                 (nvbo->pin_refcnt ? TTM_PL_FLAG_NO_EVICT : 0);
 191
 192         pl->placement = nvbo->placements;
 193         set_placement_list(nvbo->placements, &pl->num_placement,
 194                            type, flags);
 195
 196         pl->busy_placement = nvbo->busy_placements;
 197         set_placement_list(nvbo->busy_placements, &pl->num_busy_placement,
 198                            type | busy, flags);
 199
 200         set_placement_range(nvbo, type);
 201 }
 202
 203 int
 204 nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t memtype)
 205 {
 206         struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev);
 207         struct ttm_buffer_object *bo = &nvbo->bo;
 208         int ret;
 209
 210         if (nvbo->pin_refcnt && !(memtype & (1 << bo->mem.mem_type))) {
 211                 NV_ERROR(nouveau_bdev(bo->bdev)->dev,
 212                          "bo %p pinned elsewhere: 0x%08x vs 0x%08x\n", bo,
 213                          1 << bo->mem.mem_type, memtype);
 214                 return -EINVAL;
 215         }
 216
 217         if (nvbo->pin_refcnt++)
 218                 return 0;
 219
 220         ret = ttm_bo_reserve(bo, false, false, false, 0);
 221         if (ret)
 222                 goto out;
 223
 224         nouveau_bo_placement_set(nvbo, memtype, 0);
 225
 226         ret = nouveau_bo_validate(nvbo, false, false, false);
 227         if (ret == 0) {
 228                 switch (bo->mem.mem_type) {
 229                 case TTM_PL_VRAM:
 230                         dev_priv->fb_aper_free -= bo->mem.size;
 231                         break;
 232                 case TTM_PL_TT:
 233                         dev_priv->gart_info.aper_free -= bo->mem.size;
 234                         break;
 235                 default:
 236                         break;
 237                 }
 238         }
 239         ttm_bo_unreserve(bo);
 240 out:
 241         if (unlikely(ret))
 242                 nvbo->pin_refcnt--;
 243         return ret;
 244 }
 245
 246 int
 247 nouveau_bo_unpin(struct nouveau_bo *nvbo)
 248 {
 249         struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev);
 250         struct ttm_buffer_object *bo = &nvbo->bo;
 251         int ret;
 252
 253         if (--nvbo->pin_refcnt)
 254                 return 0;
 255
 256         ret = ttm_bo_reserve(bo, false, false, false, 0);
 257         if (ret)
 258                 return ret;
 259
 260         nouveau_bo_placement_set(nvbo, bo->mem.placement, 0);
 261
 262         ret = nouveau_bo_validate(nvbo, false, false, false);
 263         if (ret == 0) {
 264                 switch (bo->mem.mem_type) {
 265                 case TTM_PL_VRAM:
 266                         dev_priv->fb_aper_free += bo->mem.size;
 267                         break;
 268                 case TTM_PL_TT:
 269                         dev_priv->gart_info.aper_free += bo->mem.size;
 270                         break;
 271                 default:
 272                         break;
 273                 }
 274         }
 275
 276         ttm_bo_unreserve(bo);
 277         return ret;
 278 }
 279
 280 int
 281 nouveau_bo_map(struct nouveau_bo *nvbo)
 282 {
 283         int ret;
 284
 285         ret = ttm_bo_reserve(&nvbo->bo, false, false, false, 0);
 286         if (ret)
 287                 return ret;
 288
 289         ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.mem.num_pages, &nvbo->kmap);
 290         ttm_bo_unreserve(&nvbo->bo);
 291         return ret;
 292 }
 293
 294 void
 295 nouveau_bo_unmap(struct nouveau_bo *nvbo)
 296 {
 297         if (nvbo)
 298                 ttm_bo_kunmap(&nvbo->kmap);
 299 }
 300
 301 int
 302 nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible,
 303                     bool no_wait_reserve, bool no_wait_gpu)
 304 {
 305         int ret;
 306
 307         ret = ttm_bo_validate(&nvbo->bo, &nvbo->placement, interruptible,
 308                               no_wait_reserve, no_wait_gpu);
 309         if (ret)
 310                 return ret;
 311
 312         return 0;
 313 }
 314
 315 u16
 316 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index)
 317 {
 318         bool is_iomem;
 319         u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
 320         mem = &mem[index];
 321         if (is_iomem)
 322                 return ioread16_native((void __force __iomem *)mem);
 323         else
 324                 return *mem;
 325 }
 326
 327 void
 328 nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val)
 329 {
 330         bool is_iomem;
 331         u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
 332         mem = &mem[index];
 333         if (is_iomem)
 334                 iowrite16_native(val, (void __force __iomem *)mem);
 335         else
 336                 *mem = val;
 337 }
 338
 339 u32
 340 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index)
 341 {
 342         bool is_iomem;
 343         u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
 344         mem = &mem[index];
 345         if (is_iomem)
 346                 return ioread32_native((void __force __iomem *)mem);
 347         else
 348                 return *mem;
 349 }
 350
 351 void
 352 nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val)
 353 {
 354         bool is_iomem;
 355         u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
 356         mem = &mem[index];
 357         if (is_iomem)
 358                 iowrite32_native(val, (void __force __iomem *)mem);
 359         else
 360                 *mem = val;
 361 }
 362
 363 static struct ttm_backend *
 364 nouveau_bo_create_ttm_backend_entry(struct ttm_bo_device *bdev)
 365 {
 366         struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev);
 367         struct drm_device *dev = dev_priv->dev;
 368
 369         switch (dev_priv->gart_info.type) {
 370 #if __OS_HAS_AGP
 371         case NOUVEAU_GART_AGP:
 372                 return ttm_agp_backend_init(bdev, dev->agp->bridge);
 373 #endif
 374         case NOUVEAU_GART_PDMA:
 375         case NOUVEAU_GART_HW:
 376                 return nouveau_sgdma_init_ttm(dev);
 377         default:
 378                 NV_ERROR(dev, "Unknown GART type %d\n",
 379                          dev_priv->gart_info.type);
 380                 break;
 381         }
 382
 383         return NULL;
 384 }
 385
 386 static int
 387 nouveau_bo_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
 388 {
 389         /* We'll do this from user space. */
 390         return 0;
 391 }
 392
 393 static int
 394 nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
 395                          struct ttm_mem_type_manager *man)
 396 {
 397         struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev);
 398         struct drm_device *dev = dev_priv->dev;
 399
 400         switch (type) {
 401         case TTM_PL_SYSTEM:
 402                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
 403                 man->available_caching = TTM_PL_MASK_CACHING;
 404                 man->default_caching = TTM_PL_FLAG_CACHED;
 405                 break;
 406         case TTM_PL_VRAM:
 407                 if (dev_priv->card_type >= NV_50) {
 408                         man->func = &nouveau_vram_manager;
 409                         man->io_reserve_fastpath = false;
 410                         man->use_io_reserve_lru = true;
 411                 } else {
 412                         man->func = &ttm_bo_manager_func;
 413                 }
 414                 man->flags = TTM_MEMTYPE_FLAG_FIXED |
 415                              TTM_MEMTYPE_FLAG_MAPPABLE;
 416                 man->available_caching = TTM_PL_FLAG_UNCACHED |
 417                                          TTM_PL_FLAG_WC;
 418                 man->default_caching = TTM_PL_FLAG_WC;
 419                 break;
 420         case TTM_PL_TT:
 421                 if (dev_priv->card_type >= NV_50)
 422                         man->func = &nouveau_gart_manager;
 423                 else
 424                         man->func = &ttm_bo_manager_func;
 425                 switch (dev_priv->gart_info.type) {
 426                 case NOUVEAU_GART_AGP:
 427                         man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
 428                         man->available_caching = TTM_PL_FLAG_UNCACHED |
 429                                 TTM_PL_FLAG_WC;
 430                         man->default_caching = TTM_PL_FLAG_WC;
 431                         break;
 432                 case NOUVEAU_GART_PDMA:
 433                 case NOUVEAU_GART_HW:
 434                         man->flags = TTM_MEMTYPE_FLAG_MAPPABLE |
 435                                      TTM_MEMTYPE_FLAG_CMA;
 436                         man->available_caching = TTM_PL_MASK_CACHING;
 437                         man->default_caching = TTM_PL_FLAG_CACHED;
 438                         man->gpu_offset = dev_priv->gart_info.aper_base;
 439                         break;
 440                 default:
 441                         NV_ERROR(dev, "Unknown GART type: %d\n",
 442                                  dev_priv->gart_info.type);
 443                         return -EINVAL;
 444                 }
 445                 break;
 446         default:
 447                 NV_ERROR(dev, "Unsupported memory type %u\n", (unsigned)type);
 448                 return -EINVAL;
 449         }
 450         return 0;
 451 }
 452
 453 static void
 454 nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl)
 455 {
 456         struct nouveau_bo *nvbo = nouveau_bo(bo);
 457
 458         switch (bo->mem.mem_type) {
 459         case TTM_PL_VRAM:
 460                 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT,
 461                                          TTM_PL_FLAG_SYSTEM);
 462                 break;
 463         default:
 464                 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_SYSTEM, 0);
 465                 break;
 466         }
 467
 468         *pl = nvbo->placement;
 469 }
 470
 471
 472 /* GPU-assisted copy using NV_MEMORY_TO_MEMORY_FORMAT, can access
 473  * TTM_PL_{VRAM,TT} directly.
 474  */
 475
 476 static int
 477 nouveau_bo_move_accel_cleanup(struct nouveau_channel *chan,
 478                               struct nouveau_bo *nvbo, bool evict,
 479                               bool no_wait_reserve, bool no_wait_gpu,
 480                               struct ttm_mem_reg *new_mem)
 481 {
 482         struct nouveau_fence *fence = NULL;
 483         int ret;
 484
 485         ret = nouveau_fence_new(chan, &fence, true);
 486         if (ret)
 487                 return ret;
 488
 489         ret = ttm_bo_move_accel_cleanup(&nvbo->bo, fence, NULL, evict,
 490                                         no_wait_reserve, no_wait_gpu, new_mem);
 491         nouveau_fence_unref(&fence);
 492         return ret;
 493 }
 494
 495 static int
 496 nvc0_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
 497                   struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
 498 {
 499         struct nouveau_mem *node = old_mem->mm_node;
 500         u64 src_offset = node->vma[0].offset;
 501         u64 dst_offset = node->vma[1].offset;
 502         u32 page_count = new_mem->num_pages;
 503         int ret;
 504
 505         page_count = new_mem->num_pages;
 506         while (page_count) {
 507                 int line_count = (page_count > 2047) ? 2047 : page_count;
 508
 509                 ret = RING_SPACE(chan, 12);
 510                 if (ret)
 511                         return ret;
 512
 513                 BEGIN_NVC0(chan, 2, NvSubM2MF, 0x0238, 2);
 514                 OUT_RING  (chan, upper_32_bits(dst_offset));
 515                 OUT_RING  (chan, lower_32_bits(dst_offset));
 516                 BEGIN_NVC0(chan, 2, NvSubM2MF, 0x030c, 6);
 517                 OUT_RING  (chan, upper_32_bits(src_offset));
 518                 OUT_RING  (chan, lower_32_bits(src_offset));
 519                 OUT_RING  (chan, PAGE_SIZE); /* src_pitch */
 520                 OUT_RING  (chan, PAGE_SIZE); /* dst_pitch */
 521                 OUT_RING  (chan, PAGE_SIZE); /* line_length */
 522                 OUT_RING  (chan, line_count);
 523                 BEGIN_NVC0(chan, 2, NvSubM2MF, 0x0300, 1);
 524                 OUT_RING  (chan, 0x00100110);
 525
 526                 page_count -= line_count;
 527                 src_offset += (PAGE_SIZE * line_count);
 528                 dst_offset += (PAGE_SIZE * line_count);
 529         }
 530
 531         return 0;
 532 }
 533
 534 static int
 535 nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
 536                   struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
 537 {
 538         struct nouveau_mem *node = old_mem->mm_node;
 539         struct nouveau_bo *nvbo = nouveau_bo(bo);
 540         u64 length = (new_mem->num_pages << PAGE_SHIFT);
 541         u64 src_offset = node->vma[0].offset;
 542         u64 dst_offset = node->vma[1].offset;
 543         int ret;
 544
 545         while (length) {
 546                 u32 amount, stride, height;
 547
 548                 amount  = min(length, (u64)(4 * 1024 * 1024));
 549                 stride  = 16 * 4;
 550                 height  = amount / stride;
 551
 552                 if (new_mem->mem_type == TTM_PL_VRAM &&
 553                     nouveau_bo_tile_layout(nvbo)) {
 554                         ret = RING_SPACE(chan, 8);
 555                         if (ret)
 556                                 return ret;
 557
 558                         BEGIN_RING(chan, NvSubM2MF, 0x0200, 7);
 559                         OUT_RING  (chan, 0);
 560                         OUT_RING  (chan, 0);
 561                         OUT_RING  (chan, stride);
 562                         OUT_RING  (chan, height);
 563                         OUT_RING  (chan, 1);
 564                         OUT_RING  (chan, 0);
 565                         OUT_RING  (chan, 0);
 566                 } else {
 567                         ret = RING_SPACE(chan, 2);
 568                         if (ret)
 569                                 return ret;
 570
 571                         BEGIN_RING(chan, NvSubM2MF, 0x0200, 1);
 572                         OUT_RING  (chan, 1);
 573                 }
 574                 if (old_mem->mem_type == TTM_PL_VRAM &&
 575                     nouveau_bo_tile_layout(nvbo)) {
 576                         ret = RING_SPACE(chan, 8);
 577                         if (ret)
 578                                 return ret;
 579
 580                         BEGIN_RING(chan, NvSubM2MF, 0x021c, 7);
 581                         OUT_RING  (chan, 0);
 582                         OUT_RING  (chan, 0);
 583                         OUT_RING  (chan, stride);
 584                         OUT_RING  (chan, height);
 585                         OUT_RING  (chan, 1);
 586                         OUT_RING  (chan, 0);
 587                         OUT_RING  (chan, 0);
 588                 } else {
 589                         ret = RING_SPACE(chan, 2);
 590                         if (ret)
 591                                 return ret;
 592
 593                         BEGIN_RING(chan, NvSubM2MF, 0x021c, 1);
 594                         OUT_RING  (chan, 1);
 595                 }
 596
 597                 ret = RING_SPACE(chan, 14);
 598                 if (ret)
 599                         return ret;
 600
 601                 BEGIN_RING(chan, NvSubM2MF, 0x0238, 2);
 602                 OUT_RING  (chan, upper_32_bits(src_offset));
 603                 OUT_RING  (chan, upper_32_bits(dst_offset));
 604                 BEGIN_RING(chan, NvSubM2MF, 0x030c, 8);
 605                 OUT_RING  (chan, lower_32_bits(src_offset));
 606                 OUT_RING  (chan, lower_32_bits(dst_offset));
 607                 OUT_RING  (chan, stride);
 608                 OUT_RING  (chan, stride);
 609                 OUT_RING  (chan, stride);
 610                 OUT_RING  (chan, height);
 611                 OUT_RING  (chan, 0x00000101);
 612                 OUT_RING  (chan, 0x00000000);
 613                 BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
 614                 OUT_RING  (chan, 0);
 615
 616                 length -= amount;
 617                 src_offset += amount;
 618                 dst_offset += amount;
 619         }
 620
 621         return 0;
 622 }
 623
 624 static inline uint32_t
 625 nouveau_bo_mem_ctxdma(struct ttm_buffer_object *bo,
 626                       struct nouveau_channel *chan, struct ttm_mem_reg *mem)
 627 {
 628         if (mem->mem_type == TTM_PL_TT)
 629                 return chan->gart_handle;
 630         return chan->vram_handle;
 631 }
 632
 633 static int
 634 nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
 635                   struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
 636 {
 637         u32 src_offset = old_mem->start << PAGE_SHIFT;
 638         u32 dst_offset = new_mem->start << PAGE_SHIFT;
 639         u32 page_count = new_mem->num_pages;
 640         int ret;
 641
 642         ret = RING_SPACE(chan, 3);
 643         if (ret)
 644                 return ret;
 645
 646         BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE, 2);
 647         OUT_RING  (chan, nouveau_bo_mem_ctxdma(bo, chan, old_mem));
 648         OUT_RING  (chan, nouveau_bo_mem_ctxdma(bo, chan, new_mem));
 649
 650         page_count = new_mem->num_pages;
 651         while (page_count) {
 652                 int line_count = (page_count > 2047) ? 2047 : page_count;
 653
 654                 ret = RING_SPACE(chan, 11);
 655                 if (ret)
 656                         return ret;
 657
 658                 BEGIN_RING(chan, NvSubM2MF,
 659                                  NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
 660                 OUT_RING  (chan, src_offset);
 661                 OUT_RING  (chan, dst_offset);
 662                 OUT_RING  (chan, PAGE_SIZE); /* src_pitch */
 663                 OUT_RING  (chan, PAGE_SIZE); /* dst_pitch */
 664                 OUT_RING  (chan, PAGE_SIZE); /* line_length */
 665                 OUT_RING  (chan, line_count);
 666                 OUT_RING  (chan, 0x00000101);
 667                 OUT_RING  (chan, 0x00000000);
 668                 BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
 669                 OUT_RING  (chan, 0);
 670
 671                 page_count -= line_count;
 672                 src_offset += (PAGE_SIZE * line_count);
 673                 dst_offset += (PAGE_SIZE * line_count);
 674         }
 675
 676         return 0;
 677 }
 678
 679 static int
 680 nouveau_vma_getmap(struct nouveau_channel *chan, struct nouveau_bo *nvbo,
 681                    struct ttm_mem_reg *mem, struct nouveau_vma *vma)
 682 {
 683         struct nouveau_mem *node = mem->mm_node;
 684         int ret;
 685
 686         ret = nouveau_vm_get(chan->vm, mem->num_pages << PAGE_SHIFT,
 687                              node->page_shift, NV_MEM_ACCESS_RO, vma);
 688         if (ret)
 689                 return ret;
 690
 691         if (mem->mem_type == TTM_PL_VRAM)
 692                 nouveau_vm_map(vma, node);
 693         else
 694                 nouveau_vm_map_sg(vma, 0, mem->num_pages << PAGE_SHIFT,
 695                                   node, node->pages);
 696
 697         return 0;
 698 }
 699
 700 static int
 701 nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr,
 702                      bool no_wait_reserve, bool no_wait_gpu,
 703                      struct ttm_mem_reg *new_mem)
 704 {
 705         struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
 706         struct nouveau_bo *nvbo = nouveau_bo(bo);
 707         struct ttm_mem_reg *old_mem = &bo->mem;
 708         struct nouveau_channel *chan;
 709         int ret;
 710
 711         chan = nvbo->channel;
 712         if (!chan) {
 713                 chan = dev_priv->channel;
 714                 mutex_lock_nested(&chan->mutex, NOUVEAU_KCHANNEL_MUTEX);
 715         }
 716
 717         /* create temporary vmas for the transfer and attach them to the
 718          * old nouveau_mem node, these will get cleaned up after ttm has
 719          * destroyed the ttm_mem_reg
 720          */
 721         if (dev_priv->card_type >= NV_50) {
 722                 struct nouveau_mem *node = old_mem->mm_node;
 723
 724                 ret = nouveau_vma_getmap(chan, nvbo, old_mem, &node->vma[0]);
 725                 if (ret)
 726                         goto out;
 727
 728                 ret = nouveau_vma_getmap(chan, nvbo, new_mem, &node->vma[1]);
 729                 if (ret)
 730                         goto out;
 731         }
 732
 733         if (dev_priv->card_type < NV_50)
 734                 ret = nv04_bo_move_m2mf(chan, bo, &bo->mem, new_mem);
 735         else
 736         if (dev_priv->card_type < NV_C0)
 737                 ret = nv50_bo_move_m2mf(chan, bo, &bo->mem, new_mem);
 738         else
 739                 ret = nvc0_bo_move_m2mf(chan, bo, &bo->mem, new_mem);
 740         if (ret == 0) {
 741                 ret = nouveau_bo_move_accel_cleanup(chan, nvbo, evict,
 742                                                     no_wait_reserve,
 743                                                     no_wait_gpu, new_mem);
 744         }
 745
 746 out:
 747         if (chan == dev_priv->channel)
 748                 mutex_unlock(&chan->mutex);
 749         return ret;
 750 }
 751
 752 static int
 753 nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr,
 754                       bool no_wait_reserve, bool no_wait_gpu,
 755                       struct ttm_mem_reg *new_mem)
 756 {
 757         u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
 758         struct ttm_placement placement;
 759         struct ttm_mem_reg tmp_mem;
 760         int ret;
 761
 762         placement.fpfn = placement.lpfn = 0;
 763         placement.num_placement = placement.num_busy_placement = 1;
 764         placement.placement = placement.busy_placement = &placement_memtype;
 765
 766         tmp_mem = *new_mem;
 767         tmp_mem.mm_node = NULL;
 768         ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_reserve, no_wait_gpu);
 769         if (ret)
 770                 return ret;
 771
 772         ret = ttm_tt_bind(bo->ttm, &tmp_mem);
 773         if (ret)
 774                 goto out;
 775
 776         ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_reserve, no_wait_gpu, &tmp_mem);
 777         if (ret)
 778                 goto out;
 779
 780         ret = ttm_bo_move_ttm(bo, true, no_wait_reserve, no_wait_gpu, new_mem);
 781 out:
 782         ttm_bo_mem_put(bo, &tmp_mem);
 783         return ret;
 784 }
 785
 786 static int
 787 nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr,
 788                       bool no_wait_reserve, bool no_wait_gpu,
 789                       struct ttm_mem_reg *new_mem)
 790 {
 791         u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
 792         struct ttm_placement placement;
 793         struct ttm_mem_reg tmp_mem;
 794         int ret;
 795
 796         placement.fpfn = placement.lpfn = 0;
 797         placement.num_placement = placement.num_busy_placement = 1;
 798         placement.placement = placement.busy_placement = &placement_memtype;
 799
 800         tmp_mem = *new_mem;
 801         tmp_mem.mm_node = NULL;
 802         ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_reserve, no_wait_gpu);
 803         if (ret)
 804                 return ret;
 805
 806         ret = ttm_bo_move_ttm(bo, true, no_wait_reserve, no_wait_gpu, &tmp_mem);
 807         if (ret)
 808                 goto out;
 809
 810         ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_reserve, no_wait_gpu, new_mem);
 811         if (ret)
 812                 goto out;
 813
 814 out:
 815         ttm_bo_mem_put(bo, &tmp_mem);
 816         return ret;
 817 }
 818
 819 static void
 820 nouveau_bo_move_ntfy(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem)
 821 {
 822         struct nouveau_mem *node = new_mem->mm_node;
 823         struct nouveau_bo *nvbo = nouveau_bo(bo);
 824         struct nouveau_vma *vma = &nvbo->vma;
 825
 826         if (!vma->vm)
 827                 return;
 828
 829         if (new_mem->mem_type == TTM_PL_VRAM) {
 830                 nouveau_vm_map(&nvbo->vma, new_mem->mm_node);
 831         } else
 832         if (new_mem->mem_type == TTM_PL_TT &&
 833             nvbo->page_shift == nvbo->vma.vm->spg_shift) {
 834                 nouveau_vm_map_sg(&nvbo->vma, 0, new_mem->
 835                                   num_pages << PAGE_SHIFT, node, node->pages);
 836         } else {
 837                 nouveau_vm_unmap(&nvbo->vma);
 838         }
 839 }
 840
 841 static int
 842 nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem,
 843                    struct nouveau_tile_reg **new_tile)
 844 {
 845         struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
 846         struct drm_device *dev = dev_priv->dev;
 847         struct nouveau_bo *nvbo = nouveau_bo(bo);
 848         u64 offset = new_mem->start << PAGE_SHIFT;
 849
 850         *new_tile = NULL;
 851         if (new_mem->mem_type != TTM_PL_VRAM)
 852                 return 0;
 853
 854         if (dev_priv->card_type >= NV_10) {
 855                 *new_tile = nv10_mem_set_tiling(dev, offset, new_mem->size,
 856                                                 nvbo->tile_mode,
 857                                                 nvbo->tile_flags);
 858         }
 859
 860         return 0;
 861 }
 862
 863 static void
 864 nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo,
 865                       struct nouveau_tile_reg *new_tile,
 866                       struct nouveau_tile_reg **old_tile)
 867 {
 868         struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
 869         struct drm_device *dev = dev_priv->dev;
 870
 871         nv10_mem_put_tile_region(dev, *old_tile, bo->sync_obj);
 872         *old_tile = new_tile;
 873 }
 874
 875 static int
 876 nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, bool intr,
 877                 bool no_wait_reserve, bool no_wait_gpu,
 878                 struct ttm_mem_reg *new_mem)
 879 {
 880         struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
 881         struct nouveau_bo *nvbo = nouveau_bo(bo);
 882         struct ttm_mem_reg *old_mem = &bo->mem;
 883         struct nouveau_tile_reg *new_tile = NULL;
 884         int ret = 0;
 885
 886         if (dev_priv->card_type < NV_50) {
 887                 ret = nouveau_bo_vm_bind(bo, new_mem, &new_tile);
 888                 if (ret)
 889                         return ret;
 890         }
 891
 892         /* Fake bo copy. */
 893         if (old_mem->mem_type == TTM_PL_SYSTEM && !bo->ttm) {
 894                 BUG_ON(bo->mem.mm_node != NULL);
 895                 bo->mem = *new_mem;
 896                 new_mem->mm_node = NULL;
 897                 goto out;
 898         }
 899
 900         /* Software copy if the card isn't up and running yet. */
 901         if (!dev_priv->channel) {
 902                 ret = ttm_bo_move_memcpy(bo, evict, no_wait_reserve, no_wait_gpu, new_mem);
 903                 goto out;
 904         }
 905
 906         /* Hardware assisted copy. */
 907         if (new_mem->mem_type == TTM_PL_SYSTEM)
 908                 ret = nouveau_bo_move_flipd(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem);
 909         else if (old_mem->mem_type == TTM_PL_SYSTEM)
 910                 ret = nouveau_bo_move_flips(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem);
 911         else
 912                 ret = nouveau_bo_move_m2mf(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem);
 913
 914         if (!ret)
 915                 goto out;
 916
 917         /* Fallback to software copy. */
 918         ret = ttm_bo_move_memcpy(bo, evict, no_wait_reserve, no_wait_gpu, new_mem);
 919
 920 out:
 921         if (dev_priv->card_type < NV_50) {
 922                 if (ret)
 923                         nouveau_bo_vm_cleanup(bo, NULL, &new_tile);
 924                 else
 925                         nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile);
 926         }
 927
 928         return ret;
 929 }
 930
 931 static int
 932 nouveau_bo_verify_access(struct ttm_buffer_object *bo, struct file *filp)
 933 {
 934         return 0;
 935 }
 936
 937 static int
 938 nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 939 {
 940         struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
 941         struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev);
 942         struct drm_device *dev = dev_priv->dev;
 943         int ret;
 944
 945         mem->bus.addr = NULL;
 946         mem->bus.offset = 0;
 947         mem->bus.size = mem->num_pages << PAGE_SHIFT;
 948         mem->bus.base = 0;
 949         mem->bus.is_iomem = false;
 950         if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
 951                 return -EINVAL;
 952         switch (mem->mem_type) {
 953         case TTM_PL_SYSTEM:
 954                 /* System memory */
 955                 return 0;
 956         case TTM_PL_TT:
 957 #if __OS_HAS_AGP
 958                 if (dev_priv->gart_info.type == NOUVEAU_GART_AGP) {
 959                         mem->bus.offset = mem->start << PAGE_SHIFT;
 960                         mem->bus.base = dev_priv->gart_info.aper_base;
 961                         mem->bus.is_iomem = true;
 962                 }
 963 #endif
 964                 break;
 965         case TTM_PL_VRAM:
 966         {
 967                 struct nouveau_mem *node = mem->mm_node;
 968                 u8 page_shift;
 969
 970                 if (!dev_priv->bar1_vm) {
 971                         mem->bus.offset = mem->start << PAGE_SHIFT;
 972                         mem->bus.base = pci_resource_start(dev->pdev, 1);
 973                         mem->bus.is_iomem = true;
 974                         break;
 975                 }
 976
 977                 if (dev_priv->card_type == NV_C0)
 978                         page_shift = node->page_shift;
 979                 else
 980                         page_shift = 12;
 981
 982                 ret = nouveau_vm_get(dev_priv->bar1_vm, mem->bus.size,
 983                                      page_shift, NV_MEM_ACCESS_RW,
 984                                      &node->bar_vma);
 985                 if (ret)
 986                         return ret;
 987
 988                 nouveau_vm_map(&node->bar_vma, node);
 989                 if (ret) {
 990                         nouveau_vm_put(&node->bar_vma);
 991                         return ret;
 992                 }
 993
 994                 mem->bus.offset = node->bar_vma.offset;
 995                 if (dev_priv->card_type == NV_50) /*XXX*/
 996                         mem->bus.offset -= 0x0020000000ULL;
 997                 mem->bus.base = pci_resource_start(dev->pdev, 1);
 998                 mem->bus.is_iomem = true;
 999         }
1000                 break;
1001         default:
1002                 return -EINVAL;
1003         }
1004         return 0;
1005 }
1006
1007 static void
1008 nouveau_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
1009 {
1010         struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev);
1011         struct nouveau_mem *node = mem->mm_node;
1012
1013         if (!dev_priv->bar1_vm || mem->mem_type != TTM_PL_VRAM)
1014                 return;
1015
1016         if (!node->bar_vma.node)
1017                 return;
1018
1019         nouveau_vm_unmap(&node->bar_vma);
1020         nouveau_vm_put(&node->bar_vma);
1021 }
1022
1023 static int
1024 nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo)
1025 {
1026         struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
1027         struct nouveau_bo *nvbo = nouveau_bo(bo);
1028
1029         /* as long as the bo isn't in vram, and isn't tiled, we've got
1030          * nothing to do here.
1031          */
1032         if (bo->mem.mem_type != TTM_PL_VRAM) {
1033                 if (dev_priv->card_type < NV_50 ||
1034                     !nouveau_bo_tile_layout(nvbo))
1035                         return 0;
1036         }
1037
1038         /* make sure bo is in mappable vram */
1039         if (bo->mem.start + bo->mem.num_pages < dev_priv->fb_mappable_pages)
1040                 return 0;
1041
1042
1043         nvbo->placement.fpfn = 0;
1044         nvbo->placement.lpfn = dev_priv->fb_mappable_pages;
1045         nouveau_bo_placement_set(nvbo, TTM_PL_VRAM, 0);
1046         return nouveau_bo_validate(nvbo, false, true, false);
1047 }
1048
1049 void
1050 nouveau_bo_fence(struct nouveau_bo *nvbo, struct nouveau_fence *fence)
1051 {
1052         struct nouveau_fence *old_fence;
1053
1054         if (likely(fence))
1055                 nouveau_fence_ref(fence);
1056
1057         spin_lock(&nvbo->bo.bdev->fence_lock);
1058         old_fence = nvbo->bo.sync_obj;
1059         nvbo->bo.sync_obj = fence;
1060         spin_unlock(&nvbo->bo.bdev->fence_lock);
1061
1062         nouveau_fence_unref(&old_fence);
1063 }
1064
1065 struct ttm_bo_driver nouveau_bo_driver = {
1066         .create_ttm_backend_entry = nouveau_bo_create_ttm_backend_entry,
1067         .invalidate_caches = nouveau_bo_invalidate_caches,
1068         .init_mem_type = nouveau_bo_init_mem_type,
1069         .evict_flags = nouveau_bo_evict_flags,
1070         .move_notify = nouveau_bo_move_ntfy,
1071         .move = nouveau_bo_move,
1072         .verify_access = nouveau_bo_verify_access,
1073         .sync_obj_signaled = __nouveau_fence_signalled,
1074         .sync_obj_wait = __nouveau_fence_wait,
1075         .sync_obj_flush = __nouveau_fence_flush,
1076         .sync_obj_unref = __nouveau_fence_unref,
1077         .sync_obj_ref = __nouveau_fence_ref,
1078         .fault_reserve_notify = &nouveau_ttm_fault_reserve_notify,
1079         .io_mem_reserve = &nouveau_ttm_io_mem_reserve,
1080         .io_mem_free = &nouveau_ttm_io_mem_free,
1081 };
1082