2 * Copyright 2005-2006 Erik Waling
3 * Copyright 2006 Stephane Marchesin
4 * Copyright 2007-2009 Stuart Bennett
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
20 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
21 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 #define NV_DEBUG_NOTRACE
27 #include "nouveau_drv.h"
28 #include "nouveau_hw.h"
29 #include "nouveau_encoder.h"
31 #include <linux/io-mapping.h>
32 #include <linux/firmware.h>
34 /* these defines are made up */
35 #define NV_CIO_CRE_44_HEADA 0x0
36 #define NV_CIO_CRE_44_HEADB 0x3
37 #define FEATURE_MOBILE 0x10 /* also FEATURE_QUADRO for BMP */
41 #define BIOSLOG(sip, fmt, arg...) NV_DEBUG(sip->dev, fmt, ##arg)
42 #define LOG_OLD_VALUE(x)
49 static bool nv_cksum(const uint8_t *data, unsigned int length)
52 * There's a few checksums in the BIOS, so here's a generic checking
58 for (i = 0; i < length; i++)
67 struct init_tbl_entry {
71 * > 0: success, length of opcode
72 * 0: success, but abort further parsing of table (INIT_DONE etc)
73 * < 0: failure, table parsing will be aborted
75 int (*handler)(struct nvbios *, uint16_t, struct init_exec *);
78 static int parse_init_table(struct nvbios *, uint16_t, struct init_exec *);
80 #define MACRO_INDEX_SIZE 2
82 #define CONDITION_SIZE 12
83 #define IO_FLAG_CONDITION_SIZE 9
84 #define IO_CONDITION_SIZE 5
85 #define MEM_INIT_SIZE 66
87 static void still_alive(void)
96 munge_reg(struct nvbios *bios, uint32_t reg)
98 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
99 struct dcb_entry *dcbent = bios->display.output;
101 if (dev_priv->card_type < NV_50)
104 if (reg & 0x80000000) {
105 BUG_ON(bios->display.crtc < 0);
106 reg += bios->display.crtc * 0x800;
109 if (reg & 0x40000000) {
112 reg += (ffs(dcbent->or) - 1) * 0x800;
113 if ((reg & 0x20000000) && !(dcbent->sorconf.link & 1))
122 valid_reg(struct nvbios *bios, uint32_t reg)
124 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
125 struct drm_device *dev = bios->dev;
127 /* C51 has misaligned regs on purpose. Marvellous */
129 (reg & 0x1 && dev_priv->vbios.chip_version != 0x51))
130 NV_ERROR(dev, "======= misaligned reg 0x%08X =======\n", reg);
132 /* warn on C51 regs that haven't been verified accessible in tracing */
133 if (reg & 0x1 && dev_priv->vbios.chip_version == 0x51 &&
134 reg != 0x130d && reg != 0x1311 && reg != 0x60081d)
135 NV_WARN(dev, "=== C51 misaligned reg 0x%08X not verified ===\n",
138 if (reg >= (8*1024*1024)) {
139 NV_ERROR(dev, "=== reg 0x%08x out of mapped bounds ===\n", reg);
147 valid_idx_port(struct nvbios *bios, uint16_t port)
149 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
150 struct drm_device *dev = bios->dev;
153 * If adding more ports here, the read/write functions below will need
154 * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is
155 * used for the port in question
157 if (dev_priv->card_type < NV_50) {
158 if (port == NV_CIO_CRX__COLOR)
160 if (port == NV_VIO_SRX)
163 if (port == NV_CIO_CRX__COLOR)
167 NV_ERROR(dev, "========== unknown indexed io port 0x%04X ==========\n",
174 valid_port(struct nvbios *bios, uint16_t port)
176 struct drm_device *dev = bios->dev;
179 * If adding more ports here, the read/write functions below will need
180 * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is
181 * used for the port in question
183 if (port == NV_VIO_VSE2)
186 NV_ERROR(dev, "========== unknown io port 0x%04X ==========\n", port);
192 bios_rd32(struct nvbios *bios, uint32_t reg)
196 reg = munge_reg(bios, reg);
197 if (!valid_reg(bios, reg))
201 * C51 sometimes uses regs with bit0 set in the address. For these
202 * cases there should exist a translation in a BIOS table to an IO
203 * port address which the BIOS uses for accessing the reg
205 * These only seem to appear for the power control regs to a flat panel,
206 * and the GPIO regs at 0x60081*. In C51 mmio traces the normal regs
207 * for 0x1308 and 0x1310 are used - hence the mask below. An S3
208 * suspend-resume mmio trace from a C51 will be required to see if this
209 * is true for the power microcode in 0x14.., or whether the direct IO
210 * port access method is needed
215 data = nv_rd32(bios->dev, reg);
217 BIOSLOG(bios, " Read: Reg: 0x%08X, Data: 0x%08X\n", reg, data);
223 bios_wr32(struct nvbios *bios, uint32_t reg, uint32_t data)
225 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
227 reg = munge_reg(bios, reg);
228 if (!valid_reg(bios, reg))
231 /* see note in bios_rd32 */
235 LOG_OLD_VALUE(bios_rd32(bios, reg));
236 BIOSLOG(bios, " Write: Reg: 0x%08X, Data: 0x%08X\n", reg, data);
238 if (dev_priv->vbios.execute) {
240 nv_wr32(bios->dev, reg, data);
245 bios_idxprt_rd(struct nvbios *bios, uint16_t port, uint8_t index)
247 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
248 struct drm_device *dev = bios->dev;
251 if (!valid_idx_port(bios, port))
254 if (dev_priv->card_type < NV_50) {
255 if (port == NV_VIO_SRX)
256 data = NVReadVgaSeq(dev, bios->state.crtchead, index);
257 else /* assume NV_CIO_CRX__COLOR */
258 data = NVReadVgaCrtc(dev, bios->state.crtchead, index);
262 data32 = bios_rd32(bios, NV50_PDISPLAY_VGACRTC(index & ~3));
263 data = (data32 >> ((index & 3) << 3)) & 0xff;
266 BIOSLOG(bios, " Indexed IO read: Port: 0x%04X, Index: 0x%02X, "
267 "Head: 0x%02X, Data: 0x%02X\n",
268 port, index, bios->state.crtchead, data);
273 bios_idxprt_wr(struct nvbios *bios, uint16_t port, uint8_t index, uint8_t data)
275 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
276 struct drm_device *dev = bios->dev;
278 if (!valid_idx_port(bios, port))
282 * The current head is maintained in the nvbios member state.crtchead.
283 * We trap changes to CR44 and update the head variable and hence the
284 * register set written.
285 * As CR44 only exists on CRTC0, we update crtchead to head0 in advance
286 * of the write, and to head1 after the write
288 if (port == NV_CIO_CRX__COLOR && index == NV_CIO_CRE_44 &&
289 data != NV_CIO_CRE_44_HEADB)
290 bios->state.crtchead = 0;
292 LOG_OLD_VALUE(bios_idxprt_rd(bios, port, index));
293 BIOSLOG(bios, " Indexed IO write: Port: 0x%04X, Index: 0x%02X, "
294 "Head: 0x%02X, Data: 0x%02X\n",
295 port, index, bios->state.crtchead, data);
297 if (bios->execute && dev_priv->card_type < NV_50) {
299 if (port == NV_VIO_SRX)
300 NVWriteVgaSeq(dev, bios->state.crtchead, index, data);
301 else /* assume NV_CIO_CRX__COLOR */
302 NVWriteVgaCrtc(dev, bios->state.crtchead, index, data);
305 uint32_t data32, shift = (index & 3) << 3;
309 data32 = bios_rd32(bios, NV50_PDISPLAY_VGACRTC(index & ~3));
310 data32 &= ~(0xff << shift);
311 data32 |= (data << shift);
312 bios_wr32(bios, NV50_PDISPLAY_VGACRTC(index & ~3), data32);
315 if (port == NV_CIO_CRX__COLOR &&
316 index == NV_CIO_CRE_44 && data == NV_CIO_CRE_44_HEADB)
317 bios->state.crtchead = 1;
321 bios_port_rd(struct nvbios *bios, uint16_t port)
323 uint8_t data, head = bios->state.crtchead;
325 if (!valid_port(bios, port))
328 data = NVReadPRMVIO(bios->dev, head, NV_PRMVIO0_OFFSET + port);
330 BIOSLOG(bios, " IO read: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n",
337 bios_port_wr(struct nvbios *bios, uint16_t port, uint8_t data)
339 int head = bios->state.crtchead;
341 if (!valid_port(bios, port))
344 LOG_OLD_VALUE(bios_port_rd(bios, port));
345 BIOSLOG(bios, " IO write: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n",
352 NVWritePRMVIO(bios->dev, head, NV_PRMVIO0_OFFSET + port, data);
356 io_flag_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond)
359 * The IO flag condition entry has 2 bytes for the CRTC port; 1 byte
360 * for the CRTC index; 1 byte for the mask to apply to the value
361 * retrieved from the CRTC; 1 byte for the shift right to apply to the
362 * masked CRTC value; 2 bytes for the offset to the flag array, to
363 * which the shifted value is added; 1 byte for the mask applied to the
364 * value read from the flag array; and 1 byte for the value to compare
365 * against the masked byte from the flag table.
368 uint16_t condptr = bios->io_flag_condition_tbl_ptr + cond * IO_FLAG_CONDITION_SIZE;
369 uint16_t crtcport = ROM16(bios->data[condptr]);
370 uint8_t crtcindex = bios->data[condptr + 2];
371 uint8_t mask = bios->data[condptr + 3];
372 uint8_t shift = bios->data[condptr + 4];
373 uint16_t flagarray = ROM16(bios->data[condptr + 5]);
374 uint8_t flagarraymask = bios->data[condptr + 7];
375 uint8_t cmpval = bios->data[condptr + 8];
378 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
379 "Shift: 0x%02X, FlagArray: 0x%04X, FAMask: 0x%02X, "
381 offset, crtcport, crtcindex, mask, shift, flagarray, flagarraymask, cmpval);
383 data = bios_idxprt_rd(bios, crtcport, crtcindex);
385 data = bios->data[flagarray + ((data & mask) >> shift)];
386 data &= flagarraymask;
388 BIOSLOG(bios, "0x%04X: Checking if 0x%02X equals 0x%02X\n",
389 offset, data, cmpval);
391 return (data == cmpval);
395 bios_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond)
398 * The condition table entry has 4 bytes for the address of the
399 * register to check, 4 bytes for a mask to apply to the register and
400 * 4 for a test comparison value
403 uint16_t condptr = bios->condition_tbl_ptr + cond * CONDITION_SIZE;
404 uint32_t reg = ROM32(bios->data[condptr]);
405 uint32_t mask = ROM32(bios->data[condptr + 4]);
406 uint32_t cmpval = ROM32(bios->data[condptr + 8]);
409 BIOSLOG(bios, "0x%04X: Cond: 0x%02X, Reg: 0x%08X, Mask: 0x%08X\n",
410 offset, cond, reg, mask);
412 data = bios_rd32(bios, reg) & mask;
414 BIOSLOG(bios, "0x%04X: Checking if 0x%08X equals 0x%08X\n",
415 offset, data, cmpval);
417 return (data == cmpval);
421 io_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond)
424 * The IO condition entry has 2 bytes for the IO port address; 1 byte
425 * for the index to write to io_port; 1 byte for the mask to apply to
426 * the byte read from io_port+1; and 1 byte for the value to compare
427 * against the masked byte.
430 uint16_t condptr = bios->io_condition_tbl_ptr + cond * IO_CONDITION_SIZE;
431 uint16_t io_port = ROM16(bios->data[condptr]);
432 uint8_t port_index = bios->data[condptr + 2];
433 uint8_t mask = bios->data[condptr + 3];
434 uint8_t cmpval = bios->data[condptr + 4];
436 uint8_t data = bios_idxprt_rd(bios, io_port, port_index) & mask;
438 BIOSLOG(bios, "0x%04X: Checking if 0x%02X equals 0x%02X\n",
439 offset, data, cmpval);
441 return (data == cmpval);
445 nv50_pll_set(struct drm_device *dev, uint32_t reg, uint32_t clk)
447 struct drm_nouveau_private *dev_priv = dev->dev_private;
448 struct nouveau_pll_vals pll;
449 struct pll_lims pll_limits;
450 u32 ctrl, mask, coef;
453 ret = get_pll_limits(dev, reg, &pll_limits);
457 clk = nouveau_calc_pll_mnp(dev, &pll_limits, clk, &pll);
461 coef = pll.N1 << 8 | pll.M1;
462 ctrl = pll.log2P << 16;
464 if (reg == 0x004008) {
466 ctrl |= (pll_limits.log2p_bias << 19);
467 ctrl |= (pll.log2P << 22);
470 if (!dev_priv->vbios.execute)
473 nv_mask(dev, reg + 0, mask, ctrl);
474 nv_wr32(dev, reg + 4, coef);
479 setPLL(struct nvbios *bios, uint32_t reg, uint32_t clk)
481 struct drm_device *dev = bios->dev;
482 struct drm_nouveau_private *dev_priv = dev->dev_private;
484 struct pll_lims pll_lim;
485 struct nouveau_pll_vals pllvals;
488 if (dev_priv->card_type >= NV_50)
489 return nv50_pll_set(dev, reg, clk);
491 /* high regs (such as in the mac g5 table) are not -= 4 */
492 ret = get_pll_limits(dev, reg > 0x405c ? reg : reg - 4, &pll_lim);
496 clk = nouveau_calc_pll_mnp(dev, &pll_lim, clk, &pllvals);
502 nouveau_hw_setpll(dev, reg, &pllvals);
508 static int dcb_entry_idx_from_crtchead(struct drm_device *dev)
510 struct drm_nouveau_private *dev_priv = dev->dev_private;
511 struct nvbios *bios = &dev_priv->vbios;
514 * For the results of this function to be correct, CR44 must have been
515 * set (using bios_idxprt_wr to set crtchead), CR58 set for CR57 = 0,
516 * and the DCB table parsed, before the script calling the function is
517 * run. run_digital_op_script is example of how to do such setup
520 uint8_t dcb_entry = NVReadVgaCrtc5758(dev, bios->state.crtchead, 0);
522 if (dcb_entry > bios->dcb.entries) {
523 NV_ERROR(dev, "CR58 doesn't have a valid DCB entry currently "
524 "(%02X)\n", dcb_entry);
525 dcb_entry = 0x7f; /* unused / invalid marker */
531 static struct nouveau_i2c_chan *
532 init_i2c_device_find(struct drm_device *dev, int i2c_index)
534 if (i2c_index == 0xff) {
535 struct drm_nouveau_private *dev_priv = dev->dev_private;
536 struct dcb_table *dcb = &dev_priv->vbios.dcb;
537 /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */
538 int idx = dcb_entry_idx_from_crtchead(dev);
540 i2c_index = NV_I2C_DEFAULT(0);
541 if (idx != 0x7f && dcb->entry[idx].i2c_upper_default)
542 i2c_index = NV_I2C_DEFAULT(1);
545 return nouveau_i2c_find(dev, i2c_index);
549 get_tmds_index_reg(struct drm_device *dev, uint8_t mlv)
552 * For mlv < 0x80, it is an index into a table of TMDS base addresses.
553 * For mlv == 0x80 use the "or" value of the dcb_entry indexed by
554 * CR58 for CR57 = 0 to index a table of offsets to the basic
556 * For mlv == 0x81 use the "or" value of the dcb_entry indexed by
557 * CR58 for CR57 = 0 to index a table of offsets to the basic
558 * 0x6808b0 address, and then flip the offset by 8.
561 struct drm_nouveau_private *dev_priv = dev->dev_private;
562 struct nvbios *bios = &dev_priv->vbios;
563 const int pramdac_offset[13] = {
564 0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000 };
565 const uint32_t pramdac_table[4] = {
566 0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8 };
569 int dcb_entry, dacoffset;
571 /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */
572 dcb_entry = dcb_entry_idx_from_crtchead(dev);
573 if (dcb_entry == 0x7f)
575 dacoffset = pramdac_offset[bios->dcb.entry[dcb_entry].or];
578 return 0x6808b0 + dacoffset;
580 if (mlv >= ARRAY_SIZE(pramdac_table)) {
581 NV_ERROR(dev, "Magic Lookup Value too big (%02X)\n",
585 return pramdac_table[mlv];
590 init_io_restrict_prog(struct nvbios *bios, uint16_t offset,
591 struct init_exec *iexec)
594 * INIT_IO_RESTRICT_PROG opcode: 0x32 ('2')
596 * offset (8 bit): opcode
597 * offset + 1 (16 bit): CRTC port
598 * offset + 3 (8 bit): CRTC index
599 * offset + 4 (8 bit): mask
600 * offset + 5 (8 bit): shift
601 * offset + 6 (8 bit): count
602 * offset + 7 (32 bit): register
603 * offset + 11 (32 bit): configuration 1
606 * Starting at offset + 11 there are "count" 32 bit values.
607 * To find out which value to use read index "CRTC index" on "CRTC
608 * port", AND this value with "mask" and then bit shift right "shift"
609 * bits. Read the appropriate value using this index and write to
613 uint16_t crtcport = ROM16(bios->data[offset + 1]);
614 uint8_t crtcindex = bios->data[offset + 3];
615 uint8_t mask = bios->data[offset + 4];
616 uint8_t shift = bios->data[offset + 5];
617 uint8_t count = bios->data[offset + 6];
618 uint32_t reg = ROM32(bios->data[offset + 7]);
621 int len = 11 + count * 4;
626 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
627 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
628 offset, crtcport, crtcindex, mask, shift, count, reg);
630 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift;
631 if (config > count) {
633 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
634 offset, config, count);
638 configval = ROM32(bios->data[offset + 11 + config * 4]);
640 BIOSLOG(bios, "0x%04X: Writing config %02X\n", offset, config);
642 bios_wr32(bios, reg, configval);
648 init_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
651 * INIT_REPEAT opcode: 0x33 ('3')
653 * offset (8 bit): opcode
654 * offset + 1 (8 bit): count
656 * Execute script following this opcode up to INIT_REPEAT_END
660 uint8_t count = bios->data[offset + 1];
663 /* no iexec->execute check by design */
665 BIOSLOG(bios, "0x%04X: Repeating following segment %d times\n",
668 iexec->repeat = true;
671 * count - 1, as the script block will execute once when we leave this
672 * opcode -- this is compatible with bios behaviour as:
673 * a) the block is always executed at least once, even if count == 0
674 * b) the bios interpreter skips to the op following INIT_END_REPEAT,
677 for (i = 0; i < count - 1; i++)
678 parse_init_table(bios, offset + 2, iexec);
680 iexec->repeat = false;
686 init_io_restrict_pll(struct nvbios *bios, uint16_t offset,
687 struct init_exec *iexec)
690 * INIT_IO_RESTRICT_PLL opcode: 0x34 ('4')
692 * offset (8 bit): opcode
693 * offset + 1 (16 bit): CRTC port
694 * offset + 3 (8 bit): CRTC index
695 * offset + 4 (8 bit): mask
696 * offset + 5 (8 bit): shift
697 * offset + 6 (8 bit): IO flag condition index
698 * offset + 7 (8 bit): count
699 * offset + 8 (32 bit): register
700 * offset + 12 (16 bit): frequency 1
703 * Starting at offset + 12 there are "count" 16 bit frequencies (10kHz).
704 * Set PLL register "register" to coefficients for frequency n,
705 * selected by reading index "CRTC index" of "CRTC port" ANDed with
706 * "mask" and shifted right by "shift".
708 * If "IO flag condition index" > 0, and condition met, double
709 * frequency before setting it.
712 uint16_t crtcport = ROM16(bios->data[offset + 1]);
713 uint8_t crtcindex = bios->data[offset + 3];
714 uint8_t mask = bios->data[offset + 4];
715 uint8_t shift = bios->data[offset + 5];
716 int8_t io_flag_condition_idx = bios->data[offset + 6];
717 uint8_t count = bios->data[offset + 7];
718 uint32_t reg = ROM32(bios->data[offset + 8]);
721 int len = 12 + count * 2;
726 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
727 "Shift: 0x%02X, IO Flag Condition: 0x%02X, "
728 "Count: 0x%02X, Reg: 0x%08X\n",
729 offset, crtcport, crtcindex, mask, shift,
730 io_flag_condition_idx, count, reg);
732 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift;
733 if (config > count) {
735 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
736 offset, config, count);
740 freq = ROM16(bios->data[offset + 12 + config * 2]);
742 if (io_flag_condition_idx > 0) {
743 if (io_flag_condition_met(bios, offset, io_flag_condition_idx)) {
744 BIOSLOG(bios, "0x%04X: Condition fulfilled -- "
745 "frequency doubled\n", offset);
748 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- "
749 "frequency unchanged\n", offset);
752 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %d0kHz\n",
753 offset, reg, config, freq);
755 setPLL(bios, reg, freq * 10);
761 init_end_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
764 * INIT_END_REPEAT opcode: 0x36 ('6')
766 * offset (8 bit): opcode
768 * Marks the end of the block for INIT_REPEAT to repeat
771 /* no iexec->execute check by design */
774 * iexec->repeat flag necessary to go past INIT_END_REPEAT opcode when
775 * we're not in repeat mode
784 init_copy(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
787 * INIT_COPY opcode: 0x37 ('7')
789 * offset (8 bit): opcode
790 * offset + 1 (32 bit): register
791 * offset + 5 (8 bit): shift
792 * offset + 6 (8 bit): srcmask
793 * offset + 7 (16 bit): CRTC port
794 * offset + 9 (8 bit): CRTC index
795 * offset + 10 (8 bit): mask
797 * Read index "CRTC index" on "CRTC port", AND with "mask", OR with
798 * (REGVAL("register") >> "shift" & "srcmask") and write-back to CRTC
802 uint32_t reg = ROM32(bios->data[offset + 1]);
803 uint8_t shift = bios->data[offset + 5];
804 uint8_t srcmask = bios->data[offset + 6];
805 uint16_t crtcport = ROM16(bios->data[offset + 7]);
806 uint8_t crtcindex = bios->data[offset + 9];
807 uint8_t mask = bios->data[offset + 10];
814 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%02X, "
815 "Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X\n",
816 offset, reg, shift, srcmask, crtcport, crtcindex, mask);
818 data = bios_rd32(bios, reg);
823 data <<= (0x100 - shift);
827 crtcdata = bios_idxprt_rd(bios, crtcport, crtcindex) & mask;
828 crtcdata |= (uint8_t)data;
829 bios_idxprt_wr(bios, crtcport, crtcindex, crtcdata);
835 init_not(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
838 * INIT_NOT opcode: 0x38 ('8')
840 * offset (8 bit): opcode
842 * Invert the current execute / no-execute condition (i.e. "else")
845 BIOSLOG(bios, "0x%04X: ------ Skipping following commands ------\n", offset);
847 BIOSLOG(bios, "0x%04X: ------ Executing following commands ------\n", offset);
849 iexec->execute = !iexec->execute;
854 init_io_flag_condition(struct nvbios *bios, uint16_t offset,
855 struct init_exec *iexec)
858 * INIT_IO_FLAG_CONDITION opcode: 0x39 ('9')
860 * offset (8 bit): opcode
861 * offset + 1 (8 bit): condition number
863 * Check condition "condition number" in the IO flag condition table.
864 * If condition not met skip subsequent opcodes until condition is
865 * inverted (INIT_NOT), or we hit INIT_RESUME
868 uint8_t cond = bios->data[offset + 1];
873 if (io_flag_condition_met(bios, offset, cond))
874 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
876 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
877 iexec->execute = false;
884 init_dp_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
887 * INIT_DP_CONDITION opcode: 0x3A ('')
889 * offset (8 bit): opcode
890 * offset + 1 (8 bit): "sub" opcode
891 * offset + 2 (8 bit): unknown
895 struct dcb_entry *dcb = bios->display.output;
896 struct drm_device *dev = bios->dev;
897 uint8_t cond = bios->data[offset + 1];
898 uint8_t *table, *entry;
900 BIOSLOG(bios, "0x%04X: subop 0x%02X\n", offset, cond);
905 table = nouveau_dp_bios_data(dev, dcb, &entry);
911 entry = dcb_conn(dev, dcb->connector);
912 if (!entry || entry[0] != DCB_CONNECTOR_eDP)
913 iexec->execute = false;
917 if ((table[0] < 0x40 && !(entry[5] & cond)) ||
918 (table[0] == 0x40 && !(entry[4] & cond)))
919 iexec->execute = false;
923 struct nouveau_i2c_chan *auxch;
926 auxch = nouveau_i2c_find(dev, bios->display.output->i2c_index);
928 NV_ERROR(dev, "0x%04X: couldn't get auxch\n", offset);
932 ret = nouveau_dp_auxch(auxch, 9, 0xd, &cond, 1);
934 NV_ERROR(dev, "0x%04X: auxch rd fail: %d\n", offset, ret);
939 iexec->execute = false;
943 NV_WARN(dev, "0x%04X: unknown INIT_3A op: %d\n", offset, cond);
948 BIOSLOG(bios, "0x%04X: continuing to execute\n", offset);
950 BIOSLOG(bios, "0x%04X: skipping following commands\n", offset);
956 init_op_3b(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
959 * INIT_3B opcode: 0x3B ('')
961 * offset (8 bit): opcode
962 * offset + 1 (8 bit): crtc index
966 uint8_t or = ffs(bios->display.output->or) - 1;
967 uint8_t index = bios->data[offset + 1];
973 data = bios_idxprt_rd(bios, 0x3d4, index);
974 bios_idxprt_wr(bios, 0x3d4, index, data & ~(1 << or));
979 init_op_3c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
982 * INIT_3C opcode: 0x3C ('')
984 * offset (8 bit): opcode
985 * offset + 1 (8 bit): crtc index
989 uint8_t or = ffs(bios->display.output->or) - 1;
990 uint8_t index = bios->data[offset + 1];
996 data = bios_idxprt_rd(bios, 0x3d4, index);
997 bios_idxprt_wr(bios, 0x3d4, index, data | (1 << or));
1002 init_idx_addr_latched(struct nvbios *bios, uint16_t offset,
1003 struct init_exec *iexec)
1006 * INIT_INDEX_ADDRESS_LATCHED opcode: 0x49 ('I')
1008 * offset (8 bit): opcode
1009 * offset + 1 (32 bit): control register
1010 * offset + 5 (32 bit): data register
1011 * offset + 9 (32 bit): mask
1012 * offset + 13 (32 bit): data
1013 * offset + 17 (8 bit): count
1014 * offset + 18 (8 bit): address 1
1015 * offset + 19 (8 bit): data 1
1018 * For each of "count" address and data pairs, write "data n" to
1019 * "data register", read the current value of "control register",
1020 * and write it back once ANDed with "mask", ORed with "data",
1021 * and ORed with "address n"
1024 uint32_t controlreg = ROM32(bios->data[offset + 1]);
1025 uint32_t datareg = ROM32(bios->data[offset + 5]);
1026 uint32_t mask = ROM32(bios->data[offset + 9]);
1027 uint32_t data = ROM32(bios->data[offset + 13]);
1028 uint8_t count = bios->data[offset + 17];
1029 int len = 18 + count * 2;
1033 if (!iexec->execute)
1036 BIOSLOG(bios, "0x%04X: ControlReg: 0x%08X, DataReg: 0x%08X, "
1037 "Mask: 0x%08X, Data: 0x%08X, Count: 0x%02X\n",
1038 offset, controlreg, datareg, mask, data, count);
1040 for (i = 0; i < count; i++) {
1041 uint8_t instaddress = bios->data[offset + 18 + i * 2];
1042 uint8_t instdata = bios->data[offset + 19 + i * 2];
1044 BIOSLOG(bios, "0x%04X: Address: 0x%02X, Data: 0x%02X\n",
1045 offset, instaddress, instdata);
1047 bios_wr32(bios, datareg, instdata);
1048 value = bios_rd32(bios, controlreg) & mask;
1050 value |= instaddress;
1051 bios_wr32(bios, controlreg, value);
1058 init_io_restrict_pll2(struct nvbios *bios, uint16_t offset,
1059 struct init_exec *iexec)
1062 * INIT_IO_RESTRICT_PLL2 opcode: 0x4A ('J')
1064 * offset (8 bit): opcode
1065 * offset + 1 (16 bit): CRTC port
1066 * offset + 3 (8 bit): CRTC index
1067 * offset + 4 (8 bit): mask
1068 * offset + 5 (8 bit): shift
1069 * offset + 6 (8 bit): count
1070 * offset + 7 (32 bit): register
1071 * offset + 11 (32 bit): frequency 1
1074 * Starting at offset + 11 there are "count" 32 bit frequencies (kHz).
1075 * Set PLL register "register" to coefficients for frequency n,
1076 * selected by reading index "CRTC index" of "CRTC port" ANDed with
1077 * "mask" and shifted right by "shift".
1080 uint16_t crtcport = ROM16(bios->data[offset + 1]);
1081 uint8_t crtcindex = bios->data[offset + 3];
1082 uint8_t mask = bios->data[offset + 4];
1083 uint8_t shift = bios->data[offset + 5];
1084 uint8_t count = bios->data[offset + 6];
1085 uint32_t reg = ROM32(bios->data[offset + 7]);
1086 int len = 11 + count * 4;
1090 if (!iexec->execute)
1093 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
1094 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
1095 offset, crtcport, crtcindex, mask, shift, count, reg);
1100 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift;
1101 if (config > count) {
1103 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
1104 offset, config, count);
1108 freq = ROM32(bios->data[offset + 11 + config * 4]);
1110 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %dkHz\n",
1111 offset, reg, config, freq);
1113 setPLL(bios, reg, freq);
1119 init_pll2(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1122 * INIT_PLL2 opcode: 0x4B ('K')
1124 * offset (8 bit): opcode
1125 * offset + 1 (32 bit): register
1126 * offset + 5 (32 bit): freq
1128 * Set PLL register "register" to coefficients for frequency "freq"
1131 uint32_t reg = ROM32(bios->data[offset + 1]);
1132 uint32_t freq = ROM32(bios->data[offset + 5]);
1134 if (!iexec->execute)
1137 BIOSLOG(bios, "0x%04X: Reg: 0x%04X, Freq: %dkHz\n",
1140 setPLL(bios, reg, freq);
1145 init_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1148 * INIT_I2C_BYTE opcode: 0x4C ('L')
1150 * offset (8 bit): opcode
1151 * offset + 1 (8 bit): DCB I2C table entry index
1152 * offset + 2 (8 bit): I2C slave address
1153 * offset + 3 (8 bit): count
1154 * offset + 4 (8 bit): I2C register 1
1155 * offset + 5 (8 bit): mask 1
1156 * offset + 6 (8 bit): data 1
1159 * For each of "count" registers given by "I2C register n" on the device
1160 * addressed by "I2C slave address" on the I2C bus given by
1161 * "DCB I2C table entry index", read the register, AND the result with
1162 * "mask n" and OR it with "data n" before writing it back to the device
1165 struct drm_device *dev = bios->dev;
1166 uint8_t i2c_index = bios->data[offset + 1];
1167 uint8_t i2c_address = bios->data[offset + 2] >> 1;
1168 uint8_t count = bios->data[offset + 3];
1169 struct nouveau_i2c_chan *chan;
1170 int len = 4 + count * 3;
1173 if (!iexec->execute)
1176 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1178 offset, i2c_index, i2c_address, count);
1180 chan = init_i2c_device_find(dev, i2c_index);
1182 NV_ERROR(dev, "0x%04X: i2c bus not found\n", offset);
1186 for (i = 0; i < count; i++) {
1187 uint8_t reg = bios->data[offset + 4 + i * 3];
1188 uint8_t mask = bios->data[offset + 5 + i * 3];
1189 uint8_t data = bios->data[offset + 6 + i * 3];
1190 union i2c_smbus_data val;
1192 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0,
1193 I2C_SMBUS_READ, reg,
1194 I2C_SMBUS_BYTE_DATA, &val);
1196 NV_ERROR(dev, "0x%04X: i2c rd fail: %d\n", offset, ret);
1200 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: 0x%02X, "
1201 "Mask: 0x%02X, Data: 0x%02X\n",
1202 offset, reg, val.byte, mask, data);
1209 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0,
1210 I2C_SMBUS_WRITE, reg,
1211 I2C_SMBUS_BYTE_DATA, &val);
1213 NV_ERROR(dev, "0x%04X: i2c wr fail: %d\n", offset, ret);
1222 init_zm_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1225 * INIT_ZM_I2C_BYTE opcode: 0x4D ('M')
1227 * offset (8 bit): opcode
1228 * offset + 1 (8 bit): DCB I2C table entry index
1229 * offset + 2 (8 bit): I2C slave address
1230 * offset + 3 (8 bit): count
1231 * offset + 4 (8 bit): I2C register 1
1232 * offset + 5 (8 bit): data 1
1235 * For each of "count" registers given by "I2C register n" on the device
1236 * addressed by "I2C slave address" on the I2C bus given by
1237 * "DCB I2C table entry index", set the register to "data n"
1240 struct drm_device *dev = bios->dev;
1241 uint8_t i2c_index = bios->data[offset + 1];
1242 uint8_t i2c_address = bios->data[offset + 2] >> 1;
1243 uint8_t count = bios->data[offset + 3];
1244 struct nouveau_i2c_chan *chan;
1245 int len = 4 + count * 2;
1248 if (!iexec->execute)
1251 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1253 offset, i2c_index, i2c_address, count);
1255 chan = init_i2c_device_find(dev, i2c_index);
1257 NV_ERROR(dev, "0x%04X: i2c bus not found\n", offset);
1261 for (i = 0; i < count; i++) {
1262 uint8_t reg = bios->data[offset + 4 + i * 2];
1263 union i2c_smbus_data val;
1265 val.byte = bios->data[offset + 5 + i * 2];
1267 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Data: 0x%02X\n",
1268 offset, reg, val.byte);
1273 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0,
1274 I2C_SMBUS_WRITE, reg,
1275 I2C_SMBUS_BYTE_DATA, &val);
1277 NV_ERROR(dev, "0x%04X: i2c wr fail: %d\n", offset, ret);
1286 init_zm_i2c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1289 * INIT_ZM_I2C opcode: 0x4E ('N')
1291 * offset (8 bit): opcode
1292 * offset + 1 (8 bit): DCB I2C table entry index
1293 * offset + 2 (8 bit): I2C slave address
1294 * offset + 3 (8 bit): count
1295 * offset + 4 (8 bit): data 1
1298 * Send "count" bytes ("data n") to the device addressed by "I2C slave
1299 * address" on the I2C bus given by "DCB I2C table entry index"
1302 struct drm_device *dev = bios->dev;
1303 uint8_t i2c_index = bios->data[offset + 1];
1304 uint8_t i2c_address = bios->data[offset + 2] >> 1;
1305 uint8_t count = bios->data[offset + 3];
1306 int len = 4 + count;
1307 struct nouveau_i2c_chan *chan;
1312 if (!iexec->execute)
1315 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1317 offset, i2c_index, i2c_address, count);
1319 chan = init_i2c_device_find(dev, i2c_index);
1321 NV_ERROR(dev, "0x%04X: i2c bus not found\n", offset);
1325 for (i = 0; i < count; i++) {
1326 data[i] = bios->data[offset + 4 + i];
1328 BIOSLOG(bios, "0x%04X: Data: 0x%02X\n", offset, data[i]);
1331 if (bios->execute) {
1332 msg.addr = i2c_address;
1336 ret = i2c_transfer(&chan->adapter, &msg, 1);
1338 NV_ERROR(dev, "0x%04X: i2c wr fail: %d\n", offset, ret);
1347 init_tmds(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1350 * INIT_TMDS opcode: 0x4F ('O') (non-canon name)
1352 * offset (8 bit): opcode
1353 * offset + 1 (8 bit): magic lookup value
1354 * offset + 2 (8 bit): TMDS address
1355 * offset + 3 (8 bit): mask
1356 * offset + 4 (8 bit): data
1358 * Read the data reg for TMDS address "TMDS address", AND it with mask
1359 * and OR it with data, then write it back
1360 * "magic lookup value" determines which TMDS base address register is
1361 * used -- see get_tmds_index_reg()
1364 struct drm_device *dev = bios->dev;
1365 uint8_t mlv = bios->data[offset + 1];
1366 uint32_t tmdsaddr = bios->data[offset + 2];
1367 uint8_t mask = bios->data[offset + 3];
1368 uint8_t data = bios->data[offset + 4];
1369 uint32_t reg, value;
1371 if (!iexec->execute)
1374 BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, TMDSAddr: 0x%02X, "
1375 "Mask: 0x%02X, Data: 0x%02X\n",
1376 offset, mlv, tmdsaddr, mask, data);
1378 reg = get_tmds_index_reg(bios->dev, mlv);
1380 NV_ERROR(dev, "0x%04X: no tmds_index_reg\n", offset);
1384 bios_wr32(bios, reg,
1385 tmdsaddr | NV_PRAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE);
1386 value = (bios_rd32(bios, reg + 4) & mask) | data;
1387 bios_wr32(bios, reg + 4, value);
1388 bios_wr32(bios, reg, tmdsaddr);
1394 init_zm_tmds_group(struct nvbios *bios, uint16_t offset,
1395 struct init_exec *iexec)
1398 * INIT_ZM_TMDS_GROUP opcode: 0x50 ('P') (non-canon name)
1400 * offset (8 bit): opcode
1401 * offset + 1 (8 bit): magic lookup value
1402 * offset + 2 (8 bit): count
1403 * offset + 3 (8 bit): addr 1
1404 * offset + 4 (8 bit): data 1
1407 * For each of "count" TMDS address and data pairs write "data n" to
1408 * "addr n". "magic lookup value" determines which TMDS base address
1409 * register is used -- see get_tmds_index_reg()
1412 struct drm_device *dev = bios->dev;
1413 uint8_t mlv = bios->data[offset + 1];
1414 uint8_t count = bios->data[offset + 2];
1415 int len = 3 + count * 2;
1419 if (!iexec->execute)
1422 BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, Count: 0x%02X\n",
1423 offset, mlv, count);
1425 reg = get_tmds_index_reg(bios->dev, mlv);
1427 NV_ERROR(dev, "0x%04X: no tmds_index_reg\n", offset);
1431 for (i = 0; i < count; i++) {
1432 uint8_t tmdsaddr = bios->data[offset + 3 + i * 2];
1433 uint8_t tmdsdata = bios->data[offset + 4 + i * 2];
1435 bios_wr32(bios, reg + 4, tmdsdata);
1436 bios_wr32(bios, reg, tmdsaddr);
1443 init_cr_idx_adr_latch(struct nvbios *bios, uint16_t offset,
1444 struct init_exec *iexec)
1447 * INIT_CR_INDEX_ADDRESS_LATCHED opcode: 0x51 ('Q')
1449 * offset (8 bit): opcode
1450 * offset + 1 (8 bit): CRTC index1
1451 * offset + 2 (8 bit): CRTC index2
1452 * offset + 3 (8 bit): baseaddr
1453 * offset + 4 (8 bit): count
1454 * offset + 5 (8 bit): data 1
1457 * For each of "count" address and data pairs, write "baseaddr + n" to
1458 * "CRTC index1" and "data n" to "CRTC index2"
1459 * Once complete, restore initial value read from "CRTC index1"
1461 uint8_t crtcindex1 = bios->data[offset + 1];
1462 uint8_t crtcindex2 = bios->data[offset + 2];
1463 uint8_t baseaddr = bios->data[offset + 3];
1464 uint8_t count = bios->data[offset + 4];
1465 int len = 5 + count;
1466 uint8_t oldaddr, data;
1469 if (!iexec->execute)
1472 BIOSLOG(bios, "0x%04X: Index1: 0x%02X, Index2: 0x%02X, "
1473 "BaseAddr: 0x%02X, Count: 0x%02X\n",
1474 offset, crtcindex1, crtcindex2, baseaddr, count);
1476 oldaddr = bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, crtcindex1);
1478 for (i = 0; i < count; i++) {
1479 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex1,
1481 data = bios->data[offset + 5 + i];
1482 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex2, data);
1485 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex1, oldaddr);
1491 init_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1494 * INIT_CR opcode: 0x52 ('R')
1496 * offset (8 bit): opcode
1497 * offset + 1 (8 bit): CRTC index
1498 * offset + 2 (8 bit): mask
1499 * offset + 3 (8 bit): data
1501 * Assign the value of at "CRTC index" ANDed with mask and ORed with
1502 * data back to "CRTC index"
1505 uint8_t crtcindex = bios->data[offset + 1];
1506 uint8_t mask = bios->data[offset + 2];
1507 uint8_t data = bios->data[offset + 3];
1510 if (!iexec->execute)
1513 BIOSLOG(bios, "0x%04X: Index: 0x%02X, Mask: 0x%02X, Data: 0x%02X\n",
1514 offset, crtcindex, mask, data);
1516 value = bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, crtcindex) & mask;
1518 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, value);
1524 init_zm_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1527 * INIT_ZM_CR opcode: 0x53 ('S')
1529 * offset (8 bit): opcode
1530 * offset + 1 (8 bit): CRTC index
1531 * offset + 2 (8 bit): value
1533 * Assign "value" to CRTC register with index "CRTC index".
1536 uint8_t crtcindex = ROM32(bios->data[offset + 1]);
1537 uint8_t data = bios->data[offset + 2];
1539 if (!iexec->execute)
1542 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, data);
1548 init_zm_cr_group(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1551 * INIT_ZM_CR_GROUP opcode: 0x54 ('T')
1553 * offset (8 bit): opcode
1554 * offset + 1 (8 bit): count
1555 * offset + 2 (8 bit): CRTC index 1
1556 * offset + 3 (8 bit): value 1
1559 * For "count", assign "value n" to CRTC register with index
1563 uint8_t count = bios->data[offset + 1];
1564 int len = 2 + count * 2;
1567 if (!iexec->execute)
1570 for (i = 0; i < count; i++)
1571 init_zm_cr(bios, offset + 2 + 2 * i - 1, iexec);
1577 init_condition_time(struct nvbios *bios, uint16_t offset,
1578 struct init_exec *iexec)
1581 * INIT_CONDITION_TIME opcode: 0x56 ('V')
1583 * offset (8 bit): opcode
1584 * offset + 1 (8 bit): condition number
1585 * offset + 2 (8 bit): retries / 50
1587 * Check condition "condition number" in the condition table.
1588 * Bios code then sleeps for 2ms if the condition is not met, and
1589 * repeats up to "retries" times, but on one C51 this has proved
1590 * insufficient. In mmiotraces the driver sleeps for 20ms, so we do
1591 * this, and bail after "retries" times, or 2s, whichever is less.
1592 * If still not met after retries, clear execution flag for this table.
1595 uint8_t cond = bios->data[offset + 1];
1596 uint16_t retries = bios->data[offset + 2] * 50;
1599 if (!iexec->execute)
1605 BIOSLOG(bios, "0x%04X: Condition: 0x%02X, Retries: 0x%02X\n",
1606 offset, cond, retries);
1608 if (!bios->execute) /* avoid 2s delays when "faking" execution */
1611 for (cnt = 0; cnt < retries; cnt++) {
1612 if (bios_condition_met(bios, offset, cond)) {
1613 BIOSLOG(bios, "0x%04X: Condition met, continuing\n",
1617 BIOSLOG(bios, "0x%04X: "
1618 "Condition not met, sleeping for 20ms\n",
1624 if (!bios_condition_met(bios, offset, cond)) {
1626 "0x%04X: Condition still not met after %dms, "
1627 "skipping following opcodes\n", offset, 20 * retries);
1628 iexec->execute = false;
1635 init_ltime(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1638 * INIT_LTIME opcode: 0x57 ('V')
1640 * offset (8 bit): opcode
1641 * offset + 1 (16 bit): time
1643 * Sleep for "time" milliseconds.
1646 unsigned time = ROM16(bios->data[offset + 1]);
1648 if (!iexec->execute)
1651 BIOSLOG(bios, "0x%04X: Sleeping for 0x%04X milliseconds\n",
1660 init_zm_reg_sequence(struct nvbios *bios, uint16_t offset,
1661 struct init_exec *iexec)
1664 * INIT_ZM_REG_SEQUENCE opcode: 0x58 ('X')
1666 * offset (8 bit): opcode
1667 * offset + 1 (32 bit): base register
1668 * offset + 5 (8 bit): count
1669 * offset + 6 (32 bit): value 1
1672 * Starting at offset + 6 there are "count" 32 bit values.
1673 * For "count" iterations set "base register" + 4 * current_iteration
1674 * to "value current_iteration"
1677 uint32_t basereg = ROM32(bios->data[offset + 1]);
1678 uint32_t count = bios->data[offset + 5];
1679 int len = 6 + count * 4;
1682 if (!iexec->execute)
1685 BIOSLOG(bios, "0x%04X: BaseReg: 0x%08X, Count: 0x%02X\n",
1686 offset, basereg, count);
1688 for (i = 0; i < count; i++) {
1689 uint32_t reg = basereg + i * 4;
1690 uint32_t data = ROM32(bios->data[offset + 6 + i * 4]);
1692 bios_wr32(bios, reg, data);
1699 init_sub_direct(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1702 * INIT_SUB_DIRECT opcode: 0x5B ('[')
1704 * offset (8 bit): opcode
1705 * offset + 1 (16 bit): subroutine offset (in bios)
1707 * Calls a subroutine that will execute commands until INIT_DONE
1711 uint16_t sub_offset = ROM16(bios->data[offset + 1]);
1713 if (!iexec->execute)
1716 BIOSLOG(bios, "0x%04X: Executing subroutine at 0x%04X\n",
1717 offset, sub_offset);
1719 parse_init_table(bios, sub_offset, iexec);
1721 BIOSLOG(bios, "0x%04X: End of 0x%04X subroutine\n", offset, sub_offset);
1727 init_jump(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1730 * INIT_JUMP opcode: 0x5C ('\')
1732 * offset (8 bit): opcode
1733 * offset + 1 (16 bit): offset (in bios)
1735 * Continue execution of init table from 'offset'
1738 uint16_t jmp_offset = ROM16(bios->data[offset + 1]);
1740 if (!iexec->execute)
1743 BIOSLOG(bios, "0x%04X: Jump to 0x%04X\n", offset, jmp_offset);
1744 return jmp_offset - offset;
1748 init_i2c_if(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1751 * INIT_I2C_IF opcode: 0x5E ('^')
1753 * offset (8 bit): opcode
1754 * offset + 1 (8 bit): DCB I2C table entry index
1755 * offset + 2 (8 bit): I2C slave address
1756 * offset + 3 (8 bit): I2C register
1757 * offset + 4 (8 bit): mask
1758 * offset + 5 (8 bit): data
1760 * Read the register given by "I2C register" on the device addressed
1761 * by "I2C slave address" on the I2C bus given by "DCB I2C table
1762 * entry index". Compare the result AND "mask" to "data".
1763 * If they're not equal, skip subsequent opcodes until condition is
1764 * inverted (INIT_NOT), or we hit INIT_RESUME
1767 uint8_t i2c_index = bios->data[offset + 1];
1768 uint8_t i2c_address = bios->data[offset + 2] >> 1;
1769 uint8_t reg = bios->data[offset + 3];
1770 uint8_t mask = bios->data[offset + 4];
1771 uint8_t data = bios->data[offset + 5];
1772 struct nouveau_i2c_chan *chan;
1773 union i2c_smbus_data val;
1776 /* no execute check by design */
1778 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X\n",
1779 offset, i2c_index, i2c_address);
1781 chan = init_i2c_device_find(bios->dev, i2c_index);
1785 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0,
1786 I2C_SMBUS_READ, reg,
1787 I2C_SMBUS_BYTE_DATA, &val);
1789 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: [no device], "
1790 "Mask: 0x%02X, Data: 0x%02X\n",
1791 offset, reg, mask, data);
1796 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: 0x%02X, "
1797 "Mask: 0x%02X, Data: 0x%02X\n",
1798 offset, reg, val.byte, mask, data);
1800 iexec->execute = ((val.byte & mask) == data);
1806 init_copy_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1809 * INIT_COPY_NV_REG opcode: 0x5F ('_')
1811 * offset (8 bit): opcode
1812 * offset + 1 (32 bit): src reg
1813 * offset + 5 (8 bit): shift
1814 * offset + 6 (32 bit): src mask
1815 * offset + 10 (32 bit): xor
1816 * offset + 14 (32 bit): dst reg
1817 * offset + 18 (32 bit): dst mask
1819 * Shift REGVAL("src reg") right by (signed) "shift", AND result with
1820 * "src mask", then XOR with "xor". Write this OR'd with
1821 * (REGVAL("dst reg") AND'd with "dst mask") to "dst reg"
1824 uint32_t srcreg = *((uint32_t *)(&bios->data[offset + 1]));
1825 uint8_t shift = bios->data[offset + 5];
1826 uint32_t srcmask = *((uint32_t *)(&bios->data[offset + 6]));
1827 uint32_t xor = *((uint32_t *)(&bios->data[offset + 10]));
1828 uint32_t dstreg = *((uint32_t *)(&bios->data[offset + 14]));
1829 uint32_t dstmask = *((uint32_t *)(&bios->data[offset + 18]));
1830 uint32_t srcvalue, dstvalue;
1832 if (!iexec->execute)
1835 BIOSLOG(bios, "0x%04X: SrcReg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%08X, "
1836 "Xor: 0x%08X, DstReg: 0x%08X, DstMask: 0x%08X\n",
1837 offset, srcreg, shift, srcmask, xor, dstreg, dstmask);
1839 srcvalue = bios_rd32(bios, srcreg);
1844 srcvalue <<= (0x100 - shift);
1846 srcvalue = (srcvalue & srcmask) ^ xor;
1848 dstvalue = bios_rd32(bios, dstreg) & dstmask;
1850 bios_wr32(bios, dstreg, dstvalue | srcvalue);
1856 init_zm_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1859 * INIT_ZM_INDEX_IO opcode: 0x62 ('b')
1861 * offset (8 bit): opcode
1862 * offset + 1 (16 bit): CRTC port
1863 * offset + 3 (8 bit): CRTC index
1864 * offset + 4 (8 bit): data
1866 * Write "data" to index "CRTC index" of "CRTC port"
1868 uint16_t crtcport = ROM16(bios->data[offset + 1]);
1869 uint8_t crtcindex = bios->data[offset + 3];
1870 uint8_t data = bios->data[offset + 4];
1872 if (!iexec->execute)
1875 bios_idxprt_wr(bios, crtcport, crtcindex, data);
1881 bios_md32(struct nvbios *bios, uint32_t reg,
1882 uint32_t mask, uint32_t val)
1884 bios_wr32(bios, reg, (bios_rd32(bios, reg) & ~mask) | val);
1888 peek_fb(struct drm_device *dev, struct io_mapping *fb,
1893 if (off < pci_resource_len(dev->pdev, 1)) {
1894 uint8_t __iomem *p =
1895 io_mapping_map_atomic_wc(fb, off & PAGE_MASK);
1897 val = ioread32(p + (off & ~PAGE_MASK));
1899 io_mapping_unmap_atomic(p);
1906 poke_fb(struct drm_device *dev, struct io_mapping *fb,
1907 uint32_t off, uint32_t val)
1909 if (off < pci_resource_len(dev->pdev, 1)) {
1910 uint8_t __iomem *p =
1911 io_mapping_map_atomic_wc(fb, off & PAGE_MASK);
1913 iowrite32(val, p + (off & ~PAGE_MASK));
1916 io_mapping_unmap_atomic(p);
1921 read_back_fb(struct drm_device *dev, struct io_mapping *fb,
1922 uint32_t off, uint32_t val)
1924 poke_fb(dev, fb, off, val);
1925 return val == peek_fb(dev, fb, off);
1929 nv04_init_compute_mem(struct nvbios *bios)
1931 struct drm_device *dev = bios->dev;
1932 uint32_t patt = 0xdeadbeef;
1933 struct io_mapping *fb;
1936 /* Map the framebuffer aperture */
1937 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1),
1938 pci_resource_len(dev->pdev, 1));
1942 /* Sequencer and refresh off */
1943 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) | 0x20);
1944 bios_md32(bios, NV04_PFB_DEBUG_0, 0, NV04_PFB_DEBUG_0_REFRESH_OFF);
1946 bios_md32(bios, NV04_PFB_BOOT_0, ~0,
1947 NV04_PFB_BOOT_0_RAM_AMOUNT_16MB |
1948 NV04_PFB_BOOT_0_RAM_WIDTH_128 |
1949 NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT);
1951 for (i = 0; i < 4; i++)
1952 poke_fb(dev, fb, 4 * i, patt);
1954 poke_fb(dev, fb, 0x400000, patt + 1);
1956 if (peek_fb(dev, fb, 0) == patt + 1) {
1957 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_TYPE,
1958 NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_16MBIT);
1959 bios_md32(bios, NV04_PFB_DEBUG_0,
1960 NV04_PFB_DEBUG_0_REFRESH_OFF, 0);
1962 for (i = 0; i < 4; i++)
1963 poke_fb(dev, fb, 4 * i, patt);
1965 if ((peek_fb(dev, fb, 0xc) & 0xffff) != (patt & 0xffff))
1966 bios_md32(bios, NV04_PFB_BOOT_0,
1967 NV04_PFB_BOOT_0_RAM_WIDTH_128 |
1968 NV04_PFB_BOOT_0_RAM_AMOUNT,
1969 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
1971 } else if ((peek_fb(dev, fb, 0xc) & 0xffff0000) !=
1972 (patt & 0xffff0000)) {
1973 bios_md32(bios, NV04_PFB_BOOT_0,
1974 NV04_PFB_BOOT_0_RAM_WIDTH_128 |
1975 NV04_PFB_BOOT_0_RAM_AMOUNT,
1976 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB);
1978 } else if (peek_fb(dev, fb, 0) != patt) {
1979 if (read_back_fb(dev, fb, 0x800000, patt))
1980 bios_md32(bios, NV04_PFB_BOOT_0,
1981 NV04_PFB_BOOT_0_RAM_AMOUNT,
1982 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
1984 bios_md32(bios, NV04_PFB_BOOT_0,
1985 NV04_PFB_BOOT_0_RAM_AMOUNT,
1986 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB);
1988 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_TYPE,
1989 NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_8MBIT);
1991 } else if (!read_back_fb(dev, fb, 0x800000, patt)) {
1992 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
1993 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
1997 /* Refresh on, sequencer on */
1998 bios_md32(bios, NV04_PFB_DEBUG_0, NV04_PFB_DEBUG_0_REFRESH_OFF, 0);
1999 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) & ~0x20);
2001 io_mapping_free(fb);
2005 static const uint8_t *
2006 nv05_memory_config(struct nvbios *bios)
2008 /* Defaults for BIOSes lacking a memory config table */
2009 static const uint8_t default_config_tab[][2] = {
2019 int i = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) &
2020 NV_PEXTDEV_BOOT_0_RAMCFG) >> 2;
2022 if (bios->legacy.mem_init_tbl_ptr)
2023 return &bios->data[bios->legacy.mem_init_tbl_ptr + 2 * i];
2025 return default_config_tab[i];
2029 nv05_init_compute_mem(struct nvbios *bios)
2031 struct drm_device *dev = bios->dev;
2032 const uint8_t *ramcfg = nv05_memory_config(bios);
2033 uint32_t patt = 0xdeadbeef;
2034 struct io_mapping *fb;
2037 /* Map the framebuffer aperture */
2038 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1),
2039 pci_resource_len(dev->pdev, 1));
2044 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) | 0x20);
2046 if (bios_rd32(bios, NV04_PFB_BOOT_0) & NV04_PFB_BOOT_0_UMA_ENABLE)
2049 bios_md32(bios, NV04_PFB_DEBUG_0, NV04_PFB_DEBUG_0_REFRESH_OFF, 0);
2051 /* If present load the hardcoded scrambling table */
2052 if (bios->legacy.mem_init_tbl_ptr) {
2053 uint32_t *scramble_tab = (uint32_t *)&bios->data[
2054 bios->legacy.mem_init_tbl_ptr + 0x10];
2056 for (i = 0; i < 8; i++)
2057 bios_wr32(bios, NV04_PFB_SCRAMBLE(i),
2058 ROM32(scramble_tab[i]));
2061 /* Set memory type/width/length defaults depending on the straps */
2062 bios_md32(bios, NV04_PFB_BOOT_0, 0x3f, ramcfg[0]);
2064 if (ramcfg[1] & 0x80)
2065 bios_md32(bios, NV04_PFB_CFG0, 0, NV04_PFB_CFG0_SCRAMBLE);
2067 bios_md32(bios, NV04_PFB_CFG1, 0x700001, (ramcfg[1] & 1) << 20);
2068 bios_md32(bios, NV04_PFB_CFG1, 0, 1);
2070 /* Probe memory bus width */
2071 for (i = 0; i < 4; i++)
2072 poke_fb(dev, fb, 4 * i, patt);
2074 if (peek_fb(dev, fb, 0xc) != patt)
2075 bios_md32(bios, NV04_PFB_BOOT_0,
2076 NV04_PFB_BOOT_0_RAM_WIDTH_128, 0);
2078 /* Probe memory length */
2079 v = bios_rd32(bios, NV04_PFB_BOOT_0) & NV04_PFB_BOOT_0_RAM_AMOUNT;
2081 if (v == NV04_PFB_BOOT_0_RAM_AMOUNT_32MB &&
2082 (!read_back_fb(dev, fb, 0x1000000, ++patt) ||
2083 !read_back_fb(dev, fb, 0, ++patt)))
2084 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
2085 NV04_PFB_BOOT_0_RAM_AMOUNT_16MB);
2087 if (v == NV04_PFB_BOOT_0_RAM_AMOUNT_16MB &&
2088 !read_back_fb(dev, fb, 0x800000, ++patt))
2089 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
2090 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
2092 if (!read_back_fb(dev, fb, 0x400000, ++patt))
2093 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
2094 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB);
2098 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) & ~0x20);
2100 io_mapping_free(fb);
2105 nv10_init_compute_mem(struct nvbios *bios)
2107 struct drm_device *dev = bios->dev;
2108 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
2109 const int mem_width[] = { 0x10, 0x00, 0x20 };
2110 const int mem_width_count = (dev_priv->chipset >= 0x17 ? 3 : 2);
2111 uint32_t patt = 0xdeadbeef;
2112 struct io_mapping *fb;
2115 /* Map the framebuffer aperture */
2116 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1),
2117 pci_resource_len(dev->pdev, 1));
2121 bios_wr32(bios, NV10_PFB_REFCTRL, NV10_PFB_REFCTRL_VALID_1);
2123 /* Probe memory bus width */
2124 for (i = 0; i < mem_width_count; i++) {
2125 bios_md32(bios, NV04_PFB_CFG0, 0x30, mem_width[i]);
2127 for (j = 0; j < 4; j++) {
2128 for (k = 0; k < 4; k++)
2129 poke_fb(dev, fb, 0x1c, 0);
2131 poke_fb(dev, fb, 0x1c, patt);
2132 poke_fb(dev, fb, 0x3c, 0);
2134 if (peek_fb(dev, fb, 0x1c) == patt)
2135 goto mem_width_found;
2142 /* Probe amount of installed memory */
2143 for (i = 0; i < 4; i++) {
2144 int off = bios_rd32(bios, NV04_PFB_FIFO_DATA) - 0x100000;
2146 poke_fb(dev, fb, off, patt);
2147 poke_fb(dev, fb, 0, 0);
2149 peek_fb(dev, fb, 0);
2150 peek_fb(dev, fb, 0);
2151 peek_fb(dev, fb, 0);
2152 peek_fb(dev, fb, 0);
2154 if (peek_fb(dev, fb, off) == patt)
2158 /* IC missing - disable the upper half memory space. */
2159 bios_md32(bios, NV04_PFB_CFG0, 0x1000, 0);
2162 io_mapping_free(fb);
2167 nv20_init_compute_mem(struct nvbios *bios)
2169 struct drm_device *dev = bios->dev;
2170 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
2171 uint32_t mask = (dev_priv->chipset >= 0x25 ? 0x300 : 0x900);
2172 uint32_t amount, off;
2173 struct io_mapping *fb;
2175 /* Map the framebuffer aperture */
2176 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1),
2177 pci_resource_len(dev->pdev, 1));
2181 bios_wr32(bios, NV10_PFB_REFCTRL, NV10_PFB_REFCTRL_VALID_1);
2183 /* Allow full addressing */
2184 bios_md32(bios, NV04_PFB_CFG0, 0, mask);
2186 amount = bios_rd32(bios, NV04_PFB_FIFO_DATA);
2187 for (off = amount; off > 0x2000000; off -= 0x2000000)
2188 poke_fb(dev, fb, off - 4, off);
2190 amount = bios_rd32(bios, NV04_PFB_FIFO_DATA);
2191 if (amount != peek_fb(dev, fb, amount - 4))
2192 /* IC missing - disable the upper half memory space. */
2193 bios_md32(bios, NV04_PFB_CFG0, mask, 0);
2195 io_mapping_free(fb);
2200 init_compute_mem(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2203 * INIT_COMPUTE_MEM opcode: 0x63 ('c')
2205 * offset (8 bit): opcode
2207 * This opcode is meant to set the PFB memory config registers
2208 * appropriately so that we can correctly calculate how much VRAM it
2209 * has (on nv10 and better chipsets the amount of installed VRAM is
2210 * subsequently reported in NV_PFB_CSTATUS (0x10020C)).
2212 * The implementation of this opcode in general consists of several
2215 * 1) Determination of memory type and density. Only necessary for
2216 * really old chipsets, the memory type reported by the strap bits
2217 * (0x101000) is assumed to be accurate on nv05 and newer.
2219 * 2) Determination of the memory bus width. Usually done by a cunning
2220 * combination of writes to offsets 0x1c and 0x3c in the fb, and
2221 * seeing whether the written values are read back correctly.
2223 * Only necessary on nv0x-nv1x and nv34, on the other cards we can
2226 * 3) Determination of how many of the card's RAM pads have ICs
2227 * attached, usually done by a cunning combination of writes to an
2228 * offset slightly less than the maximum memory reported by
2229 * NV_PFB_CSTATUS, then seeing if the test pattern can be read back.
2231 * This appears to be a NOP on IGPs and NV4x or newer chipsets, both io
2232 * logs of the VBIOS and kmmio traces of the binary driver POSTing the
2233 * card show nothing being done for this opcode. Why is it still listed
2237 /* no iexec->execute check by design */
2239 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
2242 if (dev_priv->chipset >= 0x40 ||
2243 dev_priv->chipset == 0x1a ||
2244 dev_priv->chipset == 0x1f)
2246 else if (dev_priv->chipset >= 0x20 &&
2247 dev_priv->chipset != 0x34)
2248 ret = nv20_init_compute_mem(bios);
2249 else if (dev_priv->chipset >= 0x10)
2250 ret = nv10_init_compute_mem(bios);
2251 else if (dev_priv->chipset >= 0x5)
2252 ret = nv05_init_compute_mem(bios);
2254 ret = nv04_init_compute_mem(bios);
2263 init_reset(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2266 * INIT_RESET opcode: 0x65 ('e')
2268 * offset (8 bit): opcode
2269 * offset + 1 (32 bit): register
2270 * offset + 5 (32 bit): value1
2271 * offset + 9 (32 bit): value2
2273 * Assign "value1" to "register", then assign "value2" to "register"
2276 uint32_t reg = ROM32(bios->data[offset + 1]);
2277 uint32_t value1 = ROM32(bios->data[offset + 5]);
2278 uint32_t value2 = ROM32(bios->data[offset + 9]);
2279 uint32_t pci_nv_19, pci_nv_20;
2281 /* no iexec->execute check by design */
2283 pci_nv_19 = bios_rd32(bios, NV_PBUS_PCI_NV_19);
2284 bios_wr32(bios, NV_PBUS_PCI_NV_19, pci_nv_19 & ~0xf00);
2286 bios_wr32(bios, reg, value1);
2290 bios_wr32(bios, reg, value2);
2291 bios_wr32(bios, NV_PBUS_PCI_NV_19, pci_nv_19);
2293 pci_nv_20 = bios_rd32(bios, NV_PBUS_PCI_NV_20);
2294 pci_nv_20 &= ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED; /* 0xfffffffe */
2295 bios_wr32(bios, NV_PBUS_PCI_NV_20, pci_nv_20);
2301 init_configure_mem(struct nvbios *bios, uint16_t offset,
2302 struct init_exec *iexec)
2305 * INIT_CONFIGURE_MEM opcode: 0x66 ('f')
2307 * offset (8 bit): opcode
2309 * Equivalent to INIT_DONE on bios version 3 or greater.
2310 * For early bios versions, sets up the memory registers, using values
2311 * taken from the memory init table
2314 /* no iexec->execute check by design */
2316 uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_SCRATCH4__INDEX) >> 4);
2317 uint16_t seqtbloffs = bios->legacy.sdr_seq_tbl_ptr, meminitdata = meminitoffs + 6;
2320 if (bios->major_version > 2)
2323 bios_idxprt_wr(bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX, bios_idxprt_rd(
2324 bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX) | 0x20);
2326 if (bios->data[meminitoffs] & 1)
2327 seqtbloffs = bios->legacy.ddr_seq_tbl_ptr;
2329 for (reg = ROM32(bios->data[seqtbloffs]);
2331 reg = ROM32(bios->data[seqtbloffs += 4])) {
2335 data = NV04_PFB_PRE_CMD_PRECHARGE;
2338 data = NV04_PFB_PAD_CKE_NORMAL;
2341 data = NV04_PFB_REF_CMD_REFRESH;
2344 data = ROM32(bios->data[meminitdata]);
2346 if (data == 0xffffffff)
2350 bios_wr32(bios, reg, data);
2357 init_configure_clk(struct nvbios *bios, uint16_t offset,
2358 struct init_exec *iexec)
2361 * INIT_CONFIGURE_CLK opcode: 0x67 ('g')
2363 * offset (8 bit): opcode
2365 * Equivalent to INIT_DONE on bios version 3 or greater.
2366 * For early bios versions, sets up the NVClk and MClk PLLs, using
2367 * values taken from the memory init table
2370 /* no iexec->execute check by design */
2372 uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_SCRATCH4__INDEX) >> 4);
2375 if (bios->major_version > 2)
2378 clock = ROM16(bios->data[meminitoffs + 4]) * 10;
2379 setPLL(bios, NV_PRAMDAC_NVPLL_COEFF, clock);
2381 clock = ROM16(bios->data[meminitoffs + 2]) * 10;
2382 if (bios->data[meminitoffs] & 1) /* DDR */
2384 setPLL(bios, NV_PRAMDAC_MPLL_COEFF, clock);
2390 init_configure_preinit(struct nvbios *bios, uint16_t offset,
2391 struct init_exec *iexec)
2394 * INIT_CONFIGURE_PREINIT opcode: 0x68 ('h')
2396 * offset (8 bit): opcode
2398 * Equivalent to INIT_DONE on bios version 3 or greater.
2399 * For early bios versions, does early init, loading ram and crystal
2400 * configuration from straps into CR3C
2403 /* no iexec->execute check by design */
2405 uint32_t straps = bios_rd32(bios, NV_PEXTDEV_BOOT_0);
2406 uint8_t cr3c = ((straps << 2) & 0xf0) | (straps & 0x40) >> 6;
2408 if (bios->major_version > 2)
2411 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR,
2412 NV_CIO_CRE_SCRATCH4__INDEX, cr3c);
2418 init_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2421 * INIT_IO opcode: 0x69 ('i')
2423 * offset (8 bit): opcode
2424 * offset + 1 (16 bit): CRTC port
2425 * offset + 3 (8 bit): mask
2426 * offset + 4 (8 bit): data
2428 * Assign ((IOVAL("crtc port") & "mask") | "data") to "crtc port"
2431 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
2432 uint16_t crtcport = ROM16(bios->data[offset + 1]);
2433 uint8_t mask = bios->data[offset + 3];
2434 uint8_t data = bios->data[offset + 4];
2436 if (!iexec->execute)
2439 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Mask: 0x%02X, Data: 0x%02X\n",
2440 offset, crtcport, mask, data);
2443 * I have no idea what this does, but NVIDIA do this magic sequence
2444 * in the places where this INIT_IO happens..
2446 if (dev_priv->card_type >= NV_50 && crtcport == 0x3c3 && data == 1) {
2449 bios_wr32(bios, 0x614100, (bios_rd32(
2450 bios, 0x614100) & 0x0fffffff) | 0x00800000);
2452 bios_wr32(bios, 0x00e18c, bios_rd32(
2453 bios, 0x00e18c) | 0x00020000);
2455 bios_wr32(bios, 0x614900, (bios_rd32(
2456 bios, 0x614900) & 0x0fffffff) | 0x00800000);
2458 bios_wr32(bios, 0x000200, bios_rd32(
2459 bios, 0x000200) & ~0x40000000);
2463 bios_wr32(bios, 0x00e18c, bios_rd32(
2464 bios, 0x00e18c) & ~0x00020000);
2466 bios_wr32(bios, 0x000200, bios_rd32(
2467 bios, 0x000200) | 0x40000000);
2469 bios_wr32(bios, 0x614100, 0x00800018);
2470 bios_wr32(bios, 0x614900, 0x00800018);
2474 bios_wr32(bios, 0x614100, 0x10000018);
2475 bios_wr32(bios, 0x614900, 0x10000018);
2477 for (i = 0; i < 3; i++)
2478 bios_wr32(bios, 0x614280 + (i*0x800), bios_rd32(
2479 bios, 0x614280 + (i*0x800)) & 0xf0f0f0f0);
2481 for (i = 0; i < 2; i++)
2482 bios_wr32(bios, 0x614300 + (i*0x800), bios_rd32(
2483 bios, 0x614300 + (i*0x800)) & 0xfffff0f0);
2485 for (i = 0; i < 3; i++)
2486 bios_wr32(bios, 0x614380 + (i*0x800), bios_rd32(
2487 bios, 0x614380 + (i*0x800)) & 0xfffff0f0);
2489 for (i = 0; i < 2; i++)
2490 bios_wr32(bios, 0x614200 + (i*0x800), bios_rd32(
2491 bios, 0x614200 + (i*0x800)) & 0xfffffff0);
2493 for (i = 0; i < 2; i++)
2494 bios_wr32(bios, 0x614108 + (i*0x800), bios_rd32(
2495 bios, 0x614108 + (i*0x800)) & 0x0fffffff);
2499 bios_port_wr(bios, crtcport, (bios_port_rd(bios, crtcport) & mask) |
2505 init_sub(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2508 * INIT_SUB opcode: 0x6B ('k')
2510 * offset (8 bit): opcode
2511 * offset + 1 (8 bit): script number
2513 * Execute script number "script number", as a subroutine
2516 uint8_t sub = bios->data[offset + 1];
2518 if (!iexec->execute)
2521 BIOSLOG(bios, "0x%04X: Calling script %d\n", offset, sub);
2523 parse_init_table(bios,
2524 ROM16(bios->data[bios->init_script_tbls_ptr + sub * 2]),
2527 BIOSLOG(bios, "0x%04X: End of script %d\n", offset, sub);
2533 init_ram_condition(struct nvbios *bios, uint16_t offset,
2534 struct init_exec *iexec)
2537 * INIT_RAM_CONDITION opcode: 0x6D ('m')
2539 * offset (8 bit): opcode
2540 * offset + 1 (8 bit): mask
2541 * offset + 2 (8 bit): cmpval
2543 * Test if (NV04_PFB_BOOT_0 & "mask") equals "cmpval".
2544 * If condition not met skip subsequent opcodes until condition is
2545 * inverted (INIT_NOT), or we hit INIT_RESUME
2548 uint8_t mask = bios->data[offset + 1];
2549 uint8_t cmpval = bios->data[offset + 2];
2552 if (!iexec->execute)
2555 data = bios_rd32(bios, NV04_PFB_BOOT_0) & mask;
2557 BIOSLOG(bios, "0x%04X: Checking if 0x%08X equals 0x%08X\n",
2558 offset, data, cmpval);
2561 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
2563 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
2564 iexec->execute = false;
2571 init_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2574 * INIT_NV_REG opcode: 0x6E ('n')
2576 * offset (8 bit): opcode
2577 * offset + 1 (32 bit): register
2578 * offset + 5 (32 bit): mask
2579 * offset + 9 (32 bit): data
2581 * Assign ((REGVAL("register") & "mask") | "data") to "register"
2584 uint32_t reg = ROM32(bios->data[offset + 1]);
2585 uint32_t mask = ROM32(bios->data[offset + 5]);
2586 uint32_t data = ROM32(bios->data[offset + 9]);
2588 if (!iexec->execute)
2591 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Mask: 0x%08X, Data: 0x%08X\n",
2592 offset, reg, mask, data);
2594 bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | data);
2600 init_macro(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2603 * INIT_MACRO opcode: 0x6F ('o')
2605 * offset (8 bit): opcode
2606 * offset + 1 (8 bit): macro number
2608 * Look up macro index "macro number" in the macro index table.
2609 * The macro index table entry has 1 byte for the index in the macro
2610 * table, and 1 byte for the number of times to repeat the macro.
2611 * The macro table entry has 4 bytes for the register address and
2612 * 4 bytes for the value to write to that register
2615 uint8_t macro_index_tbl_idx = bios->data[offset + 1];
2616 uint16_t tmp = bios->macro_index_tbl_ptr + (macro_index_tbl_idx * MACRO_INDEX_SIZE);
2617 uint8_t macro_tbl_idx = bios->data[tmp];
2618 uint8_t count = bios->data[tmp + 1];
2622 if (!iexec->execute)
2625 BIOSLOG(bios, "0x%04X: Macro: 0x%02X, MacroTableIndex: 0x%02X, "
2627 offset, macro_index_tbl_idx, macro_tbl_idx, count);
2629 for (i = 0; i < count; i++) {
2630 uint16_t macroentryptr = bios->macro_tbl_ptr + (macro_tbl_idx + i) * MACRO_SIZE;
2632 reg = ROM32(bios->data[macroentryptr]);
2633 data = ROM32(bios->data[macroentryptr + 4]);
2635 bios_wr32(bios, reg, data);
2642 init_done(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2645 * INIT_DONE opcode: 0x71 ('q')
2647 * offset (8 bit): opcode
2649 * End the current script
2652 /* mild retval abuse to stop parsing this table */
2657 init_resume(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2660 * INIT_RESUME opcode: 0x72 ('r')
2662 * offset (8 bit): opcode
2664 * End the current execute / no-execute condition
2670 iexec->execute = true;
2671 BIOSLOG(bios, "0x%04X: ---- Executing following commands ----\n", offset);
2677 init_time(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2680 * INIT_TIME opcode: 0x74 ('t')
2682 * offset (8 bit): opcode
2683 * offset + 1 (16 bit): time
2685 * Sleep for "time" microseconds.
2688 unsigned time = ROM16(bios->data[offset + 1]);
2690 if (!iexec->execute)
2693 BIOSLOG(bios, "0x%04X: Sleeping for 0x%04X microseconds\n",
2699 mdelay((time + 900) / 1000);
2705 init_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2708 * INIT_CONDITION opcode: 0x75 ('u')
2710 * offset (8 bit): opcode
2711 * offset + 1 (8 bit): condition number
2713 * Check condition "condition number" in the condition table.
2714 * If condition not met skip subsequent opcodes until condition is
2715 * inverted (INIT_NOT), or we hit INIT_RESUME
2718 uint8_t cond = bios->data[offset + 1];
2720 if (!iexec->execute)
2723 BIOSLOG(bios, "0x%04X: Condition: 0x%02X\n", offset, cond);
2725 if (bios_condition_met(bios, offset, cond))
2726 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
2728 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
2729 iexec->execute = false;
2736 init_io_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2739 * INIT_IO_CONDITION opcode: 0x76
2741 * offset (8 bit): opcode
2742 * offset + 1 (8 bit): condition number
2744 * Check condition "condition number" in the io condition table.
2745 * If condition not met skip subsequent opcodes until condition is
2746 * inverted (INIT_NOT), or we hit INIT_RESUME
2749 uint8_t cond = bios->data[offset + 1];
2751 if (!iexec->execute)
2754 BIOSLOG(bios, "0x%04X: IO condition: 0x%02X\n", offset, cond);
2756 if (io_condition_met(bios, offset, cond))
2757 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
2759 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
2760 iexec->execute = false;
2767 init_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2770 * INIT_INDEX_IO opcode: 0x78 ('x')
2772 * offset (8 bit): opcode
2773 * offset + 1 (16 bit): CRTC port
2774 * offset + 3 (8 bit): CRTC index
2775 * offset + 4 (8 bit): mask
2776 * offset + 5 (8 bit): data
2778 * Read value at index "CRTC index" on "CRTC port", AND with "mask",
2779 * OR with "data", write-back
2782 uint16_t crtcport = ROM16(bios->data[offset + 1]);
2783 uint8_t crtcindex = bios->data[offset + 3];
2784 uint8_t mask = bios->data[offset + 4];
2785 uint8_t data = bios->data[offset + 5];
2788 if (!iexec->execute)
2791 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
2793 offset, crtcport, crtcindex, mask, data);
2795 value = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) | data;
2796 bios_idxprt_wr(bios, crtcport, crtcindex, value);
2802 init_pll(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2805 * INIT_PLL opcode: 0x79 ('y')
2807 * offset (8 bit): opcode
2808 * offset + 1 (32 bit): register
2809 * offset + 5 (16 bit): freq
2811 * Set PLL register "register" to coefficients for frequency (10kHz)
2815 uint32_t reg = ROM32(bios->data[offset + 1]);
2816 uint16_t freq = ROM16(bios->data[offset + 5]);
2818 if (!iexec->execute)
2821 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Freq: %d0kHz\n", offset, reg, freq);
2823 setPLL(bios, reg, freq * 10);
2829 init_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2832 * INIT_ZM_REG opcode: 0x7A ('z')
2834 * offset (8 bit): opcode
2835 * offset + 1 (32 bit): register
2836 * offset + 5 (32 bit): value
2838 * Assign "value" to "register"
2841 uint32_t reg = ROM32(bios->data[offset + 1]);
2842 uint32_t value = ROM32(bios->data[offset + 5]);
2844 if (!iexec->execute)
2847 if (reg == 0x000200)
2850 bios_wr32(bios, reg, value);
2856 init_ram_restrict_pll(struct nvbios *bios, uint16_t offset,
2857 struct init_exec *iexec)
2860 * INIT_RAM_RESTRICT_PLL opcode: 0x87 ('')
2862 * offset (8 bit): opcode
2863 * offset + 1 (8 bit): PLL type
2864 * offset + 2 (32 bit): frequency 0
2866 * Uses the RAMCFG strap of PEXTDEV_BOOT as an index into the table at
2867 * ram_restrict_table_ptr. The value read from there is used to select
2868 * a frequency from the table starting at 'frequency 0' to be
2869 * programmed into the PLL corresponding to 'type'.
2871 * The PLL limits table on cards using this opcode has a mapping of
2872 * 'type' to the relevant registers.
2875 struct drm_device *dev = bios->dev;
2876 uint32_t strap = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) & 0x0000003c) >> 2;
2877 uint8_t index = bios->data[bios->ram_restrict_tbl_ptr + strap];
2878 uint8_t type = bios->data[offset + 1];
2879 uint32_t freq = ROM32(bios->data[offset + 2 + (index * 4)]);
2880 uint8_t *pll_limits = &bios->data[bios->pll_limit_tbl_ptr], *entry;
2881 int len = 2 + bios->ram_restrict_group_count * 4;
2884 if (!iexec->execute)
2887 if (!bios->pll_limit_tbl_ptr || (pll_limits[0] & 0xf0) != 0x30) {
2888 NV_ERROR(dev, "PLL limits table not version 3.x\n");
2889 return len; /* deliberate, allow default clocks to remain */
2892 entry = pll_limits + pll_limits[1];
2893 for (i = 0; i < pll_limits[3]; i++, entry += pll_limits[2]) {
2894 if (entry[0] == type) {
2895 uint32_t reg = ROM32(entry[3]);
2897 BIOSLOG(bios, "0x%04X: "
2898 "Type %02x Reg 0x%08x Freq %dKHz\n",
2899 offset, type, reg, freq);
2901 setPLL(bios, reg, freq);
2906 NV_ERROR(dev, "PLL type 0x%02x not found in PLL limits table", type);
2911 init_8c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2914 * INIT_8C opcode: 0x8C ('')
2924 init_8d(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2927 * INIT_8D opcode: 0x8D ('')
2937 init_gpio(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2940 * INIT_GPIO opcode: 0x8E ('')
2942 * offset (8 bit): opcode
2944 * Loop over all entries in the DCB GPIO table, and initialise
2945 * each GPIO according to various values listed in each entry
2948 if (iexec->execute && bios->execute)
2949 nouveau_gpio_reset(bios->dev);
2955 init_ram_restrict_zm_reg_group(struct nvbios *bios, uint16_t offset,
2956 struct init_exec *iexec)
2959 * INIT_RAM_RESTRICT_ZM_REG_GROUP opcode: 0x8F ('')
2961 * offset (8 bit): opcode
2962 * offset + 1 (32 bit): reg
2963 * offset + 5 (8 bit): regincrement
2964 * offset + 6 (8 bit): count
2965 * offset + 7 (32 bit): value 1,1
2968 * Use the RAMCFG strap of PEXTDEV_BOOT as an index into the table at
2969 * ram_restrict_table_ptr. The value read from here is 'n', and
2970 * "value 1,n" gets written to "reg". This repeats "count" times and on
2971 * each iteration 'm', "reg" increases by "regincrement" and
2972 * "value m,n" is used. The extent of n is limited by a number read
2973 * from the 'M' BIT table, herein called "blocklen"
2976 uint32_t reg = ROM32(bios->data[offset + 1]);
2977 uint8_t regincrement = bios->data[offset + 5];
2978 uint8_t count = bios->data[offset + 6];
2979 uint32_t strap_ramcfg, data;
2980 /* previously set by 'M' BIT table */
2981 uint16_t blocklen = bios->ram_restrict_group_count * 4;
2982 int len = 7 + count * blocklen;
2986 /* critical! to know the length of the opcode */;
2989 "0x%04X: Zero block length - has the M table "
2990 "been parsed?\n", offset);
2994 if (!iexec->execute)
2997 strap_ramcfg = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 2) & 0xf;
2998 index = bios->data[bios->ram_restrict_tbl_ptr + strap_ramcfg];
3000 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, RegIncrement: 0x%02X, "
3001 "Count: 0x%02X, StrapRamCfg: 0x%02X, Index: 0x%02X\n",
3002 offset, reg, regincrement, count, strap_ramcfg, index);
3004 for (i = 0; i < count; i++) {
3005 data = ROM32(bios->data[offset + 7 + index * 4 + blocklen * i]);
3007 bios_wr32(bios, reg, data);
3009 reg += regincrement;
3016 init_copy_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3019 * INIT_COPY_ZM_REG opcode: 0x90 ('')
3021 * offset (8 bit): opcode
3022 * offset + 1 (32 bit): src reg
3023 * offset + 5 (32 bit): dst reg
3025 * Put contents of "src reg" into "dst reg"
3028 uint32_t srcreg = ROM32(bios->data[offset + 1]);
3029 uint32_t dstreg = ROM32(bios->data[offset + 5]);
3031 if (!iexec->execute)
3034 bios_wr32(bios, dstreg, bios_rd32(bios, srcreg));
3040 init_zm_reg_group_addr_latched(struct nvbios *bios, uint16_t offset,
3041 struct init_exec *iexec)
3044 * INIT_ZM_REG_GROUP_ADDRESS_LATCHED opcode: 0x91 ('')
3046 * offset (8 bit): opcode
3047 * offset + 1 (32 bit): dst reg
3048 * offset + 5 (8 bit): count
3049 * offset + 6 (32 bit): data 1
3052 * For each of "count" values write "data n" to "dst reg"
3055 uint32_t reg = ROM32(bios->data[offset + 1]);
3056 uint8_t count = bios->data[offset + 5];
3057 int len = 6 + count * 4;
3060 if (!iexec->execute)
3063 for (i = 0; i < count; i++) {
3064 uint32_t data = ROM32(bios->data[offset + 6 + 4 * i]);
3065 bios_wr32(bios, reg, data);
3072 init_reserved(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3075 * INIT_RESERVED opcode: 0x92 ('')
3077 * offset (8 bit): opcode
3079 * Seemingly does nothing
3086 init_96(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3089 * INIT_96 opcode: 0x96 ('')
3091 * offset (8 bit): opcode
3092 * offset + 1 (32 bit): sreg
3093 * offset + 5 (8 bit): sshift
3094 * offset + 6 (8 bit): smask
3095 * offset + 7 (8 bit): index
3096 * offset + 8 (32 bit): reg
3097 * offset + 12 (32 bit): mask
3098 * offset + 16 (8 bit): shift
3102 uint16_t xlatptr = bios->init96_tbl_ptr + (bios->data[offset + 7] * 2);
3103 uint32_t reg = ROM32(bios->data[offset + 8]);
3104 uint32_t mask = ROM32(bios->data[offset + 12]);
3107 val = bios_rd32(bios, ROM32(bios->data[offset + 1]));
3108 if (bios->data[offset + 5] < 0x80)
3109 val >>= bios->data[offset + 5];
3111 val <<= (0x100 - bios->data[offset + 5]);
3112 val &= bios->data[offset + 6];
3114 val = bios->data[ROM16(bios->data[xlatptr]) + val];
3115 val <<= bios->data[offset + 16];
3117 if (!iexec->execute)
3120 bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | val);
3125 init_97(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3128 * INIT_97 opcode: 0x97 ('')
3130 * offset (8 bit): opcode
3131 * offset + 1 (32 bit): register
3132 * offset + 5 (32 bit): mask
3133 * offset + 9 (32 bit): value
3135 * Adds "value" to "register" preserving the fields specified
3139 uint32_t reg = ROM32(bios->data[offset + 1]);
3140 uint32_t mask = ROM32(bios->data[offset + 5]);
3141 uint32_t add = ROM32(bios->data[offset + 9]);
3144 val = bios_rd32(bios, reg);
3145 val = (val & mask) | ((val + add) & ~mask);
3147 if (!iexec->execute)
3150 bios_wr32(bios, reg, val);
3155 init_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3158 * INIT_AUXCH opcode: 0x98 ('')
3160 * offset (8 bit): opcode
3161 * offset + 1 (32 bit): address
3162 * offset + 5 (8 bit): count
3163 * offset + 6 (8 bit): mask 0
3164 * offset + 7 (8 bit): data 0
3169 struct drm_device *dev = bios->dev;
3170 struct nouveau_i2c_chan *auxch;
3171 uint32_t addr = ROM32(bios->data[offset + 1]);
3172 uint8_t count = bios->data[offset + 5];
3173 int len = 6 + count * 2;
3176 if (!bios->display.output) {
3177 NV_ERROR(dev, "INIT_AUXCH: no active output\n");
3181 auxch = init_i2c_device_find(dev, bios->display.output->i2c_index);
3183 NV_ERROR(dev, "INIT_AUXCH: couldn't get auxch %d\n",
3184 bios->display.output->i2c_index);
3188 if (!iexec->execute)
3192 for (i = 0; i < count; i++, offset += 2) {
3195 ret = nouveau_dp_auxch(auxch, 9, addr, &data, 1);
3197 NV_ERROR(dev, "INIT_AUXCH: rd auxch fail %d\n", ret);
3201 data &= bios->data[offset + 0];
3202 data |= bios->data[offset + 1];
3204 ret = nouveau_dp_auxch(auxch, 8, addr, &data, 1);
3206 NV_ERROR(dev, "INIT_AUXCH: wr auxch fail %d\n", ret);
3215 init_zm_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3218 * INIT_ZM_AUXCH opcode: 0x99 ('')
3220 * offset (8 bit): opcode
3221 * offset + 1 (32 bit): address
3222 * offset + 5 (8 bit): count
3223 * offset + 6 (8 bit): data 0
3228 struct drm_device *dev = bios->dev;
3229 struct nouveau_i2c_chan *auxch;
3230 uint32_t addr = ROM32(bios->data[offset + 1]);
3231 uint8_t count = bios->data[offset + 5];
3232 int len = 6 + count;
3235 if (!bios->display.output) {
3236 NV_ERROR(dev, "INIT_ZM_AUXCH: no active output\n");
3240 auxch = init_i2c_device_find(dev, bios->display.output->i2c_index);
3242 NV_ERROR(dev, "INIT_ZM_AUXCH: couldn't get auxch %d\n",
3243 bios->display.output->i2c_index);
3247 if (!iexec->execute)
3251 for (i = 0; i < count; i++, offset++) {
3252 ret = nouveau_dp_auxch(auxch, 8, addr, &bios->data[offset], 1);
3254 NV_ERROR(dev, "INIT_ZM_AUXCH: wr auxch fail %d\n", ret);
3263 init_i2c_long_if(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3266 * INIT_I2C_LONG_IF opcode: 0x9A ('')
3268 * offset (8 bit): opcode
3269 * offset + 1 (8 bit): DCB I2C table entry index
3270 * offset + 2 (8 bit): I2C slave address
3271 * offset + 3 (16 bit): I2C register
3272 * offset + 5 (8 bit): mask
3273 * offset + 6 (8 bit): data
3275 * Read the register given by "I2C register" on the device addressed
3276 * by "I2C slave address" on the I2C bus given by "DCB I2C table
3277 * entry index". Compare the result AND "mask" to "data".
3278 * If they're not equal, skip subsequent opcodes until condition is
3279 * inverted (INIT_NOT), or we hit INIT_RESUME
3282 uint8_t i2c_index = bios->data[offset + 1];
3283 uint8_t i2c_address = bios->data[offset + 2] >> 1;
3284 uint8_t reglo = bios->data[offset + 3];
3285 uint8_t reghi = bios->data[offset + 4];
3286 uint8_t mask = bios->data[offset + 5];
3287 uint8_t data = bios->data[offset + 6];
3288 struct nouveau_i2c_chan *chan;
3289 uint8_t buf0[2] = { reghi, reglo };
3291 struct i2c_msg msg[2] = {
3292 { i2c_address, 0, 1, buf0 },
3293 { i2c_address, I2C_M_RD, 1, buf1 },
3297 /* no execute check by design */
3299 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X\n",
3300 offset, i2c_index, i2c_address);
3302 chan = init_i2c_device_find(bios->dev, i2c_index);
3307 ret = i2c_transfer(&chan->adapter, msg, 2);
3309 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X:0x%02X, Value: [no device], "
3310 "Mask: 0x%02X, Data: 0x%02X\n",
3311 offset, reghi, reglo, mask, data);
3316 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X:0x%02X, Value: 0x%02X, "
3317 "Mask: 0x%02X, Data: 0x%02X\n",
3318 offset, reghi, reglo, buf1[0], mask, data);
3320 iexec->execute = ((buf1[0] & mask) == data);
3325 static struct init_tbl_entry itbl_entry[] = {
3326 /* command name , id , length , offset , mult , command handler */
3327 /* INIT_PROG (0x31, 15, 10, 4) removed due to no example of use */
3328 { "INIT_IO_RESTRICT_PROG" , 0x32, init_io_restrict_prog },
3329 { "INIT_REPEAT" , 0x33, init_repeat },
3330 { "INIT_IO_RESTRICT_PLL" , 0x34, init_io_restrict_pll },
3331 { "INIT_END_REPEAT" , 0x36, init_end_repeat },
3332 { "INIT_COPY" , 0x37, init_copy },
3333 { "INIT_NOT" , 0x38, init_not },
3334 { "INIT_IO_FLAG_CONDITION" , 0x39, init_io_flag_condition },
3335 { "INIT_DP_CONDITION" , 0x3A, init_dp_condition },
3336 { "INIT_OP_3B" , 0x3B, init_op_3b },
3337 { "INIT_OP_3C" , 0x3C, init_op_3c },
3338 { "INIT_INDEX_ADDRESS_LATCHED" , 0x49, init_idx_addr_latched },
3339 { "INIT_IO_RESTRICT_PLL2" , 0x4A, init_io_restrict_pll2 },
3340 { "INIT_PLL2" , 0x4B, init_pll2 },
3341 { "INIT_I2C_BYTE" , 0x4C, init_i2c_byte },
3342 { "INIT_ZM_I2C_BYTE" , 0x4D, init_zm_i2c_byte },
3343 { "INIT_ZM_I2C" , 0x4E, init_zm_i2c },
3344 { "INIT_TMDS" , 0x4F, init_tmds },
3345 { "INIT_ZM_TMDS_GROUP" , 0x50, init_zm_tmds_group },
3346 { "INIT_CR_INDEX_ADDRESS_LATCHED" , 0x51, init_cr_idx_adr_latch },
3347 { "INIT_CR" , 0x52, init_cr },
3348 { "INIT_ZM_CR" , 0x53, init_zm_cr },
3349 { "INIT_ZM_CR_GROUP" , 0x54, init_zm_cr_group },
3350 { "INIT_CONDITION_TIME" , 0x56, init_condition_time },
3351 { "INIT_LTIME" , 0x57, init_ltime },
3352 { "INIT_ZM_REG_SEQUENCE" , 0x58, init_zm_reg_sequence },
3353 /* INIT_INDIRECT_REG (0x5A, 7, 0, 0) removed due to no example of use */
3354 { "INIT_SUB_DIRECT" , 0x5B, init_sub_direct },
3355 { "INIT_JUMP" , 0x5C, init_jump },
3356 { "INIT_I2C_IF" , 0x5E, init_i2c_if },
3357 { "INIT_COPY_NV_REG" , 0x5F, init_copy_nv_reg },
3358 { "INIT_ZM_INDEX_IO" , 0x62, init_zm_index_io },
3359 { "INIT_COMPUTE_MEM" , 0x63, init_compute_mem },
3360 { "INIT_RESET" , 0x65, init_reset },
3361 { "INIT_CONFIGURE_MEM" , 0x66, init_configure_mem },
3362 { "INIT_CONFIGURE_CLK" , 0x67, init_configure_clk },
3363 { "INIT_CONFIGURE_PREINIT" , 0x68, init_configure_preinit },
3364 { "INIT_IO" , 0x69, init_io },
3365 { "INIT_SUB" , 0x6B, init_sub },
3366 { "INIT_RAM_CONDITION" , 0x6D, init_ram_condition },
3367 { "INIT_NV_REG" , 0x6E, init_nv_reg },
3368 { "INIT_MACRO" , 0x6F, init_macro },
3369 { "INIT_DONE" , 0x71, init_done },
3370 { "INIT_RESUME" , 0x72, init_resume },
3371 /* INIT_RAM_CONDITION2 (0x73, 9, 0, 0) removed due to no example of use */
3372 { "INIT_TIME" , 0x74, init_time },
3373 { "INIT_CONDITION" , 0x75, init_condition },
3374 { "INIT_IO_CONDITION" , 0x76, init_io_condition },
3375 { "INIT_INDEX_IO" , 0x78, init_index_io },
3376 { "INIT_PLL" , 0x79, init_pll },
3377 { "INIT_ZM_REG" , 0x7A, init_zm_reg },
3378 { "INIT_RAM_RESTRICT_PLL" , 0x87, init_ram_restrict_pll },
3379 { "INIT_8C" , 0x8C, init_8c },
3380 { "INIT_8D" , 0x8D, init_8d },
3381 { "INIT_GPIO" , 0x8E, init_gpio },
3382 { "INIT_RAM_RESTRICT_ZM_REG_GROUP" , 0x8F, init_ram_restrict_zm_reg_group },
3383 { "INIT_COPY_ZM_REG" , 0x90, init_copy_zm_reg },
3384 { "INIT_ZM_REG_GROUP_ADDRESS_LATCHED" , 0x91, init_zm_reg_group_addr_latched },
3385 { "INIT_RESERVED" , 0x92, init_reserved },
3386 { "INIT_96" , 0x96, init_96 },
3387 { "INIT_97" , 0x97, init_97 },
3388 { "INIT_AUXCH" , 0x98, init_auxch },
3389 { "INIT_ZM_AUXCH" , 0x99, init_zm_auxch },
3390 { "INIT_I2C_LONG_IF" , 0x9A, init_i2c_long_if },
3394 #define MAX_TABLE_OPS 1000
3397 parse_init_table(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3400 * Parses all commands in an init table.
3402 * We start out executing all commands found in the init table. Some
3403 * opcodes may change the status of iexec->execute to SKIP, which will
3404 * cause the following opcodes to perform no operation until the value
3405 * is changed back to EXECUTE.
3408 int count = 0, i, ret;
3411 /* catch NULL script pointers */
3416 * Loop until INIT_DONE causes us to break out of the loop
3417 * (or until offset > bios length just in case... )
3418 * (and no more than MAX_TABLE_OPS iterations, just in case... )
3420 while ((offset < bios->length) && (count++ < MAX_TABLE_OPS)) {
3421 id = bios->data[offset];
3423 /* Find matching id in itbl_entry */
3424 for (i = 0; itbl_entry[i].name && (itbl_entry[i].id != id); i++)
3427 if (!itbl_entry[i].name) {
3429 "0x%04X: Init table command not found: "
3430 "0x%02X\n", offset, id);
3434 BIOSLOG(bios, "0x%04X: [ (0x%02X) - %s ]\n", offset,
3435 itbl_entry[i].id, itbl_entry[i].name);
3437 /* execute eventual command handler */
3438 ret = (*itbl_entry[i].handler)(bios, offset, iexec);
3440 NV_ERROR(bios->dev, "0x%04X: Failed parsing init "
3441 "table opcode: %s %d\n", offset,
3442 itbl_entry[i].name, ret);
3449 * Add the offset of the current command including all data
3450 * of that command. The offset will then be pointing on the
3456 if (offset >= bios->length)
3458 "Offset 0x%04X greater than known bios image length. "
3459 "Corrupt image?\n", offset);
3460 if (count >= MAX_TABLE_OPS)
3462 "More than %d opcodes to a table is unlikely, "
3463 "is the bios image corrupt?\n", MAX_TABLE_OPS);
3469 parse_init_tables(struct nvbios *bios)
3471 /* Loops and calls parse_init_table() for each present table. */
3475 struct init_exec iexec = {true, false};
3477 if (bios->old_style_init) {
3478 if (bios->init_script_tbls_ptr)
3479 parse_init_table(bios, bios->init_script_tbls_ptr, &iexec);
3480 if (bios->extra_init_script_tbl_ptr)
3481 parse_init_table(bios, bios->extra_init_script_tbl_ptr, &iexec);
3486 while ((table = ROM16(bios->data[bios->init_script_tbls_ptr + i]))) {
3488 "Parsing VBIOS init table %d at offset 0x%04X\n",
3490 BIOSLOG(bios, "0x%04X: ------ Executing following commands ------\n", table);
3492 parse_init_table(bios, table, &iexec);
3497 static uint16_t clkcmptable(struct nvbios *bios, uint16_t clktable, int pxclk)
3499 int compare_record_len, i = 0;
3500 uint16_t compareclk, scriptptr = 0;
3502 if (bios->major_version < 5) /* pre BIT */
3503 compare_record_len = 3;
3505 compare_record_len = 4;
3508 compareclk = ROM16(bios->data[clktable + compare_record_len * i]);
3509 if (pxclk >= compareclk * 10) {
3510 if (bios->major_version < 5) {
3511 uint8_t tmdssub = bios->data[clktable + 2 + compare_record_len * i];
3512 scriptptr = ROM16(bios->data[bios->init_script_tbls_ptr + tmdssub * 2]);
3514 scriptptr = ROM16(bios->data[clktable + 2 + compare_record_len * i]);
3518 } while (compareclk);
3524 run_digital_op_script(struct drm_device *dev, uint16_t scriptptr,
3525 struct dcb_entry *dcbent, int head, bool dl)
3527 struct drm_nouveau_private *dev_priv = dev->dev_private;
3528 struct nvbios *bios = &dev_priv->vbios;
3529 struct init_exec iexec = {true, false};
3531 NV_TRACE(dev, "0x%04X: Parsing digital output script table\n",
3533 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_44,
3534 head ? NV_CIO_CRE_44_HEADB : NV_CIO_CRE_44_HEADA);
3535 /* note: if dcb entries have been merged, index may be misleading */
3536 NVWriteVgaCrtc5758(dev, head, 0, dcbent->index);
3537 parse_init_table(bios, scriptptr, &iexec);
3539 nv04_dfp_bind_head(dev, dcbent, head, dl);
3542 static int call_lvds_manufacturer_script(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script)
3544 struct drm_nouveau_private *dev_priv = dev->dev_private;
3545 struct nvbios *bios = &dev_priv->vbios;
3546 uint8_t sub = bios->data[bios->fp.xlated_entry + script] + (bios->fp.link_c_increment && dcbent->or & OUTPUT_C ? 1 : 0);
3547 uint16_t scriptofs = ROM16(bios->data[bios->init_script_tbls_ptr + sub * 2]);
3549 if (!bios->fp.xlated_entry || !sub || !scriptofs)
3552 run_digital_op_script(dev, scriptofs, dcbent, head, bios->fp.dual_link);
3554 if (script == LVDS_PANEL_OFF) {
3555 /* off-on delay in ms */
3556 mdelay(ROM16(bios->data[bios->fp.xlated_entry + 7]));
3559 /* Powerbook specific quirks */
3560 if (script == LVDS_RESET &&
3561 (dev->pci_device == 0x0179 || dev->pci_device == 0x0189 ||
3562 dev->pci_device == 0x0329))
3563 nv_write_tmds(dev, dcbent->or, 0, 0x02, 0x72);
3569 static int run_lvds_table(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script, int pxclk)
3572 * The BIT LVDS table's header has the information to setup the
3573 * necessary registers. Following the standard 4 byte header are:
3574 * A bitmask byte and a dual-link transition pxclk value for use in
3575 * selecting the init script when not using straps; 4 script pointers
3576 * for panel power, selected by output and on/off; and 8 table pointers
3577 * for panel init, the needed one determined by output, and bits in the
3578 * conf byte. These tables are similar to the TMDS tables, consisting
3579 * of a list of pxclks and script pointers.
3581 struct drm_nouveau_private *dev_priv = dev->dev_private;
3582 struct nvbios *bios = &dev_priv->vbios;
3583 unsigned int outputset = (dcbent->or == 4) ? 1 : 0;
3584 uint16_t scriptptr = 0, clktable;
3587 * For now we assume version 3.0 table - g80 support will need some
3594 case LVDS_BACKLIGHT_ON:
3596 scriptptr = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 7 + outputset * 2]);
3598 case LVDS_BACKLIGHT_OFF:
3599 case LVDS_PANEL_OFF:
3600 scriptptr = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 11 + outputset * 2]);
3603 clktable = bios->fp.lvdsmanufacturerpointer + 15;
3604 if (dcbent->or == 4)
3607 if (dcbent->lvdsconf.use_straps_for_mode) {
3608 if (bios->fp.dual_link)
3610 if (bios->fp.if_is_24bit)
3614 int cmpval_24bit = (dcbent->or == 4) ? 4 : 1;
3616 if (bios->fp.dual_link) {
3621 if (bios->fp.strapless_is_24bit & cmpval_24bit)
3625 clktable = ROM16(bios->data[clktable]);
3627 NV_ERROR(dev, "Pixel clock comparison table not found\n");
3630 scriptptr = clkcmptable(bios, clktable, pxclk);
3634 NV_ERROR(dev, "LVDS output init script not found\n");
3637 run_digital_op_script(dev, scriptptr, dcbent, head, bios->fp.dual_link);
3642 int call_lvds_script(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script, int pxclk)
3645 * LVDS operations are multiplexed in an effort to present a single API
3646 * which works with two vastly differing underlying structures.
3647 * This acts as the demux
3650 struct drm_nouveau_private *dev_priv = dev->dev_private;
3651 struct nvbios *bios = &dev_priv->vbios;
3652 uint8_t lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer];
3653 uint32_t sel_clk_binding, sel_clk;
3656 if (bios->fp.last_script_invoc == (script << 1 | head) || !lvds_ver ||
3657 (lvds_ver >= 0x30 && script == LVDS_INIT))
3660 if (!bios->fp.lvds_init_run) {
3661 bios->fp.lvds_init_run = true;
3662 call_lvds_script(dev, dcbent, head, LVDS_INIT, pxclk);
3665 if (script == LVDS_PANEL_ON && bios->fp.reset_after_pclk_change)
3666 call_lvds_script(dev, dcbent, head, LVDS_RESET, pxclk);
3667 if (script == LVDS_RESET && bios->fp.power_off_for_reset)
3668 call_lvds_script(dev, dcbent, head, LVDS_PANEL_OFF, pxclk);
3670 NV_TRACE(dev, "Calling LVDS script %d:\n", script);
3672 /* don't let script change pll->head binding */
3673 sel_clk_binding = bios_rd32(bios, NV_PRAMDAC_SEL_CLK) & 0x50000;
3675 if (lvds_ver < 0x30)
3676 ret = call_lvds_manufacturer_script(dev, dcbent, head, script);
3678 ret = run_lvds_table(dev, dcbent, head, script, pxclk);
3680 bios->fp.last_script_invoc = (script << 1 | head);
3682 sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000;
3683 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding);
3684 /* some scripts set a value in NV_PBUS_POWERCTRL_2 and break video overlay */
3685 nvWriteMC(dev, NV_PBUS_POWERCTRL_2, 0);
3690 struct lvdstableheader {
3691 uint8_t lvds_ver, headerlen, recordlen;
3694 static int parse_lvds_manufacturer_table_header(struct drm_device *dev, struct nvbios *bios, struct lvdstableheader *lth)
3697 * BMP version (0xa) LVDS table has a simple header of version and
3698 * record length. The BIT LVDS table has the typical BIT table header:
3699 * version byte, header length byte, record length byte, and a byte for
3700 * the maximum number of records that can be held in the table.
3703 uint8_t lvds_ver, headerlen, recordlen;
3705 memset(lth, 0, sizeof(struct lvdstableheader));
3707 if (bios->fp.lvdsmanufacturerpointer == 0x0) {
3708 NV_ERROR(dev, "Pointer to LVDS manufacturer table invalid\n");
3712 lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer];
3715 case 0x0a: /* pre NV40 */
3717 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
3719 case 0x30: /* NV4x */
3720 headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
3721 if (headerlen < 0x1f) {
3722 NV_ERROR(dev, "LVDS table header not understood\n");
3725 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2];
3727 case 0x40: /* G80/G90 */
3728 headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
3729 if (headerlen < 0x7) {
3730 NV_ERROR(dev, "LVDS table header not understood\n");
3733 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2];
3737 "LVDS table revision %d.%d not currently supported\n",
3738 lvds_ver >> 4, lvds_ver & 0xf);
3742 lth->lvds_ver = lvds_ver;
3743 lth->headerlen = headerlen;
3744 lth->recordlen = recordlen;
3750 get_fp_strap(struct drm_device *dev, struct nvbios *bios)
3752 struct drm_nouveau_private *dev_priv = dev->dev_private;
3755 * The fp strap is normally dictated by the "User Strap" in
3756 * PEXTDEV_BOOT_0[20:16], but on BMP cards when bit 2 of the
3757 * Internal_Flags struct at 0x48 is set, the user strap gets overriden
3758 * by the PCI subsystem ID during POST, but not before the previous user
3759 * strap has been committed to CR58 for CR57=0xf on head A, which may be
3760 * read and used instead
3763 if (bios->major_version < 5 && bios->data[0x48] & 0x4)
3764 return NVReadVgaCrtc5758(dev, 0, 0xf) & 0xf;
3766 if (dev_priv->card_type >= NV_50)
3767 return (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 24) & 0xf;
3769 return (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 16) & 0xf;
3772 static int parse_fp_mode_table(struct drm_device *dev, struct nvbios *bios)
3775 uint8_t fptable_ver, headerlen = 0, recordlen, fpentries = 0xf, fpindex;
3776 int ret, ofs, fpstrapping;
3777 struct lvdstableheader lth;
3779 if (bios->fp.fptablepointer == 0x0) {
3780 /* Apple cards don't have the fp table; the laptops use DDC */
3781 /* The table is also missing on some x86 IGPs */
3783 NV_ERROR(dev, "Pointer to flat panel table invalid\n");
3785 bios->digital_min_front_porch = 0x4b;
3789 fptable = &bios->data[bios->fp.fptablepointer];
3790 fptable_ver = fptable[0];
3792 switch (fptable_ver) {
3794 * BMP version 0x5.0x11 BIOSen have version 1 like tables, but no
3795 * version field, and miss one of the spread spectrum/PWM bytes.
3796 * This could affect early GF2Go parts (not seen any appropriate ROMs
3797 * though). Here we assume that a version of 0x05 matches this case
3798 * (combining with a BMP version check would be better), as the
3799 * common case for the panel type field is 0x0005, and that is in
3800 * fact what we are reading the first byte of.
3802 case 0x05: /* some NV10, 11, 15, 16 */
3806 case 0x10: /* some NV15/16, and NV11+ */
3810 case 0x20: /* NV40+ */
3811 headerlen = fptable[1];
3812 recordlen = fptable[2];
3813 fpentries = fptable[3];
3815 * fptable[4] is the minimum
3816 * RAMDAC_FP_HCRTC -> RAMDAC_FP_HSYNC_START gap
3818 bios->digital_min_front_porch = fptable[4];
3823 "FP table revision %d.%d not currently supported\n",
3824 fptable_ver >> 4, fptable_ver & 0xf);
3828 if (!bios->is_mobile) /* !mobile only needs digital_min_front_porch */
3831 ret = parse_lvds_manufacturer_table_header(dev, bios, <h);
3835 if (lth.lvds_ver == 0x30 || lth.lvds_ver == 0x40) {
3836 bios->fp.fpxlatetableptr = bios->fp.lvdsmanufacturerpointer +
3838 bios->fp.xlatwidth = lth.recordlen;
3840 if (bios->fp.fpxlatetableptr == 0x0) {
3841 NV_ERROR(dev, "Pointer to flat panel xlat table invalid\n");
3845 fpstrapping = get_fp_strap(dev, bios);
3847 fpindex = bios->data[bios->fp.fpxlatetableptr +
3848 fpstrapping * bios->fp.xlatwidth];
3850 if (fpindex > fpentries) {
3851 NV_ERROR(dev, "Bad flat panel table index\n");
3855 /* nv4x cards need both a strap value and fpindex of 0xf to use DDC */
3856 if (lth.lvds_ver > 0x10)
3857 bios->fp_no_ddc = fpstrapping != 0xf || fpindex != 0xf;
3860 * If either the strap or xlated fpindex value are 0xf there is no
3861 * panel using a strap-derived bios mode present. this condition
3862 * includes, but is different from, the DDC panel indicator above
3864 if (fpstrapping == 0xf || fpindex == 0xf)
3867 bios->fp.mode_ptr = bios->fp.fptablepointer + headerlen +
3868 recordlen * fpindex + ofs;
3870 NV_TRACE(dev, "BIOS FP mode: %dx%d (%dkHz pixel clock)\n",
3871 ROM16(bios->data[bios->fp.mode_ptr + 11]) + 1,
3872 ROM16(bios->data[bios->fp.mode_ptr + 25]) + 1,
3873 ROM16(bios->data[bios->fp.mode_ptr + 7]) * 10);
3878 bool nouveau_bios_fp_mode(struct drm_device *dev, struct drm_display_mode *mode)
3880 struct drm_nouveau_private *dev_priv = dev->dev_private;
3881 struct nvbios *bios = &dev_priv->vbios;
3882 uint8_t *mode_entry = &bios->data[bios->fp.mode_ptr];
3884 if (!mode) /* just checking whether we can produce a mode */
3885 return bios->fp.mode_ptr;
3887 memset(mode, 0, sizeof(struct drm_display_mode));
3889 * For version 1.0 (version in byte 0):
3890 * bytes 1-2 are "panel type", including bits on whether Colour/mono,
3891 * single/dual link, and type (TFT etc.)
3892 * bytes 3-6 are bits per colour in RGBX
3894 mode->clock = ROM16(mode_entry[7]) * 10;
3895 /* bytes 9-10 is HActive */
3896 mode->hdisplay = ROM16(mode_entry[11]) + 1;
3898 * bytes 13-14 is HValid Start
3899 * bytes 15-16 is HValid End
3901 mode->hsync_start = ROM16(mode_entry[17]) + 1;
3902 mode->hsync_end = ROM16(mode_entry[19]) + 1;
3903 mode->htotal = ROM16(mode_entry[21]) + 1;
3904 /* bytes 23-24, 27-30 similarly, but vertical */
3905 mode->vdisplay = ROM16(mode_entry[25]) + 1;
3906 mode->vsync_start = ROM16(mode_entry[31]) + 1;
3907 mode->vsync_end = ROM16(mode_entry[33]) + 1;
3908 mode->vtotal = ROM16(mode_entry[35]) + 1;
3909 mode->flags |= (mode_entry[37] & 0x10) ?
3910 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
3911 mode->flags |= (mode_entry[37] & 0x1) ?
3912 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
3914 * bytes 38-39 relate to spread spectrum settings
3915 * bytes 40-43 are something to do with PWM
3918 mode->status = MODE_OK;
3919 mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
3920 drm_mode_set_name(mode);
3921 return bios->fp.mode_ptr;
3924 int nouveau_bios_parse_lvds_table(struct drm_device *dev, int pxclk, bool *dl, bool *if_is_24bit)
3927 * The LVDS table header is (mostly) described in
3928 * parse_lvds_manufacturer_table_header(): the BIT header additionally
3929 * contains the dual-link transition pxclk (in 10s kHz), at byte 5 - if
3930 * straps are not being used for the panel, this specifies the frequency
3931 * at which modes should be set up in the dual link style.
3933 * Following the header, the BMP (ver 0xa) table has several records,
3934 * indexed by a separate xlat table, indexed in turn by the fp strap in
3935 * EXTDEV_BOOT. Each record had a config byte, followed by 6 script
3936 * numbers for use by INIT_SUB which controlled panel init and power,
3937 * and finally a dword of ms to sleep between power off and on
3940 * In the BIT versions, the table following the header serves as an
3941 * integrated config and xlat table: the records in the table are
3942 * indexed by the FP strap nibble in EXTDEV_BOOT, and each record has
3943 * two bytes - the first as a config byte, the second for indexing the
3944 * fp mode table pointed to by the BIT 'D' table
3946 * DDC is not used until after card init, so selecting the correct table
3947 * entry and setting the dual link flag for EDID equipped panels,
3948 * requiring tests against the native-mode pixel clock, cannot be done
3949 * until later, when this function should be called with non-zero pxclk
3951 struct drm_nouveau_private *dev_priv = dev->dev_private;
3952 struct nvbios *bios = &dev_priv->vbios;
3953 int fpstrapping = get_fp_strap(dev, bios), lvdsmanufacturerindex = 0;
3954 struct lvdstableheader lth;
3956 int ret, chip_version = bios->chip_version;
3958 ret = parse_lvds_manufacturer_table_header(dev, bios, <h);
3962 switch (lth.lvds_ver) {
3963 case 0x0a: /* pre NV40 */
3964 lvdsmanufacturerindex = bios->data[
3965 bios->fp.fpxlatemanufacturertableptr +
3968 /* we're done if this isn't the EDID panel case */
3972 if (chip_version < 0x25) {
3975 * It seems the old style lvds script pointer is reused
3976 * to select 18/24 bit colour depth for EDID panels.
3978 lvdsmanufacturerindex =
3979 (bios->legacy.lvds_single_a_script_ptr & 1) ?
3981 if (pxclk >= bios->fp.duallink_transition_clk)
3982 lvdsmanufacturerindex++;
3983 } else if (chip_version < 0x30) {
3984 /* nv28 behaviour (off-chip encoder)
3986 * nv28 does a complex dance of first using byte 121 of
3987 * the EDID to choose the lvdsmanufacturerindex, then
3988 * later attempting to match the EDID manufacturer and
3989 * product IDs in a table (signature 'pidt' (panel id
3990 * table?)), setting an lvdsmanufacturerindex of 0 and
3991 * an fp strap of the match index (or 0xf if none)
3993 lvdsmanufacturerindex = 0;
3995 /* nv31, nv34 behaviour */
3996 lvdsmanufacturerindex = 0;
3997 if (pxclk >= bios->fp.duallink_transition_clk)
3998 lvdsmanufacturerindex = 2;
3999 if (pxclk >= 140000)
4000 lvdsmanufacturerindex = 3;
4004 * nvidia set the high nibble of (cr57=f, cr58) to
4005 * lvdsmanufacturerindex in this case; we don't
4008 case 0x30: /* NV4x */
4009 case 0x40: /* G80/G90 */
4010 lvdsmanufacturerindex = fpstrapping;
4013 NV_ERROR(dev, "LVDS table revision not currently supported\n");
4017 lvdsofs = bios->fp.xlated_entry = bios->fp.lvdsmanufacturerpointer + lth.headerlen + lth.recordlen * lvdsmanufacturerindex;
4018 switch (lth.lvds_ver) {
4020 bios->fp.power_off_for_reset = bios->data[lvdsofs] & 1;
4021 bios->fp.reset_after_pclk_change = bios->data[lvdsofs] & 2;
4022 bios->fp.dual_link = bios->data[lvdsofs] & 4;
4023 bios->fp.link_c_increment = bios->data[lvdsofs] & 8;
4024 *if_is_24bit = bios->data[lvdsofs] & 16;
4029 * No sign of the "power off for reset" or "reset for panel
4030 * on" bits, but it's safer to assume we should
4032 bios->fp.power_off_for_reset = true;
4033 bios->fp.reset_after_pclk_change = true;
4036 * It's ok lvdsofs is wrong for nv4x edid case; dual_link is
4037 * over-written, and if_is_24bit isn't used
4039 bios->fp.dual_link = bios->data[lvdsofs] & 1;
4040 bios->fp.if_is_24bit = bios->data[lvdsofs] & 2;
4041 bios->fp.strapless_is_24bit = bios->data[bios->fp.lvdsmanufacturerpointer + 4];
4042 bios->fp.duallink_transition_clk = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 5]) * 10;
4046 /* set dual_link flag for EDID case */
4047 if (pxclk && (chip_version < 0x25 || chip_version > 0x28))
4048 bios->fp.dual_link = (pxclk >= bios->fp.duallink_transition_clk);
4050 *dl = bios->fp.dual_link;
4055 /* BIT 'U'/'d' table encoder subtables have hashes matching them to
4056 * a particular set of encoders.
4058 * This function returns true if a particular DCB entry matches.
4061 bios_encoder_match(struct dcb_entry *dcb, u32 hash)
4063 if ((hash & 0x000000f0) != (dcb->location << 4))
4065 if ((hash & 0x0000000f) != dcb->type)
4067 if (!(hash & (dcb->or << 16)))
4070 switch (dcb->type) {
4074 if (hash & 0x00c00000) {
4075 if (!(hash & (dcb->sorconf.link << 22)))
4084 nouveau_bios_run_display_table(struct drm_device *dev, u16 type, int pclk,
4085 struct dcb_entry *dcbent, int crtc)
4088 * The display script table is located by the BIT 'U' table.
4090 * It contains an array of pointers to various tables describing
4091 * a particular output type. The first 32-bits of the output
4092 * tables contains similar information to a DCB entry, and is
4093 * used to decide whether that particular table is suitable for
4094 * the output you want to access.
4096 * The "record header length" field here seems to indicate the
4097 * offset of the first configuration entry in the output tables.
4098 * This is 10 on most cards I've seen, but 12 has been witnessed
4099 * on DP cards, and there's another script pointer within the
4102 * offset + 0 ( 8 bits): version
4103 * offset + 1 ( 8 bits): header length
4104 * offset + 2 ( 8 bits): record length
4105 * offset + 3 ( 8 bits): number of records
4106 * offset + 4 ( 8 bits): record header length
4107 * offset + 5 (16 bits): pointer to first output script table
4110 struct drm_nouveau_private *dev_priv = dev->dev_private;
4111 struct nvbios *bios = &dev_priv->vbios;
4112 uint8_t *table = &bios->data[bios->display.script_table_ptr];
4113 uint8_t *otable = NULL;
4117 if (!bios->display.script_table_ptr) {
4118 NV_ERROR(dev, "No pointer to output script table\n");
4123 * Nothing useful has been in any of the pre-2.0 tables I've seen,
4124 * so until they are, we really don't need to care.
4126 if (table[0] < 0x20)
4129 if (table[0] != 0x20 && table[0] != 0x21) {
4130 NV_ERROR(dev, "Output script table version 0x%02x unknown\n",
4136 * The output script tables describing a particular output type
4139 * offset + 0 (32 bits): output this table matches (hash of DCB)
4140 * offset + 4 ( 8 bits): unknown
4141 * offset + 5 ( 8 bits): number of configurations
4142 * offset + 6 (16 bits): pointer to some script
4143 * offset + 8 (16 bits): pointer to some script
4146 * offset + 10 : configuration 0
4149 * offset + 10 : pointer to some script
4150 * offset + 12 : configuration 0
4152 * Each config entry is as follows:
4154 * offset + 0 (16 bits): unknown, assumed to be a match value
4155 * offset + 2 (16 bits): pointer to script table (clock set?)
4156 * offset + 4 (16 bits): pointer to script table (reset?)
4158 * There doesn't appear to be a count value to say how many
4159 * entries exist in each script table, instead, a 0 value in
4160 * the first 16-bit word seems to indicate both the end of the
4161 * list and the default entry. The second 16-bit word in the
4162 * script tables is a pointer to the script to execute.
4165 NV_DEBUG_KMS(dev, "Searching for output entry for %d %d %d\n",
4166 dcbent->type, dcbent->location, dcbent->or);
4167 for (i = 0; i < table[3]; i++) {
4168 otable = ROMPTR(dev, table[table[1] + (i * table[2])]);
4169 if (otable && bios_encoder_match(dcbent, ROM32(otable[0])))
4174 NV_DEBUG_KMS(dev, "failed to match any output table\n");
4178 if (pclk < -2 || pclk > 0) {
4179 /* Try to find matching script table entry */
4180 for (i = 0; i < otable[5]; i++) {
4181 if (ROM16(otable[table[4] + i*6]) == type)
4185 if (i == otable[5]) {
4186 NV_ERROR(dev, "Table 0x%04x not found for %d/%d, "
4188 type, dcbent->type, dcbent->or);
4194 script = ROM16(otable[6]);
4196 NV_DEBUG_KMS(dev, "output script 0 not found\n");
4200 NV_DEBUG_KMS(dev, "0x%04X: parsing output script 0\n", script);
4201 nouveau_bios_run_init_table(dev, script, dcbent, crtc);
4204 script = ROM16(otable[8]);
4206 NV_DEBUG_KMS(dev, "output script 1 not found\n");
4210 NV_DEBUG_KMS(dev, "0x%04X: parsing output script 1\n", script);
4211 nouveau_bios_run_init_table(dev, script, dcbent, crtc);
4215 script = ROM16(otable[10]);
4219 NV_DEBUG_KMS(dev, "output script 2 not found\n");
4223 NV_DEBUG_KMS(dev, "0x%04X: parsing output script 2\n", script);
4224 nouveau_bios_run_init_table(dev, script, dcbent, crtc);
4227 script = ROM16(otable[table[4] + i*6 + 2]);
4229 script = clkcmptable(bios, script, pclk);
4231 NV_DEBUG_KMS(dev, "clock script 0 not found\n");
4235 NV_DEBUG_KMS(dev, "0x%04X: parsing clock script 0\n", script);
4236 nouveau_bios_run_init_table(dev, script, dcbent, crtc);
4239 script = ROM16(otable[table[4] + i*6 + 4]);
4241 script = clkcmptable(bios, script, -pclk);
4243 NV_DEBUG_KMS(dev, "clock script 1 not found\n");
4247 NV_DEBUG_KMS(dev, "0x%04X: parsing clock script 1\n", script);
4248 nouveau_bios_run_init_table(dev, script, dcbent, crtc);
4255 int run_tmds_table(struct drm_device *dev, struct dcb_entry *dcbent, int head, int pxclk)
4258 * the pxclk parameter is in kHz
4260 * This runs the TMDS regs setting code found on BIT bios cards
4262 * For ffs(or) == 1 use the first table, for ffs(or) == 2 and
4263 * ffs(or) == 3, use the second.
4266 struct drm_nouveau_private *dev_priv = dev->dev_private;
4267 struct nvbios *bios = &dev_priv->vbios;
4268 int cv = bios->chip_version;
4269 uint16_t clktable = 0, scriptptr;
4270 uint32_t sel_clk_binding, sel_clk;
4272 /* pre-nv17 off-chip tmds uses scripts, post nv17 doesn't */
4273 if (cv >= 0x17 && cv != 0x1a && cv != 0x20 &&
4274 dcbent->location != DCB_LOC_ON_CHIP)
4277 switch (ffs(dcbent->or)) {
4279 clktable = bios->tmds.output0_script_ptr;
4283 clktable = bios->tmds.output1_script_ptr;
4288 NV_ERROR(dev, "Pixel clock comparison table not found\n");
4292 scriptptr = clkcmptable(bios, clktable, pxclk);
4295 NV_ERROR(dev, "TMDS output init script not found\n");
4299 /* don't let script change pll->head binding */
4300 sel_clk_binding = bios_rd32(bios, NV_PRAMDAC_SEL_CLK) & 0x50000;
4301 run_digital_op_script(dev, scriptptr, dcbent, head, pxclk >= 165000);
4302 sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000;
4303 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding);
4308 struct pll_mapping {
4313 static struct pll_mapping nv04_pll_mapping[] = {
4314 { PLL_CORE , NV_PRAMDAC_NVPLL_COEFF },
4315 { PLL_MEMORY, NV_PRAMDAC_MPLL_COEFF },
4316 { PLL_VPLL0 , NV_PRAMDAC_VPLL_COEFF },
4317 { PLL_VPLL1 , NV_RAMDAC_VPLL2 },
4321 static struct pll_mapping nv40_pll_mapping[] = {
4322 { PLL_CORE , 0x004000 },
4323 { PLL_MEMORY, 0x004020 },
4324 { PLL_VPLL0 , NV_PRAMDAC_VPLL_COEFF },
4325 { PLL_VPLL1 , NV_RAMDAC_VPLL2 },
4329 static struct pll_mapping nv50_pll_mapping[] = {
4330 { PLL_CORE , 0x004028 },
4331 { PLL_SHADER, 0x004020 },
4332 { PLL_UNK03 , 0x004000 },
4333 { PLL_MEMORY, 0x004008 },
4334 { PLL_UNK40 , 0x00e810 },
4335 { PLL_UNK41 , 0x00e818 },
4336 { PLL_UNK42 , 0x00e824 },
4337 { PLL_VPLL0 , 0x614100 },
4338 { PLL_VPLL1 , 0x614900 },
4342 static struct pll_mapping nv84_pll_mapping[] = {
4343 { PLL_CORE , 0x004028 },
4344 { PLL_SHADER, 0x004020 },
4345 { PLL_MEMORY, 0x004008 },
4346 { PLL_VDEC , 0x004030 },
4347 { PLL_UNK41 , 0x00e818 },
4348 { PLL_VPLL0 , 0x614100 },
4349 { PLL_VPLL1 , 0x614900 },
4354 get_pll_register(struct drm_device *dev, enum pll_types type)
4356 struct drm_nouveau_private *dev_priv = dev->dev_private;
4357 struct nvbios *bios = &dev_priv->vbios;
4358 struct pll_mapping *map;
4361 if (dev_priv->card_type < NV_40)
4362 map = nv04_pll_mapping;
4364 if (dev_priv->card_type < NV_50)
4365 map = nv40_pll_mapping;
4367 u8 *plim = &bios->data[bios->pll_limit_tbl_ptr];
4369 if (plim[0] >= 0x30) {
4370 u8 *entry = plim + plim[1];
4371 for (i = 0; i < plim[3]; i++, entry += plim[2]) {
4372 if (entry[0] == type)
4373 return ROM32(entry[3]);
4379 if (dev_priv->chipset == 0x50)
4380 map = nv50_pll_mapping;
4382 map = nv84_pll_mapping;
4386 if (map->type == type)
4394 int get_pll_limits(struct drm_device *dev, uint32_t limit_match, struct pll_lims *pll_lim)
4399 * Version 0x10: NV30, NV31
4400 * One byte header (version), one record of 24 bytes
4401 * Version 0x11: NV36 - Not implemented
4402 * Seems to have same record style as 0x10, but 3 records rather than 1
4403 * Version 0x20: Found on Geforce 6 cards
4404 * Trivial 4 byte BIT header. 31 (0x1f) byte record length
4405 * Version 0x21: Found on Geforce 7, 8 and some Geforce 6 cards
4406 * 5 byte header, fifth byte of unknown purpose. 35 (0x23) byte record
4407 * length in general, some (integrated) have an extra configuration byte
4408 * Version 0x30: Found on Geforce 8, separates the register mapping
4409 * from the limits tables.
4412 struct drm_nouveau_private *dev_priv = dev->dev_private;
4413 struct nvbios *bios = &dev_priv->vbios;
4414 int cv = bios->chip_version, pllindex = 0;
4415 uint8_t pll_lim_ver = 0, headerlen = 0, recordlen = 0, entries = 0;
4416 uint32_t crystal_strap_mask, crystal_straps;
4418 if (!bios->pll_limit_tbl_ptr) {
4419 if (cv == 0x30 || cv == 0x31 || cv == 0x35 || cv == 0x36 ||
4421 NV_ERROR(dev, "Pointer to PLL limits table invalid\n");
4425 pll_lim_ver = bios->data[bios->pll_limit_tbl_ptr];
4427 crystal_strap_mask = 1 << 6;
4428 /* open coded dev->twoHeads test */
4429 if (cv > 0x10 && cv != 0x15 && cv != 0x1a && cv != 0x20)
4430 crystal_strap_mask |= 1 << 22;
4431 crystal_straps = nvReadEXTDEV(dev, NV_PEXTDEV_BOOT_0) &
4434 switch (pll_lim_ver) {
4436 * We use version 0 to indicate a pre limit table bios (single stage
4437 * pll) and load the hard coded limits instead.
4444 * Strictly v0x11 has 3 entries, but the last two don't seem
4456 headerlen = bios->data[bios->pll_limit_tbl_ptr + 1];
4457 recordlen = bios->data[bios->pll_limit_tbl_ptr + 2];
4458 entries = bios->data[bios->pll_limit_tbl_ptr + 3];
4461 NV_ERROR(dev, "PLL limits table revision 0x%X not currently "
4462 "supported\n", pll_lim_ver);
4466 /* initialize all members to zero */
4467 memset(pll_lim, 0, sizeof(struct pll_lims));
4469 /* if we were passed a type rather than a register, figure
4470 * out the register and store it
4472 if (limit_match > PLL_MAX)
4473 pll_lim->reg = limit_match;
4475 pll_lim->reg = get_pll_register(dev, limit_match);
4480 if (pll_lim_ver == 0x10 || pll_lim_ver == 0x11) {
4481 uint8_t *pll_rec = &bios->data[bios->pll_limit_tbl_ptr + headerlen + recordlen * pllindex];
4483 pll_lim->vco1.minfreq = ROM32(pll_rec[0]);
4484 pll_lim->vco1.maxfreq = ROM32(pll_rec[4]);
4485 pll_lim->vco2.minfreq = ROM32(pll_rec[8]);
4486 pll_lim->vco2.maxfreq = ROM32(pll_rec[12]);
4487 pll_lim->vco1.min_inputfreq = ROM32(pll_rec[16]);
4488 pll_lim->vco2.min_inputfreq = ROM32(pll_rec[20]);
4489 pll_lim->vco1.max_inputfreq = pll_lim->vco2.max_inputfreq = INT_MAX;
4491 /* these values taken from nv30/31/36 */
4492 pll_lim->vco1.min_n = 0x1;
4494 pll_lim->vco1.min_n = 0x5;
4495 pll_lim->vco1.max_n = 0xff;
4496 pll_lim->vco1.min_m = 0x1;
4497 pll_lim->vco1.max_m = 0xd;
4498 pll_lim->vco2.min_n = 0x4;
4500 * On nv30, 31, 36 (i.e. all cards with two stage PLLs with this
4501 * table version (apart from nv35)), N2 is compared to
4502 * maxN2 (0x46) and 10 * maxM2 (0x4), so set maxN2 to 0x28 and
4505 pll_lim->vco2.max_n = 0x28;
4506 if (cv == 0x30 || cv == 0x35)
4507 /* only 5 bits available for N2 on nv30/35 */
4508 pll_lim->vco2.max_n = 0x1f;
4509 pll_lim->vco2.min_m = 0x1;
4510 pll_lim->vco2.max_m = 0x4;
4511 pll_lim->max_log2p = 0x7;
4512 pll_lim->max_usable_log2p = 0x6;
4513 } else if (pll_lim_ver == 0x20 || pll_lim_ver == 0x21) {
4514 uint16_t plloffs = bios->pll_limit_tbl_ptr + headerlen;
4519 * First entry is default match, if nothing better. warn if
4522 if (ROM32(bios->data[plloffs]))
4523 NV_WARN(dev, "Default PLL limit entry has non-zero "
4524 "register field\n");
4526 for (i = 1; i < entries; i++)
4527 if (ROM32(bios->data[plloffs + recordlen * i]) == pll_lim->reg) {
4532 if ((dev_priv->card_type >= NV_50) && (pllindex == 0)) {
4533 NV_ERROR(dev, "Register 0x%08x not found in PLL "
4534 "limits table", pll_lim->reg);
4538 pll_rec = &bios->data[plloffs + recordlen * pllindex];
4540 BIOSLOG(bios, "Loading PLL limits for reg 0x%08x\n",
4541 pllindex ? pll_lim->reg : 0);
4544 * Frequencies are stored in tables in MHz, kHz are more
4545 * useful, so we convert.
4548 /* What output frequencies can each VCO generate? */
4549 pll_lim->vco1.minfreq = ROM16(pll_rec[4]) * 1000;
4550 pll_lim->vco1.maxfreq = ROM16(pll_rec[6]) * 1000;
4551 pll_lim->vco2.minfreq = ROM16(pll_rec[8]) * 1000;
4552 pll_lim->vco2.maxfreq = ROM16(pll_rec[10]) * 1000;
4554 /* What input frequencies they accept (past the m-divider)? */
4555 pll_lim->vco1.min_inputfreq = ROM16(pll_rec[12]) * 1000;
4556 pll_lim->vco2.min_inputfreq = ROM16(pll_rec[14]) * 1000;
4557 pll_lim->vco1.max_inputfreq = ROM16(pll_rec[16]) * 1000;
4558 pll_lim->vco2.max_inputfreq = ROM16(pll_rec[18]) * 1000;
4560 /* What values are accepted as multiplier and divider? */
4561 pll_lim->vco1.min_n = pll_rec[20];
4562 pll_lim->vco1.max_n = pll_rec[21];
4563 pll_lim->vco1.min_m = pll_rec[22];
4564 pll_lim->vco1.max_m = pll_rec[23];
4565 pll_lim->vco2.min_n = pll_rec[24];
4566 pll_lim->vco2.max_n = pll_rec[25];
4567 pll_lim->vco2.min_m = pll_rec[26];
4568 pll_lim->vco2.max_m = pll_rec[27];
4570 pll_lim->max_usable_log2p = pll_lim->max_log2p = pll_rec[29];
4571 if (pll_lim->max_log2p > 0x7)
4572 /* pll decoding in nv_hw.c assumes never > 7 */
4573 NV_WARN(dev, "Max log2 P value greater than 7 (%d)\n",
4574 pll_lim->max_log2p);
4576 pll_lim->max_usable_log2p = 0x6;
4577 pll_lim->log2p_bias = pll_rec[30];
4579 if (recordlen > 0x22)
4580 pll_lim->refclk = ROM32(pll_rec[31]);
4582 if (recordlen > 0x23 && pll_rec[35])
4584 "Bits set in PLL configuration byte (%x)\n",
4587 /* C51 special not seen elsewhere */
4588 if (cv == 0x51 && !pll_lim->refclk) {
4589 uint32_t sel_clk = bios_rd32(bios, NV_PRAMDAC_SEL_CLK);
4591 if ((pll_lim->reg == NV_PRAMDAC_VPLL_COEFF && sel_clk & 0x20) ||
4592 (pll_lim->reg == NV_RAMDAC_VPLL2 && sel_clk & 0x80)) {
4593 if (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_CHIP_ID_INDEX) < 0xa3)
4594 pll_lim->refclk = 200000;
4596 pll_lim->refclk = 25000;
4599 } else if (pll_lim_ver == 0x30) { /* ver 0x30 */
4600 uint8_t *entry = &bios->data[bios->pll_limit_tbl_ptr + headerlen];
4601 uint8_t *record = NULL;
4604 BIOSLOG(bios, "Loading PLL limits for register 0x%08x\n",
4607 for (i = 0; i < entries; i++, entry += recordlen) {
4608 if (ROM32(entry[3]) == pll_lim->reg) {
4609 record = &bios->data[ROM16(entry[1])];
4615 NV_ERROR(dev, "Register 0x%08x not found in PLL "
4616 "limits table", pll_lim->reg);
4620 pll_lim->vco1.minfreq = ROM16(record[0]) * 1000;
4621 pll_lim->vco1.maxfreq = ROM16(record[2]) * 1000;
4622 pll_lim->vco2.minfreq = ROM16(record[4]) * 1000;
4623 pll_lim->vco2.maxfreq = ROM16(record[6]) * 1000;
4624 pll_lim->vco1.min_inputfreq = ROM16(record[8]) * 1000;
4625 pll_lim->vco2.min_inputfreq = ROM16(record[10]) * 1000;
4626 pll_lim->vco1.max_inputfreq = ROM16(record[12]) * 1000;
4627 pll_lim->vco2.max_inputfreq = ROM16(record[14]) * 1000;
4628 pll_lim->vco1.min_n = record[16];
4629 pll_lim->vco1.max_n = record[17];
4630 pll_lim->vco1.min_m = record[18];
4631 pll_lim->vco1.max_m = record[19];
4632 pll_lim->vco2.min_n = record[20];
4633 pll_lim->vco2.max_n = record[21];
4634 pll_lim->vco2.min_m = record[22];
4635 pll_lim->vco2.max_m = record[23];
4636 pll_lim->max_usable_log2p = pll_lim->max_log2p = record[25];
4637 pll_lim->log2p_bias = record[27];
4638 pll_lim->refclk = ROM32(record[28]);
4639 } else if (pll_lim_ver) { /* ver 0x40 */
4640 uint8_t *entry = &bios->data[bios->pll_limit_tbl_ptr + headerlen];
4641 uint8_t *record = NULL;
4644 BIOSLOG(bios, "Loading PLL limits for register 0x%08x\n",
4647 for (i = 0; i < entries; i++, entry += recordlen) {
4648 if (ROM32(entry[3]) == pll_lim->reg) {
4649 record = &bios->data[ROM16(entry[1])];
4655 NV_ERROR(dev, "Register 0x%08x not found in PLL "
4656 "limits table", pll_lim->reg);
4660 pll_lim->vco1.minfreq = ROM16(record[0]) * 1000;
4661 pll_lim->vco1.maxfreq = ROM16(record[2]) * 1000;
4662 pll_lim->vco1.min_inputfreq = ROM16(record[4]) * 1000;
4663 pll_lim->vco1.max_inputfreq = ROM16(record[6]) * 1000;
4664 pll_lim->vco1.min_m = record[8];
4665 pll_lim->vco1.max_m = record[9];
4666 pll_lim->vco1.min_n = record[10];
4667 pll_lim->vco1.max_n = record[11];
4668 pll_lim->min_p = record[12];
4669 pll_lim->max_p = record[13];
4670 pll_lim->refclk = ROM16(entry[9]) * 1000;
4674 * By now any valid limit table ought to have set a max frequency for
4675 * vco1, so if it's zero it's either a pre limit table bios, or one
4676 * with an empty limit table (seen on nv18)
4678 if (!pll_lim->vco1.maxfreq) {
4679 pll_lim->vco1.minfreq = bios->fminvco;
4680 pll_lim->vco1.maxfreq = bios->fmaxvco;
4681 pll_lim->vco1.min_inputfreq = 0;
4682 pll_lim->vco1.max_inputfreq = INT_MAX;
4683 pll_lim->vco1.min_n = 0x1;
4684 pll_lim->vco1.max_n = 0xff;
4685 pll_lim->vco1.min_m = 0x1;
4686 if (crystal_straps == 0) {
4687 /* nv05 does this, nv11 doesn't, nv10 unknown */
4689 pll_lim->vco1.min_m = 0x7;
4690 pll_lim->vco1.max_m = 0xd;
4693 pll_lim->vco1.min_m = 0x8;
4694 pll_lim->vco1.max_m = 0xe;
4696 if (cv < 0x17 || cv == 0x1a || cv == 0x20)
4697 pll_lim->max_log2p = 4;
4699 pll_lim->max_log2p = 5;
4700 pll_lim->max_usable_log2p = pll_lim->max_log2p;
4703 if (!pll_lim->refclk)
4704 switch (crystal_straps) {
4706 pll_lim->refclk = 13500;
4709 pll_lim->refclk = 14318;
4712 pll_lim->refclk = 27000;
4714 case (1 << 22 | 1 << 6):
4715 pll_lim->refclk = 25000;
4719 NV_DEBUG(dev, "pll.vco1.minfreq: %d\n", pll_lim->vco1.minfreq);
4720 NV_DEBUG(dev, "pll.vco1.maxfreq: %d\n", pll_lim->vco1.maxfreq);
4721 NV_DEBUG(dev, "pll.vco1.min_inputfreq: %d\n", pll_lim->vco1.min_inputfreq);
4722 NV_DEBUG(dev, "pll.vco1.max_inputfreq: %d\n", pll_lim->vco1.max_inputfreq);
4723 NV_DEBUG(dev, "pll.vco1.min_n: %d\n", pll_lim->vco1.min_n);
4724 NV_DEBUG(dev, "pll.vco1.max_n: %d\n", pll_lim->vco1.max_n);
4725 NV_DEBUG(dev, "pll.vco1.min_m: %d\n", pll_lim->vco1.min_m);
4726 NV_DEBUG(dev, "pll.vco1.max_m: %d\n", pll_lim->vco1.max_m);
4727 if (pll_lim->vco2.maxfreq) {
4728 NV_DEBUG(dev, "pll.vco2.minfreq: %d\n", pll_lim->vco2.minfreq);
4729 NV_DEBUG(dev, "pll.vco2.maxfreq: %d\n", pll_lim->vco2.maxfreq);
4730 NV_DEBUG(dev, "pll.vco2.min_inputfreq: %d\n", pll_lim->vco2.min_inputfreq);
4731 NV_DEBUG(dev, "pll.vco2.max_inputfreq: %d\n", pll_lim->vco2.max_inputfreq);
4732 NV_DEBUG(dev, "pll.vco2.min_n: %d\n", pll_lim->vco2.min_n);
4733 NV_DEBUG(dev, "pll.vco2.max_n: %d\n", pll_lim->vco2.max_n);
4734 NV_DEBUG(dev, "pll.vco2.min_m: %d\n", pll_lim->vco2.min_m);
4735 NV_DEBUG(dev, "pll.vco2.max_m: %d\n", pll_lim->vco2.max_m);
4737 if (!pll_lim->max_p) {
4738 NV_DEBUG(dev, "pll.max_log2p: %d\n", pll_lim->max_log2p);
4739 NV_DEBUG(dev, "pll.log2p_bias: %d\n", pll_lim->log2p_bias);
4741 NV_DEBUG(dev, "pll.min_p: %d\n", pll_lim->min_p);
4742 NV_DEBUG(dev, "pll.max_p: %d\n", pll_lim->max_p);
4744 NV_DEBUG(dev, "pll.refclk: %d\n", pll_lim->refclk);
4749 static void parse_bios_version(struct drm_device *dev, struct nvbios *bios, uint16_t offset)
4752 * offset + 0 (8 bits): Micro version
4753 * offset + 1 (8 bits): Minor version
4754 * offset + 2 (8 bits): Chip version
4755 * offset + 3 (8 bits): Major version
4758 bios->major_version = bios->data[offset + 3];
4759 bios->chip_version = bios->data[offset + 2];
4760 NV_TRACE(dev, "Bios version %02x.%02x.%02x.%02x\n",
4761 bios->data[offset + 3], bios->data[offset + 2],
4762 bios->data[offset + 1], bios->data[offset]);
4765 static void parse_script_table_pointers(struct nvbios *bios, uint16_t offset)
4768 * Parses the init table segment for pointers used in script execution.
4770 * offset + 0 (16 bits): init script tables pointer
4771 * offset + 2 (16 bits): macro index table pointer
4772 * offset + 4 (16 bits): macro table pointer
4773 * offset + 6 (16 bits): condition table pointer
4774 * offset + 8 (16 bits): io condition table pointer
4775 * offset + 10 (16 bits): io flag condition table pointer
4776 * offset + 12 (16 bits): init function table pointer
4779 bios->init_script_tbls_ptr = ROM16(bios->data[offset]);
4780 bios->macro_index_tbl_ptr = ROM16(bios->data[offset + 2]);
4781 bios->macro_tbl_ptr = ROM16(bios->data[offset + 4]);
4782 bios->condition_tbl_ptr = ROM16(bios->data[offset + 6]);
4783 bios->io_condition_tbl_ptr = ROM16(bios->data[offset + 8]);
4784 bios->io_flag_condition_tbl_ptr = ROM16(bios->data[offset + 10]);
4785 bios->init_function_tbl_ptr = ROM16(bios->data[offset + 12]);
4788 static int parse_bit_A_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
4791 * Parses the load detect values for g80 cards.
4793 * offset + 0 (16 bits): loadval table pointer
4796 uint16_t load_table_ptr;
4797 uint8_t version, headerlen, entrylen, num_entries;
4799 if (bitentry->length != 3) {
4800 NV_ERROR(dev, "Do not understand BIT A table\n");
4804 load_table_ptr = ROM16(bios->data[bitentry->offset]);
4806 if (load_table_ptr == 0x0) {
4807 NV_DEBUG(dev, "Pointer to BIT loadval table invalid\n");
4811 version = bios->data[load_table_ptr];
4813 if (version != 0x10) {
4814 NV_ERROR(dev, "BIT loadval table version %d.%d not supported\n",
4815 version >> 4, version & 0xF);
4819 headerlen = bios->data[load_table_ptr + 1];
4820 entrylen = bios->data[load_table_ptr + 2];
4821 num_entries = bios->data[load_table_ptr + 3];
4823 if (headerlen != 4 || entrylen != 4 || num_entries != 2) {
4824 NV_ERROR(dev, "Do not understand BIT loadval table\n");
4828 /* First entry is normal dac, 2nd tv-out perhaps? */
4829 bios->dactestval = ROM32(bios->data[load_table_ptr + headerlen]) & 0x3ff;
4834 static int parse_bit_C_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
4837 * offset + 8 (16 bits): PLL limits table pointer
4839 * There's more in here, but that's unknown.
4842 if (bitentry->length < 10) {
4843 NV_ERROR(dev, "Do not understand BIT C table\n");
4847 bios->pll_limit_tbl_ptr = ROM16(bios->data[bitentry->offset + 8]);
4852 static int parse_bit_display_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
4855 * Parses the flat panel table segment that the bit entry points to.
4856 * Starting at bitentry->offset:
4858 * offset + 0 (16 bits): ??? table pointer - seems to have 18 byte
4859 * records beginning with a freq.
4860 * offset + 2 (16 bits): mode table pointer
4863 if (bitentry->length != 4) {
4864 NV_ERROR(dev, "Do not understand BIT display table\n");
4868 bios->fp.fptablepointer = ROM16(bios->data[bitentry->offset + 2]);
4873 static int parse_bit_init_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
4876 * Parses the init table segment that the bit entry points to.
4878 * See parse_script_table_pointers for layout
4881 if (bitentry->length < 14) {
4882 NV_ERROR(dev, "Do not understand init table\n");
4886 parse_script_table_pointers(bios, bitentry->offset);
4888 if (bitentry->length >= 16)
4889 bios->some_script_ptr = ROM16(bios->data[bitentry->offset + 14]);
4890 if (bitentry->length >= 18)
4891 bios->init96_tbl_ptr = ROM16(bios->data[bitentry->offset + 16]);
4896 static int parse_bit_i_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
4899 * BIT 'i' (info?) table
4901 * offset + 0 (32 bits): BIOS version dword (as in B table)
4902 * offset + 5 (8 bits): BIOS feature byte (same as for BMP?)
4903 * offset + 13 (16 bits): pointer to table containing DAC load
4904 * detection comparison values
4906 * There's other things in the table, purpose unknown
4909 uint16_t daccmpoffset;
4910 uint8_t dacver, dacheaderlen;
4912 if (bitentry->length < 6) {
4913 NV_ERROR(dev, "BIT i table too short for needed information\n");
4917 parse_bios_version(dev, bios, bitentry->offset);
4920 * bit 4 seems to indicate a mobile bios (doesn't suffer from BMP's
4921 * Quadro identity crisis), other bits possibly as for BMP feature byte
4923 bios->feature_byte = bios->data[bitentry->offset + 5];
4924 bios->is_mobile = bios->feature_byte & FEATURE_MOBILE;
4926 if (bitentry->length < 15) {
4927 NV_WARN(dev, "BIT i table not long enough for DAC load "
4928 "detection comparison table\n");
4932 daccmpoffset = ROM16(bios->data[bitentry->offset + 13]);
4934 /* doesn't exist on g80 */
4939 * The first value in the table, following the header, is the
4940 * comparison value, the second entry is a comparison value for
4941 * TV load detection.
4944 dacver = bios->data[daccmpoffset];
4945 dacheaderlen = bios->data[daccmpoffset + 1];
4947 if (dacver != 0x00 && dacver != 0x10) {
4948 NV_WARN(dev, "DAC load detection comparison table version "
4949 "%d.%d not known\n", dacver >> 4, dacver & 0xf);
4953 bios->dactestval = ROM32(bios->data[daccmpoffset + dacheaderlen]);
4954 bios->tvdactestval = ROM32(bios->data[daccmpoffset + dacheaderlen + 4]);
4959 static int parse_bit_lvds_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
4962 * Parses the LVDS table segment that the bit entry points to.
4963 * Starting at bitentry->offset:
4965 * offset + 0 (16 bits): LVDS strap xlate table pointer
4968 if (bitentry->length != 2) {
4969 NV_ERROR(dev, "Do not understand BIT LVDS table\n");
4974 * No idea if it's still called the LVDS manufacturer table, but
4975 * the concept's close enough.
4977 bios->fp.lvdsmanufacturerpointer = ROM16(bios->data[bitentry->offset]);
4983 parse_bit_M_tbl_entry(struct drm_device *dev, struct nvbios *bios,
4984 struct bit_entry *bitentry)
4987 * offset + 2 (8 bits): number of options in an
4988 * INIT_RAM_RESTRICT_ZM_REG_GROUP opcode option set
4989 * offset + 3 (16 bits): pointer to strap xlate table for RAM
4990 * restrict option selection
4992 * There's a bunch of bits in this table other than the RAM restrict
4993 * stuff that we don't use - their use currently unknown
4997 * Older bios versions don't have a sufficiently long table for
5000 if (bitentry->length < 0x5)
5003 if (bitentry->version < 2) {
5004 bios->ram_restrict_group_count = bios->data[bitentry->offset + 2];
5005 bios->ram_restrict_tbl_ptr = ROM16(bios->data[bitentry->offset + 3]);
5007 bios->ram_restrict_group_count = bios->data[bitentry->offset + 0];
5008 bios->ram_restrict_tbl_ptr = ROM16(bios->data[bitentry->offset + 1]);
5014 static int parse_bit_tmds_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
5017 * Parses the pointer to the TMDS table
5019 * Starting at bitentry->offset:
5021 * offset + 0 (16 bits): TMDS table pointer
5023 * The TMDS table is typically found just before the DCB table, with a
5024 * characteristic signature of 0x11,0x13 (1.1 being version, 0x13 being
5027 * At offset +7 is a pointer to a script, which I don't know how to
5029 * At offset +9 is a pointer to another script, likewise
5030 * Offset +11 has a pointer to a table where the first word is a pxclk
5031 * frequency and the second word a pointer to a script, which should be
5032 * run if the comparison pxclk frequency is less than the pxclk desired.
5033 * This repeats for decreasing comparison frequencies
5034 * Offset +13 has a pointer to a similar table
5035 * The selection of table (and possibly +7/+9 script) is dictated by
5036 * "or" from the DCB.
5039 uint16_t tmdstableptr, script1, script2;
5041 if (bitentry->length != 2) {
5042 NV_ERROR(dev, "Do not understand BIT TMDS table\n");
5046 tmdstableptr = ROM16(bios->data[bitentry->offset]);
5047 if (!tmdstableptr) {
5048 NV_ERROR(dev, "Pointer to TMDS table invalid\n");
5052 NV_INFO(dev, "TMDS table version %d.%d\n",
5053 bios->data[tmdstableptr] >> 4, bios->data[tmdstableptr] & 0xf);
5055 /* nv50+ has v2.0, but we don't parse it atm */
5056 if (bios->data[tmdstableptr] != 0x11)
5060 * These two scripts are odd: they don't seem to get run even when
5061 * they are not stubbed.
5063 script1 = ROM16(bios->data[tmdstableptr + 7]);
5064 script2 = ROM16(bios->data[tmdstableptr + 9]);
5065 if (bios->data[script1] != 'q' || bios->data[script2] != 'q')
5066 NV_WARN(dev, "TMDS table script pointers not stubbed\n");
5068 bios->tmds.output0_script_ptr = ROM16(bios->data[tmdstableptr + 11]);
5069 bios->tmds.output1_script_ptr = ROM16(bios->data[tmdstableptr + 13]);
5075 parse_bit_U_tbl_entry(struct drm_device *dev, struct nvbios *bios,
5076 struct bit_entry *bitentry)
5079 * Parses the pointer to the G80 output script tables
5081 * Starting at bitentry->offset:
5083 * offset + 0 (16 bits): output script table pointer
5086 uint16_t outputscripttableptr;
5088 if (bitentry->length != 3) {
5089 NV_ERROR(dev, "Do not understand BIT U table\n");
5093 outputscripttableptr = ROM16(bios->data[bitentry->offset]);
5094 bios->display.script_table_ptr = outputscripttableptr;
5100 int (* const parse_fn)(struct drm_device *, struct nvbios *, struct bit_entry *);
5103 #define BIT_TABLE(id, funcid) ((struct bit_table){ id, parse_bit_##funcid##_tbl_entry })
5106 bit_table(struct drm_device *dev, u8 id, struct bit_entry *bit)
5108 struct drm_nouveau_private *dev_priv = dev->dev_private;
5109 struct nvbios *bios = &dev_priv->vbios;
5112 if (bios->type != NVBIOS_BIT)
5115 entries = bios->data[bios->offset + 10];
5116 entry = &bios->data[bios->offset + 12];
5118 if (entry[0] == id) {
5120 bit->version = entry[1];
5121 bit->length = ROM16(entry[2]);
5122 bit->offset = ROM16(entry[4]);
5123 bit->data = ROMPTR(dev, entry[4]);
5127 entry += bios->data[bios->offset + 9];
5134 parse_bit_table(struct nvbios *bios, const uint16_t bitoffset,
5135 struct bit_table *table)
5137 struct drm_device *dev = bios->dev;
5138 struct bit_entry bitentry;
5140 if (bit_table(dev, table->id, &bitentry) == 0)
5141 return table->parse_fn(dev, bios, &bitentry);
5143 NV_INFO(dev, "BIT table '%c' not found\n", table->id);
5148 parse_bit_structure(struct nvbios *bios, const uint16_t bitoffset)
5153 * The only restriction on parsing order currently is having 'i' first
5154 * for use of bios->*_version or bios->feature_byte while parsing;
5155 * functions shouldn't be actually *doing* anything apart from pulling
5156 * data from the image into the bios struct, thus no interdependencies
5158 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('i', i));
5159 if (ret) /* info? */
5161 if (bios->major_version >= 0x60) /* g80+ */
5162 parse_bit_table(bios, bitoffset, &BIT_TABLE('A', A));
5163 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('C', C));
5166 parse_bit_table(bios, bitoffset, &BIT_TABLE('D', display));
5167 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('I', init));
5170 parse_bit_table(bios, bitoffset, &BIT_TABLE('M', M)); /* memory? */
5171 parse_bit_table(bios, bitoffset, &BIT_TABLE('L', lvds));
5172 parse_bit_table(bios, bitoffset, &BIT_TABLE('T', tmds));
5173 parse_bit_table(bios, bitoffset, &BIT_TABLE('U', U));
5178 static int parse_bmp_structure(struct drm_device *dev, struct nvbios *bios, unsigned int offset)
5181 * Parses the BMP structure for useful things, but does not act on them
5183 * offset + 5: BMP major version
5184 * offset + 6: BMP minor version
5185 * offset + 9: BMP feature byte
5186 * offset + 10: BCD encoded BIOS version
5188 * offset + 18: init script table pointer (for bios versions < 5.10h)
5189 * offset + 20: extra init script table pointer (for bios
5192 * offset + 24: memory init table pointer (used on early bios versions)
5193 * offset + 26: SDR memory sequencing setup data table
5194 * offset + 28: DDR memory sequencing setup data table
5196 * offset + 54: index of I2C CRTC pair to use for CRT output
5197 * offset + 55: index of I2C CRTC pair to use for TV output
5198 * offset + 56: index of I2C CRTC pair to use for flat panel output
5199 * offset + 58: write CRTC index for I2C pair 0
5200 * offset + 59: read CRTC index for I2C pair 0
5201 * offset + 60: write CRTC index for I2C pair 1
5202 * offset + 61: read CRTC index for I2C pair 1
5204 * offset + 67: maximum internal PLL frequency (single stage PLL)
5205 * offset + 71: minimum internal PLL frequency (single stage PLL)
5207 * offset + 75: script table pointers, as described in
5208 * parse_script_table_pointers
5210 * offset + 89: TMDS single link output A table pointer
5211 * offset + 91: TMDS single link output B table pointer
5212 * offset + 95: LVDS single link output A table pointer
5213 * offset + 105: flat panel timings table pointer
5214 * offset + 107: flat panel strapping translation table pointer
5215 * offset + 117: LVDS manufacturer panel config table pointer
5216 * offset + 119: LVDS manufacturer strapping translation table pointer
5218 * offset + 142: PLL limits table pointer
5220 * offset + 156: minimum pixel clock for LVDS dual link
5223 uint8_t *bmp = &bios->data[offset], bmp_version_major, bmp_version_minor;
5225 uint16_t legacy_scripts_offset, legacy_i2c_offset;
5227 /* load needed defaults in case we can't parse this info */
5228 bios->digital_min_front_porch = 0x4b;
5229 bios->fmaxvco = 256000;
5230 bios->fminvco = 128000;
5231 bios->fp.duallink_transition_clk = 90000;
5233 bmp_version_major = bmp[5];
5234 bmp_version_minor = bmp[6];
5236 NV_TRACE(dev, "BMP version %d.%d\n",
5237 bmp_version_major, bmp_version_minor);
5240 * Make sure that 0x36 is blank and can't be mistaken for a DCB
5241 * pointer on early versions
5243 if (bmp_version_major < 5)
5244 *(uint16_t *)&bios->data[0x36] = 0;
5247 * Seems that the minor version was 1 for all major versions prior
5248 * to 5. Version 6 could theoretically exist, but I suspect BIT
5251 if ((bmp_version_major < 5 && bmp_version_minor != 1) || bmp_version_major > 5) {
5252 NV_ERROR(dev, "You have an unsupported BMP version. "
5253 "Please send in your bios\n");
5257 if (bmp_version_major == 0)
5258 /* nothing that's currently useful in this version */
5260 else if (bmp_version_major == 1)
5261 bmplength = 44; /* exact for 1.01 */
5262 else if (bmp_version_major == 2)
5263 bmplength = 48; /* exact for 2.01 */
5264 else if (bmp_version_major == 3)
5266 /* guessed - mem init tables added in this version */
5267 else if (bmp_version_major == 4 || bmp_version_minor < 0x1)
5268 /* don't know if 5.0 exists... */
5270 /* guessed - BMP I2C indices added in version 4*/
5271 else if (bmp_version_minor < 0x6)
5272 bmplength = 67; /* exact for 5.01 */
5273 else if (bmp_version_minor < 0x10)
5274 bmplength = 75; /* exact for 5.06 */
5275 else if (bmp_version_minor == 0x10)
5276 bmplength = 89; /* exact for 5.10h */
5277 else if (bmp_version_minor < 0x14)
5278 bmplength = 118; /* exact for 5.11h */
5279 else if (bmp_version_minor < 0x24)
5281 * Not sure of version where pll limits came in;
5282 * certainly exist by 0x24 though.
5284 /* length not exact: this is long enough to get lvds members */
5286 else if (bmp_version_minor < 0x27)
5288 * Length not exact: this is long enough to get pll limit
5294 * Length not exact: this is long enough to get dual link
5300 if (nv_cksum(bmp, 8)) {
5301 NV_ERROR(dev, "Bad BMP checksum\n");
5306 * Bit 4 seems to indicate either a mobile bios or a quadro card --
5307 * mobile behaviour consistent (nv11+), quadro only seen nv18gl-nv36gl
5308 * (not nv10gl), bit 5 that the flat panel tables are present, and
5311 bios->feature_byte = bmp[9];
5313 parse_bios_version(dev, bios, offset + 10);
5315 if (bmp_version_major < 5 || bmp_version_minor < 0x10)
5316 bios->old_style_init = true;
5317 legacy_scripts_offset = 18;
5318 if (bmp_version_major < 2)
5319 legacy_scripts_offset -= 4;
5320 bios->init_script_tbls_ptr = ROM16(bmp[legacy_scripts_offset]);
5321 bios->extra_init_script_tbl_ptr = ROM16(bmp[legacy_scripts_offset + 2]);
5323 if (bmp_version_major > 2) { /* appears in BMP 3 */
5324 bios->legacy.mem_init_tbl_ptr = ROM16(bmp[24]);
5325 bios->legacy.sdr_seq_tbl_ptr = ROM16(bmp[26]);
5326 bios->legacy.ddr_seq_tbl_ptr = ROM16(bmp[28]);
5329 legacy_i2c_offset = 0x48; /* BMP version 2 & 3 */
5331 legacy_i2c_offset = offset + 54;
5332 bios->legacy.i2c_indices.crt = bios->data[legacy_i2c_offset];
5333 bios->legacy.i2c_indices.tv = bios->data[legacy_i2c_offset + 1];
5334 bios->legacy.i2c_indices.panel = bios->data[legacy_i2c_offset + 2];
5336 if (bmplength > 74) {
5337 bios->fmaxvco = ROM32(bmp[67]);
5338 bios->fminvco = ROM32(bmp[71]);
5341 parse_script_table_pointers(bios, offset + 75);
5342 if (bmplength > 94) {
5343 bios->tmds.output0_script_ptr = ROM16(bmp[89]);
5344 bios->tmds.output1_script_ptr = ROM16(bmp[91]);
5346 * Never observed in use with lvds scripts, but is reused for
5347 * 18/24 bit panel interface default for EDID equipped panels
5348 * (if_is_24bit not set directly to avoid any oscillation).
5350 bios->legacy.lvds_single_a_script_ptr = ROM16(bmp[95]);
5352 if (bmplength > 108) {
5353 bios->fp.fptablepointer = ROM16(bmp[105]);
5354 bios->fp.fpxlatetableptr = ROM16(bmp[107]);
5355 bios->fp.xlatwidth = 1;
5357 if (bmplength > 120) {
5358 bios->fp.lvdsmanufacturerpointer = ROM16(bmp[117]);
5359 bios->fp.fpxlatemanufacturertableptr = ROM16(bmp[119]);
5361 if (bmplength > 143)
5362 bios->pll_limit_tbl_ptr = ROM16(bmp[142]);
5364 if (bmplength > 157)
5365 bios->fp.duallink_transition_clk = ROM16(bmp[156]) * 10;
5370 static uint16_t findstr(uint8_t *data, int n, const uint8_t *str, int len)
5374 for (i = 0; i <= (n - len); i++) {
5375 for (j = 0; j < len; j++)
5376 if (data[i + j] != str[j])
5386 olddcb_table(struct drm_device *dev)
5388 struct drm_nouveau_private *dev_priv = dev->dev_private;
5391 if (dev_priv->card_type > NV_04)
5392 dcb = ROMPTR(dev, dev_priv->vbios.data[0x36]);
5394 NV_WARNONCE(dev, "No DCB data found in VBIOS\n");
5398 if (dcb[0] >= 0x41) {
5399 NV_WARNONCE(dev, "DCB version 0x%02x unknown\n", dcb[0]);
5402 if (dcb[0] >= 0x30) {
5403 if (ROM32(dcb[6]) == 0x4edcbdcb)
5406 if (dcb[0] >= 0x20) {
5407 if (ROM32(dcb[4]) == 0x4edcbdcb)
5410 if (dcb[0] >= 0x15) {
5411 if (!memcmp(&dcb[-7], "DEV_REC", 7))
5415 * v1.4 (some NV15/16, NV11+) seems the same as v1.5, but
5416 * always has the same single (crt) entry, even when tv-out
5417 * present, so the conclusion is this version cannot really
5420 * v1.2 tables (some NV6/10, and NV15+) normally have the
5421 * same 5 entries, which are not specific to the card and so
5424 * v1.2 does have an I2C table that read_dcb_i2c_table can
5425 * handle, but cards exist (nv11 in #14821) with a bad i2c
5426 * table pointer, so use the indices parsed in
5427 * parse_bmp_structure.
5429 * v1.1 (NV5+, maybe some NV4) is entirely unhelpful
5431 NV_WARNONCE(dev, "No useful DCB data in VBIOS\n");
5435 NV_WARNONCE(dev, "DCB header validation failed\n");
5440 olddcb_outp(struct drm_device *dev, u8 idx)
5442 u8 *dcb = olddcb_table(dev);
5443 if (dcb && dcb[0] >= 0x30) {
5445 return dcb + dcb[1] + (idx * dcb[3]);
5447 if (dcb && dcb[0] >= 0x20) {
5448 u8 *i2c = ROMPTR(dev, dcb[2]);
5449 u8 *ent = dcb + 8 + (idx * 8);
5450 if (i2c && ent < i2c)
5453 if (dcb && dcb[0] >= 0x15) {
5454 u8 *i2c = ROMPTR(dev, dcb[2]);
5455 u8 *ent = dcb + 4 + (idx * 10);
5456 if (i2c && ent < i2c)
5464 olddcb_outp_foreach(struct drm_device *dev, void *data,
5465 int (*exec)(struct drm_device *, void *, int idx, u8 *outp))
5469 while ((outp = olddcb_outp(dev, ++idx))) {
5470 if (ROM32(outp[0]) == 0x00000000)
5471 break; /* seen on an NV11 with DCB v1.5 */
5472 if (ROM32(outp[0]) == 0xffffffff)
5473 break; /* seen on an NV17 with DCB v2.0 */
5475 if ((outp[0] & 0x0f) == OUTPUT_UNUSED)
5477 if ((outp[0] & 0x0f) == OUTPUT_EOL)
5480 ret = exec(dev, data, idx, outp);
5489 dcb_conntab(struct drm_device *dev)
5491 u8 *dcb = olddcb_table(dev);
5492 if (dcb && dcb[0] >= 0x30 && dcb[1] >= 0x16) {
5493 u8 *conntab = ROMPTR(dev, dcb[0x14]);
5494 if (conntab && conntab[0] >= 0x30 && conntab[0] <= 0x40)
5501 dcb_conn(struct drm_device *dev, u8 idx)
5503 u8 *conntab = dcb_conntab(dev);
5504 if (conntab && idx < conntab[2])
5505 return conntab + conntab[1] + (idx * conntab[3]);
5509 static struct dcb_entry *new_dcb_entry(struct dcb_table *dcb)
5511 struct dcb_entry *entry = &dcb->entry[dcb->entries];
5513 memset(entry, 0, sizeof(struct dcb_entry));
5514 entry->index = dcb->entries++;
5519 static void fabricate_dcb_output(struct dcb_table *dcb, int type, int i2c,
5522 struct dcb_entry *entry = new_dcb_entry(dcb);
5525 entry->i2c_index = i2c;
5526 entry->heads = heads;
5527 if (type != OUTPUT_ANALOG)
5528 entry->location = !DCB_LOC_ON_CHIP; /* ie OFF CHIP */
5533 parse_dcb20_entry(struct drm_device *dev, struct dcb_table *dcb,
5534 uint32_t conn, uint32_t conf, struct dcb_entry *entry)
5536 entry->type = conn & 0xf;
5537 entry->i2c_index = (conn >> 4) & 0xf;
5538 entry->heads = (conn >> 8) & 0xf;
5539 entry->connector = (conn >> 12) & 0xf;
5540 entry->bus = (conn >> 16) & 0xf;
5541 entry->location = (conn >> 20) & 0x3;
5542 entry->or = (conn >> 24) & 0xf;
5544 switch (entry->type) {
5547 * Although the rest of a CRT conf dword is usually
5548 * zeros, mac biosen have stuff there so we must mask
5550 entry->crtconf.maxfreq = (dcb->version < 0x30) ?
5551 (conf & 0xffff) * 10 :
5552 (conf & 0xff) * 10000;
5558 entry->lvdsconf.use_straps_for_mode = true;
5559 if (dcb->version < 0x22) {
5562 * The laptop in bug 14567 lies and claims to not use
5563 * straps when it does, so assume all DCB 2.0 laptops
5564 * use straps, until a broken EDID using one is produced
5566 entry->lvdsconf.use_straps_for_mode = true;
5568 * Both 0x4 and 0x8 show up in v2.0 tables; assume they
5569 * mean the same thing (probably wrong, but might work)
5571 if (conf & 0x4 || conf & 0x8)
5572 entry->lvdsconf.use_power_scripts = true;
5576 entry->lvdsconf.use_acpi_for_edid = true;
5578 entry->lvdsconf.use_power_scripts = true;
5579 entry->lvdsconf.sor.link = (conf & 0x00000030) >> 4;
5583 * Until we even try to use these on G8x, it's
5584 * useless reporting unknown bits. They all are.
5586 if (dcb->version >= 0x40)
5589 NV_ERROR(dev, "Unknown LVDS configuration bits, "
5596 if (dcb->version >= 0x30)
5597 entry->tvconf.has_component_output = conf & (0x8 << 4);
5599 entry->tvconf.has_component_output = false;
5604 entry->dpconf.sor.link = (conf & 0x00000030) >> 4;
5605 switch ((conf & 0x00e00000) >> 21) {
5607 entry->dpconf.link_bw = 162000;
5610 entry->dpconf.link_bw = 270000;
5613 switch ((conf & 0x0f000000) >> 24) {
5615 entry->dpconf.link_nr = 4;
5618 entry->dpconf.link_nr = 2;
5621 entry->dpconf.link_nr = 1;
5626 if (dcb->version >= 0x40)
5627 entry->tmdsconf.sor.link = (conf & 0x00000030) >> 4;
5628 else if (dcb->version >= 0x30)
5629 entry->tmdsconf.slave_addr = (conf & 0x00000700) >> 8;
5630 else if (dcb->version >= 0x22)
5631 entry->tmdsconf.slave_addr = (conf & 0x00000070) >> 4;
5635 /* weird g80 mobile type that "nv" treats as a terminator */
5642 if (dcb->version < 0x40) {
5643 /* Normal entries consist of a single bit, but dual link has
5644 * the next most significant bit set too
5646 entry->duallink_possible =
5647 ((1 << (ffs(entry->or) - 1)) * 3 == entry->or);
5649 entry->duallink_possible = (entry->sorconf.link == 3);
5652 /* unsure what DCB version introduces this, 3.0? */
5653 if (conf & 0x100000)
5654 entry->i2c_upper_default = true;
5660 parse_dcb15_entry(struct drm_device *dev, struct dcb_table *dcb,
5661 uint32_t conn, uint32_t conf, struct dcb_entry *entry)
5663 switch (conn & 0x0000000f) {
5665 entry->type = OUTPUT_ANALOG;
5668 entry->type = OUTPUT_TV;
5673 entry->type = OUTPUT_LVDS;
5675 entry->type = OUTPUT_TMDS;
5678 entry->type = OUTPUT_LVDS;
5681 NV_ERROR(dev, "Unknown DCB type %d\n", conn & 0x0000000f);
5685 entry->i2c_index = (conn & 0x0003c000) >> 14;
5686 entry->heads = ((conn & 0x001c0000) >> 18) + 1;
5687 entry->or = entry->heads; /* same as heads, hopefully safe enough */
5688 entry->location = (conn & 0x01e00000) >> 21;
5689 entry->bus = (conn & 0x0e000000) >> 25;
5690 entry->duallink_possible = false;
5692 switch (entry->type) {
5694 entry->crtconf.maxfreq = (conf & 0xffff) * 10;
5697 entry->tvconf.has_component_output = false;
5700 if ((conn & 0x00003f00) >> 8 != 0x10)
5701 entry->lvdsconf.use_straps_for_mode = true;
5702 entry->lvdsconf.use_power_scripts = true;
5712 void merge_like_dcb_entries(struct drm_device *dev, struct dcb_table *dcb)
5715 * DCB v2.0 lists each output combination separately.
5716 * Here we merge compatible entries to have fewer outputs, with
5720 int i, newentries = 0;
5722 for (i = 0; i < dcb->entries; i++) {
5723 struct dcb_entry *ient = &dcb->entry[i];
5726 for (j = i + 1; j < dcb->entries; j++) {
5727 struct dcb_entry *jent = &dcb->entry[j];
5729 if (jent->type == 100) /* already merged entry */
5732 /* merge heads field when all other fields the same */
5733 if (jent->i2c_index == ient->i2c_index &&
5734 jent->type == ient->type &&
5735 jent->location == ient->location &&
5736 jent->or == ient->or) {
5737 NV_TRACE(dev, "Merging DCB entries %d and %d\n",
5739 ient->heads |= jent->heads;
5740 jent->type = 100; /* dummy value */
5745 /* Compact entries merged into others out of dcb */
5746 for (i = 0; i < dcb->entries; i++) {
5747 if (dcb->entry[i].type == 100)
5750 if (newentries != i) {
5751 dcb->entry[newentries] = dcb->entry[i];
5752 dcb->entry[newentries].index = newentries;
5757 dcb->entries = newentries;
5761 apply_dcb_encoder_quirks(struct drm_device *dev, int idx, u32 *conn, u32 *conf)
5763 struct drm_nouveau_private *dev_priv = dev->dev_private;
5764 struct dcb_table *dcb = &dev_priv->vbios.dcb;
5766 /* Dell Precision M6300
5767 * DCB entry 2: 02025312 00000010
5768 * DCB entry 3: 02026312 00000020
5770 * Identical, except apparently a different connector on a
5771 * different SOR link. Not a clue how we're supposed to know
5772 * which one is in use if it even shares an i2c line...
5774 * Ignore the connector on the second SOR link to prevent
5775 * nasty problems until this is sorted (assuming it's not a
5778 if (nv_match_device(dev, 0x040d, 0x1028, 0x019b)) {
5779 if (*conn == 0x02026312 && *conf == 0x00000020)
5785 * DCB reports an LVDS output that should be TMDS:
5786 * DCB entry 1: f2005014 ffffffff
5788 if (nv_match_device(dev, 0x0201, 0x1462, 0x8851)) {
5789 if (*conn == 0xf2005014 && *conf == 0xffffffff) {
5790 fabricate_dcb_output(dcb, OUTPUT_TMDS, 1, 1, 1);
5797 * So many things wrong here, replace the entire encoder table..
5799 if (nv_match_device(dev, 0x0ca3, 0x1682, 0x3003)) {
5801 *conn = 0x02001300; /* VGA, connector 1 */
5805 *conn = 0x01010312; /* DVI, connector 0 */
5809 *conn = 0x01010310; /* VGA, connector 0 */
5813 *conn = 0x02022362; /* HDMI, connector 2 */
5816 *conn = 0x0000000e; /* EOL */
5821 /* Some other twisted XFX board (rhbz#694914)
5823 * The DVI/VGA encoder combo that's supposed to represent the
5824 * DVI-I connector actually point at two different ones, and
5825 * the HDMI connector ends up paired with the VGA instead.
5827 * Connector table is missing anything for VGA at all, pointing it
5828 * an invalid conntab entry 2 so we figure it out ourself.
5830 if (nv_match_device(dev, 0x0615, 0x1682, 0x2605)) {
5832 *conn = 0x02002300; /* VGA, connector 2 */
5836 *conn = 0x01010312; /* DVI, connector 0 */
5840 *conn = 0x04020310; /* VGA, connector 0 */
5844 *conn = 0x02021322; /* HDMI, connector 1 */
5847 *conn = 0x0000000e; /* EOL */
5852 /* fdo#50830: connector indices for VGA and DVI-I are backwards */
5853 if (nv_match_device(dev, 0x0421, 0x3842, 0xc793)) {
5854 if (idx == 0 && *conn == 0x02000300)
5857 if (idx == 1 && *conn == 0x04011310)
5860 if (idx == 2 && *conn == 0x02011312)
5868 fabricate_dcb_encoder_table(struct drm_device *dev, struct nvbios *bios)
5870 struct dcb_table *dcb = &bios->dcb;
5871 int all_heads = (nv_two_heads(dev) ? 3 : 1);
5874 /* Apple iMac G4 NV17 */
5875 if (of_machine_is_compatible("PowerMac4,5")) {
5876 fabricate_dcb_output(dcb, OUTPUT_TMDS, 0, all_heads, 1);
5877 fabricate_dcb_output(dcb, OUTPUT_ANALOG, 1, all_heads, 2);
5882 /* Make up some sane defaults */
5883 fabricate_dcb_output(dcb, OUTPUT_ANALOG,
5884 bios->legacy.i2c_indices.crt, 1, 1);
5886 if (nv04_tv_identify(dev, bios->legacy.i2c_indices.tv) >= 0)
5887 fabricate_dcb_output(dcb, OUTPUT_TV,
5888 bios->legacy.i2c_indices.tv,
5891 else if (bios->tmds.output0_script_ptr ||
5892 bios->tmds.output1_script_ptr)
5893 fabricate_dcb_output(dcb, OUTPUT_TMDS,
5894 bios->legacy.i2c_indices.panel,
5899 parse_dcb_entry(struct drm_device *dev, void *data, int idx, u8 *outp)
5901 struct drm_nouveau_private *dev_priv = dev->dev_private;
5902 struct dcb_table *dcb = &dev_priv->vbios.dcb;
5903 u32 conf = (dcb->version >= 0x20) ? ROM32(outp[4]) : ROM32(outp[6]);
5904 u32 conn = ROM32(outp[0]);
5907 if (apply_dcb_encoder_quirks(dev, idx, &conn, &conf)) {
5908 struct dcb_entry *entry = new_dcb_entry(dcb);
5910 NV_TRACEWARN(dev, "DCB outp %02d: %08x %08x\n", idx, conn, conf);
5912 if (dcb->version >= 0x20)
5913 ret = parse_dcb20_entry(dev, dcb, conn, conf, entry);
5915 ret = parse_dcb15_entry(dev, dcb, conn, conf, entry);
5917 return 1; /* stop parsing */
5919 /* Ignore the I2C index for on-chip TV-out, as there
5920 * are cards with bogus values (nv31m in bug 23212),
5921 * and it's otherwise useless.
5923 if (entry->type == OUTPUT_TV &&
5924 entry->location == DCB_LOC_ON_CHIP)
5925 entry->i2c_index = 0x0f;
5932 dcb_fake_connectors(struct nvbios *bios)
5934 struct dcb_table *dcbt = &bios->dcb;
5938 /* heuristic: if we ever get a non-zero connector field, assume
5939 * that all the indices are valid and we don't need fake them.
5941 * and, as usual, a blacklist of boards with bad bios data..
5943 if (!nv_match_device(bios->dev, 0x0392, 0x107d, 0x20a2)) {
5944 for (i = 0; i < dcbt->entries; i++) {
5945 if (dcbt->entry[i].connector)
5950 /* no useful connector info available, we need to make it up
5951 * ourselves. the rule here is: anything on the same i2c bus
5952 * is considered to be on the same connector. any output
5953 * without an associated i2c bus is assigned its own unique
5956 for (i = 0; i < dcbt->entries; i++) {
5957 u8 i2c = dcbt->entry[i].i2c_index;
5959 dcbt->entry[i].connector = idx++;
5963 dcbt->entry[i].connector = map[i2c] - 1;
5967 /* if we created more than one connector, destroy the connector
5968 * table - just in case it has random, rather than stub, entries.
5971 u8 *conntab = dcb_conntab(bios->dev);
5978 parse_dcb_table(struct drm_device *dev, struct nvbios *bios)
5980 struct dcb_table *dcb = &bios->dcb;
5984 dcbt = olddcb_table(dev);
5986 /* handle pre-DCB boards */
5987 if (bios->type == NVBIOS_BMP) {
5988 fabricate_dcb_encoder_table(dev, bios);
5995 NV_TRACE(dev, "DCB version %d.%d\n", dcbt[0] >> 4, dcbt[0] & 0xf);
5997 dcb->version = dcbt[0];
5998 olddcb_outp_foreach(dev, NULL, parse_dcb_entry);
6001 * apart for v2.1+ not being known for requiring merging, this
6002 * guarantees dcbent->index is the index of the entry in the rom image
6004 if (dcb->version < 0x21)
6005 merge_like_dcb_entries(dev, dcb);
6010 /* dump connector table entries to log, if any exist */
6012 while ((conn = dcb_conn(dev, ++idx))) {
6013 if (conn[0] != 0xff) {
6014 NV_TRACE(dev, "DCB conn %02d: ", idx);
6015 if (dcb_conntab(dev)[3] < 4)
6016 printk("%04x\n", ROM16(conn[0]));
6018 printk("%08x\n", ROM32(conn[0]));
6021 dcb_fake_connectors(bios);
6025 static int load_nv17_hwsq_ucode_entry(struct drm_device *dev, struct nvbios *bios, uint16_t hwsq_offset, int entry)
6028 * The header following the "HWSQ" signature has the number of entries,
6029 * and the entry size
6031 * An entry consists of a dword to write to the sequencer control reg
6032 * (0x00001304), followed by the ucode bytes, written sequentially,
6033 * starting at reg 0x00001400
6036 uint8_t bytes_to_write;
6037 uint16_t hwsq_entry_offset;
6040 if (bios->data[hwsq_offset] <= entry) {
6041 NV_ERROR(dev, "Too few entries in HW sequencer table for "
6042 "requested entry\n");
6046 bytes_to_write = bios->data[hwsq_offset + 1];
6048 if (bytes_to_write != 36) {
6049 NV_ERROR(dev, "Unknown HW sequencer entry size\n");
6053 NV_TRACE(dev, "Loading NV17 power sequencing microcode\n");
6055 hwsq_entry_offset = hwsq_offset + 2 + entry * bytes_to_write;
6057 /* set sequencer control */
6058 bios_wr32(bios, 0x00001304, ROM32(bios->data[hwsq_entry_offset]));
6059 bytes_to_write -= 4;
6062 for (i = 0; i < bytes_to_write; i += 4)
6063 bios_wr32(bios, 0x00001400 + i, ROM32(bios->data[hwsq_entry_offset + i + 4]));
6065 /* twiddle NV_PBUS_DEBUG_4 */
6066 bios_wr32(bios, NV_PBUS_DEBUG_4, bios_rd32(bios, NV_PBUS_DEBUG_4) | 0x18);
6071 static int load_nv17_hw_sequencer_ucode(struct drm_device *dev,
6072 struct nvbios *bios)
6075 * BMP based cards, from NV17, need a microcode loading to correctly
6076 * control the GPIO etc for LVDS panels
6078 * BIT based cards seem to do this directly in the init scripts
6080 * The microcode entries are found by the "HWSQ" signature.
6083 const uint8_t hwsq_signature[] = { 'H', 'W', 'S', 'Q' };
6084 const int sz = sizeof(hwsq_signature);
6087 hwsq_offset = findstr(bios->data, bios->length, hwsq_signature, sz);
6091 /* always use entry 0? */
6092 return load_nv17_hwsq_ucode_entry(dev, bios, hwsq_offset + sz, 0);
6095 uint8_t *nouveau_bios_embedded_edid(struct drm_device *dev)
6097 struct drm_nouveau_private *dev_priv = dev->dev_private;
6098 struct nvbios *bios = &dev_priv->vbios;
6099 const uint8_t edid_sig[] = {
6100 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 };
6101 uint16_t offset = 0;
6103 int searchlen = NV_PROM_SIZE;
6106 return bios->fp.edid;
6109 newoffset = findstr(&bios->data[offset], searchlen,
6113 offset += newoffset;
6114 if (!nv_cksum(&bios->data[offset], EDID1_LEN))
6117 searchlen -= offset;
6121 NV_TRACE(dev, "Found EDID in BIOS\n");
6123 return bios->fp.edid = &bios->data[offset];
6127 nouveau_bios_run_init_table(struct drm_device *dev, uint16_t table,
6128 struct dcb_entry *dcbent, int crtc)
6130 struct drm_nouveau_private *dev_priv = dev->dev_private;
6131 struct nvbios *bios = &dev_priv->vbios;
6132 struct init_exec iexec = { true, false };
6134 spin_lock_bh(&bios->lock);
6135 bios->display.output = dcbent;
6136 bios->display.crtc = crtc;
6137 parse_init_table(bios, table, &iexec);
6138 bios->display.output = NULL;
6139 spin_unlock_bh(&bios->lock);
6143 nouveau_bios_init_exec(struct drm_device *dev, uint16_t table)
6145 struct drm_nouveau_private *dev_priv = dev->dev_private;
6146 struct nvbios *bios = &dev_priv->vbios;
6147 struct init_exec iexec = { true, false };
6149 parse_init_table(bios, table, &iexec);
6152 static bool NVInitVBIOS(struct drm_device *dev)
6154 struct drm_nouveau_private *dev_priv = dev->dev_private;
6155 struct nvbios *bios = &dev_priv->vbios;
6157 memset(bios, 0, sizeof(struct nvbios));
6158 spin_lock_init(&bios->lock);
6161 return _nv_bios(dev, &bios->data, &bios->length);
6164 static int nouveau_parse_vbios_struct(struct drm_device *dev)
6166 struct drm_nouveau_private *dev_priv = dev->dev_private;
6167 struct nvbios *bios = &dev_priv->vbios;
6168 const uint8_t bit_signature[] = { 0xff, 0xb8, 'B', 'I', 'T' };
6169 const uint8_t bmp_signature[] = { 0xff, 0x7f, 'N', 'V', 0x0 };
6172 offset = findstr(bios->data, bios->length,
6173 bit_signature, sizeof(bit_signature));
6175 NV_TRACE(dev, "BIT BIOS found\n");
6176 bios->type = NVBIOS_BIT;
6177 bios->offset = offset;
6178 return parse_bit_structure(bios, offset + 6);
6181 offset = findstr(bios->data, bios->length,
6182 bmp_signature, sizeof(bmp_signature));
6184 NV_TRACE(dev, "BMP BIOS found\n");
6185 bios->type = NVBIOS_BMP;
6186 bios->offset = offset;
6187 return parse_bmp_structure(dev, bios, offset);
6190 NV_ERROR(dev, "No known BIOS signature found\n");
6195 nouveau_run_vbios_init(struct drm_device *dev)
6197 struct drm_nouveau_private *dev_priv = dev->dev_private;
6198 struct nvbios *bios = &dev_priv->vbios;
6201 /* Reset the BIOS head to 0. */
6202 bios->state.crtchead = 0;
6204 if (bios->major_version < 5) /* BMP only */
6205 load_nv17_hw_sequencer_ucode(dev, bios);
6207 if (bios->execute) {
6208 bios->fp.last_script_invoc = 0;
6209 bios->fp.lvds_init_run = false;
6212 parse_init_tables(bios);
6215 * Runs some additional script seen on G8x VBIOSen. The VBIOS'
6216 * parser will run this right after the init tables, the binary
6217 * driver appears to run it at some point later.
6219 if (bios->some_script_ptr) {
6220 struct init_exec iexec = {true, false};
6222 NV_INFO(dev, "Parsing VBIOS init table at offset 0x%04X\n",
6223 bios->some_script_ptr);
6224 parse_init_table(bios, bios->some_script_ptr, &iexec);
6227 if (dev_priv->card_type >= NV_50) {
6228 for (i = 0; i < bios->dcb.entries; i++) {
6229 nouveau_bios_run_display_table(dev, 0, 0,
6230 &bios->dcb.entry[i], -1);
6238 nouveau_bios_posted(struct drm_device *dev)
6240 struct drm_nouveau_private *dev_priv = dev->dev_private;
6243 if (dev_priv->card_type >= NV_50) {
6244 if (NVReadVgaCrtc(dev, 0, 0x00) == 0 &&
6245 NVReadVgaCrtc(dev, 0, 0x1a) == 0)
6250 htotal = NVReadVgaCrtc(dev, 0, 0x06);
6251 htotal |= (NVReadVgaCrtc(dev, 0, 0x07) & 0x01) << 8;
6252 htotal |= (NVReadVgaCrtc(dev, 0, 0x07) & 0x20) << 4;
6253 htotal |= (NVReadVgaCrtc(dev, 0, 0x25) & 0x01) << 10;
6254 htotal |= (NVReadVgaCrtc(dev, 0, 0x41) & 0x01) << 11;
6256 return (htotal != 0);
6260 nouveau_bios_init(struct drm_device *dev)
6262 struct drm_nouveau_private *dev_priv = dev->dev_private;
6263 struct nvbios *bios = &dev_priv->vbios;
6266 if (!NVInitVBIOS(dev))
6269 ret = nouveau_parse_vbios_struct(dev);
6273 ret = nouveau_i2c_init(dev);
6277 ret = nouveau_mxm_init(dev);
6281 ret = parse_dcb_table(dev, bios);
6285 if (!bios->major_version) /* we don't run version 0 bios */
6288 /* init script execution disabled */
6289 bios->execute = false;
6291 /* ... unless card isn't POSTed already */
6292 if (!nouveau_bios_posted(dev)) {
6293 NV_INFO(dev, "Adaptor not initialised, "
6294 "running VBIOS init tables.\n");
6295 bios->execute = true;
6297 if (nouveau_force_post)
6298 bios->execute = true;
6300 ret = nouveau_run_vbios_init(dev);
6304 /* feature_byte on BMP is poor, but init always sets CR4B */
6305 if (bios->major_version < 5)
6306 bios->is_mobile = NVReadVgaCrtc(dev, 0, NV_CIO_CRE_4B) & 0x40;
6308 /* all BIT systems need p_f_m_t for digital_min_front_porch */
6309 if (bios->is_mobile || bios->major_version >= 5)
6310 ret = parse_fp_mode_table(dev, bios);
6312 /* allow subsequent scripts to execute */
6313 bios->execute = true;
6319 nouveau_bios_takedown(struct drm_device *dev)
6321 struct drm_nouveau_private *dev_priv = dev->dev_private;
6323 nouveau_mxm_fini(dev);
6324 nouveau_i2c_fini(dev);