Pileus Git - ~andy/linux/blob - drivers/gpu/drm/nouveau/core/subdev/pwr/fuc/macros.fuc

   1 /*
   2  * Copyright 2013 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #define GT215 0xa3
  26 #define GF100 0xc0
  27 #define GF119 0xd9
  28 #define GK208 0x108
  29
  30 #include "os.h"
  31
  32 // IO addresses
  33 #define NV_PPWR_INTR_TRIGGER                                             0x0000
  34 #define NV_PPWR_INTR_TRIGGER_USER1                                   0x00000080
  35 #define NV_PPWR_INTR_TRIGGER_USER0                                   0x00000040
  36 #define NV_PPWR_INTR_ACK                                                 0x0004
  37 #define NV_PPWR_INTR_ACK_SUBINTR                                     0x00000800
  38 #define NV_PPWR_INTR_ACK_WATCHDOG                                    0x00000002
  39 #define NV_PPWR_INTR                                                     0x0008
  40 #define NV_PPWR_INTR_SUBINTR                                         0x00000800
  41 #define NV_PPWR_INTR_USER1                                           0x00000080
  42 #define NV_PPWR_INTR_USER0                                           0x00000040
  43 #define NV_PPWR_INTR_PAUSE                                           0x00000020
  44 #define NV_PPWR_INTR_WATCHDOG                                        0x00000002
  45 #define NV_PPWR_INTR_EN_SET                                              0x0010
  46 #define NV_PPWR_INTR_EN_SET_SUBINTR                                  0x00000800
  47 #define NV_PPWR_INTR_EN_SET_WATCHDOG                                 0x00000002
  48 #define NV_PPWR_INTR_EN_CLR                                              0x0014
  49 #define NV_PPWR_INTR_EN_CLR_MASK                    /* fuck i hate envyas */ -1
  50 #define NV_PPWR_INTR_ROUTE                                               0x001c
  51 #define NV_PPWR_TIMER_LOW                                                0x002c
  52 #define NV_PPWR_WATCHDOG_TIME                                            0x0034
  53 #define NV_PPWR_WATCHDOG_ENABLE                                          0x0038
  54 #define NV_PPWR_CAPS                                                     0x0108
  55 #define NV_PPWR_UAS_CONFIG                                               0x0164
  56 #define NV_PPWR_UAS_CONFIG_ENABLE                                    0x00010000
  57 #if NVKM_PPWR_CHIPSET >= GK208
  58 #define NV_PPWR_DSCRATCH(i)                                   (4 * (i) + 0x0450)
  59 #endif
  60 #define NV_PPWR_FIFO_PUT(i)                                   (4 * (i) + 0x04a0)
  61 #define NV_PPWR_FIFO_GET(i)                                   (4 * (i) + 0x04b0)
  62 #define NV_PPWR_FIFO_INTR                                                0x04c0
  63 #define NV_PPWR_FIFO_INTR_EN                                             0x04c4
  64 #define NV_PPWR_RFIFO_PUT                                                0x04c8
  65 #define NV_PPWR_RFIFO_GET                                                0x04cc
  66 #define NV_PPWR_H2D                                                      0x04d0
  67 #define NV_PPWR_D2H                                                      0x04dc
  68 #if NVKM_PPWR_CHIPSET < GK208
  69 #define NV_PPWR_DSCRATCH(i)                                   (4 * (i) + 0x05d0)
  70 #endif
  71 #define NV_PPWR_SUBINTR                                                  0x0688
  72 #define NV_PPWR_SUBINTR_FIFO                                         0x00000002
  73 #define NV_PPWR_MMIO_ADDR                                                0x07a0
  74 #define NV_PPWR_MMIO_DATA                                                0x07a4
  75 #define NV_PPWR_MMIO_CTRL                                                0x07ac
  76 #define NV_PPWR_MMIO_CTRL_TRIGGER                                    0x00010000
  77 #define NV_PPWR_MMIO_CTRL_STATUS                                     0x00007000
  78 #define NV_PPWR_MMIO_CTRL_STATUS_IDLE                                0x00000000
  79 #define NV_PPWR_MMIO_CTRL_MASK                                       0x000000f0
  80 #define NV_PPWR_MMIO_CTRL_MASK_B32_0                                 0x000000f0
  81 #define NV_PPWR_MMIO_CTRL_OP                                         0x00000003
  82 #define NV_PPWR_MMIO_CTRL_OP_RD                                      0x00000001
  83 #define NV_PPWR_MMIO_CTRL_OP_WR                                      0x00000002
  84 #define NV_PPWR_OUTPUT                                                   0x07c0
  85 #define NV_PPWR_OUTPUT_FB_PAUSE                                      0x00000004
  86 #define NV_PPWR_OUTPUT_SET                                               0x07e0
  87 #define NV_PPWR_OUTPUT_SET_FB_PAUSE                                  0x00000004
  88 #define NV_PPWR_OUTPUT_CLR                                               0x07e4
  89 #define NV_PPWR_OUTPUT_CLR_FB_PAUSE                                  0x00000004
  90
  91 // Inter-process message format
  92 .equ #msg_process 0x00 /* send() target, recv() sender */
  93 .equ #msg_message 0x04
  94 .equ #msg_data0   0x08
  95 .equ #msg_data1   0x0c
  96
  97 // Kernel message IDs
  98 #define KMSG_FIFO  0x00000000
  99 #define KMSG_ALARM 0x00000001
 100
 101 // Process message queue description
 102 .equ #proc_qlen 4 // log2(size of queue entry in bytes)
 103 .equ #proc_qnum 2 // log2(max number of entries in queue)
 104 .equ #proc_qmaskb (1 << #proc_qnum) // max number of entries in queue
 105 .equ #proc_qmaskp (#proc_qmaskb - 1)
 106 .equ #proc_qmaskf ((#proc_qmaskb << 1) - 1)
 107 .equ #proc_qsize  (1 << (#proc_qlen + #proc_qnum))
 108
 109 // Process table entry
 110 .equ #proc_id    0x00
 111 .equ #proc_init  0x04
 112 .equ #proc_recv  0x08
 113 .equ #proc_time  0x0c
 114 .equ #proc_qput  0x10
 115 .equ #proc_qget  0x14
 116 .equ #proc_queue 0x18
 117 .equ #proc_size (0x18 + #proc_qsize)
 118
 119 #define process(id,init,recv) /*
 120 */      .b32 id /*
 121 */      .b32 init /*
 122 */      .b32 recv /*
 123 */      .b32 0 /*
 124 */      .b32 0 /*
 125 */      .b32 0 /*
 126 */      .skip 64
 127
 128 #ifndef NVKM_FALCON_UNSHIFTED_IO
 129 #define nv_iord(reg,ior) /*
 130 */      mov reg ior /*
 131 */      shl b32 reg 6 /*
 132 */      iord reg I[reg + 0x000]
 133 #else
 134 #define nv_iord(reg,ior) /*
 135 */      mov reg ior /*
 136 */      iord reg I[reg + 0x000]
 137 #endif
 138
 139 #ifndef NVKM_FALCON_UNSHIFTED_IO
 140 #define nv_iowr(ior,reg) /*
 141 */      mov $r0 ior /*
 142 */      shl b32 $r0 6 /*
 143 */      iowr I[$r0 + 0x000] reg /*
 144 */      clear b32 $r0
 145 #else
 146 #define nv_iowr(ior,reg) /*
 147 */      mov $r0 ior /*
 148 */      iowr I[$r0 + 0x000] reg /*
 149 */      clear b32 $r0
 150 #endif
 151
 152 #ifndef NVKM_FALCON_UNSHIFTED_IO
 153 #define nv_iowrs(ior,reg) /*
 154 */      mov $r0 ior /*
 155 */      shl b32 $r0 6 /*
 156 */      iowrs I[$r0 + 0x000] reg /*
 157 */      clear b32 $r0
 158 #else
 159 #define nv_iowrs(ior,reg) /*
 160 */      mov $r0 ior /*
 161 */      iowrs I[$r0 + 0x000] reg /*
 162 */      clear b32 $r0
 163 #endif
 164
 165 #define hash #
 166 #define fn(a) a
 167 #ifndef NVKM_FALCON_PC24
 168 #define call(a) call fn(hash)a
 169 #else
 170 #define call(a) lcall fn(hash)a
 171 #endif
 172
 173 #ifndef NVKM_FALCON_MMIO_UAS
 174 #define nv_rd32(reg,addr) /*
 175 */      mov b32 $r14 addr /*
 176 */      call(rd32) /*
 177 */      mov b32 reg $r13
 178 #else
 179 #define nv_rd32(reg,addr) /*
 180 */      sethi $r0 0x14000000 /*
 181 */      or $r0 addr /*
 182 */      ld b32 reg D[$r0] /*
 183 */      clear b32 $r0
 184 #endif
 185
 186 #if !defined(NVKM_FALCON_MMIO_UAS) || defined(NVKM_FALCON_MMIO_TRAP)
 187 #define nv_wr32(addr,reg) /*
 188 */      push addr /*
 189 */      push reg /*
 190 */      pop $r13 /*
 191 */      pop $r14 /*
 192 */      call(wr32) /*
 193 #else
 194 #define nv_wr32(addr,reg) /*
 195 */      sethi $r0 0x14000000 /*
 196 */      or $r0 addr /*
 197 */      st b32 D[$r0] reg /*
 198 */      clear b32 $r0
 199 #endif