2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <engine/graph/nv40.h>
30 nv40_instmem_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
31 struct nouveau_oclass *oclass, void *data, u32 size,
32 struct nouveau_object **pobject)
34 struct nouveau_device *device = nv_device(parent);
35 struct pci_dev *pdev = device->pdev;
36 struct nv04_instmem_priv *priv;
39 ret = nouveau_instmem_create(parent, engine, oclass, &priv);
40 *pobject = nv_object(priv);
45 if (pci_resource_len(pdev, 2))
50 priv->iomem = ioremap(pci_resource_start(pdev, bar),
51 pci_resource_len(pdev, bar));
53 nv_error(priv, "unable to map PRAMIN BAR\n");
57 /* PRAMIN aperture maps over the end of vram, reserve enough space
58 * to fit graphics contexts for every channel, the magics come
59 * from engine/graph/nv40.c
61 vs = hweight8((nv_rd32(priv, 0x001540) & 0x0000ff00) >> 8);
62 if (device->chipset == 0x40) priv->base.reserved = 0x6aa0 * vs;
63 else if (device->chipset < 0x43) priv->base.reserved = 0x4f00 * vs;
64 else if (nv44_graph_class(priv)) priv->base.reserved = 0x4980 * vs;
65 else priv->base.reserved = 0x4a40 * vs;
66 priv->base.reserved += 16 * 1024;
67 priv->base.reserved *= 32; /* per-channel */
68 priv->base.reserved += 512 * 1024; /* pci(e)gart table */
69 priv->base.reserved += 512 * 1024; /* object storage */
71 priv->base.reserved = round_up(priv->base.reserved, 4096);
72 priv->base.alloc = nv04_instmem_alloc;
74 ret = nouveau_mm_init(&priv->heap, 0, priv->base.reserved, 1);
78 /* 0x00000-0x10000: reserve for probable vbios image */
79 ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x10000, 0, 0,
84 /* 0x10000-0x18000: reserve for RAMHT */
85 ret = nouveau_ramht_new(nv_object(priv), NULL, 0x08000, 0,
90 /* 0x18000-0x18200: reserve for RAMRO
91 * 0x18200-0x20000: padding
93 ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x08000, 0, 0,
98 /* 0x20000-0x21000: reserve for RAMFC
99 * 0x21000-0x40000: padding and some unknown crap
101 ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x20000, 0,
102 NVOBJ_FLAG_ZERO_ALLOC, &priv->ramfc);
110 nv40_instmem_rd32(struct nouveau_object *object, u64 addr)
112 struct nv04_instmem_priv *priv = (void *)object;
113 return ioread32_native(priv->iomem + addr);
117 nv40_instmem_wr32(struct nouveau_object *object, u64 addr, u32 data)
119 struct nv04_instmem_priv *priv = (void *)object;
120 iowrite32_native(data, priv->iomem + addr);
123 struct nouveau_oclass
124 nv40_instmem_oclass = {
125 .handle = NV_SUBDEV(INSTMEM, 0x40),
126 .ofuncs = &(struct nouveau_ofuncs) {
127 .ctor = nv40_instmem_ctor,
128 .dtor = nv04_instmem_dtor,
129 .init = _nouveau_instmem_init,
130 .fini = _nouveau_instmem_fini,
131 .rd32 = nv40_instmem_rd32,
132 .wr32 = nv40_instmem_wr32,