2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <core/client.h>
26 #include <core/enum.h>
27 #include <core/engctx.h>
28 #include <core/object.h>
30 #include <subdev/bios.h>
35 nv50_fb_memtype[0x80] = {
36 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
37 1, 1, 1, 1, 0, 0, 0, 0, 2, 2, 2, 2, 0, 0, 0, 0,
38 1, 1, 1, 1, 1, 1, 1, 0, 2, 2, 2, 2, 2, 2, 2, 0,
39 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
40 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 0, 0,
41 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0,
42 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 2, 2, 2, 2,
43 1, 0, 2, 0, 1, 0, 2, 0, 1, 1, 2, 2, 1, 1, 0, 0
47 nv50_fb_memtype_valid(struct nouveau_fb *pfb, u32 memtype)
49 return nv50_fb_memtype[(memtype & 0xff00) >> 8] != 0;
52 static const struct nouveau_enum vm_dispatch_subclients[] = {
53 { 0x00000000, "GRCTX", NULL },
54 { 0x00000001, "NOTIFY", NULL },
55 { 0x00000002, "QUERY", NULL },
56 { 0x00000003, "COND", NULL },
57 { 0x00000004, "M2M_IN", NULL },
58 { 0x00000005, "M2M_OUT", NULL },
59 { 0x00000006, "M2M_NOTIFY", NULL },
63 static const struct nouveau_enum vm_ccache_subclients[] = {
64 { 0x00000000, "CB", NULL },
65 { 0x00000001, "TIC", NULL },
66 { 0x00000002, "TSC", NULL },
70 static const struct nouveau_enum vm_prop_subclients[] = {
71 { 0x00000000, "RT0", NULL },
72 { 0x00000001, "RT1", NULL },
73 { 0x00000002, "RT2", NULL },
74 { 0x00000003, "RT3", NULL },
75 { 0x00000004, "RT4", NULL },
76 { 0x00000005, "RT5", NULL },
77 { 0x00000006, "RT6", NULL },
78 { 0x00000007, "RT7", NULL },
79 { 0x00000008, "ZETA", NULL },
80 { 0x00000009, "LOCAL", NULL },
81 { 0x0000000a, "GLOBAL", NULL },
82 { 0x0000000b, "STACK", NULL },
83 { 0x0000000c, "DST2D", NULL },
87 static const struct nouveau_enum vm_pfifo_subclients[] = {
88 { 0x00000000, "PUSHBUF", NULL },
89 { 0x00000001, "SEMAPHORE", NULL },
93 static const struct nouveau_enum vm_bar_subclients[] = {
94 { 0x00000000, "FB", NULL },
95 { 0x00000001, "IN", NULL },
99 static const struct nouveau_enum vm_client[] = {
100 { 0x00000000, "STRMOUT", NULL },
101 { 0x00000003, "DISPATCH", vm_dispatch_subclients },
102 { 0x00000004, "PFIFO_WRITE", NULL },
103 { 0x00000005, "CCACHE", vm_ccache_subclients },
104 { 0x00000006, "PPPP", NULL },
105 { 0x00000007, "CLIPID", NULL },
106 { 0x00000008, "PFIFO_READ", NULL },
107 { 0x00000009, "VFETCH", NULL },
108 { 0x0000000a, "TEXTURE", NULL },
109 { 0x0000000b, "PROP", vm_prop_subclients },
110 { 0x0000000c, "PVP", NULL },
111 { 0x0000000d, "PBSP", NULL },
112 { 0x0000000e, "PCRYPT", NULL },
113 { 0x0000000f, "PCOUNTER", NULL },
114 { 0x00000011, "PDAEMON", NULL },
118 static const struct nouveau_enum vm_engine[] = {
119 { 0x00000000, "PGRAPH", NULL, NVDEV_ENGINE_GR },
120 { 0x00000001, "PVP", NULL, NVDEV_ENGINE_VP },
121 { 0x00000004, "PEEPHOLE", NULL },
122 { 0x00000005, "PFIFO", vm_pfifo_subclients, NVDEV_ENGINE_FIFO },
123 { 0x00000006, "BAR", vm_bar_subclients },
124 { 0x00000008, "PPPP", NULL, NVDEV_ENGINE_PPP },
125 { 0x00000008, "PMPEG", NULL, NVDEV_ENGINE_MPEG },
126 { 0x00000009, "PBSP", NULL, NVDEV_ENGINE_BSP },
127 { 0x0000000a, "PCRYPT", NULL, NVDEV_ENGINE_CRYPT },
128 { 0x0000000b, "PCOUNTER", NULL },
129 { 0x0000000c, "SEMAPHORE_BG", NULL },
130 { 0x0000000d, "PCOPY", NULL, NVDEV_ENGINE_COPY0 },
131 { 0x0000000e, "PDAEMON", NULL },
135 static const struct nouveau_enum vm_fault[] = {
136 { 0x00000000, "PT_NOT_PRESENT", NULL },
137 { 0x00000001, "PT_TOO_SHORT", NULL },
138 { 0x00000002, "PAGE_NOT_PRESENT", NULL },
139 { 0x00000003, "PAGE_SYSTEM_ONLY", NULL },
140 { 0x00000004, "PAGE_READ_ONLY", NULL },
141 { 0x00000006, "NULL_DMAOBJ", NULL },
142 { 0x00000007, "WRONG_MEMTYPE", NULL },
143 { 0x0000000b, "VRAM_LIMIT", NULL },
144 { 0x0000000f, "DMAOBJ_LIMIT", NULL },
149 nv50_fb_intr(struct nouveau_subdev *subdev)
151 struct nouveau_device *device = nv_device(subdev);
152 struct nouveau_engine *engine;
153 struct nv50_fb_priv *priv = (void *)subdev;
154 const struct nouveau_enum *en, *cl;
155 struct nouveau_object *engctx = NULL;
156 u32 trap[6], idx, chan;
157 u8 st0, st1, st2, st3;
160 idx = nv_rd32(priv, 0x100c90);
161 if (!(idx & 0x80000000))
165 for (i = 0; i < 6; i++) {
166 nv_wr32(priv, 0x100c90, idx | i << 24);
167 trap[i] = nv_rd32(priv, 0x100c94);
169 nv_wr32(priv, 0x100c90, idx | 0x80000000);
171 /* decode status bits into something more useful */
172 if (device->chipset < 0xa3 ||
173 device->chipset == 0xaa || device->chipset == 0xac) {
174 st0 = (trap[0] & 0x0000000f) >> 0;
175 st1 = (trap[0] & 0x000000f0) >> 4;
176 st2 = (trap[0] & 0x00000f00) >> 8;
177 st3 = (trap[0] & 0x0000f000) >> 12;
179 st0 = (trap[0] & 0x000000ff) >> 0;
180 st1 = (trap[0] & 0x0000ff00) >> 8;
181 st2 = (trap[0] & 0x00ff0000) >> 16;
182 st3 = (trap[0] & 0xff000000) >> 24;
184 chan = (trap[2] << 16) | trap[1];
186 en = nouveau_enum_find(vm_engine, st0);
188 if (en && en->data2) {
189 const struct nouveau_enum *orig_en = en;
190 while (en->name && en->value == st0 && en->data2) {
191 engine = nouveau_engine(subdev, en->data2);
193 engctx = nouveau_engctx_get(engine, chan);
203 nv_error(priv, "trapped %s at 0x%02x%04x%04x on channel 0x%08x [%s] ",
204 (trap[5] & 0x00000100) ? "read" : "write",
205 trap[5] & 0xff, trap[4] & 0xffff, trap[3] & 0xffff, chan,
206 nouveau_client_name(engctx));
208 nouveau_engctx_put(engctx);
211 pr_cont("%s/", en->name);
213 pr_cont("%02x/", st0);
215 cl = nouveau_enum_find(vm_client, st2);
217 pr_cont("%s/", cl->name);
219 pr_cont("%02x/", st2);
221 if (cl && cl->data) cl = nouveau_enum_find(cl->data, st3);
222 else if (en && en->data) cl = nouveau_enum_find(en->data, st3);
225 pr_cont("%s", cl->name);
227 pr_cont("%02x", st3);
229 pr_cont(" reason: ");
230 en = nouveau_enum_find(vm_fault, st1);
232 pr_cont("%s\n", en->name);
234 pr_cont("0x%08x\n", st1);
238 nv50_fb_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
239 struct nouveau_oclass *oclass, void *data, u32 size,
240 struct nouveau_object **pobject)
242 struct nouveau_device *device = nv_device(parent);
243 struct nv50_fb_priv *priv;
246 ret = nouveau_fb_create(parent, engine, oclass, &priv);
247 *pobject = nv_object(priv);
251 priv->r100c08_page = alloc_page(GFP_KERNEL | __GFP_ZERO);
252 if (priv->r100c08_page) {
253 priv->r100c08 = pci_map_page(device->pdev, priv->r100c08_page,
255 PCI_DMA_BIDIRECTIONAL);
256 if (pci_dma_mapping_error(device->pdev, priv->r100c08))
257 nv_warn(priv, "failed 0x100c08 page map\n");
259 nv_warn(priv, "failed 0x100c08 page alloc\n");
262 nv_subdev(priv)->intr = nv50_fb_intr;
267 nv50_fb_dtor(struct nouveau_object *object)
269 struct nouveau_device *device = nv_device(object);
270 struct nv50_fb_priv *priv = (void *)object;
272 if (priv->r100c08_page) {
273 pci_unmap_page(device->pdev, priv->r100c08, PAGE_SIZE,
274 PCI_DMA_BIDIRECTIONAL);
275 __free_page(priv->r100c08_page);
278 nouveau_fb_destroy(&priv->base);
282 nv50_fb_init(struct nouveau_object *object)
284 struct nv50_fb_impl *impl = (void *)object->oclass;
285 struct nv50_fb_priv *priv = (void *)object;
288 ret = nouveau_fb_init(&priv->base);
292 /* Not a clue what this is exactly. Without pointing it at a
293 * scratch page, VRAM->GART blits with M2MF (as in DDX DFS)
294 * cause IOMMU "read from address 0" errors (rh#561267)
296 nv_wr32(priv, 0x100c08, priv->r100c08 >> 8);
298 /* This is needed to get meaningful information from 100c90
299 * on traps. No idea what these values mean exactly. */
300 nv_wr32(priv, 0x100c90, impl->trap);
304 struct nouveau_oclass *
305 nv50_fb_oclass = &(struct nv50_fb_impl) {
306 .base.base.handle = NV_SUBDEV(FB, 0x50),
307 .base.base.ofuncs = &(struct nouveau_ofuncs) {
308 .ctor = nv50_fb_ctor,
309 .dtor = nv50_fb_dtor,
310 .init = nv50_fb_init,
311 .fini = _nouveau_fb_fini,
313 .base.memtype = nv50_fb_memtype_valid,
314 .base.ram = &nv50_ram_oclass,