Pileus Git - ~andy/linux/blob - drivers/gpu/drm/nouveau/core/include/core/class.h

   1 #ifndef __NOUVEAU_CLASS_H__
   2 #define __NOUVEAU_CLASS_H__
   3
   4 /* Device class
   5  *
   6  * 0080: NV_DEVICE
   7  */
   8 #define NV_DEVICE_CLASS                                              0x00000080
   9
  10 #define NV_DEVICE_DISABLE_IDENTIFY                        0x0000000000000001ULL
  11 #define NV_DEVICE_DISABLE_MMIO                            0x0000000000000002ULL
  12 #define NV_DEVICE_DISABLE_VBIOS                           0x0000000000000004ULL
  13 #define NV_DEVICE_DISABLE_CORE                            0x0000000000000008ULL
  14 #define NV_DEVICE_DISABLE_DISP                            0x0000000000010000ULL
  15 #define NV_DEVICE_DISABLE_FIFO                            0x0000000000020000ULL
  16 #define NV_DEVICE_DISABLE_GRAPH                           0x0000000100000000ULL
  17 #define NV_DEVICE_DISABLE_MPEG                            0x0000000200000000ULL
  18 #define NV_DEVICE_DISABLE_ME                              0x0000000400000000ULL
  19 #define NV_DEVICE_DISABLE_VP                              0x0000000800000000ULL
  20 #define NV_DEVICE_DISABLE_CRYPT                           0x0000001000000000ULL
  21 #define NV_DEVICE_DISABLE_BSP                             0x0000002000000000ULL
  22 #define NV_DEVICE_DISABLE_PPP                             0x0000004000000000ULL
  23 #define NV_DEVICE_DISABLE_COPY0                           0x0000008000000000ULL
  24 #define NV_DEVICE_DISABLE_COPY1                           0x0000010000000000ULL
  25 #define NV_DEVICE_DISABLE_UNK1C1                          0x0000020000000000ULL
  26 #define NV_DEVICE_DISABLE_VENC                            0x0000040000000000ULL
  27
  28 struct nv_device_class {
  29         u64 device;     /* device identifier, ~0 for client default */
  30         u64 disable;    /* disable particular subsystems */
  31         u64 debug0;     /* as above, but *internal* ids, and *NOT* ABI */
  32 };
  33
  34 /* DMA object classes
  35  *
  36  * 0002: NV_DMA_FROM_MEMORY
  37  * 0003: NV_DMA_TO_MEMORY
  38  * 003d: NV_DMA_IN_MEMORY
  39  */
  40 #define NV_DMA_FROM_MEMORY_CLASS                                     0x00000002
  41 #define NV_DMA_TO_MEMORY_CLASS                                       0x00000003
  42 #define NV_DMA_IN_MEMORY_CLASS                                       0x0000003d
  43
  44 #define NV_DMA_TARGET_MASK                                           0x000000ff
  45 #define NV_DMA_TARGET_VM                                             0x00000000
  46 #define NV_DMA_TARGET_VRAM                                           0x00000001
  47 #define NV_DMA_TARGET_PCI                                            0x00000002
  48 #define NV_DMA_TARGET_PCI_US                                         0x00000003
  49 #define NV_DMA_TARGET_AGP                                            0x00000004
  50 #define NV_DMA_ACCESS_MASK                                           0x00000f00
  51 #define NV_DMA_ACCESS_VM                                             0x00000000
  52 #define NV_DMA_ACCESS_RD                                             0x00000100
  53 #define NV_DMA_ACCESS_WR                                             0x00000200
  54 #define NV_DMA_ACCESS_RDWR                                           0x00000300
  55
  56 /* NV50:NVC0 */
  57 #define NV50_DMA_CONF0_ENABLE                                        0x80000000
  58 #define NV50_DMA_CONF0_PRIV                                          0x00300000
  59 #define NV50_DMA_CONF0_PRIV_VM                                       0x00000000
  60 #define NV50_DMA_CONF0_PRIV_US                                       0x00100000
  61 #define NV50_DMA_CONF0_PRIV__S                                       0x00200000
  62 #define NV50_DMA_CONF0_PART                                          0x00030000
  63 #define NV50_DMA_CONF0_PART_VM                                       0x00000000
  64 #define NV50_DMA_CONF0_PART_256                                      0x00010000
  65 #define NV50_DMA_CONF0_PART_1KB                                      0x00020000
  66 #define NV50_DMA_CONF0_COMP                                          0x00000180
  67 #define NV50_DMA_CONF0_COMP_NONE                                     0x00000000
  68 #define NV50_DMA_CONF0_COMP_VM                                       0x00000180
  69 #define NV50_DMA_CONF0_TYPE                                          0x0000007f
  70 #define NV50_DMA_CONF0_TYPE_LINEAR                                   0x00000000
  71 #define NV50_DMA_CONF0_TYPE_VM                                       0x0000007f
  72
  73 /* NVC0:NVD9 */
  74 #define NVC0_DMA_CONF0_ENABLE                                        0x80000000
  75 #define NVC0_DMA_CONF0_PRIV                                          0x00300000
  76 #define NVC0_DMA_CONF0_PRIV_VM                                       0x00000000
  77 #define NVC0_DMA_CONF0_PRIV_US                                       0x00100000
  78 #define NVC0_DMA_CONF0_PRIV__S                                       0x00200000
  79 #define NVC0_DMA_CONF0_UNKN /* PART? */                              0x00030000
  80 #define NVC0_DMA_CONF0_TYPE                                          0x000000ff
  81 #define NVC0_DMA_CONF0_TYPE_LINEAR                                   0x00000000
  82 #define NVC0_DMA_CONF0_TYPE_VM                                       0x000000ff
  83
  84 /* NVD9- */
  85 #define NVD0_DMA_CONF0_ENABLE                                        0x80000000
  86 #define NVD0_DMA_CONF0_PAGE                                          0x00000400
  87 #define NVD0_DMA_CONF0_PAGE_LP                                       0x00000000
  88 #define NVD0_DMA_CONF0_PAGE_SP                                       0x00000400
  89 #define NVD0_DMA_CONF0_TYPE                                          0x000000ff
  90 #define NVD0_DMA_CONF0_TYPE_LINEAR                                   0x00000000
  91 #define NVD0_DMA_CONF0_TYPE_VM                                       0x000000ff
  92
  93 struct nv_dma_class {
  94         u32 flags;
  95         u32 pad0;
  96         u64 start;
  97         u64 limit;
  98         u32 conf0;
  99 };
 100
 101 /* DMA FIFO channel classes
 102  *
 103  * 006b: NV03_CHANNEL_DMA
 104  * 006e: NV10_CHANNEL_DMA
 105  * 176e: NV17_CHANNEL_DMA
 106  * 406e: NV40_CHANNEL_DMA
 107  * 506e: NV50_CHANNEL_DMA
 108  * 826e: NV84_CHANNEL_DMA
 109  */
 110 #define NV03_CHANNEL_DMA_CLASS                                       0x0000006b
 111 #define NV10_CHANNEL_DMA_CLASS                                       0x0000006e
 112 #define NV17_CHANNEL_DMA_CLASS                                       0x0000176e
 113 #define NV40_CHANNEL_DMA_CLASS                                       0x0000406e
 114 #define NV50_CHANNEL_DMA_CLASS                                       0x0000506e
 115 #define NV84_CHANNEL_DMA_CLASS                                       0x0000826e
 116
 117 struct nv03_channel_dma_class {
 118         u32 pushbuf;
 119         u32 pad0;
 120         u64 offset;
 121 };
 122
 123 /* Indirect FIFO channel classes
 124  *
 125  * 506f: NV50_CHANNEL_IND
 126  * 826f: NV84_CHANNEL_IND
 127  * 906f: NVC0_CHANNEL_IND
 128  * a06f: NVE0_CHANNEL_IND
 129  */
 130
 131 #define NV50_CHANNEL_IND_CLASS                                       0x0000506f
 132 #define NV84_CHANNEL_IND_CLASS                                       0x0000826f
 133 #define NVC0_CHANNEL_IND_CLASS                                       0x0000906f
 134 #define NVE0_CHANNEL_IND_CLASS                                       0x0000a06f
 135
 136 struct nv50_channel_ind_class {
 137         u32 pushbuf;
 138         u32 ilength;
 139         u64 ioffset;
 140 };
 141
 142 #define NVE0_CHANNEL_IND_ENGINE_GR                                   0x00000001
 143 #define NVE0_CHANNEL_IND_ENGINE_VP                                   0x00000002
 144 #define NVE0_CHANNEL_IND_ENGINE_PPP                                  0x00000004
 145 #define NVE0_CHANNEL_IND_ENGINE_BSP                                  0x00000008
 146 #define NVE0_CHANNEL_IND_ENGINE_CE0                                  0x00000010
 147 #define NVE0_CHANNEL_IND_ENGINE_CE1                                  0x00000020
 148 #define NVE0_CHANNEL_IND_ENGINE_ENC                                  0x00000040
 149
 150 struct nve0_channel_ind_class {
 151         u32 pushbuf;
 152         u32 ilength;
 153         u64 ioffset;
 154         u32 engine;
 155 };
 156
 157 /* 0046: NV04_DISP
 158  */
 159
 160 #define NV04_DISP_CLASS                                              0x00000046
 161
 162 struct nv04_display_class {
 163 };
 164
 165 /* 5070: NV50_DISP
 166  * 8270: NV84_DISP
 167  * 8370: NVA0_DISP
 168  * 8870: NV94_DISP
 169  * 8570: NVA3_DISP
 170  * 9070: NVD0_DISP
 171  * 9170: NVE0_DISP
 172  * 9270: NVF0_DISP
 173  */
 174
 175 #define NV50_DISP_CLASS                                              0x00005070
 176 #define NV84_DISP_CLASS                                              0x00008270
 177 #define NVA0_DISP_CLASS                                              0x00008370
 178 #define NV94_DISP_CLASS                                              0x00008870
 179 #define NVA3_DISP_CLASS                                              0x00008570
 180 #define NVD0_DISP_CLASS                                              0x00009070
 181 #define NVE0_DISP_CLASS                                              0x00009170
 182 #define NVF0_DISP_CLASS                                              0x00009270
 183
 184 #define NV50_DISP_SOR_MTHD                                           0x00010000
 185 #define NV50_DISP_SOR_MTHD_TYPE                                      0x0000f000
 186 #define NV50_DISP_SOR_MTHD_HEAD                                      0x00000018
 187 #define NV50_DISP_SOR_MTHD_LINK                                      0x00000004
 188 #define NV50_DISP_SOR_MTHD_OR                                        0x00000003
 189
 190 #define NV50_DISP_SOR_PWR                                            0x00010000
 191 #define NV50_DISP_SOR_PWR_STATE                                      0x00000001
 192 #define NV50_DISP_SOR_PWR_STATE_ON                                   0x00000001
 193 #define NV50_DISP_SOR_PWR_STATE_OFF                                  0x00000000
 194 #define NVA3_DISP_SOR_HDA_ELD                                        0x00010100
 195 #define NV84_DISP_SOR_HDMI_PWR                                       0x00012000
 196 #define NV84_DISP_SOR_HDMI_PWR_STATE                                 0x40000000
 197 #define NV84_DISP_SOR_HDMI_PWR_STATE_OFF                             0x00000000
 198 #define NV84_DISP_SOR_HDMI_PWR_STATE_ON                              0x40000000
 199 #define NV84_DISP_SOR_HDMI_PWR_MAX_AC_PACKET                         0x001f0000
 200 #define NV84_DISP_SOR_HDMI_PWR_REKEY                                 0x0000007f
 201 #define NV50_DISP_SOR_LVDS_SCRIPT                                    0x00013000
 202 #define NV50_DISP_SOR_LVDS_SCRIPT_ID                                 0x0000ffff
 203
 204 #define NV50_DISP_DAC_MTHD                                           0x00020000
 205 #define NV50_DISP_DAC_MTHD_TYPE                                      0x0000f000
 206 #define NV50_DISP_DAC_MTHD_OR                                        0x00000003
 207
 208 #define NV50_DISP_DAC_PWR                                            0x00020000
 209 #define NV50_DISP_DAC_PWR_HSYNC                                      0x00000001
 210 #define NV50_DISP_DAC_PWR_HSYNC_ON                                   0x00000000
 211 #define NV50_DISP_DAC_PWR_HSYNC_LO                                   0x00000001
 212 #define NV50_DISP_DAC_PWR_VSYNC                                      0x00000004
 213 #define NV50_DISP_DAC_PWR_VSYNC_ON                                   0x00000000
 214 #define NV50_DISP_DAC_PWR_VSYNC_LO                                   0x00000004
 215 #define NV50_DISP_DAC_PWR_DATA                                       0x00000010
 216 #define NV50_DISP_DAC_PWR_DATA_ON                                    0x00000000
 217 #define NV50_DISP_DAC_PWR_DATA_LO                                    0x00000010
 218 #define NV50_DISP_DAC_PWR_STATE                                      0x00000040
 219 #define NV50_DISP_DAC_PWR_STATE_ON                                   0x00000000
 220 #define NV50_DISP_DAC_PWR_STATE_OFF                                  0x00000040
 221 #define NV50_DISP_DAC_LOAD                                           0x00020100
 222 #define NV50_DISP_DAC_LOAD_VALUE                                     0x00000007
 223
 224 #define NV50_DISP_PIOR_MTHD                                          0x00030000
 225 #define NV50_DISP_PIOR_MTHD_TYPE                                     0x0000f000
 226 #define NV50_DISP_PIOR_MTHD_OR                                       0x00000003
 227
 228 #define NV50_DISP_PIOR_PWR                                           0x00030000
 229 #define NV50_DISP_PIOR_PWR_STATE                                     0x00000001
 230 #define NV50_DISP_PIOR_PWR_STATE_ON                                  0x00000001
 231 #define NV50_DISP_PIOR_PWR_STATE_OFF                                 0x00000000
 232 #define NV50_DISP_PIOR_TMDS_PWR                                      0x00032000
 233 #define NV50_DISP_PIOR_TMDS_PWR_STATE                                0x00000001
 234 #define NV50_DISP_PIOR_TMDS_PWR_STATE_ON                             0x00000001
 235 #define NV50_DISP_PIOR_TMDS_PWR_STATE_OFF                            0x00000000
 236 #define NV50_DISP_PIOR_DP_PWR                                        0x00036000
 237 #define NV50_DISP_PIOR_DP_PWR_STATE                                  0x00000001
 238 #define NV50_DISP_PIOR_DP_PWR_STATE_ON                               0x00000001
 239 #define NV50_DISP_PIOR_DP_PWR_STATE_OFF                              0x00000000
 240
 241 struct nv50_display_class {
 242 };
 243
 244 /* 507a: NV50_DISP_CURS
 245  * 827a: NV84_DISP_CURS
 246  * 837a: NVA0_DISP_CURS
 247  * 887a: NV94_DISP_CURS
 248  * 857a: NVA3_DISP_CURS
 249  * 907a: NVD0_DISP_CURS
 250  * 917a: NVE0_DISP_CURS
 251  * 927a: NVF0_DISP_CURS
 252  */
 253
 254 #define NV50_DISP_CURS_CLASS                                         0x0000507a
 255 #define NV84_DISP_CURS_CLASS                                         0x0000827a
 256 #define NVA0_DISP_CURS_CLASS                                         0x0000837a
 257 #define NV94_DISP_CURS_CLASS                                         0x0000887a
 258 #define NVA3_DISP_CURS_CLASS                                         0x0000857a
 259 #define NVD0_DISP_CURS_CLASS                                         0x0000907a
 260 #define NVE0_DISP_CURS_CLASS                                         0x0000917a
 261 #define NVF0_DISP_CURS_CLASS                                         0x0000927a
 262
 263 struct nv50_display_curs_class {
 264         u32 head;
 265 };
 266
 267 /* 507b: NV50_DISP_OIMM
 268  * 827b: NV84_DISP_OIMM
 269  * 837b: NVA0_DISP_OIMM
 270  * 887b: NV94_DISP_OIMM
 271  * 857b: NVA3_DISP_OIMM
 272  * 907b: NVD0_DISP_OIMM
 273  * 917b: NVE0_DISP_OIMM
 274  * 927b: NVE0_DISP_OIMM
 275  */
 276
 277 #define NV50_DISP_OIMM_CLASS                                         0x0000507b
 278 #define NV84_DISP_OIMM_CLASS                                         0x0000827b
 279 #define NVA0_DISP_OIMM_CLASS                                         0x0000837b
 280 #define NV94_DISP_OIMM_CLASS                                         0x0000887b
 281 #define NVA3_DISP_OIMM_CLASS                                         0x0000857b
 282 #define NVD0_DISP_OIMM_CLASS                                         0x0000907b
 283 #define NVE0_DISP_OIMM_CLASS                                         0x0000917b
 284 #define NVF0_DISP_OIMM_CLASS                                         0x0000927b
 285
 286 struct nv50_display_oimm_class {
 287         u32 head;
 288 };
 289
 290 /* 507c: NV50_DISP_SYNC
 291  * 827c: NV84_DISP_SYNC
 292  * 837c: NVA0_DISP_SYNC
 293  * 887c: NV94_DISP_SYNC
 294  * 857c: NVA3_DISP_SYNC
 295  * 907c: NVD0_DISP_SYNC
 296  * 917c: NVE0_DISP_SYNC
 297  * 927c: NVF0_DISP_SYNC
 298  */
 299
 300 #define NV50_DISP_SYNC_CLASS                                         0x0000507c
 301 #define NV84_DISP_SYNC_CLASS                                         0x0000827c
 302 #define NVA0_DISP_SYNC_CLASS                                         0x0000837c
 303 #define NV94_DISP_SYNC_CLASS                                         0x0000887c
 304 #define NVA3_DISP_SYNC_CLASS                                         0x0000857c
 305 #define NVD0_DISP_SYNC_CLASS                                         0x0000907c
 306 #define NVE0_DISP_SYNC_CLASS                                         0x0000917c
 307 #define NVF0_DISP_SYNC_CLASS                                         0x0000927c
 308
 309 struct nv50_display_sync_class {
 310         u32 pushbuf;
 311         u32 head;
 312 };
 313
 314 /* 507d: NV50_DISP_MAST
 315  * 827d: NV84_DISP_MAST
 316  * 837d: NVA0_DISP_MAST
 317  * 887d: NV94_DISP_MAST
 318  * 857d: NVA3_DISP_MAST
 319  * 907d: NVD0_DISP_MAST
 320  * 917d: NVE0_DISP_MAST
 321  * 927d: NVF0_DISP_MAST
 322  */
 323
 324 #define NV50_DISP_MAST_CLASS                                         0x0000507d
 325 #define NV84_DISP_MAST_CLASS                                         0x0000827d
 326 #define NVA0_DISP_MAST_CLASS                                         0x0000837d
 327 #define NV94_DISP_MAST_CLASS                                         0x0000887d
 328 #define NVA3_DISP_MAST_CLASS                                         0x0000857d
 329 #define NVD0_DISP_MAST_CLASS                                         0x0000907d
 330 #define NVE0_DISP_MAST_CLASS                                         0x0000917d
 331 #define NVF0_DISP_MAST_CLASS                                         0x0000927d
 332
 333 struct nv50_display_mast_class {
 334         u32 pushbuf;
 335 };
 336
 337 /* 507e: NV50_DISP_OVLY
 338  * 827e: NV84_DISP_OVLY
 339  * 837e: NVA0_DISP_OVLY
 340  * 887e: NV94_DISP_OVLY
 341  * 857e: NVA3_DISP_OVLY
 342  * 907e: NVD0_DISP_OVLY
 343  * 917e: NVE0_DISP_OVLY
 344  * 927e: NVF0_DISP_OVLY
 345  */
 346
 347 #define NV50_DISP_OVLY_CLASS                                         0x0000507e
 348 #define NV84_DISP_OVLY_CLASS                                         0x0000827e
 349 #define NVA0_DISP_OVLY_CLASS                                         0x0000837e
 350 #define NV94_DISP_OVLY_CLASS                                         0x0000887e
 351 #define NVA3_DISP_OVLY_CLASS                                         0x0000857e
 352 #define NVD0_DISP_OVLY_CLASS                                         0x0000907e
 353 #define NVE0_DISP_OVLY_CLASS                                         0x0000917e
 354 #define NVF0_DISP_OVLY_CLASS                                         0x0000927e
 355
 356 struct nv50_display_ovly_class {
 357         u32 pushbuf;
 358         u32 head;
 359 };
 360
 361 #endif