Pileus Git - ~andy/linux/blob - drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c

   1 /*
   2  * Copyright 2010 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <linux/firmware.h>
  26 #include <linux/module.h>
  27
  28 #include "drmP.h"
  29
  30 #include "nouveau_drv.h"
  31 #include <core/mm.h>
  32 #include <engine/fifo.h>
  33
  34 #include "nvc0.h"
  35 #include "fuc/hubnvc0.fuc.h"
  36 #include "fuc/gpcnvc0.fuc.h"
  37
  38 static void
  39 nvc0_graph_ctxctl_debug_unit(struct drm_device *dev, u32 base)
  40 {
  41         NV_INFO(dev, "PGRAPH: %06x - done 0x%08x\n", base,
  42                 nv_rd32(dev, base + 0x400));
  43         NV_INFO(dev, "PGRAPH: %06x - stat 0x%08x 0x%08x 0x%08x 0x%08x\n", base,
  44                 nv_rd32(dev, base + 0x800), nv_rd32(dev, base + 0x804),
  45                 nv_rd32(dev, base + 0x808), nv_rd32(dev, base + 0x80c));
  46         NV_INFO(dev, "PGRAPH: %06x - stat 0x%08x 0x%08x 0x%08x 0x%08x\n", base,
  47                 nv_rd32(dev, base + 0x810), nv_rd32(dev, base + 0x814),
  48                 nv_rd32(dev, base + 0x818), nv_rd32(dev, base + 0x81c));
  49 }
  50
  51 void
  52 nvc0_graph_ctxctl_debug(struct drm_device *dev)
  53 {
  54         u32 gpcnr = nv_rd32(dev, 0x409604) & 0xffff;
  55         u32 gpc;
  56
  57         nvc0_graph_ctxctl_debug_unit(dev, 0x409000);
  58         for (gpc = 0; gpc < gpcnr; gpc++)
  59                 nvc0_graph_ctxctl_debug_unit(dev, 0x502000 + (gpc * 0x8000));
  60 }
  61
  62 int
  63 nvc0_graph_context_new(struct nouveau_channel *chan, int engine)
  64 {
  65         struct drm_device *dev = chan->dev;
  66         struct nvc0_graph_priv *priv = nv_engine(dev, engine);
  67         struct nvc0_graph_data *data = priv->mmio_data;
  68         struct nvc0_graph_mmio *mmio = priv->mmio_list;
  69         struct nvc0_graph_chan *grch;
  70         struct nouveau_gpuobj *grctx;
  71         int ret, i;
  72
  73         grch = kzalloc(sizeof(*grch), GFP_KERNEL);
  74         if (!grch)
  75                 return -ENOMEM;
  76         chan->engctx[NVOBJ_ENGINE_GR] = grch;
  77
  78         ret = nouveau_gpuobj_new(dev, NULL, priv->size, 256, 0, &grch->grctx);
  79         if (ret)
  80                 goto error;
  81
  82         ret = nouveau_gpuobj_map_vm(grch->grctx, chan->vm, NV_MEM_ACCESS_RW |
  83                                     NV_MEM_ACCESS_SYS, &grch->grctx_vma);
  84         if (ret)
  85                 return ret;
  86
  87         grctx = grch->grctx;
  88
  89         /* allocate memory for a "mmio list" buffer that's used by the HUB
  90          * fuc to modify some per-context register settings on first load
  91          * of the context.
  92          */
  93         ret = nouveau_gpuobj_new(dev, NULL, 0x1000, 0x100, 0, &grch->mmio);
  94         if (ret)
  95                 return ret;
  96
  97         ret = nouveau_gpuobj_map_vm(grch->mmio, chan->vm,
  98                                     NV_MEM_ACCESS_RW | NV_MEM_ACCESS_SYS,
  99                                     &grch->mmio_vma);
 100         if (ret)
 101                 return ret;
 102
 103         /* allocate buffers referenced by mmio list */
 104         for (i = 0; data->size && i < ARRAY_SIZE(priv->mmio_data); i++) {
 105                 ret = nouveau_gpuobj_new(dev, NULL, data->size, data->align,
 106                                          0, &grch->data[i].mem);
 107                 if (ret)
 108                         return ret;
 109
 110                 ret = nouveau_gpuobj_map_vm(grch->data[i].mem, chan->vm,
 111                                             data->access,
 112                                            &grch->data[i].vma);
 113                 if (ret)
 114                         return ret;
 115
 116                 data++;
 117         }
 118
 119         /* finally, fill in the mmio list and point the context at it */
 120         for (i = 0; mmio->addr && i < ARRAY_SIZE(priv->mmio_list); i++) {
 121                 u32 addr = mmio->addr;
 122                 u32 data = mmio->data;
 123
 124                 if (mmio->shift) {
 125                         u64 info = grch->data[mmio->buffer].vma.offset;
 126                         data |= info >> mmio->shift;
 127                 }
 128
 129                 nv_wo32(grch->mmio, grch->mmio_nr++ * 4, addr);
 130                 nv_wo32(grch->mmio, grch->mmio_nr++ * 4, data);
 131                 mmio++;
 132         }
 133
 134         for (i = 0; i < priv->size; i += 4)
 135                 nv_wo32(grch->grctx, i, priv->data[i / 4]);
 136
 137         nv_wo32(chan->ramin, 0x0210, lower_32_bits(grch->grctx_vma.offset) | 4);
 138         nv_wo32(chan->ramin, 0x0214, upper_32_bits(grch->grctx_vma.offset));
 139         nvimem_flush(dev);
 140
 141         if (!priv->firmware) {
 142                 nv_wo32(grctx, 0x00, grch->mmio_nr / 2);
 143                 nv_wo32(grctx, 0x04, grch->mmio_vma.offset >> 8);
 144         } else {
 145                 nv_wo32(grctx, 0xf4, 0);
 146                 nv_wo32(grctx, 0xf8, 0);
 147                 nv_wo32(grctx, 0x10, grch->mmio_nr / 2);
 148                 nv_wo32(grctx, 0x14, lower_32_bits(grch->mmio_vma.offset));
 149                 nv_wo32(grctx, 0x18, upper_32_bits(grch->mmio_vma.offset));
 150                 nv_wo32(grctx, 0x1c, 1);
 151                 nv_wo32(grctx, 0x20, 0);
 152                 nv_wo32(grctx, 0x28, 0);
 153                 nv_wo32(grctx, 0x2c, 0);
 154         }
 155         nvimem_flush(dev);
 156         return 0;
 157
 158 error:
 159         priv->base.context_del(chan, engine);
 160         return ret;
 161 }
 162
 163 void
 164 nvc0_graph_context_del(struct nouveau_channel *chan, int engine)
 165 {
 166         struct nvc0_graph_chan *grch = chan->engctx[engine];
 167         int i;
 168
 169         for (i = 0; i < ARRAY_SIZE(grch->data); i++) {
 170                 nouveau_gpuobj_unmap(&grch->data[i].vma);
 171                 nouveau_gpuobj_ref(NULL, &grch->data[i].mem);
 172         }
 173
 174         nouveau_gpuobj_unmap(&grch->mmio_vma);
 175         nouveau_gpuobj_ref(NULL, &grch->mmio);
 176
 177         nouveau_gpuobj_unmap(&grch->grctx_vma);
 178         nouveau_gpuobj_ref(NULL, &grch->grctx);
 179         chan->engctx[engine] = NULL;
 180 }
 181
 182 static int
 183 nvc0_graph_object_new(struct nouveau_channel *chan, int engine,
 184                       u32 handle, u16 class)
 185 {
 186         return 0;
 187 }
 188
 189 static int
 190 nvc0_graph_fini(struct drm_device *dev, int engine, bool suspend)
 191 {
 192         return 0;
 193 }
 194
 195 static void
 196 nvc0_graph_init_obj418880(struct drm_device *dev)
 197 {
 198         struct nvc0_graph_priv *priv = nv_engine(dev, NVOBJ_ENGINE_GR);
 199         int i;
 200
 201         nv_wr32(dev, GPC_BCAST(0x0880), 0x00000000);
 202         nv_wr32(dev, GPC_BCAST(0x08a4), 0x00000000);
 203         for (i = 0; i < 4; i++)
 204                 nv_wr32(dev, GPC_BCAST(0x0888) + (i * 4), 0x00000000);
 205         nv_wr32(dev, GPC_BCAST(0x08b4), priv->unk4188b4->addr >> 8);
 206         nv_wr32(dev, GPC_BCAST(0x08b8), priv->unk4188b8->addr >> 8);
 207 }
 208
 209 static void
 210 nvc0_graph_init_regs(struct drm_device *dev)
 211 {
 212         nv_wr32(dev, 0x400080, 0x003083c2);
 213         nv_wr32(dev, 0x400088, 0x00006fe7);
 214         nv_wr32(dev, 0x40008c, 0x00000000);
 215         nv_wr32(dev, 0x400090, 0x00000030);
 216         nv_wr32(dev, 0x40013c, 0x013901f7);
 217         nv_wr32(dev, 0x400140, 0x00000100);
 218         nv_wr32(dev, 0x400144, 0x00000000);
 219         nv_wr32(dev, 0x400148, 0x00000110);
 220         nv_wr32(dev, 0x400138, 0x00000000);
 221         nv_wr32(dev, 0x400130, 0x00000000);
 222         nv_wr32(dev, 0x400134, 0x00000000);
 223         nv_wr32(dev, 0x400124, 0x00000002);
 224 }
 225
 226 static void
 227 nvc0_graph_init_gpc_0(struct drm_device *dev)
 228 {
 229         struct nvc0_graph_priv *priv = nv_engine(dev, NVOBJ_ENGINE_GR);
 230         const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, priv->tpc_total);
 231         u32 data[TPC_MAX / 8];
 232         u8  tpnr[GPC_MAX];
 233         int i, gpc, tpc;
 234
 235         nv_wr32(dev, TPC_UNIT(0, 0, 0x5c), 1); /* affects TFB offset queries */
 236
 237         /*
 238          *      TP      ROP UNKVAL(magic_not_rop_nr)
 239          * 450: 4/0/0/0 2        3
 240          * 460: 3/4/0/0 4        1
 241          * 465: 3/4/4/0 4        7
 242          * 470: 3/3/4/4 5        5
 243          * 480: 3/4/4/4 6        6
 244          */
 245
 246         memset(data, 0x00, sizeof(data));
 247         memcpy(tpnr, priv->tpc_nr, sizeof(priv->tpc_nr));
 248         for (i = 0, gpc = -1; i < priv->tpc_total; i++) {
 249                 do {
 250                         gpc = (gpc + 1) % priv->gpc_nr;
 251                 } while (!tpnr[gpc]);
 252                 tpc = priv->tpc_nr[gpc] - tpnr[gpc]--;
 253
 254                 data[i / 8] |= tpc << ((i % 8) * 4);
 255         }
 256
 257         nv_wr32(dev, GPC_BCAST(0x0980), data[0]);
 258         nv_wr32(dev, GPC_BCAST(0x0984), data[1]);
 259         nv_wr32(dev, GPC_BCAST(0x0988), data[2]);
 260         nv_wr32(dev, GPC_BCAST(0x098c), data[3]);
 261
 262         for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
 263                 nv_wr32(dev, GPC_UNIT(gpc, 0x0914), priv->magic_not_rop_nr << 8 |
 264                                                   priv->tpc_nr[gpc]);
 265                 nv_wr32(dev, GPC_UNIT(gpc, 0x0910), 0x00040000 | priv->tpc_total);
 266                 nv_wr32(dev, GPC_UNIT(gpc, 0x0918), magicgpc918);
 267         }
 268
 269         nv_wr32(dev, GPC_BCAST(0x1bd4), magicgpc918);
 270         nv_wr32(dev, GPC_BCAST(0x08ac), nv_rd32(dev, 0x100800));
 271 }
 272
 273 static void
 274 nvc0_graph_init_units(struct drm_device *dev)
 275 {
 276         nv_wr32(dev, 0x409c24, 0x000f0000);
 277         nv_wr32(dev, 0x404000, 0xc0000000); /* DISPATCH */
 278         nv_wr32(dev, 0x404600, 0xc0000000); /* M2MF */
 279         nv_wr32(dev, 0x408030, 0xc0000000);
 280         nv_wr32(dev, 0x40601c, 0xc0000000);
 281         nv_wr32(dev, 0x404490, 0xc0000000); /* MACRO */
 282         nv_wr32(dev, 0x406018, 0xc0000000);
 283         nv_wr32(dev, 0x405840, 0xc0000000);
 284         nv_wr32(dev, 0x405844, 0x00ffffff);
 285         nv_mask(dev, 0x419cc0, 0x00000008, 0x00000008);
 286         nv_mask(dev, 0x419eb4, 0x00001000, 0x00001000);
 287 }
 288
 289 static void
 290 nvc0_graph_init_gpc_1(struct drm_device *dev)
 291 {
 292         struct nvc0_graph_priv *priv = nv_engine(dev, NVOBJ_ENGINE_GR);
 293         int gpc, tp;
 294
 295         for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
 296                 nv_wr32(dev, GPC_UNIT(gpc, 0x0420), 0xc0000000);
 297                 nv_wr32(dev, GPC_UNIT(gpc, 0x0900), 0xc0000000);
 298                 nv_wr32(dev, GPC_UNIT(gpc, 0x1028), 0xc0000000);
 299                 nv_wr32(dev, GPC_UNIT(gpc, 0x0824), 0xc0000000);
 300                 for (tp = 0; tp < priv->tpc_nr[gpc]; tp++) {
 301                         nv_wr32(dev, TPC_UNIT(gpc, tp, 0x508), 0xffffffff);
 302                         nv_wr32(dev, TPC_UNIT(gpc, tp, 0x50c), 0xffffffff);
 303                         nv_wr32(dev, TPC_UNIT(gpc, tp, 0x224), 0xc0000000);
 304                         nv_wr32(dev, TPC_UNIT(gpc, tp, 0x48c), 0xc0000000);
 305                         nv_wr32(dev, TPC_UNIT(gpc, tp, 0x084), 0xc0000000);
 306                         nv_wr32(dev, TPC_UNIT(gpc, tp, 0x644), 0x001ffffe);
 307                         nv_wr32(dev, TPC_UNIT(gpc, tp, 0x64c), 0x0000000f);
 308                 }
 309                 nv_wr32(dev, GPC_UNIT(gpc, 0x2c90), 0xffffffff);
 310                 nv_wr32(dev, GPC_UNIT(gpc, 0x2c94), 0xffffffff);
 311         }
 312 }
 313
 314 static void
 315 nvc0_graph_init_rop(struct drm_device *dev)
 316 {
 317         struct nvc0_graph_priv *priv = nv_engine(dev, NVOBJ_ENGINE_GR);
 318         int rop;
 319
 320         for (rop = 0; rop < priv->rop_nr; rop++) {
 321                 nv_wr32(dev, ROP_UNIT(rop, 0x144), 0xc0000000);
 322                 nv_wr32(dev, ROP_UNIT(rop, 0x070), 0xc0000000);
 323                 nv_wr32(dev, ROP_UNIT(rop, 0x204), 0xffffffff);
 324                 nv_wr32(dev, ROP_UNIT(rop, 0x208), 0xffffffff);
 325         }
 326 }
 327
 328 static void
 329 nvc0_graph_init_fuc(struct drm_device *dev, u32 fuc_base,
 330                     struct nvc0_graph_fuc *code, struct nvc0_graph_fuc *data)
 331 {
 332         int i;
 333
 334         nv_wr32(dev, fuc_base + 0x01c0, 0x01000000);
 335         for (i = 0; i < data->size / 4; i++)
 336                 nv_wr32(dev, fuc_base + 0x01c4, data->data[i]);
 337
 338         nv_wr32(dev, fuc_base + 0x0180, 0x01000000);
 339         for (i = 0; i < code->size / 4; i++) {
 340                 if ((i & 0x3f) == 0)
 341                         nv_wr32(dev, fuc_base + 0x0188, i >> 6);
 342                 nv_wr32(dev, fuc_base + 0x0184, code->data[i]);
 343         }
 344 }
 345
 346 static int
 347 nvc0_graph_init_ctxctl(struct drm_device *dev)
 348 {
 349         struct drm_nouveau_private *dev_priv = dev->dev_private;
 350         struct nvc0_graph_priv *priv = nv_engine(dev, NVOBJ_ENGINE_GR);
 351         u32 r000260;
 352         int i;
 353
 354         if (priv->firmware) {
 355                 /* load fuc microcode */
 356                 r000260 = nv_mask(dev, 0x000260, 0x00000001, 0x00000000);
 357                 nvc0_graph_init_fuc(dev, 0x409000, &priv->fuc409c,
 358                                                    &priv->fuc409d);
 359                 nvc0_graph_init_fuc(dev, 0x41a000, &priv->fuc41ac,
 360                                                    &priv->fuc41ad);
 361                 nv_wr32(dev, 0x000260, r000260);
 362
 363                 /* start both of them running */
 364                 nv_wr32(dev, 0x409840, 0xffffffff);
 365                 nv_wr32(dev, 0x41a10c, 0x00000000);
 366                 nv_wr32(dev, 0x40910c, 0x00000000);
 367                 nv_wr32(dev, 0x41a100, 0x00000002);
 368                 nv_wr32(dev, 0x409100, 0x00000002);
 369                 if (!nv_wait(dev, 0x409800, 0x00000001, 0x00000001))
 370                         NV_INFO(dev, "0x409800 wait failed\n");
 371
 372                 nv_wr32(dev, 0x409840, 0xffffffff);
 373                 nv_wr32(dev, 0x409500, 0x7fffffff);
 374                 nv_wr32(dev, 0x409504, 0x00000021);
 375
 376                 nv_wr32(dev, 0x409840, 0xffffffff);
 377                 nv_wr32(dev, 0x409500, 0x00000000);
 378                 nv_wr32(dev, 0x409504, 0x00000010);
 379                 if (!nv_wait_ne(dev, 0x409800, 0xffffffff, 0x00000000)) {
 380                         NV_ERROR(dev, "fuc09 req 0x10 timeout\n");
 381                         return -EBUSY;
 382                 }
 383                 priv->size = nv_rd32(dev, 0x409800);
 384
 385                 nv_wr32(dev, 0x409840, 0xffffffff);
 386                 nv_wr32(dev, 0x409500, 0x00000000);
 387                 nv_wr32(dev, 0x409504, 0x00000016);
 388                 if (!nv_wait_ne(dev, 0x409800, 0xffffffff, 0x00000000)) {
 389                         NV_ERROR(dev, "fuc09 req 0x16 timeout\n");
 390                         return -EBUSY;
 391                 }
 392
 393                 nv_wr32(dev, 0x409840, 0xffffffff);
 394                 nv_wr32(dev, 0x409500, 0x00000000);
 395                 nv_wr32(dev, 0x409504, 0x00000025);
 396                 if (!nv_wait_ne(dev, 0x409800, 0xffffffff, 0x00000000)) {
 397                         NV_ERROR(dev, "fuc09 req 0x25 timeout\n");
 398                         return -EBUSY;
 399                 }
 400
 401                 goto done;
 402         }
 403
 404         /* load HUB microcode */
 405         r000260 = nv_mask(dev, 0x000260, 0x00000001, 0x00000000);
 406         nv_wr32(dev, 0x4091c0, 0x01000000);
 407         for (i = 0; i < sizeof(nvc0_grhub_data) / 4; i++)
 408                 nv_wr32(dev, 0x4091c4, nvc0_grhub_data[i]);
 409
 410         nv_wr32(dev, 0x409180, 0x01000000);
 411         for (i = 0; i < sizeof(nvc0_grhub_code) / 4; i++) {
 412                 if ((i & 0x3f) == 0)
 413                         nv_wr32(dev, 0x409188, i >> 6);
 414                 nv_wr32(dev, 0x409184, nvc0_grhub_code[i]);
 415         }
 416
 417         /* load GPC microcode */
 418         nv_wr32(dev, 0x41a1c0, 0x01000000);
 419         for (i = 0; i < sizeof(nvc0_grgpc_data) / 4; i++)
 420                 nv_wr32(dev, 0x41a1c4, nvc0_grgpc_data[i]);
 421
 422         nv_wr32(dev, 0x41a180, 0x01000000);
 423         for (i = 0; i < sizeof(nvc0_grgpc_code) / 4; i++) {
 424                 if ((i & 0x3f) == 0)
 425                         nv_wr32(dev, 0x41a188, i >> 6);
 426                 nv_wr32(dev, 0x41a184, nvc0_grgpc_code[i]);
 427         }
 428         nv_wr32(dev, 0x000260, r000260);
 429
 430         /* start HUB ucode running, it'll init the GPCs */
 431         nv_wr32(dev, 0x409800, dev_priv->chipset);
 432         nv_wr32(dev, 0x40910c, 0x00000000);
 433         nv_wr32(dev, 0x409100, 0x00000002);
 434         if (!nv_wait(dev, 0x409800, 0x80000000, 0x80000000)) {
 435                 NV_ERROR(dev, "PGRAPH: HUB_INIT timed out\n");
 436                 nvc0_graph_ctxctl_debug(dev);
 437                 return -EBUSY;
 438         }
 439
 440         priv->size = nv_rd32(dev, 0x409804);
 441 done:
 442         if (priv->data == NULL) {
 443                 int ret = nvc0_grctx_generate(dev);
 444                 if (ret) {
 445                         NV_ERROR(dev, "PGRAPH: failed to construct context\n");
 446                         return ret;
 447                 }
 448
 449                 return 1;
 450         }
 451
 452         return 0;
 453 }
 454
 455 static int
 456 nvc0_graph_init(struct drm_device *dev, int engine)
 457 {
 458         int ret;
 459
 460 reset:
 461         nv_mask(dev, 0x000200, 0x18001000, 0x00000000);
 462         nv_mask(dev, 0x000200, 0x18001000, 0x18001000);
 463
 464         nvc0_graph_init_obj418880(dev);
 465         nvc0_graph_init_regs(dev);
 466         /*nvc0_graph_init_unitplemented_magics(dev);*/
 467         nvc0_graph_init_gpc_0(dev);
 468         /*nvc0_graph_init_unitplemented_c242(dev);*/
 469
 470         nv_wr32(dev, 0x400500, 0x00010001);
 471         nv_wr32(dev, 0x400100, 0xffffffff);
 472         nv_wr32(dev, 0x40013c, 0xffffffff);
 473
 474         nvc0_graph_init_units(dev);
 475         nvc0_graph_init_gpc_1(dev);
 476         nvc0_graph_init_rop(dev);
 477
 478         nv_wr32(dev, 0x400108, 0xffffffff);
 479         nv_wr32(dev, 0x400138, 0xffffffff);
 480         nv_wr32(dev, 0x400118, 0xffffffff);
 481         nv_wr32(dev, 0x400130, 0xffffffff);
 482         nv_wr32(dev, 0x40011c, 0xffffffff);
 483         nv_wr32(dev, 0x400134, 0xffffffff);
 484         nv_wr32(dev, 0x400054, 0x34ce3464);
 485
 486         ret = nvc0_graph_init_ctxctl(dev);
 487         if (ret) {
 488                 if (ret == 1)
 489                         goto reset;
 490                 return ret;
 491         }
 492
 493         return 0;
 494 }
 495
 496 int
 497 nvc0_graph_isr_chid(struct drm_device *dev, u64 inst)
 498 {
 499         struct nouveau_fifo_priv *pfifo = nv_engine(dev, NVOBJ_ENGINE_FIFO);
 500         struct drm_nouveau_private *dev_priv = dev->dev_private;
 501         struct nouveau_channel *chan;
 502         unsigned long flags;
 503         int i;
 504
 505         spin_lock_irqsave(&dev_priv->channels.lock, flags);
 506         for (i = 0; i < pfifo->channels; i++) {
 507                 chan = dev_priv->channels.ptr[i];
 508                 if (!chan || !chan->ramin)
 509                         continue;
 510
 511                 if (inst == chan->ramin->addr)
 512                         break;
 513         }
 514         spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
 515         return i;
 516 }
 517
 518 static void
 519 nvc0_graph_ctxctl_isr(struct drm_device *dev)
 520 {
 521         u32 ustat = nv_rd32(dev, 0x409c18);
 522
 523         if (ustat & 0x00000001)
 524                 NV_INFO(dev, "PGRAPH: CTXCTRL ucode error\n");
 525         if (ustat & 0x00080000)
 526                 NV_INFO(dev, "PGRAPH: CTXCTRL watchdog timeout\n");
 527         if (ustat & ~0x00080001)
 528                 NV_INFO(dev, "PGRAPH: CTXCTRL 0x%08x\n", ustat);
 529
 530         nvc0_graph_ctxctl_debug(dev);
 531         nv_wr32(dev, 0x409c20, ustat);
 532 }
 533
 534 static void
 535 nvc0_graph_isr(struct drm_device *dev)
 536 {
 537         u64 inst = (u64)(nv_rd32(dev, 0x409b00) & 0x0fffffff) << 12;
 538         u32 chid = nvc0_graph_isr_chid(dev, inst);
 539         u32 stat = nv_rd32(dev, 0x400100);
 540         u32 addr = nv_rd32(dev, 0x400704);
 541         u32 mthd = (addr & 0x00003ffc);
 542         u32 subc = (addr & 0x00070000) >> 16;
 543         u32 data = nv_rd32(dev, 0x400708);
 544         u32 code = nv_rd32(dev, 0x400110);
 545         u32 class = nv_rd32(dev, 0x404200 + (subc * 4));
 546
 547         if (stat & 0x00000010) {
 548                 if (nouveau_gpuobj_mthd_call2(dev, chid, class, mthd, data)) {
 549                         NV_INFO(dev, "PGRAPH: ILLEGAL_MTHD ch %d [0x%010llx] "
 550                                      "subc %d class 0x%04x mthd 0x%04x "
 551                                      "data 0x%08x\n",
 552                                 chid, inst, subc, class, mthd, data);
 553                 }
 554                 nv_wr32(dev, 0x400100, 0x00000010);
 555                 stat &= ~0x00000010;
 556         }
 557
 558         if (stat & 0x00000020) {
 559                 NV_INFO(dev, "PGRAPH: ILLEGAL_CLASS ch %d [0x%010llx] subc %d "
 560                              "class 0x%04x mthd 0x%04x data 0x%08x\n",
 561                         chid, inst, subc, class, mthd, data);
 562                 nv_wr32(dev, 0x400100, 0x00000020);
 563                 stat &= ~0x00000020;
 564         }
 565
 566         if (stat & 0x00100000) {
 567                 NV_INFO(dev, "PGRAPH: DATA_ERROR [");
 568                 nouveau_enum_print(nv50_data_error_names, code);
 569                 printk("] ch %d [0x%010llx] subc %d class 0x%04x "
 570                        "mthd 0x%04x data 0x%08x\n",
 571                        chid, inst, subc, class, mthd, data);
 572                 nv_wr32(dev, 0x400100, 0x00100000);
 573                 stat &= ~0x00100000;
 574         }
 575
 576         if (stat & 0x00200000) {
 577                 u32 trap = nv_rd32(dev, 0x400108);
 578                 NV_INFO(dev, "PGRAPH: TRAP ch %d status 0x%08x\n", chid, trap);
 579                 nv_wr32(dev, 0x400108, trap);
 580                 nv_wr32(dev, 0x400100, 0x00200000);
 581                 stat &= ~0x00200000;
 582         }
 583
 584         if (stat & 0x00080000) {
 585                 nvc0_graph_ctxctl_isr(dev);
 586                 nv_wr32(dev, 0x400100, 0x00080000);
 587                 stat &= ~0x00080000;
 588         }
 589
 590         if (stat) {
 591                 NV_INFO(dev, "PGRAPH: unknown stat 0x%08x\n", stat);
 592                 nv_wr32(dev, 0x400100, stat);
 593         }
 594
 595         nv_wr32(dev, 0x400500, 0x00010001);
 596 }
 597
 598 static int
 599 nvc0_graph_create_fw(struct drm_device *dev, const char *fwname,
 600                      struct nvc0_graph_fuc *fuc)
 601 {
 602         struct drm_nouveau_private *dev_priv = dev->dev_private;
 603         const struct firmware *fw;
 604         char f[32];
 605         int ret;
 606
 607         snprintf(f, sizeof(f), "nouveau/nv%02x_%s", dev_priv->chipset, fwname);
 608         ret = request_firmware(&fw, f, &dev->pdev->dev);
 609         if (ret) {
 610                 snprintf(f, sizeof(f), "nouveau/%s", fwname);
 611                 ret = request_firmware(&fw, f, &dev->pdev->dev);
 612                 if (ret) {
 613                         NV_ERROR(dev, "failed to load %s\n", fwname);
 614                         return ret;
 615                 }
 616         }
 617
 618         fuc->size = fw->size;
 619         fuc->data = kmemdup(fw->data, fuc->size, GFP_KERNEL);
 620         release_firmware(fw);
 621         return (fuc->data != NULL) ? 0 : -ENOMEM;
 622 }
 623
 624 static void
 625 nvc0_graph_destroy_fw(struct nvc0_graph_fuc *fuc)
 626 {
 627         if (fuc->data) {
 628                 kfree(fuc->data);
 629                 fuc->data = NULL;
 630         }
 631 }
 632
 633 static void
 634 nvc0_graph_destroy(struct drm_device *dev, int engine)
 635 {
 636         struct nvc0_graph_priv *priv = nv_engine(dev, engine);
 637
 638         nvc0_graph_destroy_fw(&priv->fuc409c);
 639         nvc0_graph_destroy_fw(&priv->fuc409d);
 640         nvc0_graph_destroy_fw(&priv->fuc41ac);
 641         nvc0_graph_destroy_fw(&priv->fuc41ad);
 642
 643         nouveau_irq_unregister(dev, 12);
 644
 645         nouveau_gpuobj_ref(NULL, &priv->unk4188b8);
 646         nouveau_gpuobj_ref(NULL, &priv->unk4188b4);
 647
 648         if (priv->data)
 649                 kfree(priv->data);
 650
 651         NVOBJ_ENGINE_DEL(dev, GR);
 652         kfree(priv);
 653 }
 654
 655 int
 656 nvc0_graph_create(struct drm_device *dev)
 657 {
 658         struct drm_nouveau_private *dev_priv = dev->dev_private;
 659         struct nvc0_graph_priv *priv;
 660         int ret, gpc, i;
 661         u32 fermi;
 662
 663         fermi = nvc0_graph_class(dev);
 664         if (!fermi) {
 665                 NV_ERROR(dev, "PGRAPH: unsupported chipset, please report!\n");
 666                 return 0;
 667         }
 668
 669         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 670         if (!priv)
 671                 return -ENOMEM;
 672
 673         priv->base.destroy = nvc0_graph_destroy;
 674         priv->base.init = nvc0_graph_init;
 675         priv->base.fini = nvc0_graph_fini;
 676         priv->base.context_new = nvc0_graph_context_new;
 677         priv->base.context_del = nvc0_graph_context_del;
 678         priv->base.object_new = nvc0_graph_object_new;
 679
 680         NVOBJ_ENGINE_ADD(dev, GR, &priv->base);
 681         nouveau_irq_register(dev, 12, nvc0_graph_isr);
 682
 683         if (nouveau_ctxfw) {
 684                 NV_INFO(dev, "PGRAPH: using external firmware\n");
 685                 if (nvc0_graph_create_fw(dev, "fuc409c", &priv->fuc409c) ||
 686                     nvc0_graph_create_fw(dev, "fuc409d", &priv->fuc409d) ||
 687                     nvc0_graph_create_fw(dev, "fuc41ac", &priv->fuc41ac) ||
 688                     nvc0_graph_create_fw(dev, "fuc41ad", &priv->fuc41ad)) {
 689                         ret = 0;
 690                         goto error;
 691                 }
 692                 priv->firmware = true;
 693         }
 694
 695         ret = nouveau_gpuobj_new(dev, NULL, 0x1000, 256, 0, &priv->unk4188b4);
 696         if (ret)
 697                 goto error;
 698
 699         ret = nouveau_gpuobj_new(dev, NULL, 0x1000, 256, 0, &priv->unk4188b8);
 700         if (ret)
 701                 goto error;
 702
 703         for (i = 0; i < 0x1000; i += 4) {
 704                 nv_wo32(priv->unk4188b4, i, 0x00000010);
 705                 nv_wo32(priv->unk4188b8, i, 0x00000010);
 706         }
 707
 708         priv->gpc_nr  =  nv_rd32(dev, 0x409604) & 0x0000001f;
 709         priv->rop_nr = (nv_rd32(dev, 0x409604) & 0x001f0000) >> 16;
 710         for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
 711                 priv->tpc_nr[gpc] = nv_rd32(dev, GPC_UNIT(gpc, 0x2608));
 712                 priv->tpc_total += priv->tpc_nr[gpc];
 713         }
 714
 715         /*XXX: these need figuring out... */
 716         switch (dev_priv->chipset) {
 717         case 0xc0:
 718                 if (priv->tpc_total == 11) { /* 465, 3/4/4/0, 4 */
 719                         priv->magic_not_rop_nr = 0x07;
 720                 } else
 721                 if (priv->tpc_total == 14) { /* 470, 3/3/4/4, 5 */
 722                         priv->magic_not_rop_nr = 0x05;
 723                 } else
 724                 if (priv->tpc_total == 15) { /* 480, 3/4/4/4, 6 */
 725                         priv->magic_not_rop_nr = 0x06;
 726                 }
 727                 break;
 728         case 0xc3: /* 450, 4/0/0/0, 2 */
 729                 priv->magic_not_rop_nr = 0x03;
 730                 break;
 731         case 0xc4: /* 460, 3/4/0/0, 4 */
 732                 priv->magic_not_rop_nr = 0x01;
 733                 break;
 734         case 0xc1: /* 2/0/0/0, 1 */
 735                 priv->magic_not_rop_nr = 0x01;
 736                 break;
 737         case 0xc8: /* 4/4/3/4, 5 */
 738                 priv->magic_not_rop_nr = 0x06;
 739                 break;
 740         case 0xce: /* 4/4/0/0, 4 */
 741                 priv->magic_not_rop_nr = 0x03;
 742                 break;
 743         case 0xcf: /* 4/0/0/0, 3 */
 744                 priv->magic_not_rop_nr = 0x03;
 745                 break;
 746         case 0xd9: /* 1/0/0/0, 1 */
 747                 priv->magic_not_rop_nr = 0x01;
 748                 break;
 749         }
 750
 751         if (!priv->magic_not_rop_nr) {
 752                 NV_ERROR(dev, "PGRAPH: unknown config: %d/%d/%d/%d, %d\n",
 753                          priv->tpc_nr[0], priv->tpc_nr[1], priv->tpc_nr[2],
 754                          priv->tpc_nr[3], priv->rop_nr);
 755                 priv->magic_not_rop_nr = 0x00;
 756         }
 757
 758         NVOBJ_CLASS(dev, 0x902d, GR); /* 2D */
 759         NVOBJ_CLASS(dev, 0x9039, GR); /* M2MF */
 760         NVOBJ_CLASS(dev, 0x9097, GR); /* 3D */
 761         if (fermi >= 0x9197)
 762                 NVOBJ_CLASS(dev, 0x9197, GR); /* 3D (NVC1-) */
 763         if (fermi >= 0x9297)
 764                 NVOBJ_CLASS(dev, 0x9297, GR); /* 3D (NVC8-) */
 765         NVOBJ_CLASS(dev, 0x90c0, GR); /* COMPUTE */
 766         return 0;
 767
 768 error:
 769         nvc0_graph_destroy(dev, NVOBJ_ENGINE_GR);
 770         return ret;
 771 }