Pileus Git - ~andy/linux/blob - drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <core/client.h>
  26 #include <core/handle.h>
  27 #include <core/namedb.h>
  28 #include <core/gpuobj.h>
  29 #include <core/engctx.h>
  30 #include <core/event.h>
  31 #include <core/class.h>
  32 #include <core/enum.h>
  33
  34 #include <subdev/timer.h>
  35 #include <subdev/bar.h>
  36 #include <subdev/vm.h>
  37
  38 #include <engine/dmaobj.h>
  39 #include <engine/fifo.h>
  40
  41 #define _(a,b) { (a), ((1ULL << (a)) | (b)) }
  42 static const struct {
  43         u64 subdev;
  44         u64 mask;
  45 } fifo_engine[] = {
  46         _(NVDEV_ENGINE_GR      , (1ULL << NVDEV_ENGINE_SW) |
  47                                  (1ULL << NVDEV_ENGINE_COPY2)),
  48         _(NVDEV_ENGINE_VP      , 0),
  49         _(NVDEV_ENGINE_PPP     , 0),
  50         _(NVDEV_ENGINE_BSP     , 0),
  51         _(NVDEV_ENGINE_COPY0   , 0),
  52         _(NVDEV_ENGINE_COPY1   , 0),
  53         _(NVDEV_ENGINE_VENC    , 0),
  54 };
  55 #undef _
  56 #define FIFO_ENGINE_NR ARRAY_SIZE(fifo_engine)
  57
  58 struct nve0_fifo_engn {
  59         struct nouveau_gpuobj *playlist[2];
  60         int cur_playlist;
  61 };
  62
  63 struct nve0_fifo_priv {
  64         struct nouveau_fifo base;
  65         struct nve0_fifo_engn engine[FIFO_ENGINE_NR];
  66         struct {
  67                 struct nouveau_gpuobj *mem;
  68                 struct nouveau_vma bar;
  69         } user;
  70         int spoon_nr;
  71 };
  72
  73 struct nve0_fifo_base {
  74         struct nouveau_fifo_base base;
  75         struct nouveau_gpuobj *pgd;
  76         struct nouveau_vm *vm;
  77 };
  78
  79 struct nve0_fifo_chan {
  80         struct nouveau_fifo_chan base;
  81         u32 engine;
  82 };
  83
  84 /*******************************************************************************
  85  * FIFO channel objects
  86  ******************************************************************************/
  87
  88 static void
  89 nve0_fifo_playlist_update(struct nve0_fifo_priv *priv, u32 engine)
  90 {
  91         struct nouveau_bar *bar = nouveau_bar(priv);
  92         struct nve0_fifo_engn *engn = &priv->engine[engine];
  93         struct nouveau_gpuobj *cur;
  94         u32 match = (engine << 16) | 0x00000001;
  95         int i, p;
  96
  97         mutex_lock(&nv_subdev(priv)->mutex);
  98         cur = engn->playlist[engn->cur_playlist];
  99         engn->cur_playlist = !engn->cur_playlist;
 100
 101         for (i = 0, p = 0; i < priv->base.max; i++) {
 102                 u32 ctrl = nv_rd32(priv, 0x800004 + (i * 8)) & 0x001f0001;
 103                 if (ctrl != match)
 104                         continue;
 105                 nv_wo32(cur, p + 0, i);
 106                 nv_wo32(cur, p + 4, 0x00000000);
 107                 p += 8;
 108         }
 109         bar->flush(bar);
 110
 111         nv_wr32(priv, 0x002270, cur->addr >> 12);
 112         nv_wr32(priv, 0x002274, (engine << 20) | (p >> 3));
 113         if (!nv_wait(priv, 0x002284 + (engine * 4), 0x00100000, 0x00000000))
 114                 nv_error(priv, "playlist %d update timeout\n", engine);
 115         mutex_unlock(&nv_subdev(priv)->mutex);
 116 }
 117
 118 static int
 119 nve0_fifo_context_attach(struct nouveau_object *parent,
 120                          struct nouveau_object *object)
 121 {
 122         struct nouveau_bar *bar = nouveau_bar(parent);
 123         struct nve0_fifo_base *base = (void *)parent->parent;
 124         struct nouveau_engctx *ectx = (void *)object;
 125         u32 addr;
 126         int ret;
 127
 128         switch (nv_engidx(object->engine)) {
 129         case NVDEV_ENGINE_SW   :
 130         case NVDEV_ENGINE_COPY0:
 131         case NVDEV_ENGINE_COPY1:
 132         case NVDEV_ENGINE_COPY2:
 133                 return 0;
 134         case NVDEV_ENGINE_GR   : addr = 0x0210; break;
 135         case NVDEV_ENGINE_BSP  : addr = 0x0270; break;
 136         case NVDEV_ENGINE_VP   : addr = 0x0250; break;
 137         case NVDEV_ENGINE_PPP  : addr = 0x0260; break;
 138         default:
 139                 return -EINVAL;
 140         }
 141
 142         if (!ectx->vma.node) {
 143                 ret = nouveau_gpuobj_map_vm(nv_gpuobj(ectx), base->vm,
 144                                             NV_MEM_ACCESS_RW, &ectx->vma);
 145                 if (ret)
 146                         return ret;
 147
 148                 nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12;
 149         }
 150
 151         nv_wo32(base, addr + 0x00, lower_32_bits(ectx->vma.offset) | 4);
 152         nv_wo32(base, addr + 0x04, upper_32_bits(ectx->vma.offset));
 153         bar->flush(bar);
 154         return 0;
 155 }
 156
 157 static int
 158 nve0_fifo_context_detach(struct nouveau_object *parent, bool suspend,
 159                          struct nouveau_object *object)
 160 {
 161         struct nouveau_bar *bar = nouveau_bar(parent);
 162         struct nve0_fifo_priv *priv = (void *)parent->engine;
 163         struct nve0_fifo_base *base = (void *)parent->parent;
 164         struct nve0_fifo_chan *chan = (void *)parent;
 165         u32 addr;
 166
 167         switch (nv_engidx(object->engine)) {
 168         case NVDEV_ENGINE_SW   : return 0;
 169         case NVDEV_ENGINE_COPY0:
 170         case NVDEV_ENGINE_COPY1:
 171         case NVDEV_ENGINE_COPY2: addr = 0x0000; break;
 172         case NVDEV_ENGINE_GR   : addr = 0x0210; break;
 173         case NVDEV_ENGINE_BSP  : addr = 0x0270; break;
 174         case NVDEV_ENGINE_VP   : addr = 0x0250; break;
 175         case NVDEV_ENGINE_PPP  : addr = 0x0260; break;
 176         default:
 177                 return -EINVAL;
 178         }
 179
 180         nv_wr32(priv, 0x002634, chan->base.chid);
 181         if (!nv_wait(priv, 0x002634, 0xffffffff, chan->base.chid)) {
 182                 nv_error(priv, "channel %d [%s] kick timeout\n",
 183                          chan->base.chid, nouveau_client_name(chan));
 184                 if (suspend)
 185                         return -EBUSY;
 186         }
 187
 188         if (addr) {
 189                 nv_wo32(base, addr + 0x00, 0x00000000);
 190                 nv_wo32(base, addr + 0x04, 0x00000000);
 191                 bar->flush(bar);
 192         }
 193
 194         return 0;
 195 }
 196
 197 static int
 198 nve0_fifo_chan_ctor(struct nouveau_object *parent,
 199                     struct nouveau_object *engine,
 200                     struct nouveau_oclass *oclass, void *data, u32 size,
 201                     struct nouveau_object **pobject)
 202 {
 203         struct nouveau_bar *bar = nouveau_bar(parent);
 204         struct nve0_fifo_priv *priv = (void *)engine;
 205         struct nve0_fifo_base *base = (void *)parent;
 206         struct nve0_fifo_chan *chan;
 207         struct nve0_channel_ind_class *args = data;
 208         u64 usermem, ioffset, ilength;
 209         int ret, i;
 210
 211         if (size < sizeof(*args))
 212                 return -EINVAL;
 213
 214         for (i = 0; i < FIFO_ENGINE_NR; i++) {
 215                 if (args->engine & (1 << i)) {
 216                         if (nouveau_engine(parent, fifo_engine[i].subdev)) {
 217                                 args->engine = (1 << i);
 218                                 break;
 219                         }
 220                 }
 221         }
 222
 223         if (i == FIFO_ENGINE_NR) {
 224                 nv_error(priv, "unsupported engines 0x%08x\n", args->engine);
 225                 return -ENODEV;
 226         }
 227
 228         ret = nouveau_fifo_channel_create(parent, engine, oclass, 1,
 229                                           priv->user.bar.offset, 0x200,
 230                                           args->pushbuf,
 231                                           fifo_engine[i].mask, &chan);
 232         *pobject = nv_object(chan);
 233         if (ret)
 234                 return ret;
 235
 236         nv_parent(chan)->context_attach = nve0_fifo_context_attach;
 237         nv_parent(chan)->context_detach = nve0_fifo_context_detach;
 238         chan->engine = i;
 239
 240         usermem = chan->base.chid * 0x200;
 241         ioffset = args->ioffset;
 242         ilength = order_base_2(args->ilength / 8);
 243
 244         for (i = 0; i < 0x200; i += 4)
 245                 nv_wo32(priv->user.mem, usermem + i, 0x00000000);
 246
 247         nv_wo32(base, 0x08, lower_32_bits(priv->user.mem->addr + usermem));
 248         nv_wo32(base, 0x0c, upper_32_bits(priv->user.mem->addr + usermem));
 249         nv_wo32(base, 0x10, 0x0000face);
 250         nv_wo32(base, 0x30, 0xfffff902);
 251         nv_wo32(base, 0x48, lower_32_bits(ioffset));
 252         nv_wo32(base, 0x4c, upper_32_bits(ioffset) | (ilength << 16));
 253         nv_wo32(base, 0x84, 0x20400000);
 254         nv_wo32(base, 0x94, 0x30000001);
 255         nv_wo32(base, 0x9c, 0x00000100);
 256         nv_wo32(base, 0xac, 0x0000001f);
 257         nv_wo32(base, 0xe8, chan->base.chid);
 258         nv_wo32(base, 0xb8, 0xf8000000);
 259         nv_wo32(base, 0xf8, 0x10003080); /* 0x002310 */
 260         nv_wo32(base, 0xfc, 0x10000010); /* 0x002350 */
 261         bar->flush(bar);
 262         return 0;
 263 }
 264
 265 static int
 266 nve0_fifo_chan_init(struct nouveau_object *object)
 267 {
 268         struct nouveau_gpuobj *base = nv_gpuobj(object->parent);
 269         struct nve0_fifo_priv *priv = (void *)object->engine;
 270         struct nve0_fifo_chan *chan = (void *)object;
 271         u32 chid = chan->base.chid;
 272         int ret;
 273
 274         ret = nouveau_fifo_channel_init(&chan->base);
 275         if (ret)
 276                 return ret;
 277
 278         nv_mask(priv, 0x800004 + (chid * 8), 0x000f0000, chan->engine << 16);
 279         nv_wr32(priv, 0x800000 + (chid * 8), 0x80000000 | base->addr >> 12);
 280         nv_mask(priv, 0x800004 + (chid * 8), 0x00000400, 0x00000400);
 281         nve0_fifo_playlist_update(priv, chan->engine);
 282         nv_mask(priv, 0x800004 + (chid * 8), 0x00000400, 0x00000400);
 283         return 0;
 284 }
 285
 286 static int
 287 nve0_fifo_chan_fini(struct nouveau_object *object, bool suspend)
 288 {
 289         struct nve0_fifo_priv *priv = (void *)object->engine;
 290         struct nve0_fifo_chan *chan = (void *)object;
 291         u32 chid = chan->base.chid;
 292
 293         nv_mask(priv, 0x800004 + (chid * 8), 0x00000800, 0x00000800);
 294         nve0_fifo_playlist_update(priv, chan->engine);
 295         nv_wr32(priv, 0x800000 + (chid * 8), 0x00000000);
 296
 297         return nouveau_fifo_channel_fini(&chan->base, suspend);
 298 }
 299
 300 static struct nouveau_ofuncs
 301 nve0_fifo_ofuncs = {
 302         .ctor = nve0_fifo_chan_ctor,
 303         .dtor = _nouveau_fifo_channel_dtor,
 304         .init = nve0_fifo_chan_init,
 305         .fini = nve0_fifo_chan_fini,
 306         .rd32 = _nouveau_fifo_channel_rd32,
 307         .wr32 = _nouveau_fifo_channel_wr32,
 308 };
 309
 310 static struct nouveau_oclass
 311 nve0_fifo_sclass[] = {
 312         { NVE0_CHANNEL_IND_CLASS, &nve0_fifo_ofuncs },
 313         {}
 314 };
 315
 316 /*******************************************************************************
 317  * FIFO context - instmem heap and vm setup
 318  ******************************************************************************/
 319
 320 static int
 321 nve0_fifo_context_ctor(struct nouveau_object *parent,
 322                     struct nouveau_object *engine,
 323                     struct nouveau_oclass *oclass, void *data, u32 size,
 324                     struct nouveau_object **pobject)
 325 {
 326         struct nve0_fifo_base *base;
 327         int ret;
 328
 329         ret = nouveau_fifo_context_create(parent, engine, oclass, NULL, 0x1000,
 330                                           0x1000, NVOBJ_FLAG_ZERO_ALLOC, &base);
 331         *pobject = nv_object(base);
 332         if (ret)
 333                 return ret;
 334
 335         ret = nouveau_gpuobj_new(nv_object(base), NULL, 0x10000, 0x1000, 0,
 336                                 &base->pgd);
 337         if (ret)
 338                 return ret;
 339
 340         nv_wo32(base, 0x0200, lower_32_bits(base->pgd->addr));
 341         nv_wo32(base, 0x0204, upper_32_bits(base->pgd->addr));
 342         nv_wo32(base, 0x0208, 0xffffffff);
 343         nv_wo32(base, 0x020c, 0x000000ff);
 344
 345         ret = nouveau_vm_ref(nouveau_client(parent)->vm, &base->vm, base->pgd);
 346         if (ret)
 347                 return ret;
 348
 349         return 0;
 350 }
 351
 352 static void
 353 nve0_fifo_context_dtor(struct nouveau_object *object)
 354 {
 355         struct nve0_fifo_base *base = (void *)object;
 356         nouveau_vm_ref(NULL, &base->vm, base->pgd);
 357         nouveau_gpuobj_ref(NULL, &base->pgd);
 358         nouveau_fifo_context_destroy(&base->base);
 359 }
 360
 361 static struct nouveau_oclass
 362 nve0_fifo_cclass = {
 363         .handle = NV_ENGCTX(FIFO, 0xe0),
 364         .ofuncs = &(struct nouveau_ofuncs) {
 365                 .ctor = nve0_fifo_context_ctor,
 366                 .dtor = nve0_fifo_context_dtor,
 367                 .init = _nouveau_fifo_context_init,
 368                 .fini = _nouveau_fifo_context_fini,
 369                 .rd32 = _nouveau_fifo_context_rd32,
 370                 .wr32 = _nouveau_fifo_context_wr32,
 371         },
 372 };
 373
 374 /*******************************************************************************
 375  * PFIFO engine
 376  ******************************************************************************/
 377
 378 static const struct nouveau_enum nve0_fifo_fault_unit[] = {
 379         {}
 380 };
 381
 382 static const struct nouveau_enum nve0_fifo_fault_reason[] = {
 383         { 0x00, "PT_NOT_PRESENT" },
 384         { 0x01, "PT_TOO_SHORT" },
 385         { 0x02, "PAGE_NOT_PRESENT" },
 386         { 0x03, "VM_LIMIT_EXCEEDED" },
 387         { 0x04, "NO_CHANNEL" },
 388         { 0x05, "PAGE_SYSTEM_ONLY" },
 389         { 0x06, "PAGE_READ_ONLY" },
 390         { 0x0a, "COMPRESSED_SYSRAM" },
 391         { 0x0c, "INVALID_STORAGE_TYPE" },
 392         {}
 393 };
 394
 395 static const struct nouveau_enum nve0_fifo_fault_hubclient[] = {
 396         {}
 397 };
 398
 399 static const struct nouveau_enum nve0_fifo_fault_gpcclient[] = {
 400         {}
 401 };
 402
 403 static const struct nouveau_bitfield nve0_fifo_subfifo_intr[] = {
 404         { 0x00200000, "ILLEGAL_MTHD" },
 405         { 0x00800000, "EMPTY_SUBC" },
 406         {}
 407 };
 408
 409 static void
 410 nve0_fifo_isr_vm_fault(struct nve0_fifo_priv *priv, int unit)
 411 {
 412         u32 inst = nv_rd32(priv, 0x2800 + (unit * 0x10));
 413         u32 valo = nv_rd32(priv, 0x2804 + (unit * 0x10));
 414         u32 vahi = nv_rd32(priv, 0x2808 + (unit * 0x10));
 415         u32 stat = nv_rd32(priv, 0x280c + (unit * 0x10));
 416         u32 client = (stat & 0x00001f00) >> 8;
 417         const struct nouveau_enum *en;
 418         struct nouveau_engine *engine;
 419         struct nouveau_object *engctx = NULL;
 420
 421         nv_error(priv, "PFIFO: %s fault at 0x%010llx [", (stat & 0x00000080) ?
 422                        "write" : "read", (u64)vahi << 32 | valo);
 423         nouveau_enum_print(nve0_fifo_fault_reason, stat & 0x0000000f);
 424         pr_cont("] from ");
 425         en = nouveau_enum_print(nve0_fifo_fault_unit, unit);
 426         if (stat & 0x00000040) {
 427                 pr_cont("/");
 428                 nouveau_enum_print(nve0_fifo_fault_hubclient, client);
 429         } else {
 430                 pr_cont("/GPC%d/", (stat & 0x1f000000) >> 24);
 431                 nouveau_enum_print(nve0_fifo_fault_gpcclient, client);
 432         }
 433
 434         if (en && en->data2) {
 435                 engine = nouveau_engine(priv, en->data2);
 436                 if (engine)
 437                         engctx = nouveau_engctx_get(engine, inst);
 438
 439         }
 440
 441         pr_cont(" on channel 0x%010llx [%s]\n", (u64)inst << 12,
 442                         nouveau_client_name(engctx));
 443
 444         nouveau_engctx_put(engctx);
 445 }
 446
 447 static int
 448 nve0_fifo_swmthd(struct nve0_fifo_priv *priv, u32 chid, u32 mthd, u32 data)
 449 {
 450         struct nve0_fifo_chan *chan = NULL;
 451         struct nouveau_handle *bind;
 452         unsigned long flags;
 453         int ret = -EINVAL;
 454
 455         spin_lock_irqsave(&priv->base.lock, flags);
 456         if (likely(chid >= priv->base.min && chid <= priv->base.max))
 457                 chan = (void *)priv->base.channel[chid];
 458         if (unlikely(!chan))
 459                 goto out;
 460
 461         bind = nouveau_namedb_get_class(nv_namedb(chan), 0x906e);
 462         if (likely(bind)) {
 463                 if (!mthd || !nv_call(bind->object, mthd, data))
 464                         ret = 0;
 465                 nouveau_namedb_put(bind);
 466         }
 467
 468 out:
 469         spin_unlock_irqrestore(&priv->base.lock, flags);
 470         return ret;
 471 }
 472
 473 static void
 474 nve0_fifo_isr_subfifo_intr(struct nve0_fifo_priv *priv, int unit)
 475 {
 476         u32 stat = nv_rd32(priv, 0x040108 + (unit * 0x2000));
 477         u32 addr = nv_rd32(priv, 0x0400c0 + (unit * 0x2000));
 478         u32 data = nv_rd32(priv, 0x0400c4 + (unit * 0x2000));
 479         u32 chid = nv_rd32(priv, 0x040120 + (unit * 0x2000)) & 0xfff;
 480         u32 subc = (addr & 0x00070000) >> 16;
 481         u32 mthd = (addr & 0x00003ffc);
 482         u32 show = stat;
 483
 484         if (stat & 0x00800000) {
 485                 if (!nve0_fifo_swmthd(priv, chid, mthd, data))
 486                         show &= ~0x00800000;
 487         }
 488
 489         if (show) {
 490                 nv_error(priv, "SUBFIFO%d:", unit);
 491                 nouveau_bitfield_print(nve0_fifo_subfifo_intr, show);
 492                 pr_cont("\n");
 493                 nv_error(priv,
 494                          "SUBFIFO%d: ch %d [%s] subc %d mthd 0x%04x data 0x%08x\n",
 495                          unit, chid,
 496                          nouveau_client_name_for_fifo_chid(&priv->base, chid),
 497                          subc, mthd, data);
 498         }
 499
 500         nv_wr32(priv, 0x0400c0 + (unit * 0x2000), 0x80600008);
 501         nv_wr32(priv, 0x040108 + (unit * 0x2000), stat);
 502 }
 503
 504 static void
 505 nve0_fifo_intr(struct nouveau_subdev *subdev)
 506 {
 507         struct nve0_fifo_priv *priv = (void *)subdev;
 508         u32 mask = nv_rd32(priv, 0x002140);
 509         u32 stat = nv_rd32(priv, 0x002100) & mask;
 510
 511         if (stat & 0x00000100) {
 512                 nv_warn(priv, "unknown status 0x00000100\n");
 513                 nv_wr32(priv, 0x002100, 0x00000100);
 514                 stat &= ~0x00000100;
 515         }
 516
 517         if (stat & 0x10000000) {
 518                 u32 units = nv_rd32(priv, 0x00259c);
 519                 u32 u = units;
 520
 521                 while (u) {
 522                         int i = ffs(u) - 1;
 523                         nve0_fifo_isr_vm_fault(priv, i);
 524                         u &= ~(1 << i);
 525                 }
 526
 527                 nv_wr32(priv, 0x00259c, units);
 528                 stat &= ~0x10000000;
 529         }
 530
 531         if (stat & 0x20000000) {
 532                 u32 units = nv_rd32(priv, 0x0025a0);
 533                 u32 u = units;
 534
 535                 while (u) {
 536                         int i = ffs(u) - 1;
 537                         nve0_fifo_isr_subfifo_intr(priv, i);
 538                         u &= ~(1 << i);
 539                 }
 540
 541                 nv_wr32(priv, 0x0025a0, units);
 542                 stat &= ~0x20000000;
 543         }
 544
 545         if (stat & 0x40000000) {
 546                 nv_warn(priv, "unknown status 0x40000000\n");
 547                 nv_mask(priv, 0x002a00, 0x00000000, 0x00000000);
 548                 stat &= ~0x40000000;
 549         }
 550
 551         if (stat & 0x80000000) {
 552                 nouveau_event_trigger(priv->base.uevent, 0);
 553                 nv_wr32(priv, 0x002100, 0x80000000);
 554                 stat &= ~0x80000000;
 555         }
 556
 557         if (stat) {
 558                 nv_fatal(priv, "unhandled status 0x%08x\n", stat);
 559                 nv_wr32(priv, 0x002100, stat);
 560                 nv_wr32(priv, 0x002140, 0);
 561         }
 562 }
 563
 564 static void
 565 nve0_fifo_uevent_enable(struct nouveau_event *event, int index)
 566 {
 567         struct nve0_fifo_priv *priv = event->priv;
 568         nv_mask(priv, 0x002140, 0x80000000, 0x80000000);
 569 }
 570
 571 static void
 572 nve0_fifo_uevent_disable(struct nouveau_event *event, int index)
 573 {
 574         struct nve0_fifo_priv *priv = event->priv;
 575         nv_mask(priv, 0x002140, 0x80000000, 0x00000000);
 576 }
 577
 578 static int
 579 nve0_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 580                struct nouveau_oclass *oclass, void *data, u32 size,
 581                struct nouveau_object **pobject)
 582 {
 583         struct nve0_fifo_priv *priv;
 584         int ret, i;
 585
 586         ret = nouveau_fifo_create(parent, engine, oclass, 0, 4095, &priv);
 587         *pobject = nv_object(priv);
 588         if (ret)
 589                 return ret;
 590
 591         for (i = 0; i < FIFO_ENGINE_NR; i++) {
 592                 ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x8000, 0x1000,
 593                                          0, &priv->engine[i].playlist[0]);
 594                 if (ret)
 595                         return ret;
 596
 597                 ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x8000, 0x1000,
 598                                          0, &priv->engine[i].playlist[1]);
 599                 if (ret)
 600                         return ret;
 601         }
 602
 603         ret = nouveau_gpuobj_new(nv_object(priv), NULL, 4096 * 0x200, 0x1000,
 604                                  NVOBJ_FLAG_ZERO_ALLOC, &priv->user.mem);
 605         if (ret)
 606                 return ret;
 607
 608         ret = nouveau_gpuobj_map(priv->user.mem, NV_MEM_ACCESS_RW,
 609                                 &priv->user.bar);
 610         if (ret)
 611                 return ret;
 612
 613         priv->base.uevent->enable = nve0_fifo_uevent_enable;
 614         priv->base.uevent->disable = nve0_fifo_uevent_disable;
 615         priv->base.uevent->priv = priv;
 616
 617         nv_subdev(priv)->unit = 0x00000100;
 618         nv_subdev(priv)->intr = nve0_fifo_intr;
 619         nv_engine(priv)->cclass = &nve0_fifo_cclass;
 620         nv_engine(priv)->sclass = nve0_fifo_sclass;
 621         return 0;
 622 }
 623
 624 static void
 625 nve0_fifo_dtor(struct nouveau_object *object)
 626 {
 627         struct nve0_fifo_priv *priv = (void *)object;
 628         int i;
 629
 630         nouveau_gpuobj_unmap(&priv->user.bar);
 631         nouveau_gpuobj_ref(NULL, &priv->user.mem);
 632
 633         for (i = 0; i < FIFO_ENGINE_NR; i++) {
 634                 nouveau_gpuobj_ref(NULL, &priv->engine[i].playlist[1]);
 635                 nouveau_gpuobj_ref(NULL, &priv->engine[i].playlist[0]);
 636         }
 637
 638         nouveau_fifo_destroy(&priv->base);
 639 }
 640
 641 static int
 642 nve0_fifo_init(struct nouveau_object *object)
 643 {
 644         struct nve0_fifo_priv *priv = (void *)object;
 645         int ret, i;
 646
 647         ret = nouveau_fifo_init(&priv->base);
 648         if (ret)
 649                 return ret;
 650
 651         /* enable all available PSUBFIFOs */
 652         nv_wr32(priv, 0x000204, 0xffffffff);
 653         priv->spoon_nr = hweight32(nv_rd32(priv, 0x000204));
 654         nv_debug(priv, "%d subfifo(s)\n", priv->spoon_nr);
 655
 656         /* PSUBFIFO[n] */
 657         for (i = 0; i < priv->spoon_nr; i++) {
 658                 nv_mask(priv, 0x04013c + (i * 0x2000), 0x10000100, 0x00000000);
 659                 nv_wr32(priv, 0x040108 + (i * 0x2000), 0xffffffff); /* INTR */
 660                 nv_wr32(priv, 0x04010c + (i * 0x2000), 0xfffffeff); /* INTREN */
 661         }
 662
 663         nv_wr32(priv, 0x002254, 0x10000000 | priv->user.bar.offset >> 12);
 664
 665         nv_wr32(priv, 0x002a00, 0xffffffff);
 666         nv_wr32(priv, 0x002100, 0xffffffff);
 667         nv_wr32(priv, 0x002140, 0x3fffffff);
 668         return 0;
 669 }
 670
 671 struct nouveau_oclass *
 672 nve0_fifo_oclass = &(struct nouveau_oclass) {
 673         .handle = NV_ENGINE(FIFO, 0xe0),
 674         .ofuncs = &(struct nouveau_ofuncs) {
 675                 .ctor = nve0_fifo_ctor,
 676                 .dtor = nve0_fifo_dtor,
 677                 .init = nve0_fifo_init,
 678                 .fini = _nouveau_fifo_fini,
 679         },
 680 };