Pileus Git - ~andy/linux/blob - drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <core/client.h>
  26 #include <core/handle.h>
  27 #include <core/namedb.h>
  28 #include <core/gpuobj.h>
  29 #include <core/engctx.h>
  30 #include <core/event.h>
  31 #include <core/class.h>
  32 #include <core/math.h>
  33 #include <core/enum.h>
  34
  35 #include <subdev/timer.h>
  36 #include <subdev/bar.h>
  37 #include <subdev/vm.h>
  38
  39 #include <engine/dmaobj.h>
  40 #include <engine/fifo.h>
  41
  42 struct nvc0_fifo_priv {
  43         struct nouveau_fifo base;
  44         struct nouveau_gpuobj *playlist[2];
  45         int cur_playlist;
  46         struct {
  47                 struct nouveau_gpuobj *mem;
  48                 struct nouveau_vma bar;
  49         } user;
  50         int spoon_nr;
  51 };
  52
  53 struct nvc0_fifo_base {
  54         struct nouveau_fifo_base base;
  55         struct nouveau_gpuobj *pgd;
  56         struct nouveau_vm *vm;
  57 };
  58
  59 struct nvc0_fifo_chan {
  60         struct nouveau_fifo_chan base;
  61 };
  62
  63 /*******************************************************************************
  64  * FIFO channel objects
  65  ******************************************************************************/
  66
  67 static void
  68 nvc0_fifo_playlist_update(struct nvc0_fifo_priv *priv)
  69 {
  70         struct nouveau_bar *bar = nouveau_bar(priv);
  71         struct nouveau_gpuobj *cur;
  72         int i, p;
  73
  74         mutex_lock(&nv_subdev(priv)->mutex);
  75         cur = priv->playlist[priv->cur_playlist];
  76         priv->cur_playlist = !priv->cur_playlist;
  77
  78         for (i = 0, p = 0; i < 128; i++) {
  79                 if (!(nv_rd32(priv, 0x003004 + (i * 8)) & 1))
  80                         continue;
  81                 nv_wo32(cur, p + 0, i);
  82                 nv_wo32(cur, p + 4, 0x00000004);
  83                 p += 8;
  84         }
  85         bar->flush(bar);
  86
  87         nv_wr32(priv, 0x002270, cur->addr >> 12);
  88         nv_wr32(priv, 0x002274, 0x01f00000 | (p >> 3));
  89         if (!nv_wait(priv, 0x00227c, 0x00100000, 0x00000000))
  90                 nv_error(priv, "playlist update failed\n");
  91         mutex_unlock(&nv_subdev(priv)->mutex);
  92 }
  93
  94 static int
  95 nvc0_fifo_context_attach(struct nouveau_object *parent,
  96                          struct nouveau_object *object)
  97 {
  98         struct nouveau_bar *bar = nouveau_bar(parent);
  99         struct nvc0_fifo_base *base = (void *)parent->parent;
 100         struct nouveau_engctx *ectx = (void *)object;
 101         u32 addr;
 102         int ret;
 103
 104         switch (nv_engidx(object->engine)) {
 105         case NVDEV_ENGINE_SW   : return 0;
 106         case NVDEV_ENGINE_GR   : addr = 0x0210; break;
 107         case NVDEV_ENGINE_COPY0: addr = 0x0230; break;
 108         case NVDEV_ENGINE_COPY1: addr = 0x0240; break;
 109         case NVDEV_ENGINE_BSP  : addr = 0x0270; break;
 110         case NVDEV_ENGINE_VP   : addr = 0x0250; break;
 111         case NVDEV_ENGINE_PPP  : addr = 0x0260; break;
 112         default:
 113                 return -EINVAL;
 114         }
 115
 116         if (!ectx->vma.node) {
 117                 ret = nouveau_gpuobj_map_vm(nv_gpuobj(ectx), base->vm,
 118                                             NV_MEM_ACCESS_RW, &ectx->vma);
 119                 if (ret)
 120                         return ret;
 121
 122                 nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12;
 123         }
 124
 125         nv_wo32(base, addr + 0x00, lower_32_bits(ectx->vma.offset) | 4);
 126         nv_wo32(base, addr + 0x04, upper_32_bits(ectx->vma.offset));
 127         bar->flush(bar);
 128         return 0;
 129 }
 130
 131 static int
 132 nvc0_fifo_context_detach(struct nouveau_object *parent, bool suspend,
 133                          struct nouveau_object *object)
 134 {
 135         struct nouveau_bar *bar = nouveau_bar(parent);
 136         struct nvc0_fifo_priv *priv = (void *)parent->engine;
 137         struct nvc0_fifo_base *base = (void *)parent->parent;
 138         struct nvc0_fifo_chan *chan = (void *)parent;
 139         u32 addr;
 140
 141         switch (nv_engidx(object->engine)) {
 142         case NVDEV_ENGINE_SW   : return 0;
 143         case NVDEV_ENGINE_GR   : addr = 0x0210; break;
 144         case NVDEV_ENGINE_COPY0: addr = 0x0230; break;
 145         case NVDEV_ENGINE_COPY1: addr = 0x0240; break;
 146         case NVDEV_ENGINE_BSP  : addr = 0x0270; break;
 147         case NVDEV_ENGINE_VP   : addr = 0x0250; break;
 148         case NVDEV_ENGINE_PPP  : addr = 0x0260; break;
 149         default:
 150                 return -EINVAL;
 151         }
 152
 153         nv_wr32(priv, 0x002634, chan->base.chid);
 154         if (!nv_wait(priv, 0x002634, 0xffffffff, chan->base.chid)) {
 155                 nv_error(priv, "channel %d [%s] kick timeout\n",
 156                          chan->base.chid, nouveau_client_name(chan));
 157                 if (suspend)
 158                         return -EBUSY;
 159         }
 160
 161         nv_wo32(base, addr + 0x00, 0x00000000);
 162         nv_wo32(base, addr + 0x04, 0x00000000);
 163         bar->flush(bar);
 164         return 0;
 165 }
 166
 167 static int
 168 nvc0_fifo_chan_ctor(struct nouveau_object *parent,
 169                     struct nouveau_object *engine,
 170                     struct nouveau_oclass *oclass, void *data, u32 size,
 171                     struct nouveau_object **pobject)
 172 {
 173         struct nouveau_bar *bar = nouveau_bar(parent);
 174         struct nvc0_fifo_priv *priv = (void *)engine;
 175         struct nvc0_fifo_base *base = (void *)parent;
 176         struct nvc0_fifo_chan *chan;
 177         struct nv50_channel_ind_class *args = data;
 178         u64 usermem, ioffset, ilength;
 179         int ret, i;
 180
 181         if (size < sizeof(*args))
 182                 return -EINVAL;
 183
 184         ret = nouveau_fifo_channel_create(parent, engine, oclass, 1,
 185                                           priv->user.bar.offset, 0x1000,
 186                                           args->pushbuf,
 187                                           (1ULL << NVDEV_ENGINE_SW) |
 188                                           (1ULL << NVDEV_ENGINE_GR) |
 189                                           (1ULL << NVDEV_ENGINE_COPY0) |
 190                                           (1ULL << NVDEV_ENGINE_COPY1) |
 191                                           (1ULL << NVDEV_ENGINE_BSP) |
 192                                           (1ULL << NVDEV_ENGINE_VP) |
 193                                           (1ULL << NVDEV_ENGINE_PPP), &chan);
 194         *pobject = nv_object(chan);
 195         if (ret)
 196                 return ret;
 197
 198         nv_parent(chan)->context_attach = nvc0_fifo_context_attach;
 199         nv_parent(chan)->context_detach = nvc0_fifo_context_detach;
 200
 201         usermem = chan->base.chid * 0x1000;
 202         ioffset = args->ioffset;
 203         ilength = log2i(args->ilength / 8);
 204
 205         for (i = 0; i < 0x1000; i += 4)
 206                 nv_wo32(priv->user.mem, usermem + i, 0x00000000);
 207
 208         nv_wo32(base, 0x08, lower_32_bits(priv->user.mem->addr + usermem));
 209         nv_wo32(base, 0x0c, upper_32_bits(priv->user.mem->addr + usermem));
 210         nv_wo32(base, 0x10, 0x0000face);
 211         nv_wo32(base, 0x30, 0xfffff902);
 212         nv_wo32(base, 0x48, lower_32_bits(ioffset));
 213         nv_wo32(base, 0x4c, upper_32_bits(ioffset) | (ilength << 16));
 214         nv_wo32(base, 0x54, 0x00000002);
 215         nv_wo32(base, 0x84, 0x20400000);
 216         nv_wo32(base, 0x94, 0x30000001);
 217         nv_wo32(base, 0x9c, 0x00000100);
 218         nv_wo32(base, 0xa4, 0x1f1f1f1f);
 219         nv_wo32(base, 0xa8, 0x1f1f1f1f);
 220         nv_wo32(base, 0xac, 0x0000001f);
 221         nv_wo32(base, 0xb8, 0xf8000000);
 222         nv_wo32(base, 0xf8, 0x10003080); /* 0x002310 */
 223         nv_wo32(base, 0xfc, 0x10000010); /* 0x002350 */
 224         bar->flush(bar);
 225         return 0;
 226 }
 227
 228 static int
 229 nvc0_fifo_chan_init(struct nouveau_object *object)
 230 {
 231         struct nouveau_gpuobj *base = nv_gpuobj(object->parent);
 232         struct nvc0_fifo_priv *priv = (void *)object->engine;
 233         struct nvc0_fifo_chan *chan = (void *)object;
 234         u32 chid = chan->base.chid;
 235         int ret;
 236
 237         ret = nouveau_fifo_channel_init(&chan->base);
 238         if (ret)
 239                 return ret;
 240
 241         nv_wr32(priv, 0x003000 + (chid * 8), 0xc0000000 | base->addr >> 12);
 242         nv_wr32(priv, 0x003004 + (chid * 8), 0x001f0001);
 243         nvc0_fifo_playlist_update(priv);
 244         return 0;
 245 }
 246
 247 static int
 248 nvc0_fifo_chan_fini(struct nouveau_object *object, bool suspend)
 249 {
 250         struct nvc0_fifo_priv *priv = (void *)object->engine;
 251         struct nvc0_fifo_chan *chan = (void *)object;
 252         u32 chid = chan->base.chid;
 253         u32 mask, engine;
 254
 255         nv_mask(priv, 0x003004 + (chid * 8), 0x00000001, 0x00000000);
 256         nvc0_fifo_playlist_update(priv);
 257         mask = nv_rd32(priv, 0x0025a4);
 258         for (engine = 0; mask && engine < 16; engine++) {
 259                 if (!(mask & (1 << engine)))
 260                         continue;
 261                 nv_mask(priv, 0x0025a8 + (engine * 4), 0x00000000, 0x00000000);
 262                 mask &= ~(1 << engine);
 263         }
 264         nv_wr32(priv, 0x003000 + (chid * 8), 0x00000000);
 265
 266         return nouveau_fifo_channel_fini(&chan->base, suspend);
 267 }
 268
 269 static struct nouveau_ofuncs
 270 nvc0_fifo_ofuncs = {
 271         .ctor = nvc0_fifo_chan_ctor,
 272         .dtor = _nouveau_fifo_channel_dtor,
 273         .init = nvc0_fifo_chan_init,
 274         .fini = nvc0_fifo_chan_fini,
 275         .rd32 = _nouveau_fifo_channel_rd32,
 276         .wr32 = _nouveau_fifo_channel_wr32,
 277 };
 278
 279 static struct nouveau_oclass
 280 nvc0_fifo_sclass[] = {
 281         { NVC0_CHANNEL_IND_CLASS, &nvc0_fifo_ofuncs },
 282         {}
 283 };
 284
 285 /*******************************************************************************
 286  * FIFO context - instmem heap and vm setup
 287  ******************************************************************************/
 288
 289 static int
 290 nvc0_fifo_context_ctor(struct nouveau_object *parent,
 291                        struct nouveau_object *engine,
 292                        struct nouveau_oclass *oclass, void *data, u32 size,
 293                        struct nouveau_object **pobject)
 294 {
 295         struct nvc0_fifo_base *base;
 296         int ret;
 297
 298         ret = nouveau_fifo_context_create(parent, engine, oclass, NULL, 0x1000,
 299                                           0x1000, NVOBJ_FLAG_ZERO_ALLOC |
 300                                           NVOBJ_FLAG_HEAP, &base);
 301         *pobject = nv_object(base);
 302         if (ret)
 303                 return ret;
 304
 305         ret = nouveau_gpuobj_new(nv_object(base), NULL, 0x10000, 0x1000, 0,
 306                                 &base->pgd);
 307         if (ret)
 308                 return ret;
 309
 310         nv_wo32(base, 0x0200, lower_32_bits(base->pgd->addr));
 311         nv_wo32(base, 0x0204, upper_32_bits(base->pgd->addr));
 312         nv_wo32(base, 0x0208, 0xffffffff);
 313         nv_wo32(base, 0x020c, 0x000000ff);
 314
 315         ret = nouveau_vm_ref(nouveau_client(parent)->vm, &base->vm, base->pgd);
 316         if (ret)
 317                 return ret;
 318
 319         return 0;
 320 }
 321
 322 static void
 323 nvc0_fifo_context_dtor(struct nouveau_object *object)
 324 {
 325         struct nvc0_fifo_base *base = (void *)object;
 326         nouveau_vm_ref(NULL, &base->vm, base->pgd);
 327         nouveau_gpuobj_ref(NULL, &base->pgd);
 328         nouveau_fifo_context_destroy(&base->base);
 329 }
 330
 331 static struct nouveau_oclass
 332 nvc0_fifo_cclass = {
 333         .handle = NV_ENGCTX(FIFO, 0xc0),
 334         .ofuncs = &(struct nouveau_ofuncs) {
 335                 .ctor = nvc0_fifo_context_ctor,
 336                 .dtor = nvc0_fifo_context_dtor,
 337                 .init = _nouveau_fifo_context_init,
 338                 .fini = _nouveau_fifo_context_fini,
 339                 .rd32 = _nouveau_fifo_context_rd32,
 340                 .wr32 = _nouveau_fifo_context_wr32,
 341         },
 342 };
 343
 344 /*******************************************************************************
 345  * PFIFO engine
 346  ******************************************************************************/
 347
 348 static const struct nouveau_enum nvc0_fifo_fault_unit[] = {
 349         { 0x00, "PGRAPH", NULL, NVDEV_ENGINE_GR },
 350         { 0x03, "PEEPHOLE" },
 351         { 0x04, "BAR1" },
 352         { 0x05, "BAR3" },
 353         { 0x07, "PFIFO", NULL, NVDEV_ENGINE_FIFO },
 354         { 0x10, "PBSP", NULL, NVDEV_ENGINE_BSP },
 355         { 0x11, "PPPP", NULL, NVDEV_ENGINE_PPP },
 356         { 0x13, "PCOUNTER" },
 357         { 0x14, "PVP", NULL, NVDEV_ENGINE_VP },
 358         { 0x15, "PCOPY0", NULL, NVDEV_ENGINE_COPY0 },
 359         { 0x16, "PCOPY1", NULL, NVDEV_ENGINE_COPY1 },
 360         { 0x17, "PDAEMON" },
 361         {}
 362 };
 363
 364 static const struct nouveau_enum nvc0_fifo_fault_reason[] = {
 365         { 0x00, "PT_NOT_PRESENT" },
 366         { 0x01, "PT_TOO_SHORT" },
 367         { 0x02, "PAGE_NOT_PRESENT" },
 368         { 0x03, "VM_LIMIT_EXCEEDED" },
 369         { 0x04, "NO_CHANNEL" },
 370         { 0x05, "PAGE_SYSTEM_ONLY" },
 371         { 0x06, "PAGE_READ_ONLY" },
 372         { 0x0a, "COMPRESSED_SYSRAM" },
 373         { 0x0c, "INVALID_STORAGE_TYPE" },
 374         {}
 375 };
 376
 377 static const struct nouveau_enum nvc0_fifo_fault_hubclient[] = {
 378         { 0x01, "PCOPY0" },
 379         { 0x02, "PCOPY1" },
 380         { 0x04, "DISPATCH" },
 381         { 0x05, "CTXCTL" },
 382         { 0x06, "PFIFO" },
 383         { 0x07, "BAR_READ" },
 384         { 0x08, "BAR_WRITE" },
 385         { 0x0b, "PVP" },
 386         { 0x0c, "PPPP" },
 387         { 0x0d, "PBSP" },
 388         { 0x11, "PCOUNTER" },
 389         { 0x12, "PDAEMON" },
 390         { 0x14, "CCACHE" },
 391         { 0x15, "CCACHE_POST" },
 392         {}
 393 };
 394
 395 static const struct nouveau_enum nvc0_fifo_fault_gpcclient[] = {
 396         { 0x01, "TEX" },
 397         { 0x0c, "ESETUP" },
 398         { 0x0e, "CTXCTL" },
 399         { 0x0f, "PROP" },
 400         {}
 401 };
 402
 403 static const struct nouveau_bitfield nvc0_fifo_subfifo_intr[] = {
 404 /*      { 0x00008000, "" }      seen with null ib push */
 405         { 0x00200000, "ILLEGAL_MTHD" },
 406         { 0x00800000, "EMPTY_SUBC" },
 407         {}
 408 };
 409
 410 static void
 411 nvc0_fifo_isr_vm_fault(struct nvc0_fifo_priv *priv, int unit)
 412 {
 413         u32 inst = nv_rd32(priv, 0x002800 + (unit * 0x10));
 414         u32 valo = nv_rd32(priv, 0x002804 + (unit * 0x10));
 415         u32 vahi = nv_rd32(priv, 0x002808 + (unit * 0x10));
 416         u32 stat = nv_rd32(priv, 0x00280c + (unit * 0x10));
 417         u32 client = (stat & 0x00001f00) >> 8;
 418         const struct nouveau_enum *en;
 419         struct nouveau_engine *engine;
 420         struct nouveau_object *engctx = NULL;
 421
 422         switch (unit) {
 423         case 3: /* PEEPHOLE */
 424                 nv_mask(priv, 0x001718, 0x00000000, 0x00000000);
 425                 break;
 426         case 4: /* BAR1 */
 427                 nv_mask(priv, 0x001704, 0x00000000, 0x00000000);
 428                 break;
 429         case 5: /* BAR3 */
 430                 nv_mask(priv, 0x001714, 0x00000000, 0x00000000);
 431                 break;
 432         default:
 433                 break;
 434         }
 435
 436         nv_error(priv, "%s fault at 0x%010llx [", (stat & 0x00000080) ?
 437                  "write" : "read", (u64)vahi << 32 | valo);
 438         nouveau_enum_print(nvc0_fifo_fault_reason, stat & 0x0000000f);
 439         pr_cont("] from ");
 440         en = nouveau_enum_print(nvc0_fifo_fault_unit, unit);
 441         if (stat & 0x00000040) {
 442                 pr_cont("/");
 443                 nouveau_enum_print(nvc0_fifo_fault_hubclient, client);
 444         } else {
 445                 pr_cont("/GPC%d/", (stat & 0x1f000000) >> 24);
 446                 nouveau_enum_print(nvc0_fifo_fault_gpcclient, client);
 447         }
 448
 449         if (en && en->data2) {
 450                 engine = nouveau_engine(priv, en->data2);
 451                 if (engine)
 452                         engctx = nouveau_engctx_get(engine, inst);
 453
 454         }
 455         pr_cont(" on channel 0x%010llx [%s]\n", (u64)inst << 12,
 456                         nouveau_client_name(engctx));
 457
 458         nouveau_engctx_put(engctx);
 459 }
 460
 461 static int
 462 nvc0_fifo_swmthd(struct nvc0_fifo_priv *priv, u32 chid, u32 mthd, u32 data)
 463 {
 464         struct nvc0_fifo_chan *chan = NULL;
 465         struct nouveau_handle *bind;
 466         unsigned long flags;
 467         int ret = -EINVAL;
 468
 469         spin_lock_irqsave(&priv->base.lock, flags);
 470         if (likely(chid >= priv->base.min && chid <= priv->base.max))
 471                 chan = (void *)priv->base.channel[chid];
 472         if (unlikely(!chan))
 473                 goto out;
 474
 475         bind = nouveau_namedb_get_class(nv_namedb(chan), 0x906e);
 476         if (likely(bind)) {
 477                 if (!mthd || !nv_call(bind->object, mthd, data))
 478                         ret = 0;
 479                 nouveau_namedb_put(bind);
 480         }
 481
 482 out:
 483         spin_unlock_irqrestore(&priv->base.lock, flags);
 484         return ret;
 485 }
 486
 487 static void
 488 nvc0_fifo_isr_subfifo_intr(struct nvc0_fifo_priv *priv, int unit)
 489 {
 490         u32 stat = nv_rd32(priv, 0x040108 + (unit * 0x2000));
 491         u32 addr = nv_rd32(priv, 0x0400c0 + (unit * 0x2000));
 492         u32 data = nv_rd32(priv, 0x0400c4 + (unit * 0x2000));
 493         u32 chid = nv_rd32(priv, 0x040120 + (unit * 0x2000)) & 0x7f;
 494         u32 subc = (addr & 0x00070000) >> 16;
 495         u32 mthd = (addr & 0x00003ffc);
 496         u32 show = stat;
 497
 498         if (stat & 0x00200000) {
 499                 if (mthd == 0x0054) {
 500                         if (!nvc0_fifo_swmthd(priv, chid, 0x0500, 0x00000000))
 501                                 show &= ~0x00200000;
 502                 }
 503         }
 504
 505         if (stat & 0x00800000) {
 506                 if (!nvc0_fifo_swmthd(priv, chid, mthd, data))
 507                         show &= ~0x00800000;
 508         }
 509
 510         if (show) {
 511                 nv_error(priv, "SUBFIFO%d:", unit);
 512                 nouveau_bitfield_print(nvc0_fifo_subfifo_intr, show);
 513                 pr_cont("\n");
 514                 nv_error(priv,
 515                          "SUBFIFO%d: ch %d [%s] subc %d mthd 0x%04x data 0x%08x\n",
 516                          unit, chid,
 517                          nouveau_client_name_for_fifo_chid(&priv->base, chid),
 518                          subc, mthd, data);
 519         }
 520
 521         nv_wr32(priv, 0x0400c0 + (unit * 0x2000), 0x80600008);
 522         nv_wr32(priv, 0x040108 + (unit * 0x2000), stat);
 523 }
 524
 525 static void
 526 nvc0_fifo_intr(struct nouveau_subdev *subdev)
 527 {
 528         struct nvc0_fifo_priv *priv = (void *)subdev;
 529         u32 mask = nv_rd32(priv, 0x002140);
 530         u32 stat = nv_rd32(priv, 0x002100) & mask;
 531
 532         if (stat & 0x00000001) {
 533                 u32 intr = nv_rd32(priv, 0x00252c);
 534                 nv_warn(priv, "INTR 0x00000001: 0x%08x\n", intr);
 535                 nv_wr32(priv, 0x002100, 0x00000001);
 536                 stat &= ~0x00000001;
 537         }
 538
 539         if (stat & 0x00000100) {
 540                 u32 intr = nv_rd32(priv, 0x00254c);
 541                 nv_warn(priv, "INTR 0x00000100: 0x%08x\n", intr);
 542                 nv_wr32(priv, 0x002100, 0x00000100);
 543                 stat &= ~0x00000100;
 544         }
 545
 546         if (stat & 0x00010000) {
 547                 u32 intr = nv_rd32(priv, 0x00256c);
 548                 nv_warn(priv, "INTR 0x00010000: 0x%08x\n", intr);
 549                 nv_wr32(priv, 0x002100, 0x00010000);
 550                 stat &= ~0x00010000;
 551         }
 552
 553         if (stat & 0x01000000) {
 554                 u32 intr = nv_rd32(priv, 0x00258c);
 555                 nv_warn(priv, "INTR 0x01000000: 0x%08x\n", intr);
 556                 nv_wr32(priv, 0x002100, 0x01000000);
 557                 stat &= ~0x01000000;
 558         }
 559
 560         if (stat & 0x10000000) {
 561                 u32 units = nv_rd32(priv, 0x00259c);
 562                 u32 u = units;
 563
 564                 while (u) {
 565                         int i = ffs(u) - 1;
 566                         nvc0_fifo_isr_vm_fault(priv, i);
 567                         u &= ~(1 << i);
 568                 }
 569
 570                 nv_wr32(priv, 0x00259c, units);
 571                 stat &= ~0x10000000;
 572         }
 573
 574         if (stat & 0x20000000) {
 575                 u32 units = nv_rd32(priv, 0x0025a0);
 576                 u32 u = units;
 577
 578                 while (u) {
 579                         int i = ffs(u) - 1;
 580                         nvc0_fifo_isr_subfifo_intr(priv, i);
 581                         u &= ~(1 << i);
 582                 }
 583
 584                 nv_wr32(priv, 0x0025a0, units);
 585                 stat &= ~0x20000000;
 586         }
 587
 588         if (stat & 0x40000000) {
 589                 u32 intr0 = nv_rd32(priv, 0x0025a4);
 590                 u32 intr1 = nv_mask(priv, 0x002a00, 0x00000000, 0x00000);
 591                 nv_debug(priv, "INTR 0x40000000: 0x%08x 0x%08x\n",
 592                                intr0, intr1);
 593                 stat &= ~0x40000000;
 594         }
 595
 596         if (stat & 0x80000000) {
 597                 u32 intr = nv_mask(priv, 0x0025a8, 0x00000000, 0x00000000);
 598                 nouveau_event_trigger(priv->base.uevent, 0);
 599                 nv_debug(priv, "INTR 0x80000000: 0x%08x\n", intr);
 600                 stat &= ~0x80000000;
 601         }
 602
 603         if (stat) {
 604                 nv_fatal(priv, "unhandled status 0x%08x\n", stat);
 605                 nv_wr32(priv, 0x002100, stat);
 606                 nv_wr32(priv, 0x002140, 0);
 607         }
 608 }
 609
 610 static void
 611 nvc0_fifo_uevent_enable(struct nouveau_event *event, int index)
 612 {
 613         struct nvc0_fifo_priv *priv = event->priv;
 614         nv_mask(priv, 0x002140, 0x80000000, 0x80000000);
 615 }
 616
 617 static void
 618 nvc0_fifo_uevent_disable(struct nouveau_event *event, int index)
 619 {
 620         struct nvc0_fifo_priv *priv = event->priv;
 621         nv_mask(priv, 0x002140, 0x80000000, 0x00000000);
 622 }
 623
 624 static int
 625 nvc0_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 626                struct nouveau_oclass *oclass, void *data, u32 size,
 627                struct nouveau_object **pobject)
 628 {
 629         struct nvc0_fifo_priv *priv;
 630         int ret;
 631
 632         ret = nouveau_fifo_create(parent, engine, oclass, 0, 127, &priv);
 633         *pobject = nv_object(priv);
 634         if (ret)
 635                 return ret;
 636
 637         ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x1000, 0x1000, 0,
 638                                 &priv->playlist[0]);
 639         if (ret)
 640                 return ret;
 641
 642         ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x1000, 0x1000, 0,
 643                                 &priv->playlist[1]);
 644         if (ret)
 645                 return ret;
 646
 647         ret = nouveau_gpuobj_new(nv_object(priv), NULL, 128 * 0x1000, 0x1000, 0,
 648                                 &priv->user.mem);
 649         if (ret)
 650                 return ret;
 651
 652         ret = nouveau_gpuobj_map(priv->user.mem, NV_MEM_ACCESS_RW,
 653                                 &priv->user.bar);
 654         if (ret)
 655                 return ret;
 656
 657         priv->base.uevent->enable = nvc0_fifo_uevent_enable;
 658         priv->base.uevent->disable = nvc0_fifo_uevent_disable;
 659         priv->base.uevent->priv = priv;
 660
 661         nv_subdev(priv)->unit = 0x00000100;
 662         nv_subdev(priv)->intr = nvc0_fifo_intr;
 663         nv_engine(priv)->cclass = &nvc0_fifo_cclass;
 664         nv_engine(priv)->sclass = nvc0_fifo_sclass;
 665         return 0;
 666 }
 667
 668 static void
 669 nvc0_fifo_dtor(struct nouveau_object *object)
 670 {
 671         struct nvc0_fifo_priv *priv = (void *)object;
 672
 673         nouveau_gpuobj_unmap(&priv->user.bar);
 674         nouveau_gpuobj_ref(NULL, &priv->user.mem);
 675         nouveau_gpuobj_ref(NULL, &priv->playlist[1]);
 676         nouveau_gpuobj_ref(NULL, &priv->playlist[0]);
 677
 678         nouveau_fifo_destroy(&priv->base);
 679 }
 680
 681 static int
 682 nvc0_fifo_init(struct nouveau_object *object)
 683 {
 684         struct nvc0_fifo_priv *priv = (void *)object;
 685         int ret, i;
 686
 687         ret = nouveau_fifo_init(&priv->base);
 688         if (ret)
 689                 return ret;
 690
 691         nv_wr32(priv, 0x000204, 0xffffffff);
 692         nv_wr32(priv, 0x002204, 0xffffffff);
 693
 694         priv->spoon_nr = hweight32(nv_rd32(priv, 0x002204));
 695         nv_debug(priv, "%d subfifo(s)\n", priv->spoon_nr);
 696
 697         /* assign engines to subfifos */
 698         if (priv->spoon_nr >= 3) {
 699                 nv_wr32(priv, 0x002208, ~(1 << 0)); /* PGRAPH */
 700                 nv_wr32(priv, 0x00220c, ~(1 << 1)); /* PVP */
 701                 nv_wr32(priv, 0x002210, ~(1 << 1)); /* PPP */
 702                 nv_wr32(priv, 0x002214, ~(1 << 1)); /* PBSP */
 703                 nv_wr32(priv, 0x002218, ~(1 << 2)); /* PCE0 */
 704                 nv_wr32(priv, 0x00221c, ~(1 << 1)); /* PCE1 */
 705         }
 706
 707         /* PSUBFIFO[n] */
 708         for (i = 0; i < priv->spoon_nr; i++) {
 709                 nv_mask(priv, 0x04013c + (i * 0x2000), 0x10000100, 0x00000000);
 710                 nv_wr32(priv, 0x040108 + (i * 0x2000), 0xffffffff); /* INTR */
 711                 nv_wr32(priv, 0x04010c + (i * 0x2000), 0xfffffeff); /* INTREN */
 712         }
 713
 714         nv_mask(priv, 0x002200, 0x00000001, 0x00000001);
 715         nv_wr32(priv, 0x002254, 0x10000000 | priv->user.bar.offset >> 12);
 716
 717         nv_wr32(priv, 0x002a00, 0xffffffff); /* clears PFIFO.INTR bit 30 */
 718         nv_wr32(priv, 0x002100, 0xffffffff);
 719         nv_wr32(priv, 0x002140, 0x3fffffff);
 720         nv_wr32(priv, 0x002628, 0x00000001); /* makes mthd 0x20 work */
 721         return 0;
 722 }
 723
 724 struct nouveau_oclass
 725 nvc0_fifo_oclass = {
 726         .handle = NV_ENGINE(FIFO, 0xc0),
 727         .ofuncs = &(struct nouveau_ofuncs) {
 728                 .ctor = nvc0_fifo_ctor,
 729                 .dtor = nvc0_fifo_dtor,
 730                 .init = nvc0_fifo_init,
 731                 .fini = _nouveau_fifo_fini,
 732         },
 733 };