2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include <core/client.h>
27 #include <core/engctx.h>
28 #include <core/ramht.h>
29 #include <core/event.h>
30 #include <core/class.h>
31 #include <core/math.h>
33 #include <subdev/timer.h>
34 #include <subdev/bar.h>
36 #include <engine/dmaobj.h>
37 #include <engine/fifo.h>
41 /*******************************************************************************
42 * FIFO channel objects
43 ******************************************************************************/
46 nv84_fifo_context_attach(struct nouveau_object *parent,
47 struct nouveau_object *object)
49 struct nouveau_bar *bar = nouveau_bar(parent);
50 struct nv50_fifo_base *base = (void *)parent->parent;
51 struct nouveau_gpuobj *ectx = (void *)object;
52 u64 limit = ectx->addr + ectx->size - 1;
53 u64 start = ectx->addr;
56 switch (nv_engidx(object->engine)) {
57 case NVDEV_ENGINE_SW : return 0;
58 case NVDEV_ENGINE_GR : addr = 0x0020; break;
59 case NVDEV_ENGINE_VP : addr = 0x0040; break;
60 case NVDEV_ENGINE_MPEG : addr = 0x0060; break;
61 case NVDEV_ENGINE_BSP : addr = 0x0080; break;
62 case NVDEV_ENGINE_CRYPT: addr = 0x00a0; break;
63 case NVDEV_ENGINE_COPY0: addr = 0x00c0; break;
68 nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12;
69 nv_wo32(base->eng, addr + 0x00, 0x00190000);
70 nv_wo32(base->eng, addr + 0x04, lower_32_bits(limit));
71 nv_wo32(base->eng, addr + 0x08, lower_32_bits(start));
72 nv_wo32(base->eng, addr + 0x0c, upper_32_bits(limit) << 24 |
73 upper_32_bits(start));
74 nv_wo32(base->eng, addr + 0x10, 0x00000000);
75 nv_wo32(base->eng, addr + 0x14, 0x00000000);
81 nv84_fifo_context_detach(struct nouveau_object *parent, bool suspend,
82 struct nouveau_object *object)
84 struct nouveau_bar *bar = nouveau_bar(parent);
85 struct nv50_fifo_priv *priv = (void *)parent->engine;
86 struct nv50_fifo_base *base = (void *)parent->parent;
87 struct nv50_fifo_chan *chan = (void *)parent;
91 switch (nv_engidx(object->engine)) {
92 case NVDEV_ENGINE_SW : return 0;
93 case NVDEV_ENGINE_GR : engn = 0; addr = 0x0020; break;
94 case NVDEV_ENGINE_VP : engn = 3; addr = 0x0040; break;
95 case NVDEV_ENGINE_MPEG : engn = 1; addr = 0x0060; break;
96 case NVDEV_ENGINE_BSP : engn = 5; addr = 0x0080; break;
97 case NVDEV_ENGINE_CRYPT: engn = 4; addr = 0x00a0; break;
98 case NVDEV_ENGINE_COPY0: engn = 2; addr = 0x00c0; break;
103 save = nv_mask(priv, 0x002520, 0x0000003f, 1 << engn);
104 nv_wr32(priv, 0x0032fc, nv_gpuobj(base)->addr >> 12);
105 done = nv_wait_ne(priv, 0x0032fc, 0xffffffff, 0xffffffff);
106 nv_wr32(priv, 0x002520, save);
108 nv_error(priv, "channel %d [%s] unload timeout\n",
109 chan->base.chid, nouveau_client_name(chan));
114 nv_wo32(base->eng, addr + 0x00, 0x00000000);
115 nv_wo32(base->eng, addr + 0x04, 0x00000000);
116 nv_wo32(base->eng, addr + 0x08, 0x00000000);
117 nv_wo32(base->eng, addr + 0x0c, 0x00000000);
118 nv_wo32(base->eng, addr + 0x10, 0x00000000);
119 nv_wo32(base->eng, addr + 0x14, 0x00000000);
125 nv84_fifo_object_attach(struct nouveau_object *parent,
126 struct nouveau_object *object, u32 handle)
128 struct nv50_fifo_chan *chan = (void *)parent;
131 if (nv_iclass(object, NV_GPUOBJ_CLASS))
132 context = nv_gpuobj(object)->node->offset >> 4;
134 context = 0x00000004; /* just non-zero */
136 switch (nv_engidx(object->engine)) {
137 case NVDEV_ENGINE_DMAOBJ:
138 case NVDEV_ENGINE_SW : context |= 0x00000000; break;
139 case NVDEV_ENGINE_GR : context |= 0x00100000; break;
140 case NVDEV_ENGINE_MPEG :
141 case NVDEV_ENGINE_PPP : context |= 0x00200000; break;
142 case NVDEV_ENGINE_ME :
143 case NVDEV_ENGINE_COPY0 : context |= 0x00300000; break;
144 case NVDEV_ENGINE_VP : context |= 0x00400000; break;
145 case NVDEV_ENGINE_CRYPT :
146 case NVDEV_ENGINE_UNK1C1: context |= 0x00500000; break;
147 case NVDEV_ENGINE_BSP : context |= 0x00600000; break;
152 return nouveau_ramht_insert(chan->ramht, 0, handle, context);
156 nv84_fifo_chan_ctor_dma(struct nouveau_object *parent,
157 struct nouveau_object *engine,
158 struct nouveau_oclass *oclass, void *data, u32 size,
159 struct nouveau_object **pobject)
161 struct nouveau_bar *bar = nouveau_bar(parent);
162 struct nv50_fifo_base *base = (void *)parent;
163 struct nv50_fifo_chan *chan;
164 struct nv03_channel_dma_class *args = data;
167 if (size < sizeof(*args))
170 ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0xc00000,
171 0x2000, args->pushbuf,
172 (1ULL << NVDEV_ENGINE_DMAOBJ) |
173 (1ULL << NVDEV_ENGINE_SW) |
174 (1ULL << NVDEV_ENGINE_GR) |
175 (1ULL << NVDEV_ENGINE_MPEG) |
176 (1ULL << NVDEV_ENGINE_ME) |
177 (1ULL << NVDEV_ENGINE_VP) |
178 (1ULL << NVDEV_ENGINE_CRYPT) |
179 (1ULL << NVDEV_ENGINE_BSP) |
180 (1ULL << NVDEV_ENGINE_PPP) |
181 (1ULL << NVDEV_ENGINE_COPY0) |
182 (1ULL << NVDEV_ENGINE_UNK1C1), &chan);
183 *pobject = nv_object(chan);
187 ret = nouveau_ramht_new(nv_object(chan), nv_object(chan), 0x8000, 16,
192 nv_parent(chan)->context_attach = nv84_fifo_context_attach;
193 nv_parent(chan)->context_detach = nv84_fifo_context_detach;
194 nv_parent(chan)->object_attach = nv84_fifo_object_attach;
195 nv_parent(chan)->object_detach = nv50_fifo_object_detach;
197 nv_wo32(base->ramfc, 0x08, lower_32_bits(args->offset));
198 nv_wo32(base->ramfc, 0x0c, upper_32_bits(args->offset));
199 nv_wo32(base->ramfc, 0x10, lower_32_bits(args->offset));
200 nv_wo32(base->ramfc, 0x14, upper_32_bits(args->offset));
201 nv_wo32(base->ramfc, 0x3c, 0x003f6078);
202 nv_wo32(base->ramfc, 0x44, 0x01003fff);
203 nv_wo32(base->ramfc, 0x48, chan->base.pushgpu->node->offset >> 4);
204 nv_wo32(base->ramfc, 0x4c, 0xffffffff);
205 nv_wo32(base->ramfc, 0x60, 0x7fffffff);
206 nv_wo32(base->ramfc, 0x78, 0x00000000);
207 nv_wo32(base->ramfc, 0x7c, 0x30000001);
208 nv_wo32(base->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) |
209 (4 << 24) /* SEARCH_FULL */ |
210 (chan->ramht->base.node->offset >> 4));
211 nv_wo32(base->ramfc, 0x88, base->cache->addr >> 10);
212 nv_wo32(base->ramfc, 0x98, nv_gpuobj(base)->addr >> 12);
218 nv84_fifo_chan_ctor_ind(struct nouveau_object *parent,
219 struct nouveau_object *engine,
220 struct nouveau_oclass *oclass, void *data, u32 size,
221 struct nouveau_object **pobject)
223 struct nouveau_bar *bar = nouveau_bar(parent);
224 struct nv50_fifo_base *base = (void *)parent;
225 struct nv50_fifo_chan *chan;
226 struct nv50_channel_ind_class *args = data;
227 u64 ioffset, ilength;
230 if (size < sizeof(*args))
233 ret = nouveau_fifo_channel_create(parent, engine, oclass, 0, 0xc00000,
234 0x2000, args->pushbuf,
235 (1ULL << NVDEV_ENGINE_DMAOBJ) |
236 (1ULL << NVDEV_ENGINE_SW) |
237 (1ULL << NVDEV_ENGINE_GR) |
238 (1ULL << NVDEV_ENGINE_MPEG) |
239 (1ULL << NVDEV_ENGINE_ME) |
240 (1ULL << NVDEV_ENGINE_VP) |
241 (1ULL << NVDEV_ENGINE_CRYPT) |
242 (1ULL << NVDEV_ENGINE_BSP) |
243 (1ULL << NVDEV_ENGINE_PPP) |
244 (1ULL << NVDEV_ENGINE_COPY0) |
245 (1ULL << NVDEV_ENGINE_UNK1C1), &chan);
246 *pobject = nv_object(chan);
250 ret = nouveau_ramht_new(nv_object(chan), nv_object(chan), 0x8000, 16,
255 nv_parent(chan)->context_attach = nv84_fifo_context_attach;
256 nv_parent(chan)->context_detach = nv84_fifo_context_detach;
257 nv_parent(chan)->object_attach = nv84_fifo_object_attach;
258 nv_parent(chan)->object_detach = nv50_fifo_object_detach;
260 ioffset = args->ioffset;
261 ilength = log2i(args->ilength / 8);
263 nv_wo32(base->ramfc, 0x3c, 0x403f6078);
264 nv_wo32(base->ramfc, 0x44, 0x01003fff);
265 nv_wo32(base->ramfc, 0x48, chan->base.pushgpu->node->offset >> 4);
266 nv_wo32(base->ramfc, 0x50, lower_32_bits(ioffset));
267 nv_wo32(base->ramfc, 0x54, upper_32_bits(ioffset) | (ilength << 16));
268 nv_wo32(base->ramfc, 0x60, 0x7fffffff);
269 nv_wo32(base->ramfc, 0x78, 0x00000000);
270 nv_wo32(base->ramfc, 0x7c, 0x30000001);
271 nv_wo32(base->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) |
272 (4 << 24) /* SEARCH_FULL */ |
273 (chan->ramht->base.node->offset >> 4));
274 nv_wo32(base->ramfc, 0x88, base->cache->addr >> 10);
275 nv_wo32(base->ramfc, 0x98, nv_gpuobj(base)->addr >> 12);
281 nv84_fifo_chan_init(struct nouveau_object *object)
283 struct nv50_fifo_priv *priv = (void *)object->engine;
284 struct nv50_fifo_base *base = (void *)object->parent;
285 struct nv50_fifo_chan *chan = (void *)object;
286 struct nouveau_gpuobj *ramfc = base->ramfc;
287 u32 chid = chan->base.chid;
290 ret = nouveau_fifo_channel_init(&chan->base);
294 nv_wr32(priv, 0x002600 + (chid * 4), 0x80000000 | ramfc->addr >> 8);
295 nv50_fifo_playlist_update(priv);
299 static struct nouveau_ofuncs
300 nv84_fifo_ofuncs_dma = {
301 .ctor = nv84_fifo_chan_ctor_dma,
302 .dtor = nv50_fifo_chan_dtor,
303 .init = nv84_fifo_chan_init,
304 .fini = nv50_fifo_chan_fini,
305 .rd32 = _nouveau_fifo_channel_rd32,
306 .wr32 = _nouveau_fifo_channel_wr32,
309 static struct nouveau_ofuncs
310 nv84_fifo_ofuncs_ind = {
311 .ctor = nv84_fifo_chan_ctor_ind,
312 .dtor = nv50_fifo_chan_dtor,
313 .init = nv84_fifo_chan_init,
314 .fini = nv50_fifo_chan_fini,
315 .rd32 = _nouveau_fifo_channel_rd32,
316 .wr32 = _nouveau_fifo_channel_wr32,
319 static struct nouveau_oclass
320 nv84_fifo_sclass[] = {
321 { NV84_CHANNEL_DMA_CLASS, &nv84_fifo_ofuncs_dma },
322 { NV84_CHANNEL_IND_CLASS, &nv84_fifo_ofuncs_ind },
326 /*******************************************************************************
327 * FIFO context - basically just the instmem reserved for the channel
328 ******************************************************************************/
331 nv84_fifo_context_ctor(struct nouveau_object *parent,
332 struct nouveau_object *engine,
333 struct nouveau_oclass *oclass, void *data, u32 size,
334 struct nouveau_object **pobject)
336 struct nv50_fifo_base *base;
339 ret = nouveau_fifo_context_create(parent, engine, oclass, NULL, 0x10000,
340 0x1000, NVOBJ_FLAG_HEAP, &base);
341 *pobject = nv_object(base);
345 ret = nouveau_gpuobj_new(nv_object(base), nv_object(base), 0x0200, 0,
346 NVOBJ_FLAG_ZERO_ALLOC, &base->eng);
350 ret = nouveau_gpuobj_new(nv_object(base), nv_object(base), 0x4000, 0,
355 ret = nouveau_vm_ref(nouveau_client(parent)->vm, &base->vm, base->pgd);
359 ret = nouveau_gpuobj_new(nv_object(base), nv_object(base), 0x1000,
360 0x400, NVOBJ_FLAG_ZERO_ALLOC, &base->cache);
364 ret = nouveau_gpuobj_new(nv_object(base), nv_object(base), 0x0100,
365 0x100, NVOBJ_FLAG_ZERO_ALLOC, &base->ramfc);
372 static struct nouveau_oclass
374 .handle = NV_ENGCTX(FIFO, 0x84),
375 .ofuncs = &(struct nouveau_ofuncs) {
376 .ctor = nv84_fifo_context_ctor,
377 .dtor = nv50_fifo_context_dtor,
378 .init = _nouveau_fifo_context_init,
379 .fini = _nouveau_fifo_context_fini,
380 .rd32 = _nouveau_fifo_context_rd32,
381 .wr32 = _nouveau_fifo_context_wr32,
385 /*******************************************************************************
387 ******************************************************************************/
390 nv84_fifo_uevent_enable(struct nouveau_event *event, int index)
392 struct nv84_fifo_priv *priv = event->priv;
393 nv_mask(priv, 0x002140, 0x40000000, 0x40000000);
397 nv84_fifo_uevent_disable(struct nouveau_event *event, int index)
399 struct nv84_fifo_priv *priv = event->priv;
400 nv_mask(priv, 0x002140, 0x40000000, 0x00000000);
404 nv84_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
405 struct nouveau_oclass *oclass, void *data, u32 size,
406 struct nouveau_object **pobject)
408 struct nv50_fifo_priv *priv;
411 ret = nouveau_fifo_create(parent, engine, oclass, 1, 127, &priv);
412 *pobject = nv_object(priv);
416 ret = nouveau_gpuobj_new(nv_object(priv), NULL, 128 * 4, 0x1000, 0,
421 ret = nouveau_gpuobj_new(nv_object(priv), NULL, 128 * 4, 0x1000, 0,
426 priv->base.uevent->enable = nv84_fifo_uevent_enable;
427 priv->base.uevent->disable = nv84_fifo_uevent_disable;
428 priv->base.uevent->priv = priv;
430 nv_subdev(priv)->unit = 0x00000100;
431 nv_subdev(priv)->intr = nv04_fifo_intr;
432 nv_engine(priv)->cclass = &nv84_fifo_cclass;
433 nv_engine(priv)->sclass = nv84_fifo_sclass;
437 struct nouveau_oclass
439 .handle = NV_ENGINE(FIFO, 0x84),
440 .ofuncs = &(struct nouveau_ofuncs) {
441 .ctor = nv84_fifo_ctor,
442 .dtor = nv50_fifo_dtor,
443 .init = nv50_fifo_init,
444 .fini = _nouveau_fifo_fini,