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[~andy/linux] / drivers / gpu / drm / nouveau / core / engine / device / base.c
1 /*
2  * Copyright 2012 Red Hat Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: Ben Skeggs
23  */
24
25 #include <core/object.h>
26 #include <core/device.h>
27 #include <core/client.h>
28 #include <core/option.h>
29
30 #include <core/class.h>
31
32 #include "priv.h"
33
34 static DEFINE_MUTEX(nv_devices_mutex);
35 static LIST_HEAD(nv_devices);
36
37 struct nouveau_device *
38 nouveau_device_find(u64 name)
39 {
40         struct nouveau_device *device, *match = NULL;
41         mutex_lock(&nv_devices_mutex);
42         list_for_each_entry(device, &nv_devices, head) {
43                 if (device->handle == name) {
44                         match = device;
45                         break;
46                 }
47         }
48         mutex_unlock(&nv_devices_mutex);
49         return match;
50 }
51
52 /******************************************************************************
53  * nouveau_devobj (0x0080): class implementation
54  *****************************************************************************/
55 struct nouveau_devobj {
56         struct nouveau_parent base;
57         struct nouveau_object *subdev[NVDEV_SUBDEV_NR];
58 };
59
60 static const u64 disable_map[] = {
61         [NVDEV_SUBDEV_VBIOS]    = NV_DEVICE_DISABLE_VBIOS,
62         [NVDEV_SUBDEV_DEVINIT]  = NV_DEVICE_DISABLE_CORE,
63         [NVDEV_SUBDEV_GPIO]     = NV_DEVICE_DISABLE_CORE,
64         [NVDEV_SUBDEV_I2C]      = NV_DEVICE_DISABLE_CORE,
65         [NVDEV_SUBDEV_CLOCK]    = NV_DEVICE_DISABLE_CORE,
66         [NVDEV_SUBDEV_MXM]      = NV_DEVICE_DISABLE_CORE,
67         [NVDEV_SUBDEV_MC]       = NV_DEVICE_DISABLE_CORE,
68         [NVDEV_SUBDEV_BUS]      = NV_DEVICE_DISABLE_CORE,
69         [NVDEV_SUBDEV_TIMER]    = NV_DEVICE_DISABLE_CORE,
70         [NVDEV_SUBDEV_FB]       = NV_DEVICE_DISABLE_CORE,
71         [NVDEV_SUBDEV_LTCG]     = NV_DEVICE_DISABLE_CORE,
72         [NVDEV_SUBDEV_IBUS]     = NV_DEVICE_DISABLE_CORE,
73         [NVDEV_SUBDEV_INSTMEM]  = NV_DEVICE_DISABLE_CORE,
74         [NVDEV_SUBDEV_VM]       = NV_DEVICE_DISABLE_CORE,
75         [NVDEV_SUBDEV_BAR]      = NV_DEVICE_DISABLE_CORE,
76         [NVDEV_SUBDEV_VOLT]     = NV_DEVICE_DISABLE_CORE,
77         [NVDEV_SUBDEV_THERM]    = NV_DEVICE_DISABLE_CORE,
78         [NVDEV_SUBDEV_PWR]      = NV_DEVICE_DISABLE_CORE,
79         [NVDEV_ENGINE_DMAOBJ]   = NV_DEVICE_DISABLE_CORE,
80         [NVDEV_ENGINE_PERFMON]  = NV_DEVICE_DISABLE_CORE,
81         [NVDEV_ENGINE_FIFO]     = NV_DEVICE_DISABLE_FIFO,
82         [NVDEV_ENGINE_SW]       = NV_DEVICE_DISABLE_FIFO,
83         [NVDEV_ENGINE_GR]       = NV_DEVICE_DISABLE_GRAPH,
84         [NVDEV_ENGINE_MPEG]     = NV_DEVICE_DISABLE_MPEG,
85         [NVDEV_ENGINE_ME]       = NV_DEVICE_DISABLE_ME,
86         [NVDEV_ENGINE_VP]       = NV_DEVICE_DISABLE_VP,
87         [NVDEV_ENGINE_CRYPT]    = NV_DEVICE_DISABLE_CRYPT,
88         [NVDEV_ENGINE_BSP]      = NV_DEVICE_DISABLE_BSP,
89         [NVDEV_ENGINE_PPP]      = NV_DEVICE_DISABLE_PPP,
90         [NVDEV_ENGINE_COPY0]    = NV_DEVICE_DISABLE_COPY0,
91         [NVDEV_ENGINE_COPY1]    = NV_DEVICE_DISABLE_COPY1,
92         [NVDEV_ENGINE_VIC]      = NV_DEVICE_DISABLE_VIC,
93         [NVDEV_ENGINE_VENC]     = NV_DEVICE_DISABLE_VENC,
94         [NVDEV_ENGINE_DISP]     = NV_DEVICE_DISABLE_DISP,
95         [NVDEV_SUBDEV_NR]       = 0,
96 };
97
98 static int
99 nouveau_devobj_ctor(struct nouveau_object *parent,
100                     struct nouveau_object *engine,
101                     struct nouveau_oclass *oclass, void *data, u32 size,
102                     struct nouveau_object **pobject)
103 {
104         struct nouveau_client *client = nv_client(parent);
105         struct nouveau_device *device;
106         struct nouveau_devobj *devobj;
107         struct nv_device_class *args = data;
108         u32 boot0, strap;
109         u64 disable, mmio_base, mmio_size;
110         void __iomem *map;
111         int ret, i, c;
112
113         if (size < sizeof(struct nv_device_class))
114                 return -EINVAL;
115
116         /* find the device subdev that matches what the client requested */
117         device = nv_device(client->device);
118         if (args->device != ~0) {
119                 device = nouveau_device_find(args->device);
120                 if (!device)
121                         return -ENODEV;
122         }
123
124         ret = nouveau_parent_create(parent, nv_object(device), oclass, 0,
125                                     nouveau_control_oclass,
126                                     (1ULL << NVDEV_ENGINE_DMAOBJ) |
127                                     (1ULL << NVDEV_ENGINE_FIFO) |
128                                     (1ULL << NVDEV_ENGINE_DISP) |
129                                     (1ULL << NVDEV_ENGINE_PERFMON), &devobj);
130         *pobject = nv_object(devobj);
131         if (ret)
132                 return ret;
133
134         mmio_base = pci_resource_start(device->pdev, 0);
135         mmio_size = pci_resource_len(device->pdev, 0);
136
137         /* translate api disable mask into internal mapping */
138         disable = args->debug0;
139         for (i = 0; i < NVDEV_SUBDEV_NR; i++) {
140                 if (args->disable & disable_map[i])
141                         disable |= (1ULL << i);
142         }
143
144         /* identify the chipset, and determine classes of subdev/engines */
145         if (!(args->disable & NV_DEVICE_DISABLE_IDENTIFY) &&
146             !device->card_type) {
147                 map = ioremap(mmio_base, 0x102000);
148                 if (map == NULL)
149                         return -ENOMEM;
150
151                 /* switch mmio to cpu's native endianness */
152 #ifndef __BIG_ENDIAN
153                 if (ioread32_native(map + 0x000004) != 0x00000000)
154 #else
155                 if (ioread32_native(map + 0x000004) == 0x00000000)
156 #endif
157                         iowrite32_native(0x01000001, map + 0x000004);
158
159                 /* read boot0 and strapping information */
160                 boot0 = ioread32_native(map + 0x000000);
161                 strap = ioread32_native(map + 0x101000);
162                 iounmap(map);
163
164                 /* determine chipset and derive architecture from it */
165                 if ((boot0 & 0x1f000000) > 0) {
166                         device->chipset = (boot0 & 0x1ff00000) >> 20;
167                         switch (device->chipset & 0x1f0) {
168                         case 0x010: {
169                                 if (0x461 & (1 << (device->chipset & 0xf)))
170                                         device->card_type = NV_10;
171                                 else
172                                         device->card_type = NV_11;
173                                 break;
174                         }
175                         case 0x020: device->card_type = NV_20; break;
176                         case 0x030: device->card_type = NV_30; break;
177                         case 0x040:
178                         case 0x060: device->card_type = NV_40; break;
179                         case 0x050:
180                         case 0x080:
181                         case 0x090:
182                         case 0x0a0: device->card_type = NV_50; break;
183                         case 0x0c0: device->card_type = NV_C0; break;
184                         case 0x0d0: device->card_type = NV_D0; break;
185                         case 0x0e0:
186                         case 0x0f0:
187                         case 0x100: device->card_type = NV_E0; break;
188                         default:
189                                 break;
190                         }
191                 } else
192                 if ((boot0 & 0xff00fff0) == 0x20004000) {
193                         if (boot0 & 0x00f00000)
194                                 device->chipset = 0x05;
195                         else
196                                 device->chipset = 0x04;
197                         device->card_type = NV_04;
198                 }
199
200                 switch (device->card_type) {
201                 case NV_04: ret = nv04_identify(device); break;
202                 case NV_10:
203                 case NV_11: ret = nv10_identify(device); break;
204                 case NV_20: ret = nv20_identify(device); break;
205                 case NV_30: ret = nv30_identify(device); break;
206                 case NV_40: ret = nv40_identify(device); break;
207                 case NV_50: ret = nv50_identify(device); break;
208                 case NV_C0:
209                 case NV_D0: ret = nvc0_identify(device); break;
210                 case NV_E0: ret = nve0_identify(device); break;
211                 default:
212                         ret = -EINVAL;
213                         break;
214                 }
215
216                 if (ret) {
217                         nv_error(device, "unknown chipset, 0x%08x\n", boot0);
218                         return ret;
219                 }
220
221                 nv_info(device, "BOOT0  : 0x%08x\n", boot0);
222                 nv_info(device, "Chipset: %s (NV%02X)\n",
223                         device->cname, device->chipset);
224                 nv_info(device, "Family : NV%02X\n", device->card_type);
225
226                 /* determine frequency of timing crystal */
227                 if ( device->card_type <= NV_10 || device->chipset < 0x17 ||
228                     (device->chipset >= 0x20 && device->chipset < 0x25))
229                         strap &= 0x00000040;
230                 else
231                         strap &= 0x00400040;
232
233                 switch (strap) {
234                 case 0x00000000: device->crystal = 13500; break;
235                 case 0x00000040: device->crystal = 14318; break;
236                 case 0x00400000: device->crystal = 27000; break;
237                 case 0x00400040: device->crystal = 25000; break;
238                 }
239
240                 nv_debug(device, "crystal freq: %dKHz\n", device->crystal);
241         }
242
243         if (!(args->disable & NV_DEVICE_DISABLE_MMIO) &&
244             !nv_subdev(device)->mmio) {
245                 nv_subdev(device)->mmio  = ioremap(mmio_base, mmio_size);
246                 if (!nv_subdev(device)->mmio) {
247                         nv_error(device, "unable to map device registers\n");
248                         return -ENOMEM;
249                 }
250         }
251
252         /* ensure requested subsystems are available for use */
253         for (i = 1, c = 1; i < NVDEV_SUBDEV_NR; i++) {
254                 if (!(oclass = device->oclass[i]) || (disable & (1ULL << i)))
255                         continue;
256
257                 if (device->subdev[i]) {
258                         nouveau_object_ref(device->subdev[i],
259                                           &devobj->subdev[i]);
260                         continue;
261                 }
262
263                 ret = nouveau_object_ctor(nv_object(device), NULL,
264                                           oclass, NULL, i,
265                                           &devobj->subdev[i]);
266                 if (ret == -ENODEV)
267                         continue;
268                 if (ret)
269                         return ret;
270
271                 device->subdev[i] = devobj->subdev[i];
272
273                 /* note: can't init *any* subdevs until devinit has been run
274                  * due to not knowing exactly what the vbios init tables will
275                  * mess with.  devinit also can't be run until all of its
276                  * dependencies have been created.
277                  *
278                  * this code delays init of any subdev until all of devinit's
279                  * dependencies have been created, and then initialises each
280                  * subdev in turn as they're created.
281                  */
282                 while (i >= NVDEV_SUBDEV_DEVINIT_LAST && c <= i) {
283                         struct nouveau_object *subdev = devobj->subdev[c++];
284                         if (subdev && !nv_iclass(subdev, NV_ENGINE_CLASS)) {
285                                 ret = nouveau_object_inc(subdev);
286                                 if (ret)
287                                         return ret;
288                                 atomic_dec(&nv_object(device)->usecount);
289                         } else
290                         if (subdev) {
291                                 nouveau_subdev_reset(subdev);
292                         }
293                 }
294         }
295
296         return 0;
297 }
298
299 static void
300 nouveau_devobj_dtor(struct nouveau_object *object)
301 {
302         struct nouveau_devobj *devobj = (void *)object;
303         int i;
304
305         for (i = NVDEV_SUBDEV_NR - 1; i >= 0; i--)
306                 nouveau_object_ref(NULL, &devobj->subdev[i]);
307
308         nouveau_parent_destroy(&devobj->base);
309 }
310
311 static u8
312 nouveau_devobj_rd08(struct nouveau_object *object, u64 addr)
313 {
314         return nv_rd08(object->engine, addr);
315 }
316
317 static u16
318 nouveau_devobj_rd16(struct nouveau_object *object, u64 addr)
319 {
320         return nv_rd16(object->engine, addr);
321 }
322
323 static u32
324 nouveau_devobj_rd32(struct nouveau_object *object, u64 addr)
325 {
326         return nv_rd32(object->engine, addr);
327 }
328
329 static void
330 nouveau_devobj_wr08(struct nouveau_object *object, u64 addr, u8 data)
331 {
332         nv_wr08(object->engine, addr, data);
333 }
334
335 static void
336 nouveau_devobj_wr16(struct nouveau_object *object, u64 addr, u16 data)
337 {
338         nv_wr16(object->engine, addr, data);
339 }
340
341 static void
342 nouveau_devobj_wr32(struct nouveau_object *object, u64 addr, u32 data)
343 {
344         nv_wr32(object->engine, addr, data);
345 }
346
347 static struct nouveau_ofuncs
348 nouveau_devobj_ofuncs = {
349         .ctor = nouveau_devobj_ctor,
350         .dtor = nouveau_devobj_dtor,
351         .init = _nouveau_parent_init,
352         .fini = _nouveau_parent_fini,
353         .rd08 = nouveau_devobj_rd08,
354         .rd16 = nouveau_devobj_rd16,
355         .rd32 = nouveau_devobj_rd32,
356         .wr08 = nouveau_devobj_wr08,
357         .wr16 = nouveau_devobj_wr16,
358         .wr32 = nouveau_devobj_wr32,
359 };
360
361 /******************************************************************************
362  * nouveau_device: engine functions
363  *****************************************************************************/
364 static struct nouveau_oclass
365 nouveau_device_sclass[] = {
366         { 0x0080, &nouveau_devobj_ofuncs },
367         {}
368 };
369
370 static int
371 nouveau_device_fini(struct nouveau_object *object, bool suspend)
372 {
373         struct nouveau_device *device = (void *)object;
374         struct nouveau_object *subdev;
375         int ret, i;
376
377         for (i = NVDEV_SUBDEV_NR - 1; i >= 0; i--) {
378                 if ((subdev = device->subdev[i])) {
379                         if (!nv_iclass(subdev, NV_ENGINE_CLASS)) {
380                                 ret = nouveau_object_dec(subdev, suspend);
381                                 if (ret && suspend)
382                                         goto fail;
383                         }
384                 }
385         }
386
387         ret = 0;
388 fail:
389         for (; ret && i < NVDEV_SUBDEV_NR; i++) {
390                 if ((subdev = device->subdev[i])) {
391                         if (!nv_iclass(subdev, NV_ENGINE_CLASS)) {
392                                 ret = nouveau_object_inc(subdev);
393                                 if (ret) {
394                                         /* XXX */
395                                 }
396                         }
397                 }
398         }
399
400         return ret;
401 }
402
403 static int
404 nouveau_device_init(struct nouveau_object *object)
405 {
406         struct nouveau_device *device = (void *)object;
407         struct nouveau_object *subdev;
408         int ret, i;
409
410         for (i = 0; i < NVDEV_SUBDEV_NR; i++) {
411                 if ((subdev = device->subdev[i])) {
412                         if (!nv_iclass(subdev, NV_ENGINE_CLASS)) {
413                                 ret = nouveau_object_inc(subdev);
414                                 if (ret)
415                                         goto fail;
416                         } else {
417                                 nouveau_subdev_reset(subdev);
418                         }
419                 }
420         }
421
422         ret = 0;
423 fail:
424         for (--i; ret && i >= 0; i--) {
425                 if ((subdev = device->subdev[i])) {
426                         if (!nv_iclass(subdev, NV_ENGINE_CLASS))
427                                 nouveau_object_dec(subdev, false);
428                 }
429         }
430
431         return ret;
432 }
433
434 static void
435 nouveau_device_dtor(struct nouveau_object *object)
436 {
437         struct nouveau_device *device = (void *)object;
438
439         mutex_lock(&nv_devices_mutex);
440         list_del(&device->head);
441         mutex_unlock(&nv_devices_mutex);
442
443         if (nv_subdev(device)->mmio)
444                 iounmap(nv_subdev(device)->mmio);
445
446         nouveau_engine_destroy(&device->base);
447 }
448
449 static struct nouveau_oclass
450 nouveau_device_oclass = {
451         .handle = NV_ENGINE(DEVICE, 0x00),
452         .ofuncs = &(struct nouveau_ofuncs) {
453                 .dtor = nouveau_device_dtor,
454                 .init = nouveau_device_init,
455                 .fini = nouveau_device_fini,
456         },
457 };
458
459 int
460 nouveau_device_create_(struct pci_dev *pdev, u64 name, const char *sname,
461                        const char *cfg, const char *dbg,
462                        int length, void **pobject)
463 {
464         struct nouveau_device *device;
465         int ret = -EEXIST;
466
467         mutex_lock(&nv_devices_mutex);
468         list_for_each_entry(device, &nv_devices, head) {
469                 if (device->handle == name)
470                         goto done;
471         }
472
473         ret = nouveau_engine_create_(NULL, NULL, &nouveau_device_oclass, true,
474                                      "DEVICE", "device", length, pobject);
475         device = *pobject;
476         if (ret)
477                 goto done;
478
479         device->pdev = pdev;
480         device->handle = name;
481         device->cfgopt = cfg;
482         device->dbgopt = dbg;
483         device->name = sname;
484
485         nv_subdev(device)->debug = nouveau_dbgopt(device->dbgopt, "DEVICE");
486         nv_engine(device)->sclass = nouveau_device_sclass;
487         list_add(&device->head, &nv_devices);
488 done:
489         mutex_unlock(&nv_devices_mutex);
490         return ret;
491 }