2 * Copyright 2010 Matt Turner.
3 * Copyright 2012 Red Hat
5 * This file is subject to the terms and conditions of the GNU General
6 * Public License version 2. See the file COPYING in the main
7 * directory of this archive for more details.
9 * Authors: Matthew Garrett
14 #include <linux/delay.h>
17 #include <drm/drm_crtc_helper.h>
19 #include "mgag200_drv.h"
21 #define MGAG200_LUT_SIZE 256
24 * This file contains setup code for the CRTC.
27 static void mga_crtc_load_lut(struct drm_crtc *crtc)
29 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
30 struct drm_device *dev = crtc->dev;
31 struct mga_device *mdev = dev->dev_private;
37 WREG8(DAC_INDEX + MGA1064_INDEX, 0);
39 for (i = 0; i < MGAG200_LUT_SIZE; i++) {
41 WREG8(DAC_INDEX + MGA1064_COL_PAL, mga_crtc->lut_r[i]);
42 WREG8(DAC_INDEX + MGA1064_COL_PAL, mga_crtc->lut_g[i]);
43 WREG8(DAC_INDEX + MGA1064_COL_PAL, mga_crtc->lut_b[i]);
47 static inline void mga_wait_vsync(struct mga_device *mdev)
49 unsigned long timeout = jiffies + HZ/10;
50 unsigned int status = 0;
53 status = RREG32(MGAREG_Status);
54 } while ((status & 0x08) && time_before(jiffies, timeout));
55 timeout = jiffies + HZ/10;
58 status = RREG32(MGAREG_Status);
59 } while (!(status & 0x08) && time_before(jiffies, timeout));
62 static inline void mga_wait_busy(struct mga_device *mdev)
64 unsigned long timeout = jiffies + HZ;
65 unsigned int status = 0;
67 status = RREG8(MGAREG_Status + 2);
68 } while ((status & 0x01) && time_before(jiffies, timeout));
72 * The core passes the desired mode to the CRTC code to see whether any
73 * CRTC-specific modifications need to be made to it. We're in a position
74 * to just pass that straight through, so this does nothing
76 static bool mga_crtc_mode_fixup(struct drm_crtc *crtc,
77 const struct drm_display_mode *mode,
78 struct drm_display_mode *adjusted_mode)
83 static int mga_g200se_set_plls(struct mga_device *mdev, long clock)
85 unsigned int vcomax, vcomin, pllreffreq;
86 unsigned int delta, tmpdelta, permitteddelta;
87 unsigned int testp, testm, testn;
89 unsigned int computed;
97 permitteddelta = clock * 5 / 1000;
99 for (testp = 8; testp > 0; testp /= 2) {
100 if (clock * testp > vcomax)
102 if (clock * testp < vcomin)
105 for (testn = 17; testn < 256; testn++) {
106 for (testm = 1; testm < 32; testm++) {
107 computed = (pllreffreq * testn) /
109 if (computed > clock)
110 tmpdelta = computed - clock;
112 tmpdelta = clock - computed;
113 if (tmpdelta < delta) {
123 if (delta > permitteddelta) {
124 printk(KERN_WARNING "PLL delta too large\n");
128 WREG_DAC(MGA1064_PIX_PLLC_M, m);
129 WREG_DAC(MGA1064_PIX_PLLC_N, n);
130 WREG_DAC(MGA1064_PIX_PLLC_P, p);
134 static int mga_g200wb_set_plls(struct mga_device *mdev, long clock)
136 unsigned int vcomax, vcomin, pllreffreq;
137 unsigned int delta, tmpdelta, permitteddelta;
138 unsigned int testp, testm, testn;
139 unsigned int p, m, n;
140 unsigned int computed;
141 int i, j, tmpcount, vcount;
142 bool pll_locked = false;
151 permitteddelta = clock * 5 / 1000;
153 for (testp = 1; testp < 9; testp++) {
154 if (clock * testp > vcomax)
156 if (clock * testp < vcomin)
159 for (testm = 1; testm < 17; testm++) {
160 for (testn = 1; testn < 151; testn++) {
161 computed = (pllreffreq * testn) /
163 if (computed > clock)
164 tmpdelta = computed - clock;
166 tmpdelta = clock - computed;
167 if (tmpdelta < delta) {
170 m = (testm - 1) | ((n >> 1) & 0x80);
177 for (i = 0; i <= 32 && pll_locked == false; i++) {
179 WREG8(MGAREG_CRTC_INDEX, 0x1e);
180 tmp = RREG8(MGAREG_CRTC_DATA);
182 WREG8(MGAREG_CRTC_DATA, tmp+1);
185 /* set pixclkdis to 1 */
186 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
187 tmp = RREG8(DAC_DATA);
188 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
189 WREG8(DAC_DATA, tmp);
191 WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
192 tmp = RREG8(DAC_DATA);
193 tmp |= MGA1064_REMHEADCTL_CLKDIS;
194 WREG8(DAC_DATA, tmp);
196 /* select PLL Set C */
197 tmp = RREG8(MGAREG_MEM_MISC_READ);
199 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
201 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
202 tmp = RREG8(DAC_DATA);
203 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN | 0x80;
204 WREG8(DAC_DATA, tmp);
209 WREG8(DAC_INDEX, MGA1064_VREF_CTL);
210 tmp = RREG8(DAC_DATA);
212 WREG8(DAC_DATA, tmp);
216 /* program pixel pll register */
217 WREG_DAC(MGA1064_WB_PIX_PLLC_N, n);
218 WREG_DAC(MGA1064_WB_PIX_PLLC_M, m);
219 WREG_DAC(MGA1064_WB_PIX_PLLC_P, p);
224 WREG8(DAC_INDEX, MGA1064_VREF_CTL);
225 tmp = RREG8(DAC_DATA);
227 WREG_DAC(MGA1064_VREF_CTL, tmp);
231 /* select the pixel pll */
232 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
233 tmp = RREG8(DAC_DATA);
234 tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK;
235 tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL;
236 WREG8(DAC_DATA, tmp);
238 WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
239 tmp = RREG8(DAC_DATA);
240 tmp &= ~MGA1064_REMHEADCTL_CLKSL_MSK;
241 tmp |= MGA1064_REMHEADCTL_CLKSL_PLL;
242 WREG8(DAC_DATA, tmp);
244 /* reset dotclock rate bit */
245 WREG8(MGAREG_SEQ_INDEX, 1);
246 tmp = RREG8(MGAREG_SEQ_DATA);
248 WREG8(MGAREG_SEQ_DATA, tmp);
250 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
251 tmp = RREG8(DAC_DATA);
252 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
253 WREG8(DAC_DATA, tmp);
255 vcount = RREG8(MGAREG_VCOUNT);
257 for (j = 0; j < 30 && pll_locked == false; j++) {
258 tmpcount = RREG8(MGAREG_VCOUNT);
259 if (tmpcount < vcount)
261 if ((tmpcount - vcount) > 2)
267 WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
268 tmp = RREG8(DAC_DATA);
269 tmp &= ~MGA1064_REMHEADCTL_CLKDIS;
270 WREG_DAC(MGA1064_REMHEADCTL, tmp);
274 static int mga_g200ev_set_plls(struct mga_device *mdev, long clock)
276 unsigned int vcomax, vcomin, pllreffreq;
277 unsigned int delta, tmpdelta, permitteddelta;
278 unsigned int testp, testm, testn;
279 unsigned int p, m, n;
280 unsigned int computed;
289 permitteddelta = clock * 5 / 1000;
291 for (testp = 16; testp > 0; testp--) {
292 if (clock * testp > vcomax)
294 if (clock * testp < vcomin)
297 for (testn = 1; testn < 257; testn++) {
298 for (testm = 1; testm < 17; testm++) {
299 computed = (pllreffreq * testn) /
301 if (computed > clock)
302 tmpdelta = computed - clock;
304 tmpdelta = clock - computed;
305 if (tmpdelta < delta) {
315 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
316 tmp = RREG8(DAC_DATA);
317 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
318 WREG8(DAC_DATA, tmp);
320 tmp = RREG8(MGAREG_MEM_MISC_READ);
322 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
324 WREG8(DAC_INDEX, MGA1064_PIX_PLL_STAT);
325 tmp = RREG8(DAC_DATA);
326 WREG8(DAC_DATA, tmp & ~0x40);
328 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
329 tmp = RREG8(DAC_DATA);
330 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
331 WREG8(DAC_DATA, tmp);
333 WREG_DAC(MGA1064_EV_PIX_PLLC_M, m);
334 WREG_DAC(MGA1064_EV_PIX_PLLC_N, n);
335 WREG_DAC(MGA1064_EV_PIX_PLLC_P, p);
339 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
340 tmp = RREG8(DAC_DATA);
341 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
342 WREG8(DAC_DATA, tmp);
346 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
347 tmp = RREG8(DAC_DATA);
348 tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK;
349 tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL;
350 WREG8(DAC_DATA, tmp);
352 WREG8(DAC_INDEX, MGA1064_PIX_PLL_STAT);
353 tmp = RREG8(DAC_DATA);
354 WREG8(DAC_DATA, tmp | 0x40);
356 tmp = RREG8(MGAREG_MEM_MISC_READ);
358 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
360 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
361 tmp = RREG8(DAC_DATA);
362 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
363 WREG8(DAC_DATA, tmp);
368 static int mga_g200eh_set_plls(struct mga_device *mdev, long clock)
370 unsigned int vcomax, vcomin, pllreffreq;
371 unsigned int delta, tmpdelta, permitteddelta;
372 unsigned int testp, testm, testn;
373 unsigned int p, m, n;
374 unsigned int computed;
375 int i, j, tmpcount, vcount;
377 bool pll_locked = false;
385 permitteddelta = clock * 5 / 1000;
387 for (testp = 16; testp > 0; testp >>= 1) {
388 if (clock * testp > vcomax)
390 if (clock * testp < vcomin)
393 for (testm = 1; testm < 33; testm++) {
394 for (testn = 17; testn < 257; testn++) {
395 computed = (pllreffreq * testn) /
397 if (computed > clock)
398 tmpdelta = computed - clock;
400 tmpdelta = clock - computed;
401 if (tmpdelta < delta) {
407 if ((clock * testp) >= 600000)
412 for (i = 0; i <= 32 && pll_locked == false; i++) {
413 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
414 tmp = RREG8(DAC_DATA);
415 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
416 WREG8(DAC_DATA, tmp);
418 tmp = RREG8(MGAREG_MEM_MISC_READ);
420 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
422 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
423 tmp = RREG8(DAC_DATA);
424 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
425 WREG8(DAC_DATA, tmp);
429 WREG_DAC(MGA1064_EH_PIX_PLLC_M, m);
430 WREG_DAC(MGA1064_EH_PIX_PLLC_N, n);
431 WREG_DAC(MGA1064_EH_PIX_PLLC_P, p);
435 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
436 tmp = RREG8(DAC_DATA);
437 tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK;
438 tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL;
439 WREG8(DAC_DATA, tmp);
441 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
442 tmp = RREG8(DAC_DATA);
443 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
444 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
445 WREG8(DAC_DATA, tmp);
447 vcount = RREG8(MGAREG_VCOUNT);
449 for (j = 0; j < 30 && pll_locked == false; j++) {
450 tmpcount = RREG8(MGAREG_VCOUNT);
451 if (tmpcount < vcount)
453 if ((tmpcount - vcount) > 2)
463 static int mga_g200er_set_plls(struct mga_device *mdev, long clock)
465 unsigned int vcomax, vcomin, pllreffreq;
466 unsigned int delta, tmpdelta;
467 int testr, testn, testm, testo;
468 unsigned int p, m, n;
469 unsigned int computed, vco;
471 const unsigned int m_div_val[] = { 1, 2, 4, 8 };
480 for (testr = 0; testr < 4; testr++) {
483 for (testn = 5; testn < 129; testn++) {
486 for (testm = 3; testm >= 0; testm--) {
489 for (testo = 5; testo < 33; testo++) {
490 vco = pllreffreq * (testn + 1) /
496 computed = vco / (m_div_val[testm] * (testo + 1));
497 if (computed > clock)
498 tmpdelta = computed - clock;
500 tmpdelta = clock - computed;
501 if (tmpdelta < delta) {
503 m = testm | (testo << 3);
505 p = testr | (testr << 3);
512 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
513 tmp = RREG8(DAC_DATA);
514 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
515 WREG8(DAC_DATA, tmp);
517 WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
518 tmp = RREG8(DAC_DATA);
519 tmp |= MGA1064_REMHEADCTL_CLKDIS;
520 WREG8(DAC_DATA, tmp);
522 tmp = RREG8(MGAREG_MEM_MISC_READ);
523 tmp |= (0x3<<2) | 0xc0;
524 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
526 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
527 tmp = RREG8(DAC_DATA);
528 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
529 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
530 WREG8(DAC_DATA, tmp);
534 WREG_DAC(MGA1064_ER_PIX_PLLC_N, n);
535 WREG_DAC(MGA1064_ER_PIX_PLLC_M, m);
536 WREG_DAC(MGA1064_ER_PIX_PLLC_P, p);
543 static int mga_crtc_set_plls(struct mga_device *mdev, long clock)
548 return mga_g200se_set_plls(mdev, clock);
551 return mga_g200wb_set_plls(mdev, clock);
554 return mga_g200ev_set_plls(mdev, clock);
557 return mga_g200eh_set_plls(mdev, clock);
560 return mga_g200er_set_plls(mdev, clock);
566 static void mga_g200wb_prepare(struct drm_crtc *crtc)
568 struct mga_device *mdev = crtc->dev->dev_private;
572 /* 1- The first step is to warn the BMC of an upcoming mode change.
573 * We are putting the misc<0> to output.*/
575 WREG8(DAC_INDEX, MGA1064_GEN_IO_CTL);
576 tmp = RREG8(DAC_DATA);
578 WREG_DAC(MGA1064_GEN_IO_CTL, tmp);
580 /* we are putting a 1 on the misc<0> line */
581 WREG8(DAC_INDEX, MGA1064_GEN_IO_DATA);
582 tmp = RREG8(DAC_DATA);
584 WREG_DAC(MGA1064_GEN_IO_DATA, tmp);
586 /* 2- Second step to mask and further scan request
587 * This will be done by asserting the remfreqmsk bit (XSPAREREG<7>)
589 WREG8(DAC_INDEX, MGA1064_SPAREREG);
590 tmp = RREG8(DAC_DATA);
592 WREG_DAC(MGA1064_SPAREREG, tmp);
594 /* 3a- the third step is to verifu if there is an active scan
595 * We are searching for a 0 on remhsyncsts <XSPAREREG<0>)
598 while (!(tmp & 0x1) && iter_max) {
599 WREG8(DAC_INDEX, MGA1064_SPAREREG);
600 tmp = RREG8(DAC_DATA);
605 /* 3b- this step occurs only if the remove is actually scanning
606 * we are waiting for the end of the frame which is a 1 on
607 * remvsyncsts (XSPAREREG<1>)
611 while ((tmp & 0x2) && iter_max) {
612 WREG8(DAC_INDEX, MGA1064_SPAREREG);
613 tmp = RREG8(DAC_DATA);
620 static void mga_g200wb_commit(struct drm_crtc *crtc)
623 struct mga_device *mdev = crtc->dev->dev_private;
625 /* 1- The first step is to ensure that the vrsten and hrsten are set */
626 WREG8(MGAREG_CRTCEXT_INDEX, 1);
627 tmp = RREG8(MGAREG_CRTCEXT_DATA);
628 WREG8(MGAREG_CRTCEXT_DATA, tmp | 0x88);
630 /* 2- second step is to assert the rstlvl2 */
631 WREG8(DAC_INDEX, MGA1064_REMHEADCTL2);
632 tmp = RREG8(DAC_DATA);
634 WREG8(DAC_DATA, tmp);
639 /* 3- deassert rstlvl2 */
641 WREG8(DAC_INDEX, MGA1064_REMHEADCTL2);
642 WREG8(DAC_DATA, tmp);
644 /* 4- remove mask of scan request */
645 WREG8(DAC_INDEX, MGA1064_SPAREREG);
646 tmp = RREG8(DAC_DATA);
648 WREG8(DAC_DATA, tmp);
650 /* 5- put back a 0 on the misc<0> line */
651 WREG8(DAC_INDEX, MGA1064_GEN_IO_DATA);
652 tmp = RREG8(DAC_DATA);
654 WREG_DAC(MGA1064_GEN_IO_DATA, tmp);
658 void mga_set_start_address(struct drm_crtc *crtc, unsigned offset)
660 struct mga_device *mdev = crtc->dev->dev_private;
664 while (RREG8(0x1fda) & 0x08);
665 while (!(RREG8(0x1fda) & 0x08));
667 count = RREG8(MGAREG_VCOUNT) + 2;
668 while (RREG8(MGAREG_VCOUNT) < count);
671 WREG_CRT(0x0d, (u8)(addr & 0xff));
672 WREG_CRT(0x0c, (u8)(addr >> 8) & 0xff);
673 WREG_CRT(0xaf, (u8)(addr >> 16) & 0xf);
677 /* ast is different - we will force move buffers out of VRAM */
678 static int mga_crtc_do_set_base(struct drm_crtc *crtc,
679 struct drm_framebuffer *fb,
680 int x, int y, int atomic)
682 struct mga_device *mdev = crtc->dev->dev_private;
683 struct drm_gem_object *obj;
684 struct mga_framebuffer *mga_fb;
685 struct mgag200_bo *bo;
689 /* push the previous fb to system ram */
691 mga_fb = to_mga_framebuffer(fb);
693 bo = gem_to_mga_bo(obj);
694 ret = mgag200_bo_reserve(bo, false);
697 mgag200_bo_push_sysram(bo);
698 mgag200_bo_unreserve(bo);
701 mga_fb = to_mga_framebuffer(crtc->fb);
703 bo = gem_to_mga_bo(obj);
705 ret = mgag200_bo_reserve(bo, false);
709 ret = mgag200_bo_pin(bo, TTM_PL_FLAG_VRAM, &gpu_addr);
711 mgag200_bo_unreserve(bo);
715 if (&mdev->mfbdev->mfb == mga_fb) {
716 /* if pushing console in kmap it */
717 ret = ttm_bo_kmap(&bo->bo, 0, bo->bo.num_pages, &bo->kmap);
719 DRM_ERROR("failed to kmap fbcon\n");
722 mgag200_bo_unreserve(bo);
724 DRM_INFO("mga base %llx\n", gpu_addr);
726 mga_set_start_address(crtc, (u32)gpu_addr);
731 static int mga_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
732 struct drm_framebuffer *old_fb)
734 return mga_crtc_do_set_base(crtc, old_fb, x, y, 0);
737 static int mga_crtc_mode_set(struct drm_crtc *crtc,
738 struct drm_display_mode *mode,
739 struct drm_display_mode *adjusted_mode,
740 int x, int y, struct drm_framebuffer *old_fb)
742 struct drm_device *dev = crtc->dev;
743 struct mga_device *mdev = dev->dev_private;
744 int hdisplay, hsyncstart, hsyncend, htotal;
745 int vdisplay, vsyncstart, vsyncend, vtotal;
747 int option = 0, option2 = 0;
749 unsigned char misc = 0;
750 unsigned char ext_vga[6];
751 unsigned char ext_vga_index24;
752 unsigned char dac_index90 = 0;
755 static unsigned char dacvalue[] = {
756 /* 0x00: */ 0, 0, 0, 0, 0, 0, 0x00, 0,
757 /* 0x08: */ 0, 0, 0, 0, 0, 0, 0, 0,
758 /* 0x10: */ 0, 0, 0, 0, 0, 0, 0, 0,
759 /* 0x18: */ 0x00, 0, 0xC9, 0xFF, 0xBF, 0x20, 0x1F, 0x20,
760 /* 0x20: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
761 /* 0x28: */ 0x00, 0x00, 0x00, 0x00, 0, 0, 0, 0x40,
762 /* 0x30: */ 0x00, 0xB0, 0x00, 0xC2, 0x34, 0x14, 0x02, 0x83,
763 /* 0x38: */ 0x00, 0x93, 0x00, 0x77, 0x00, 0x00, 0x00, 0x3A,
764 /* 0x40: */ 0, 0, 0, 0, 0, 0, 0, 0,
765 /* 0x48: */ 0, 0, 0, 0, 0, 0, 0, 0
768 bppshift = mdev->bpp_shifts[(crtc->fb->bits_per_pixel >> 3) - 1];
770 switch (mdev->type) {
773 dacvalue[MGA1064_VREF_CTL] = 0x03;
774 dacvalue[MGA1064_PIX_CLK_CTL] = MGA1064_PIX_CLK_CTL_SEL_PLL;
775 dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_DAC_EN |
776 MGA1064_MISC_CTL_VGA8 |
777 MGA1064_MISC_CTL_DAC_RAM_CS;
782 option2 = 0x00008000;
785 dacvalue[MGA1064_VREF_CTL] = 0x07;
787 option2 = 0x0000b000;
790 dacvalue[MGA1064_PIX_CLK_CTL] = MGA1064_PIX_CLK_CTL_SEL_PLL;
791 dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_VGA8 |
792 MGA1064_MISC_CTL_DAC_RAM_CS;
794 option2 = 0x0000b000;
797 dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_VGA8 |
798 MGA1064_MISC_CTL_DAC_RAM_CS;
800 option2 = 0x0000b000;
807 switch (crtc->fb->bits_per_pixel) {
809 dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_8bits;
812 if (crtc->fb->depth == 15)
813 dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_15bits;
815 dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_16bits;
818 dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_24bits;
821 dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_32_24bits;
825 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
827 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
831 for (i = 0; i < sizeof(dacvalue); i++) {
835 ((i >= 0x1f) && (i <= 0x29)) ||
836 ((i >= 0x30) && (i <= 0x37)))
838 if (IS_G200_SE(mdev) &&
839 ((i == 0x2c) || (i == 0x2d) || (i == 0x2e)))
841 if ((mdev->type == G200_EV || mdev->type == G200_WB || mdev->type == G200_EH) &&
842 (i >= 0x44) && (i <= 0x4e))
845 WREG_DAC(i, dacvalue[i]);
848 if (mdev->type == G200_ER) {
849 WREG_DAC(0x90, dac_index90);
854 pci_write_config_dword(dev->pdev, PCI_MGA_OPTION, option);
856 pci_write_config_dword(dev->pdev, PCI_MGA_OPTION2, option2);
862 pitch = crtc->fb->pitches[0] / (crtc->fb->bits_per_pixel / 8);
863 if (crtc->fb->bits_per_pixel == 24)
864 pitch = pitch >> (4 - bppshift);
866 pitch = pitch >> (4 - bppshift);
868 hdisplay = mode->hdisplay / 8 - 1;
869 hsyncstart = mode->hsync_start / 8 - 1;
870 hsyncend = mode->hsync_end / 8 - 1;
871 htotal = mode->htotal / 8 - 1;
873 /* Work around hardware quirk */
874 if ((htotal & 0x07) == 0x06 || (htotal & 0x07) == 0x04)
877 vdisplay = mode->vdisplay - 1;
878 vsyncstart = mode->vsync_start - 1;
879 vsyncend = mode->vsync_end - 1;
880 vtotal = mode->vtotal - 2;
892 WREG_CRT(0, htotal - 4);
893 WREG_CRT(1, hdisplay);
894 WREG_CRT(2, hdisplay);
895 WREG_CRT(3, (htotal & 0x1F) | 0x80);
896 WREG_CRT(4, hsyncstart);
897 WREG_CRT(5, ((htotal & 0x20) << 2) | (hsyncend & 0x1F));
898 WREG_CRT(6, vtotal & 0xFF);
899 WREG_CRT(7, ((vtotal & 0x100) >> 8) |
900 ((vdisplay & 0x100) >> 7) |
901 ((vsyncstart & 0x100) >> 6) |
902 ((vdisplay & 0x100) >> 5) |
903 ((vdisplay & 0x100) >> 4) | /* linecomp */
904 ((vtotal & 0x200) >> 4)|
905 ((vdisplay & 0x200) >> 3) |
906 ((vsyncstart & 0x200) >> 2));
907 WREG_CRT(9, ((vdisplay & 0x200) >> 4) |
908 ((vdisplay & 0x200) >> 3));
915 WREG_CRT(16, vsyncstart & 0xFF);
916 WREG_CRT(17, (vsyncend & 0x0F) | 0x20);
917 WREG_CRT(18, vdisplay & 0xFF);
918 WREG_CRT(19, pitch & 0xFF);
920 WREG_CRT(21, vdisplay & 0xFF);
921 WREG_CRT(22, (vtotal + 1) & 0xFF);
923 WREG_CRT(24, vdisplay & 0xFF);
930 ext_vga[0] |= (pitch & 0x300) >> 4;
931 ext_vga[1] = (((htotal - 4) & 0x100) >> 8) |
932 ((hdisplay & 0x100) >> 7) |
933 ((hsyncstart & 0x100) >> 6) |
935 ext_vga[2] = ((vtotal & 0xc00) >> 10) |
936 ((vdisplay & 0x400) >> 8) |
937 ((vdisplay & 0xc00) >> 7) |
938 ((vsyncstart & 0xc00) >> 5) |
939 ((vdisplay & 0x400) >> 3);
940 if (crtc->fb->bits_per_pixel == 24)
941 ext_vga[3] = (((1 << bppshift) * 3) - 1) | 0x80;
943 ext_vga[3] = ((1 << bppshift) - 1) | 0x80;
945 if (mdev->type == G200_WB)
948 ext_vga_index24 = 0x05;
950 /* Set pixel clocks */
952 WREG8(MGA_MISC_OUT, misc);
954 mga_crtc_set_plls(mdev, mode->clock);
956 for (i = 0; i < 6; i++) {
957 WREG_ECRT(i, ext_vga[i]);
960 if (mdev->type == G200_ER)
961 WREG_ECRT(24, ext_vga_index24);
963 if (mdev->type == G200_EV) {
967 WREG_ECRT(0, ext_vga[0]);
968 /* Enable mga pixel clock */
971 WREG8(MGA_MISC_OUT, misc);
974 memcpy(&mdev->mode, mode, sizeof(struct drm_display_mode));
976 mga_crtc_do_set_base(crtc, old_fb, x, y, 0);
979 if (mdev->type == G200_ER) {
980 u32 mem_ctl = RREG32(MGAREG_MEMCTL);
984 WREG8(MGAREG_SEQ_INDEX, 0x01);
985 seq1 = RREG8(MGAREG_SEQ_DATA) | 0x20;
986 WREG8(MGAREG_SEQ_DATA, seq1);
988 WREG32(MGAREG_MEMCTL, mem_ctl | 0x00200000);
990 WREG32(MGAREG_MEMCTL, mem_ctl & ~0x00200000);
992 WREG8(MGAREG_SEQ_DATA, seq1 & ~0x20);
996 if (IS_G200_SE(mdev)) {
997 if (mdev->reg_1e24 >= 0x02) {
1002 if (crtc->fb->bits_per_pixel > 16)
1004 else if (crtc->fb->bits_per_pixel > 8)
1009 mb = (mode->clock * bpp) / 1000;
1023 WREG8(0x1fde, 0x06);
1024 WREG8(0x1fdf, hi_pri_lvl);
1026 if (mdev->reg_1e24 >= 0x01)
1027 WREG8(0x1fdf, 0x03);
1029 WREG8(0x1fdf, 0x04);
1035 #if 0 /* code from mjg to attempt D3 on crtc dpms off - revisit later */
1036 static int mga_suspend(struct drm_crtc *crtc)
1038 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
1039 struct drm_device *dev = crtc->dev;
1040 struct mga_device *mdev = dev->dev_private;
1041 struct pci_dev *pdev = dev->pdev;
1044 if (mdev->suspended)
1049 /* Disable the pixel clock */
1050 WREG_DAC(0x1a, 0x05);
1051 /* Power down the DAC */
1052 WREG_DAC(0x1e, 0x18);
1053 /* Power down the pixel PLL */
1054 WREG_DAC(0x1a, 0x0d);
1056 /* Disable PLLs and clocks */
1057 pci_read_config_dword(pdev, PCI_MGA_OPTION, &option);
1058 option &= ~(0x1F8024);
1059 pci_write_config_dword(pdev, PCI_MGA_OPTION, option);
1060 pci_set_power_state(pdev, PCI_D3hot);
1061 pci_disable_device(pdev);
1063 mdev->suspended = true;
1068 static int mga_resume(struct drm_crtc *crtc)
1070 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
1071 struct drm_device *dev = crtc->dev;
1072 struct mga_device *mdev = dev->dev_private;
1073 struct pci_dev *pdev = dev->pdev;
1076 if (!mdev->suspended)
1079 pci_set_power_state(pdev, PCI_D0);
1080 pci_enable_device(pdev);
1082 /* Disable sysclk */
1083 pci_read_config_dword(pdev, PCI_MGA_OPTION, &option);
1085 pci_write_config_dword(pdev, PCI_MGA_OPTION, option);
1087 mdev->suspended = false;
1094 static void mga_crtc_dpms(struct drm_crtc *crtc, int mode)
1096 struct drm_device *dev = crtc->dev;
1097 struct mga_device *mdev = dev->dev_private;
1098 u8 seq1 = 0, crtcext1 = 0;
1101 case DRM_MODE_DPMS_ON:
1104 mga_crtc_load_lut(crtc);
1106 case DRM_MODE_DPMS_STANDBY:
1110 case DRM_MODE_DPMS_SUSPEND:
1114 case DRM_MODE_DPMS_OFF:
1121 if (mode == DRM_MODE_DPMS_OFF) {
1125 WREG8(MGAREG_SEQ_INDEX, 0x01);
1126 seq1 |= RREG8(MGAREG_SEQ_DATA) & ~0x20;
1127 mga_wait_vsync(mdev);
1128 mga_wait_busy(mdev);
1129 WREG8(MGAREG_SEQ_DATA, seq1);
1131 WREG8(MGAREG_CRTCEXT_INDEX, 0x01);
1132 crtcext1 |= RREG8(MGAREG_CRTCEXT_DATA) & ~0x30;
1133 WREG8(MGAREG_CRTCEXT_DATA, crtcext1);
1136 if (mode == DRM_MODE_DPMS_ON && mdev->suspended == true) {
1138 drm_helper_resume_force_mode(dev);
1144 * This is called before a mode is programmed. A typical use might be to
1145 * enable DPMS during the programming to avoid seeing intermediate stages,
1146 * but that's not relevant to us
1148 static void mga_crtc_prepare(struct drm_crtc *crtc)
1150 struct drm_device *dev = crtc->dev;
1151 struct mga_device *mdev = dev->dev_private;
1154 /* mga_resume(crtc);*/
1156 WREG8(MGAREG_CRTC_INDEX, 0x11);
1157 tmp = RREG8(MGAREG_CRTC_DATA);
1158 WREG_CRT(0x11, tmp | 0x80);
1160 if (mdev->type == G200_SE_A || mdev->type == G200_SE_B) {
1166 WREG8(MGAREG_SEQ_INDEX, 0x1);
1167 tmp = RREG8(MGAREG_SEQ_DATA);
1169 /* start sync reset */
1171 WREG_SEQ(1, tmp | 0x20);
1174 if (mdev->type == G200_WB)
1175 mga_g200wb_prepare(crtc);
1181 * This is called after a mode is programmed. It should reverse anything done
1182 * by the prepare function
1184 static void mga_crtc_commit(struct drm_crtc *crtc)
1186 struct drm_device *dev = crtc->dev;
1187 struct mga_device *mdev = dev->dev_private;
1188 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
1191 if (mdev->type == G200_WB)
1192 mga_g200wb_commit(crtc);
1194 if (mdev->type == G200_SE_A || mdev->type == G200_SE_B) {
1200 WREG8(MGAREG_SEQ_INDEX, 0x1);
1201 tmp = RREG8(MGAREG_SEQ_DATA);
1207 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
1211 * The core can pass us a set of gamma values to program. We actually only
1212 * use this for 8-bit mode so can't perform smooth fades on deeper modes,
1213 * but it's a requirement that we provide the function
1215 static void mga_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
1216 u16 *blue, uint32_t start, uint32_t size)
1218 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
1219 int end = (start + size > MGAG200_LUT_SIZE) ? MGAG200_LUT_SIZE : start + size;
1222 for (i = start; i < end; i++) {
1223 mga_crtc->lut_r[i] = red[i] >> 8;
1224 mga_crtc->lut_g[i] = green[i] >> 8;
1225 mga_crtc->lut_b[i] = blue[i] >> 8;
1227 mga_crtc_load_lut(crtc);
1230 /* Simple cleanup function */
1231 static void mga_crtc_destroy(struct drm_crtc *crtc)
1233 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
1235 drm_crtc_cleanup(crtc);
1239 /* These provide the minimum set of functions required to handle a CRTC */
1240 static const struct drm_crtc_funcs mga_crtc_funcs = {
1241 .gamma_set = mga_crtc_gamma_set,
1242 .set_config = drm_crtc_helper_set_config,
1243 .destroy = mga_crtc_destroy,
1246 static const struct drm_crtc_helper_funcs mga_helper_funcs = {
1247 .dpms = mga_crtc_dpms,
1248 .mode_fixup = mga_crtc_mode_fixup,
1249 .mode_set = mga_crtc_mode_set,
1250 .mode_set_base = mga_crtc_mode_set_base,
1251 .prepare = mga_crtc_prepare,
1252 .commit = mga_crtc_commit,
1253 .load_lut = mga_crtc_load_lut,
1257 static void mga_crtc_init(struct mga_device *mdev)
1259 struct mga_crtc *mga_crtc;
1262 mga_crtc = kzalloc(sizeof(struct mga_crtc) +
1263 (MGAG200FB_CONN_LIMIT * sizeof(struct drm_connector *)),
1266 if (mga_crtc == NULL)
1269 drm_crtc_init(mdev->dev, &mga_crtc->base, &mga_crtc_funcs);
1271 drm_mode_crtc_set_gamma_size(&mga_crtc->base, MGAG200_LUT_SIZE);
1272 mdev->mode_info.crtc = mga_crtc;
1274 for (i = 0; i < MGAG200_LUT_SIZE; i++) {
1275 mga_crtc->lut_r[i] = i;
1276 mga_crtc->lut_g[i] = i;
1277 mga_crtc->lut_b[i] = i;
1280 drm_crtc_helper_add(&mga_crtc->base, &mga_helper_funcs);
1283 /** Sets the color ramps on behalf of fbcon */
1284 void mga_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
1285 u16 blue, int regno)
1287 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
1289 mga_crtc->lut_r[regno] = red >> 8;
1290 mga_crtc->lut_g[regno] = green >> 8;
1291 mga_crtc->lut_b[regno] = blue >> 8;
1294 /** Gets the color ramps on behalf of fbcon */
1295 void mga_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
1296 u16 *blue, int regno)
1298 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
1300 *red = (u16)mga_crtc->lut_r[regno] << 8;
1301 *green = (u16)mga_crtc->lut_g[regno] << 8;
1302 *blue = (u16)mga_crtc->lut_b[regno] << 8;
1306 * The encoder comes after the CRTC in the output pipeline, but before
1307 * the connector. It's responsible for ensuring that the digital
1308 * stream is appropriately converted into the output format. Setup is
1309 * very simple in this case - all we have to do is inform qemu of the
1310 * colour depth in order to ensure that it displays appropriately
1314 * These functions are analagous to those in the CRTC code, but are intended
1315 * to handle any encoder-specific limitations
1317 static bool mga_encoder_mode_fixup(struct drm_encoder *encoder,
1318 const struct drm_display_mode *mode,
1319 struct drm_display_mode *adjusted_mode)
1324 static void mga_encoder_mode_set(struct drm_encoder *encoder,
1325 struct drm_display_mode *mode,
1326 struct drm_display_mode *adjusted_mode)
1331 static void mga_encoder_dpms(struct drm_encoder *encoder, int state)
1336 static void mga_encoder_prepare(struct drm_encoder *encoder)
1340 static void mga_encoder_commit(struct drm_encoder *encoder)
1344 void mga_encoder_destroy(struct drm_encoder *encoder)
1346 struct mga_encoder *mga_encoder = to_mga_encoder(encoder);
1347 drm_encoder_cleanup(encoder);
1351 static const struct drm_encoder_helper_funcs mga_encoder_helper_funcs = {
1352 .dpms = mga_encoder_dpms,
1353 .mode_fixup = mga_encoder_mode_fixup,
1354 .mode_set = mga_encoder_mode_set,
1355 .prepare = mga_encoder_prepare,
1356 .commit = mga_encoder_commit,
1359 static const struct drm_encoder_funcs mga_encoder_encoder_funcs = {
1360 .destroy = mga_encoder_destroy,
1363 static struct drm_encoder *mga_encoder_init(struct drm_device *dev)
1365 struct drm_encoder *encoder;
1366 struct mga_encoder *mga_encoder;
1368 mga_encoder = kzalloc(sizeof(struct mga_encoder), GFP_KERNEL);
1372 encoder = &mga_encoder->base;
1373 encoder->possible_crtcs = 0x1;
1375 drm_encoder_init(dev, encoder, &mga_encoder_encoder_funcs,
1376 DRM_MODE_ENCODER_DAC);
1377 drm_encoder_helper_add(encoder, &mga_encoder_helper_funcs);
1383 static int mga_vga_get_modes(struct drm_connector *connector)
1385 struct mga_connector *mga_connector = to_mga_connector(connector);
1389 edid = drm_get_edid(connector, &mga_connector->i2c->adapter);
1391 drm_mode_connector_update_edid_property(connector, edid);
1392 ret = drm_add_edid_modes(connector, edid);
1398 static int mga_vga_mode_valid(struct drm_connector *connector,
1399 struct drm_display_mode *mode)
1401 struct drm_device *dev = connector->dev;
1402 struct mga_device *mdev = (struct mga_device*)dev->dev_private;
1403 struct mga_fbdev *mfbdev = mdev->mfbdev;
1404 struct drm_fb_helper *fb_helper = &mfbdev->helper;
1405 struct drm_fb_helper_connector *fb_helper_conn = NULL;
1409 /* FIXME: Add bandwidth and g200se limitations */
1411 if (mode->crtc_hdisplay > 2048 || mode->crtc_hsync_start > 4096 ||
1412 mode->crtc_hsync_end > 4096 || mode->crtc_htotal > 4096 ||
1413 mode->crtc_vdisplay > 2048 || mode->crtc_vsync_start > 4096 ||
1414 mode->crtc_vsync_end > 4096 || mode->crtc_vtotal > 4096) {
1418 /* Validate the mode input by the user */
1419 for (i = 0; i < fb_helper->connector_count; i++) {
1420 if (fb_helper->connector_info[i]->connector == connector) {
1421 /* Found the helper for this connector */
1422 fb_helper_conn = fb_helper->connector_info[i];
1423 if (fb_helper_conn->cmdline_mode.specified) {
1424 if (fb_helper_conn->cmdline_mode.bpp_specified) {
1425 bpp = fb_helper_conn->cmdline_mode.bpp;
1431 if ((mode->hdisplay * mode->vdisplay * (bpp/8)) > mdev->mc.vram_size) {
1433 fb_helper_conn->cmdline_mode.specified = false;
1440 struct drm_encoder *mga_connector_best_encoder(struct drm_connector
1443 int enc_id = connector->encoder_ids[0];
1444 struct drm_mode_object *obj;
1445 struct drm_encoder *encoder;
1447 /* pick the encoder ids */
1450 drm_mode_object_find(connector->dev, enc_id,
1451 DRM_MODE_OBJECT_ENCODER);
1454 encoder = obj_to_encoder(obj);
1460 static enum drm_connector_status mga_vga_detect(struct drm_connector
1461 *connector, bool force)
1463 return connector_status_connected;
1466 static void mga_connector_destroy(struct drm_connector *connector)
1468 struct mga_connector *mga_connector = to_mga_connector(connector);
1469 mgag200_i2c_destroy(mga_connector->i2c);
1470 drm_connector_cleanup(connector);
1474 struct drm_connector_helper_funcs mga_vga_connector_helper_funcs = {
1475 .get_modes = mga_vga_get_modes,
1476 .mode_valid = mga_vga_mode_valid,
1477 .best_encoder = mga_connector_best_encoder,
1480 struct drm_connector_funcs mga_vga_connector_funcs = {
1481 .dpms = drm_helper_connector_dpms,
1482 .detect = mga_vga_detect,
1483 .fill_modes = drm_helper_probe_single_connector_modes,
1484 .destroy = mga_connector_destroy,
1487 static struct drm_connector *mga_vga_init(struct drm_device *dev)
1489 struct drm_connector *connector;
1490 struct mga_connector *mga_connector;
1492 mga_connector = kzalloc(sizeof(struct mga_connector), GFP_KERNEL);
1496 connector = &mga_connector->base;
1498 drm_connector_init(dev, connector,
1499 &mga_vga_connector_funcs, DRM_MODE_CONNECTOR_VGA);
1501 drm_connector_helper_add(connector, &mga_vga_connector_helper_funcs);
1503 mga_connector->i2c = mgag200_i2c_create(dev);
1504 if (!mga_connector->i2c)
1505 DRM_ERROR("failed to add ddc bus\n");
1511 int mgag200_modeset_init(struct mga_device *mdev)
1513 struct drm_encoder *encoder;
1514 struct drm_connector *connector;
1517 mdev->mode_info.mode_config_initialized = true;
1519 mdev->dev->mode_config.max_width = MGAG200_MAX_FB_WIDTH;
1520 mdev->dev->mode_config.max_height = MGAG200_MAX_FB_HEIGHT;
1522 mdev->dev->mode_config.fb_base = mdev->mc.vram_base;
1524 mga_crtc_init(mdev);
1526 encoder = mga_encoder_init(mdev->dev);
1528 DRM_ERROR("mga_encoder_init failed\n");
1532 connector = mga_vga_init(mdev->dev);
1534 DRM_ERROR("mga_vga_init failed\n");
1538 drm_mode_connector_attach_encoder(connector, encoder);
1540 ret = mgag200_fbdev_init(mdev);
1542 DRM_ERROR("mga_fbdev_init failed\n");
1549 void mgag200_modeset_fini(struct mga_device *mdev)