Pileus Git - ~andy/linux/blob - drivers/gpu/drm/i915/intel_ringbuffer.h

   1 #ifndef _INTEL_RINGBUFFER_H_
   2 #define _INTEL_RINGBUFFER_H_
   3
   4 struct  intel_hw_status_page {
   5         u32             *page_addr;
   6         unsigned int    gfx_addr;
   7         struct          drm_i915_gem_object *obj;
   8 };
   9
  10 #define I915_READ_TAIL(ring) I915_READ(RING_TAIL((ring)->mmio_base))
  11 #define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val)
  12
  13 #define I915_READ_START(ring) I915_READ(RING_START((ring)->mmio_base))
  14 #define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val)
  15
  16 #define I915_READ_HEAD(ring)  I915_READ(RING_HEAD((ring)->mmio_base))
  17 #define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val)
  18
  19 #define I915_READ_CTL(ring) I915_READ(RING_CTL((ring)->mmio_base))
  20 #define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val)
  21
  22 #define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base))
  23 #define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val)
  24
  25 #define I915_READ_NOPID(ring) I915_READ(RING_NOPID((ring)->mmio_base))
  26 #define I915_READ_SYNC_0(ring) I915_READ(RING_SYNC_0((ring)->mmio_base))
  27 #define I915_READ_SYNC_1(ring) I915_READ(RING_SYNC_1((ring)->mmio_base))
  28
  29 struct  intel_ring_buffer {
  30         const char      *name;
  31         enum intel_ring_id {
  32                 RCS = 0x0,
  33                 VCS,
  34                 BCS,
  35         } id;
  36 #define I915_NUM_RINGS 3
  37         u32             mmio_base;
  38         void            __iomem *virtual_start;
  39         struct          drm_device *dev;
  40         struct          drm_i915_gem_object *obj;
  41
  42         u32             head;
  43         u32             tail;
  44         int             space;
  45         int             size;
  46         int             effective_size;
  47         struct intel_hw_status_page status_page;
  48
  49         /** We track the position of the requests in the ring buffer, and
  50          * when each is retired we increment last_retired_head as the GPU
  51          * must have finished processing the request and so we know we
  52          * can advance the ringbuffer up to that position.
  53          *
  54          * last_retired_head is set to -1 after the value is consumed so
  55          * we can detect new retirements.
  56          */
  57         u32             last_retired_head;
  58
  59         u32             irq_refcount;           /* protected by dev_priv->irq_lock */
  60         u32             irq_enable_mask;        /* bitmask to enable ring interrupt */
  61         u32             trace_irq_seqno;
  62         u32             sync_seqno[I915_NUM_RINGS-1];
  63         bool __must_check (*irq_get)(struct intel_ring_buffer *ring);
  64         void            (*irq_put)(struct intel_ring_buffer *ring);
  65
  66         int             (*init)(struct intel_ring_buffer *ring);
  67
  68         void            (*write_tail)(struct intel_ring_buffer *ring,
  69                                       u32 value);
  70         int __must_check (*flush)(struct intel_ring_buffer *ring,
  71                                   u32   invalidate_domains,
  72                                   u32   flush_domains);
  73         int             (*add_request)(struct intel_ring_buffer *ring,
  74                                        u32 *seqno);
  75         /* Some chipsets are not quite as coherent as advertised and need
  76          * an expensive kick to force a true read of the up-to-date seqno.
  77          * However, the up-to-date seqno is not always required and the last
  78          * seen value is good enough. Note that the seqno will always be
  79          * monotonic, even if not coherent.
  80          */
  81         u32             (*get_seqno)(struct intel_ring_buffer *ring,
  82                                      bool lazy_coherency);
  83         int             (*dispatch_execbuffer)(struct intel_ring_buffer *ring,
  84                                                u32 offset, u32 length);
  85         void            (*cleanup)(struct intel_ring_buffer *ring);
  86         int             (*sync_to)(struct intel_ring_buffer *ring,
  87                                    struct intel_ring_buffer *to,
  88                                    u32 seqno);
  89
  90         u32             semaphore_register[3]; /*our mbox written by others */
  91         u32             signal_mbox[2]; /* mboxes this ring signals to */
  92         /**
  93          * List of objects currently involved in rendering from the
  94          * ringbuffer.
  95          *
  96          * Includes buffers having the contents of their GPU caches
  97          * flushed, not necessarily primitives.  last_rendering_seqno
  98          * represents when the rendering involved will be completed.
  99          *
 100          * A reference is held on the buffer while on this list.
 101          */
 102         struct list_head active_list;
 103
 104         /**
 105          * List of breadcrumbs associated with GPU requests currently
 106          * outstanding.
 107          */
 108         struct list_head request_list;
 109
 110         /**
 111          * Do we have some not yet emitted requests outstanding?
 112          */
 113         u32 outstanding_lazy_request;
 114         bool gpu_caches_dirty;
 115
 116         wait_queue_head_t irq_queue;
 117
 118         /**
 119          * Do an explicit TLB flush before MI_SET_CONTEXT
 120          */
 121         bool itlb_before_ctx_switch;
 122         struct i915_hw_context *default_context;
 123         struct drm_i915_gem_object *last_context_obj;
 124
 125         void *private;
 126 };
 127
 128 static inline bool
 129 intel_ring_initialized(struct intel_ring_buffer *ring)
 130 {
 131         return ring->obj != NULL;
 132 }
 133
 134 static inline unsigned
 135 intel_ring_flag(struct intel_ring_buffer *ring)
 136 {
 137         return 1 << ring->id;
 138 }
 139
 140 static inline u32
 141 intel_ring_sync_index(struct intel_ring_buffer *ring,
 142                       struct intel_ring_buffer *other)
 143 {
 144         int idx;
 145
 146         /*
 147          * cs -> 0 = vcs, 1 = bcs
 148          * vcs -> 0 = bcs, 1 = cs,
 149          * bcs -> 0 = cs, 1 = vcs.
 150          */
 151
 152         idx = (other - ring) - 1;
 153         if (idx < 0)
 154                 idx += I915_NUM_RINGS;
 155
 156         return idx;
 157 }
 158
 159 static inline u32
 160 intel_read_status_page(struct intel_ring_buffer *ring,
 161                        int reg)
 162 {
 163         /* Ensure that the compiler doesn't optimize away the load. */
 164         barrier();
 165         return ring->status_page.page_addr[reg];
 166 }
 167
 168 /**
 169  * Reads a dword out of the status page, which is written to from the command
 170  * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
 171  * MI_STORE_DATA_IMM.
 172  *
 173  * The following dwords have a reserved meaning:
 174  * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
 175  * 0x04: ring 0 head pointer
 176  * 0x05: ring 1 head pointer (915-class)
 177  * 0x06: ring 2 head pointer (915-class)
 178  * 0x10-0x1b: Context status DWords (GM45)
 179  * 0x1f: Last written status offset. (GM45)
 180  *
 181  * The area from dword 0x20 to 0x3ff is available for driver usage.
 182  */
 183 #define I915_GEM_HWS_INDEX              0x20
 184
 185 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring);
 186
 187 int __must_check intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n);
 188 static inline int intel_wait_ring_idle(struct intel_ring_buffer *ring)
 189 {
 190         return intel_wait_ring_buffer(ring, ring->size - 8);
 191 }
 192
 193 int __must_check intel_ring_begin(struct intel_ring_buffer *ring, int n);
 194
 195 static inline void intel_ring_emit(struct intel_ring_buffer *ring,
 196                                    u32 data)
 197 {
 198         iowrite32(data, ring->virtual_start + ring->tail);
 199         ring->tail += 4;
 200 }
 201
 202 void intel_ring_advance(struct intel_ring_buffer *ring);
 203
 204 u32 intel_ring_get_seqno(struct intel_ring_buffer *ring);
 205 int intel_ring_flush_all_caches(struct intel_ring_buffer *ring);
 206 int intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring);
 207
 208 int intel_init_render_ring_buffer(struct drm_device *dev);
 209 int intel_init_bsd_ring_buffer(struct drm_device *dev);
 210 int intel_init_blt_ring_buffer(struct drm_device *dev);
 211
 212 u32 intel_ring_get_active_head(struct intel_ring_buffer *ring);
 213 void intel_ring_setup_status_page(struct intel_ring_buffer *ring);
 214
 215 static inline u32 intel_ring_get_tail(struct intel_ring_buffer *ring)
 216 {
 217         return ring->tail;
 218 }
 219
 220 static inline void i915_trace_irq_get(struct intel_ring_buffer *ring, u32 seqno)
 221 {
 222         if (ring->trace_irq_seqno == 0 && ring->irq_get(ring))
 223                 ring->trace_irq_seqno = seqno;
 224 }
 225
 226 /* DRI warts */
 227 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size);
 228
 229 #endif /* _INTEL_RINGBUFFER_H_ */