Pileus Git - ~andy/linux/blob - drivers/gpu/drm/i915/intel_ringbuffer.c

   1 /*
   2  * Copyright © 2008-2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Zou Nan hai <nanhai.zou@intel.com>
  26  *    Xiang Hai hao<haihao.xiang@intel.com>
  27  *
  28  */
  29
  30 #include "drmP.h"
  31 #include "drm.h"
  32 #include "i915_drv.h"
  33 #include "i915_drm.h"
  34 #include "i915_trace.h"
  35 #include "intel_drv.h"
  36
  37 /*
  38  * 965+ support PIPE_CONTROL commands, which provide finer grained control
  39  * over cache flushing.
  40  */
  41 struct pipe_control {
  42         struct drm_i915_gem_object *obj;
  43         volatile u32 *cpu_page;
  44         u32 gtt_offset;
  45 };
  46
  47 static inline int ring_space(struct intel_ring_buffer *ring)
  48 {
  49         int space = (ring->head & HEAD_ADDR) - (ring->tail + 8);
  50         if (space < 0)
  51                 space += ring->size;
  52         return space;
  53 }
  54
  55 static u32 i915_gem_get_seqno(struct drm_device *dev)
  56 {
  57         drm_i915_private_t *dev_priv = dev->dev_private;
  58         u32 seqno;
  59
  60         seqno = dev_priv->next_seqno;
  61
  62         /* reserve 0 for non-seqno */
  63         if (++dev_priv->next_seqno == 0)
  64                 dev_priv->next_seqno = 1;
  65
  66         return seqno;
  67 }
  68
  69 static int
  70 render_ring_flush(struct intel_ring_buffer *ring,
  71                   u32   invalidate_domains,
  72                   u32   flush_domains)
  73 {
  74         struct drm_device *dev = ring->dev;
  75         u32 cmd;
  76         int ret;
  77
  78         /*
  79          * read/write caches:
  80          *
  81          * I915_GEM_DOMAIN_RENDER is always invalidated, but is
  82          * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
  83          * also flushed at 2d versus 3d pipeline switches.
  84          *
  85          * read-only caches:
  86          *
  87          * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
  88          * MI_READ_FLUSH is set, and is always flushed on 965.
  89          *
  90          * I915_GEM_DOMAIN_COMMAND may not exist?
  91          *
  92          * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
  93          * invalidated when MI_EXE_FLUSH is set.
  94          *
  95          * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
  96          * invalidated with every MI_FLUSH.
  97          *
  98          * TLBs:
  99          *
 100          * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
 101          * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
 102          * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
 103          * are flushed at any MI_FLUSH.
 104          */
 105
 106         cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
 107         if ((invalidate_domains|flush_domains) &
 108             I915_GEM_DOMAIN_RENDER)
 109                 cmd &= ~MI_NO_WRITE_FLUSH;
 110         if (INTEL_INFO(dev)->gen < 4) {
 111                 /*
 112                  * On the 965, the sampler cache always gets flushed
 113                  * and this bit is reserved.
 114                  */
 115                 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
 116                         cmd |= MI_READ_FLUSH;
 117         }
 118         if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
 119                 cmd |= MI_EXE_FLUSH;
 120
 121         if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
 122             (IS_G4X(dev) || IS_GEN5(dev)))
 123                 cmd |= MI_INVALIDATE_ISP;
 124
 125         ret = intel_ring_begin(ring, 2);
 126         if (ret)
 127                 return ret;
 128
 129         intel_ring_emit(ring, cmd);
 130         intel_ring_emit(ring, MI_NOOP);
 131         intel_ring_advance(ring);
 132
 133         return 0;
 134 }
 135
 136 /**
 137  * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
 138  * implementing two workarounds on gen6.  From section 1.4.7.1
 139  * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
 140  *
 141  * [DevSNB-C+{W/A}] Before any depth stall flush (including those
 142  * produced by non-pipelined state commands), software needs to first
 143  * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
 144  * 0.
 145  *
 146  * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
 147  * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
 148  *
 149  * And the workaround for these two requires this workaround first:
 150  *
 151  * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
 152  * BEFORE the pipe-control with a post-sync op and no write-cache
 153  * flushes.
 154  *
 155  * And this last workaround is tricky because of the requirements on
 156  * that bit.  From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
 157  * volume 2 part 1:
 158  *
 159  *     "1 of the following must also be set:
 160  *      - Render Target Cache Flush Enable ([12] of DW1)
 161  *      - Depth Cache Flush Enable ([0] of DW1)
 162  *      - Stall at Pixel Scoreboard ([1] of DW1)
 163  *      - Depth Stall ([13] of DW1)
 164  *      - Post-Sync Operation ([13] of DW1)
 165  *      - Notify Enable ([8] of DW1)"
 166  *
 167  * The cache flushes require the workaround flush that triggered this
 168  * one, so we can't use it.  Depth stall would trigger the same.
 169  * Post-sync nonzero is what triggered this second workaround, so we
 170  * can't use that one either.  Notify enable is IRQs, which aren't
 171  * really our business.  That leaves only stall at scoreboard.
 172  */
 173 static int
 174 intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring)
 175 {
 176         struct pipe_control *pc = ring->private;
 177         u32 scratch_addr = pc->gtt_offset + 128;
 178         int ret;
 179
 180
 181         ret = intel_ring_begin(ring, 6);
 182         if (ret)
 183                 return ret;
 184
 185         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 186         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 187                         PIPE_CONTROL_STALL_AT_SCOREBOARD);
 188         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 189         intel_ring_emit(ring, 0); /* low dword */
 190         intel_ring_emit(ring, 0); /* high dword */
 191         intel_ring_emit(ring, MI_NOOP);
 192         intel_ring_advance(ring);
 193
 194         ret = intel_ring_begin(ring, 6);
 195         if (ret)
 196                 return ret;
 197
 198         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 199         intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
 200         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 201         intel_ring_emit(ring, 0);
 202         intel_ring_emit(ring, 0);
 203         intel_ring_emit(ring, MI_NOOP);
 204         intel_ring_advance(ring);
 205
 206         return 0;
 207 }
 208
 209 static int
 210 gen6_render_ring_flush(struct intel_ring_buffer *ring,
 211                          u32 invalidate_domains, u32 flush_domains)
 212 {
 213         u32 flags = 0;
 214         struct pipe_control *pc = ring->private;
 215         u32 scratch_addr = pc->gtt_offset + 128;
 216         int ret;
 217
 218         /* Force SNB workarounds for PIPE_CONTROL flushes */
 219         intel_emit_post_sync_nonzero_flush(ring);
 220
 221         /* Just flush everything.  Experiments have shown that reducing the
 222          * number of bits based on the write domains has little performance
 223          * impact.
 224          */
 225         flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 226         flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 227         flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 228         flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 229         flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 230         flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 231         flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 232
 233         ret = intel_ring_begin(ring, 6);
 234         if (ret)
 235                 return ret;
 236
 237         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 238         intel_ring_emit(ring, flags);
 239         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
 240         intel_ring_emit(ring, 0); /* lower dword */
 241         intel_ring_emit(ring, 0); /* uppwer dword */
 242         intel_ring_emit(ring, MI_NOOP);
 243         intel_ring_advance(ring);
 244
 245         return 0;
 246 }
 247
 248 static void ring_write_tail(struct intel_ring_buffer *ring,
 249                             u32 value)
 250 {
 251         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 252         I915_WRITE_TAIL(ring, value);
 253 }
 254
 255 u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
 256 {
 257         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 258         u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
 259                         RING_ACTHD(ring->mmio_base) : ACTHD;
 260
 261         return I915_READ(acthd_reg);
 262 }
 263
 264 static int init_ring_common(struct intel_ring_buffer *ring)
 265 {
 266         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 267         struct drm_i915_gem_object *obj = ring->obj;
 268         u32 head;
 269
 270         /* Stop the ring if it's running. */
 271         I915_WRITE_CTL(ring, 0);
 272         I915_WRITE_HEAD(ring, 0);
 273         ring->write_tail(ring, 0);
 274
 275         /* Initialize the ring. */
 276         I915_WRITE_START(ring, obj->gtt_offset);
 277         head = I915_READ_HEAD(ring) & HEAD_ADDR;
 278
 279         /* G45 ring initialization fails to reset head to zero */
 280         if (head != 0) {
 281                 DRM_DEBUG_KMS("%s head not reset to zero "
 282                               "ctl %08x head %08x tail %08x start %08x\n",
 283                               ring->name,
 284                               I915_READ_CTL(ring),
 285                               I915_READ_HEAD(ring),
 286                               I915_READ_TAIL(ring),
 287                               I915_READ_START(ring));
 288
 289                 I915_WRITE_HEAD(ring, 0);
 290
 291                 if (I915_READ_HEAD(ring) & HEAD_ADDR) {
 292                         DRM_ERROR("failed to set %s head to zero "
 293                                   "ctl %08x head %08x tail %08x start %08x\n",
 294                                   ring->name,
 295                                   I915_READ_CTL(ring),
 296                                   I915_READ_HEAD(ring),
 297                                   I915_READ_TAIL(ring),
 298                                   I915_READ_START(ring));
 299                 }
 300         }
 301
 302         I915_WRITE_CTL(ring,
 303                         ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
 304                         | RING_REPORT_64K | RING_VALID);
 305
 306         /* If the head is still not zero, the ring is dead */
 307         if ((I915_READ_CTL(ring) & RING_VALID) == 0 ||
 308             I915_READ_START(ring) != obj->gtt_offset ||
 309             (I915_READ_HEAD(ring) & HEAD_ADDR) != 0) {
 310                 DRM_ERROR("%s initialization failed "
 311                                 "ctl %08x head %08x tail %08x start %08x\n",
 312                                 ring->name,
 313                                 I915_READ_CTL(ring),
 314                                 I915_READ_HEAD(ring),
 315                                 I915_READ_TAIL(ring),
 316                                 I915_READ_START(ring));
 317                 return -EIO;
 318         }
 319
 320         if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
 321                 i915_kernel_lost_context(ring->dev);
 322         else {
 323                 ring->head = I915_READ_HEAD(ring);
 324                 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 325                 ring->space = ring_space(ring);
 326         }
 327
 328         return 0;
 329 }
 330
 331 static int
 332 init_pipe_control(struct intel_ring_buffer *ring)
 333 {
 334         struct pipe_control *pc;
 335         struct drm_i915_gem_object *obj;
 336         int ret;
 337
 338         if (ring->private)
 339                 return 0;
 340
 341         pc = kmalloc(sizeof(*pc), GFP_KERNEL);
 342         if (!pc)
 343                 return -ENOMEM;
 344
 345         obj = i915_gem_alloc_object(ring->dev, 4096);
 346         if (obj == NULL) {
 347                 DRM_ERROR("Failed to allocate seqno page\n");
 348                 ret = -ENOMEM;
 349                 goto err;
 350         }
 351
 352         i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
 353
 354         ret = i915_gem_object_pin(obj, 4096, true);
 355         if (ret)
 356                 goto err_unref;
 357
 358         pc->gtt_offset = obj->gtt_offset;
 359         pc->cpu_page =  kmap(obj->pages[0]);
 360         if (pc->cpu_page == NULL)
 361                 goto err_unpin;
 362
 363         pc->obj = obj;
 364         ring->private = pc;
 365         return 0;
 366
 367 err_unpin:
 368         i915_gem_object_unpin(obj);
 369 err_unref:
 370         drm_gem_object_unreference(&obj->base);
 371 err:
 372         kfree(pc);
 373         return ret;
 374 }
 375
 376 static void
 377 cleanup_pipe_control(struct intel_ring_buffer *ring)
 378 {
 379         struct pipe_control *pc = ring->private;
 380         struct drm_i915_gem_object *obj;
 381
 382         if (!ring->private)
 383                 return;
 384
 385         obj = pc->obj;
 386         kunmap(obj->pages[0]);
 387         i915_gem_object_unpin(obj);
 388         drm_gem_object_unreference(&obj->base);
 389
 390         kfree(pc);
 391         ring->private = NULL;
 392 }
 393
 394 static int init_render_ring(struct intel_ring_buffer *ring)
 395 {
 396         struct drm_device *dev = ring->dev;
 397         struct drm_i915_private *dev_priv = dev->dev_private;
 398         int ret = init_ring_common(ring);
 399
 400         if (INTEL_INFO(dev)->gen > 3) {
 401                 int mode = VS_TIMER_DISPATCH << 16 | VS_TIMER_DISPATCH;
 402                 if (IS_GEN6(dev) || IS_GEN7(dev))
 403                         mode |= MI_FLUSH_ENABLE << 16 | MI_FLUSH_ENABLE;
 404                 I915_WRITE(MI_MODE, mode);
 405                 if (IS_GEN7(dev))
 406                         I915_WRITE(GFX_MODE_GEN7,
 407                                    GFX_MODE_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
 408                                    GFX_MODE_ENABLE(GFX_REPLAY_MODE));
 409         }
 410
 411         if (INTEL_INFO(dev)->gen >= 5) {
 412                 ret = init_pipe_control(ring);
 413                 if (ret)
 414                         return ret;
 415         }
 416
 417         if (INTEL_INFO(dev)->gen >= 6) {
 418                 I915_WRITE(INSTPM,
 419                            INSTPM_FORCE_ORDERING << 16 | INSTPM_FORCE_ORDERING);
 420         }
 421
 422         return ret;
 423 }
 424
 425 static void render_ring_cleanup(struct intel_ring_buffer *ring)
 426 {
 427         if (!ring->private)
 428                 return;
 429
 430         cleanup_pipe_control(ring);
 431 }
 432
 433 static void
 434 update_mboxes(struct intel_ring_buffer *ring,
 435             u32 seqno,
 436             u32 mmio_offset)
 437 {
 438         intel_ring_emit(ring, MI_SEMAPHORE_MBOX |
 439                               MI_SEMAPHORE_GLOBAL_GTT |
 440                               MI_SEMAPHORE_REGISTER |
 441                               MI_SEMAPHORE_UPDATE);
 442         intel_ring_emit(ring, seqno);
 443         intel_ring_emit(ring, mmio_offset);
 444 }
 445
 446 /**
 447  * gen6_add_request - Update the semaphore mailbox registers
 448  *
 449  * @ring - ring that is adding a request
 450  * @seqno - return seqno stuck into the ring
 451  *
 452  * Update the mailbox registers in the *other* rings with the current seqno.
 453  * This acts like a signal in the canonical semaphore.
 454  */
 455 static int
 456 gen6_add_request(struct intel_ring_buffer *ring,
 457                  u32 *seqno)
 458 {
 459         u32 mbox1_reg;
 460         u32 mbox2_reg;
 461         int ret;
 462
 463         ret = intel_ring_begin(ring, 10);
 464         if (ret)
 465                 return ret;
 466
 467         mbox1_reg = ring->signal_mbox[0];
 468         mbox2_reg = ring->signal_mbox[1];
 469
 470         *seqno = i915_gem_get_seqno(ring->dev);
 471
 472         update_mboxes(ring, *seqno, mbox1_reg);
 473         update_mboxes(ring, *seqno, mbox2_reg);
 474         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
 475         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 476         intel_ring_emit(ring, *seqno);
 477         intel_ring_emit(ring, MI_USER_INTERRUPT);
 478         intel_ring_advance(ring);
 479
 480         return 0;
 481 }
 482
 483 /**
 484  * intel_ring_sync - sync the waiter to the signaller on seqno
 485  *
 486  * @waiter - ring that is waiting
 487  * @signaller - ring which has, or will signal
 488  * @seqno - seqno which the waiter will block on
 489  */
 490 static int
 491 intel_ring_sync(struct intel_ring_buffer *waiter,
 492                 struct intel_ring_buffer *signaller,
 493                 int ring,
 494                 u32 seqno)
 495 {
 496         int ret;
 497         u32 dw1 = MI_SEMAPHORE_MBOX |
 498                   MI_SEMAPHORE_COMPARE |
 499                   MI_SEMAPHORE_REGISTER;
 500
 501         ret = intel_ring_begin(waiter, 4);
 502         if (ret)
 503                 return ret;
 504
 505         intel_ring_emit(waiter, dw1 | signaller->semaphore_register[ring]);
 506         intel_ring_emit(waiter, seqno);
 507         intel_ring_emit(waiter, 0);
 508         intel_ring_emit(waiter, MI_NOOP);
 509         intel_ring_advance(waiter);
 510
 511         return 0;
 512 }
 513
 514 /* VCS->RCS (RVSYNC) or BCS->RCS (RBSYNC) */
 515 int
 516 render_ring_sync_to(struct intel_ring_buffer *waiter,
 517                     struct intel_ring_buffer *signaller,
 518                     u32 seqno)
 519 {
 520         WARN_ON(signaller->semaphore_register[RCS] == MI_SEMAPHORE_SYNC_INVALID);
 521         return intel_ring_sync(waiter,
 522                                signaller,
 523                                RCS,
 524                                seqno);
 525 }
 526
 527 /* RCS->VCS (VRSYNC) or BCS->VCS (VBSYNC) */
 528 int
 529 gen6_bsd_ring_sync_to(struct intel_ring_buffer *waiter,
 530                       struct intel_ring_buffer *signaller,
 531                       u32 seqno)
 532 {
 533         WARN_ON(signaller->semaphore_register[VCS] == MI_SEMAPHORE_SYNC_INVALID);
 534         return intel_ring_sync(waiter,
 535                                signaller,
 536                                VCS,
 537                                seqno);
 538 }
 539
 540 /* RCS->BCS (BRSYNC) or VCS->BCS (BVSYNC) */
 541 int
 542 gen6_blt_ring_sync_to(struct intel_ring_buffer *waiter,
 543                       struct intel_ring_buffer *signaller,
 544                       u32 seqno)
 545 {
 546         WARN_ON(signaller->semaphore_register[BCS] == MI_SEMAPHORE_SYNC_INVALID);
 547         return intel_ring_sync(waiter,
 548                                signaller,
 549                                BCS,
 550                                seqno);
 551 }
 552
 553
 554
 555 #define PIPE_CONTROL_FLUSH(ring__, addr__)                                      \
 556 do {                                                                    \
 557         intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |                \
 558                  PIPE_CONTROL_DEPTH_STALL);                             \
 559         intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT);                    \
 560         intel_ring_emit(ring__, 0);                                                     \
 561         intel_ring_emit(ring__, 0);                                                     \
 562 } while (0)
 563
 564 static int
 565 pc_render_add_request(struct intel_ring_buffer *ring,
 566                       u32 *result)
 567 {
 568         struct drm_device *dev = ring->dev;
 569         u32 seqno = i915_gem_get_seqno(dev);
 570         struct pipe_control *pc = ring->private;
 571         u32 scratch_addr = pc->gtt_offset + 128;
 572         int ret;
 573
 574         /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
 575          * incoherent with writes to memory, i.e. completely fubar,
 576          * so we need to use PIPE_NOTIFY instead.
 577          *
 578          * However, we also need to workaround the qword write
 579          * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
 580          * memory before requesting an interrupt.
 581          */
 582         ret = intel_ring_begin(ring, 32);
 583         if (ret)
 584                 return ret;
 585
 586         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
 587                         PIPE_CONTROL_WRITE_FLUSH |
 588                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
 589         intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
 590         intel_ring_emit(ring, seqno);
 591         intel_ring_emit(ring, 0);
 592         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 593         scratch_addr += 128; /* write to separate cachelines */
 594         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 595         scratch_addr += 128;
 596         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 597         scratch_addr += 128;
 598         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 599         scratch_addr += 128;
 600         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 601         scratch_addr += 128;
 602         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 603         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
 604                         PIPE_CONTROL_WRITE_FLUSH |
 605                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
 606                         PIPE_CONTROL_NOTIFY);
 607         intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
 608         intel_ring_emit(ring, seqno);
 609         intel_ring_emit(ring, 0);
 610         intel_ring_advance(ring);
 611
 612         *result = seqno;
 613         return 0;
 614 }
 615
 616 static int
 617 render_ring_add_request(struct intel_ring_buffer *ring,
 618                         u32 *result)
 619 {
 620         struct drm_device *dev = ring->dev;
 621         u32 seqno = i915_gem_get_seqno(dev);
 622         int ret;
 623
 624         ret = intel_ring_begin(ring, 4);
 625         if (ret)
 626                 return ret;
 627
 628         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
 629         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 630         intel_ring_emit(ring, seqno);
 631         intel_ring_emit(ring, MI_USER_INTERRUPT);
 632         intel_ring_advance(ring);
 633
 634         *result = seqno;
 635         return 0;
 636 }
 637
 638 static u32
 639 ring_get_seqno(struct intel_ring_buffer *ring)
 640 {
 641         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
 642 }
 643
 644 static u32
 645 pc_render_get_seqno(struct intel_ring_buffer *ring)
 646 {
 647         struct pipe_control *pc = ring->private;
 648         return pc->cpu_page[0];
 649 }
 650
 651 static void
 652 ironlake_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
 653 {
 654         dev_priv->gt_irq_mask &= ~mask;
 655         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 656         POSTING_READ(GTIMR);
 657 }
 658
 659 static void
 660 ironlake_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
 661 {
 662         dev_priv->gt_irq_mask |= mask;
 663         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 664         POSTING_READ(GTIMR);
 665 }
 666
 667 static void
 668 i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
 669 {
 670         dev_priv->irq_mask &= ~mask;
 671         I915_WRITE(IMR, dev_priv->irq_mask);
 672         POSTING_READ(IMR);
 673 }
 674
 675 static void
 676 i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
 677 {
 678         dev_priv->irq_mask |= mask;
 679         I915_WRITE(IMR, dev_priv->irq_mask);
 680         POSTING_READ(IMR);
 681 }
 682
 683 static bool
 684 render_ring_get_irq(struct intel_ring_buffer *ring)
 685 {
 686         struct drm_device *dev = ring->dev;
 687         drm_i915_private_t *dev_priv = dev->dev_private;
 688
 689         if (!dev->irq_enabled)
 690                 return false;
 691
 692         spin_lock(&ring->irq_lock);
 693         if (ring->irq_refcount++ == 0) {
 694                 if (HAS_PCH_SPLIT(dev))
 695                         ironlake_enable_irq(dev_priv,
 696                                             GT_PIPE_NOTIFY | GT_USER_INTERRUPT);
 697                 else
 698                         i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
 699         }
 700         spin_unlock(&ring->irq_lock);
 701
 702         return true;
 703 }
 704
 705 static void
 706 render_ring_put_irq(struct intel_ring_buffer *ring)
 707 {
 708         struct drm_device *dev = ring->dev;
 709         drm_i915_private_t *dev_priv = dev->dev_private;
 710
 711         spin_lock(&ring->irq_lock);
 712         if (--ring->irq_refcount == 0) {
 713                 if (HAS_PCH_SPLIT(dev))
 714                         ironlake_disable_irq(dev_priv,
 715                                              GT_USER_INTERRUPT |
 716                                              GT_PIPE_NOTIFY);
 717                 else
 718                         i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
 719         }
 720         spin_unlock(&ring->irq_lock);
 721 }
 722
 723 void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
 724 {
 725         struct drm_device *dev = ring->dev;
 726         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 727         u32 mmio = 0;
 728
 729         /* The ring status page addresses are no longer next to the rest of
 730          * the ring registers as of gen7.
 731          */
 732         if (IS_GEN7(dev)) {
 733                 switch (ring->id) {
 734                 case RING_RENDER:
 735                         mmio = RENDER_HWS_PGA_GEN7;
 736                         break;
 737                 case RING_BLT:
 738                         mmio = BLT_HWS_PGA_GEN7;
 739                         break;
 740                 case RING_BSD:
 741                         mmio = BSD_HWS_PGA_GEN7;
 742                         break;
 743                 }
 744         } else if (IS_GEN6(ring->dev)) {
 745                 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
 746         } else {
 747                 mmio = RING_HWS_PGA(ring->mmio_base);
 748         }
 749
 750         I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
 751         POSTING_READ(mmio);
 752 }
 753
 754 static int
 755 bsd_ring_flush(struct intel_ring_buffer *ring,
 756                u32     invalidate_domains,
 757                u32     flush_domains)
 758 {
 759         int ret;
 760
 761         ret = intel_ring_begin(ring, 2);
 762         if (ret)
 763                 return ret;
 764
 765         intel_ring_emit(ring, MI_FLUSH);
 766         intel_ring_emit(ring, MI_NOOP);
 767         intel_ring_advance(ring);
 768         return 0;
 769 }
 770
 771 static int
 772 ring_add_request(struct intel_ring_buffer *ring,
 773                  u32 *result)
 774 {
 775         u32 seqno;
 776         int ret;
 777
 778         ret = intel_ring_begin(ring, 4);
 779         if (ret)
 780                 return ret;
 781
 782         seqno = i915_gem_get_seqno(ring->dev);
 783
 784         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
 785         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 786         intel_ring_emit(ring, seqno);
 787         intel_ring_emit(ring, MI_USER_INTERRUPT);
 788         intel_ring_advance(ring);
 789
 790         *result = seqno;
 791         return 0;
 792 }
 793
 794 static bool
 795 gen6_ring_get_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
 796 {
 797         struct drm_device *dev = ring->dev;
 798         drm_i915_private_t *dev_priv = dev->dev_private;
 799
 800         if (!dev->irq_enabled)
 801                return false;
 802
 803         spin_lock(&ring->irq_lock);
 804         if (ring->irq_refcount++ == 0) {
 805                 ring->irq_mask &= ~rflag;
 806                 I915_WRITE_IMR(ring, ring->irq_mask);
 807                 ironlake_enable_irq(dev_priv, gflag);
 808         }
 809         spin_unlock(&ring->irq_lock);
 810
 811         return true;
 812 }
 813
 814 static void
 815 gen6_ring_put_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
 816 {
 817         struct drm_device *dev = ring->dev;
 818         drm_i915_private_t *dev_priv = dev->dev_private;
 819
 820         spin_lock(&ring->irq_lock);
 821         if (--ring->irq_refcount == 0) {
 822                 ring->irq_mask |= rflag;
 823                 I915_WRITE_IMR(ring, ring->irq_mask);
 824                 ironlake_disable_irq(dev_priv, gflag);
 825         }
 826         spin_unlock(&ring->irq_lock);
 827 }
 828
 829 static bool
 830 bsd_ring_get_irq(struct intel_ring_buffer *ring)
 831 {
 832         struct drm_device *dev = ring->dev;
 833         drm_i915_private_t *dev_priv = dev->dev_private;
 834
 835         if (!dev->irq_enabled)
 836                 return false;
 837
 838         spin_lock(&ring->irq_lock);
 839         if (ring->irq_refcount++ == 0) {
 840                 if (IS_G4X(dev))
 841                         i915_enable_irq(dev_priv, I915_BSD_USER_INTERRUPT);
 842                 else
 843                         ironlake_enable_irq(dev_priv, GT_BSD_USER_INTERRUPT);
 844         }
 845         spin_unlock(&ring->irq_lock);
 846
 847         return true;
 848 }
 849 static void
 850 bsd_ring_put_irq(struct intel_ring_buffer *ring)
 851 {
 852         struct drm_device *dev = ring->dev;
 853         drm_i915_private_t *dev_priv = dev->dev_private;
 854
 855         spin_lock(&ring->irq_lock);
 856         if (--ring->irq_refcount == 0) {
 857                 if (IS_G4X(dev))
 858                         i915_disable_irq(dev_priv, I915_BSD_USER_INTERRUPT);
 859                 else
 860                         ironlake_disable_irq(dev_priv, GT_BSD_USER_INTERRUPT);
 861         }
 862         spin_unlock(&ring->irq_lock);
 863 }
 864
 865 static int
 866 ring_dispatch_execbuffer(struct intel_ring_buffer *ring, u32 offset, u32 length)
 867 {
 868         int ret;
 869
 870         ret = intel_ring_begin(ring, 2);
 871         if (ret)
 872                 return ret;
 873
 874         intel_ring_emit(ring,
 875                         MI_BATCH_BUFFER_START | (2 << 6) |
 876                         MI_BATCH_NON_SECURE_I965);
 877         intel_ring_emit(ring, offset);
 878         intel_ring_advance(ring);
 879
 880         return 0;
 881 }
 882
 883 static int
 884 render_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
 885                                 u32 offset, u32 len)
 886 {
 887         struct drm_device *dev = ring->dev;
 888         int ret;
 889
 890         if (IS_I830(dev) || IS_845G(dev)) {
 891                 ret = intel_ring_begin(ring, 4);
 892                 if (ret)
 893                         return ret;
 894
 895                 intel_ring_emit(ring, MI_BATCH_BUFFER);
 896                 intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
 897                 intel_ring_emit(ring, offset + len - 8);
 898                 intel_ring_emit(ring, 0);
 899         } else {
 900                 ret = intel_ring_begin(ring, 2);
 901                 if (ret)
 902                         return ret;
 903
 904                 if (INTEL_INFO(dev)->gen >= 4) {
 905                         intel_ring_emit(ring,
 906                                         MI_BATCH_BUFFER_START | (2 << 6) |
 907                                         MI_BATCH_NON_SECURE_I965);
 908                         intel_ring_emit(ring, offset);
 909                 } else {
 910                         intel_ring_emit(ring,
 911                                         MI_BATCH_BUFFER_START | (2 << 6));
 912                         intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
 913                 }
 914         }
 915         intel_ring_advance(ring);
 916
 917         return 0;
 918 }
 919
 920 static void cleanup_status_page(struct intel_ring_buffer *ring)
 921 {
 922         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 923         struct drm_i915_gem_object *obj;
 924
 925         obj = ring->status_page.obj;
 926         if (obj == NULL)
 927                 return;
 928
 929         kunmap(obj->pages[0]);
 930         i915_gem_object_unpin(obj);
 931         drm_gem_object_unreference(&obj->base);
 932         ring->status_page.obj = NULL;
 933
 934         memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
 935 }
 936
 937 static int init_status_page(struct intel_ring_buffer *ring)
 938 {
 939         struct drm_device *dev = ring->dev;
 940         drm_i915_private_t *dev_priv = dev->dev_private;
 941         struct drm_i915_gem_object *obj;
 942         int ret;
 943
 944         obj = i915_gem_alloc_object(dev, 4096);
 945         if (obj == NULL) {
 946                 DRM_ERROR("Failed to allocate status page\n");
 947                 ret = -ENOMEM;
 948                 goto err;
 949         }
 950
 951         i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
 952
 953         ret = i915_gem_object_pin(obj, 4096, true);
 954         if (ret != 0) {
 955                 goto err_unref;
 956         }
 957
 958         ring->status_page.gfx_addr = obj->gtt_offset;
 959         ring->status_page.page_addr = kmap(obj->pages[0]);
 960         if (ring->status_page.page_addr == NULL) {
 961                 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
 962                 goto err_unpin;
 963         }
 964         ring->status_page.obj = obj;
 965         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
 966
 967         intel_ring_setup_status_page(ring);
 968         DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
 969                         ring->name, ring->status_page.gfx_addr);
 970
 971         return 0;
 972
 973 err_unpin:
 974         i915_gem_object_unpin(obj);
 975 err_unref:
 976         drm_gem_object_unreference(&obj->base);
 977 err:
 978         return ret;
 979 }
 980
 981 int intel_init_ring_buffer(struct drm_device *dev,
 982                            struct intel_ring_buffer *ring)
 983 {
 984         struct drm_i915_gem_object *obj;
 985         int ret;
 986
 987         ring->dev = dev;
 988         INIT_LIST_HEAD(&ring->active_list);
 989         INIT_LIST_HEAD(&ring->request_list);
 990         INIT_LIST_HEAD(&ring->gpu_write_list);
 991
 992         init_waitqueue_head(&ring->irq_queue);
 993         spin_lock_init(&ring->irq_lock);
 994         ring->irq_mask = ~0;
 995
 996         if (I915_NEED_GFX_HWS(dev)) {
 997                 ret = init_status_page(ring);
 998                 if (ret)
 999                         return ret;
1000         }
1001
1002         obj = i915_gem_alloc_object(dev, ring->size);
1003         if (obj == NULL) {
1004                 DRM_ERROR("Failed to allocate ringbuffer\n");
1005                 ret = -ENOMEM;
1006                 goto err_hws;
1007         }
1008
1009         ring->obj = obj;
1010
1011         ret = i915_gem_object_pin(obj, PAGE_SIZE, true);
1012         if (ret)
1013                 goto err_unref;
1014
1015         ring->map.size = ring->size;
1016         ring->map.offset = dev->agp->base + obj->gtt_offset;
1017         ring->map.type = 0;
1018         ring->map.flags = 0;
1019         ring->map.mtrr = 0;
1020
1021         drm_core_ioremap_wc(&ring->map, dev);
1022         if (ring->map.handle == NULL) {
1023                 DRM_ERROR("Failed to map ringbuffer.\n");
1024                 ret = -EINVAL;
1025                 goto err_unpin;
1026         }
1027
1028         ring->virtual_start = ring->map.handle;
1029         ret = ring->init(ring);
1030         if (ret)
1031                 goto err_unmap;
1032
1033         /* Workaround an erratum on the i830 which causes a hang if
1034          * the TAIL pointer points to within the last 2 cachelines
1035          * of the buffer.
1036          */
1037         ring->effective_size = ring->size;
1038         if (IS_I830(ring->dev))
1039                 ring->effective_size -= 128;
1040
1041         return 0;
1042
1043 err_unmap:
1044         drm_core_ioremapfree(&ring->map, dev);
1045 err_unpin:
1046         i915_gem_object_unpin(obj);
1047 err_unref:
1048         drm_gem_object_unreference(&obj->base);
1049         ring->obj = NULL;
1050 err_hws:
1051         cleanup_status_page(ring);
1052         return ret;
1053 }
1054
1055 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
1056 {
1057         struct drm_i915_private *dev_priv;
1058         int ret;
1059
1060         if (ring->obj == NULL)
1061                 return;
1062
1063         /* Disable the ring buffer. The ring must be idle at this point */
1064         dev_priv = ring->dev->dev_private;
1065         ret = intel_wait_ring_idle(ring);
1066         if (ret)
1067                 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1068                           ring->name, ret);
1069
1070         I915_WRITE_CTL(ring, 0);
1071
1072         drm_core_ioremapfree(&ring->map, ring->dev);
1073
1074         i915_gem_object_unpin(ring->obj);
1075         drm_gem_object_unreference(&ring->obj->base);
1076         ring->obj = NULL;
1077
1078         if (ring->cleanup)
1079                 ring->cleanup(ring);
1080
1081         cleanup_status_page(ring);
1082 }
1083
1084 static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
1085 {
1086         unsigned int *virt;
1087         int rem = ring->size - ring->tail;
1088
1089         if (ring->space < rem) {
1090                 int ret = intel_wait_ring_buffer(ring, rem);
1091                 if (ret)
1092                         return ret;
1093         }
1094
1095         virt = (unsigned int *)(ring->virtual_start + ring->tail);
1096         rem /= 8;
1097         while (rem--) {
1098                 *virt++ = MI_NOOP;
1099                 *virt++ = MI_NOOP;
1100         }
1101
1102         ring->tail = 0;
1103         ring->space = ring_space(ring);
1104
1105         return 0;
1106 }
1107
1108 int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n)
1109 {
1110         struct drm_device *dev = ring->dev;
1111         struct drm_i915_private *dev_priv = dev->dev_private;
1112         unsigned long end;
1113         u32 head;
1114
1115         /* If the reported head position has wrapped or hasn't advanced,
1116          * fallback to the slow and accurate path.
1117          */
1118         head = intel_read_status_page(ring, 4);
1119         if (head > ring->head) {
1120                 ring->head = head;
1121                 ring->space = ring_space(ring);
1122                 if (ring->space >= n)
1123                         return 0;
1124         }
1125
1126         trace_i915_ring_wait_begin(ring);
1127         end = jiffies + 3 * HZ;
1128         do {
1129                 ring->head = I915_READ_HEAD(ring);
1130                 ring->space = ring_space(ring);
1131                 if (ring->space >= n) {
1132                         trace_i915_ring_wait_end(ring);
1133                         return 0;
1134                 }
1135
1136                 if (dev->primary->master) {
1137                         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1138                         if (master_priv->sarea_priv)
1139                                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1140                 }
1141
1142                 msleep(1);
1143                 if (atomic_read(&dev_priv->mm.wedged))
1144                         return -EAGAIN;
1145         } while (!time_after(jiffies, end));
1146         trace_i915_ring_wait_end(ring);
1147         return -EBUSY;
1148 }
1149
1150 int intel_ring_begin(struct intel_ring_buffer *ring,
1151                      int num_dwords)
1152 {
1153         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1154         int n = 4*num_dwords;
1155         int ret;
1156
1157         if (unlikely(atomic_read(&dev_priv->mm.wedged)))
1158                 return -EIO;
1159
1160         if (unlikely(ring->tail + n > ring->effective_size)) {
1161                 ret = intel_wrap_ring_buffer(ring);
1162                 if (unlikely(ret))
1163                         return ret;
1164         }
1165
1166         if (unlikely(ring->space < n)) {
1167                 ret = intel_wait_ring_buffer(ring, n);
1168                 if (unlikely(ret))
1169                         return ret;
1170         }
1171
1172         ring->space -= n;
1173         return 0;
1174 }
1175
1176 void intel_ring_advance(struct intel_ring_buffer *ring)
1177 {
1178         ring->tail &= ring->size - 1;
1179         ring->write_tail(ring, ring->tail);
1180 }
1181
1182 static const struct intel_ring_buffer render_ring = {
1183         .name                   = "render ring",
1184         .id                     = RING_RENDER,
1185         .mmio_base              = RENDER_RING_BASE,
1186         .size                   = 32 * PAGE_SIZE,
1187         .init                   = init_render_ring,
1188         .write_tail             = ring_write_tail,
1189         .flush                  = render_ring_flush,
1190         .add_request            = render_ring_add_request,
1191         .get_seqno              = ring_get_seqno,
1192         .irq_get                = render_ring_get_irq,
1193         .irq_put                = render_ring_put_irq,
1194         .dispatch_execbuffer    = render_ring_dispatch_execbuffer,
1195         .cleanup                = render_ring_cleanup,
1196         .sync_to                = render_ring_sync_to,
1197         .semaphore_register     = {MI_SEMAPHORE_SYNC_INVALID,
1198                                    MI_SEMAPHORE_SYNC_RV,
1199                                    MI_SEMAPHORE_SYNC_RB},
1200         .signal_mbox            = {GEN6_VRSYNC, GEN6_BRSYNC},
1201 };
1202
1203 /* ring buffer for bit-stream decoder */
1204
1205 static const struct intel_ring_buffer bsd_ring = {
1206         .name                   = "bsd ring",
1207         .id                     = RING_BSD,
1208         .mmio_base              = BSD_RING_BASE,
1209         .size                   = 32 * PAGE_SIZE,
1210         .init                   = init_ring_common,
1211         .write_tail             = ring_write_tail,
1212         .flush                  = bsd_ring_flush,
1213         .add_request            = ring_add_request,
1214         .get_seqno              = ring_get_seqno,
1215         .irq_get                = bsd_ring_get_irq,
1216         .irq_put                = bsd_ring_put_irq,
1217         .dispatch_execbuffer    = ring_dispatch_execbuffer,
1218 };
1219
1220
1221 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
1222                                      u32 value)
1223 {
1224         drm_i915_private_t *dev_priv = ring->dev->dev_private;
1225
1226        /* Every tail move must follow the sequence below */
1227         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1228                 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
1229                 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE);
1230         I915_WRITE(GEN6_BSD_RNCID, 0x0);
1231
1232         if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
1233                 GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR) == 0,
1234                 50))
1235         DRM_ERROR("timed out waiting for IDLE Indicator\n");
1236
1237         I915_WRITE_TAIL(ring, value);
1238         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1239                 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
1240                 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE);
1241 }
1242
1243 static int gen6_ring_flush(struct intel_ring_buffer *ring,
1244                            u32 invalidate, u32 flush)
1245 {
1246         uint32_t cmd;
1247         int ret;
1248
1249         ret = intel_ring_begin(ring, 4);
1250         if (ret)
1251                 return ret;
1252
1253         cmd = MI_FLUSH_DW;
1254         if (invalidate & I915_GEM_GPU_DOMAINS)
1255                 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
1256         intel_ring_emit(ring, cmd);
1257         intel_ring_emit(ring, 0);
1258         intel_ring_emit(ring, 0);
1259         intel_ring_emit(ring, MI_NOOP);
1260         intel_ring_advance(ring);
1261         return 0;
1262 }
1263
1264 static int
1265 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1266                               u32 offset, u32 len)
1267 {
1268         int ret;
1269
1270         ret = intel_ring_begin(ring, 2);
1271         if (ret)
1272                 return ret;
1273
1274         intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965);
1275         /* bit0-7 is the length on GEN6+ */
1276         intel_ring_emit(ring, offset);
1277         intel_ring_advance(ring);
1278
1279         return 0;
1280 }
1281
1282 static bool
1283 gen6_render_ring_get_irq(struct intel_ring_buffer *ring)
1284 {
1285         return gen6_ring_get_irq(ring,
1286                                  GT_USER_INTERRUPT,
1287                                  GEN6_RENDER_USER_INTERRUPT);
1288 }
1289
1290 static void
1291 gen6_render_ring_put_irq(struct intel_ring_buffer *ring)
1292 {
1293         return gen6_ring_put_irq(ring,
1294                                  GT_USER_INTERRUPT,
1295                                  GEN6_RENDER_USER_INTERRUPT);
1296 }
1297
1298 static bool
1299 gen6_bsd_ring_get_irq(struct intel_ring_buffer *ring)
1300 {
1301         return gen6_ring_get_irq(ring,
1302                                  GT_GEN6_BSD_USER_INTERRUPT,
1303                                  GEN6_BSD_USER_INTERRUPT);
1304 }
1305
1306 static void
1307 gen6_bsd_ring_put_irq(struct intel_ring_buffer *ring)
1308 {
1309         return gen6_ring_put_irq(ring,
1310                                  GT_GEN6_BSD_USER_INTERRUPT,
1311                                  GEN6_BSD_USER_INTERRUPT);
1312 }
1313
1314 /* ring buffer for Video Codec for Gen6+ */
1315 static const struct intel_ring_buffer gen6_bsd_ring = {
1316         .name                   = "gen6 bsd ring",
1317         .id                     = RING_BSD,
1318         .mmio_base              = GEN6_BSD_RING_BASE,
1319         .size                   = 32 * PAGE_SIZE,
1320         .init                   = init_ring_common,
1321         .write_tail             = gen6_bsd_ring_write_tail,
1322         .flush                  = gen6_ring_flush,
1323         .add_request            = gen6_add_request,
1324         .get_seqno              = ring_get_seqno,
1325         .irq_get                = gen6_bsd_ring_get_irq,
1326         .irq_put                = gen6_bsd_ring_put_irq,
1327         .dispatch_execbuffer    = gen6_ring_dispatch_execbuffer,
1328         .sync_to                = gen6_bsd_ring_sync_to,
1329         .semaphore_register     = {MI_SEMAPHORE_SYNC_VR,
1330                                    MI_SEMAPHORE_SYNC_INVALID,
1331                                    MI_SEMAPHORE_SYNC_VB},
1332         .signal_mbox            = {GEN6_RVSYNC, GEN6_BVSYNC},
1333 };
1334
1335 /* Blitter support (SandyBridge+) */
1336
1337 static bool
1338 blt_ring_get_irq(struct intel_ring_buffer *ring)
1339 {
1340         return gen6_ring_get_irq(ring,
1341                                  GT_BLT_USER_INTERRUPT,
1342                                  GEN6_BLITTER_USER_INTERRUPT);
1343 }
1344
1345 static void
1346 blt_ring_put_irq(struct intel_ring_buffer *ring)
1347 {
1348         gen6_ring_put_irq(ring,
1349                           GT_BLT_USER_INTERRUPT,
1350                           GEN6_BLITTER_USER_INTERRUPT);
1351 }
1352
1353
1354 /* Workaround for some stepping of SNB,
1355  * each time when BLT engine ring tail moved,
1356  * the first command in the ring to be parsed
1357  * should be MI_BATCH_BUFFER_START
1358  */
1359 #define NEED_BLT_WORKAROUND(dev) \
1360         (IS_GEN6(dev) && (dev->pdev->revision < 8))
1361
1362 static inline struct drm_i915_gem_object *
1363 to_blt_workaround(struct intel_ring_buffer *ring)
1364 {
1365         return ring->private;
1366 }
1367
1368 static int blt_ring_init(struct intel_ring_buffer *ring)
1369 {
1370         if (NEED_BLT_WORKAROUND(ring->dev)) {
1371                 struct drm_i915_gem_object *obj;
1372                 u32 *ptr;
1373                 int ret;
1374
1375                 obj = i915_gem_alloc_object(ring->dev, 4096);
1376                 if (obj == NULL)
1377                         return -ENOMEM;
1378
1379                 ret = i915_gem_object_pin(obj, 4096, true);
1380                 if (ret) {
1381                         drm_gem_object_unreference(&obj->base);
1382                         return ret;
1383                 }
1384
1385                 ptr = kmap(obj->pages[0]);
1386                 *ptr++ = MI_BATCH_BUFFER_END;
1387                 *ptr++ = MI_NOOP;
1388                 kunmap(obj->pages[0]);
1389
1390                 ret = i915_gem_object_set_to_gtt_domain(obj, false);
1391                 if (ret) {
1392                         i915_gem_object_unpin(obj);
1393                         drm_gem_object_unreference(&obj->base);
1394                         return ret;
1395                 }
1396
1397                 ring->private = obj;
1398         }
1399
1400         return init_ring_common(ring);
1401 }
1402
1403 static int blt_ring_begin(struct intel_ring_buffer *ring,
1404                           int num_dwords)
1405 {
1406         if (ring->private) {
1407                 int ret = intel_ring_begin(ring, num_dwords+2);
1408                 if (ret)
1409                         return ret;
1410
1411                 intel_ring_emit(ring, MI_BATCH_BUFFER_START);
1412                 intel_ring_emit(ring, to_blt_workaround(ring)->gtt_offset);
1413
1414                 return 0;
1415         } else
1416                 return intel_ring_begin(ring, 4);
1417 }
1418
1419 static int blt_ring_flush(struct intel_ring_buffer *ring,
1420                           u32 invalidate, u32 flush)
1421 {
1422         uint32_t cmd;
1423         int ret;
1424
1425         ret = blt_ring_begin(ring, 4);
1426         if (ret)
1427                 return ret;
1428
1429         cmd = MI_FLUSH_DW;
1430         if (invalidate & I915_GEM_DOMAIN_RENDER)
1431                 cmd |= MI_INVALIDATE_TLB;
1432         intel_ring_emit(ring, cmd);
1433         intel_ring_emit(ring, 0);
1434         intel_ring_emit(ring, 0);
1435         intel_ring_emit(ring, MI_NOOP);
1436         intel_ring_advance(ring);
1437         return 0;
1438 }
1439
1440 static void blt_ring_cleanup(struct intel_ring_buffer *ring)
1441 {
1442         if (!ring->private)
1443                 return;
1444
1445         i915_gem_object_unpin(ring->private);
1446         drm_gem_object_unreference(ring->private);
1447         ring->private = NULL;
1448 }
1449
1450 static const struct intel_ring_buffer gen6_blt_ring = {
1451         .name                   = "blt ring",
1452         .id                     = RING_BLT,
1453         .mmio_base              = BLT_RING_BASE,
1454         .size                   = 32 * PAGE_SIZE,
1455         .init                   = blt_ring_init,
1456         .write_tail             = ring_write_tail,
1457         .flush                  = blt_ring_flush,
1458         .add_request            = gen6_add_request,
1459         .get_seqno              = ring_get_seqno,
1460         .irq_get                = blt_ring_get_irq,
1461         .irq_put                = blt_ring_put_irq,
1462         .dispatch_execbuffer    = gen6_ring_dispatch_execbuffer,
1463         .cleanup                = blt_ring_cleanup,
1464         .sync_to                = gen6_blt_ring_sync_to,
1465         .semaphore_register     = {MI_SEMAPHORE_SYNC_BR,
1466                                    MI_SEMAPHORE_SYNC_BV,
1467                                    MI_SEMAPHORE_SYNC_INVALID},
1468         .signal_mbox            = {GEN6_RBSYNC, GEN6_VBSYNC},
1469 };
1470
1471 int intel_init_render_ring_buffer(struct drm_device *dev)
1472 {
1473         drm_i915_private_t *dev_priv = dev->dev_private;
1474         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1475
1476         *ring = render_ring;
1477         if (INTEL_INFO(dev)->gen >= 6) {
1478                 ring->add_request = gen6_add_request;
1479                 ring->flush = gen6_render_ring_flush;
1480                 ring->irq_get = gen6_render_ring_get_irq;
1481                 ring->irq_put = gen6_render_ring_put_irq;
1482         } else if (IS_GEN5(dev)) {
1483                 ring->add_request = pc_render_add_request;
1484                 ring->get_seqno = pc_render_get_seqno;
1485         }
1486
1487         if (!I915_NEED_GFX_HWS(dev)) {
1488                 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1489                 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1490         }
1491
1492         return intel_init_ring_buffer(dev, ring);
1493 }
1494
1495 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
1496 {
1497         drm_i915_private_t *dev_priv = dev->dev_private;
1498         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1499
1500         *ring = render_ring;
1501         if (INTEL_INFO(dev)->gen >= 6) {
1502                 ring->add_request = gen6_add_request;
1503                 ring->irq_get = gen6_render_ring_get_irq;
1504                 ring->irq_put = gen6_render_ring_put_irq;
1505         } else if (IS_GEN5(dev)) {
1506                 ring->add_request = pc_render_add_request;
1507                 ring->get_seqno = pc_render_get_seqno;
1508         }
1509
1510         if (!I915_NEED_GFX_HWS(dev))
1511                 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1512
1513         ring->dev = dev;
1514         INIT_LIST_HEAD(&ring->active_list);
1515         INIT_LIST_HEAD(&ring->request_list);
1516         INIT_LIST_HEAD(&ring->gpu_write_list);
1517
1518         ring->size = size;
1519         ring->effective_size = ring->size;
1520         if (IS_I830(ring->dev))
1521                 ring->effective_size -= 128;
1522
1523         ring->map.offset = start;
1524         ring->map.size = size;
1525         ring->map.type = 0;
1526         ring->map.flags = 0;
1527         ring->map.mtrr = 0;
1528
1529         drm_core_ioremap_wc(&ring->map, dev);
1530         if (ring->map.handle == NULL) {
1531                 DRM_ERROR("can not ioremap virtual address for"
1532                           " ring buffer\n");
1533                 return -ENOMEM;
1534         }
1535
1536         ring->virtual_start = (void __force __iomem *)ring->map.handle;
1537         return 0;
1538 }
1539
1540 int intel_init_bsd_ring_buffer(struct drm_device *dev)
1541 {
1542         drm_i915_private_t *dev_priv = dev->dev_private;
1543         struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
1544
1545         if (IS_GEN6(dev) || IS_GEN7(dev))
1546                 *ring = gen6_bsd_ring;
1547         else
1548                 *ring = bsd_ring;
1549
1550         return intel_init_ring_buffer(dev, ring);
1551 }
1552
1553 int intel_init_blt_ring_buffer(struct drm_device *dev)
1554 {
1555         drm_i915_private_t *dev_priv = dev->dev_private;
1556         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
1557
1558         *ring = gen6_blt_ring;
1559
1560         return intel_init_ring_buffer(dev, ring);
1561 }