2 * Copyright © 2008-2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
34 #include "i915_trace.h"
35 #include "intel_drv.h"
38 * 965+ support PIPE_CONTROL commands, which provide finer grained control
39 * over cache flushing.
42 struct drm_i915_gem_object *obj;
43 volatile u32 *cpu_page;
47 static inline int ring_space(struct intel_ring_buffer *ring)
49 int space = (ring->head & HEAD_ADDR) - (ring->tail + 8);
56 gen2_render_ring_flush(struct intel_ring_buffer *ring,
57 u32 invalidate_domains,
64 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
65 cmd |= MI_NO_WRITE_FLUSH;
67 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
70 ret = intel_ring_begin(ring, 2);
74 intel_ring_emit(ring, cmd);
75 intel_ring_emit(ring, MI_NOOP);
76 intel_ring_advance(ring);
82 gen4_render_ring_flush(struct intel_ring_buffer *ring,
83 u32 invalidate_domains,
86 struct drm_device *dev = ring->dev;
93 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
94 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
95 * also flushed at 2d versus 3d pipeline switches.
99 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
100 * MI_READ_FLUSH is set, and is always flushed on 965.
102 * I915_GEM_DOMAIN_COMMAND may not exist?
104 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
105 * invalidated when MI_EXE_FLUSH is set.
107 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
108 * invalidated with every MI_FLUSH.
112 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
113 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
114 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
115 * are flushed at any MI_FLUSH.
118 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
119 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
120 cmd &= ~MI_NO_WRITE_FLUSH;
121 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
124 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
125 (IS_G4X(dev) || IS_GEN5(dev)))
126 cmd |= MI_INVALIDATE_ISP;
128 ret = intel_ring_begin(ring, 2);
132 intel_ring_emit(ring, cmd);
133 intel_ring_emit(ring, MI_NOOP);
134 intel_ring_advance(ring);
140 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
141 * implementing two workarounds on gen6. From section 1.4.7.1
142 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
144 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
145 * produced by non-pipelined state commands), software needs to first
146 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
149 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
150 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
152 * And the workaround for these two requires this workaround first:
154 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
155 * BEFORE the pipe-control with a post-sync op and no write-cache
158 * And this last workaround is tricky because of the requirements on
159 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
162 * "1 of the following must also be set:
163 * - Render Target Cache Flush Enable ([12] of DW1)
164 * - Depth Cache Flush Enable ([0] of DW1)
165 * - Stall at Pixel Scoreboard ([1] of DW1)
166 * - Depth Stall ([13] of DW1)
167 * - Post-Sync Operation ([13] of DW1)
168 * - Notify Enable ([8] of DW1)"
170 * The cache flushes require the workaround flush that triggered this
171 * one, so we can't use it. Depth stall would trigger the same.
172 * Post-sync nonzero is what triggered this second workaround, so we
173 * can't use that one either. Notify enable is IRQs, which aren't
174 * really our business. That leaves only stall at scoreboard.
177 intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring)
179 struct pipe_control *pc = ring->private;
180 u32 scratch_addr = pc->gtt_offset + 128;
184 ret = intel_ring_begin(ring, 6);
188 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
189 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
190 PIPE_CONTROL_STALL_AT_SCOREBOARD);
191 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
192 intel_ring_emit(ring, 0); /* low dword */
193 intel_ring_emit(ring, 0); /* high dword */
194 intel_ring_emit(ring, MI_NOOP);
195 intel_ring_advance(ring);
197 ret = intel_ring_begin(ring, 6);
201 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
202 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
203 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
204 intel_ring_emit(ring, 0);
205 intel_ring_emit(ring, 0);
206 intel_ring_emit(ring, MI_NOOP);
207 intel_ring_advance(ring);
213 gen6_render_ring_flush(struct intel_ring_buffer *ring,
214 u32 invalidate_domains, u32 flush_domains)
217 struct pipe_control *pc = ring->private;
218 u32 scratch_addr = pc->gtt_offset + 128;
221 /* Force SNB workarounds for PIPE_CONTROL flushes */
222 intel_emit_post_sync_nonzero_flush(ring);
224 /* Just flush everything. Experiments have shown that reducing the
225 * number of bits based on the write domains has little performance
228 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
229 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
230 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
231 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
232 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
233 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
234 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
236 ret = intel_ring_begin(ring, 6);
240 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
241 intel_ring_emit(ring, flags);
242 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
243 intel_ring_emit(ring, 0); /* lower dword */
244 intel_ring_emit(ring, 0); /* uppwer dword */
245 intel_ring_emit(ring, MI_NOOP);
246 intel_ring_advance(ring);
251 static void ring_write_tail(struct intel_ring_buffer *ring,
254 drm_i915_private_t *dev_priv = ring->dev->dev_private;
255 I915_WRITE_TAIL(ring, value);
258 u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
260 drm_i915_private_t *dev_priv = ring->dev->dev_private;
261 u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
262 RING_ACTHD(ring->mmio_base) : ACTHD;
264 return I915_READ(acthd_reg);
267 static int init_ring_common(struct intel_ring_buffer *ring)
269 struct drm_device *dev = ring->dev;
270 drm_i915_private_t *dev_priv = dev->dev_private;
271 struct drm_i915_gem_object *obj = ring->obj;
275 if (HAS_FORCE_WAKE(dev))
276 gen6_gt_force_wake_get(dev_priv);
278 /* Stop the ring if it's running. */
279 I915_WRITE_CTL(ring, 0);
280 I915_WRITE_HEAD(ring, 0);
281 ring->write_tail(ring, 0);
283 /* Initialize the ring. */
284 I915_WRITE_START(ring, obj->gtt_offset);
285 head = I915_READ_HEAD(ring) & HEAD_ADDR;
287 /* G45 ring initialization fails to reset head to zero */
289 DRM_DEBUG_KMS("%s head not reset to zero "
290 "ctl %08x head %08x tail %08x start %08x\n",
293 I915_READ_HEAD(ring),
294 I915_READ_TAIL(ring),
295 I915_READ_START(ring));
297 I915_WRITE_HEAD(ring, 0);
299 if (I915_READ_HEAD(ring) & HEAD_ADDR) {
300 DRM_ERROR("failed to set %s head to zero "
301 "ctl %08x head %08x tail %08x start %08x\n",
304 I915_READ_HEAD(ring),
305 I915_READ_TAIL(ring),
306 I915_READ_START(ring));
311 ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
314 /* If the head is still not zero, the ring is dead */
315 if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
316 I915_READ_START(ring) == obj->gtt_offset &&
317 (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
318 DRM_ERROR("%s initialization failed "
319 "ctl %08x head %08x tail %08x start %08x\n",
322 I915_READ_HEAD(ring),
323 I915_READ_TAIL(ring),
324 I915_READ_START(ring));
329 if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
330 i915_kernel_lost_context(ring->dev);
332 ring->head = I915_READ_HEAD(ring);
333 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
334 ring->space = ring_space(ring);
335 ring->last_retired_head = -1;
339 if (HAS_FORCE_WAKE(dev))
340 gen6_gt_force_wake_put(dev_priv);
346 init_pipe_control(struct intel_ring_buffer *ring)
348 struct pipe_control *pc;
349 struct drm_i915_gem_object *obj;
355 pc = kmalloc(sizeof(*pc), GFP_KERNEL);
359 obj = i915_gem_alloc_object(ring->dev, 4096);
361 DRM_ERROR("Failed to allocate seqno page\n");
366 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
368 ret = i915_gem_object_pin(obj, 4096, true);
372 pc->gtt_offset = obj->gtt_offset;
373 pc->cpu_page = kmap(obj->pages[0]);
374 if (pc->cpu_page == NULL)
382 i915_gem_object_unpin(obj);
384 drm_gem_object_unreference(&obj->base);
391 cleanup_pipe_control(struct intel_ring_buffer *ring)
393 struct pipe_control *pc = ring->private;
394 struct drm_i915_gem_object *obj;
400 kunmap(obj->pages[0]);
401 i915_gem_object_unpin(obj);
402 drm_gem_object_unreference(&obj->base);
405 ring->private = NULL;
408 static int init_render_ring(struct intel_ring_buffer *ring)
410 struct drm_device *dev = ring->dev;
411 struct drm_i915_private *dev_priv = dev->dev_private;
412 int ret = init_ring_common(ring);
414 if (INTEL_INFO(dev)->gen > 3) {
415 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
417 I915_WRITE(GFX_MODE_GEN7,
418 _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
419 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
422 if (INTEL_INFO(dev)->gen >= 5) {
423 ret = init_pipe_control(ring);
429 /* From the Sandybridge PRM, volume 1 part 3, page 24:
430 * "If this bit is set, STCunit will have LRA as replacement
431 * policy. [...] This bit must be reset. LRA replacement
432 * policy is not supported."
434 I915_WRITE(CACHE_MODE_0,
435 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
438 if (INTEL_INFO(dev)->gen >= 6)
439 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
444 static void render_ring_cleanup(struct intel_ring_buffer *ring)
449 cleanup_pipe_control(ring);
453 update_mboxes(struct intel_ring_buffer *ring,
457 intel_ring_emit(ring, MI_SEMAPHORE_MBOX |
458 MI_SEMAPHORE_GLOBAL_GTT |
459 MI_SEMAPHORE_REGISTER |
460 MI_SEMAPHORE_UPDATE);
461 intel_ring_emit(ring, seqno);
462 intel_ring_emit(ring, mmio_offset);
466 * gen6_add_request - Update the semaphore mailbox registers
468 * @ring - ring that is adding a request
469 * @seqno - return seqno stuck into the ring
471 * Update the mailbox registers in the *other* rings with the current seqno.
472 * This acts like a signal in the canonical semaphore.
475 gen6_add_request(struct intel_ring_buffer *ring,
482 ret = intel_ring_begin(ring, 10);
486 mbox1_reg = ring->signal_mbox[0];
487 mbox2_reg = ring->signal_mbox[1];
489 *seqno = i915_gem_next_request_seqno(ring);
491 update_mboxes(ring, *seqno, mbox1_reg);
492 update_mboxes(ring, *seqno, mbox2_reg);
493 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
494 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
495 intel_ring_emit(ring, *seqno);
496 intel_ring_emit(ring, MI_USER_INTERRUPT);
497 intel_ring_advance(ring);
503 * intel_ring_sync - sync the waiter to the signaller on seqno
505 * @waiter - ring that is waiting
506 * @signaller - ring which has, or will signal
507 * @seqno - seqno which the waiter will block on
510 gen6_ring_sync(struct intel_ring_buffer *waiter,
511 struct intel_ring_buffer *signaller,
515 u32 dw1 = MI_SEMAPHORE_MBOX |
516 MI_SEMAPHORE_COMPARE |
517 MI_SEMAPHORE_REGISTER;
519 /* Throughout all of the GEM code, seqno passed implies our current
520 * seqno is >= the last seqno executed. However for hardware the
521 * comparison is strictly greater than.
525 WARN_ON(signaller->semaphore_register[waiter->id] ==
526 MI_SEMAPHORE_SYNC_INVALID);
528 ret = intel_ring_begin(waiter, 4);
532 intel_ring_emit(waiter,
533 dw1 | signaller->semaphore_register[waiter->id]);
534 intel_ring_emit(waiter, seqno);
535 intel_ring_emit(waiter, 0);
536 intel_ring_emit(waiter, MI_NOOP);
537 intel_ring_advance(waiter);
542 #define PIPE_CONTROL_FLUSH(ring__, addr__) \
544 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
545 PIPE_CONTROL_DEPTH_STALL); \
546 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
547 intel_ring_emit(ring__, 0); \
548 intel_ring_emit(ring__, 0); \
552 pc_render_add_request(struct intel_ring_buffer *ring,
555 u32 seqno = i915_gem_next_request_seqno(ring);
556 struct pipe_control *pc = ring->private;
557 u32 scratch_addr = pc->gtt_offset + 128;
560 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
561 * incoherent with writes to memory, i.e. completely fubar,
562 * so we need to use PIPE_NOTIFY instead.
564 * However, we also need to workaround the qword write
565 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
566 * memory before requesting an interrupt.
568 ret = intel_ring_begin(ring, 32);
572 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
573 PIPE_CONTROL_WRITE_FLUSH |
574 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
575 intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
576 intel_ring_emit(ring, seqno);
577 intel_ring_emit(ring, 0);
578 PIPE_CONTROL_FLUSH(ring, scratch_addr);
579 scratch_addr += 128; /* write to separate cachelines */
580 PIPE_CONTROL_FLUSH(ring, scratch_addr);
582 PIPE_CONTROL_FLUSH(ring, scratch_addr);
584 PIPE_CONTROL_FLUSH(ring, scratch_addr);
586 PIPE_CONTROL_FLUSH(ring, scratch_addr);
588 PIPE_CONTROL_FLUSH(ring, scratch_addr);
590 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
591 PIPE_CONTROL_WRITE_FLUSH |
592 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
593 PIPE_CONTROL_NOTIFY);
594 intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
595 intel_ring_emit(ring, seqno);
596 intel_ring_emit(ring, 0);
597 intel_ring_advance(ring);
604 gen6_ring_get_seqno(struct intel_ring_buffer *ring)
606 struct drm_device *dev = ring->dev;
608 /* Workaround to force correct ordering between irq and seqno writes on
609 * ivb (and maybe also on snb) by reading from a CS register (like
610 * ACTHD) before reading the status page. */
611 if (IS_GEN6(dev) || IS_GEN7(dev))
612 intel_ring_get_active_head(ring);
613 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
617 ring_get_seqno(struct intel_ring_buffer *ring)
619 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
623 pc_render_get_seqno(struct intel_ring_buffer *ring)
625 struct pipe_control *pc = ring->private;
626 return pc->cpu_page[0];
630 gen5_ring_get_irq(struct intel_ring_buffer *ring)
632 struct drm_device *dev = ring->dev;
633 drm_i915_private_t *dev_priv = dev->dev_private;
636 if (!dev->irq_enabled)
639 spin_lock_irqsave(&dev_priv->irq_lock, flags);
640 if (ring->irq_refcount++ == 0) {
641 dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
642 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
645 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
651 gen5_ring_put_irq(struct intel_ring_buffer *ring)
653 struct drm_device *dev = ring->dev;
654 drm_i915_private_t *dev_priv = dev->dev_private;
657 spin_lock_irqsave(&dev_priv->irq_lock, flags);
658 if (--ring->irq_refcount == 0) {
659 dev_priv->gt_irq_mask |= ring->irq_enable_mask;
660 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
663 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
667 i9xx_ring_get_irq(struct intel_ring_buffer *ring)
669 struct drm_device *dev = ring->dev;
670 drm_i915_private_t *dev_priv = dev->dev_private;
673 if (!dev->irq_enabled)
676 spin_lock_irqsave(&dev_priv->irq_lock, flags);
677 if (ring->irq_refcount++ == 0) {
678 dev_priv->irq_mask &= ~ring->irq_enable_mask;
679 I915_WRITE(IMR, dev_priv->irq_mask);
682 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
688 i9xx_ring_put_irq(struct intel_ring_buffer *ring)
690 struct drm_device *dev = ring->dev;
691 drm_i915_private_t *dev_priv = dev->dev_private;
694 spin_lock_irqsave(&dev_priv->irq_lock, flags);
695 if (--ring->irq_refcount == 0) {
696 dev_priv->irq_mask |= ring->irq_enable_mask;
697 I915_WRITE(IMR, dev_priv->irq_mask);
700 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
704 i8xx_ring_get_irq(struct intel_ring_buffer *ring)
706 struct drm_device *dev = ring->dev;
707 drm_i915_private_t *dev_priv = dev->dev_private;
710 if (!dev->irq_enabled)
713 spin_lock_irqsave(&dev_priv->irq_lock, flags);
714 if (ring->irq_refcount++ == 0) {
715 dev_priv->irq_mask &= ~ring->irq_enable_mask;
716 I915_WRITE16(IMR, dev_priv->irq_mask);
719 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
725 i8xx_ring_put_irq(struct intel_ring_buffer *ring)
727 struct drm_device *dev = ring->dev;
728 drm_i915_private_t *dev_priv = dev->dev_private;
731 spin_lock_irqsave(&dev_priv->irq_lock, flags);
732 if (--ring->irq_refcount == 0) {
733 dev_priv->irq_mask |= ring->irq_enable_mask;
734 I915_WRITE16(IMR, dev_priv->irq_mask);
737 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
740 void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
742 struct drm_device *dev = ring->dev;
743 drm_i915_private_t *dev_priv = ring->dev->dev_private;
746 /* The ring status page addresses are no longer next to the rest of
747 * the ring registers as of gen7.
752 mmio = RENDER_HWS_PGA_GEN7;
755 mmio = BLT_HWS_PGA_GEN7;
758 mmio = BSD_HWS_PGA_GEN7;
761 } else if (IS_GEN6(ring->dev)) {
762 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
764 mmio = RING_HWS_PGA(ring->mmio_base);
767 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
772 bsd_ring_flush(struct intel_ring_buffer *ring,
773 u32 invalidate_domains,
778 ret = intel_ring_begin(ring, 2);
782 intel_ring_emit(ring, MI_FLUSH);
783 intel_ring_emit(ring, MI_NOOP);
784 intel_ring_advance(ring);
789 i9xx_add_request(struct intel_ring_buffer *ring,
795 ret = intel_ring_begin(ring, 4);
799 seqno = i915_gem_next_request_seqno(ring);
801 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
802 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
803 intel_ring_emit(ring, seqno);
804 intel_ring_emit(ring, MI_USER_INTERRUPT);
805 intel_ring_advance(ring);
812 gen6_ring_get_irq(struct intel_ring_buffer *ring)
814 struct drm_device *dev = ring->dev;
815 drm_i915_private_t *dev_priv = dev->dev_private;
818 if (!dev->irq_enabled)
821 /* It looks like we need to prevent the gt from suspending while waiting
822 * for an notifiy irq, otherwise irqs seem to get lost on at least the
823 * blt/bsd rings on ivb. */
824 gen6_gt_force_wake_get(dev_priv);
826 spin_lock_irqsave(&dev_priv->irq_lock, flags);
827 if (ring->irq_refcount++ == 0) {
828 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
829 dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
830 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
833 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
839 gen6_ring_put_irq(struct intel_ring_buffer *ring)
841 struct drm_device *dev = ring->dev;
842 drm_i915_private_t *dev_priv = dev->dev_private;
845 spin_lock_irqsave(&dev_priv->irq_lock, flags);
846 if (--ring->irq_refcount == 0) {
847 I915_WRITE_IMR(ring, ~0);
848 dev_priv->gt_irq_mask |= ring->irq_enable_mask;
849 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
852 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
854 gen6_gt_force_wake_put(dev_priv);
858 i965_dispatch_execbuffer(struct intel_ring_buffer *ring, u32 offset, u32 length)
862 ret = intel_ring_begin(ring, 2);
866 intel_ring_emit(ring,
867 MI_BATCH_BUFFER_START |
869 MI_BATCH_NON_SECURE_I965);
870 intel_ring_emit(ring, offset);
871 intel_ring_advance(ring);
877 i830_dispatch_execbuffer(struct intel_ring_buffer *ring,
882 ret = intel_ring_begin(ring, 4);
886 intel_ring_emit(ring, MI_BATCH_BUFFER);
887 intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
888 intel_ring_emit(ring, offset + len - 8);
889 intel_ring_emit(ring, 0);
890 intel_ring_advance(ring);
896 i915_dispatch_execbuffer(struct intel_ring_buffer *ring,
901 ret = intel_ring_begin(ring, 2);
905 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
906 intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
907 intel_ring_advance(ring);
912 static void cleanup_status_page(struct intel_ring_buffer *ring)
914 struct drm_i915_gem_object *obj;
916 obj = ring->status_page.obj;
920 kunmap(obj->pages[0]);
921 i915_gem_object_unpin(obj);
922 drm_gem_object_unreference(&obj->base);
923 ring->status_page.obj = NULL;
926 static int init_status_page(struct intel_ring_buffer *ring)
928 struct drm_device *dev = ring->dev;
929 struct drm_i915_gem_object *obj;
932 obj = i915_gem_alloc_object(dev, 4096);
934 DRM_ERROR("Failed to allocate status page\n");
939 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
941 ret = i915_gem_object_pin(obj, 4096, true);
946 ring->status_page.gfx_addr = obj->gtt_offset;
947 ring->status_page.page_addr = kmap(obj->pages[0]);
948 if (ring->status_page.page_addr == NULL) {
951 ring->status_page.obj = obj;
952 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
954 intel_ring_setup_status_page(ring);
955 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
956 ring->name, ring->status_page.gfx_addr);
961 i915_gem_object_unpin(obj);
963 drm_gem_object_unreference(&obj->base);
968 static int intel_init_ring_buffer(struct drm_device *dev,
969 struct intel_ring_buffer *ring)
971 struct drm_i915_gem_object *obj;
975 INIT_LIST_HEAD(&ring->active_list);
976 INIT_LIST_HEAD(&ring->request_list);
977 INIT_LIST_HEAD(&ring->gpu_write_list);
978 ring->size = 32 * PAGE_SIZE;
980 init_waitqueue_head(&ring->irq_queue);
982 if (I915_NEED_GFX_HWS(dev)) {
983 ret = init_status_page(ring);
988 obj = i915_gem_alloc_object(dev, ring->size);
990 DRM_ERROR("Failed to allocate ringbuffer\n");
997 ret = i915_gem_object_pin(obj, PAGE_SIZE, true);
1001 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1005 ring->virtual_start = ioremap_wc(dev->agp->base + obj->gtt_offset,
1007 if (ring->virtual_start == NULL) {
1008 DRM_ERROR("Failed to map ringbuffer.\n");
1013 ret = ring->init(ring);
1017 /* Workaround an erratum on the i830 which causes a hang if
1018 * the TAIL pointer points to within the last 2 cachelines
1021 ring->effective_size = ring->size;
1022 if (IS_I830(ring->dev) || IS_845G(ring->dev))
1023 ring->effective_size -= 128;
1028 iounmap(ring->virtual_start);
1030 i915_gem_object_unpin(obj);
1032 drm_gem_object_unreference(&obj->base);
1035 cleanup_status_page(ring);
1039 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
1041 struct drm_i915_private *dev_priv;
1044 if (ring->obj == NULL)
1047 /* Disable the ring buffer. The ring must be idle at this point */
1048 dev_priv = ring->dev->dev_private;
1049 ret = intel_wait_ring_idle(ring);
1051 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1054 I915_WRITE_CTL(ring, 0);
1056 iounmap(ring->virtual_start);
1058 i915_gem_object_unpin(ring->obj);
1059 drm_gem_object_unreference(&ring->obj->base);
1063 ring->cleanup(ring);
1065 cleanup_status_page(ring);
1068 static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
1070 uint32_t __iomem *virt;
1071 int rem = ring->size - ring->tail;
1073 if (ring->space < rem) {
1074 int ret = intel_wait_ring_buffer(ring, rem);
1079 virt = ring->virtual_start + ring->tail;
1082 iowrite32(MI_NOOP, virt++);
1085 ring->space = ring_space(ring);
1090 static int intel_ring_wait_seqno(struct intel_ring_buffer *ring, u32 seqno)
1092 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1093 bool was_interruptible;
1096 /* XXX As we have not yet audited all the paths to check that
1097 * they are ready for ERESTARTSYS from intel_ring_begin, do not
1098 * allow us to be interruptible by a signal.
1100 was_interruptible = dev_priv->mm.interruptible;
1101 dev_priv->mm.interruptible = false;
1103 ret = i915_wait_request(ring, seqno);
1105 dev_priv->mm.interruptible = was_interruptible;
1107 i915_gem_retire_requests_ring(ring);
1112 static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n)
1114 struct drm_i915_gem_request *request;
1118 i915_gem_retire_requests_ring(ring);
1120 if (ring->last_retired_head != -1) {
1121 ring->head = ring->last_retired_head;
1122 ring->last_retired_head = -1;
1123 ring->space = ring_space(ring);
1124 if (ring->space >= n)
1128 list_for_each_entry(request, &ring->request_list, list) {
1131 if (request->tail == -1)
1134 space = request->tail - (ring->tail + 8);
1136 space += ring->size;
1138 seqno = request->seqno;
1142 /* Consume this request in case we need more space than
1143 * is available and so need to prevent a race between
1144 * updating last_retired_head and direct reads of
1145 * I915_RING_HEAD. It also provides a nice sanity check.
1153 ret = intel_ring_wait_seqno(ring, seqno);
1157 if (WARN_ON(ring->last_retired_head == -1))
1160 ring->head = ring->last_retired_head;
1161 ring->last_retired_head = -1;
1162 ring->space = ring_space(ring);
1163 if (WARN_ON(ring->space < n))
1169 int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n)
1171 struct drm_device *dev = ring->dev;
1172 struct drm_i915_private *dev_priv = dev->dev_private;
1176 ret = intel_ring_wait_request(ring, n);
1180 trace_i915_ring_wait_begin(ring);
1181 /* With GEM the hangcheck timer should kick us out of the loop,
1182 * leaving it early runs the risk of corrupting GEM state (due
1183 * to running on almost untested codepaths). But on resume
1184 * timers don't work yet, so prevent a complete hang in that
1185 * case by choosing an insanely large timeout. */
1186 end = jiffies + 60 * HZ;
1189 ring->head = I915_READ_HEAD(ring);
1190 ring->space = ring_space(ring);
1191 if (ring->space >= n) {
1192 trace_i915_ring_wait_end(ring);
1196 if (dev->primary->master) {
1197 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1198 if (master_priv->sarea_priv)
1199 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1203 if (atomic_read(&dev_priv->mm.wedged))
1205 } while (!time_after(jiffies, end));
1206 trace_i915_ring_wait_end(ring);
1210 int intel_ring_begin(struct intel_ring_buffer *ring,
1213 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1214 int n = 4*num_dwords;
1217 if (unlikely(atomic_read(&dev_priv->mm.wedged)))
1220 if (unlikely(ring->tail + n > ring->effective_size)) {
1221 ret = intel_wrap_ring_buffer(ring);
1226 if (unlikely(ring->space < n)) {
1227 ret = intel_wait_ring_buffer(ring, n);
1236 void intel_ring_advance(struct intel_ring_buffer *ring)
1238 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1240 ring->tail &= ring->size - 1;
1241 if (dev_priv->stop_rings & intel_ring_flag(ring))
1243 ring->write_tail(ring, ring->tail);
1247 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
1250 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1252 /* Every tail move must follow the sequence below */
1253 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1254 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
1255 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE);
1256 I915_WRITE(GEN6_BSD_RNCID, 0x0);
1258 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
1259 GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR) == 0,
1261 DRM_ERROR("timed out waiting for IDLE Indicator\n");
1263 I915_WRITE_TAIL(ring, value);
1264 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1265 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
1266 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE);
1269 static int gen6_ring_flush(struct intel_ring_buffer *ring,
1270 u32 invalidate, u32 flush)
1275 ret = intel_ring_begin(ring, 4);
1280 if (invalidate & I915_GEM_GPU_DOMAINS)
1281 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
1282 intel_ring_emit(ring, cmd);
1283 intel_ring_emit(ring, 0);
1284 intel_ring_emit(ring, 0);
1285 intel_ring_emit(ring, MI_NOOP);
1286 intel_ring_advance(ring);
1291 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1292 u32 offset, u32 len)
1296 ret = intel_ring_begin(ring, 2);
1300 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965);
1301 /* bit0-7 is the length on GEN6+ */
1302 intel_ring_emit(ring, offset);
1303 intel_ring_advance(ring);
1308 /* Blitter support (SandyBridge+) */
1310 static int blt_ring_flush(struct intel_ring_buffer *ring,
1311 u32 invalidate, u32 flush)
1316 ret = intel_ring_begin(ring, 4);
1321 if (invalidate & I915_GEM_DOMAIN_RENDER)
1322 cmd |= MI_INVALIDATE_TLB;
1323 intel_ring_emit(ring, cmd);
1324 intel_ring_emit(ring, 0);
1325 intel_ring_emit(ring, 0);
1326 intel_ring_emit(ring, MI_NOOP);
1327 intel_ring_advance(ring);
1331 int intel_init_render_ring_buffer(struct drm_device *dev)
1333 drm_i915_private_t *dev_priv = dev->dev_private;
1334 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1336 ring->name = "render ring";
1338 ring->mmio_base = RENDER_RING_BASE;
1340 if (INTEL_INFO(dev)->gen >= 6) {
1341 ring->add_request = gen6_add_request;
1342 ring->flush = gen6_render_ring_flush;
1343 ring->irq_get = gen6_ring_get_irq;
1344 ring->irq_put = gen6_ring_put_irq;
1345 ring->irq_enable_mask = GT_USER_INTERRUPT;
1346 ring->get_seqno = gen6_ring_get_seqno;
1347 ring->sync_to = gen6_ring_sync;
1348 ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_INVALID;
1349 ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_RV;
1350 ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_RB;
1351 ring->signal_mbox[0] = GEN6_VRSYNC;
1352 ring->signal_mbox[1] = GEN6_BRSYNC;
1353 } else if (IS_GEN5(dev)) {
1354 ring->add_request = pc_render_add_request;
1355 ring->flush = gen4_render_ring_flush;
1356 ring->get_seqno = pc_render_get_seqno;
1357 ring->irq_get = gen5_ring_get_irq;
1358 ring->irq_put = gen5_ring_put_irq;
1359 ring->irq_enable_mask = GT_USER_INTERRUPT | GT_PIPE_NOTIFY;
1361 ring->add_request = i9xx_add_request;
1362 if (INTEL_INFO(dev)->gen < 4)
1363 ring->flush = gen2_render_ring_flush;
1365 ring->flush = gen4_render_ring_flush;
1366 ring->get_seqno = ring_get_seqno;
1368 ring->irq_get = i8xx_ring_get_irq;
1369 ring->irq_put = i8xx_ring_put_irq;
1371 ring->irq_get = i9xx_ring_get_irq;
1372 ring->irq_put = i9xx_ring_put_irq;
1374 ring->irq_enable_mask = I915_USER_INTERRUPT;
1376 ring->write_tail = ring_write_tail;
1377 if (INTEL_INFO(dev)->gen >= 6)
1378 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1379 else if (INTEL_INFO(dev)->gen >= 4)
1380 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1381 else if (IS_I830(dev) || IS_845G(dev))
1382 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1384 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1385 ring->init = init_render_ring;
1386 ring->cleanup = render_ring_cleanup;
1389 if (!I915_NEED_GFX_HWS(dev)) {
1390 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1391 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1394 return intel_init_ring_buffer(dev, ring);
1397 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
1399 drm_i915_private_t *dev_priv = dev->dev_private;
1400 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1402 ring->name = "render ring";
1404 ring->mmio_base = RENDER_RING_BASE;
1406 if (INTEL_INFO(dev)->gen >= 6) {
1407 /* non-kms not supported on gen6+ */
1411 /* Note: gem is not supported on gen5/ilk without kms (the corresponding
1412 * gem_init ioctl returns with -ENODEV). Hence we do not need to set up
1413 * the special gen5 functions. */
1414 ring->add_request = i9xx_add_request;
1415 if (INTEL_INFO(dev)->gen < 4)
1416 ring->flush = gen2_render_ring_flush;
1418 ring->flush = gen4_render_ring_flush;
1419 ring->get_seqno = ring_get_seqno;
1421 ring->irq_get = i8xx_ring_get_irq;
1422 ring->irq_put = i8xx_ring_put_irq;
1424 ring->irq_get = i9xx_ring_get_irq;
1425 ring->irq_put = i9xx_ring_put_irq;
1427 ring->irq_enable_mask = I915_USER_INTERRUPT;
1428 ring->write_tail = ring_write_tail;
1429 if (INTEL_INFO(dev)->gen >= 4)
1430 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1431 else if (IS_I830(dev) || IS_845G(dev))
1432 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1434 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1435 ring->init = init_render_ring;
1436 ring->cleanup = render_ring_cleanup;
1438 if (!I915_NEED_GFX_HWS(dev))
1439 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1442 INIT_LIST_HEAD(&ring->active_list);
1443 INIT_LIST_HEAD(&ring->request_list);
1444 INIT_LIST_HEAD(&ring->gpu_write_list);
1447 ring->effective_size = ring->size;
1448 if (IS_I830(ring->dev))
1449 ring->effective_size -= 128;
1451 ring->virtual_start = ioremap_wc(start, size);
1452 if (ring->virtual_start == NULL) {
1453 DRM_ERROR("can not ioremap virtual address for"
1461 int intel_init_bsd_ring_buffer(struct drm_device *dev)
1463 drm_i915_private_t *dev_priv = dev->dev_private;
1464 struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
1466 ring->name = "bsd ring";
1469 ring->write_tail = ring_write_tail;
1470 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1471 ring->mmio_base = GEN6_BSD_RING_BASE;
1472 /* gen6 bsd needs a special wa for tail updates */
1474 ring->write_tail = gen6_bsd_ring_write_tail;
1475 ring->flush = gen6_ring_flush;
1476 ring->add_request = gen6_add_request;
1477 ring->get_seqno = gen6_ring_get_seqno;
1478 ring->irq_enable_mask = GEN6_BSD_USER_INTERRUPT;
1479 ring->irq_get = gen6_ring_get_irq;
1480 ring->irq_put = gen6_ring_put_irq;
1481 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1482 ring->sync_to = gen6_ring_sync;
1483 ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_VR;
1484 ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_INVALID;
1485 ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_VB;
1486 ring->signal_mbox[0] = GEN6_RVSYNC;
1487 ring->signal_mbox[1] = GEN6_BVSYNC;
1489 ring->mmio_base = BSD_RING_BASE;
1490 ring->flush = bsd_ring_flush;
1491 ring->add_request = i9xx_add_request;
1492 ring->get_seqno = ring_get_seqno;
1494 ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
1495 ring->irq_get = gen5_ring_get_irq;
1496 ring->irq_put = gen5_ring_put_irq;
1498 ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
1499 ring->irq_get = i9xx_ring_get_irq;
1500 ring->irq_put = i9xx_ring_put_irq;
1502 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1504 ring->init = init_ring_common;
1507 return intel_init_ring_buffer(dev, ring);
1510 int intel_init_blt_ring_buffer(struct drm_device *dev)
1512 drm_i915_private_t *dev_priv = dev->dev_private;
1513 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
1515 ring->name = "blitter ring";
1518 ring->mmio_base = BLT_RING_BASE;
1519 ring->write_tail = ring_write_tail;
1520 ring->flush = blt_ring_flush;
1521 ring->add_request = gen6_add_request;
1522 ring->get_seqno = gen6_ring_get_seqno;
1523 ring->irq_enable_mask = GEN6_BLITTER_USER_INTERRUPT;
1524 ring->irq_get = gen6_ring_get_irq;
1525 ring->irq_put = gen6_ring_put_irq;
1526 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1527 ring->sync_to = gen6_ring_sync;
1528 ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_BR;
1529 ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_BV;
1530 ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_INVALID;
1531 ring->signal_mbox[0] = GEN6_RBSYNC;
1532 ring->signal_mbox[1] = GEN6_VBSYNC;
1533 ring->init = init_ring_common;
1535 return intel_init_ring_buffer(dev, ring);