Pileus Git - ~andy/linux/blob - drivers/gpu/drm/i915/intel_ringbuffer.c

   1 /*
   2  * Copyright © 2008-2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Zou Nan hai <nanhai.zou@intel.com>
  26  *    Xiang Hai hao<haihao.xiang@intel.com>
  27  *
  28  */
  29
  30 #include <drm/drmP.h>
  31 #include "i915_drv.h"
  32 #include <drm/i915_drm.h>
  33 #include "i915_trace.h"
  34 #include "intel_drv.h"
  35
  36 static inline int ring_space(struct intel_ring_buffer *ring)
  37 {
  38         int space = (ring->head & HEAD_ADDR) - (ring->tail + I915_RING_FREE_SPACE);
  39         if (space < 0)
  40                 space += ring->size;
  41         return space;
  42 }
  43
  44 void __intel_ring_advance(struct intel_ring_buffer *ring)
  45 {
  46         struct drm_i915_private *dev_priv = ring->dev->dev_private;
  47
  48         ring->tail &= ring->size - 1;
  49         if (dev_priv->gpu_error.stop_rings & intel_ring_flag(ring))
  50                 return;
  51         ring->write_tail(ring, ring->tail);
  52 }
  53
  54 static int
  55 gen2_render_ring_flush(struct intel_ring_buffer *ring,
  56                        u32      invalidate_domains,
  57                        u32      flush_domains)
  58 {
  59         u32 cmd;
  60         int ret;
  61
  62         cmd = MI_FLUSH;
  63         if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
  64                 cmd |= MI_NO_WRITE_FLUSH;
  65
  66         if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
  67                 cmd |= MI_READ_FLUSH;
  68
  69         ret = intel_ring_begin(ring, 2);
  70         if (ret)
  71                 return ret;
  72
  73         intel_ring_emit(ring, cmd);
  74         intel_ring_emit(ring, MI_NOOP);
  75         intel_ring_advance(ring);
  76
  77         return 0;
  78 }
  79
  80 static int
  81 gen4_render_ring_flush(struct intel_ring_buffer *ring,
  82                        u32      invalidate_domains,
  83                        u32      flush_domains)
  84 {
  85         struct drm_device *dev = ring->dev;
  86         u32 cmd;
  87         int ret;
  88
  89         /*
  90          * read/write caches:
  91          *
  92          * I915_GEM_DOMAIN_RENDER is always invalidated, but is
  93          * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
  94          * also flushed at 2d versus 3d pipeline switches.
  95          *
  96          * read-only caches:
  97          *
  98          * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
  99          * MI_READ_FLUSH is set, and is always flushed on 965.
 100          *
 101          * I915_GEM_DOMAIN_COMMAND may not exist?
 102          *
 103          * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
 104          * invalidated when MI_EXE_FLUSH is set.
 105          *
 106          * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
 107          * invalidated with every MI_FLUSH.
 108          *
 109          * TLBs:
 110          *
 111          * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
 112          * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
 113          * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
 114          * are flushed at any MI_FLUSH.
 115          */
 116
 117         cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
 118         if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
 119                 cmd &= ~MI_NO_WRITE_FLUSH;
 120         if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
 121                 cmd |= MI_EXE_FLUSH;
 122
 123         if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
 124             (IS_G4X(dev) || IS_GEN5(dev)))
 125                 cmd |= MI_INVALIDATE_ISP;
 126
 127         ret = intel_ring_begin(ring, 2);
 128         if (ret)
 129                 return ret;
 130
 131         intel_ring_emit(ring, cmd);
 132         intel_ring_emit(ring, MI_NOOP);
 133         intel_ring_advance(ring);
 134
 135         return 0;
 136 }
 137
 138 /**
 139  * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
 140  * implementing two workarounds on gen6.  From section 1.4.7.1
 141  * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
 142  *
 143  * [DevSNB-C+{W/A}] Before any depth stall flush (including those
 144  * produced by non-pipelined state commands), software needs to first
 145  * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
 146  * 0.
 147  *
 148  * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
 149  * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
 150  *
 151  * And the workaround for these two requires this workaround first:
 152  *
 153  * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
 154  * BEFORE the pipe-control with a post-sync op and no write-cache
 155  * flushes.
 156  *
 157  * And this last workaround is tricky because of the requirements on
 158  * that bit.  From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
 159  * volume 2 part 1:
 160  *
 161  *     "1 of the following must also be set:
 162  *      - Render Target Cache Flush Enable ([12] of DW1)
 163  *      - Depth Cache Flush Enable ([0] of DW1)
 164  *      - Stall at Pixel Scoreboard ([1] of DW1)
 165  *      - Depth Stall ([13] of DW1)
 166  *      - Post-Sync Operation ([13] of DW1)
 167  *      - Notify Enable ([8] of DW1)"
 168  *
 169  * The cache flushes require the workaround flush that triggered this
 170  * one, so we can't use it.  Depth stall would trigger the same.
 171  * Post-sync nonzero is what triggered this second workaround, so we
 172  * can't use that one either.  Notify enable is IRQs, which aren't
 173  * really our business.  That leaves only stall at scoreboard.
 174  */
 175 static int
 176 intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring)
 177 {
 178         u32 scratch_addr = ring->scratch.gtt_offset + 128;
 179         int ret;
 180
 181
 182         ret = intel_ring_begin(ring, 6);
 183         if (ret)
 184                 return ret;
 185
 186         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 187         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 188                         PIPE_CONTROL_STALL_AT_SCOREBOARD);
 189         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 190         intel_ring_emit(ring, 0); /* low dword */
 191         intel_ring_emit(ring, 0); /* high dword */
 192         intel_ring_emit(ring, MI_NOOP);
 193         intel_ring_advance(ring);
 194
 195         ret = intel_ring_begin(ring, 6);
 196         if (ret)
 197                 return ret;
 198
 199         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 200         intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
 201         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 202         intel_ring_emit(ring, 0);
 203         intel_ring_emit(ring, 0);
 204         intel_ring_emit(ring, MI_NOOP);
 205         intel_ring_advance(ring);
 206
 207         return 0;
 208 }
 209
 210 static int
 211 gen6_render_ring_flush(struct intel_ring_buffer *ring,
 212                          u32 invalidate_domains, u32 flush_domains)
 213 {
 214         u32 flags = 0;
 215         u32 scratch_addr = ring->scratch.gtt_offset + 128;
 216         int ret;
 217
 218         /* Force SNB workarounds for PIPE_CONTROL flushes */
 219         ret = intel_emit_post_sync_nonzero_flush(ring);
 220         if (ret)
 221                 return ret;
 222
 223         /* Just flush everything.  Experiments have shown that reducing the
 224          * number of bits based on the write domains has little performance
 225          * impact.
 226          */
 227         if (flush_domains) {
 228                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 229                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 230                 /*
 231                  * Ensure that any following seqno writes only happen
 232                  * when the render cache is indeed flushed.
 233                  */
 234                 flags |= PIPE_CONTROL_CS_STALL;
 235         }
 236         if (invalidate_domains) {
 237                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 238                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 239                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 240                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 241                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 242                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 243                 /*
 244                  * TLB invalidate requires a post-sync write.
 245                  */
 246                 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
 247         }
 248
 249         ret = intel_ring_begin(ring, 4);
 250         if (ret)
 251                 return ret;
 252
 253         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 254         intel_ring_emit(ring, flags);
 255         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
 256         intel_ring_emit(ring, 0);
 257         intel_ring_advance(ring);
 258
 259         return 0;
 260 }
 261
 262 static int
 263 gen7_render_ring_cs_stall_wa(struct intel_ring_buffer *ring)
 264 {
 265         int ret;
 266
 267         ret = intel_ring_begin(ring, 4);
 268         if (ret)
 269                 return ret;
 270
 271         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 272         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 273                               PIPE_CONTROL_STALL_AT_SCOREBOARD);
 274         intel_ring_emit(ring, 0);
 275         intel_ring_emit(ring, 0);
 276         intel_ring_advance(ring);
 277
 278         return 0;
 279 }
 280
 281 static int gen7_ring_fbc_flush(struct intel_ring_buffer *ring, u32 value)
 282 {
 283         int ret;
 284
 285         if (!ring->fbc_dirty)
 286                 return 0;
 287
 288         ret = intel_ring_begin(ring, 6);
 289         if (ret)
 290                 return ret;
 291         /* WaFbcNukeOn3DBlt:ivb/hsw */
 292         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
 293         intel_ring_emit(ring, MSG_FBC_REND_STATE);
 294         intel_ring_emit(ring, value);
 295         intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | MI_SRM_LRM_GLOBAL_GTT);
 296         intel_ring_emit(ring, MSG_FBC_REND_STATE);
 297         intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
 298         intel_ring_advance(ring);
 299
 300         ring->fbc_dirty = false;
 301         return 0;
 302 }
 303
 304 static int
 305 gen7_render_ring_flush(struct intel_ring_buffer *ring,
 306                        u32 invalidate_domains, u32 flush_domains)
 307 {
 308         u32 flags = 0;
 309         u32 scratch_addr = ring->scratch.gtt_offset + 128;
 310         int ret;
 311
 312         /*
 313          * Ensure that any following seqno writes only happen when the render
 314          * cache is indeed flushed.
 315          *
 316          * Workaround: 4th PIPE_CONTROL command (except the ones with only
 317          * read-cache invalidate bits set) must have the CS_STALL bit set. We
 318          * don't try to be clever and just set it unconditionally.
 319          */
 320         flags |= PIPE_CONTROL_CS_STALL;
 321
 322         /* Just flush everything.  Experiments have shown that reducing the
 323          * number of bits based on the write domains has little performance
 324          * impact.
 325          */
 326         if (flush_domains) {
 327                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 328                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 329         }
 330         if (invalidate_domains) {
 331                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 332                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 333                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 334                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 335                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 336                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 337                 /*
 338                  * TLB invalidate requires a post-sync write.
 339                  */
 340                 flags |= PIPE_CONTROL_QW_WRITE;
 341                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 342
 343                 /* Workaround: we must issue a pipe_control with CS-stall bit
 344                  * set before a pipe_control command that has the state cache
 345                  * invalidate bit set. */
 346                 gen7_render_ring_cs_stall_wa(ring);
 347         }
 348
 349         ret = intel_ring_begin(ring, 4);
 350         if (ret)
 351                 return ret;
 352
 353         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 354         intel_ring_emit(ring, flags);
 355         intel_ring_emit(ring, scratch_addr);
 356         intel_ring_emit(ring, 0);
 357         intel_ring_advance(ring);
 358
 359         if (!invalidate_domains && flush_domains)
 360                 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
 361
 362         return 0;
 363 }
 364
 365 static int
 366 gen8_render_ring_flush(struct intel_ring_buffer *ring,
 367                        u32 invalidate_domains, u32 flush_domains)
 368 {
 369         u32 flags = 0;
 370         u32 scratch_addr = ring->scratch.gtt_offset + 128;
 371         int ret;
 372
 373         flags |= PIPE_CONTROL_CS_STALL;
 374
 375         if (flush_domains) {
 376                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 377                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 378         }
 379         if (invalidate_domains) {
 380                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 381                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 382                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 383                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 384                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 385                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 386                 flags |= PIPE_CONTROL_QW_WRITE;
 387                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 388         }
 389
 390         ret = intel_ring_begin(ring, 6);
 391         if (ret)
 392                 return ret;
 393
 394         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
 395         intel_ring_emit(ring, flags);
 396         intel_ring_emit(ring, scratch_addr);
 397         intel_ring_emit(ring, 0);
 398         intel_ring_emit(ring, 0);
 399         intel_ring_emit(ring, 0);
 400         intel_ring_advance(ring);
 401
 402         return 0;
 403
 404 }
 405
 406 static void ring_write_tail(struct intel_ring_buffer *ring,
 407                             u32 value)
 408 {
 409         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 410         I915_WRITE_TAIL(ring, value);
 411 }
 412
 413 u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
 414 {
 415         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 416         u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
 417                         RING_ACTHD(ring->mmio_base) : ACTHD;
 418
 419         return I915_READ(acthd_reg);
 420 }
 421
 422 static void ring_setup_phys_status_page(struct intel_ring_buffer *ring)
 423 {
 424         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 425         u32 addr;
 426
 427         addr = dev_priv->status_page_dmah->busaddr;
 428         if (INTEL_INFO(ring->dev)->gen >= 4)
 429                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
 430         I915_WRITE(HWS_PGA, addr);
 431 }
 432
 433 static int init_ring_common(struct intel_ring_buffer *ring)
 434 {
 435         struct drm_device *dev = ring->dev;
 436         drm_i915_private_t *dev_priv = dev->dev_private;
 437         struct drm_i915_gem_object *obj = ring->obj;
 438         int ret = 0;
 439         u32 head;
 440
 441         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
 442
 443         if (I915_NEED_GFX_HWS(dev))
 444                 intel_ring_setup_status_page(ring);
 445         else
 446                 ring_setup_phys_status_page(ring);
 447
 448         /* Stop the ring if it's running. */
 449         I915_WRITE_CTL(ring, 0);
 450         I915_WRITE_HEAD(ring, 0);
 451         ring->write_tail(ring, 0);
 452
 453         head = I915_READ_HEAD(ring) & HEAD_ADDR;
 454
 455         /* G45 ring initialization fails to reset head to zero */
 456         if (head != 0) {
 457                 DRM_DEBUG_KMS("%s head not reset to zero "
 458                               "ctl %08x head %08x tail %08x start %08x\n",
 459                               ring->name,
 460                               I915_READ_CTL(ring),
 461                               I915_READ_HEAD(ring),
 462                               I915_READ_TAIL(ring),
 463                               I915_READ_START(ring));
 464
 465                 I915_WRITE_HEAD(ring, 0);
 466
 467                 if (I915_READ_HEAD(ring) & HEAD_ADDR) {
 468                         DRM_ERROR("failed to set %s head to zero "
 469                                   "ctl %08x head %08x tail %08x start %08x\n",
 470                                   ring->name,
 471                                   I915_READ_CTL(ring),
 472                                   I915_READ_HEAD(ring),
 473                                   I915_READ_TAIL(ring),
 474                                   I915_READ_START(ring));
 475                 }
 476         }
 477
 478         /* Initialize the ring. This must happen _after_ we've cleared the ring
 479          * registers with the above sequence (the readback of the HEAD registers
 480          * also enforces ordering), otherwise the hw might lose the new ring
 481          * register values. */
 482         I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj));
 483         I915_WRITE_CTL(ring,
 484                         ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
 485                         | RING_VALID);
 486
 487         /* If the head is still not zero, the ring is dead */
 488         if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
 489                      I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) &&
 490                      (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
 491                 DRM_ERROR("%s initialization failed "
 492                                 "ctl %08x head %08x tail %08x start %08x\n",
 493                                 ring->name,
 494                                 I915_READ_CTL(ring),
 495                                 I915_READ_HEAD(ring),
 496                                 I915_READ_TAIL(ring),
 497                                 I915_READ_START(ring));
 498                 ret = -EIO;
 499                 goto out;
 500         }
 501
 502         if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
 503                 i915_kernel_lost_context(ring->dev);
 504         else {
 505                 ring->head = I915_READ_HEAD(ring);
 506                 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 507                 ring->space = ring_space(ring);
 508                 ring->last_retired_head = -1;
 509         }
 510
 511         memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
 512
 513 out:
 514         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
 515
 516         return ret;
 517 }
 518
 519 static int
 520 init_pipe_control(struct intel_ring_buffer *ring)
 521 {
 522         int ret;
 523
 524         if (ring->scratch.obj)
 525                 return 0;
 526
 527         ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096);
 528         if (ring->scratch.obj == NULL) {
 529                 DRM_ERROR("Failed to allocate seqno page\n");
 530                 ret = -ENOMEM;
 531                 goto err;
 532         }
 533
 534         i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC);
 535
 536         ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, true, false);
 537         if (ret)
 538                 goto err_unref;
 539
 540         ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj);
 541         ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl));
 542         if (ring->scratch.cpu_page == NULL) {
 543                 ret = -ENOMEM;
 544                 goto err_unpin;
 545         }
 546
 547         DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
 548                          ring->name, ring->scratch.gtt_offset);
 549         return 0;
 550
 551 err_unpin:
 552         i915_gem_object_unpin(ring->scratch.obj);
 553 err_unref:
 554         drm_gem_object_unreference(&ring->scratch.obj->base);
 555 err:
 556         return ret;
 557 }
 558
 559 static int init_render_ring(struct intel_ring_buffer *ring)
 560 {
 561         struct drm_device *dev = ring->dev;
 562         struct drm_i915_private *dev_priv = dev->dev_private;
 563         int ret = init_ring_common(ring);
 564
 565         if (INTEL_INFO(dev)->gen > 3)
 566                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
 567
 568         /* We need to disable the AsyncFlip performance optimisations in order
 569          * to use MI_WAIT_FOR_EVENT within the CS. It should already be
 570          * programmed to '1' on all products.
 571          *
 572          * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
 573          */
 574         if (INTEL_INFO(dev)->gen >= 6)
 575                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
 576
 577         /* Required for the hardware to program scanline values for waiting */
 578         if (INTEL_INFO(dev)->gen == 6)
 579                 I915_WRITE(GFX_MODE,
 580                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_ALWAYS));
 581
 582         if (IS_GEN7(dev))
 583                 I915_WRITE(GFX_MODE_GEN7,
 584                            _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
 585                            _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
 586
 587         if (INTEL_INFO(dev)->gen >= 5) {
 588                 ret = init_pipe_control(ring);
 589                 if (ret)
 590                         return ret;
 591         }
 592
 593         if (IS_GEN6(dev)) {
 594                 /* From the Sandybridge PRM, volume 1 part 3, page 24:
 595                  * "If this bit is set, STCunit will have LRA as replacement
 596                  *  policy. [...] This bit must be reset.  LRA replacement
 597                  *  policy is not supported."
 598                  */
 599                 I915_WRITE(CACHE_MODE_0,
 600                            _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
 601
 602                 /* This is not explicitly set for GEN6, so read the register.
 603                  * see intel_ring_mi_set_context() for why we care.
 604                  * TODO: consider explicitly setting the bit for GEN5
 605                  */
 606                 ring->itlb_before_ctx_switch =
 607                         !!(I915_READ(GFX_MODE) & GFX_TLB_INVALIDATE_ALWAYS);
 608         }
 609
 610         if (INTEL_INFO(dev)->gen >= 6)
 611                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
 612
 613         if (HAS_L3_DPF(dev))
 614                 I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
 615
 616         return ret;
 617 }
 618
 619 static void render_ring_cleanup(struct intel_ring_buffer *ring)
 620 {
 621         struct drm_device *dev = ring->dev;
 622
 623         if (ring->scratch.obj == NULL)
 624                 return;
 625
 626         if (INTEL_INFO(dev)->gen >= 5) {
 627                 kunmap(sg_page(ring->scratch.obj->pages->sgl));
 628                 i915_gem_object_unpin(ring->scratch.obj);
 629         }
 630
 631         drm_gem_object_unreference(&ring->scratch.obj->base);
 632         ring->scratch.obj = NULL;
 633 }
 634
 635 static void
 636 update_mboxes(struct intel_ring_buffer *ring,
 637               u32 mmio_offset)
 638 {
 639 /* NB: In order to be able to do semaphore MBOX updates for varying number
 640  * of rings, it's easiest if we round up each individual update to a
 641  * multiple of 2 (since ring updates must always be a multiple of 2)
 642  * even though the actual update only requires 3 dwords.
 643  */
 644 #define MBOX_UPDATE_DWORDS 4
 645         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
 646         intel_ring_emit(ring, mmio_offset);
 647         intel_ring_emit(ring, ring->outstanding_lazy_seqno);
 648         intel_ring_emit(ring, MI_NOOP);
 649 }
 650
 651 /**
 652  * gen6_add_request - Update the semaphore mailbox registers
 653  *
 654  * @ring - ring that is adding a request
 655  * @seqno - return seqno stuck into the ring
 656  *
 657  * Update the mailbox registers in the *other* rings with the current seqno.
 658  * This acts like a signal in the canonical semaphore.
 659  */
 660 static int
 661 gen6_add_request(struct intel_ring_buffer *ring)
 662 {
 663         struct drm_device *dev = ring->dev;
 664         struct drm_i915_private *dev_priv = dev->dev_private;
 665         struct intel_ring_buffer *useless;
 666         int i, ret, num_dwords = 4;
 667
 668         if (i915_semaphore_is_enabled(dev))
 669                 num_dwords += ((I915_NUM_RINGS-1) * MBOX_UPDATE_DWORDS);
 670 #undef MBOX_UPDATE_DWORDS
 671
 672         ret = intel_ring_begin(ring, num_dwords);
 673         if (ret)
 674                 return ret;
 675
 676         for_each_ring(useless, dev_priv, i) {
 677                 u32 mbox_reg = ring->signal_mbox[i];
 678                 if (mbox_reg != GEN6_NOSYNC)
 679                         update_mboxes(ring, mbox_reg);
 680         }
 681
 682         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
 683         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 684         intel_ring_emit(ring, ring->outstanding_lazy_seqno);
 685         intel_ring_emit(ring, MI_USER_INTERRUPT);
 686         __intel_ring_advance(ring);
 687
 688         return 0;
 689 }
 690
 691 static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
 692                                               u32 seqno)
 693 {
 694         struct drm_i915_private *dev_priv = dev->dev_private;
 695         return dev_priv->last_seqno < seqno;
 696 }
 697
 698 /**
 699  * intel_ring_sync - sync the waiter to the signaller on seqno
 700  *
 701  * @waiter - ring that is waiting
 702  * @signaller - ring which has, or will signal
 703  * @seqno - seqno which the waiter will block on
 704  */
 705 static int
 706 gen6_ring_sync(struct intel_ring_buffer *waiter,
 707                struct intel_ring_buffer *signaller,
 708                u32 seqno)
 709 {
 710         int ret;
 711         u32 dw1 = MI_SEMAPHORE_MBOX |
 712                   MI_SEMAPHORE_COMPARE |
 713                   MI_SEMAPHORE_REGISTER;
 714
 715         /* Throughout all of the GEM code, seqno passed implies our current
 716          * seqno is >= the last seqno executed. However for hardware the
 717          * comparison is strictly greater than.
 718          */
 719         seqno -= 1;
 720
 721         WARN_ON(signaller->semaphore_register[waiter->id] ==
 722                 MI_SEMAPHORE_SYNC_INVALID);
 723
 724         ret = intel_ring_begin(waiter, 4);
 725         if (ret)
 726                 return ret;
 727
 728         /* If seqno wrap happened, omit the wait with no-ops */
 729         if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
 730                 intel_ring_emit(waiter,
 731                                 dw1 |
 732                                 signaller->semaphore_register[waiter->id]);
 733                 intel_ring_emit(waiter, seqno);
 734                 intel_ring_emit(waiter, 0);
 735                 intel_ring_emit(waiter, MI_NOOP);
 736         } else {
 737                 intel_ring_emit(waiter, MI_NOOP);
 738                 intel_ring_emit(waiter, MI_NOOP);
 739                 intel_ring_emit(waiter, MI_NOOP);
 740                 intel_ring_emit(waiter, MI_NOOP);
 741         }
 742         intel_ring_advance(waiter);
 743
 744         return 0;
 745 }
 746
 747 #define PIPE_CONTROL_FLUSH(ring__, addr__)                                      \
 748 do {                                                                    \
 749         intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |                \
 750                  PIPE_CONTROL_DEPTH_STALL);                             \
 751         intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT);                    \
 752         intel_ring_emit(ring__, 0);                                                     \
 753         intel_ring_emit(ring__, 0);                                                     \
 754 } while (0)
 755
 756 static int
 757 pc_render_add_request(struct intel_ring_buffer *ring)
 758 {
 759         u32 scratch_addr = ring->scratch.gtt_offset + 128;
 760         int ret;
 761
 762         /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
 763          * incoherent with writes to memory, i.e. completely fubar,
 764          * so we need to use PIPE_NOTIFY instead.
 765          *
 766          * However, we also need to workaround the qword write
 767          * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
 768          * memory before requesting an interrupt.
 769          */
 770         ret = intel_ring_begin(ring, 32);
 771         if (ret)
 772                 return ret;
 773
 774         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
 775                         PIPE_CONTROL_WRITE_FLUSH |
 776                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
 777         intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
 778         intel_ring_emit(ring, ring->outstanding_lazy_seqno);
 779         intel_ring_emit(ring, 0);
 780         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 781         scratch_addr += 128; /* write to separate cachelines */
 782         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 783         scratch_addr += 128;
 784         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 785         scratch_addr += 128;
 786         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 787         scratch_addr += 128;
 788         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 789         scratch_addr += 128;
 790         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 791
 792         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
 793                         PIPE_CONTROL_WRITE_FLUSH |
 794                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
 795                         PIPE_CONTROL_NOTIFY);
 796         intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
 797         intel_ring_emit(ring, ring->outstanding_lazy_seqno);
 798         intel_ring_emit(ring, 0);
 799         __intel_ring_advance(ring);
 800
 801         return 0;
 802 }
 803
 804 static u32
 805 gen6_ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
 806 {
 807         /* Workaround to force correct ordering between irq and seqno writes on
 808          * ivb (and maybe also on snb) by reading from a CS register (like
 809          * ACTHD) before reading the status page. */
 810         if (!lazy_coherency)
 811                 intel_ring_get_active_head(ring);
 812         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
 813 }
 814
 815 static u32
 816 ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
 817 {
 818         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
 819 }
 820
 821 static void
 822 ring_set_seqno(struct intel_ring_buffer *ring, u32 seqno)
 823 {
 824         intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
 825 }
 826
 827 static u32
 828 pc_render_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
 829 {
 830         return ring->scratch.cpu_page[0];
 831 }
 832
 833 static void
 834 pc_render_set_seqno(struct intel_ring_buffer *ring, u32 seqno)
 835 {
 836         ring->scratch.cpu_page[0] = seqno;
 837 }
 838
 839 static bool
 840 gen5_ring_get_irq(struct intel_ring_buffer *ring)
 841 {
 842         struct drm_device *dev = ring->dev;
 843         drm_i915_private_t *dev_priv = dev->dev_private;
 844         unsigned long flags;
 845
 846         if (!dev->irq_enabled)
 847                 return false;
 848
 849         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 850         if (ring->irq_refcount++ == 0)
 851                 ilk_enable_gt_irq(dev_priv, ring->irq_enable_mask);
 852         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 853
 854         return true;
 855 }
 856
 857 static void
 858 gen5_ring_put_irq(struct intel_ring_buffer *ring)
 859 {
 860         struct drm_device *dev = ring->dev;
 861         drm_i915_private_t *dev_priv = dev->dev_private;
 862         unsigned long flags;
 863
 864         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 865         if (--ring->irq_refcount == 0)
 866                 ilk_disable_gt_irq(dev_priv, ring->irq_enable_mask);
 867         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 868 }
 869
 870 static bool
 871 i9xx_ring_get_irq(struct intel_ring_buffer *ring)
 872 {
 873         struct drm_device *dev = ring->dev;
 874         drm_i915_private_t *dev_priv = dev->dev_private;
 875         unsigned long flags;
 876
 877         if (!dev->irq_enabled)
 878                 return false;
 879
 880         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 881         if (ring->irq_refcount++ == 0) {
 882                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
 883                 I915_WRITE(IMR, dev_priv->irq_mask);
 884                 POSTING_READ(IMR);
 885         }
 886         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 887
 888         return true;
 889 }
 890
 891 static void
 892 i9xx_ring_put_irq(struct intel_ring_buffer *ring)
 893 {
 894         struct drm_device *dev = ring->dev;
 895         drm_i915_private_t *dev_priv = dev->dev_private;
 896         unsigned long flags;
 897
 898         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 899         if (--ring->irq_refcount == 0) {
 900                 dev_priv->irq_mask |= ring->irq_enable_mask;
 901                 I915_WRITE(IMR, dev_priv->irq_mask);
 902                 POSTING_READ(IMR);
 903         }
 904         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 905 }
 906
 907 static bool
 908 i8xx_ring_get_irq(struct intel_ring_buffer *ring)
 909 {
 910         struct drm_device *dev = ring->dev;
 911         drm_i915_private_t *dev_priv = dev->dev_private;
 912         unsigned long flags;
 913
 914         if (!dev->irq_enabled)
 915                 return false;
 916
 917         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 918         if (ring->irq_refcount++ == 0) {
 919                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
 920                 I915_WRITE16(IMR, dev_priv->irq_mask);
 921                 POSTING_READ16(IMR);
 922         }
 923         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 924
 925         return true;
 926 }
 927
 928 static void
 929 i8xx_ring_put_irq(struct intel_ring_buffer *ring)
 930 {
 931         struct drm_device *dev = ring->dev;
 932         drm_i915_private_t *dev_priv = dev->dev_private;
 933         unsigned long flags;
 934
 935         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 936         if (--ring->irq_refcount == 0) {
 937                 dev_priv->irq_mask |= ring->irq_enable_mask;
 938                 I915_WRITE16(IMR, dev_priv->irq_mask);
 939                 POSTING_READ16(IMR);
 940         }
 941         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 942 }
 943
 944 void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
 945 {
 946         struct drm_device *dev = ring->dev;
 947         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 948         u32 mmio = 0;
 949
 950         /* The ring status page addresses are no longer next to the rest of
 951          * the ring registers as of gen7.
 952          */
 953         if (IS_GEN7(dev)) {
 954                 switch (ring->id) {
 955                 case RCS:
 956                         mmio = RENDER_HWS_PGA_GEN7;
 957                         break;
 958                 case BCS:
 959                         mmio = BLT_HWS_PGA_GEN7;
 960                         break;
 961                 case VCS:
 962                         mmio = BSD_HWS_PGA_GEN7;
 963                         break;
 964                 case VECS:
 965                         mmio = VEBOX_HWS_PGA_GEN7;
 966                         break;
 967                 }
 968         } else if (IS_GEN6(ring->dev)) {
 969                 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
 970         } else {
 971                 /* XXX: gen8 returns to sanity */
 972                 mmio = RING_HWS_PGA(ring->mmio_base);
 973         }
 974
 975         I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
 976         POSTING_READ(mmio);
 977
 978         /* Flush the TLB for this page */
 979         if (INTEL_INFO(dev)->gen >= 6) {
 980                 u32 reg = RING_INSTPM(ring->mmio_base);
 981                 I915_WRITE(reg,
 982                            _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
 983                                               INSTPM_SYNC_FLUSH));
 984                 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
 985                              1000))
 986                         DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
 987                                   ring->name);
 988         }
 989 }
 990
 991 static int
 992 bsd_ring_flush(struct intel_ring_buffer *ring,
 993                u32     invalidate_domains,
 994                u32     flush_domains)
 995 {
 996         int ret;
 997
 998         ret = intel_ring_begin(ring, 2);
 999         if (ret)
1000                 return ret;
1001
1002         intel_ring_emit(ring, MI_FLUSH);
1003         intel_ring_emit(ring, MI_NOOP);
1004         intel_ring_advance(ring);
1005         return 0;
1006 }
1007
1008 static int
1009 i9xx_add_request(struct intel_ring_buffer *ring)
1010 {
1011         int ret;
1012
1013         ret = intel_ring_begin(ring, 4);
1014         if (ret)
1015                 return ret;
1016
1017         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1018         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1019         intel_ring_emit(ring, ring->outstanding_lazy_seqno);
1020         intel_ring_emit(ring, MI_USER_INTERRUPT);
1021         __intel_ring_advance(ring);
1022
1023         return 0;
1024 }
1025
1026 static bool
1027 gen6_ring_get_irq(struct intel_ring_buffer *ring)
1028 {
1029         struct drm_device *dev = ring->dev;
1030         drm_i915_private_t *dev_priv = dev->dev_private;
1031         unsigned long flags;
1032
1033         if (!dev->irq_enabled)
1034                return false;
1035
1036         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1037         if (ring->irq_refcount++ == 0) {
1038                 if (HAS_L3_DPF(dev) && ring->id == RCS)
1039                         I915_WRITE_IMR(ring,
1040                                        ~(ring->irq_enable_mask |
1041                                          GT_PARITY_ERROR(dev)));
1042                 else
1043                         I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1044                 ilk_enable_gt_irq(dev_priv, ring->irq_enable_mask);
1045         }
1046         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1047
1048         return true;
1049 }
1050
1051 static void
1052 gen6_ring_put_irq(struct intel_ring_buffer *ring)
1053 {
1054         struct drm_device *dev = ring->dev;
1055         drm_i915_private_t *dev_priv = dev->dev_private;
1056         unsigned long flags;
1057
1058         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1059         if (--ring->irq_refcount == 0) {
1060                 if (HAS_L3_DPF(dev) && ring->id == RCS)
1061                         I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev));
1062                 else
1063                         I915_WRITE_IMR(ring, ~0);
1064                 ilk_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1065         }
1066         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1067 }
1068
1069 static bool
1070 hsw_vebox_get_irq(struct intel_ring_buffer *ring)
1071 {
1072         struct drm_device *dev = ring->dev;
1073         struct drm_i915_private *dev_priv = dev->dev_private;
1074         unsigned long flags;
1075
1076         if (!dev->irq_enabled)
1077                 return false;
1078
1079         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1080         if (ring->irq_refcount++ == 0) {
1081                 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1082                 snb_enable_pm_irq(dev_priv, ring->irq_enable_mask);
1083         }
1084         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1085
1086         return true;
1087 }
1088
1089 static void
1090 hsw_vebox_put_irq(struct intel_ring_buffer *ring)
1091 {
1092         struct drm_device *dev = ring->dev;
1093         struct drm_i915_private *dev_priv = dev->dev_private;
1094         unsigned long flags;
1095
1096         if (!dev->irq_enabled)
1097                 return;
1098
1099         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1100         if (--ring->irq_refcount == 0) {
1101                 I915_WRITE_IMR(ring, ~0);
1102                 snb_disable_pm_irq(dev_priv, ring->irq_enable_mask);
1103         }
1104         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1105 }
1106
1107 static bool
1108 gen8_ring_get_irq(struct intel_ring_buffer *ring)
1109 {
1110         struct drm_device *dev = ring->dev;
1111         struct drm_i915_private *dev_priv = dev->dev_private;
1112         unsigned long flags;
1113
1114         if (!dev->irq_enabled)
1115                 return false;
1116
1117         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1118         if (ring->irq_refcount++ == 0) {
1119                 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1120                         I915_WRITE_IMR(ring,
1121                                        ~(ring->irq_enable_mask |
1122                                          GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1123                 } else {
1124                         I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1125                 }
1126                 POSTING_READ(RING_IMR(ring->mmio_base));
1127         }
1128         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1129
1130         return true;
1131 }
1132
1133 static void
1134 gen8_ring_put_irq(struct intel_ring_buffer *ring)
1135 {
1136         struct drm_device *dev = ring->dev;
1137         struct drm_i915_private *dev_priv = dev->dev_private;
1138         unsigned long flags;
1139
1140         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1141         if (--ring->irq_refcount == 0) {
1142                 if (HAS_L3_DPF(dev) && ring->id == RCS) {
1143                         I915_WRITE_IMR(ring,
1144                                        ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1145                 } else {
1146                         I915_WRITE_IMR(ring, ~0);
1147                 }
1148                 POSTING_READ(RING_IMR(ring->mmio_base));
1149         }
1150         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1151 }
1152
1153 static int
1154 i965_dispatch_execbuffer(struct intel_ring_buffer *ring,
1155                          u32 offset, u32 length,
1156                          unsigned flags)
1157 {
1158         int ret;
1159
1160         ret = intel_ring_begin(ring, 2);
1161         if (ret)
1162                 return ret;
1163
1164         intel_ring_emit(ring,
1165                         MI_BATCH_BUFFER_START |
1166                         MI_BATCH_GTT |
1167                         (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
1168         intel_ring_emit(ring, offset);
1169         intel_ring_advance(ring);
1170
1171         return 0;
1172 }
1173
1174 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1175 #define I830_BATCH_LIMIT (256*1024)
1176 static int
1177 i830_dispatch_execbuffer(struct intel_ring_buffer *ring,
1178                                 u32 offset, u32 len,
1179                                 unsigned flags)
1180 {
1181         int ret;
1182
1183         if (flags & I915_DISPATCH_PINNED) {
1184                 ret = intel_ring_begin(ring, 4);
1185                 if (ret)
1186                         return ret;
1187
1188                 intel_ring_emit(ring, MI_BATCH_BUFFER);
1189                 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1190                 intel_ring_emit(ring, offset + len - 8);
1191                 intel_ring_emit(ring, MI_NOOP);
1192                 intel_ring_advance(ring);
1193         } else {
1194                 u32 cs_offset = ring->scratch.gtt_offset;
1195
1196                 if (len > I830_BATCH_LIMIT)
1197                         return -ENOSPC;
1198
1199                 ret = intel_ring_begin(ring, 9+3);
1200                 if (ret)
1201                         return ret;
1202                 /* Blit the batch (which has now all relocs applied) to the stable batch
1203                  * scratch bo area (so that the CS never stumbles over its tlb
1204                  * invalidation bug) ... */
1205                 intel_ring_emit(ring, XY_SRC_COPY_BLT_CMD |
1206                                 XY_SRC_COPY_BLT_WRITE_ALPHA |
1207                                 XY_SRC_COPY_BLT_WRITE_RGB);
1208                 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_GXCOPY | 4096);
1209                 intel_ring_emit(ring, 0);
1210                 intel_ring_emit(ring, (DIV_ROUND_UP(len, 4096) << 16) | 1024);
1211                 intel_ring_emit(ring, cs_offset);
1212                 intel_ring_emit(ring, 0);
1213                 intel_ring_emit(ring, 4096);
1214                 intel_ring_emit(ring, offset);
1215                 intel_ring_emit(ring, MI_FLUSH);
1216
1217                 /* ... and execute it. */
1218                 intel_ring_emit(ring, MI_BATCH_BUFFER);
1219                 intel_ring_emit(ring, cs_offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1220                 intel_ring_emit(ring, cs_offset + len - 8);
1221                 intel_ring_advance(ring);
1222         }
1223
1224         return 0;
1225 }
1226
1227 static int
1228 i915_dispatch_execbuffer(struct intel_ring_buffer *ring,
1229                          u32 offset, u32 len,
1230                          unsigned flags)
1231 {
1232         int ret;
1233
1234         ret = intel_ring_begin(ring, 2);
1235         if (ret)
1236                 return ret;
1237
1238         intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1239         intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1240         intel_ring_advance(ring);
1241
1242         return 0;
1243 }
1244
1245 static void cleanup_status_page(struct intel_ring_buffer *ring)
1246 {
1247         struct drm_i915_gem_object *obj;
1248
1249         obj = ring->status_page.obj;
1250         if (obj == NULL)
1251                 return;
1252
1253         kunmap(sg_page(obj->pages->sgl));
1254         i915_gem_object_unpin(obj);
1255         drm_gem_object_unreference(&obj->base);
1256         ring->status_page.obj = NULL;
1257 }
1258
1259 static int init_status_page(struct intel_ring_buffer *ring)
1260 {
1261         struct drm_device *dev = ring->dev;
1262         struct drm_i915_gem_object *obj;
1263         int ret;
1264
1265         obj = i915_gem_alloc_object(dev, 4096);
1266         if (obj == NULL) {
1267                 DRM_ERROR("Failed to allocate status page\n");
1268                 ret = -ENOMEM;
1269                 goto err;
1270         }
1271
1272         i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1273
1274         ret = i915_gem_obj_ggtt_pin(obj, 4096, true, false);
1275         if (ret != 0) {
1276                 goto err_unref;
1277         }
1278
1279         ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
1280         ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
1281         if (ring->status_page.page_addr == NULL) {
1282                 ret = -ENOMEM;
1283                 goto err_unpin;
1284         }
1285         ring->status_page.obj = obj;
1286         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1287
1288         DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1289                         ring->name, ring->status_page.gfx_addr);
1290
1291         return 0;
1292
1293 err_unpin:
1294         i915_gem_object_unpin(obj);
1295 err_unref:
1296         drm_gem_object_unreference(&obj->base);
1297 err:
1298         return ret;
1299 }
1300
1301 static int init_phys_status_page(struct intel_ring_buffer *ring)
1302 {
1303         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1304
1305         if (!dev_priv->status_page_dmah) {
1306                 dev_priv->status_page_dmah =
1307                         drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1308                 if (!dev_priv->status_page_dmah)
1309                         return -ENOMEM;
1310         }
1311
1312         ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1313         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1314
1315         return 0;
1316 }
1317
1318 static int intel_init_ring_buffer(struct drm_device *dev,
1319                                   struct intel_ring_buffer *ring)
1320 {
1321         struct drm_i915_gem_object *obj;
1322         struct drm_i915_private *dev_priv = dev->dev_private;
1323         int ret;
1324
1325         ring->dev = dev;
1326         INIT_LIST_HEAD(&ring->active_list);
1327         INIT_LIST_HEAD(&ring->request_list);
1328         ring->size = 32 * PAGE_SIZE;
1329         memset(ring->sync_seqno, 0, sizeof(ring->sync_seqno));
1330
1331         init_waitqueue_head(&ring->irq_queue);
1332
1333         if (I915_NEED_GFX_HWS(dev)) {
1334                 ret = init_status_page(ring);
1335                 if (ret)
1336                         return ret;
1337         } else {
1338                 BUG_ON(ring->id != RCS);
1339                 ret = init_phys_status_page(ring);
1340                 if (ret)
1341                         return ret;
1342         }
1343
1344         obj = NULL;
1345         if (!HAS_LLC(dev))
1346                 obj = i915_gem_object_create_stolen(dev, ring->size);
1347         if (obj == NULL)
1348                 obj = i915_gem_alloc_object(dev, ring->size);
1349         if (obj == NULL) {
1350                 DRM_ERROR("Failed to allocate ringbuffer\n");
1351                 ret = -ENOMEM;
1352                 goto err_hws;
1353         }
1354
1355         ring->obj = obj;
1356
1357         ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, true, false);
1358         if (ret)
1359                 goto err_unref;
1360
1361         ret = i915_gem_object_set_to_gtt_domain(obj, true);
1362         if (ret)
1363                 goto err_unpin;
1364
1365         ring->virtual_start =
1366                 ioremap_wc(dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj),
1367                            ring->size);
1368         if (ring->virtual_start == NULL) {
1369                 DRM_ERROR("Failed to map ringbuffer.\n");
1370                 ret = -EINVAL;
1371                 goto err_unpin;
1372         }
1373
1374         ret = ring->init(ring);
1375         if (ret)
1376                 goto err_unmap;
1377
1378         /* Workaround an erratum on the i830 which causes a hang if
1379          * the TAIL pointer points to within the last 2 cachelines
1380          * of the buffer.
1381          */
1382         ring->effective_size = ring->size;
1383         if (IS_I830(ring->dev) || IS_845G(ring->dev))
1384                 ring->effective_size -= 128;
1385
1386         return 0;
1387
1388 err_unmap:
1389         iounmap(ring->virtual_start);
1390 err_unpin:
1391         i915_gem_object_unpin(obj);
1392 err_unref:
1393         drm_gem_object_unreference(&obj->base);
1394         ring->obj = NULL;
1395 err_hws:
1396         cleanup_status_page(ring);
1397         return ret;
1398 }
1399
1400 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
1401 {
1402         struct drm_i915_private *dev_priv;
1403         int ret;
1404
1405         if (ring->obj == NULL)
1406                 return;
1407
1408         /* Disable the ring buffer. The ring must be idle at this point */
1409         dev_priv = ring->dev->dev_private;
1410         ret = intel_ring_idle(ring);
1411         if (ret && !i915_reset_in_progress(&dev_priv->gpu_error))
1412                 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1413                           ring->name, ret);
1414
1415         I915_WRITE_CTL(ring, 0);
1416
1417         iounmap(ring->virtual_start);
1418
1419         i915_gem_object_unpin(ring->obj);
1420         drm_gem_object_unreference(&ring->obj->base);
1421         ring->obj = NULL;
1422         ring->preallocated_lazy_request = NULL;
1423         ring->outstanding_lazy_seqno = 0;
1424
1425         if (ring->cleanup)
1426                 ring->cleanup(ring);
1427
1428         cleanup_status_page(ring);
1429 }
1430
1431 static int intel_ring_wait_seqno(struct intel_ring_buffer *ring, u32 seqno)
1432 {
1433         int ret;
1434
1435         ret = i915_wait_seqno(ring, seqno);
1436         if (!ret)
1437                 i915_gem_retire_requests_ring(ring);
1438
1439         return ret;
1440 }
1441
1442 static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n)
1443 {
1444         struct drm_i915_gem_request *request;
1445         u32 seqno = 0;
1446         int ret;
1447
1448         i915_gem_retire_requests_ring(ring);
1449
1450         if (ring->last_retired_head != -1) {
1451                 ring->head = ring->last_retired_head;
1452                 ring->last_retired_head = -1;
1453                 ring->space = ring_space(ring);
1454                 if (ring->space >= n)
1455                         return 0;
1456         }
1457
1458         list_for_each_entry(request, &ring->request_list, list) {
1459                 int space;
1460
1461                 if (request->tail == -1)
1462                         continue;
1463
1464                 space = request->tail - (ring->tail + I915_RING_FREE_SPACE);
1465                 if (space < 0)
1466                         space += ring->size;
1467                 if (space >= n) {
1468                         seqno = request->seqno;
1469                         break;
1470                 }
1471
1472                 /* Consume this request in case we need more space than
1473                  * is available and so need to prevent a race between
1474                  * updating last_retired_head and direct reads of
1475                  * I915_RING_HEAD. It also provides a nice sanity check.
1476                  */
1477                 request->tail = -1;
1478         }
1479
1480         if (seqno == 0)
1481                 return -ENOSPC;
1482
1483         ret = intel_ring_wait_seqno(ring, seqno);
1484         if (ret)
1485                 return ret;
1486
1487         if (WARN_ON(ring->last_retired_head == -1))
1488                 return -ENOSPC;
1489
1490         ring->head = ring->last_retired_head;
1491         ring->last_retired_head = -1;
1492         ring->space = ring_space(ring);
1493         if (WARN_ON(ring->space < n))
1494                 return -ENOSPC;
1495
1496         return 0;
1497 }
1498
1499 static int ring_wait_for_space(struct intel_ring_buffer *ring, int n)
1500 {
1501         struct drm_device *dev = ring->dev;
1502         struct drm_i915_private *dev_priv = dev->dev_private;
1503         unsigned long end;
1504         int ret;
1505
1506         ret = intel_ring_wait_request(ring, n);
1507         if (ret != -ENOSPC)
1508                 return ret;
1509
1510         /* force the tail write in case we have been skipping them */
1511         __intel_ring_advance(ring);
1512
1513         trace_i915_ring_wait_begin(ring);
1514         /* With GEM the hangcheck timer should kick us out of the loop,
1515          * leaving it early runs the risk of corrupting GEM state (due
1516          * to running on almost untested codepaths). But on resume
1517          * timers don't work yet, so prevent a complete hang in that
1518          * case by choosing an insanely large timeout. */
1519         end = jiffies + 60 * HZ;
1520
1521         do {
1522                 ring->head = I915_READ_HEAD(ring);
1523                 ring->space = ring_space(ring);
1524                 if (ring->space >= n) {
1525                         trace_i915_ring_wait_end(ring);
1526                         return 0;
1527                 }
1528
1529                 if (dev->primary->master) {
1530                         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1531                         if (master_priv->sarea_priv)
1532                                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1533                 }
1534
1535                 msleep(1);
1536
1537                 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1538                                            dev_priv->mm.interruptible);
1539                 if (ret)
1540                         return ret;
1541         } while (!time_after(jiffies, end));
1542         trace_i915_ring_wait_end(ring);
1543         return -EBUSY;
1544 }
1545
1546 static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
1547 {
1548         uint32_t __iomem *virt;
1549         int rem = ring->size - ring->tail;
1550
1551         if (ring->space < rem) {
1552                 int ret = ring_wait_for_space(ring, rem);
1553                 if (ret)
1554                         return ret;
1555         }
1556
1557         virt = ring->virtual_start + ring->tail;
1558         rem /= 4;
1559         while (rem--)
1560                 iowrite32(MI_NOOP, virt++);
1561
1562         ring->tail = 0;
1563         ring->space = ring_space(ring);
1564
1565         return 0;
1566 }
1567
1568 int intel_ring_idle(struct intel_ring_buffer *ring)
1569 {
1570         u32 seqno;
1571         int ret;
1572
1573         /* We need to add any requests required to flush the objects and ring */
1574         if (ring->outstanding_lazy_seqno) {
1575                 ret = i915_add_request(ring, NULL);
1576                 if (ret)
1577                         return ret;
1578         }
1579
1580         /* Wait upon the last request to be completed */
1581         if (list_empty(&ring->request_list))
1582                 return 0;
1583
1584         seqno = list_entry(ring->request_list.prev,
1585                            struct drm_i915_gem_request,
1586                            list)->seqno;
1587
1588         return i915_wait_seqno(ring, seqno);
1589 }
1590
1591 static int
1592 intel_ring_alloc_seqno(struct intel_ring_buffer *ring)
1593 {
1594         if (ring->outstanding_lazy_seqno)
1595                 return 0;
1596
1597         if (ring->preallocated_lazy_request == NULL) {
1598                 struct drm_i915_gem_request *request;
1599
1600                 request = kmalloc(sizeof(*request), GFP_KERNEL);
1601                 if (request == NULL)
1602                         return -ENOMEM;
1603
1604                 ring->preallocated_lazy_request = request;
1605         }
1606
1607         return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_seqno);
1608 }
1609
1610 static int __intel_ring_begin(struct intel_ring_buffer *ring,
1611                               int bytes)
1612 {
1613         int ret;
1614
1615         if (unlikely(ring->tail + bytes > ring->effective_size)) {
1616                 ret = intel_wrap_ring_buffer(ring);
1617                 if (unlikely(ret))
1618                         return ret;
1619         }
1620
1621         if (unlikely(ring->space < bytes)) {
1622                 ret = ring_wait_for_space(ring, bytes);
1623                 if (unlikely(ret))
1624                         return ret;
1625         }
1626
1627         ring->space -= bytes;
1628         return 0;
1629 }
1630
1631 int intel_ring_begin(struct intel_ring_buffer *ring,
1632                      int num_dwords)
1633 {
1634         drm_i915_private_t *dev_priv = ring->dev->dev_private;
1635         int ret;
1636
1637         ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1638                                    dev_priv->mm.interruptible);
1639         if (ret)
1640                 return ret;
1641
1642         /* Preallocate the olr before touching the ring */
1643         ret = intel_ring_alloc_seqno(ring);
1644         if (ret)
1645                 return ret;
1646
1647         return __intel_ring_begin(ring, num_dwords * sizeof(uint32_t));
1648 }
1649
1650 void intel_ring_init_seqno(struct intel_ring_buffer *ring, u32 seqno)
1651 {
1652         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1653
1654         BUG_ON(ring->outstanding_lazy_seqno);
1655
1656         if (INTEL_INFO(ring->dev)->gen >= 6) {
1657                 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
1658                 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
1659                 if (HAS_VEBOX(ring->dev))
1660                         I915_WRITE(RING_SYNC_2(ring->mmio_base), 0);
1661         }
1662
1663         ring->set_seqno(ring, seqno);
1664         ring->hangcheck.seqno = seqno;
1665 }
1666
1667 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
1668                                      u32 value)
1669 {
1670         drm_i915_private_t *dev_priv = ring->dev->dev_private;
1671
1672        /* Every tail move must follow the sequence below */
1673
1674         /* Disable notification that the ring is IDLE. The GT
1675          * will then assume that it is busy and bring it out of rc6.
1676          */
1677         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1678                    _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1679
1680         /* Clear the context id. Here be magic! */
1681         I915_WRITE64(GEN6_BSD_RNCID, 0x0);
1682
1683         /* Wait for the ring not to be idle, i.e. for it to wake up. */
1684         if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
1685                       GEN6_BSD_SLEEP_INDICATOR) == 0,
1686                      50))
1687                 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
1688
1689         /* Now that the ring is fully powered up, update the tail */
1690         I915_WRITE_TAIL(ring, value);
1691         POSTING_READ(RING_TAIL(ring->mmio_base));
1692
1693         /* Let the ring send IDLE messages to the GT again,
1694          * and so let it sleep to conserve power when idle.
1695          */
1696         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1697                    _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1698 }
1699
1700 static int gen6_bsd_ring_flush(struct intel_ring_buffer *ring,
1701                                u32 invalidate, u32 flush)
1702 {
1703         uint32_t cmd;
1704         int ret;
1705
1706         ret = intel_ring_begin(ring, 4);
1707         if (ret)
1708                 return ret;
1709
1710         cmd = MI_FLUSH_DW;
1711         if (INTEL_INFO(ring->dev)->gen >= 8)
1712                 cmd += 1;
1713         /*
1714          * Bspec vol 1c.5 - video engine command streamer:
1715          * "If ENABLED, all TLBs will be invalidated once the flush
1716          * operation is complete. This bit is only valid when the
1717          * Post-Sync Operation field is a value of 1h or 3h."
1718          */
1719         if (invalidate & I915_GEM_GPU_DOMAINS)
1720                 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD |
1721                         MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
1722         intel_ring_emit(ring, cmd);
1723         intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
1724         if (INTEL_INFO(ring->dev)->gen >= 8) {
1725                 intel_ring_emit(ring, 0); /* upper addr */
1726                 intel_ring_emit(ring, 0); /* value */
1727         } else  {
1728                 intel_ring_emit(ring, 0);
1729                 intel_ring_emit(ring, MI_NOOP);
1730         }
1731         intel_ring_advance(ring);
1732         return 0;
1733 }
1734
1735 static int
1736 gen8_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1737                               u32 offset, u32 len,
1738                               unsigned flags)
1739 {
1740         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1741         bool ppgtt = dev_priv->mm.aliasing_ppgtt != NULL &&
1742                 !(flags & I915_DISPATCH_SECURE);
1743         int ret;
1744
1745         ret = intel_ring_begin(ring, 4);
1746         if (ret)
1747                 return ret;
1748
1749         /* FIXME(BDW): Address space and security selectors. */
1750         intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
1751         intel_ring_emit(ring, offset);
1752         intel_ring_emit(ring, 0);
1753         intel_ring_emit(ring, MI_NOOP);
1754         intel_ring_advance(ring);
1755
1756         return 0;
1757 }
1758
1759 static int
1760 hsw_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1761                               u32 offset, u32 len,
1762                               unsigned flags)
1763 {
1764         int ret;
1765
1766         ret = intel_ring_begin(ring, 2);
1767         if (ret)
1768                 return ret;
1769
1770         intel_ring_emit(ring,
1771                         MI_BATCH_BUFFER_START | MI_BATCH_PPGTT_HSW |
1772                         (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_HSW));
1773         /* bit0-7 is the length on GEN6+ */
1774         intel_ring_emit(ring, offset);
1775         intel_ring_advance(ring);
1776
1777         return 0;
1778 }
1779
1780 static int
1781 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1782                               u32 offset, u32 len,
1783                               unsigned flags)
1784 {
1785         int ret;
1786
1787         ret = intel_ring_begin(ring, 2);
1788         if (ret)
1789                 return ret;
1790
1791         intel_ring_emit(ring,
1792                         MI_BATCH_BUFFER_START |
1793                         (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
1794         /* bit0-7 is the length on GEN6+ */
1795         intel_ring_emit(ring, offset);
1796         intel_ring_advance(ring);
1797
1798         return 0;
1799 }
1800
1801 /* Blitter support (SandyBridge+) */
1802
1803 static int gen6_ring_flush(struct intel_ring_buffer *ring,
1804                            u32 invalidate, u32 flush)
1805 {
1806         struct drm_device *dev = ring->dev;
1807         uint32_t cmd;
1808         int ret;
1809
1810         ret = intel_ring_begin(ring, 4);
1811         if (ret)
1812                 return ret;
1813
1814         cmd = MI_FLUSH_DW;
1815         if (INTEL_INFO(ring->dev)->gen >= 8)
1816                 cmd += 1;
1817         /*
1818          * Bspec vol 1c.3 - blitter engine command streamer:
1819          * "If ENABLED, all TLBs will be invalidated once the flush
1820          * operation is complete. This bit is only valid when the
1821          * Post-Sync Operation field is a value of 1h or 3h."
1822          */
1823         if (invalidate & I915_GEM_DOMAIN_RENDER)
1824                 cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX |
1825                         MI_FLUSH_DW_OP_STOREDW;
1826         intel_ring_emit(ring, cmd);
1827         intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
1828         if (INTEL_INFO(ring->dev)->gen >= 8) {
1829                 intel_ring_emit(ring, 0); /* upper addr */
1830                 intel_ring_emit(ring, 0); /* value */
1831         } else  {
1832                 intel_ring_emit(ring, 0);
1833                 intel_ring_emit(ring, MI_NOOP);
1834         }
1835         intel_ring_advance(ring);
1836
1837         if (IS_GEN7(dev) && !invalidate && flush)
1838                 return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN);
1839
1840         return 0;
1841 }
1842
1843 int intel_init_render_ring_buffer(struct drm_device *dev)
1844 {
1845         drm_i915_private_t *dev_priv = dev->dev_private;
1846         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1847
1848         ring->name = "render ring";
1849         ring->id = RCS;
1850         ring->mmio_base = RENDER_RING_BASE;
1851
1852         if (INTEL_INFO(dev)->gen >= 6) {
1853                 ring->add_request = gen6_add_request;
1854                 ring->flush = gen7_render_ring_flush;
1855                 if (INTEL_INFO(dev)->gen == 6)
1856                         ring->flush = gen6_render_ring_flush;
1857                 if (INTEL_INFO(dev)->gen >= 8) {
1858                         ring->flush = gen8_render_ring_flush;
1859                         ring->irq_get = gen8_ring_get_irq;
1860                         ring->irq_put = gen8_ring_put_irq;
1861                 } else {
1862                         ring->irq_get = gen6_ring_get_irq;
1863                         ring->irq_put = gen6_ring_put_irq;
1864                 }
1865                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
1866                 ring->get_seqno = gen6_ring_get_seqno;
1867                 ring->set_seqno = ring_set_seqno;
1868                 ring->sync_to = gen6_ring_sync;
1869                 ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_INVALID;
1870                 ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_RV;
1871                 ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_RB;
1872                 ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_RVE;
1873                 ring->signal_mbox[RCS] = GEN6_NOSYNC;
1874                 ring->signal_mbox[VCS] = GEN6_VRSYNC;
1875                 ring->signal_mbox[BCS] = GEN6_BRSYNC;
1876                 ring->signal_mbox[VECS] = GEN6_VERSYNC;
1877         } else if (IS_GEN5(dev)) {
1878                 ring->add_request = pc_render_add_request;
1879                 ring->flush = gen4_render_ring_flush;
1880                 ring->get_seqno = pc_render_get_seqno;
1881                 ring->set_seqno = pc_render_set_seqno;
1882                 ring->irq_get = gen5_ring_get_irq;
1883                 ring->irq_put = gen5_ring_put_irq;
1884                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
1885                                         GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
1886         } else {
1887                 ring->add_request = i9xx_add_request;
1888                 if (INTEL_INFO(dev)->gen < 4)
1889                         ring->flush = gen2_render_ring_flush;
1890                 else
1891                         ring->flush = gen4_render_ring_flush;
1892                 ring->get_seqno = ring_get_seqno;
1893                 ring->set_seqno = ring_set_seqno;
1894                 if (IS_GEN2(dev)) {
1895                         ring->irq_get = i8xx_ring_get_irq;
1896                         ring->irq_put = i8xx_ring_put_irq;
1897                 } else {
1898                         ring->irq_get = i9xx_ring_get_irq;
1899                         ring->irq_put = i9xx_ring_put_irq;
1900                 }
1901                 ring->irq_enable_mask = I915_USER_INTERRUPT;
1902         }
1903         ring->write_tail = ring_write_tail;
1904         if (IS_HASWELL(dev))
1905                 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
1906         else if (IS_GEN8(dev))
1907                 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
1908         else if (INTEL_INFO(dev)->gen >= 6)
1909                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1910         else if (INTEL_INFO(dev)->gen >= 4)
1911                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1912         else if (IS_I830(dev) || IS_845G(dev))
1913                 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1914         else
1915                 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1916         ring->init = init_render_ring;
1917         ring->cleanup = render_ring_cleanup;
1918
1919         /* Workaround batchbuffer to combat CS tlb bug. */
1920         if (HAS_BROKEN_CS_TLB(dev)) {
1921                 struct drm_i915_gem_object *obj;
1922                 int ret;
1923
1924                 obj = i915_gem_alloc_object(dev, I830_BATCH_LIMIT);
1925                 if (obj == NULL) {
1926                         DRM_ERROR("Failed to allocate batch bo\n");
1927                         return -ENOMEM;
1928                 }
1929
1930                 ret = i915_gem_obj_ggtt_pin(obj, 0, true, false);
1931                 if (ret != 0) {
1932                         drm_gem_object_unreference(&obj->base);
1933                         DRM_ERROR("Failed to ping batch bo\n");
1934                         return ret;
1935                 }
1936
1937                 ring->scratch.obj = obj;
1938                 ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
1939         }
1940
1941         return intel_init_ring_buffer(dev, ring);
1942 }
1943
1944 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
1945 {
1946         drm_i915_private_t *dev_priv = dev->dev_private;
1947         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1948         int ret;
1949
1950         ring->name = "render ring";
1951         ring->id = RCS;
1952         ring->mmio_base = RENDER_RING_BASE;
1953
1954         if (INTEL_INFO(dev)->gen >= 6) {
1955                 /* non-kms not supported on gen6+ */
1956                 return -ENODEV;
1957         }
1958
1959         /* Note: gem is not supported on gen5/ilk without kms (the corresponding
1960          * gem_init ioctl returns with -ENODEV). Hence we do not need to set up
1961          * the special gen5 functions. */
1962         ring->add_request = i9xx_add_request;
1963         if (INTEL_INFO(dev)->gen < 4)
1964                 ring->flush = gen2_render_ring_flush;
1965         else
1966                 ring->flush = gen4_render_ring_flush;
1967         ring->get_seqno = ring_get_seqno;
1968         ring->set_seqno = ring_set_seqno;
1969         if (IS_GEN2(dev)) {
1970                 ring->irq_get = i8xx_ring_get_irq;
1971                 ring->irq_put = i8xx_ring_put_irq;
1972         } else {
1973                 ring->irq_get = i9xx_ring_get_irq;
1974                 ring->irq_put = i9xx_ring_put_irq;
1975         }
1976         ring->irq_enable_mask = I915_USER_INTERRUPT;
1977         ring->write_tail = ring_write_tail;
1978         if (INTEL_INFO(dev)->gen >= 4)
1979                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1980         else if (IS_I830(dev) || IS_845G(dev))
1981                 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1982         else
1983                 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1984         ring->init = init_render_ring;
1985         ring->cleanup = render_ring_cleanup;
1986
1987         ring->dev = dev;
1988         INIT_LIST_HEAD(&ring->active_list);
1989         INIT_LIST_HEAD(&ring->request_list);
1990
1991         ring->size = size;
1992         ring->effective_size = ring->size;
1993         if (IS_I830(ring->dev) || IS_845G(ring->dev))
1994                 ring->effective_size -= 128;
1995
1996         ring->virtual_start = ioremap_wc(start, size);
1997         if (ring->virtual_start == NULL) {
1998                 DRM_ERROR("can not ioremap virtual address for"
1999                           " ring buffer\n");
2000                 return -ENOMEM;
2001         }
2002
2003         if (!I915_NEED_GFX_HWS(dev)) {
2004                 ret = init_phys_status_page(ring);
2005                 if (ret)
2006                         return ret;
2007         }
2008
2009         return 0;
2010 }
2011
2012 int intel_init_bsd_ring_buffer(struct drm_device *dev)
2013 {
2014         drm_i915_private_t *dev_priv = dev->dev_private;
2015         struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
2016
2017         ring->name = "bsd ring";
2018         ring->id = VCS;
2019
2020         ring->write_tail = ring_write_tail;
2021         if (INTEL_INFO(dev)->gen >= 6) {
2022                 ring->mmio_base = GEN6_BSD_RING_BASE;
2023                 /* gen6 bsd needs a special wa for tail updates */
2024                 if (IS_GEN6(dev))
2025                         ring->write_tail = gen6_bsd_ring_write_tail;
2026                 ring->flush = gen6_bsd_ring_flush;
2027                 ring->add_request = gen6_add_request;
2028                 ring->get_seqno = gen6_ring_get_seqno;
2029                 ring->set_seqno = ring_set_seqno;
2030                 if (INTEL_INFO(dev)->gen >= 8) {
2031                         ring->irq_enable_mask =
2032                                 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
2033                         ring->irq_get = gen8_ring_get_irq;
2034                         ring->irq_put = gen8_ring_put_irq;
2035                         ring->dispatch_execbuffer =
2036                                 gen8_ring_dispatch_execbuffer;
2037                 } else {
2038                         ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2039                         ring->irq_get = gen6_ring_get_irq;
2040                         ring->irq_put = gen6_ring_put_irq;
2041                         ring->dispatch_execbuffer =
2042                                 gen6_ring_dispatch_execbuffer;
2043                 }
2044                 ring->sync_to = gen6_ring_sync;
2045                 ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VR;
2046                 ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2047                 ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VB;
2048                 ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_VVE;
2049                 ring->signal_mbox[RCS] = GEN6_RVSYNC;
2050                 ring->signal_mbox[VCS] = GEN6_NOSYNC;
2051                 ring->signal_mbox[BCS] = GEN6_BVSYNC;
2052                 ring->signal_mbox[VECS] = GEN6_VEVSYNC;
2053         } else {
2054                 ring->mmio_base = BSD_RING_BASE;
2055                 ring->flush = bsd_ring_flush;
2056                 ring->add_request = i9xx_add_request;
2057                 ring->get_seqno = ring_get_seqno;
2058                 ring->set_seqno = ring_set_seqno;
2059                 if (IS_GEN5(dev)) {
2060                         ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
2061                         ring->irq_get = gen5_ring_get_irq;
2062                         ring->irq_put = gen5_ring_put_irq;
2063                 } else {
2064                         ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
2065                         ring->irq_get = i9xx_ring_get_irq;
2066                         ring->irq_put = i9xx_ring_put_irq;
2067                 }
2068                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
2069         }
2070         ring->init = init_ring_common;
2071
2072         return intel_init_ring_buffer(dev, ring);
2073 }
2074
2075 int intel_init_blt_ring_buffer(struct drm_device *dev)
2076 {
2077         drm_i915_private_t *dev_priv = dev->dev_private;
2078         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
2079
2080         ring->name = "blitter ring";
2081         ring->id = BCS;
2082
2083         ring->mmio_base = BLT_RING_BASE;
2084         ring->write_tail = ring_write_tail;
2085         ring->flush = gen6_ring_flush;
2086         ring->add_request = gen6_add_request;
2087         ring->get_seqno = gen6_ring_get_seqno;
2088         ring->set_seqno = ring_set_seqno;
2089         if (INTEL_INFO(dev)->gen >= 8) {
2090                 ring->irq_enable_mask =
2091                         GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
2092                 ring->irq_get = gen8_ring_get_irq;
2093                 ring->irq_put = gen8_ring_put_irq;
2094                 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2095         } else {
2096                 ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2097                 ring->irq_get = gen6_ring_get_irq;
2098                 ring->irq_put = gen6_ring_put_irq;
2099                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2100         }
2101         ring->sync_to = gen6_ring_sync;
2102         ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_BR;
2103         ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_BV;
2104         ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_INVALID;
2105         ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_BVE;
2106         ring->signal_mbox[RCS] = GEN6_RBSYNC;
2107         ring->signal_mbox[VCS] = GEN6_VBSYNC;
2108         ring->signal_mbox[BCS] = GEN6_NOSYNC;
2109         ring->signal_mbox[VECS] = GEN6_VEBSYNC;
2110         ring->init = init_ring_common;
2111
2112         return intel_init_ring_buffer(dev, ring);
2113 }
2114
2115 int intel_init_vebox_ring_buffer(struct drm_device *dev)
2116 {
2117         drm_i915_private_t *dev_priv = dev->dev_private;
2118         struct intel_ring_buffer *ring = &dev_priv->ring[VECS];
2119
2120         ring->name = "video enhancement ring";
2121         ring->id = VECS;
2122
2123         ring->mmio_base = VEBOX_RING_BASE;
2124         ring->write_tail = ring_write_tail;
2125         ring->flush = gen6_ring_flush;
2126         ring->add_request = gen6_add_request;
2127         ring->get_seqno = gen6_ring_get_seqno;
2128         ring->set_seqno = ring_set_seqno;
2129
2130         if (INTEL_INFO(dev)->gen >= 8) {
2131                 ring->irq_enable_mask =
2132                         GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
2133                 ring->irq_get = gen8_ring_get_irq;
2134                 ring->irq_put = gen8_ring_put_irq;
2135                 ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
2136         } else {
2137                 ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
2138                 ring->irq_get = hsw_vebox_get_irq;
2139                 ring->irq_put = hsw_vebox_put_irq;
2140                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2141         }
2142         ring->sync_to = gen6_ring_sync;
2143         ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VER;
2144         ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_VEV;
2145         ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VEB;
2146         ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_INVALID;
2147         ring->signal_mbox[RCS] = GEN6_RVESYNC;
2148         ring->signal_mbox[VCS] = GEN6_VVESYNC;
2149         ring->signal_mbox[BCS] = GEN6_BVESYNC;
2150         ring->signal_mbox[VECS] = GEN6_NOSYNC;
2151         ring->init = init_ring_common;
2152
2153         return intel_init_ring_buffer(dev, ring);
2154 }
2155
2156 int
2157 intel_ring_flush_all_caches(struct intel_ring_buffer *ring)
2158 {
2159         int ret;
2160
2161         if (!ring->gpu_caches_dirty)
2162                 return 0;
2163
2164         ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
2165         if (ret)
2166                 return ret;
2167
2168         trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS);
2169
2170         ring->gpu_caches_dirty = false;
2171         return 0;
2172 }
2173
2174 int
2175 intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring)
2176 {
2177         uint32_t flush_domains;
2178         int ret;
2179
2180         flush_domains = 0;
2181         if (ring->gpu_caches_dirty)
2182                 flush_domains = I915_GEM_GPU_DOMAINS;
2183
2184         ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2185         if (ret)
2186                 return ret;
2187
2188         trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2189
2190         ring->gpu_caches_dirty = false;
2191         return 0;
2192 }