Pileus Git - ~andy/linux/blob - drivers/gpu/drm/i915/intel_ringbuffer.c

   1 /*
   2  * Copyright © 2008-2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Zou Nan hai <nanhai.zou@intel.com>
  26  *    Xiang Hai hao<haihao.xiang@intel.com>
  27  *
  28  */
  29
  30 #include "drmP.h"
  31 #include "drm.h"
  32 #include "i915_drv.h"
  33 #include "i915_drm.h"
  34 #include "i915_trace.h"
  35 #include "intel_drv.h"
  36
  37 /*
  38  * 965+ support PIPE_CONTROL commands, which provide finer grained control
  39  * over cache flushing.
  40  */
  41 struct pipe_control {
  42         struct drm_i915_gem_object *obj;
  43         volatile u32 *cpu_page;
  44         u32 gtt_offset;
  45 };
  46
  47 static inline int ring_space(struct intel_ring_buffer *ring)
  48 {
  49         int space = (ring->head & HEAD_ADDR) - (ring->tail + 8);
  50         if (space < 0)
  51                 space += ring->size;
  52         return space;
  53 }
  54
  55 static int
  56 gen2_render_ring_flush(struct intel_ring_buffer *ring,
  57                        u32      invalidate_domains,
  58                        u32      flush_domains)
  59 {
  60         u32 cmd;
  61         int ret;
  62
  63         cmd = MI_FLUSH;
  64         if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
  65                 cmd |= MI_NO_WRITE_FLUSH;
  66
  67         if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
  68                 cmd |= MI_READ_FLUSH;
  69
  70         ret = intel_ring_begin(ring, 2);
  71         if (ret)
  72                 return ret;
  73
  74         intel_ring_emit(ring, cmd);
  75         intel_ring_emit(ring, MI_NOOP);
  76         intel_ring_advance(ring);
  77
  78         return 0;
  79 }
  80
  81 static int
  82 gen4_render_ring_flush(struct intel_ring_buffer *ring,
  83                        u32      invalidate_domains,
  84                        u32      flush_domains)
  85 {
  86         struct drm_device *dev = ring->dev;
  87         u32 cmd;
  88         int ret;
  89
  90         /*
  91          * read/write caches:
  92          *
  93          * I915_GEM_DOMAIN_RENDER is always invalidated, but is
  94          * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
  95          * also flushed at 2d versus 3d pipeline switches.
  96          *
  97          * read-only caches:
  98          *
  99          * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
 100          * MI_READ_FLUSH is set, and is always flushed on 965.
 101          *
 102          * I915_GEM_DOMAIN_COMMAND may not exist?
 103          *
 104          * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
 105          * invalidated when MI_EXE_FLUSH is set.
 106          *
 107          * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
 108          * invalidated with every MI_FLUSH.
 109          *
 110          * TLBs:
 111          *
 112          * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
 113          * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
 114          * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
 115          * are flushed at any MI_FLUSH.
 116          */
 117
 118         cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
 119         if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
 120                 cmd &= ~MI_NO_WRITE_FLUSH;
 121         if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
 122                 cmd |= MI_EXE_FLUSH;
 123
 124         if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
 125             (IS_G4X(dev) || IS_GEN5(dev)))
 126                 cmd |= MI_INVALIDATE_ISP;
 127
 128         ret = intel_ring_begin(ring, 2);
 129         if (ret)
 130                 return ret;
 131
 132         intel_ring_emit(ring, cmd);
 133         intel_ring_emit(ring, MI_NOOP);
 134         intel_ring_advance(ring);
 135
 136         return 0;
 137 }
 138
 139 /**
 140  * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
 141  * implementing two workarounds on gen6.  From section 1.4.7.1
 142  * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
 143  *
 144  * [DevSNB-C+{W/A}] Before any depth stall flush (including those
 145  * produced by non-pipelined state commands), software needs to first
 146  * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
 147  * 0.
 148  *
 149  * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
 150  * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
 151  *
 152  * And the workaround for these two requires this workaround first:
 153  *
 154  * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
 155  * BEFORE the pipe-control with a post-sync op and no write-cache
 156  * flushes.
 157  *
 158  * And this last workaround is tricky because of the requirements on
 159  * that bit.  From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
 160  * volume 2 part 1:
 161  *
 162  *     "1 of the following must also be set:
 163  *      - Render Target Cache Flush Enable ([12] of DW1)
 164  *      - Depth Cache Flush Enable ([0] of DW1)
 165  *      - Stall at Pixel Scoreboard ([1] of DW1)
 166  *      - Depth Stall ([13] of DW1)
 167  *      - Post-Sync Operation ([13] of DW1)
 168  *      - Notify Enable ([8] of DW1)"
 169  *
 170  * The cache flushes require the workaround flush that triggered this
 171  * one, so we can't use it.  Depth stall would trigger the same.
 172  * Post-sync nonzero is what triggered this second workaround, so we
 173  * can't use that one either.  Notify enable is IRQs, which aren't
 174  * really our business.  That leaves only stall at scoreboard.
 175  */
 176 static int
 177 intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring)
 178 {
 179         struct pipe_control *pc = ring->private;
 180         u32 scratch_addr = pc->gtt_offset + 128;
 181         int ret;
 182
 183
 184         ret = intel_ring_begin(ring, 6);
 185         if (ret)
 186                 return ret;
 187
 188         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 189         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 190                         PIPE_CONTROL_STALL_AT_SCOREBOARD);
 191         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 192         intel_ring_emit(ring, 0); /* low dword */
 193         intel_ring_emit(ring, 0); /* high dword */
 194         intel_ring_emit(ring, MI_NOOP);
 195         intel_ring_advance(ring);
 196
 197         ret = intel_ring_begin(ring, 6);
 198         if (ret)
 199                 return ret;
 200
 201         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 202         intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
 203         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 204         intel_ring_emit(ring, 0);
 205         intel_ring_emit(ring, 0);
 206         intel_ring_emit(ring, MI_NOOP);
 207         intel_ring_advance(ring);
 208
 209         return 0;
 210 }
 211
 212 static int
 213 gen6_render_ring_flush(struct intel_ring_buffer *ring,
 214                          u32 invalidate_domains, u32 flush_domains)
 215 {
 216         u32 flags = 0;
 217         struct pipe_control *pc = ring->private;
 218         u32 scratch_addr = pc->gtt_offset + 128;
 219         int ret;
 220
 221         /* Force SNB workarounds for PIPE_CONTROL flushes */
 222         intel_emit_post_sync_nonzero_flush(ring);
 223
 224         /* Just flush everything.  Experiments have shown that reducing the
 225          * number of bits based on the write domains has little performance
 226          * impact.
 227          */
 228         flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 229         flags |= PIPE_CONTROL_TLB_INVALIDATE;
 230         flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 231         flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 232         flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 233         flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 234         flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 235         flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 236
 237         ret = intel_ring_begin(ring, 6);
 238         if (ret)
 239                 return ret;
 240
 241         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 242         intel_ring_emit(ring, flags);
 243         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
 244         intel_ring_emit(ring, 0); /* lower dword */
 245         intel_ring_emit(ring, 0); /* uppwer dword */
 246         intel_ring_emit(ring, MI_NOOP);
 247         intel_ring_advance(ring);
 248
 249         return 0;
 250 }
 251
 252 static void ring_write_tail(struct intel_ring_buffer *ring,
 253                             u32 value)
 254 {
 255         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 256         I915_WRITE_TAIL(ring, value);
 257 }
 258
 259 u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
 260 {
 261         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 262         u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
 263                         RING_ACTHD(ring->mmio_base) : ACTHD;
 264
 265         return I915_READ(acthd_reg);
 266 }
 267
 268 static int init_ring_common(struct intel_ring_buffer *ring)
 269 {
 270         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 271         struct drm_i915_gem_object *obj = ring->obj;
 272         u32 head;
 273
 274         /* Stop the ring if it's running. */
 275         I915_WRITE_CTL(ring, 0);
 276         I915_WRITE_HEAD(ring, 0);
 277         ring->write_tail(ring, 0);
 278
 279         /* Initialize the ring. */
 280         I915_WRITE_START(ring, obj->gtt_offset);
 281         head = I915_READ_HEAD(ring) & HEAD_ADDR;
 282
 283         /* G45 ring initialization fails to reset head to zero */
 284         if (head != 0) {
 285                 DRM_DEBUG_KMS("%s head not reset to zero "
 286                               "ctl %08x head %08x tail %08x start %08x\n",
 287                               ring->name,
 288                               I915_READ_CTL(ring),
 289                               I915_READ_HEAD(ring),
 290                               I915_READ_TAIL(ring),
 291                               I915_READ_START(ring));
 292
 293                 I915_WRITE_HEAD(ring, 0);
 294
 295                 if (I915_READ_HEAD(ring) & HEAD_ADDR) {
 296                         DRM_ERROR("failed to set %s head to zero "
 297                                   "ctl %08x head %08x tail %08x start %08x\n",
 298                                   ring->name,
 299                                   I915_READ_CTL(ring),
 300                                   I915_READ_HEAD(ring),
 301                                   I915_READ_TAIL(ring),
 302                                   I915_READ_START(ring));
 303                 }
 304         }
 305
 306         I915_WRITE_CTL(ring,
 307                         ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
 308                         | RING_VALID);
 309
 310         /* If the head is still not zero, the ring is dead */
 311         if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
 312                      I915_READ_START(ring) == obj->gtt_offset &&
 313                      (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
 314                 DRM_ERROR("%s initialization failed "
 315                                 "ctl %08x head %08x tail %08x start %08x\n",
 316                                 ring->name,
 317                                 I915_READ_CTL(ring),
 318                                 I915_READ_HEAD(ring),
 319                                 I915_READ_TAIL(ring),
 320                                 I915_READ_START(ring));
 321                 return -EIO;
 322         }
 323
 324         if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
 325                 i915_kernel_lost_context(ring->dev);
 326         else {
 327                 ring->head = I915_READ_HEAD(ring);
 328                 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 329                 ring->space = ring_space(ring);
 330         }
 331
 332         return 0;
 333 }
 334
 335 static int
 336 init_pipe_control(struct intel_ring_buffer *ring)
 337 {
 338         struct pipe_control *pc;
 339         struct drm_i915_gem_object *obj;
 340         int ret;
 341
 342         if (ring->private)
 343                 return 0;
 344
 345         pc = kmalloc(sizeof(*pc), GFP_KERNEL);
 346         if (!pc)
 347                 return -ENOMEM;
 348
 349         obj = i915_gem_alloc_object(ring->dev, 4096);
 350         if (obj == NULL) {
 351                 DRM_ERROR("Failed to allocate seqno page\n");
 352                 ret = -ENOMEM;
 353                 goto err;
 354         }
 355
 356         i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
 357
 358         ret = i915_gem_object_pin(obj, 4096, true);
 359         if (ret)
 360                 goto err_unref;
 361
 362         pc->gtt_offset = obj->gtt_offset;
 363         pc->cpu_page =  kmap(obj->pages[0]);
 364         if (pc->cpu_page == NULL)
 365                 goto err_unpin;
 366
 367         pc->obj = obj;
 368         ring->private = pc;
 369         return 0;
 370
 371 err_unpin:
 372         i915_gem_object_unpin(obj);
 373 err_unref:
 374         drm_gem_object_unreference(&obj->base);
 375 err:
 376         kfree(pc);
 377         return ret;
 378 }
 379
 380 static void
 381 cleanup_pipe_control(struct intel_ring_buffer *ring)
 382 {
 383         struct pipe_control *pc = ring->private;
 384         struct drm_i915_gem_object *obj;
 385
 386         if (!ring->private)
 387                 return;
 388
 389         obj = pc->obj;
 390         kunmap(obj->pages[0]);
 391         i915_gem_object_unpin(obj);
 392         drm_gem_object_unreference(&obj->base);
 393
 394         kfree(pc);
 395         ring->private = NULL;
 396 }
 397
 398 static int init_render_ring(struct intel_ring_buffer *ring)
 399 {
 400         struct drm_device *dev = ring->dev;
 401         struct drm_i915_private *dev_priv = dev->dev_private;
 402         int ret = init_ring_common(ring);
 403
 404         if (INTEL_INFO(dev)->gen > 3) {
 405                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
 406                 if (IS_GEN7(dev))
 407                         I915_WRITE(GFX_MODE_GEN7,
 408                                    _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
 409                                    _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
 410         }
 411
 412         if (INTEL_INFO(dev)->gen >= 5) {
 413                 ret = init_pipe_control(ring);
 414                 if (ret)
 415                         return ret;
 416         }
 417
 418         if (IS_GEN6(dev)) {
 419                 /* From the Sandybridge PRM, volume 1 part 3, page 24:
 420                  * "If this bit is set, STCunit will have LRA as replacement
 421                  *  policy. [...] This bit must be reset.  LRA replacement
 422                  *  policy is not supported."
 423                  */
 424                 I915_WRITE(CACHE_MODE_0,
 425                            _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
 426         }
 427
 428         if (INTEL_INFO(dev)->gen >= 6)
 429                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
 430
 431         if (IS_IVYBRIDGE(dev))
 432                 I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR);
 433
 434         return ret;
 435 }
 436
 437 static void render_ring_cleanup(struct intel_ring_buffer *ring)
 438 {
 439         if (!ring->private)
 440                 return;
 441
 442         cleanup_pipe_control(ring);
 443 }
 444
 445 static void
 446 update_mboxes(struct intel_ring_buffer *ring,
 447             u32 seqno,
 448             u32 mmio_offset)
 449 {
 450         intel_ring_emit(ring, MI_SEMAPHORE_MBOX |
 451                               MI_SEMAPHORE_GLOBAL_GTT |
 452                               MI_SEMAPHORE_REGISTER |
 453                               MI_SEMAPHORE_UPDATE);
 454         intel_ring_emit(ring, seqno);
 455         intel_ring_emit(ring, mmio_offset);
 456 }
 457
 458 /**
 459  * gen6_add_request - Update the semaphore mailbox registers
 460  *
 461  * @ring - ring that is adding a request
 462  * @seqno - return seqno stuck into the ring
 463  *
 464  * Update the mailbox registers in the *other* rings with the current seqno.
 465  * This acts like a signal in the canonical semaphore.
 466  */
 467 static int
 468 gen6_add_request(struct intel_ring_buffer *ring,
 469                  u32 *seqno)
 470 {
 471         u32 mbox1_reg;
 472         u32 mbox2_reg;
 473         int ret;
 474
 475         ret = intel_ring_begin(ring, 10);
 476         if (ret)
 477                 return ret;
 478
 479         mbox1_reg = ring->signal_mbox[0];
 480         mbox2_reg = ring->signal_mbox[1];
 481
 482         *seqno = i915_gem_next_request_seqno(ring);
 483
 484         update_mboxes(ring, *seqno, mbox1_reg);
 485         update_mboxes(ring, *seqno, mbox2_reg);
 486         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
 487         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 488         intel_ring_emit(ring, *seqno);
 489         intel_ring_emit(ring, MI_USER_INTERRUPT);
 490         intel_ring_advance(ring);
 491
 492         return 0;
 493 }
 494
 495 /**
 496  * intel_ring_sync - sync the waiter to the signaller on seqno
 497  *
 498  * @waiter - ring that is waiting
 499  * @signaller - ring which has, or will signal
 500  * @seqno - seqno which the waiter will block on
 501  */
 502 static int
 503 gen6_ring_sync(struct intel_ring_buffer *waiter,
 504                struct intel_ring_buffer *signaller,
 505                u32 seqno)
 506 {
 507         int ret;
 508         u32 dw1 = MI_SEMAPHORE_MBOX |
 509                   MI_SEMAPHORE_COMPARE |
 510                   MI_SEMAPHORE_REGISTER;
 511
 512         /* Throughout all of the GEM code, seqno passed implies our current
 513          * seqno is >= the last seqno executed. However for hardware the
 514          * comparison is strictly greater than.
 515          */
 516         seqno -= 1;
 517
 518         WARN_ON(signaller->semaphore_register[waiter->id] ==
 519                 MI_SEMAPHORE_SYNC_INVALID);
 520
 521         ret = intel_ring_begin(waiter, 4);
 522         if (ret)
 523                 return ret;
 524
 525         intel_ring_emit(waiter,
 526                         dw1 | signaller->semaphore_register[waiter->id]);
 527         intel_ring_emit(waiter, seqno);
 528         intel_ring_emit(waiter, 0);
 529         intel_ring_emit(waiter, MI_NOOP);
 530         intel_ring_advance(waiter);
 531
 532         return 0;
 533 }
 534
 535 #define PIPE_CONTROL_FLUSH(ring__, addr__)                                      \
 536 do {                                                                    \
 537         intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |                \
 538                  PIPE_CONTROL_DEPTH_STALL);                             \
 539         intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT);                    \
 540         intel_ring_emit(ring__, 0);                                                     \
 541         intel_ring_emit(ring__, 0);                                                     \
 542 } while (0)
 543
 544 static int
 545 pc_render_add_request(struct intel_ring_buffer *ring,
 546                       u32 *result)
 547 {
 548         u32 seqno = i915_gem_next_request_seqno(ring);
 549         struct pipe_control *pc = ring->private;
 550         u32 scratch_addr = pc->gtt_offset + 128;
 551         int ret;
 552
 553         /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
 554          * incoherent with writes to memory, i.e. completely fubar,
 555          * so we need to use PIPE_NOTIFY instead.
 556          *
 557          * However, we also need to workaround the qword write
 558          * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
 559          * memory before requesting an interrupt.
 560          */
 561         ret = intel_ring_begin(ring, 32);
 562         if (ret)
 563                 return ret;
 564
 565         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
 566                         PIPE_CONTROL_WRITE_FLUSH |
 567                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
 568         intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
 569         intel_ring_emit(ring, seqno);
 570         intel_ring_emit(ring, 0);
 571         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 572         scratch_addr += 128; /* write to separate cachelines */
 573         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 574         scratch_addr += 128;
 575         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 576         scratch_addr += 128;
 577         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 578         scratch_addr += 128;
 579         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 580         scratch_addr += 128;
 581         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 582
 583         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
 584                         PIPE_CONTROL_WRITE_FLUSH |
 585                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
 586                         PIPE_CONTROL_NOTIFY);
 587         intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
 588         intel_ring_emit(ring, seqno);
 589         intel_ring_emit(ring, 0);
 590         intel_ring_advance(ring);
 591
 592         *result = seqno;
 593         return 0;
 594 }
 595
 596 static u32
 597 gen6_ring_get_seqno(struct intel_ring_buffer *ring)
 598 {
 599         struct drm_device *dev = ring->dev;
 600
 601         /* Workaround to force correct ordering between irq and seqno writes on
 602          * ivb (and maybe also on snb) by reading from a CS register (like
 603          * ACTHD) before reading the status page. */
 604         if (IS_GEN6(dev) || IS_GEN7(dev))
 605                 intel_ring_get_active_head(ring);
 606         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
 607 }
 608
 609 static u32
 610 ring_get_seqno(struct intel_ring_buffer *ring)
 611 {
 612         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
 613 }
 614
 615 static u32
 616 pc_render_get_seqno(struct intel_ring_buffer *ring)
 617 {
 618         struct pipe_control *pc = ring->private;
 619         return pc->cpu_page[0];
 620 }
 621
 622 static bool
 623 gen5_ring_get_irq(struct intel_ring_buffer *ring)
 624 {
 625         struct drm_device *dev = ring->dev;
 626         drm_i915_private_t *dev_priv = dev->dev_private;
 627         unsigned long flags;
 628
 629         if (!dev->irq_enabled)
 630                 return false;
 631
 632         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 633         if (ring->irq_refcount++ == 0) {
 634                 dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
 635                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 636                 POSTING_READ(GTIMR);
 637         }
 638         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 639
 640         return true;
 641 }
 642
 643 static void
 644 gen5_ring_put_irq(struct intel_ring_buffer *ring)
 645 {
 646         struct drm_device *dev = ring->dev;
 647         drm_i915_private_t *dev_priv = dev->dev_private;
 648         unsigned long flags;
 649
 650         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 651         if (--ring->irq_refcount == 0) {
 652                 dev_priv->gt_irq_mask |= ring->irq_enable_mask;
 653                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 654                 POSTING_READ(GTIMR);
 655         }
 656         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 657 }
 658
 659 static bool
 660 i9xx_ring_get_irq(struct intel_ring_buffer *ring)
 661 {
 662         struct drm_device *dev = ring->dev;
 663         drm_i915_private_t *dev_priv = dev->dev_private;
 664         unsigned long flags;
 665
 666         if (!dev->irq_enabled)
 667                 return false;
 668
 669         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 670         if (ring->irq_refcount++ == 0) {
 671                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
 672                 I915_WRITE(IMR, dev_priv->irq_mask);
 673                 POSTING_READ(IMR);
 674         }
 675         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 676
 677         return true;
 678 }
 679
 680 static void
 681 i9xx_ring_put_irq(struct intel_ring_buffer *ring)
 682 {
 683         struct drm_device *dev = ring->dev;
 684         drm_i915_private_t *dev_priv = dev->dev_private;
 685         unsigned long flags;
 686
 687         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 688         if (--ring->irq_refcount == 0) {
 689                 dev_priv->irq_mask |= ring->irq_enable_mask;
 690                 I915_WRITE(IMR, dev_priv->irq_mask);
 691                 POSTING_READ(IMR);
 692         }
 693         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 694 }
 695
 696 static bool
 697 i8xx_ring_get_irq(struct intel_ring_buffer *ring)
 698 {
 699         struct drm_device *dev = ring->dev;
 700         drm_i915_private_t *dev_priv = dev->dev_private;
 701         unsigned long flags;
 702
 703         if (!dev->irq_enabled)
 704                 return false;
 705
 706         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 707         if (ring->irq_refcount++ == 0) {
 708                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
 709                 I915_WRITE16(IMR, dev_priv->irq_mask);
 710                 POSTING_READ16(IMR);
 711         }
 712         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 713
 714         return true;
 715 }
 716
 717 static void
 718 i8xx_ring_put_irq(struct intel_ring_buffer *ring)
 719 {
 720         struct drm_device *dev = ring->dev;
 721         drm_i915_private_t *dev_priv = dev->dev_private;
 722         unsigned long flags;
 723
 724         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 725         if (--ring->irq_refcount == 0) {
 726                 dev_priv->irq_mask |= ring->irq_enable_mask;
 727                 I915_WRITE16(IMR, dev_priv->irq_mask);
 728                 POSTING_READ16(IMR);
 729         }
 730         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 731 }
 732
 733 void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
 734 {
 735         struct drm_device *dev = ring->dev;
 736         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 737         u32 mmio = 0;
 738
 739         /* The ring status page addresses are no longer next to the rest of
 740          * the ring registers as of gen7.
 741          */
 742         if (IS_GEN7(dev)) {
 743                 switch (ring->id) {
 744                 case RCS:
 745                         mmio = RENDER_HWS_PGA_GEN7;
 746                         break;
 747                 case BCS:
 748                         mmio = BLT_HWS_PGA_GEN7;
 749                         break;
 750                 case VCS:
 751                         mmio = BSD_HWS_PGA_GEN7;
 752                         break;
 753                 }
 754         } else if (IS_GEN6(ring->dev)) {
 755                 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
 756         } else {
 757                 mmio = RING_HWS_PGA(ring->mmio_base);
 758         }
 759
 760         I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
 761         POSTING_READ(mmio);
 762 }
 763
 764 static int
 765 bsd_ring_flush(struct intel_ring_buffer *ring,
 766                u32     invalidate_domains,
 767                u32     flush_domains)
 768 {
 769         int ret;
 770
 771         ret = intel_ring_begin(ring, 2);
 772         if (ret)
 773                 return ret;
 774
 775         intel_ring_emit(ring, MI_FLUSH);
 776         intel_ring_emit(ring, MI_NOOP);
 777         intel_ring_advance(ring);
 778         return 0;
 779 }
 780
 781 static int
 782 i9xx_add_request(struct intel_ring_buffer *ring,
 783                  u32 *result)
 784 {
 785         u32 seqno;
 786         int ret;
 787
 788         ret = intel_ring_begin(ring, 4);
 789         if (ret)
 790                 return ret;
 791
 792         seqno = i915_gem_next_request_seqno(ring);
 793
 794         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
 795         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 796         intel_ring_emit(ring, seqno);
 797         intel_ring_emit(ring, MI_USER_INTERRUPT);
 798         intel_ring_advance(ring);
 799
 800         *result = seqno;
 801         return 0;
 802 }
 803
 804 static bool
 805 gen6_ring_get_irq(struct intel_ring_buffer *ring)
 806 {
 807         struct drm_device *dev = ring->dev;
 808         drm_i915_private_t *dev_priv = dev->dev_private;
 809         unsigned long flags;
 810
 811         if (!dev->irq_enabled)
 812                return false;
 813
 814         /* It looks like we need to prevent the gt from suspending while waiting
 815          * for an notifiy irq, otherwise irqs seem to get lost on at least the
 816          * blt/bsd rings on ivb. */
 817         gen6_gt_force_wake_get(dev_priv);
 818
 819         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 820         if (ring->irq_refcount++ == 0) {
 821                 if (IS_IVYBRIDGE(dev) && ring->id == RCS)
 822                         I915_WRITE_IMR(ring, ~(ring->irq_enable_mask |
 823                                                 GEN6_RENDER_L3_PARITY_ERROR));
 824                 else
 825                         I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
 826                 dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
 827                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 828                 POSTING_READ(GTIMR);
 829         }
 830         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 831
 832         return true;
 833 }
 834
 835 static void
 836 gen6_ring_put_irq(struct intel_ring_buffer *ring)
 837 {
 838         struct drm_device *dev = ring->dev;
 839         drm_i915_private_t *dev_priv = dev->dev_private;
 840         unsigned long flags;
 841
 842         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 843         if (--ring->irq_refcount == 0) {
 844                 if (IS_IVYBRIDGE(dev) && ring->id == RCS)
 845                         I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR);
 846                 else
 847                         I915_WRITE_IMR(ring, ~0);
 848                 dev_priv->gt_irq_mask |= ring->irq_enable_mask;
 849                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 850                 POSTING_READ(GTIMR);
 851         }
 852         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 853
 854         gen6_gt_force_wake_put(dev_priv);
 855 }
 856
 857 static int
 858 i965_dispatch_execbuffer(struct intel_ring_buffer *ring, u32 offset, u32 length)
 859 {
 860         int ret;
 861
 862         ret = intel_ring_begin(ring, 2);
 863         if (ret)
 864                 return ret;
 865
 866         intel_ring_emit(ring,
 867                         MI_BATCH_BUFFER_START |
 868                         MI_BATCH_GTT |
 869                         MI_BATCH_NON_SECURE_I965);
 870         intel_ring_emit(ring, offset);
 871         intel_ring_advance(ring);
 872
 873         return 0;
 874 }
 875
 876 static int
 877 i830_dispatch_execbuffer(struct intel_ring_buffer *ring,
 878                                 u32 offset, u32 len)
 879 {
 880         int ret;
 881
 882         ret = intel_ring_begin(ring, 4);
 883         if (ret)
 884                 return ret;
 885
 886         intel_ring_emit(ring, MI_BATCH_BUFFER);
 887         intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
 888         intel_ring_emit(ring, offset + len - 8);
 889         intel_ring_emit(ring, 0);
 890         intel_ring_advance(ring);
 891
 892         return 0;
 893 }
 894
 895 static int
 896 i915_dispatch_execbuffer(struct intel_ring_buffer *ring,
 897                                 u32 offset, u32 len)
 898 {
 899         int ret;
 900
 901         ret = intel_ring_begin(ring, 2);
 902         if (ret)
 903                 return ret;
 904
 905         intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
 906         intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
 907         intel_ring_advance(ring);
 908
 909         return 0;
 910 }
 911
 912 static void cleanup_status_page(struct intel_ring_buffer *ring)
 913 {
 914         struct drm_i915_gem_object *obj;
 915
 916         obj = ring->status_page.obj;
 917         if (obj == NULL)
 918                 return;
 919
 920         kunmap(obj->pages[0]);
 921         i915_gem_object_unpin(obj);
 922         drm_gem_object_unreference(&obj->base);
 923         ring->status_page.obj = NULL;
 924 }
 925
 926 static int init_status_page(struct intel_ring_buffer *ring)
 927 {
 928         struct drm_device *dev = ring->dev;
 929         struct drm_i915_gem_object *obj;
 930         int ret;
 931
 932         obj = i915_gem_alloc_object(dev, 4096);
 933         if (obj == NULL) {
 934                 DRM_ERROR("Failed to allocate status page\n");
 935                 ret = -ENOMEM;
 936                 goto err;
 937         }
 938
 939         i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
 940
 941         ret = i915_gem_object_pin(obj, 4096, true);
 942         if (ret != 0) {
 943                 goto err_unref;
 944         }
 945
 946         ring->status_page.gfx_addr = obj->gtt_offset;
 947         ring->status_page.page_addr = kmap(obj->pages[0]);
 948         if (ring->status_page.page_addr == NULL) {
 949                 goto err_unpin;
 950         }
 951         ring->status_page.obj = obj;
 952         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
 953
 954         intel_ring_setup_status_page(ring);
 955         DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
 956                         ring->name, ring->status_page.gfx_addr);
 957
 958         return 0;
 959
 960 err_unpin:
 961         i915_gem_object_unpin(obj);
 962 err_unref:
 963         drm_gem_object_unreference(&obj->base);
 964 err:
 965         return ret;
 966 }
 967
 968 static int intel_init_ring_buffer(struct drm_device *dev,
 969                                   struct intel_ring_buffer *ring)
 970 {
 971         struct drm_i915_gem_object *obj;
 972         struct drm_i915_private *dev_priv = dev->dev_private;
 973         int ret;
 974
 975         ring->dev = dev;
 976         INIT_LIST_HEAD(&ring->active_list);
 977         INIT_LIST_HEAD(&ring->request_list);
 978         INIT_LIST_HEAD(&ring->gpu_write_list);
 979         ring->size = 32 * PAGE_SIZE;
 980
 981         init_waitqueue_head(&ring->irq_queue);
 982
 983         if (I915_NEED_GFX_HWS(dev)) {
 984                 ret = init_status_page(ring);
 985                 if (ret)
 986                         return ret;
 987         }
 988
 989         obj = i915_gem_alloc_object(dev, ring->size);
 990         if (obj == NULL) {
 991                 DRM_ERROR("Failed to allocate ringbuffer\n");
 992                 ret = -ENOMEM;
 993                 goto err_hws;
 994         }
 995
 996         ring->obj = obj;
 997
 998         ret = i915_gem_object_pin(obj, PAGE_SIZE, true);
 999         if (ret)
1000                 goto err_unref;
1001
1002         ring->virtual_start =
1003                 ioremap_wc(dev_priv->mm.gtt->gma_bus_addr + obj->gtt_offset,
1004                            ring->size);
1005         if (ring->virtual_start == NULL) {
1006                 DRM_ERROR("Failed to map ringbuffer.\n");
1007                 ret = -EINVAL;
1008                 goto err_unpin;
1009         }
1010
1011         ret = ring->init(ring);
1012         if (ret)
1013                 goto err_unmap;
1014
1015         /* Workaround an erratum on the i830 which causes a hang if
1016          * the TAIL pointer points to within the last 2 cachelines
1017          * of the buffer.
1018          */
1019         ring->effective_size = ring->size;
1020         if (IS_I830(ring->dev) || IS_845G(ring->dev))
1021                 ring->effective_size -= 128;
1022
1023         return 0;
1024
1025 err_unmap:
1026         iounmap(ring->virtual_start);
1027 err_unpin:
1028         i915_gem_object_unpin(obj);
1029 err_unref:
1030         drm_gem_object_unreference(&obj->base);
1031         ring->obj = NULL;
1032 err_hws:
1033         cleanup_status_page(ring);
1034         return ret;
1035 }
1036
1037 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
1038 {
1039         struct drm_i915_private *dev_priv;
1040         int ret;
1041
1042         if (ring->obj == NULL)
1043                 return;
1044
1045         /* Disable the ring buffer. The ring must be idle at this point */
1046         dev_priv = ring->dev->dev_private;
1047         ret = intel_wait_ring_idle(ring);
1048         if (ret)
1049                 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1050                           ring->name, ret);
1051
1052         I915_WRITE_CTL(ring, 0);
1053
1054         iounmap(ring->virtual_start);
1055
1056         i915_gem_object_unpin(ring->obj);
1057         drm_gem_object_unreference(&ring->obj->base);
1058         ring->obj = NULL;
1059
1060         if (ring->cleanup)
1061                 ring->cleanup(ring);
1062
1063         cleanup_status_page(ring);
1064 }
1065
1066 static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
1067 {
1068         uint32_t __iomem *virt;
1069         int rem = ring->size - ring->tail;
1070
1071         if (ring->space < rem) {
1072                 int ret = intel_wait_ring_buffer(ring, rem);
1073                 if (ret)
1074                         return ret;
1075         }
1076
1077         virt = ring->virtual_start + ring->tail;
1078         rem /= 4;
1079         while (rem--)
1080                 iowrite32(MI_NOOP, virt++);
1081
1082         ring->tail = 0;
1083         ring->space = ring_space(ring);
1084
1085         return 0;
1086 }
1087
1088 static int intel_ring_wait_seqno(struct intel_ring_buffer *ring, u32 seqno)
1089 {
1090         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1091         bool was_interruptible;
1092         int ret;
1093
1094         /* XXX As we have not yet audited all the paths to check that
1095          * they are ready for ERESTARTSYS from intel_ring_begin, do not
1096          * allow us to be interruptible by a signal.
1097          */
1098         was_interruptible = dev_priv->mm.interruptible;
1099         dev_priv->mm.interruptible = false;
1100
1101         ret = i915_wait_seqno(ring, seqno);
1102
1103         dev_priv->mm.interruptible = was_interruptible;
1104         if (!ret)
1105                 i915_gem_retire_requests_ring(ring);
1106
1107         return ret;
1108 }
1109
1110 static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n)
1111 {
1112         struct drm_i915_gem_request *request;
1113         u32 seqno = 0;
1114         int ret;
1115
1116         i915_gem_retire_requests_ring(ring);
1117
1118         if (ring->last_retired_head != -1) {
1119                 ring->head = ring->last_retired_head;
1120                 ring->last_retired_head = -1;
1121                 ring->space = ring_space(ring);
1122                 if (ring->space >= n)
1123                         return 0;
1124         }
1125
1126         list_for_each_entry(request, &ring->request_list, list) {
1127                 int space;
1128
1129                 if (request->tail == -1)
1130                         continue;
1131
1132                 space = request->tail - (ring->tail + 8);
1133                 if (space < 0)
1134                         space += ring->size;
1135                 if (space >= n) {
1136                         seqno = request->seqno;
1137                         break;
1138                 }
1139
1140                 /* Consume this request in case we need more space than
1141                  * is available and so need to prevent a race between
1142                  * updating last_retired_head and direct reads of
1143                  * I915_RING_HEAD. It also provides a nice sanity check.
1144                  */
1145                 request->tail = -1;
1146         }
1147
1148         if (seqno == 0)
1149                 return -ENOSPC;
1150
1151         ret = intel_ring_wait_seqno(ring, seqno);
1152         if (ret)
1153                 return ret;
1154
1155         if (WARN_ON(ring->last_retired_head == -1))
1156                 return -ENOSPC;
1157
1158         ring->head = ring->last_retired_head;
1159         ring->last_retired_head = -1;
1160         ring->space = ring_space(ring);
1161         if (WARN_ON(ring->space < n))
1162                 return -ENOSPC;
1163
1164         return 0;
1165 }
1166
1167 int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n)
1168 {
1169         struct drm_device *dev = ring->dev;
1170         struct drm_i915_private *dev_priv = dev->dev_private;
1171         unsigned long end;
1172         int ret;
1173
1174         ret = intel_ring_wait_request(ring, n);
1175         if (ret != -ENOSPC)
1176                 return ret;
1177
1178         trace_i915_ring_wait_begin(ring);
1179         /* With GEM the hangcheck timer should kick us out of the loop,
1180          * leaving it early runs the risk of corrupting GEM state (due
1181          * to running on almost untested codepaths). But on resume
1182          * timers don't work yet, so prevent a complete hang in that
1183          * case by choosing an insanely large timeout. */
1184         end = jiffies + 60 * HZ;
1185
1186         do {
1187                 ring->head = I915_READ_HEAD(ring);
1188                 ring->space = ring_space(ring);
1189                 if (ring->space >= n) {
1190                         trace_i915_ring_wait_end(ring);
1191                         return 0;
1192                 }
1193
1194                 if (dev->primary->master) {
1195                         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1196                         if (master_priv->sarea_priv)
1197                                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1198                 }
1199
1200                 msleep(1);
1201                 if (atomic_read(&dev_priv->mm.wedged))
1202                         return -EAGAIN;
1203         } while (!time_after(jiffies, end));
1204         trace_i915_ring_wait_end(ring);
1205         return -EBUSY;
1206 }
1207
1208 int intel_ring_begin(struct intel_ring_buffer *ring,
1209                      int num_dwords)
1210 {
1211         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1212         int n = 4*num_dwords;
1213         int ret;
1214
1215         if (unlikely(atomic_read(&dev_priv->mm.wedged)))
1216                 return -EIO;
1217
1218         if (unlikely(ring->tail + n > ring->effective_size)) {
1219                 ret = intel_wrap_ring_buffer(ring);
1220                 if (unlikely(ret))
1221                         return ret;
1222         }
1223
1224         if (unlikely(ring->space < n)) {
1225                 ret = intel_wait_ring_buffer(ring, n);
1226                 if (unlikely(ret))
1227                         return ret;
1228         }
1229
1230         ring->space -= n;
1231         return 0;
1232 }
1233
1234 void intel_ring_advance(struct intel_ring_buffer *ring)
1235 {
1236         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1237
1238         ring->tail &= ring->size - 1;
1239         if (dev_priv->stop_rings & intel_ring_flag(ring))
1240                 return;
1241         ring->write_tail(ring, ring->tail);
1242 }
1243
1244
1245 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
1246                                      u32 value)
1247 {
1248         drm_i915_private_t *dev_priv = ring->dev->dev_private;
1249
1250        /* Every tail move must follow the sequence below */
1251         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1252                 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
1253                 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE);
1254         I915_WRITE(GEN6_BSD_RNCID, 0x0);
1255
1256         if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
1257                 GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR) == 0,
1258                 50))
1259         DRM_ERROR("timed out waiting for IDLE Indicator\n");
1260
1261         I915_WRITE_TAIL(ring, value);
1262         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1263                 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
1264                 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE);
1265 }
1266
1267 static int gen6_ring_flush(struct intel_ring_buffer *ring,
1268                            u32 invalidate, u32 flush)
1269 {
1270         uint32_t cmd;
1271         int ret;
1272
1273         ret = intel_ring_begin(ring, 4);
1274         if (ret)
1275                 return ret;
1276
1277         cmd = MI_FLUSH_DW;
1278         if (invalidate & I915_GEM_GPU_DOMAINS)
1279                 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
1280         intel_ring_emit(ring, cmd);
1281         intel_ring_emit(ring, 0);
1282         intel_ring_emit(ring, 0);
1283         intel_ring_emit(ring, MI_NOOP);
1284         intel_ring_advance(ring);
1285         return 0;
1286 }
1287
1288 static int
1289 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1290                               u32 offset, u32 len)
1291 {
1292         int ret;
1293
1294         ret = intel_ring_begin(ring, 2);
1295         if (ret)
1296                 return ret;
1297
1298         intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965);
1299         /* bit0-7 is the length on GEN6+ */
1300         intel_ring_emit(ring, offset);
1301         intel_ring_advance(ring);
1302
1303         return 0;
1304 }
1305
1306 /* Blitter support (SandyBridge+) */
1307
1308 static int blt_ring_flush(struct intel_ring_buffer *ring,
1309                           u32 invalidate, u32 flush)
1310 {
1311         uint32_t cmd;
1312         int ret;
1313
1314         ret = intel_ring_begin(ring, 4);
1315         if (ret)
1316                 return ret;
1317
1318         cmd = MI_FLUSH_DW;
1319         if (invalidate & I915_GEM_DOMAIN_RENDER)
1320                 cmd |= MI_INVALIDATE_TLB;
1321         intel_ring_emit(ring, cmd);
1322         intel_ring_emit(ring, 0);
1323         intel_ring_emit(ring, 0);
1324         intel_ring_emit(ring, MI_NOOP);
1325         intel_ring_advance(ring);
1326         return 0;
1327 }
1328
1329 int intel_init_render_ring_buffer(struct drm_device *dev)
1330 {
1331         drm_i915_private_t *dev_priv = dev->dev_private;
1332         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1333
1334         ring->name = "render ring";
1335         ring->id = RCS;
1336         ring->mmio_base = RENDER_RING_BASE;
1337
1338         if (INTEL_INFO(dev)->gen >= 6) {
1339                 ring->add_request = gen6_add_request;
1340                 ring->flush = gen6_render_ring_flush;
1341                 ring->irq_get = gen6_ring_get_irq;
1342                 ring->irq_put = gen6_ring_put_irq;
1343                 ring->irq_enable_mask = GT_USER_INTERRUPT;
1344                 ring->get_seqno = gen6_ring_get_seqno;
1345                 ring->sync_to = gen6_ring_sync;
1346                 ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_INVALID;
1347                 ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_RV;
1348                 ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_RB;
1349                 ring->signal_mbox[0] = GEN6_VRSYNC;
1350                 ring->signal_mbox[1] = GEN6_BRSYNC;
1351         } else if (IS_GEN5(dev)) {
1352                 ring->add_request = pc_render_add_request;
1353                 ring->flush = gen4_render_ring_flush;
1354                 ring->get_seqno = pc_render_get_seqno;
1355                 ring->irq_get = gen5_ring_get_irq;
1356                 ring->irq_put = gen5_ring_put_irq;
1357                 ring->irq_enable_mask = GT_USER_INTERRUPT | GT_PIPE_NOTIFY;
1358         } else {
1359                 ring->add_request = i9xx_add_request;
1360                 if (INTEL_INFO(dev)->gen < 4)
1361                         ring->flush = gen2_render_ring_flush;
1362                 else
1363                         ring->flush = gen4_render_ring_flush;
1364                 ring->get_seqno = ring_get_seqno;
1365                 if (IS_GEN2(dev)) {
1366                         ring->irq_get = i8xx_ring_get_irq;
1367                         ring->irq_put = i8xx_ring_put_irq;
1368                 } else {
1369                         ring->irq_get = i9xx_ring_get_irq;
1370                         ring->irq_put = i9xx_ring_put_irq;
1371                 }
1372                 ring->irq_enable_mask = I915_USER_INTERRUPT;
1373         }
1374         ring->write_tail = ring_write_tail;
1375         if (INTEL_INFO(dev)->gen >= 6)
1376                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1377         else if (INTEL_INFO(dev)->gen >= 4)
1378                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1379         else if (IS_I830(dev) || IS_845G(dev))
1380                 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1381         else
1382                 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1383         ring->init = init_render_ring;
1384         ring->cleanup = render_ring_cleanup;
1385
1386
1387         if (!I915_NEED_GFX_HWS(dev)) {
1388                 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1389                 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1390         }
1391
1392         return intel_init_ring_buffer(dev, ring);
1393 }
1394
1395 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
1396 {
1397         drm_i915_private_t *dev_priv = dev->dev_private;
1398         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1399
1400         ring->name = "render ring";
1401         ring->id = RCS;
1402         ring->mmio_base = RENDER_RING_BASE;
1403
1404         if (INTEL_INFO(dev)->gen >= 6) {
1405                 /* non-kms not supported on gen6+ */
1406                 return -ENODEV;
1407         }
1408
1409         /* Note: gem is not supported on gen5/ilk without kms (the corresponding
1410          * gem_init ioctl returns with -ENODEV). Hence we do not need to set up
1411          * the special gen5 functions. */
1412         ring->add_request = i9xx_add_request;
1413         if (INTEL_INFO(dev)->gen < 4)
1414                 ring->flush = gen2_render_ring_flush;
1415         else
1416                 ring->flush = gen4_render_ring_flush;
1417         ring->get_seqno = ring_get_seqno;
1418         if (IS_GEN2(dev)) {
1419                 ring->irq_get = i8xx_ring_get_irq;
1420                 ring->irq_put = i8xx_ring_put_irq;
1421         } else {
1422                 ring->irq_get = i9xx_ring_get_irq;
1423                 ring->irq_put = i9xx_ring_put_irq;
1424         }
1425         ring->irq_enable_mask = I915_USER_INTERRUPT;
1426         ring->write_tail = ring_write_tail;
1427         if (INTEL_INFO(dev)->gen >= 4)
1428                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1429         else if (IS_I830(dev) || IS_845G(dev))
1430                 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1431         else
1432                 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1433         ring->init = init_render_ring;
1434         ring->cleanup = render_ring_cleanup;
1435
1436         if (!I915_NEED_GFX_HWS(dev))
1437                 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1438
1439         ring->dev = dev;
1440         INIT_LIST_HEAD(&ring->active_list);
1441         INIT_LIST_HEAD(&ring->request_list);
1442         INIT_LIST_HEAD(&ring->gpu_write_list);
1443
1444         ring->size = size;
1445         ring->effective_size = ring->size;
1446         if (IS_I830(ring->dev))
1447                 ring->effective_size -= 128;
1448
1449         ring->virtual_start = ioremap_wc(start, size);
1450         if (ring->virtual_start == NULL) {
1451                 DRM_ERROR("can not ioremap virtual address for"
1452                           " ring buffer\n");
1453                 return -ENOMEM;
1454         }
1455
1456         return 0;
1457 }
1458
1459 int intel_init_bsd_ring_buffer(struct drm_device *dev)
1460 {
1461         drm_i915_private_t *dev_priv = dev->dev_private;
1462         struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
1463
1464         ring->name = "bsd ring";
1465         ring->id = VCS;
1466
1467         ring->write_tail = ring_write_tail;
1468         if (IS_GEN6(dev) || IS_GEN7(dev)) {
1469                 ring->mmio_base = GEN6_BSD_RING_BASE;
1470                 /* gen6 bsd needs a special wa for tail updates */
1471                 if (IS_GEN6(dev))
1472                         ring->write_tail = gen6_bsd_ring_write_tail;
1473                 ring->flush = gen6_ring_flush;
1474                 ring->add_request = gen6_add_request;
1475                 ring->get_seqno = gen6_ring_get_seqno;
1476                 ring->irq_enable_mask = GEN6_BSD_USER_INTERRUPT;
1477                 ring->irq_get = gen6_ring_get_irq;
1478                 ring->irq_put = gen6_ring_put_irq;
1479                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1480                 ring->sync_to = gen6_ring_sync;
1481                 ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_VR;
1482                 ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_INVALID;
1483                 ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_VB;
1484                 ring->signal_mbox[0] = GEN6_RVSYNC;
1485                 ring->signal_mbox[1] = GEN6_BVSYNC;
1486         } else {
1487                 ring->mmio_base = BSD_RING_BASE;
1488                 ring->flush = bsd_ring_flush;
1489                 ring->add_request = i9xx_add_request;
1490                 ring->get_seqno = ring_get_seqno;
1491                 if (IS_GEN5(dev)) {
1492                         ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
1493                         ring->irq_get = gen5_ring_get_irq;
1494                         ring->irq_put = gen5_ring_put_irq;
1495                 } else {
1496                         ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
1497                         ring->irq_get = i9xx_ring_get_irq;
1498                         ring->irq_put = i9xx_ring_put_irq;
1499                 }
1500                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1501         }
1502         ring->init = init_ring_common;
1503
1504
1505         return intel_init_ring_buffer(dev, ring);
1506 }
1507
1508 int intel_init_blt_ring_buffer(struct drm_device *dev)
1509 {
1510         drm_i915_private_t *dev_priv = dev->dev_private;
1511         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
1512
1513         ring->name = "blitter ring";
1514         ring->id = BCS;
1515
1516         ring->mmio_base = BLT_RING_BASE;
1517         ring->write_tail = ring_write_tail;
1518         ring->flush = blt_ring_flush;
1519         ring->add_request = gen6_add_request;
1520         ring->get_seqno = gen6_ring_get_seqno;
1521         ring->irq_enable_mask = GEN6_BLITTER_USER_INTERRUPT;
1522         ring->irq_get = gen6_ring_get_irq;
1523         ring->irq_put = gen6_ring_put_irq;
1524         ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1525         ring->sync_to = gen6_ring_sync;
1526         ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_BR;
1527         ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_BV;
1528         ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_INVALID;
1529         ring->signal_mbox[0] = GEN6_RBSYNC;
1530         ring->signal_mbox[1] = GEN6_VBSYNC;
1531         ring->init = init_ring_common;
1532
1533         return intel_init_ring_buffer(dev, ring);
1534 }