Pileus Git - ~andy/linux/blob - drivers/gpu/drm/i915/intel_ringbuffer.c

   1 /*
   2  * Copyright © 2008-2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Zou Nan hai <nanhai.zou@intel.com>
  26  *    Xiang Hai hao<haihao.xiang@intel.com>
  27  *
  28  */
  29
  30 #include <drm/drmP.h>
  31 #include "i915_drv.h"
  32 #include <drm/i915_drm.h>
  33 #include "i915_trace.h"
  34 #include "intel_drv.h"
  35
  36 /*
  37  * 965+ support PIPE_CONTROL commands, which provide finer grained control
  38  * over cache flushing.
  39  */
  40 struct pipe_control {
  41         struct drm_i915_gem_object *obj;
  42         volatile u32 *cpu_page;
  43         u32 gtt_offset;
  44 };
  45
  46 static inline int ring_space(struct intel_ring_buffer *ring)
  47 {
  48         int space = (ring->head & HEAD_ADDR) - (ring->tail + I915_RING_FREE_SPACE);
  49         if (space < 0)
  50                 space += ring->size;
  51         return space;
  52 }
  53
  54 static int
  55 gen2_render_ring_flush(struct intel_ring_buffer *ring,
  56                        u32      invalidate_domains,
  57                        u32      flush_domains)
  58 {
  59         u32 cmd;
  60         int ret;
  61
  62         cmd = MI_FLUSH;
  63         if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
  64                 cmd |= MI_NO_WRITE_FLUSH;
  65
  66         if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
  67                 cmd |= MI_READ_FLUSH;
  68
  69         ret = intel_ring_begin(ring, 2);
  70         if (ret)
  71                 return ret;
  72
  73         intel_ring_emit(ring, cmd);
  74         intel_ring_emit(ring, MI_NOOP);
  75         intel_ring_advance(ring);
  76
  77         return 0;
  78 }
  79
  80 static int
  81 gen4_render_ring_flush(struct intel_ring_buffer *ring,
  82                        u32      invalidate_domains,
  83                        u32      flush_domains)
  84 {
  85         struct drm_device *dev = ring->dev;
  86         u32 cmd;
  87         int ret;
  88
  89         /*
  90          * read/write caches:
  91          *
  92          * I915_GEM_DOMAIN_RENDER is always invalidated, but is
  93          * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
  94          * also flushed at 2d versus 3d pipeline switches.
  95          *
  96          * read-only caches:
  97          *
  98          * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
  99          * MI_READ_FLUSH is set, and is always flushed on 965.
 100          *
 101          * I915_GEM_DOMAIN_COMMAND may not exist?
 102          *
 103          * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
 104          * invalidated when MI_EXE_FLUSH is set.
 105          *
 106          * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
 107          * invalidated with every MI_FLUSH.
 108          *
 109          * TLBs:
 110          *
 111          * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
 112          * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
 113          * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
 114          * are flushed at any MI_FLUSH.
 115          */
 116
 117         cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
 118         if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
 119                 cmd &= ~MI_NO_WRITE_FLUSH;
 120         if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
 121                 cmd |= MI_EXE_FLUSH;
 122
 123         if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
 124             (IS_G4X(dev) || IS_GEN5(dev)))
 125                 cmd |= MI_INVALIDATE_ISP;
 126
 127         ret = intel_ring_begin(ring, 2);
 128         if (ret)
 129                 return ret;
 130
 131         intel_ring_emit(ring, cmd);
 132         intel_ring_emit(ring, MI_NOOP);
 133         intel_ring_advance(ring);
 134
 135         return 0;
 136 }
 137
 138 /**
 139  * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
 140  * implementing two workarounds on gen6.  From section 1.4.7.1
 141  * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
 142  *
 143  * [DevSNB-C+{W/A}] Before any depth stall flush (including those
 144  * produced by non-pipelined state commands), software needs to first
 145  * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
 146  * 0.
 147  *
 148  * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
 149  * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
 150  *
 151  * And the workaround for these two requires this workaround first:
 152  *
 153  * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
 154  * BEFORE the pipe-control with a post-sync op and no write-cache
 155  * flushes.
 156  *
 157  * And this last workaround is tricky because of the requirements on
 158  * that bit.  From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
 159  * volume 2 part 1:
 160  *
 161  *     "1 of the following must also be set:
 162  *      - Render Target Cache Flush Enable ([12] of DW1)
 163  *      - Depth Cache Flush Enable ([0] of DW1)
 164  *      - Stall at Pixel Scoreboard ([1] of DW1)
 165  *      - Depth Stall ([13] of DW1)
 166  *      - Post-Sync Operation ([13] of DW1)
 167  *      - Notify Enable ([8] of DW1)"
 168  *
 169  * The cache flushes require the workaround flush that triggered this
 170  * one, so we can't use it.  Depth stall would trigger the same.
 171  * Post-sync nonzero is what triggered this second workaround, so we
 172  * can't use that one either.  Notify enable is IRQs, which aren't
 173  * really our business.  That leaves only stall at scoreboard.
 174  */
 175 static int
 176 intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring)
 177 {
 178         struct pipe_control *pc = ring->private;
 179         u32 scratch_addr = pc->gtt_offset + 128;
 180         int ret;
 181
 182
 183         ret = intel_ring_begin(ring, 6);
 184         if (ret)
 185                 return ret;
 186
 187         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 188         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 189                         PIPE_CONTROL_STALL_AT_SCOREBOARD);
 190         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 191         intel_ring_emit(ring, 0); /* low dword */
 192         intel_ring_emit(ring, 0); /* high dword */
 193         intel_ring_emit(ring, MI_NOOP);
 194         intel_ring_advance(ring);
 195
 196         ret = intel_ring_begin(ring, 6);
 197         if (ret)
 198                 return ret;
 199
 200         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 201         intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
 202         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 203         intel_ring_emit(ring, 0);
 204         intel_ring_emit(ring, 0);
 205         intel_ring_emit(ring, MI_NOOP);
 206         intel_ring_advance(ring);
 207
 208         return 0;
 209 }
 210
 211 static int
 212 gen6_render_ring_flush(struct intel_ring_buffer *ring,
 213                          u32 invalidate_domains, u32 flush_domains)
 214 {
 215         u32 flags = 0;
 216         struct pipe_control *pc = ring->private;
 217         u32 scratch_addr = pc->gtt_offset + 128;
 218         int ret;
 219
 220         /* Force SNB workarounds for PIPE_CONTROL flushes */
 221         ret = intel_emit_post_sync_nonzero_flush(ring);
 222         if (ret)
 223                 return ret;
 224
 225         /* Just flush everything.  Experiments have shown that reducing the
 226          * number of bits based on the write domains has little performance
 227          * impact.
 228          */
 229         if (flush_domains) {
 230                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 231                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 232                 /*
 233                  * Ensure that any following seqno writes only happen
 234                  * when the render cache is indeed flushed.
 235                  */
 236                 flags |= PIPE_CONTROL_CS_STALL;
 237         }
 238         if (invalidate_domains) {
 239                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 240                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 241                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 242                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 243                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 244                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 245                 /*
 246                  * TLB invalidate requires a post-sync write.
 247                  */
 248                 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
 249         }
 250
 251         ret = intel_ring_begin(ring, 4);
 252         if (ret)
 253                 return ret;
 254
 255         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 256         intel_ring_emit(ring, flags);
 257         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
 258         intel_ring_emit(ring, 0);
 259         intel_ring_advance(ring);
 260
 261         return 0;
 262 }
 263
 264 static int
 265 gen7_render_ring_cs_stall_wa(struct intel_ring_buffer *ring)
 266 {
 267         int ret;
 268
 269         ret = intel_ring_begin(ring, 4);
 270         if (ret)
 271                 return ret;
 272
 273         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 274         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 275                               PIPE_CONTROL_STALL_AT_SCOREBOARD);
 276         intel_ring_emit(ring, 0);
 277         intel_ring_emit(ring, 0);
 278         intel_ring_advance(ring);
 279
 280         return 0;
 281 }
 282
 283 static int gen7_ring_fbc_flush(struct intel_ring_buffer *ring, u32 value)
 284 {
 285         int ret;
 286
 287         if (!ring->fbc_dirty)
 288                 return 0;
 289
 290         ret = intel_ring_begin(ring, 4);
 291         if (ret)
 292                 return ret;
 293         intel_ring_emit(ring, MI_NOOP);
 294         /* WaFbcNukeOn3DBlt:ivb/hsw */
 295         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
 296         intel_ring_emit(ring, MSG_FBC_REND_STATE);
 297         intel_ring_emit(ring, value);
 298         intel_ring_advance(ring);
 299
 300         ring->fbc_dirty = false;
 301         return 0;
 302 }
 303
 304 static int
 305 gen7_render_ring_flush(struct intel_ring_buffer *ring,
 306                        u32 invalidate_domains, u32 flush_domains)
 307 {
 308         u32 flags = 0;
 309         struct pipe_control *pc = ring->private;
 310         u32 scratch_addr = pc->gtt_offset + 128;
 311         int ret;
 312
 313         /*
 314          * Ensure that any following seqno writes only happen when the render
 315          * cache is indeed flushed.
 316          *
 317          * Workaround: 4th PIPE_CONTROL command (except the ones with only
 318          * read-cache invalidate bits set) must have the CS_STALL bit set. We
 319          * don't try to be clever and just set it unconditionally.
 320          */
 321         flags |= PIPE_CONTROL_CS_STALL;
 322
 323         /* Just flush everything.  Experiments have shown that reducing the
 324          * number of bits based on the write domains has little performance
 325          * impact.
 326          */
 327         if (flush_domains) {
 328                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 329                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 330         }
 331         if (invalidate_domains) {
 332                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 333                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 334                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 335                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 336                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 337                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 338                 /*
 339                  * TLB invalidate requires a post-sync write.
 340                  */
 341                 flags |= PIPE_CONTROL_QW_WRITE;
 342                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 343
 344                 /* Workaround: we must issue a pipe_control with CS-stall bit
 345                  * set before a pipe_control command that has the state cache
 346                  * invalidate bit set. */
 347                 gen7_render_ring_cs_stall_wa(ring);
 348         }
 349
 350         ret = intel_ring_begin(ring, 4);
 351         if (ret)
 352                 return ret;
 353
 354         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 355         intel_ring_emit(ring, flags);
 356         intel_ring_emit(ring, scratch_addr);
 357         intel_ring_emit(ring, 0);
 358         intel_ring_advance(ring);
 359
 360         if (flush_domains)
 361                 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
 362
 363         return 0;
 364 }
 365
 366 static void ring_write_tail(struct intel_ring_buffer *ring,
 367                             u32 value)
 368 {
 369         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 370         I915_WRITE_TAIL(ring, value);
 371 }
 372
 373 u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
 374 {
 375         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 376         u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
 377                         RING_ACTHD(ring->mmio_base) : ACTHD;
 378
 379         return I915_READ(acthd_reg);
 380 }
 381
 382 static void ring_setup_phys_status_page(struct intel_ring_buffer *ring)
 383 {
 384         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 385         u32 addr;
 386
 387         addr = dev_priv->status_page_dmah->busaddr;
 388         if (INTEL_INFO(ring->dev)->gen >= 4)
 389                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
 390         I915_WRITE(HWS_PGA, addr);
 391 }
 392
 393 static int init_ring_common(struct intel_ring_buffer *ring)
 394 {
 395         struct drm_device *dev = ring->dev;
 396         drm_i915_private_t *dev_priv = dev->dev_private;
 397         struct drm_i915_gem_object *obj = ring->obj;
 398         int ret = 0;
 399         u32 head;
 400
 401         if (HAS_FORCE_WAKE(dev))
 402                 gen6_gt_force_wake_get(dev_priv);
 403
 404         if (I915_NEED_GFX_HWS(dev))
 405                 intel_ring_setup_status_page(ring);
 406         else
 407                 ring_setup_phys_status_page(ring);
 408
 409         /* Stop the ring if it's running. */
 410         I915_WRITE_CTL(ring, 0);
 411         I915_WRITE_HEAD(ring, 0);
 412         ring->write_tail(ring, 0);
 413
 414         head = I915_READ_HEAD(ring) & HEAD_ADDR;
 415
 416         /* G45 ring initialization fails to reset head to zero */
 417         if (head != 0) {
 418                 DRM_DEBUG_KMS("%s head not reset to zero "
 419                               "ctl %08x head %08x tail %08x start %08x\n",
 420                               ring->name,
 421                               I915_READ_CTL(ring),
 422                               I915_READ_HEAD(ring),
 423                               I915_READ_TAIL(ring),
 424                               I915_READ_START(ring));
 425
 426                 I915_WRITE_HEAD(ring, 0);
 427
 428                 if (I915_READ_HEAD(ring) & HEAD_ADDR) {
 429                         DRM_ERROR("failed to set %s head to zero "
 430                                   "ctl %08x head %08x tail %08x start %08x\n",
 431                                   ring->name,
 432                                   I915_READ_CTL(ring),
 433                                   I915_READ_HEAD(ring),
 434                                   I915_READ_TAIL(ring),
 435                                   I915_READ_START(ring));
 436                 }
 437         }
 438
 439         /* Initialize the ring. This must happen _after_ we've cleared the ring
 440          * registers with the above sequence (the readback of the HEAD registers
 441          * also enforces ordering), otherwise the hw might lose the new ring
 442          * register values. */
 443         I915_WRITE_START(ring, obj->gtt_offset);
 444         I915_WRITE_CTL(ring,
 445                         ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
 446                         | RING_VALID);
 447
 448         /* If the head is still not zero, the ring is dead */
 449         if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
 450                      I915_READ_START(ring) == obj->gtt_offset &&
 451                      (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
 452                 DRM_ERROR("%s initialization failed "
 453                                 "ctl %08x head %08x tail %08x start %08x\n",
 454                                 ring->name,
 455                                 I915_READ_CTL(ring),
 456                                 I915_READ_HEAD(ring),
 457                                 I915_READ_TAIL(ring),
 458                                 I915_READ_START(ring));
 459                 ret = -EIO;
 460                 goto out;
 461         }
 462
 463         if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
 464                 i915_kernel_lost_context(ring->dev);
 465         else {
 466                 ring->head = I915_READ_HEAD(ring);
 467                 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 468                 ring->space = ring_space(ring);
 469                 ring->last_retired_head = -1;
 470         }
 471
 472         memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
 473
 474 out:
 475         if (HAS_FORCE_WAKE(dev))
 476                 gen6_gt_force_wake_put(dev_priv);
 477
 478         return ret;
 479 }
 480
 481 static int
 482 init_pipe_control(struct intel_ring_buffer *ring)
 483 {
 484         struct pipe_control *pc;
 485         struct drm_i915_gem_object *obj;
 486         int ret;
 487
 488         if (ring->private)
 489                 return 0;
 490
 491         pc = kmalloc(sizeof(*pc), GFP_KERNEL);
 492         if (!pc)
 493                 return -ENOMEM;
 494
 495         obj = i915_gem_alloc_object(ring->dev, 4096);
 496         if (obj == NULL) {
 497                 DRM_ERROR("Failed to allocate seqno page\n");
 498                 ret = -ENOMEM;
 499                 goto err;
 500         }
 501
 502         i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
 503
 504         ret = i915_gem_object_pin(obj, 4096, true, false);
 505         if (ret)
 506                 goto err_unref;
 507
 508         pc->gtt_offset = obj->gtt_offset;
 509         pc->cpu_page = kmap(sg_page(obj->pages->sgl));
 510         if (pc->cpu_page == NULL) {
 511                 ret = -ENOMEM;
 512                 goto err_unpin;
 513         }
 514
 515         DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
 516                          ring->name, pc->gtt_offset);
 517
 518         pc->obj = obj;
 519         ring->private = pc;
 520         return 0;
 521
 522 err_unpin:
 523         i915_gem_object_unpin(obj);
 524 err_unref:
 525         drm_gem_object_unreference(&obj->base);
 526 err:
 527         kfree(pc);
 528         return ret;
 529 }
 530
 531 static void
 532 cleanup_pipe_control(struct intel_ring_buffer *ring)
 533 {
 534         struct pipe_control *pc = ring->private;
 535         struct drm_i915_gem_object *obj;
 536
 537         if (!ring->private)
 538                 return;
 539
 540         obj = pc->obj;
 541
 542         kunmap(sg_page(obj->pages->sgl));
 543         i915_gem_object_unpin(obj);
 544         drm_gem_object_unreference(&obj->base);
 545
 546         kfree(pc);
 547         ring->private = NULL;
 548 }
 549
 550 static int init_render_ring(struct intel_ring_buffer *ring)
 551 {
 552         struct drm_device *dev = ring->dev;
 553         struct drm_i915_private *dev_priv = dev->dev_private;
 554         int ret = init_ring_common(ring);
 555
 556         if (INTEL_INFO(dev)->gen > 3)
 557                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
 558
 559         /* We need to disable the AsyncFlip performance optimisations in order
 560          * to use MI_WAIT_FOR_EVENT within the CS. It should already be
 561          * programmed to '1' on all products.
 562          *
 563          * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
 564          */
 565         if (INTEL_INFO(dev)->gen >= 6)
 566                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
 567
 568         /* Required for the hardware to program scanline values for waiting */
 569         if (INTEL_INFO(dev)->gen == 6)
 570                 I915_WRITE(GFX_MODE,
 571                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_ALWAYS));
 572
 573         if (IS_GEN7(dev))
 574                 I915_WRITE(GFX_MODE_GEN7,
 575                            _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
 576                            _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
 577
 578         if (INTEL_INFO(dev)->gen >= 5) {
 579                 ret = init_pipe_control(ring);
 580                 if (ret)
 581                         return ret;
 582         }
 583
 584         if (IS_GEN6(dev)) {
 585                 /* From the Sandybridge PRM, volume 1 part 3, page 24:
 586                  * "If this bit is set, STCunit will have LRA as replacement
 587                  *  policy. [...] This bit must be reset.  LRA replacement
 588                  *  policy is not supported."
 589                  */
 590                 I915_WRITE(CACHE_MODE_0,
 591                            _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
 592
 593                 /* This is not explicitly set for GEN6, so read the register.
 594                  * see intel_ring_mi_set_context() for why we care.
 595                  * TODO: consider explicitly setting the bit for GEN5
 596                  */
 597                 ring->itlb_before_ctx_switch =
 598                         !!(I915_READ(GFX_MODE) & GFX_TLB_INVALIDATE_ALWAYS);
 599         }
 600
 601         if (INTEL_INFO(dev)->gen >= 6)
 602                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
 603
 604         if (HAS_L3_GPU_CACHE(dev))
 605                 I915_WRITE_IMR(ring, ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
 606
 607         return ret;
 608 }
 609
 610 static void render_ring_cleanup(struct intel_ring_buffer *ring)
 611 {
 612         struct drm_device *dev = ring->dev;
 613
 614         if (!ring->private)
 615                 return;
 616
 617         if (HAS_BROKEN_CS_TLB(dev))
 618                 drm_gem_object_unreference(to_gem_object(ring->private));
 619
 620         cleanup_pipe_control(ring);
 621 }
 622
 623 static void
 624 update_mboxes(struct intel_ring_buffer *ring,
 625               u32 mmio_offset)
 626 {
 627 /* NB: In order to be able to do semaphore MBOX updates for varying number
 628  * of rings, it's easiest if we round up each individual update to a
 629  * multiple of 2 (since ring updates must always be a multiple of 2)
 630  * even though the actual update only requires 3 dwords.
 631  */
 632 #define MBOX_UPDATE_DWORDS 4
 633         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
 634         intel_ring_emit(ring, mmio_offset);
 635         intel_ring_emit(ring, ring->outstanding_lazy_request);
 636         intel_ring_emit(ring, MI_NOOP);
 637 }
 638
 639 /**
 640  * gen6_add_request - Update the semaphore mailbox registers
 641  *
 642  * @ring - ring that is adding a request
 643  * @seqno - return seqno stuck into the ring
 644  *
 645  * Update the mailbox registers in the *other* rings with the current seqno.
 646  * This acts like a signal in the canonical semaphore.
 647  */
 648 static int
 649 gen6_add_request(struct intel_ring_buffer *ring)
 650 {
 651         struct drm_device *dev = ring->dev;
 652         struct drm_i915_private *dev_priv = dev->dev_private;
 653         struct intel_ring_buffer *useless;
 654         int i, ret;
 655
 656         ret = intel_ring_begin(ring, ((I915_NUM_RINGS-1) *
 657                                       MBOX_UPDATE_DWORDS) +
 658                                       4);
 659         if (ret)
 660                 return ret;
 661 #undef MBOX_UPDATE_DWORDS
 662
 663         for_each_ring(useless, dev_priv, i) {
 664                 u32 mbox_reg = ring->signal_mbox[i];
 665                 if (mbox_reg != GEN6_NOSYNC)
 666                         update_mboxes(ring, mbox_reg);
 667         }
 668
 669         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
 670         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 671         intel_ring_emit(ring, ring->outstanding_lazy_request);
 672         intel_ring_emit(ring, MI_USER_INTERRUPT);
 673         intel_ring_advance(ring);
 674
 675         return 0;
 676 }
 677
 678 static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
 679                                               u32 seqno)
 680 {
 681         struct drm_i915_private *dev_priv = dev->dev_private;
 682         return dev_priv->last_seqno < seqno;
 683 }
 684
 685 /**
 686  * intel_ring_sync - sync the waiter to the signaller on seqno
 687  *
 688  * @waiter - ring that is waiting
 689  * @signaller - ring which has, or will signal
 690  * @seqno - seqno which the waiter will block on
 691  */
 692 static int
 693 gen6_ring_sync(struct intel_ring_buffer *waiter,
 694                struct intel_ring_buffer *signaller,
 695                u32 seqno)
 696 {
 697         int ret;
 698         u32 dw1 = MI_SEMAPHORE_MBOX |
 699                   MI_SEMAPHORE_COMPARE |
 700                   MI_SEMAPHORE_REGISTER;
 701
 702         /* Throughout all of the GEM code, seqno passed implies our current
 703          * seqno is >= the last seqno executed. However for hardware the
 704          * comparison is strictly greater than.
 705          */
 706         seqno -= 1;
 707
 708         WARN_ON(signaller->semaphore_register[waiter->id] ==
 709                 MI_SEMAPHORE_SYNC_INVALID);
 710
 711         ret = intel_ring_begin(waiter, 4);
 712         if (ret)
 713                 return ret;
 714
 715         /* If seqno wrap happened, omit the wait with no-ops */
 716         if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
 717                 intel_ring_emit(waiter,
 718                                 dw1 |
 719                                 signaller->semaphore_register[waiter->id]);
 720                 intel_ring_emit(waiter, seqno);
 721                 intel_ring_emit(waiter, 0);
 722                 intel_ring_emit(waiter, MI_NOOP);
 723         } else {
 724                 intel_ring_emit(waiter, MI_NOOP);
 725                 intel_ring_emit(waiter, MI_NOOP);
 726                 intel_ring_emit(waiter, MI_NOOP);
 727                 intel_ring_emit(waiter, MI_NOOP);
 728         }
 729         intel_ring_advance(waiter);
 730
 731         return 0;
 732 }
 733
 734 #define PIPE_CONTROL_FLUSH(ring__, addr__)                                      \
 735 do {                                                                    \
 736         intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |                \
 737                  PIPE_CONTROL_DEPTH_STALL);                             \
 738         intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT);                    \
 739         intel_ring_emit(ring__, 0);                                                     \
 740         intel_ring_emit(ring__, 0);                                                     \
 741 } while (0)
 742
 743 static int
 744 pc_render_add_request(struct intel_ring_buffer *ring)
 745 {
 746         struct pipe_control *pc = ring->private;
 747         u32 scratch_addr = pc->gtt_offset + 128;
 748         int ret;
 749
 750         /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
 751          * incoherent with writes to memory, i.e. completely fubar,
 752          * so we need to use PIPE_NOTIFY instead.
 753          *
 754          * However, we also need to workaround the qword write
 755          * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
 756          * memory before requesting an interrupt.
 757          */
 758         ret = intel_ring_begin(ring, 32);
 759         if (ret)
 760                 return ret;
 761
 762         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
 763                         PIPE_CONTROL_WRITE_FLUSH |
 764                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
 765         intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
 766         intel_ring_emit(ring, ring->outstanding_lazy_request);
 767         intel_ring_emit(ring, 0);
 768         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 769         scratch_addr += 128; /* write to separate cachelines */
 770         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 771         scratch_addr += 128;
 772         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 773         scratch_addr += 128;
 774         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 775         scratch_addr += 128;
 776         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 777         scratch_addr += 128;
 778         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 779
 780         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
 781                         PIPE_CONTROL_WRITE_FLUSH |
 782                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
 783                         PIPE_CONTROL_NOTIFY);
 784         intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
 785         intel_ring_emit(ring, ring->outstanding_lazy_request);
 786         intel_ring_emit(ring, 0);
 787         intel_ring_advance(ring);
 788
 789         return 0;
 790 }
 791
 792 static u32
 793 gen6_ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
 794 {
 795         /* Workaround to force correct ordering between irq and seqno writes on
 796          * ivb (and maybe also on snb) by reading from a CS register (like
 797          * ACTHD) before reading the status page. */
 798         if (!lazy_coherency)
 799                 intel_ring_get_active_head(ring);
 800         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
 801 }
 802
 803 static u32
 804 ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
 805 {
 806         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
 807 }
 808
 809 static void
 810 ring_set_seqno(struct intel_ring_buffer *ring, u32 seqno)
 811 {
 812         intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
 813 }
 814
 815 static u32
 816 pc_render_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
 817 {
 818         struct pipe_control *pc = ring->private;
 819         return pc->cpu_page[0];
 820 }
 821
 822 static void
 823 pc_render_set_seqno(struct intel_ring_buffer *ring, u32 seqno)
 824 {
 825         struct pipe_control *pc = ring->private;
 826         pc->cpu_page[0] = seqno;
 827 }
 828
 829 static bool
 830 gen5_ring_get_irq(struct intel_ring_buffer *ring)
 831 {
 832         struct drm_device *dev = ring->dev;
 833         drm_i915_private_t *dev_priv = dev->dev_private;
 834         unsigned long flags;
 835
 836         if (!dev->irq_enabled)
 837                 return false;
 838
 839         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 840         if (ring->irq_refcount.gt++ == 0) {
 841                 dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
 842                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 843                 POSTING_READ(GTIMR);
 844         }
 845         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 846
 847         return true;
 848 }
 849
 850 static void
 851 gen5_ring_put_irq(struct intel_ring_buffer *ring)
 852 {
 853         struct drm_device *dev = ring->dev;
 854         drm_i915_private_t *dev_priv = dev->dev_private;
 855         unsigned long flags;
 856
 857         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 858         if (--ring->irq_refcount.gt == 0) {
 859                 dev_priv->gt_irq_mask |= ring->irq_enable_mask;
 860                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 861                 POSTING_READ(GTIMR);
 862         }
 863         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 864 }
 865
 866 static bool
 867 i9xx_ring_get_irq(struct intel_ring_buffer *ring)
 868 {
 869         struct drm_device *dev = ring->dev;
 870         drm_i915_private_t *dev_priv = dev->dev_private;
 871         unsigned long flags;
 872
 873         if (!dev->irq_enabled)
 874                 return false;
 875
 876         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 877         if (ring->irq_refcount.gt++ == 0) {
 878                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
 879                 I915_WRITE(IMR, dev_priv->irq_mask);
 880                 POSTING_READ(IMR);
 881         }
 882         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 883
 884         return true;
 885 }
 886
 887 static void
 888 i9xx_ring_put_irq(struct intel_ring_buffer *ring)
 889 {
 890         struct drm_device *dev = ring->dev;
 891         drm_i915_private_t *dev_priv = dev->dev_private;
 892         unsigned long flags;
 893
 894         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 895         if (--ring->irq_refcount.gt == 0) {
 896                 dev_priv->irq_mask |= ring->irq_enable_mask;
 897                 I915_WRITE(IMR, dev_priv->irq_mask);
 898                 POSTING_READ(IMR);
 899         }
 900         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 901 }
 902
 903 static bool
 904 i8xx_ring_get_irq(struct intel_ring_buffer *ring)
 905 {
 906         struct drm_device *dev = ring->dev;
 907         drm_i915_private_t *dev_priv = dev->dev_private;
 908         unsigned long flags;
 909
 910         if (!dev->irq_enabled)
 911                 return false;
 912
 913         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 914         if (ring->irq_refcount.gt++ == 0) {
 915                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
 916                 I915_WRITE16(IMR, dev_priv->irq_mask);
 917                 POSTING_READ16(IMR);
 918         }
 919         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 920
 921         return true;
 922 }
 923
 924 static void
 925 i8xx_ring_put_irq(struct intel_ring_buffer *ring)
 926 {
 927         struct drm_device *dev = ring->dev;
 928         drm_i915_private_t *dev_priv = dev->dev_private;
 929         unsigned long flags;
 930
 931         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 932         if (--ring->irq_refcount.gt == 0) {
 933                 dev_priv->irq_mask |= ring->irq_enable_mask;
 934                 I915_WRITE16(IMR, dev_priv->irq_mask);
 935                 POSTING_READ16(IMR);
 936         }
 937         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 938 }
 939
 940 void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
 941 {
 942         struct drm_device *dev = ring->dev;
 943         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 944         u32 mmio = 0;
 945
 946         /* The ring status page addresses are no longer next to the rest of
 947          * the ring registers as of gen7.
 948          */
 949         if (IS_GEN7(dev)) {
 950                 switch (ring->id) {
 951                 case RCS:
 952                         mmio = RENDER_HWS_PGA_GEN7;
 953                         break;
 954                 case BCS:
 955                         mmio = BLT_HWS_PGA_GEN7;
 956                         break;
 957                 case VCS:
 958                         mmio = BSD_HWS_PGA_GEN7;
 959                         break;
 960                 case VECS:
 961                         mmio = VEBOX_HWS_PGA_GEN7;
 962                         break;
 963                 }
 964         } else if (IS_GEN6(ring->dev)) {
 965                 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
 966         } else {
 967                 mmio = RING_HWS_PGA(ring->mmio_base);
 968         }
 969
 970         I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
 971         POSTING_READ(mmio);
 972 }
 973
 974 static int
 975 bsd_ring_flush(struct intel_ring_buffer *ring,
 976                u32     invalidate_domains,
 977                u32     flush_domains)
 978 {
 979         int ret;
 980
 981         ret = intel_ring_begin(ring, 2);
 982         if (ret)
 983                 return ret;
 984
 985         intel_ring_emit(ring, MI_FLUSH);
 986         intel_ring_emit(ring, MI_NOOP);
 987         intel_ring_advance(ring);
 988         return 0;
 989 }
 990
 991 static int
 992 i9xx_add_request(struct intel_ring_buffer *ring)
 993 {
 994         int ret;
 995
 996         ret = intel_ring_begin(ring, 4);
 997         if (ret)
 998                 return ret;
 999
1000         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
1001         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1002         intel_ring_emit(ring, ring->outstanding_lazy_request);
1003         intel_ring_emit(ring, MI_USER_INTERRUPT);
1004         intel_ring_advance(ring);
1005
1006         return 0;
1007 }
1008
1009 static bool
1010 gen6_ring_get_irq(struct intel_ring_buffer *ring)
1011 {
1012         struct drm_device *dev = ring->dev;
1013         drm_i915_private_t *dev_priv = dev->dev_private;
1014         unsigned long flags;
1015
1016         if (!dev->irq_enabled)
1017                return false;
1018
1019         /* It looks like we need to prevent the gt from suspending while waiting
1020          * for an notifiy irq, otherwise irqs seem to get lost on at least the
1021          * blt/bsd rings on ivb. */
1022         gen6_gt_force_wake_get(dev_priv);
1023
1024         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1025         if (ring->irq_refcount.gt++ == 0) {
1026                 if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)
1027                         I915_WRITE_IMR(ring,
1028                                        ~(ring->irq_enable_mask |
1029                                          GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1030                 else
1031                         I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1032                 dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
1033                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1034                 POSTING_READ(GTIMR);
1035         }
1036         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1037
1038         return true;
1039 }
1040
1041 static void
1042 gen6_ring_put_irq(struct intel_ring_buffer *ring)
1043 {
1044         struct drm_device *dev = ring->dev;
1045         drm_i915_private_t *dev_priv = dev->dev_private;
1046         unsigned long flags;
1047
1048         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1049         if (--ring->irq_refcount.gt == 0) {
1050                 if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)
1051                         I915_WRITE_IMR(ring,
1052                                        ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1053                 else
1054                         I915_WRITE_IMR(ring, ~0);
1055                 dev_priv->gt_irq_mask |= ring->irq_enable_mask;
1056                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1057                 POSTING_READ(GTIMR);
1058         }
1059         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1060
1061         gen6_gt_force_wake_put(dev_priv);
1062 }
1063
1064 static bool
1065 hsw_vebox_get_irq(struct intel_ring_buffer *ring)
1066 {
1067         struct drm_device *dev = ring->dev;
1068         struct drm_i915_private *dev_priv = dev->dev_private;
1069         unsigned long flags;
1070
1071         if (!dev->irq_enabled)
1072                 return false;
1073
1074         spin_lock_irqsave(&dev_priv->rps.lock, flags);
1075         if (ring->irq_refcount.pm++ == 0) {
1076                 u32 pm_imr = I915_READ(GEN6_PMIMR);
1077                 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1078                 I915_WRITE(GEN6_PMIMR, pm_imr & ~ring->irq_enable_mask);
1079                 POSTING_READ(GEN6_PMIMR);
1080         }
1081         spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
1082
1083         return true;
1084 }
1085
1086 static void
1087 hsw_vebox_put_irq(struct intel_ring_buffer *ring)
1088 {
1089         struct drm_device *dev = ring->dev;
1090         struct drm_i915_private *dev_priv = dev->dev_private;
1091         unsigned long flags;
1092
1093         if (!dev->irq_enabled)
1094                 return;
1095
1096         spin_lock_irqsave(&dev_priv->rps.lock, flags);
1097         if (--ring->irq_refcount.pm == 0) {
1098                 u32 pm_imr = I915_READ(GEN6_PMIMR);
1099                 I915_WRITE_IMR(ring, ~0);
1100                 I915_WRITE(GEN6_PMIMR, pm_imr | ring->irq_enable_mask);
1101                 POSTING_READ(GEN6_PMIMR);
1102         }
1103         spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
1104 }
1105
1106 static int
1107 i965_dispatch_execbuffer(struct intel_ring_buffer *ring,
1108                          u32 offset, u32 length,
1109                          unsigned flags)
1110 {
1111         int ret;
1112
1113         ret = intel_ring_begin(ring, 2);
1114         if (ret)
1115                 return ret;
1116
1117         intel_ring_emit(ring,
1118                         MI_BATCH_BUFFER_START |
1119                         MI_BATCH_GTT |
1120                         (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
1121         intel_ring_emit(ring, offset);
1122         intel_ring_advance(ring);
1123
1124         return 0;
1125 }
1126
1127 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1128 #define I830_BATCH_LIMIT (256*1024)
1129 static int
1130 i830_dispatch_execbuffer(struct intel_ring_buffer *ring,
1131                                 u32 offset, u32 len,
1132                                 unsigned flags)
1133 {
1134         int ret;
1135
1136         if (flags & I915_DISPATCH_PINNED) {
1137                 ret = intel_ring_begin(ring, 4);
1138                 if (ret)
1139                         return ret;
1140
1141                 intel_ring_emit(ring, MI_BATCH_BUFFER);
1142                 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1143                 intel_ring_emit(ring, offset + len - 8);
1144                 intel_ring_emit(ring, MI_NOOP);
1145                 intel_ring_advance(ring);
1146         } else {
1147                 struct drm_i915_gem_object *obj = ring->private;
1148                 u32 cs_offset = obj->gtt_offset;
1149
1150                 if (len > I830_BATCH_LIMIT)
1151                         return -ENOSPC;
1152
1153                 ret = intel_ring_begin(ring, 9+3);
1154                 if (ret)
1155                         return ret;
1156                 /* Blit the batch (which has now all relocs applied) to the stable batch
1157                  * scratch bo area (so that the CS never stumbles over its tlb
1158                  * invalidation bug) ... */
1159                 intel_ring_emit(ring, XY_SRC_COPY_BLT_CMD |
1160                                 XY_SRC_COPY_BLT_WRITE_ALPHA |
1161                                 XY_SRC_COPY_BLT_WRITE_RGB);
1162                 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_GXCOPY | 4096);
1163                 intel_ring_emit(ring, 0);
1164                 intel_ring_emit(ring, (DIV_ROUND_UP(len, 4096) << 16) | 1024);
1165                 intel_ring_emit(ring, cs_offset);
1166                 intel_ring_emit(ring, 0);
1167                 intel_ring_emit(ring, 4096);
1168                 intel_ring_emit(ring, offset);
1169                 intel_ring_emit(ring, MI_FLUSH);
1170
1171                 /* ... and execute it. */
1172                 intel_ring_emit(ring, MI_BATCH_BUFFER);
1173                 intel_ring_emit(ring, cs_offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1174                 intel_ring_emit(ring, cs_offset + len - 8);
1175                 intel_ring_advance(ring);
1176         }
1177
1178         return 0;
1179 }
1180
1181 static int
1182 i915_dispatch_execbuffer(struct intel_ring_buffer *ring,
1183                          u32 offset, u32 len,
1184                          unsigned flags)
1185 {
1186         int ret;
1187
1188         ret = intel_ring_begin(ring, 2);
1189         if (ret)
1190                 return ret;
1191
1192         intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1193         intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1194         intel_ring_advance(ring);
1195
1196         return 0;
1197 }
1198
1199 static void cleanup_status_page(struct intel_ring_buffer *ring)
1200 {
1201         struct drm_i915_gem_object *obj;
1202
1203         obj = ring->status_page.obj;
1204         if (obj == NULL)
1205                 return;
1206
1207         kunmap(sg_page(obj->pages->sgl));
1208         i915_gem_object_unpin(obj);
1209         drm_gem_object_unreference(&obj->base);
1210         ring->status_page.obj = NULL;
1211 }
1212
1213 static int init_status_page(struct intel_ring_buffer *ring)
1214 {
1215         struct drm_device *dev = ring->dev;
1216         struct drm_i915_gem_object *obj;
1217         int ret;
1218
1219         obj = i915_gem_alloc_object(dev, 4096);
1220         if (obj == NULL) {
1221                 DRM_ERROR("Failed to allocate status page\n");
1222                 ret = -ENOMEM;
1223                 goto err;
1224         }
1225
1226         i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1227
1228         ret = i915_gem_object_pin(obj, 4096, true, false);
1229         if (ret != 0) {
1230                 goto err_unref;
1231         }
1232
1233         ring->status_page.gfx_addr = obj->gtt_offset;
1234         ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
1235         if (ring->status_page.page_addr == NULL) {
1236                 ret = -ENOMEM;
1237                 goto err_unpin;
1238         }
1239         ring->status_page.obj = obj;
1240         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1241
1242         DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1243                         ring->name, ring->status_page.gfx_addr);
1244
1245         return 0;
1246
1247 err_unpin:
1248         i915_gem_object_unpin(obj);
1249 err_unref:
1250         drm_gem_object_unreference(&obj->base);
1251 err:
1252         return ret;
1253 }
1254
1255 static int init_phys_status_page(struct intel_ring_buffer *ring)
1256 {
1257         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1258
1259         if (!dev_priv->status_page_dmah) {
1260                 dev_priv->status_page_dmah =
1261                         drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1262                 if (!dev_priv->status_page_dmah)
1263                         return -ENOMEM;
1264         }
1265
1266         ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1267         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1268
1269         return 0;
1270 }
1271
1272 static int intel_init_ring_buffer(struct drm_device *dev,
1273                                   struct intel_ring_buffer *ring)
1274 {
1275         struct drm_i915_gem_object *obj;
1276         struct drm_i915_private *dev_priv = dev->dev_private;
1277         int ret;
1278
1279         ring->dev = dev;
1280         INIT_LIST_HEAD(&ring->active_list);
1281         INIT_LIST_HEAD(&ring->request_list);
1282         ring->size = 32 * PAGE_SIZE;
1283         memset(ring->sync_seqno, 0, sizeof(ring->sync_seqno));
1284
1285         init_waitqueue_head(&ring->irq_queue);
1286
1287         if (I915_NEED_GFX_HWS(dev)) {
1288                 ret = init_status_page(ring);
1289                 if (ret)
1290                         return ret;
1291         } else {
1292                 BUG_ON(ring->id != RCS);
1293                 ret = init_phys_status_page(ring);
1294                 if (ret)
1295                         return ret;
1296         }
1297
1298         obj = NULL;
1299         if (!HAS_LLC(dev))
1300                 obj = i915_gem_object_create_stolen(dev, ring->size);
1301         if (obj == NULL)
1302                 obj = i915_gem_alloc_object(dev, ring->size);
1303         if (obj == NULL) {
1304                 DRM_ERROR("Failed to allocate ringbuffer\n");
1305                 ret = -ENOMEM;
1306                 goto err_hws;
1307         }
1308
1309         ring->obj = obj;
1310
1311         ret = i915_gem_object_pin(obj, PAGE_SIZE, true, false);
1312         if (ret)
1313                 goto err_unref;
1314
1315         ret = i915_gem_object_set_to_gtt_domain(obj, true);
1316         if (ret)
1317                 goto err_unpin;
1318
1319         ring->virtual_start =
1320                 ioremap_wc(dev_priv->gtt.mappable_base + obj->gtt_offset,
1321                            ring->size);
1322         if (ring->virtual_start == NULL) {
1323                 DRM_ERROR("Failed to map ringbuffer.\n");
1324                 ret = -EINVAL;
1325                 goto err_unpin;
1326         }
1327
1328         ret = ring->init(ring);
1329         if (ret)
1330                 goto err_unmap;
1331
1332         /* Workaround an erratum on the i830 which causes a hang if
1333          * the TAIL pointer points to within the last 2 cachelines
1334          * of the buffer.
1335          */
1336         ring->effective_size = ring->size;
1337         if (IS_I830(ring->dev) || IS_845G(ring->dev))
1338                 ring->effective_size -= 128;
1339
1340         return 0;
1341
1342 err_unmap:
1343         iounmap(ring->virtual_start);
1344 err_unpin:
1345         i915_gem_object_unpin(obj);
1346 err_unref:
1347         drm_gem_object_unreference(&obj->base);
1348         ring->obj = NULL;
1349 err_hws:
1350         cleanup_status_page(ring);
1351         return ret;
1352 }
1353
1354 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
1355 {
1356         struct drm_i915_private *dev_priv;
1357         int ret;
1358
1359         if (ring->obj == NULL)
1360                 return;
1361
1362         /* Disable the ring buffer. The ring must be idle at this point */
1363         dev_priv = ring->dev->dev_private;
1364         ret = intel_ring_idle(ring);
1365         if (ret)
1366                 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1367                           ring->name, ret);
1368
1369         I915_WRITE_CTL(ring, 0);
1370
1371         iounmap(ring->virtual_start);
1372
1373         i915_gem_object_unpin(ring->obj);
1374         drm_gem_object_unreference(&ring->obj->base);
1375         ring->obj = NULL;
1376
1377         if (ring->cleanup)
1378                 ring->cleanup(ring);
1379
1380         cleanup_status_page(ring);
1381 }
1382
1383 static int intel_ring_wait_seqno(struct intel_ring_buffer *ring, u32 seqno)
1384 {
1385         int ret;
1386
1387         ret = i915_wait_seqno(ring, seqno);
1388         if (!ret)
1389                 i915_gem_retire_requests_ring(ring);
1390
1391         return ret;
1392 }
1393
1394 static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n)
1395 {
1396         struct drm_i915_gem_request *request;
1397         u32 seqno = 0;
1398         int ret;
1399
1400         i915_gem_retire_requests_ring(ring);
1401
1402         if (ring->last_retired_head != -1) {
1403                 ring->head = ring->last_retired_head;
1404                 ring->last_retired_head = -1;
1405                 ring->space = ring_space(ring);
1406                 if (ring->space >= n)
1407                         return 0;
1408         }
1409
1410         list_for_each_entry(request, &ring->request_list, list) {
1411                 int space;
1412
1413                 if (request->tail == -1)
1414                         continue;
1415
1416                 space = request->tail - (ring->tail + I915_RING_FREE_SPACE);
1417                 if (space < 0)
1418                         space += ring->size;
1419                 if (space >= n) {
1420                         seqno = request->seqno;
1421                         break;
1422                 }
1423
1424                 /* Consume this request in case we need more space than
1425                  * is available and so need to prevent a race between
1426                  * updating last_retired_head and direct reads of
1427                  * I915_RING_HEAD. It also provides a nice sanity check.
1428                  */
1429                 request->tail = -1;
1430         }
1431
1432         if (seqno == 0)
1433                 return -ENOSPC;
1434
1435         ret = intel_ring_wait_seqno(ring, seqno);
1436         if (ret)
1437                 return ret;
1438
1439         if (WARN_ON(ring->last_retired_head == -1))
1440                 return -ENOSPC;
1441
1442         ring->head = ring->last_retired_head;
1443         ring->last_retired_head = -1;
1444         ring->space = ring_space(ring);
1445         if (WARN_ON(ring->space < n))
1446                 return -ENOSPC;
1447
1448         return 0;
1449 }
1450
1451 static int ring_wait_for_space(struct intel_ring_buffer *ring, int n)
1452 {
1453         struct drm_device *dev = ring->dev;
1454         struct drm_i915_private *dev_priv = dev->dev_private;
1455         unsigned long end;
1456         int ret;
1457
1458         ret = intel_ring_wait_request(ring, n);
1459         if (ret != -ENOSPC)
1460                 return ret;
1461
1462         trace_i915_ring_wait_begin(ring);
1463         /* With GEM the hangcheck timer should kick us out of the loop,
1464          * leaving it early runs the risk of corrupting GEM state (due
1465          * to running on almost untested codepaths). But on resume
1466          * timers don't work yet, so prevent a complete hang in that
1467          * case by choosing an insanely large timeout. */
1468         end = jiffies + 60 * HZ;
1469
1470         do {
1471                 ring->head = I915_READ_HEAD(ring);
1472                 ring->space = ring_space(ring);
1473                 if (ring->space >= n) {
1474                         trace_i915_ring_wait_end(ring);
1475                         return 0;
1476                 }
1477
1478                 if (dev->primary->master) {
1479                         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1480                         if (master_priv->sarea_priv)
1481                                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1482                 }
1483
1484                 msleep(1);
1485
1486                 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1487                                            dev_priv->mm.interruptible);
1488                 if (ret)
1489                         return ret;
1490         } while (!time_after(jiffies, end));
1491         trace_i915_ring_wait_end(ring);
1492         return -EBUSY;
1493 }
1494
1495 static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
1496 {
1497         uint32_t __iomem *virt;
1498         int rem = ring->size - ring->tail;
1499
1500         if (ring->space < rem) {
1501                 int ret = ring_wait_for_space(ring, rem);
1502                 if (ret)
1503                         return ret;
1504         }
1505
1506         virt = ring->virtual_start + ring->tail;
1507         rem /= 4;
1508         while (rem--)
1509                 iowrite32(MI_NOOP, virt++);
1510
1511         ring->tail = 0;
1512         ring->space = ring_space(ring);
1513
1514         return 0;
1515 }
1516
1517 int intel_ring_idle(struct intel_ring_buffer *ring)
1518 {
1519         u32 seqno;
1520         int ret;
1521
1522         /* We need to add any requests required to flush the objects and ring */
1523         if (ring->outstanding_lazy_request) {
1524                 ret = i915_add_request(ring, NULL);
1525                 if (ret)
1526                         return ret;
1527         }
1528
1529         /* Wait upon the last request to be completed */
1530         if (list_empty(&ring->request_list))
1531                 return 0;
1532
1533         seqno = list_entry(ring->request_list.prev,
1534                            struct drm_i915_gem_request,
1535                            list)->seqno;
1536
1537         return i915_wait_seqno(ring, seqno);
1538 }
1539
1540 static int
1541 intel_ring_alloc_seqno(struct intel_ring_buffer *ring)
1542 {
1543         if (ring->outstanding_lazy_request)
1544                 return 0;
1545
1546         return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_request);
1547 }
1548
1549 static int __intel_ring_begin(struct intel_ring_buffer *ring,
1550                               int bytes)
1551 {
1552         int ret;
1553
1554         if (unlikely(ring->tail + bytes > ring->effective_size)) {
1555                 ret = intel_wrap_ring_buffer(ring);
1556                 if (unlikely(ret))
1557                         return ret;
1558         }
1559
1560         if (unlikely(ring->space < bytes)) {
1561                 ret = ring_wait_for_space(ring, bytes);
1562                 if (unlikely(ret))
1563                         return ret;
1564         }
1565
1566         ring->space -= bytes;
1567         return 0;
1568 }
1569
1570 int intel_ring_begin(struct intel_ring_buffer *ring,
1571                      int num_dwords)
1572 {
1573         drm_i915_private_t *dev_priv = ring->dev->dev_private;
1574         int ret;
1575
1576         ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1577                                    dev_priv->mm.interruptible);
1578         if (ret)
1579                 return ret;
1580
1581         /* Preallocate the olr before touching the ring */
1582         ret = intel_ring_alloc_seqno(ring);
1583         if (ret)
1584                 return ret;
1585
1586         return __intel_ring_begin(ring, num_dwords * sizeof(uint32_t));
1587 }
1588
1589 void intel_ring_init_seqno(struct intel_ring_buffer *ring, u32 seqno)
1590 {
1591         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1592
1593         BUG_ON(ring->outstanding_lazy_request);
1594
1595         if (INTEL_INFO(ring->dev)->gen >= 6) {
1596                 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
1597                 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
1598         }
1599
1600         ring->set_seqno(ring, seqno);
1601         ring->hangcheck.seqno = seqno;
1602 }
1603
1604 void intel_ring_advance(struct intel_ring_buffer *ring)
1605 {
1606         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1607
1608         ring->tail &= ring->size - 1;
1609         if (dev_priv->gpu_error.stop_rings & intel_ring_flag(ring))
1610                 return;
1611         ring->write_tail(ring, ring->tail);
1612 }
1613
1614
1615 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
1616                                      u32 value)
1617 {
1618         drm_i915_private_t *dev_priv = ring->dev->dev_private;
1619
1620        /* Every tail move must follow the sequence below */
1621
1622         /* Disable notification that the ring is IDLE. The GT
1623          * will then assume that it is busy and bring it out of rc6.
1624          */
1625         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1626                    _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1627
1628         /* Clear the context id. Here be magic! */
1629         I915_WRITE64(GEN6_BSD_RNCID, 0x0);
1630
1631         /* Wait for the ring not to be idle, i.e. for it to wake up. */
1632         if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
1633                       GEN6_BSD_SLEEP_INDICATOR) == 0,
1634                      50))
1635                 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
1636
1637         /* Now that the ring is fully powered up, update the tail */
1638         I915_WRITE_TAIL(ring, value);
1639         POSTING_READ(RING_TAIL(ring->mmio_base));
1640
1641         /* Let the ring send IDLE messages to the GT again,
1642          * and so let it sleep to conserve power when idle.
1643          */
1644         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1645                    _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1646 }
1647
1648 static int gen6_bsd_ring_flush(struct intel_ring_buffer *ring,
1649                                u32 invalidate, u32 flush)
1650 {
1651         uint32_t cmd;
1652         int ret;
1653
1654         ret = intel_ring_begin(ring, 4);
1655         if (ret)
1656                 return ret;
1657
1658         cmd = MI_FLUSH_DW;
1659         /*
1660          * Bspec vol 1c.5 - video engine command streamer:
1661          * "If ENABLED, all TLBs will be invalidated once the flush
1662          * operation is complete. This bit is only valid when the
1663          * Post-Sync Operation field is a value of 1h or 3h."
1664          */
1665         if (invalidate & I915_GEM_GPU_DOMAINS)
1666                 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD |
1667                         MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
1668         intel_ring_emit(ring, cmd);
1669         intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
1670         intel_ring_emit(ring, 0);
1671         intel_ring_emit(ring, MI_NOOP);
1672         intel_ring_advance(ring);
1673         return 0;
1674 }
1675
1676 static int
1677 hsw_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1678                               u32 offset, u32 len,
1679                               unsigned flags)
1680 {
1681         int ret;
1682
1683         ret = intel_ring_begin(ring, 2);
1684         if (ret)
1685                 return ret;
1686
1687         intel_ring_emit(ring,
1688                         MI_BATCH_BUFFER_START | MI_BATCH_PPGTT_HSW |
1689                         (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_HSW));
1690         /* bit0-7 is the length on GEN6+ */
1691         intel_ring_emit(ring, offset);
1692         intel_ring_advance(ring);
1693
1694         return 0;
1695 }
1696
1697 static int
1698 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1699                               u32 offset, u32 len,
1700                               unsigned flags)
1701 {
1702         int ret;
1703
1704         ret = intel_ring_begin(ring, 2);
1705         if (ret)
1706                 return ret;
1707
1708         intel_ring_emit(ring,
1709                         MI_BATCH_BUFFER_START |
1710                         (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
1711         /* bit0-7 is the length on GEN6+ */
1712         intel_ring_emit(ring, offset);
1713         intel_ring_advance(ring);
1714
1715         return 0;
1716 }
1717
1718 /* Blitter support (SandyBridge+) */
1719
1720 static int gen6_ring_flush(struct intel_ring_buffer *ring,
1721                            u32 invalidate, u32 flush)
1722 {
1723         struct drm_device *dev = ring->dev;
1724         uint32_t cmd;
1725         int ret;
1726
1727         ret = intel_ring_begin(ring, 4);
1728         if (ret)
1729                 return ret;
1730
1731         cmd = MI_FLUSH_DW;
1732         /*
1733          * Bspec vol 1c.3 - blitter engine command streamer:
1734          * "If ENABLED, all TLBs will be invalidated once the flush
1735          * operation is complete. This bit is only valid when the
1736          * Post-Sync Operation field is a value of 1h or 3h."
1737          */
1738         if (invalidate & I915_GEM_DOMAIN_RENDER)
1739                 cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX |
1740                         MI_FLUSH_DW_OP_STOREDW;
1741         intel_ring_emit(ring, cmd);
1742         intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
1743         intel_ring_emit(ring, 0);
1744         intel_ring_emit(ring, MI_NOOP);
1745         intel_ring_advance(ring);
1746
1747         if (IS_GEN7(dev) && flush)
1748                 return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN);
1749
1750         return 0;
1751 }
1752
1753 int intel_init_render_ring_buffer(struct drm_device *dev)
1754 {
1755         drm_i915_private_t *dev_priv = dev->dev_private;
1756         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1757
1758         ring->name = "render ring";
1759         ring->id = RCS;
1760         ring->mmio_base = RENDER_RING_BASE;
1761
1762         if (INTEL_INFO(dev)->gen >= 6) {
1763                 ring->add_request = gen6_add_request;
1764                 ring->flush = gen7_render_ring_flush;
1765                 if (INTEL_INFO(dev)->gen == 6)
1766                         ring->flush = gen6_render_ring_flush;
1767                 ring->irq_get = gen6_ring_get_irq;
1768                 ring->irq_put = gen6_ring_put_irq;
1769                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
1770                 ring->get_seqno = gen6_ring_get_seqno;
1771                 ring->set_seqno = ring_set_seqno;
1772                 ring->sync_to = gen6_ring_sync;
1773                 ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_INVALID;
1774                 ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_RV;
1775                 ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_RB;
1776                 ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_RVE;
1777                 ring->signal_mbox[RCS] = GEN6_NOSYNC;
1778                 ring->signal_mbox[VCS] = GEN6_VRSYNC;
1779                 ring->signal_mbox[BCS] = GEN6_BRSYNC;
1780                 ring->signal_mbox[VECS] = GEN6_VERSYNC;
1781         } else if (IS_GEN5(dev)) {
1782                 ring->add_request = pc_render_add_request;
1783                 ring->flush = gen4_render_ring_flush;
1784                 ring->get_seqno = pc_render_get_seqno;
1785                 ring->set_seqno = pc_render_set_seqno;
1786                 ring->irq_get = gen5_ring_get_irq;
1787                 ring->irq_put = gen5_ring_put_irq;
1788                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
1789                                         GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
1790         } else {
1791                 ring->add_request = i9xx_add_request;
1792                 if (INTEL_INFO(dev)->gen < 4)
1793                         ring->flush = gen2_render_ring_flush;
1794                 else
1795                         ring->flush = gen4_render_ring_flush;
1796                 ring->get_seqno = ring_get_seqno;
1797                 ring->set_seqno = ring_set_seqno;
1798                 if (IS_GEN2(dev)) {
1799                         ring->irq_get = i8xx_ring_get_irq;
1800                         ring->irq_put = i8xx_ring_put_irq;
1801                 } else {
1802                         ring->irq_get = i9xx_ring_get_irq;
1803                         ring->irq_put = i9xx_ring_put_irq;
1804                 }
1805                 ring->irq_enable_mask = I915_USER_INTERRUPT;
1806         }
1807         ring->write_tail = ring_write_tail;
1808         if (IS_HASWELL(dev))
1809                 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
1810         else if (INTEL_INFO(dev)->gen >= 6)
1811                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1812         else if (INTEL_INFO(dev)->gen >= 4)
1813                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1814         else if (IS_I830(dev) || IS_845G(dev))
1815                 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1816         else
1817                 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1818         ring->init = init_render_ring;
1819         ring->cleanup = render_ring_cleanup;
1820
1821         /* Workaround batchbuffer to combat CS tlb bug. */
1822         if (HAS_BROKEN_CS_TLB(dev)) {
1823                 struct drm_i915_gem_object *obj;
1824                 int ret;
1825
1826                 obj = i915_gem_alloc_object(dev, I830_BATCH_LIMIT);
1827                 if (obj == NULL) {
1828                         DRM_ERROR("Failed to allocate batch bo\n");
1829                         return -ENOMEM;
1830                 }
1831
1832                 ret = i915_gem_object_pin(obj, 0, true, false);
1833                 if (ret != 0) {
1834                         drm_gem_object_unreference(&obj->base);
1835                         DRM_ERROR("Failed to ping batch bo\n");
1836                         return ret;
1837                 }
1838
1839                 ring->private = obj;
1840         }
1841
1842         return intel_init_ring_buffer(dev, ring);
1843 }
1844
1845 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
1846 {
1847         drm_i915_private_t *dev_priv = dev->dev_private;
1848         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1849         int ret;
1850
1851         ring->name = "render ring";
1852         ring->id = RCS;
1853         ring->mmio_base = RENDER_RING_BASE;
1854
1855         if (INTEL_INFO(dev)->gen >= 6) {
1856                 /* non-kms not supported on gen6+ */
1857                 return -ENODEV;
1858         }
1859
1860         /* Note: gem is not supported on gen5/ilk without kms (the corresponding
1861          * gem_init ioctl returns with -ENODEV). Hence we do not need to set up
1862          * the special gen5 functions. */
1863         ring->add_request = i9xx_add_request;
1864         if (INTEL_INFO(dev)->gen < 4)
1865                 ring->flush = gen2_render_ring_flush;
1866         else
1867                 ring->flush = gen4_render_ring_flush;
1868         ring->get_seqno = ring_get_seqno;
1869         ring->set_seqno = ring_set_seqno;
1870         if (IS_GEN2(dev)) {
1871                 ring->irq_get = i8xx_ring_get_irq;
1872                 ring->irq_put = i8xx_ring_put_irq;
1873         } else {
1874                 ring->irq_get = i9xx_ring_get_irq;
1875                 ring->irq_put = i9xx_ring_put_irq;
1876         }
1877         ring->irq_enable_mask = I915_USER_INTERRUPT;
1878         ring->write_tail = ring_write_tail;
1879         if (INTEL_INFO(dev)->gen >= 4)
1880                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1881         else if (IS_I830(dev) || IS_845G(dev))
1882                 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1883         else
1884                 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1885         ring->init = init_render_ring;
1886         ring->cleanup = render_ring_cleanup;
1887
1888         ring->dev = dev;
1889         INIT_LIST_HEAD(&ring->active_list);
1890         INIT_LIST_HEAD(&ring->request_list);
1891
1892         ring->size = size;
1893         ring->effective_size = ring->size;
1894         if (IS_I830(ring->dev) || IS_845G(ring->dev))
1895                 ring->effective_size -= 128;
1896
1897         ring->virtual_start = ioremap_wc(start, size);
1898         if (ring->virtual_start == NULL) {
1899                 DRM_ERROR("can not ioremap virtual address for"
1900                           " ring buffer\n");
1901                 return -ENOMEM;
1902         }
1903
1904         if (!I915_NEED_GFX_HWS(dev)) {
1905                 ret = init_phys_status_page(ring);
1906                 if (ret)
1907                         return ret;
1908         }
1909
1910         return 0;
1911 }
1912
1913 int intel_init_bsd_ring_buffer(struct drm_device *dev)
1914 {
1915         drm_i915_private_t *dev_priv = dev->dev_private;
1916         struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
1917
1918         ring->name = "bsd ring";
1919         ring->id = VCS;
1920
1921         ring->write_tail = ring_write_tail;
1922         if (IS_GEN6(dev) || IS_GEN7(dev)) {
1923                 ring->mmio_base = GEN6_BSD_RING_BASE;
1924                 /* gen6 bsd needs a special wa for tail updates */
1925                 if (IS_GEN6(dev))
1926                         ring->write_tail = gen6_bsd_ring_write_tail;
1927                 ring->flush = gen6_bsd_ring_flush;
1928                 ring->add_request = gen6_add_request;
1929                 ring->get_seqno = gen6_ring_get_seqno;
1930                 ring->set_seqno = ring_set_seqno;
1931                 ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
1932                 ring->irq_get = gen6_ring_get_irq;
1933                 ring->irq_put = gen6_ring_put_irq;
1934                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1935                 ring->sync_to = gen6_ring_sync;
1936                 ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VR;
1937                 ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_INVALID;
1938                 ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VB;
1939                 ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_VVE;
1940                 ring->signal_mbox[RCS] = GEN6_RVSYNC;
1941                 ring->signal_mbox[VCS] = GEN6_NOSYNC;
1942                 ring->signal_mbox[BCS] = GEN6_BVSYNC;
1943                 ring->signal_mbox[VECS] = GEN6_VEVSYNC;
1944         } else {
1945                 ring->mmio_base = BSD_RING_BASE;
1946                 ring->flush = bsd_ring_flush;
1947                 ring->add_request = i9xx_add_request;
1948                 ring->get_seqno = ring_get_seqno;
1949                 ring->set_seqno = ring_set_seqno;
1950                 if (IS_GEN5(dev)) {
1951                         ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
1952                         ring->irq_get = gen5_ring_get_irq;
1953                         ring->irq_put = gen5_ring_put_irq;
1954                 } else {
1955                         ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
1956                         ring->irq_get = i9xx_ring_get_irq;
1957                         ring->irq_put = i9xx_ring_put_irq;
1958                 }
1959                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1960         }
1961         ring->init = init_ring_common;
1962
1963         return intel_init_ring_buffer(dev, ring);
1964 }
1965
1966 int intel_init_blt_ring_buffer(struct drm_device *dev)
1967 {
1968         drm_i915_private_t *dev_priv = dev->dev_private;
1969         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
1970
1971         ring->name = "blitter ring";
1972         ring->id = BCS;
1973
1974         ring->mmio_base = BLT_RING_BASE;
1975         ring->write_tail = ring_write_tail;
1976         ring->flush = gen6_ring_flush;
1977         ring->add_request = gen6_add_request;
1978         ring->get_seqno = gen6_ring_get_seqno;
1979         ring->set_seqno = ring_set_seqno;
1980         ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
1981         ring->irq_get = gen6_ring_get_irq;
1982         ring->irq_put = gen6_ring_put_irq;
1983         ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1984         ring->sync_to = gen6_ring_sync;
1985         ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_BR;
1986         ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_BV;
1987         ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_INVALID;
1988         ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_BVE;
1989         ring->signal_mbox[RCS] = GEN6_RBSYNC;
1990         ring->signal_mbox[VCS] = GEN6_VBSYNC;
1991         ring->signal_mbox[BCS] = GEN6_NOSYNC;
1992         ring->signal_mbox[VECS] = GEN6_VEBSYNC;
1993         ring->init = init_ring_common;
1994
1995         return intel_init_ring_buffer(dev, ring);
1996 }
1997
1998 int intel_init_vebox_ring_buffer(struct drm_device *dev)
1999 {
2000         drm_i915_private_t *dev_priv = dev->dev_private;
2001         struct intel_ring_buffer *ring = &dev_priv->ring[VECS];
2002
2003         ring->name = "video enhancement ring";
2004         ring->id = VECS;
2005
2006         ring->mmio_base = VEBOX_RING_BASE;
2007         ring->write_tail = ring_write_tail;
2008         ring->flush = gen6_ring_flush;
2009         ring->add_request = gen6_add_request;
2010         ring->get_seqno = gen6_ring_get_seqno;
2011         ring->set_seqno = ring_set_seqno;
2012         ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT |
2013                 PM_VEBOX_CS_ERROR_INTERRUPT;
2014         ring->irq_get = hsw_vebox_get_irq;
2015         ring->irq_put = hsw_vebox_put_irq;
2016         ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2017         ring->sync_to = gen6_ring_sync;
2018         ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VER;
2019         ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_VEV;
2020         ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VEB;
2021         ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_INVALID;
2022         ring->signal_mbox[RCS] = GEN6_RVESYNC;
2023         ring->signal_mbox[VCS] = GEN6_VVESYNC;
2024         ring->signal_mbox[BCS] = GEN6_BVESYNC;
2025         ring->signal_mbox[VECS] = GEN6_NOSYNC;
2026         ring->init = init_ring_common;
2027
2028         return intel_init_ring_buffer(dev, ring);
2029 }
2030
2031 int
2032 intel_ring_flush_all_caches(struct intel_ring_buffer *ring)
2033 {
2034         int ret;
2035
2036         if (!ring->gpu_caches_dirty)
2037                 return 0;
2038
2039         ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
2040         if (ret)
2041                 return ret;
2042
2043         trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS);
2044
2045         ring->gpu_caches_dirty = false;
2046         return 0;
2047 }
2048
2049 int
2050 intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring)
2051 {
2052         uint32_t flush_domains;
2053         int ret;
2054
2055         flush_domains = 0;
2056         if (ring->gpu_caches_dirty)
2057                 flush_domains = I915_GEM_GPU_DOMAINS;
2058
2059         ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2060         if (ret)
2061                 return ret;
2062
2063         trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2064
2065         ring->gpu_caches_dirty = false;
2066         return 0;
2067 }