2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2008,2010 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
26 * Eric Anholt <eric@anholt.net>
27 * Chris Wilson <chris@chris-wilson.co.uk>
29 #include <linux/i2c.h>
30 #include <linux/i2c-algo-bit.h>
31 #include <linux/export.h>
34 #include "intel_drv.h"
38 /* Intel GPIO access functions */
40 #define I2C_RISEFALL_TIME 10
42 static inline struct intel_gmbus *
43 to_intel_gmbus(struct i2c_adapter *i2c)
45 return container_of(i2c, struct intel_gmbus, adapter);
49 intel_i2c_reset(struct drm_device *dev)
51 struct drm_i915_private *dev_priv = dev->dev_private;
52 I915_WRITE(dev_priv->gpio_mmio_base + GMBUS0, 0);
55 static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable)
59 /* When using bit bashing for I2C, this bit needs to be set to 1 */
60 if (!IS_PINEVIEW(dev_priv->dev))
63 val = I915_READ(DSPCLK_GATE_D);
65 val |= DPCUNIT_CLOCK_GATE_DISABLE;
67 val &= ~DPCUNIT_CLOCK_GATE_DISABLE;
68 I915_WRITE(DSPCLK_GATE_D, val);
71 static u32 get_reserved(struct intel_gmbus *bus)
73 struct drm_i915_private *dev_priv = bus->dev_priv;
74 struct drm_device *dev = dev_priv->dev;
77 /* On most chips, these bits must be preserved in software. */
78 if (!IS_I830(dev) && !IS_845G(dev))
79 reserved = I915_READ_NOTRACE(bus->gpio_reg) &
80 (GPIO_DATA_PULLUP_DISABLE |
81 GPIO_CLOCK_PULLUP_DISABLE);
86 static int get_clock(void *data)
88 struct intel_gmbus *bus = data;
89 struct drm_i915_private *dev_priv = bus->dev_priv;
90 u32 reserved = get_reserved(bus);
91 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_CLOCK_DIR_MASK);
92 I915_WRITE_NOTRACE(bus->gpio_reg, reserved);
93 return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0;
96 static int get_data(void *data)
98 struct intel_gmbus *bus = data;
99 struct drm_i915_private *dev_priv = bus->dev_priv;
100 u32 reserved = get_reserved(bus);
101 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_DATA_DIR_MASK);
102 I915_WRITE_NOTRACE(bus->gpio_reg, reserved);
103 return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0;
106 static void set_clock(void *data, int state_high)
108 struct intel_gmbus *bus = data;
109 struct drm_i915_private *dev_priv = bus->dev_priv;
110 u32 reserved = get_reserved(bus);
114 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
116 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
119 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | clock_bits);
120 POSTING_READ(bus->gpio_reg);
123 static void set_data(void *data, int state_high)
125 struct intel_gmbus *bus = data;
126 struct drm_i915_private *dev_priv = bus->dev_priv;
127 u32 reserved = get_reserved(bus);
131 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
133 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
136 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | data_bits);
137 POSTING_READ(bus->gpio_reg);
141 intel_gpio_setup(struct intel_gmbus *bus, u32 pin)
143 struct drm_i915_private *dev_priv = bus->dev_priv;
144 static const int map_pin_to_reg[] = {
154 struct i2c_algo_bit_data *algo;
156 if (pin >= ARRAY_SIZE(map_pin_to_reg) || !map_pin_to_reg[pin])
159 algo = &bus->bit_algo;
161 bus->gpio_reg = map_pin_to_reg[pin];
162 bus->gpio_reg += dev_priv->gpio_mmio_base;
164 bus->adapter.algo_data = algo;
165 algo->setsda = set_data;
166 algo->setscl = set_clock;
167 algo->getsda = get_data;
168 algo->getscl = get_clock;
169 algo->udelay = I2C_RISEFALL_TIME;
170 algo->timeout = usecs_to_jiffies(2200);
177 intel_i2c_quirk_xfer(struct intel_gmbus *bus,
178 struct i2c_msg *msgs,
181 struct drm_i915_private *dev_priv = bus->dev_priv;
184 intel_i2c_reset(dev_priv->dev);
186 intel_i2c_quirk_set(dev_priv, true);
189 udelay(I2C_RISEFALL_TIME);
191 ret = i2c_bit_algo.master_xfer(&bus->adapter, msgs, num);
195 intel_i2c_quirk_set(dev_priv, false);
201 gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
204 int reg_offset = dev_priv->gpio_mmio_base;
208 I915_WRITE(GMBUS1 + reg_offset,
210 (last ? GMBUS_CYCLE_STOP : 0) |
211 (len << GMBUS_BYTE_COUNT_SHIFT) |
212 (msg->addr << GMBUS_SLAVE_ADDR_SHIFT) |
213 GMBUS_SLAVE_READ | GMBUS_SW_RDY);
214 POSTING_READ(GMBUS2 + reg_offset);
218 if (wait_for(I915_READ(GMBUS2 + reg_offset) &
219 (GMBUS_SATOER | GMBUS_HW_RDY),
222 if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
225 val = I915_READ(GMBUS3 + reg_offset);
229 } while (--len && ++loop < 4);
236 gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
239 int reg_offset = dev_priv->gpio_mmio_base;
246 val |= *buf++ << (8 * loop);
247 } while (--len && ++loop < 4);
249 I915_WRITE(GMBUS3 + reg_offset, val);
250 I915_WRITE(GMBUS1 + reg_offset,
252 (last ? GMBUS_CYCLE_STOP : 0) |
253 (msg->len << GMBUS_BYTE_COUNT_SHIFT) |
254 (msg->addr << GMBUS_SLAVE_ADDR_SHIFT) |
255 GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
256 POSTING_READ(GMBUS2 + reg_offset);
258 if (wait_for(I915_READ(GMBUS2 + reg_offset) &
259 (GMBUS_SATOER | GMBUS_HW_RDY),
262 if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
267 val |= *buf++ << (8 * loop);
268 } while (--len && ++loop < 4);
270 I915_WRITE(GMBUS3 + reg_offset, val);
271 POSTING_READ(GMBUS2 + reg_offset);
277 gmbus_xfer(struct i2c_adapter *adapter,
278 struct i2c_msg *msgs,
281 struct intel_gmbus *bus = container_of(adapter,
284 struct drm_i915_private *dev_priv = bus->dev_priv;
285 int i, reg_offset, ret;
287 mutex_lock(&dev_priv->gmbus_mutex);
289 if (bus->force_bit) {
290 ret = intel_i2c_quirk_xfer(bus, msgs, num);
294 reg_offset = dev_priv->gpio_mmio_base;
296 I915_WRITE(GMBUS0 + reg_offset, bus->reg0);
298 for (i = 0; i < num; i++) {
299 bool last = i + 1 == num;
301 if (msgs[i].flags & I2C_M_RD)
302 ret = gmbus_xfer_read(dev_priv, &msgs[i], last);
304 ret = gmbus_xfer_write(dev_priv, &msgs[i], last);
306 if (ret == -ETIMEDOUT)
312 wait_for(I915_READ(GMBUS2 + reg_offset) &
313 (GMBUS_SATOER | GMBUS_HW_WAIT_PHASE),
316 if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
323 /* Toggle the Software Clear Interrupt bit. This has the effect
324 * of resetting the GMBUS controller and so clearing the
325 * BUS_ERROR raised by the slave's NAK.
327 I915_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT);
328 I915_WRITE(GMBUS1 + reg_offset, 0);
331 /* Mark the GMBUS interface as disabled after waiting for idle.
332 * We will re-enable it at the start of the next xfer,
333 * till then let it sleep.
335 if (wait_for((I915_READ(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0, 10))
336 DRM_INFO("GMBUS [%s] timed out waiting for idle\n",
338 I915_WRITE(GMBUS0 + reg_offset, 0);
343 DRM_INFO("GMBUS [%s] timed out, falling back to bit banging on pin %d\n",
344 bus->adapter.name, bus->reg0 & 0xff);
345 I915_WRITE(GMBUS0 + reg_offset, 0);
347 /* Hardware may not support GMBUS over these pins?
348 * Try GPIO bitbanging instead.
350 if (!bus->has_gpio) {
353 bus->force_bit = true;
354 ret = intel_i2c_quirk_xfer(bus, msgs, num);
357 mutex_unlock(&dev_priv->gmbus_mutex);
361 static u32 gmbus_func(struct i2c_adapter *adapter)
363 return i2c_bit_algo.functionality(adapter) &
364 (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
365 /* I2C_FUNC_10BIT_ADDR | */
366 I2C_FUNC_SMBUS_READ_BLOCK_DATA |
367 I2C_FUNC_SMBUS_BLOCK_PROC_CALL);
370 static const struct i2c_algorithm gmbus_algorithm = {
371 .master_xfer = gmbus_xfer,
372 .functionality = gmbus_func
376 * intel_gmbus_setup - instantiate all Intel i2c GMBuses
379 int intel_setup_gmbus(struct drm_device *dev)
381 static const char *names[GMBUS_NUM_PORTS] = {
391 struct drm_i915_private *dev_priv = dev->dev_private;
394 if (HAS_PCH_SPLIT(dev))
395 dev_priv->gpio_mmio_base = PCH_GPIOA - GPIOA;
397 dev_priv->gpio_mmio_base = 0;
399 dev_priv->gmbus = kcalloc(GMBUS_NUM_PORTS, sizeof(struct intel_gmbus),
401 if (dev_priv->gmbus == NULL)
404 mutex_init(&dev_priv->gmbus_mutex);
406 for (i = 0; i < GMBUS_NUM_PORTS; i++) {
407 struct intel_gmbus *bus = &dev_priv->gmbus[i];
409 bus->adapter.owner = THIS_MODULE;
410 bus->adapter.class = I2C_CLASS_DDC;
411 snprintf(bus->adapter.name,
412 sizeof(bus->adapter.name),
416 bus->adapter.dev.parent = &dev->pdev->dev;
417 bus->dev_priv = dev_priv;
419 bus->adapter.algo = &gmbus_algorithm;
420 ret = i2c_add_adapter(&bus->adapter);
424 /* By default use a conservative clock rate */
425 bus->reg0 = i | GMBUS_RATE_100KHZ;
427 bus->has_gpio = intel_gpio_setup(bus, i);
430 intel_i2c_reset(dev_priv->dev);
436 struct intel_gmbus *bus = &dev_priv->gmbus[i];
437 i2c_del_adapter(&bus->adapter);
439 kfree(dev_priv->gmbus);
440 dev_priv->gmbus = NULL;
444 void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed)
446 struct intel_gmbus *bus = to_intel_gmbus(adapter);
448 bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | speed;
451 void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
453 struct intel_gmbus *bus = to_intel_gmbus(adapter);
456 bus->force_bit = force_bit;
459 void intel_teardown_gmbus(struct drm_device *dev)
461 struct drm_i915_private *dev_priv = dev->dev_private;
464 if (dev_priv->gmbus == NULL)
467 for (i = 0; i < GMBUS_NUM_PORTS; i++) {
468 struct intel_gmbus *bus = &dev_priv->gmbus[i];
469 i2c_del_adapter(&bus->adapter);
472 kfree(dev_priv->gmbus);
473 dev_priv->gmbus = NULL;