2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2009 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Eric Anholt <eric@anholt.net>
26 * Jesse Barnes <jesse.barnes@intel.com>
29 #include <linux/i2c.h>
30 #include <linux/slab.h>
31 #include <linux/delay.h>
33 #include <drm/drm_crtc.h>
34 #include <drm/drm_edid.h>
35 #include "intel_drv.h"
36 #include <drm/i915_drm.h>
39 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
41 return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
45 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
47 struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
48 struct drm_i915_private *dev_priv = dev->dev_private;
49 uint32_t enabled_bits;
51 enabled_bits = IS_HASWELL(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
53 WARN(I915_READ(intel_hdmi->sdvox_reg) & enabled_bits,
54 "HDMI port enabled, expecting disabled\n");
57 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
59 struct intel_digital_port *intel_dig_port =
60 container_of(encoder, struct intel_digital_port, base.base);
61 return &intel_dig_port->hdmi;
64 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
66 return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
69 void intel_dip_infoframe_csum(struct dip_infoframe *frame)
71 uint8_t *data = (uint8_t *)frame;
78 for (i = 0; i < frame->len + DIP_HEADER_SIZE; i++)
81 frame->checksum = 0x100 - sum;
84 static u32 g4x_infoframe_index(struct dip_infoframe *frame)
86 switch (frame->type) {
88 return VIDEO_DIP_SELECT_AVI;
90 return VIDEO_DIP_SELECT_SPD;
92 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
97 static u32 g4x_infoframe_enable(struct dip_infoframe *frame)
99 switch (frame->type) {
101 return VIDEO_DIP_ENABLE_AVI;
103 return VIDEO_DIP_ENABLE_SPD;
105 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
110 static u32 hsw_infoframe_enable(struct dip_infoframe *frame)
112 switch (frame->type) {
114 return VIDEO_DIP_ENABLE_AVI_HSW;
116 return VIDEO_DIP_ENABLE_SPD_HSW;
118 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
123 static u32 hsw_infoframe_data_reg(struct dip_infoframe *frame, enum pipe pipe)
125 switch (frame->type) {
127 return HSW_TVIDEO_DIP_AVI_DATA(pipe);
129 return HSW_TVIDEO_DIP_SPD_DATA(pipe);
131 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
136 static void g4x_write_infoframe(struct drm_encoder *encoder,
137 struct dip_infoframe *frame)
139 uint32_t *data = (uint32_t *)frame;
140 struct drm_device *dev = encoder->dev;
141 struct drm_i915_private *dev_priv = dev->dev_private;
142 u32 val = I915_READ(VIDEO_DIP_CTL);
143 unsigned i, len = DIP_HEADER_SIZE + frame->len;
145 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
147 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
148 val |= g4x_infoframe_index(frame);
150 val &= ~g4x_infoframe_enable(frame);
152 I915_WRITE(VIDEO_DIP_CTL, val);
155 for (i = 0; i < len; i += 4) {
156 I915_WRITE(VIDEO_DIP_DATA, *data);
159 /* Write every possible data byte to force correct ECC calculation. */
160 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
161 I915_WRITE(VIDEO_DIP_DATA, 0);
164 val |= g4x_infoframe_enable(frame);
165 val &= ~VIDEO_DIP_FREQ_MASK;
166 val |= VIDEO_DIP_FREQ_VSYNC;
168 I915_WRITE(VIDEO_DIP_CTL, val);
169 POSTING_READ(VIDEO_DIP_CTL);
172 static void ibx_write_infoframe(struct drm_encoder *encoder,
173 struct dip_infoframe *frame)
175 uint32_t *data = (uint32_t *)frame;
176 struct drm_device *dev = encoder->dev;
177 struct drm_i915_private *dev_priv = dev->dev_private;
178 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
179 int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
180 unsigned i, len = DIP_HEADER_SIZE + frame->len;
181 u32 val = I915_READ(reg);
183 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
185 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
186 val |= g4x_infoframe_index(frame);
188 val &= ~g4x_infoframe_enable(frame);
190 I915_WRITE(reg, val);
193 for (i = 0; i < len; i += 4) {
194 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
197 /* Write every possible data byte to force correct ECC calculation. */
198 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
199 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
202 val |= g4x_infoframe_enable(frame);
203 val &= ~VIDEO_DIP_FREQ_MASK;
204 val |= VIDEO_DIP_FREQ_VSYNC;
206 I915_WRITE(reg, val);
210 static void cpt_write_infoframe(struct drm_encoder *encoder,
211 struct dip_infoframe *frame)
213 uint32_t *data = (uint32_t *)frame;
214 struct drm_device *dev = encoder->dev;
215 struct drm_i915_private *dev_priv = dev->dev_private;
216 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
217 int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
218 unsigned i, len = DIP_HEADER_SIZE + frame->len;
219 u32 val = I915_READ(reg);
221 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
223 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
224 val |= g4x_infoframe_index(frame);
226 /* The DIP control register spec says that we need to update the AVI
227 * infoframe without clearing its enable bit */
228 if (frame->type != DIP_TYPE_AVI)
229 val &= ~g4x_infoframe_enable(frame);
231 I915_WRITE(reg, val);
234 for (i = 0; i < len; i += 4) {
235 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
238 /* Write every possible data byte to force correct ECC calculation. */
239 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
240 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
243 val |= g4x_infoframe_enable(frame);
244 val &= ~VIDEO_DIP_FREQ_MASK;
245 val |= VIDEO_DIP_FREQ_VSYNC;
247 I915_WRITE(reg, val);
251 static void vlv_write_infoframe(struct drm_encoder *encoder,
252 struct dip_infoframe *frame)
254 uint32_t *data = (uint32_t *)frame;
255 struct drm_device *dev = encoder->dev;
256 struct drm_i915_private *dev_priv = dev->dev_private;
257 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
258 int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
259 unsigned i, len = DIP_HEADER_SIZE + frame->len;
260 u32 val = I915_READ(reg);
262 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
264 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
265 val |= g4x_infoframe_index(frame);
267 val &= ~g4x_infoframe_enable(frame);
269 I915_WRITE(reg, val);
272 for (i = 0; i < len; i += 4) {
273 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
276 /* Write every possible data byte to force correct ECC calculation. */
277 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
278 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
281 val |= g4x_infoframe_enable(frame);
282 val &= ~VIDEO_DIP_FREQ_MASK;
283 val |= VIDEO_DIP_FREQ_VSYNC;
285 I915_WRITE(reg, val);
289 static void hsw_write_infoframe(struct drm_encoder *encoder,
290 struct dip_infoframe *frame)
292 uint32_t *data = (uint32_t *)frame;
293 struct drm_device *dev = encoder->dev;
294 struct drm_i915_private *dev_priv = dev->dev_private;
295 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
296 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->pipe);
297 u32 data_reg = hsw_infoframe_data_reg(frame, intel_crtc->pipe);
298 unsigned int i, len = DIP_HEADER_SIZE + frame->len;
299 u32 val = I915_READ(ctl_reg);
304 val &= ~hsw_infoframe_enable(frame);
305 I915_WRITE(ctl_reg, val);
308 for (i = 0; i < len; i += 4) {
309 I915_WRITE(data_reg + i, *data);
312 /* Write every possible data byte to force correct ECC calculation. */
313 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
314 I915_WRITE(data_reg + i, 0);
317 val |= hsw_infoframe_enable(frame);
318 I915_WRITE(ctl_reg, val);
319 POSTING_READ(ctl_reg);
322 static void intel_set_infoframe(struct drm_encoder *encoder,
323 struct dip_infoframe *frame)
325 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
327 intel_dip_infoframe_csum(frame);
328 intel_hdmi->write_infoframe(encoder, frame);
331 static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
332 struct drm_display_mode *adjusted_mode)
334 struct dip_infoframe avi_if = {
335 .type = DIP_TYPE_AVI,
336 .ver = DIP_VERSION_AVI,
340 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
341 avi_if.body.avi.YQ_CN_PR |= DIP_AVI_PR_2;
343 avi_if.body.avi.VIC = drm_mode_cea_vic(adjusted_mode);
345 intel_set_infoframe(encoder, &avi_if);
348 static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
350 struct dip_infoframe spd_if;
352 memset(&spd_if, 0, sizeof(spd_if));
353 spd_if.type = DIP_TYPE_SPD;
354 spd_if.ver = DIP_VERSION_SPD;
355 spd_if.len = DIP_LEN_SPD;
356 strcpy(spd_if.body.spd.vn, "Intel");
357 strcpy(spd_if.body.spd.pd, "Integrated gfx");
358 spd_if.body.spd.sdi = DIP_SPD_PC;
360 intel_set_infoframe(encoder, &spd_if);
363 static void g4x_set_infoframes(struct drm_encoder *encoder,
364 struct drm_display_mode *adjusted_mode)
366 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
367 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
368 u32 reg = VIDEO_DIP_CTL;
369 u32 val = I915_READ(reg);
372 assert_hdmi_port_disabled(intel_hdmi);
374 /* If the registers were not initialized yet, they might be zeroes,
375 * which means we're selecting the AVI DIP and we're setting its
376 * frequency to once. This seems to really confuse the HW and make
377 * things stop working (the register spec says the AVI always needs to
378 * be sent every VSync). So here we avoid writing to the register more
379 * than we need and also explicitly select the AVI DIP and explicitly
380 * set its frequency to every VSync. Avoiding to write it twice seems to
381 * be enough to solve the problem, but being defensive shouldn't hurt us
383 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
385 if (!intel_hdmi->has_hdmi_sink) {
386 if (!(val & VIDEO_DIP_ENABLE))
388 val &= ~VIDEO_DIP_ENABLE;
389 I915_WRITE(reg, val);
394 switch (intel_hdmi->sdvox_reg) {
396 port = VIDEO_DIP_PORT_B;
399 port = VIDEO_DIP_PORT_C;
406 if (port != (val & VIDEO_DIP_PORT_MASK)) {
407 if (val & VIDEO_DIP_ENABLE) {
408 val &= ~VIDEO_DIP_ENABLE;
409 I915_WRITE(reg, val);
412 val &= ~VIDEO_DIP_PORT_MASK;
416 val |= VIDEO_DIP_ENABLE;
417 val &= ~VIDEO_DIP_ENABLE_VENDOR;
419 I915_WRITE(reg, val);
422 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
423 intel_hdmi_set_spd_infoframe(encoder);
426 static void ibx_set_infoframes(struct drm_encoder *encoder,
427 struct drm_display_mode *adjusted_mode)
429 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
430 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
431 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
432 u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
433 u32 val = I915_READ(reg);
436 assert_hdmi_port_disabled(intel_hdmi);
438 /* See the big comment in g4x_set_infoframes() */
439 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
441 if (!intel_hdmi->has_hdmi_sink) {
442 if (!(val & VIDEO_DIP_ENABLE))
444 val &= ~VIDEO_DIP_ENABLE;
445 I915_WRITE(reg, val);
450 switch (intel_hdmi->sdvox_reg) {
452 port = VIDEO_DIP_PORT_B;
455 port = VIDEO_DIP_PORT_C;
458 port = VIDEO_DIP_PORT_D;
465 if (port != (val & VIDEO_DIP_PORT_MASK)) {
466 if (val & VIDEO_DIP_ENABLE) {
467 val &= ~VIDEO_DIP_ENABLE;
468 I915_WRITE(reg, val);
471 val &= ~VIDEO_DIP_PORT_MASK;
475 val |= VIDEO_DIP_ENABLE;
476 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
477 VIDEO_DIP_ENABLE_GCP);
479 I915_WRITE(reg, val);
482 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
483 intel_hdmi_set_spd_infoframe(encoder);
486 static void cpt_set_infoframes(struct drm_encoder *encoder,
487 struct drm_display_mode *adjusted_mode)
489 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
490 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
491 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
492 u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
493 u32 val = I915_READ(reg);
495 assert_hdmi_port_disabled(intel_hdmi);
497 /* See the big comment in g4x_set_infoframes() */
498 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
500 if (!intel_hdmi->has_hdmi_sink) {
501 if (!(val & VIDEO_DIP_ENABLE))
503 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI);
504 I915_WRITE(reg, val);
509 /* Set both together, unset both together: see the spec. */
510 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
511 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
512 VIDEO_DIP_ENABLE_GCP);
514 I915_WRITE(reg, val);
517 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
518 intel_hdmi_set_spd_infoframe(encoder);
521 static void vlv_set_infoframes(struct drm_encoder *encoder,
522 struct drm_display_mode *adjusted_mode)
524 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
525 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
526 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
527 u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
528 u32 val = I915_READ(reg);
530 assert_hdmi_port_disabled(intel_hdmi);
532 /* See the big comment in g4x_set_infoframes() */
533 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
535 if (!intel_hdmi->has_hdmi_sink) {
536 if (!(val & VIDEO_DIP_ENABLE))
538 val &= ~VIDEO_DIP_ENABLE;
539 I915_WRITE(reg, val);
544 val |= VIDEO_DIP_ENABLE;
545 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
546 VIDEO_DIP_ENABLE_GCP);
548 I915_WRITE(reg, val);
551 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
552 intel_hdmi_set_spd_infoframe(encoder);
555 static void hsw_set_infoframes(struct drm_encoder *encoder,
556 struct drm_display_mode *adjusted_mode)
558 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
559 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
560 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
561 u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->pipe);
562 u32 val = I915_READ(reg);
564 assert_hdmi_port_disabled(intel_hdmi);
566 if (!intel_hdmi->has_hdmi_sink) {
572 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
573 VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW);
575 I915_WRITE(reg, val);
578 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
579 intel_hdmi_set_spd_infoframe(encoder);
582 static void intel_hdmi_mode_set(struct drm_encoder *encoder,
583 struct drm_display_mode *mode,
584 struct drm_display_mode *adjusted_mode)
586 struct drm_device *dev = encoder->dev;
587 struct drm_i915_private *dev_priv = dev->dev_private;
588 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
589 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
592 sdvox = SDVO_ENCODING_HDMI;
593 if (!HAS_PCH_SPLIT(dev))
594 sdvox |= intel_hdmi->color_range;
595 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
596 sdvox |= SDVO_VSYNC_ACTIVE_HIGH;
597 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
598 sdvox |= SDVO_HSYNC_ACTIVE_HIGH;
600 if (intel_crtc->bpp > 24)
601 sdvox |= COLOR_FORMAT_12bpc;
603 sdvox |= COLOR_FORMAT_8bpc;
605 /* Required on CPT */
606 if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev))
607 sdvox |= HDMI_MODE_SELECT;
609 if (intel_hdmi->has_audio) {
610 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
611 pipe_name(intel_crtc->pipe));
612 sdvox |= SDVO_AUDIO_ENABLE;
613 sdvox |= SDVO_NULL_PACKETS_DURING_VSYNC;
614 intel_write_eld(encoder, adjusted_mode);
617 if (HAS_PCH_CPT(dev))
618 sdvox |= PORT_TRANS_SEL_CPT(intel_crtc->pipe);
619 else if (intel_crtc->pipe == PIPE_B)
620 sdvox |= SDVO_PIPE_B_SELECT;
622 I915_WRITE(intel_hdmi->sdvox_reg, sdvox);
623 POSTING_READ(intel_hdmi->sdvox_reg);
625 intel_hdmi->set_infoframes(encoder, adjusted_mode);
628 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
631 struct drm_device *dev = encoder->base.dev;
632 struct drm_i915_private *dev_priv = dev->dev_private;
633 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
636 tmp = I915_READ(intel_hdmi->sdvox_reg);
638 if (!(tmp & SDVO_ENABLE))
641 if (HAS_PCH_CPT(dev))
642 *pipe = PORT_TO_PIPE_CPT(tmp);
644 *pipe = PORT_TO_PIPE(tmp);
649 static void intel_enable_hdmi(struct intel_encoder *encoder)
651 struct drm_device *dev = encoder->base.dev;
652 struct drm_i915_private *dev_priv = dev->dev_private;
653 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
655 u32 enable_bits = SDVO_ENABLE;
657 if (intel_hdmi->has_audio)
658 enable_bits |= SDVO_AUDIO_ENABLE;
660 temp = I915_READ(intel_hdmi->sdvox_reg);
662 /* HW workaround for IBX, we need to move the port to transcoder A
663 * before disabling it. */
664 if (HAS_PCH_IBX(dev)) {
665 struct drm_crtc *crtc = encoder->base.crtc;
666 int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
668 /* Restore the transcoder select bit. */
670 enable_bits |= SDVO_PIPE_B_SELECT;
673 /* HW workaround, need to toggle enable bit off and on for 12bpc, but
674 * we do this anyway which shows more stable in testing.
676 if (HAS_PCH_SPLIT(dev)) {
677 I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE);
678 POSTING_READ(intel_hdmi->sdvox_reg);
683 I915_WRITE(intel_hdmi->sdvox_reg, temp);
684 POSTING_READ(intel_hdmi->sdvox_reg);
686 /* HW workaround, need to write this twice for issue that may result
687 * in first write getting masked.
689 if (HAS_PCH_SPLIT(dev)) {
690 I915_WRITE(intel_hdmi->sdvox_reg, temp);
691 POSTING_READ(intel_hdmi->sdvox_reg);
695 static void intel_disable_hdmi(struct intel_encoder *encoder)
697 struct drm_device *dev = encoder->base.dev;
698 struct drm_i915_private *dev_priv = dev->dev_private;
699 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
701 u32 enable_bits = SDVO_ENABLE | SDVO_AUDIO_ENABLE;
703 temp = I915_READ(intel_hdmi->sdvox_reg);
705 /* HW workaround for IBX, we need to move the port to transcoder A
706 * before disabling it. */
707 if (HAS_PCH_IBX(dev)) {
708 struct drm_crtc *crtc = encoder->base.crtc;
709 int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
711 if (temp & SDVO_PIPE_B_SELECT) {
712 temp &= ~SDVO_PIPE_B_SELECT;
713 I915_WRITE(intel_hdmi->sdvox_reg, temp);
714 POSTING_READ(intel_hdmi->sdvox_reg);
716 /* Again we need to write this twice. */
717 I915_WRITE(intel_hdmi->sdvox_reg, temp);
718 POSTING_READ(intel_hdmi->sdvox_reg);
720 /* Transcoder selection bits only update
721 * effectively on vblank. */
723 intel_wait_for_vblank(dev, pipe);
729 /* HW workaround, need to toggle enable bit off and on for 12bpc, but
730 * we do this anyway which shows more stable in testing.
732 if (HAS_PCH_SPLIT(dev)) {
733 I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE);
734 POSTING_READ(intel_hdmi->sdvox_reg);
737 temp &= ~enable_bits;
739 I915_WRITE(intel_hdmi->sdvox_reg, temp);
740 POSTING_READ(intel_hdmi->sdvox_reg);
742 /* HW workaround, need to write this twice for issue that may result
743 * in first write getting masked.
745 if (HAS_PCH_SPLIT(dev)) {
746 I915_WRITE(intel_hdmi->sdvox_reg, temp);
747 POSTING_READ(intel_hdmi->sdvox_reg);
751 static int intel_hdmi_mode_valid(struct drm_connector *connector,
752 struct drm_display_mode *mode)
754 if (mode->clock > 165000)
755 return MODE_CLOCK_HIGH;
756 if (mode->clock < 20000)
757 return MODE_CLOCK_LOW;
759 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
760 return MODE_NO_DBLESCAN;
765 bool intel_hdmi_mode_fixup(struct drm_encoder *encoder,
766 const struct drm_display_mode *mode,
767 struct drm_display_mode *adjusted_mode)
772 static bool g4x_hdmi_connected(struct intel_hdmi *intel_hdmi)
774 struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
775 struct drm_i915_private *dev_priv = dev->dev_private;
778 switch (intel_hdmi->sdvox_reg) {
780 bit = HDMIB_HOTPLUG_LIVE_STATUS;
783 bit = HDMIC_HOTPLUG_LIVE_STATUS;
790 return I915_READ(PORT_HOTPLUG_STAT) & bit;
793 static enum drm_connector_status
794 intel_hdmi_detect(struct drm_connector *connector, bool force)
796 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
797 struct intel_digital_port *intel_dig_port =
798 hdmi_to_dig_port(intel_hdmi);
799 struct intel_encoder *intel_encoder = &intel_dig_port->base;
800 struct drm_i915_private *dev_priv = connector->dev->dev_private;
802 enum drm_connector_status status = connector_status_disconnected;
804 if (IS_G4X(connector->dev) && !g4x_hdmi_connected(intel_hdmi))
807 intel_hdmi->has_hdmi_sink = false;
808 intel_hdmi->has_audio = false;
809 edid = drm_get_edid(connector,
810 intel_gmbus_get_adapter(dev_priv,
811 intel_hdmi->ddc_bus));
814 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
815 status = connector_status_connected;
816 if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
817 intel_hdmi->has_hdmi_sink =
818 drm_detect_hdmi_monitor(edid);
819 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
824 if (status == connector_status_connected) {
825 if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
826 intel_hdmi->has_audio =
827 (intel_hdmi->force_audio == HDMI_AUDIO_ON);
828 intel_encoder->type = INTEL_OUTPUT_HDMI;
834 static int intel_hdmi_get_modes(struct drm_connector *connector)
836 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
837 struct drm_i915_private *dev_priv = connector->dev->dev_private;
839 /* We should parse the EDID data and find out if it's an HDMI sink so
840 * we can send audio to it.
843 return intel_ddc_get_modes(connector,
844 intel_gmbus_get_adapter(dev_priv,
845 intel_hdmi->ddc_bus));
849 intel_hdmi_detect_audio(struct drm_connector *connector)
851 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
852 struct drm_i915_private *dev_priv = connector->dev->dev_private;
854 bool has_audio = false;
856 edid = drm_get_edid(connector,
857 intel_gmbus_get_adapter(dev_priv,
858 intel_hdmi->ddc_bus));
860 if (edid->input & DRM_EDID_INPUT_DIGITAL)
861 has_audio = drm_detect_monitor_audio(edid);
869 intel_hdmi_set_property(struct drm_connector *connector,
870 struct drm_property *property,
873 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
874 struct intel_digital_port *intel_dig_port =
875 hdmi_to_dig_port(intel_hdmi);
876 struct drm_i915_private *dev_priv = connector->dev->dev_private;
879 ret = drm_object_property_set_value(&connector->base, property, val);
883 if (property == dev_priv->force_audio_property) {
884 enum hdmi_force_audio i = val;
887 if (i == intel_hdmi->force_audio)
890 intel_hdmi->force_audio = i;
892 if (i == HDMI_AUDIO_AUTO)
893 has_audio = intel_hdmi_detect_audio(connector);
895 has_audio = (i == HDMI_AUDIO_ON);
897 if (i == HDMI_AUDIO_OFF_DVI)
898 intel_hdmi->has_hdmi_sink = 0;
900 intel_hdmi->has_audio = has_audio;
904 if (property == dev_priv->broadcast_rgb_property) {
905 if (val == !!intel_hdmi->color_range)
908 intel_hdmi->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0;
915 if (intel_dig_port->base.base.crtc) {
916 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
917 intel_set_mode(crtc, &crtc->mode,
918 crtc->x, crtc->y, crtc->fb);
924 static void intel_hdmi_destroy(struct drm_connector *connector)
926 drm_sysfs_connector_remove(connector);
927 drm_connector_cleanup(connector);
931 static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = {
932 .mode_fixup = intel_hdmi_mode_fixup,
933 .mode_set = intel_hdmi_mode_set,
934 .disable = intel_encoder_noop,
937 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
938 .dpms = intel_connector_dpms,
939 .detect = intel_hdmi_detect,
940 .fill_modes = drm_helper_probe_single_connector_modes,
941 .set_property = intel_hdmi_set_property,
942 .destroy = intel_hdmi_destroy,
945 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
946 .get_modes = intel_hdmi_get_modes,
947 .mode_valid = intel_hdmi_mode_valid,
948 .best_encoder = intel_best_encoder,
951 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
952 .destroy = intel_encoder_destroy,
956 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
958 intel_attach_force_audio_property(connector);
959 intel_attach_broadcast_rgb_property(connector);
962 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
963 struct intel_connector *intel_connector)
965 struct drm_connector *connector = &intel_connector->base;
966 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
967 struct intel_encoder *intel_encoder = &intel_dig_port->base;
968 struct drm_device *dev = intel_encoder->base.dev;
969 struct drm_i915_private *dev_priv = dev->dev_private;
970 enum port port = intel_dig_port->port;
972 drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
973 DRM_MODE_CONNECTOR_HDMIA);
974 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
976 connector->polled = DRM_CONNECTOR_POLL_HPD;
977 connector->interlace_allowed = 1;
978 connector->doublescan_allowed = 0;
982 intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
983 dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS;
986 intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
987 dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS;
990 intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
991 dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS;
994 /* Internal port only for eDP. */
999 if (!HAS_PCH_SPLIT(dev)) {
1000 intel_hdmi->write_infoframe = g4x_write_infoframe;
1001 intel_hdmi->set_infoframes = g4x_set_infoframes;
1002 } else if (IS_VALLEYVIEW(dev)) {
1003 intel_hdmi->write_infoframe = vlv_write_infoframe;
1004 intel_hdmi->set_infoframes = vlv_set_infoframes;
1005 } else if (IS_HASWELL(dev)) {
1006 intel_hdmi->write_infoframe = hsw_write_infoframe;
1007 intel_hdmi->set_infoframes = hsw_set_infoframes;
1008 } else if (HAS_PCH_IBX(dev)) {
1009 intel_hdmi->write_infoframe = ibx_write_infoframe;
1010 intel_hdmi->set_infoframes = ibx_set_infoframes;
1012 intel_hdmi->write_infoframe = cpt_write_infoframe;
1013 intel_hdmi->set_infoframes = cpt_set_infoframes;
1016 if (IS_HASWELL(dev))
1017 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
1019 intel_connector->get_hw_state = intel_connector_get_hw_state;
1021 intel_hdmi_add_properties(intel_hdmi, connector);
1023 intel_connector_attach_encoder(intel_connector, intel_encoder);
1024 drm_sysfs_connector_add(connector);
1026 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1027 * 0xd. Failure to do so will result in spurious interrupts being
1028 * generated on the port when a cable is not attached.
1030 if (IS_G4X(dev) && !IS_GM45(dev)) {
1031 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
1032 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
1036 void intel_hdmi_init(struct drm_device *dev, int sdvox_reg, enum port port)
1038 struct intel_digital_port *intel_dig_port;
1039 struct intel_encoder *intel_encoder;
1040 struct drm_encoder *encoder;
1041 struct intel_connector *intel_connector;
1043 intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
1044 if (!intel_dig_port)
1047 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
1048 if (!intel_connector) {
1049 kfree(intel_dig_port);
1053 intel_encoder = &intel_dig_port->base;
1054 encoder = &intel_encoder->base;
1056 drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
1057 DRM_MODE_ENCODER_TMDS);
1058 drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs);
1060 intel_encoder->enable = intel_enable_hdmi;
1061 intel_encoder->disable = intel_disable_hdmi;
1062 intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
1064 intel_encoder->type = INTEL_OUTPUT_HDMI;
1065 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
1066 intel_encoder->cloneable = false;
1068 intel_dig_port->port = port;
1069 intel_dig_port->hdmi.sdvox_reg = sdvox_reg;
1070 intel_dig_port->dp.output_reg = 0;
1072 intel_hdmi_init_connector(intel_dig_port, intel_connector);