Pileus Git - ~andy/linux/blob - drivers/gpu/drm/i915/intel_hdmi.c

   1 /*
   2  * Copyright 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright © 2006-2009 Intel Corporation
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *      Eric Anholt <eric@anholt.net>
  26  *      Jesse Barnes <jesse.barnes@intel.com>
  27  */
  28
  29 #include <linux/i2c.h>
  30 #include <linux/slab.h>
  31 #include <linux/delay.h>
  32 #include <linux/hdmi.h>
  33 #include <drm/drmP.h>
  34 #include <drm/drm_crtc.h>
  35 #include <drm/drm_edid.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39
  40 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
  41 {
  42         return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
  43 }
  44
  45 static void
  46 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
  47 {
  48         struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
  49         struct drm_i915_private *dev_priv = dev->dev_private;
  50         uint32_t enabled_bits;
  51
  52         enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
  53
  54         WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
  55              "HDMI port enabled, expecting disabled\n");
  56 }
  57
  58 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
  59 {
  60         struct intel_digital_port *intel_dig_port =
  61                 container_of(encoder, struct intel_digital_port, base.base);
  62         return &intel_dig_port->hdmi;
  63 }
  64
  65 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
  66 {
  67         return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
  68 }
  69
  70 static u32 g4x_infoframe_index(enum hdmi_infoframe_type type)
  71 {
  72         switch (type) {
  73         case HDMI_INFOFRAME_TYPE_AVI:
  74                 return VIDEO_DIP_SELECT_AVI;
  75         case HDMI_INFOFRAME_TYPE_SPD:
  76                 return VIDEO_DIP_SELECT_SPD;
  77         default:
  78                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
  79                 return 0;
  80         }
  81 }
  82
  83 static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type)
  84 {
  85         switch (type) {
  86         case HDMI_INFOFRAME_TYPE_AVI:
  87                 return VIDEO_DIP_ENABLE_AVI;
  88         case HDMI_INFOFRAME_TYPE_SPD:
  89                 return VIDEO_DIP_ENABLE_SPD;
  90         default:
  91                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
  92                 return 0;
  93         }
  94 }
  95
  96 static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type)
  97 {
  98         switch (type) {
  99         case HDMI_INFOFRAME_TYPE_AVI:
 100                 return VIDEO_DIP_ENABLE_AVI_HSW;
 101         case HDMI_INFOFRAME_TYPE_SPD:
 102                 return VIDEO_DIP_ENABLE_SPD_HSW;
 103         default:
 104                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
 105                 return 0;
 106         }
 107 }
 108
 109 static u32 hsw_infoframe_data_reg(enum hdmi_infoframe_type type,
 110                                   enum transcoder cpu_transcoder)
 111 {
 112         switch (type) {
 113         case HDMI_INFOFRAME_TYPE_AVI:
 114                 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder);
 115         case HDMI_INFOFRAME_TYPE_SPD:
 116                 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder);
 117         default:
 118                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
 119                 return 0;
 120         }
 121 }
 122
 123 static void g4x_write_infoframe(struct drm_encoder *encoder,
 124                                 enum hdmi_infoframe_type type,
 125                                 const uint8_t *frame, ssize_t len)
 126 {
 127         uint32_t *data = (uint32_t *)frame;
 128         struct drm_device *dev = encoder->dev;
 129         struct drm_i915_private *dev_priv = dev->dev_private;
 130         u32 val = I915_READ(VIDEO_DIP_CTL);
 131         int i;
 132
 133         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 134
 135         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 136         val |= g4x_infoframe_index(type);
 137
 138         val &= ~g4x_infoframe_enable(type);
 139
 140         I915_WRITE(VIDEO_DIP_CTL, val);
 141
 142         mmiowb();
 143         for (i = 0; i < len; i += 4) {
 144                 I915_WRITE(VIDEO_DIP_DATA, *data);
 145                 data++;
 146         }
 147         /* Write every possible data byte to force correct ECC calculation. */
 148         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 149                 I915_WRITE(VIDEO_DIP_DATA, 0);
 150         mmiowb();
 151
 152         val |= g4x_infoframe_enable(type);
 153         val &= ~VIDEO_DIP_FREQ_MASK;
 154         val |= VIDEO_DIP_FREQ_VSYNC;
 155
 156         I915_WRITE(VIDEO_DIP_CTL, val);
 157         POSTING_READ(VIDEO_DIP_CTL);
 158 }
 159
 160 static void ibx_write_infoframe(struct drm_encoder *encoder,
 161                                 enum hdmi_infoframe_type type,
 162                                 const uint8_t *frame, ssize_t len)
 163 {
 164         uint32_t *data = (uint32_t *)frame;
 165         struct drm_device *dev = encoder->dev;
 166         struct drm_i915_private *dev_priv = dev->dev_private;
 167         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 168         int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 169         u32 val = I915_READ(reg);
 170
 171         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 172
 173         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 174         val |= g4x_infoframe_index(type);
 175
 176         val &= ~g4x_infoframe_enable(type);
 177
 178         I915_WRITE(reg, val);
 179
 180         mmiowb();
 181         for (i = 0; i < len; i += 4) {
 182                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 183                 data++;
 184         }
 185         /* Write every possible data byte to force correct ECC calculation. */
 186         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 187                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 188         mmiowb();
 189
 190         val |= g4x_infoframe_enable(type);
 191         val &= ~VIDEO_DIP_FREQ_MASK;
 192         val |= VIDEO_DIP_FREQ_VSYNC;
 193
 194         I915_WRITE(reg, val);
 195         POSTING_READ(reg);
 196 }
 197
 198 static void cpt_write_infoframe(struct drm_encoder *encoder,
 199                                 enum hdmi_infoframe_type type,
 200                                 const uint8_t *frame, ssize_t len)
 201 {
 202         uint32_t *data = (uint32_t *)frame;
 203         struct drm_device *dev = encoder->dev;
 204         struct drm_i915_private *dev_priv = dev->dev_private;
 205         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 206         int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 207         u32 val = I915_READ(reg);
 208
 209         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 210
 211         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 212         val |= g4x_infoframe_index(type);
 213
 214         /* The DIP control register spec says that we need to update the AVI
 215          * infoframe without clearing its enable bit */
 216         if (type != HDMI_INFOFRAME_TYPE_AVI)
 217                 val &= ~g4x_infoframe_enable(type);
 218
 219         I915_WRITE(reg, val);
 220
 221         mmiowb();
 222         for (i = 0; i < len; i += 4) {
 223                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 224                 data++;
 225         }
 226         /* Write every possible data byte to force correct ECC calculation. */
 227         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 228                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 229         mmiowb();
 230
 231         val |= g4x_infoframe_enable(type);
 232         val &= ~VIDEO_DIP_FREQ_MASK;
 233         val |= VIDEO_DIP_FREQ_VSYNC;
 234
 235         I915_WRITE(reg, val);
 236         POSTING_READ(reg);
 237 }
 238
 239 static void vlv_write_infoframe(struct drm_encoder *encoder,
 240                                 enum hdmi_infoframe_type type,
 241                                 const uint8_t *frame, ssize_t len)
 242 {
 243         uint32_t *data = (uint32_t *)frame;
 244         struct drm_device *dev = encoder->dev;
 245         struct drm_i915_private *dev_priv = dev->dev_private;
 246         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 247         int i, reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 248         u32 val = I915_READ(reg);
 249
 250         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 251
 252         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 253         val |= g4x_infoframe_index(type);
 254
 255         val &= ~g4x_infoframe_enable(type);
 256
 257         I915_WRITE(reg, val);
 258
 259         mmiowb();
 260         for (i = 0; i < len; i += 4) {
 261                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 262                 data++;
 263         }
 264         /* Write every possible data byte to force correct ECC calculation. */
 265         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 266                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 267         mmiowb();
 268
 269         val |= g4x_infoframe_enable(type);
 270         val &= ~VIDEO_DIP_FREQ_MASK;
 271         val |= VIDEO_DIP_FREQ_VSYNC;
 272
 273         I915_WRITE(reg, val);
 274         POSTING_READ(reg);
 275 }
 276
 277 static void hsw_write_infoframe(struct drm_encoder *encoder,
 278                                 enum hdmi_infoframe_type type,
 279                                 const uint8_t *frame, ssize_t len)
 280 {
 281         uint32_t *data = (uint32_t *)frame;
 282         struct drm_device *dev = encoder->dev;
 283         struct drm_i915_private *dev_priv = dev->dev_private;
 284         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 285         u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder);
 286         u32 data_reg;
 287         int i;
 288         u32 val = I915_READ(ctl_reg);
 289
 290         data_reg = hsw_infoframe_data_reg(type,
 291                                           intel_crtc->config.cpu_transcoder);
 292         if (data_reg == 0)
 293                 return;
 294
 295         val &= ~hsw_infoframe_enable(type);
 296         I915_WRITE(ctl_reg, val);
 297
 298         mmiowb();
 299         for (i = 0; i < len; i += 4) {
 300                 I915_WRITE(data_reg + i, *data);
 301                 data++;
 302         }
 303         /* Write every possible data byte to force correct ECC calculation. */
 304         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 305                 I915_WRITE(data_reg + i, 0);
 306         mmiowb();
 307
 308         val |= hsw_infoframe_enable(type);
 309         I915_WRITE(ctl_reg, val);
 310         POSTING_READ(ctl_reg);
 311 }
 312
 313 /*
 314  * The data we write to the DIP data buffer registers is 1 byte bigger than the
 315  * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
 316  * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
 317  * used for both technologies.
 318  *
 319  * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
 320  * DW1:       DB3       | DB2 | DB1 | DB0
 321  * DW2:       DB7       | DB6 | DB5 | DB4
 322  * DW3: ...
 323  *
 324  * (HB is Header Byte, DB is Data Byte)
 325  *
 326  * The hdmi pack() functions don't know about that hardware specific hole so we
 327  * trick them by giving an offset into the buffer and moving back the header
 328  * bytes by one.
 329  */
 330 static void intel_set_infoframe(struct drm_encoder *encoder,
 331                                 union hdmi_infoframe *frame)
 332 {
 333         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 334         uint8_t buffer[VIDEO_DIP_DATA_SIZE];
 335         ssize_t len;
 336
 337         /* see comment above for the reason for this offset */
 338         len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1);
 339         if (len < 0)
 340                 return;
 341
 342         /* Insert the 'hole' (see big comment above) at position 3 */
 343         buffer[0] = buffer[1];
 344         buffer[1] = buffer[2];
 345         buffer[2] = buffer[3];
 346         buffer[3] = 0;
 347         len++;
 348
 349         intel_hdmi->write_infoframe(encoder, frame->any.type, buffer, len);
 350 }
 351
 352 static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
 353                                          struct drm_display_mode *adjusted_mode)
 354 {
 355         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 356         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 357         union hdmi_infoframe frame;
 358         int ret;
 359
 360         ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
 361                                                        adjusted_mode);
 362         if (ret < 0) {
 363                 DRM_ERROR("couldn't fill AVI infoframe\n");
 364                 return;
 365         }
 366
 367         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
 368                 frame.avi.pixel_repeat = 1;
 369
 370         if (intel_hdmi->rgb_quant_range_selectable) {
 371                 if (intel_crtc->config.limited_color_range)
 372                         frame.avi.quantization_range =
 373                                 HDMI_QUANTIZATION_RANGE_LIMITED;
 374                 else
 375                         frame.avi.quantization_range =
 376                                 HDMI_QUANTIZATION_RANGE_FULL;
 377         }
 378
 379         intel_set_infoframe(encoder, &frame);
 380 }
 381
 382 static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
 383 {
 384         union hdmi_infoframe frame;
 385         int ret;
 386
 387         ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx");
 388         if (ret < 0) {
 389                 DRM_ERROR("couldn't fill SPD infoframe\n");
 390                 return;
 391         }
 392
 393         frame.spd.sdi = HDMI_SPD_SDI_PC;
 394
 395         intel_set_infoframe(encoder, &frame);
 396 }
 397
 398 static void g4x_set_infoframes(struct drm_encoder *encoder,
 399                                struct drm_display_mode *adjusted_mode)
 400 {
 401         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 402         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 403         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
 404         u32 reg = VIDEO_DIP_CTL;
 405         u32 val = I915_READ(reg);
 406         u32 port;
 407
 408         assert_hdmi_port_disabled(intel_hdmi);
 409
 410         /* If the registers were not initialized yet, they might be zeroes,
 411          * which means we're selecting the AVI DIP and we're setting its
 412          * frequency to once. This seems to really confuse the HW and make
 413          * things stop working (the register spec says the AVI always needs to
 414          * be sent every VSync). So here we avoid writing to the register more
 415          * than we need and also explicitly select the AVI DIP and explicitly
 416          * set its frequency to every VSync. Avoiding to write it twice seems to
 417          * be enough to solve the problem, but being defensive shouldn't hurt us
 418          * either. */
 419         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 420
 421         if (!intel_hdmi->has_hdmi_sink) {
 422                 if (!(val & VIDEO_DIP_ENABLE))
 423                         return;
 424                 val &= ~VIDEO_DIP_ENABLE;
 425                 I915_WRITE(reg, val);
 426                 POSTING_READ(reg);
 427                 return;
 428         }
 429
 430         switch (intel_dig_port->port) {
 431         case PORT_B:
 432                 port = VIDEO_DIP_PORT_B;
 433                 break;
 434         case PORT_C:
 435                 port = VIDEO_DIP_PORT_C;
 436                 break;
 437         default:
 438                 BUG();
 439                 return;
 440         }
 441
 442         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 443                 if (val & VIDEO_DIP_ENABLE) {
 444                         val &= ~VIDEO_DIP_ENABLE;
 445                         I915_WRITE(reg, val);
 446                         POSTING_READ(reg);
 447                 }
 448                 val &= ~VIDEO_DIP_PORT_MASK;
 449                 val |= port;
 450         }
 451
 452         val |= VIDEO_DIP_ENABLE;
 453         val &= ~VIDEO_DIP_ENABLE_VENDOR;
 454
 455         I915_WRITE(reg, val);
 456         POSTING_READ(reg);
 457
 458         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 459         intel_hdmi_set_spd_infoframe(encoder);
 460 }
 461
 462 static void ibx_set_infoframes(struct drm_encoder *encoder,
 463                                struct drm_display_mode *adjusted_mode)
 464 {
 465         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 466         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 467         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 468         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
 469         u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 470         u32 val = I915_READ(reg);
 471         u32 port;
 472
 473         assert_hdmi_port_disabled(intel_hdmi);
 474
 475         /* See the big comment in g4x_set_infoframes() */
 476         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 477
 478         if (!intel_hdmi->has_hdmi_sink) {
 479                 if (!(val & VIDEO_DIP_ENABLE))
 480                         return;
 481                 val &= ~VIDEO_DIP_ENABLE;
 482                 I915_WRITE(reg, val);
 483                 POSTING_READ(reg);
 484                 return;
 485         }
 486
 487         switch (intel_dig_port->port) {
 488         case PORT_B:
 489                 port = VIDEO_DIP_PORT_B;
 490                 break;
 491         case PORT_C:
 492                 port = VIDEO_DIP_PORT_C;
 493                 break;
 494         case PORT_D:
 495                 port = VIDEO_DIP_PORT_D;
 496                 break;
 497         default:
 498                 BUG();
 499                 return;
 500         }
 501
 502         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 503                 if (val & VIDEO_DIP_ENABLE) {
 504                         val &= ~VIDEO_DIP_ENABLE;
 505                         I915_WRITE(reg, val);
 506                         POSTING_READ(reg);
 507                 }
 508                 val &= ~VIDEO_DIP_PORT_MASK;
 509                 val |= port;
 510         }
 511
 512         val |= VIDEO_DIP_ENABLE;
 513         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 514                  VIDEO_DIP_ENABLE_GCP);
 515
 516         I915_WRITE(reg, val);
 517         POSTING_READ(reg);
 518
 519         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 520         intel_hdmi_set_spd_infoframe(encoder);
 521 }
 522
 523 static void cpt_set_infoframes(struct drm_encoder *encoder,
 524                                struct drm_display_mode *adjusted_mode)
 525 {
 526         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 527         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 528         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 529         u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 530         u32 val = I915_READ(reg);
 531
 532         assert_hdmi_port_disabled(intel_hdmi);
 533
 534         /* See the big comment in g4x_set_infoframes() */
 535         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 536
 537         if (!intel_hdmi->has_hdmi_sink) {
 538                 if (!(val & VIDEO_DIP_ENABLE))
 539                         return;
 540                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI);
 541                 I915_WRITE(reg, val);
 542                 POSTING_READ(reg);
 543                 return;
 544         }
 545
 546         /* Set both together, unset both together: see the spec. */
 547         val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
 548         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 549                  VIDEO_DIP_ENABLE_GCP);
 550
 551         I915_WRITE(reg, val);
 552         POSTING_READ(reg);
 553
 554         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 555         intel_hdmi_set_spd_infoframe(encoder);
 556 }
 557
 558 static void vlv_set_infoframes(struct drm_encoder *encoder,
 559                                struct drm_display_mode *adjusted_mode)
 560 {
 561         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 562         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 563         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 564         u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 565         u32 val = I915_READ(reg);
 566
 567         assert_hdmi_port_disabled(intel_hdmi);
 568
 569         /* See the big comment in g4x_set_infoframes() */
 570         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 571
 572         if (!intel_hdmi->has_hdmi_sink) {
 573                 if (!(val & VIDEO_DIP_ENABLE))
 574                         return;
 575                 val &= ~VIDEO_DIP_ENABLE;
 576                 I915_WRITE(reg, val);
 577                 POSTING_READ(reg);
 578                 return;
 579         }
 580
 581         val |= VIDEO_DIP_ENABLE;
 582         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 583                  VIDEO_DIP_ENABLE_GCP);
 584
 585         I915_WRITE(reg, val);
 586         POSTING_READ(reg);
 587
 588         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 589         intel_hdmi_set_spd_infoframe(encoder);
 590 }
 591
 592 static void hsw_set_infoframes(struct drm_encoder *encoder,
 593                                struct drm_display_mode *adjusted_mode)
 594 {
 595         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 596         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 597         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 598         u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder);
 599         u32 val = I915_READ(reg);
 600
 601         assert_hdmi_port_disabled(intel_hdmi);
 602
 603         if (!intel_hdmi->has_hdmi_sink) {
 604                 I915_WRITE(reg, 0);
 605                 POSTING_READ(reg);
 606                 return;
 607         }
 608
 609         val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
 610                  VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW);
 611
 612         I915_WRITE(reg, val);
 613         POSTING_READ(reg);
 614
 615         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 616         intel_hdmi_set_spd_infoframe(encoder);
 617 }
 618
 619 static void intel_hdmi_mode_set(struct intel_encoder *encoder)
 620 {
 621         struct drm_device *dev = encoder->base.dev;
 622         struct drm_i915_private *dev_priv = dev->dev_private;
 623         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
 624         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 625         struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
 626         u32 hdmi_val;
 627
 628         hdmi_val = SDVO_ENCODING_HDMI;
 629         if (!HAS_PCH_SPLIT(dev))
 630                 hdmi_val |= intel_hdmi->color_range;
 631         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 632                 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
 633         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 634                 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
 635
 636         if (crtc->config.pipe_bpp > 24)
 637                 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
 638         else
 639                 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
 640
 641         /* Required on CPT */
 642         if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev))
 643                 hdmi_val |= HDMI_MODE_SELECT_HDMI;
 644
 645         if (intel_hdmi->has_audio) {
 646                 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
 647                                  pipe_name(crtc->pipe));
 648                 hdmi_val |= SDVO_AUDIO_ENABLE;
 649                 hdmi_val |= HDMI_MODE_SELECT_HDMI;
 650                 intel_write_eld(&encoder->base, adjusted_mode);
 651         }
 652
 653         if (HAS_PCH_CPT(dev))
 654                 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
 655         else
 656                 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
 657
 658         I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
 659         POSTING_READ(intel_hdmi->hdmi_reg);
 660
 661         intel_hdmi->set_infoframes(&encoder->base, adjusted_mode);
 662 }
 663
 664 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
 665                                     enum pipe *pipe)
 666 {
 667         struct drm_device *dev = encoder->base.dev;
 668         struct drm_i915_private *dev_priv = dev->dev_private;
 669         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 670         u32 tmp;
 671
 672         tmp = I915_READ(intel_hdmi->hdmi_reg);
 673
 674         if (!(tmp & SDVO_ENABLE))
 675                 return false;
 676
 677         if (HAS_PCH_CPT(dev))
 678                 *pipe = PORT_TO_PIPE_CPT(tmp);
 679         else
 680                 *pipe = PORT_TO_PIPE(tmp);
 681
 682         return true;
 683 }
 684
 685 static void intel_hdmi_get_config(struct intel_encoder *encoder,
 686                                   struct intel_crtc_config *pipe_config)
 687 {
 688         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 689         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 690         u32 tmp, flags = 0;
 691
 692         tmp = I915_READ(intel_hdmi->hdmi_reg);
 693
 694         if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
 695                 flags |= DRM_MODE_FLAG_PHSYNC;
 696         else
 697                 flags |= DRM_MODE_FLAG_NHSYNC;
 698
 699         if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
 700                 flags |= DRM_MODE_FLAG_PVSYNC;
 701         else
 702                 flags |= DRM_MODE_FLAG_NVSYNC;
 703
 704         pipe_config->adjusted_mode.flags |= flags;
 705 }
 706
 707 static void intel_enable_hdmi(struct intel_encoder *encoder)
 708 {
 709         struct drm_device *dev = encoder->base.dev;
 710         struct drm_i915_private *dev_priv = dev->dev_private;
 711         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 712         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 713         u32 temp;
 714         u32 enable_bits = SDVO_ENABLE;
 715
 716         if (intel_hdmi->has_audio)
 717                 enable_bits |= SDVO_AUDIO_ENABLE;
 718
 719         temp = I915_READ(intel_hdmi->hdmi_reg);
 720
 721         /* HW workaround for IBX, we need to move the port to transcoder A
 722          * before disabling it, so restore the transcoder select bit here. */
 723         if (HAS_PCH_IBX(dev))
 724                 enable_bits |= SDVO_PIPE_SEL(intel_crtc->pipe);
 725
 726         /* HW workaround, need to toggle enable bit off and on for 12bpc, but
 727          * we do this anyway which shows more stable in testing.
 728          */
 729         if (HAS_PCH_SPLIT(dev)) {
 730                 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
 731                 POSTING_READ(intel_hdmi->hdmi_reg);
 732         }
 733
 734         temp |= enable_bits;
 735
 736         I915_WRITE(intel_hdmi->hdmi_reg, temp);
 737         POSTING_READ(intel_hdmi->hdmi_reg);
 738
 739         /* HW workaround, need to write this twice for issue that may result
 740          * in first write getting masked.
 741          */
 742         if (HAS_PCH_SPLIT(dev)) {
 743                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
 744                 POSTING_READ(intel_hdmi->hdmi_reg);
 745         }
 746 }
 747
 748 static void vlv_enable_hdmi(struct intel_encoder *encoder)
 749 {
 750 }
 751
 752 static void intel_disable_hdmi(struct intel_encoder *encoder)
 753 {
 754         struct drm_device *dev = encoder->base.dev;
 755         struct drm_i915_private *dev_priv = dev->dev_private;
 756         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 757         u32 temp;
 758         u32 enable_bits = SDVO_ENABLE | SDVO_AUDIO_ENABLE;
 759
 760         temp = I915_READ(intel_hdmi->hdmi_reg);
 761
 762         /* HW workaround for IBX, we need to move the port to transcoder A
 763          * before disabling it. */
 764         if (HAS_PCH_IBX(dev)) {
 765                 struct drm_crtc *crtc = encoder->base.crtc;
 766                 int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
 767
 768                 if (temp & SDVO_PIPE_B_SELECT) {
 769                         temp &= ~SDVO_PIPE_B_SELECT;
 770                         I915_WRITE(intel_hdmi->hdmi_reg, temp);
 771                         POSTING_READ(intel_hdmi->hdmi_reg);
 772
 773                         /* Again we need to write this twice. */
 774                         I915_WRITE(intel_hdmi->hdmi_reg, temp);
 775                         POSTING_READ(intel_hdmi->hdmi_reg);
 776
 777                         /* Transcoder selection bits only update
 778                          * effectively on vblank. */
 779                         if (crtc)
 780                                 intel_wait_for_vblank(dev, pipe);
 781                         else
 782                                 msleep(50);
 783                 }
 784         }
 785
 786         /* HW workaround, need to toggle enable bit off and on for 12bpc, but
 787          * we do this anyway which shows more stable in testing.
 788          */
 789         if (HAS_PCH_SPLIT(dev)) {
 790                 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
 791                 POSTING_READ(intel_hdmi->hdmi_reg);
 792         }
 793
 794         temp &= ~enable_bits;
 795
 796         I915_WRITE(intel_hdmi->hdmi_reg, temp);
 797         POSTING_READ(intel_hdmi->hdmi_reg);
 798
 799         /* HW workaround, need to write this twice for issue that may result
 800          * in first write getting masked.
 801          */
 802         if (HAS_PCH_SPLIT(dev)) {
 803                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
 804                 POSTING_READ(intel_hdmi->hdmi_reg);
 805         }
 806 }
 807
 808 static int intel_hdmi_mode_valid(struct drm_connector *connector,
 809                                  struct drm_display_mode *mode)
 810 {
 811         if (mode->clock > 165000)
 812                 return MODE_CLOCK_HIGH;
 813         if (mode->clock < 20000)
 814                 return MODE_CLOCK_LOW;
 815
 816         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 817                 return MODE_NO_DBLESCAN;
 818
 819         return MODE_OK;
 820 }
 821
 822 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
 823                                struct intel_crtc_config *pipe_config)
 824 {
 825         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 826         struct drm_device *dev = encoder->base.dev;
 827         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
 828         int clock_12bpc = pipe_config->requested_mode.clock * 3 / 2;
 829         int desired_bpp;
 830
 831         if (intel_hdmi->color_range_auto) {
 832                 /* See CEA-861-E - 5.1 Default Encoding Parameters */
 833                 if (intel_hdmi->has_hdmi_sink &&
 834                     drm_match_cea_mode(adjusted_mode) > 1)
 835                         intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235;
 836                 else
 837                         intel_hdmi->color_range = 0;
 838         }
 839
 840         if (intel_hdmi->color_range)
 841                 pipe_config->limited_color_range = true;
 842
 843         if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev))
 844                 pipe_config->has_pch_encoder = true;
 845
 846         /*
 847          * HDMI is either 12 or 8, so if the display lets 10bpc sneak
 848          * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi
 849          * outputs. We also need to check that the higher clock still fits
 850          * within limits.
 851          */
 852         if (pipe_config->pipe_bpp > 8*3 && clock_12bpc <= 225000
 853             && HAS_PCH_SPLIT(dev)) {
 854                 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
 855                 desired_bpp = 12*3;
 856
 857                 /* Need to adjust the port link by 1.5x for 12bpc. */
 858                 pipe_config->port_clock = clock_12bpc;
 859         } else {
 860                 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
 861                 desired_bpp = 8*3;
 862         }
 863
 864         if (!pipe_config->bw_constrained) {
 865                 DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp);
 866                 pipe_config->pipe_bpp = desired_bpp;
 867         }
 868
 869         if (adjusted_mode->clock > 225000) {
 870                 DRM_DEBUG_KMS("too high HDMI clock, rejecting mode\n");
 871                 return false;
 872         }
 873
 874         return true;
 875 }
 876
 877 static enum drm_connector_status
 878 intel_hdmi_detect(struct drm_connector *connector, bool force)
 879 {
 880         struct drm_device *dev = connector->dev;
 881         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
 882         struct intel_digital_port *intel_dig_port =
 883                 hdmi_to_dig_port(intel_hdmi);
 884         struct intel_encoder *intel_encoder = &intel_dig_port->base;
 885         struct drm_i915_private *dev_priv = dev->dev_private;
 886         struct edid *edid;
 887         enum drm_connector_status status = connector_status_disconnected;
 888
 889         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
 890                       connector->base.id, drm_get_connector_name(connector));
 891
 892         intel_hdmi->has_hdmi_sink = false;
 893         intel_hdmi->has_audio = false;
 894         intel_hdmi->rgb_quant_range_selectable = false;
 895         edid = drm_get_edid(connector,
 896                             intel_gmbus_get_adapter(dev_priv,
 897                                                     intel_hdmi->ddc_bus));
 898
 899         if (edid) {
 900                 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
 901                         status = connector_status_connected;
 902                         if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
 903                                 intel_hdmi->has_hdmi_sink =
 904                                                 drm_detect_hdmi_monitor(edid);
 905                         intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
 906                         intel_hdmi->rgb_quant_range_selectable =
 907                                 drm_rgb_quant_range_selectable(edid);
 908                 }
 909                 kfree(edid);
 910         }
 911
 912         if (status == connector_status_connected) {
 913                 if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
 914                         intel_hdmi->has_audio =
 915                                 (intel_hdmi->force_audio == HDMI_AUDIO_ON);
 916                 intel_encoder->type = INTEL_OUTPUT_HDMI;
 917         }
 918
 919         return status;
 920 }
 921
 922 static int intel_hdmi_get_modes(struct drm_connector *connector)
 923 {
 924         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
 925         struct drm_i915_private *dev_priv = connector->dev->dev_private;
 926
 927         /* We should parse the EDID data and find out if it's an HDMI sink so
 928          * we can send audio to it.
 929          */
 930
 931         return intel_ddc_get_modes(connector,
 932                                    intel_gmbus_get_adapter(dev_priv,
 933                                                            intel_hdmi->ddc_bus));
 934 }
 935
 936 static bool
 937 intel_hdmi_detect_audio(struct drm_connector *connector)
 938 {
 939         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
 940         struct drm_i915_private *dev_priv = connector->dev->dev_private;
 941         struct edid *edid;
 942         bool has_audio = false;
 943
 944         edid = drm_get_edid(connector,
 945                             intel_gmbus_get_adapter(dev_priv,
 946                                                     intel_hdmi->ddc_bus));
 947         if (edid) {
 948                 if (edid->input & DRM_EDID_INPUT_DIGITAL)
 949                         has_audio = drm_detect_monitor_audio(edid);
 950                 kfree(edid);
 951         }
 952
 953         return has_audio;
 954 }
 955
 956 static int
 957 intel_hdmi_set_property(struct drm_connector *connector,
 958                         struct drm_property *property,
 959                         uint64_t val)
 960 {
 961         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
 962         struct intel_digital_port *intel_dig_port =
 963                 hdmi_to_dig_port(intel_hdmi);
 964         struct drm_i915_private *dev_priv = connector->dev->dev_private;
 965         int ret;
 966
 967         ret = drm_object_property_set_value(&connector->base, property, val);
 968         if (ret)
 969                 return ret;
 970
 971         if (property == dev_priv->force_audio_property) {
 972                 enum hdmi_force_audio i = val;
 973                 bool has_audio;
 974
 975                 if (i == intel_hdmi->force_audio)
 976                         return 0;
 977
 978                 intel_hdmi->force_audio = i;
 979
 980                 if (i == HDMI_AUDIO_AUTO)
 981                         has_audio = intel_hdmi_detect_audio(connector);
 982                 else
 983                         has_audio = (i == HDMI_AUDIO_ON);
 984
 985                 if (i == HDMI_AUDIO_OFF_DVI)
 986                         intel_hdmi->has_hdmi_sink = 0;
 987
 988                 intel_hdmi->has_audio = has_audio;
 989                 goto done;
 990         }
 991
 992         if (property == dev_priv->broadcast_rgb_property) {
 993                 bool old_auto = intel_hdmi->color_range_auto;
 994                 uint32_t old_range = intel_hdmi->color_range;
 995
 996                 switch (val) {
 997                 case INTEL_BROADCAST_RGB_AUTO:
 998                         intel_hdmi->color_range_auto = true;
 999                         break;
1000                 case INTEL_BROADCAST_RGB_FULL:
1001                         intel_hdmi->color_range_auto = false;
1002                         intel_hdmi->color_range = 0;
1003                         break;
1004                 case INTEL_BROADCAST_RGB_LIMITED:
1005                         intel_hdmi->color_range_auto = false;
1006                         intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235;
1007                         break;
1008                 default:
1009                         return -EINVAL;
1010                 }
1011
1012                 if (old_auto == intel_hdmi->color_range_auto &&
1013                     old_range == intel_hdmi->color_range)
1014                         return 0;
1015
1016                 goto done;
1017         }
1018
1019         return -EINVAL;
1020
1021 done:
1022         if (intel_dig_port->base.base.crtc)
1023                 intel_crtc_restore_mode(intel_dig_port->base.base.crtc);
1024
1025         return 0;
1026 }
1027
1028 static void intel_hdmi_pre_enable(struct intel_encoder *encoder)
1029 {
1030         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1031         struct drm_device *dev = encoder->base.dev;
1032         struct drm_i915_private *dev_priv = dev->dev_private;
1033         struct intel_crtc *intel_crtc =
1034                 to_intel_crtc(encoder->base.crtc);
1035         int port = vlv_dport_to_channel(dport);
1036         int pipe = intel_crtc->pipe;
1037         u32 val;
1038
1039         if (!IS_VALLEYVIEW(dev))
1040                 return;
1041
1042         /* Enable clock channels for this port */
1043         mutex_lock(&dev_priv->dpio_lock);
1044         val = vlv_dpio_read(dev_priv, DPIO_DATA_LANE_A(port));
1045         val = 0;
1046         if (pipe)
1047                 val |= (1<<21);
1048         else
1049                 val &= ~(1<<21);
1050         val |= 0x001000c4;
1051         vlv_dpio_write(dev_priv, DPIO_DATA_CHANNEL(port), val);
1052
1053         /* HDMI 1.0V-2dB */
1054         vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0);
1055         vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL4(port),
1056                          0x2b245f5f);
1057         vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL2(port),
1058                          0x5578b83a);
1059         vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL3(port),
1060                          0x0c782040);
1061         vlv_dpio_write(dev_priv, DPIO_TX3_SWING_CTL4(port),
1062                          0x2b247878);
1063         vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER0(port), 0x00030000);
1064         vlv_dpio_write(dev_priv, DPIO_PCS_CTL_OVER1(port),
1065                          0x00002000);
1066         vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port),
1067                          DPIO_TX_OCALINIT_EN);
1068
1069         /* Program lane clock */
1070         vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF0(port),
1071                          0x00760018);
1072         vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF8(port),
1073                          0x00400888);
1074         mutex_unlock(&dev_priv->dpio_lock);
1075
1076         intel_enable_hdmi(encoder);
1077
1078         vlv_wait_port_ready(dev_priv, port);
1079 }
1080
1081 static void intel_hdmi_pre_pll_enable(struct intel_encoder *encoder)
1082 {
1083         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1084         struct drm_device *dev = encoder->base.dev;
1085         struct drm_i915_private *dev_priv = dev->dev_private;
1086         int port = vlv_dport_to_channel(dport);
1087
1088         if (!IS_VALLEYVIEW(dev))
1089                 return;
1090
1091         /* Program Tx lane resets to default */
1092         mutex_lock(&dev_priv->dpio_lock);
1093         vlv_dpio_write(dev_priv, DPIO_PCS_TX(port),
1094                          DPIO_PCS_TX_LANE2_RESET |
1095                          DPIO_PCS_TX_LANE1_RESET);
1096         vlv_dpio_write(dev_priv, DPIO_PCS_CLK(port),
1097                          DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1098                          DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1099                          (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1100                          DPIO_PCS_CLK_SOFT_RESET);
1101
1102         /* Fix up inter-pair skew failure */
1103         vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER1(port), 0x00750f00);
1104         vlv_dpio_write(dev_priv, DPIO_TX_CTL(port), 0x00001500);
1105         vlv_dpio_write(dev_priv, DPIO_TX_LANE(port), 0x40400000);
1106
1107         vlv_dpio_write(dev_priv, DPIO_PCS_CTL_OVER1(port),
1108                          0x00002000);
1109         vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port),
1110                          DPIO_TX_OCALINIT_EN);
1111         mutex_unlock(&dev_priv->dpio_lock);
1112 }
1113
1114 static void intel_hdmi_post_disable(struct intel_encoder *encoder)
1115 {
1116         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1117         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1118         int port = vlv_dport_to_channel(dport);
1119
1120         /* Reset lanes to avoid HDMI flicker (VLV w/a) */
1121         mutex_lock(&dev_priv->dpio_lock);
1122         vlv_dpio_write(dev_priv, DPIO_PCS_TX(port), 0x00000000);
1123         vlv_dpio_write(dev_priv, DPIO_PCS_CLK(port), 0x00e00060);
1124         mutex_unlock(&dev_priv->dpio_lock);
1125 }
1126
1127 static void intel_hdmi_destroy(struct drm_connector *connector)
1128 {
1129         drm_sysfs_connector_remove(connector);
1130         drm_connector_cleanup(connector);
1131         kfree(connector);
1132 }
1133
1134 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
1135         .dpms = intel_connector_dpms,
1136         .detect = intel_hdmi_detect,
1137         .fill_modes = drm_helper_probe_single_connector_modes,
1138         .set_property = intel_hdmi_set_property,
1139         .destroy = intel_hdmi_destroy,
1140 };
1141
1142 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
1143         .get_modes = intel_hdmi_get_modes,
1144         .mode_valid = intel_hdmi_mode_valid,
1145         .best_encoder = intel_best_encoder,
1146 };
1147
1148 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
1149         .destroy = intel_encoder_destroy,
1150 };
1151
1152 static void
1153 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
1154 {
1155         intel_attach_force_audio_property(connector);
1156         intel_attach_broadcast_rgb_property(connector);
1157         intel_hdmi->color_range_auto = true;
1158 }
1159
1160 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1161                                struct intel_connector *intel_connector)
1162 {
1163         struct drm_connector *connector = &intel_connector->base;
1164         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
1165         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1166         struct drm_device *dev = intel_encoder->base.dev;
1167         struct drm_i915_private *dev_priv = dev->dev_private;
1168         enum port port = intel_dig_port->port;
1169
1170         drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
1171                            DRM_MODE_CONNECTOR_HDMIA);
1172         drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
1173
1174         connector->interlace_allowed = 1;
1175         connector->doublescan_allowed = 0;
1176
1177         switch (port) {
1178         case PORT_B:
1179                 intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
1180                 intel_encoder->hpd_pin = HPD_PORT_B;
1181                 break;
1182         case PORT_C:
1183                 intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
1184                 intel_encoder->hpd_pin = HPD_PORT_C;
1185                 break;
1186         case PORT_D:
1187                 intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
1188                 intel_encoder->hpd_pin = HPD_PORT_D;
1189                 break;
1190         case PORT_A:
1191                 intel_encoder->hpd_pin = HPD_PORT_A;
1192                 /* Internal port only for eDP. */
1193         default:
1194                 BUG();
1195         }
1196
1197         if (IS_VALLEYVIEW(dev)) {
1198                 intel_hdmi->write_infoframe = vlv_write_infoframe;
1199                 intel_hdmi->set_infoframes = vlv_set_infoframes;
1200         } else if (!HAS_PCH_SPLIT(dev)) {
1201                 intel_hdmi->write_infoframe = g4x_write_infoframe;
1202                 intel_hdmi->set_infoframes = g4x_set_infoframes;
1203         } else if (HAS_DDI(dev)) {
1204                 intel_hdmi->write_infoframe = hsw_write_infoframe;
1205                 intel_hdmi->set_infoframes = hsw_set_infoframes;
1206         } else if (HAS_PCH_IBX(dev)) {
1207                 intel_hdmi->write_infoframe = ibx_write_infoframe;
1208                 intel_hdmi->set_infoframes = ibx_set_infoframes;
1209         } else {
1210                 intel_hdmi->write_infoframe = cpt_write_infoframe;
1211                 intel_hdmi->set_infoframes = cpt_set_infoframes;
1212         }
1213
1214         if (HAS_DDI(dev))
1215                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
1216         else
1217                 intel_connector->get_hw_state = intel_connector_get_hw_state;
1218
1219         intel_hdmi_add_properties(intel_hdmi, connector);
1220
1221         intel_connector_attach_encoder(intel_connector, intel_encoder);
1222         drm_sysfs_connector_add(connector);
1223
1224         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1225          * 0xd.  Failure to do so will result in spurious interrupts being
1226          * generated on the port when a cable is not attached.
1227          */
1228         if (IS_G4X(dev) && !IS_GM45(dev)) {
1229                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
1230                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
1231         }
1232 }
1233
1234 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port)
1235 {
1236         struct intel_digital_port *intel_dig_port;
1237         struct intel_encoder *intel_encoder;
1238         struct drm_encoder *encoder;
1239         struct intel_connector *intel_connector;
1240
1241         intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
1242         if (!intel_dig_port)
1243                 return;
1244
1245         intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
1246         if (!intel_connector) {
1247                 kfree(intel_dig_port);
1248                 return;
1249         }
1250
1251         intel_encoder = &intel_dig_port->base;
1252         encoder = &intel_encoder->base;
1253
1254         drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
1255                          DRM_MODE_ENCODER_TMDS);
1256
1257         intel_encoder->compute_config = intel_hdmi_compute_config;
1258         intel_encoder->mode_set = intel_hdmi_mode_set;
1259         intel_encoder->disable = intel_disable_hdmi;
1260         intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
1261         intel_encoder->get_config = intel_hdmi_get_config;
1262         if (IS_VALLEYVIEW(dev)) {
1263                 intel_encoder->pre_pll_enable = intel_hdmi_pre_pll_enable;
1264                 intel_encoder->pre_enable = intel_hdmi_pre_enable;
1265                 intel_encoder->enable = vlv_enable_hdmi;
1266                 intel_encoder->post_disable = intel_hdmi_post_disable;
1267         } else {
1268                 intel_encoder->enable = intel_enable_hdmi;
1269         }
1270
1271         intel_encoder->type = INTEL_OUTPUT_HDMI;
1272         intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
1273         intel_encoder->cloneable = false;
1274
1275         intel_dig_port->port = port;
1276         intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
1277         intel_dig_port->dp.output_reg = 0;
1278
1279         intel_hdmi_init_connector(intel_dig_port, intel_connector);
1280 }