Pileus Git - ~andy/linux/blob - drivers/gpu/drm/i915/intel_hdmi.c

   1 /*
   2  * Copyright 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright © 2006-2009 Intel Corporation
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *      Eric Anholt <eric@anholt.net>
  26  *      Jesse Barnes <jesse.barnes@intel.com>
  27  */
  28
  29 #include <linux/i2c.h>
  30 #include <linux/slab.h>
  31 #include <linux/delay.h>
  32 #include <drm/drmP.h>
  33 #include <drm/drm_crtc.h>
  34 #include <drm/drm_edid.h>
  35 #include "intel_drv.h"
  36 #include <drm/i915_drm.h>
  37 #include "i915_drv.h"
  38
  39 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
  40 {
  41         return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
  42 }
  43
  44 static void
  45 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
  46 {
  47         struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
  48         struct drm_i915_private *dev_priv = dev->dev_private;
  49         uint32_t enabled_bits;
  50
  51         enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
  52
  53         WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
  54              "HDMI port enabled, expecting disabled\n");
  55 }
  56
  57 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
  58 {
  59         struct intel_digital_port *intel_dig_port =
  60                 container_of(encoder, struct intel_digital_port, base.base);
  61         return &intel_dig_port->hdmi;
  62 }
  63
  64 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
  65 {
  66         return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
  67 }
  68
  69 void intel_dip_infoframe_csum(struct dip_infoframe *frame)
  70 {
  71         uint8_t *data = (uint8_t *)frame;
  72         uint8_t sum = 0;
  73         unsigned i;
  74
  75         frame->checksum = 0;
  76         frame->ecc = 0;
  77
  78         for (i = 0; i < frame->len + DIP_HEADER_SIZE; i++)
  79                 sum += data[i];
  80
  81         frame->checksum = 0x100 - sum;
  82 }
  83
  84 static u32 g4x_infoframe_index(struct dip_infoframe *frame)
  85 {
  86         switch (frame->type) {
  87         case DIP_TYPE_AVI:
  88                 return VIDEO_DIP_SELECT_AVI;
  89         case DIP_TYPE_SPD:
  90                 return VIDEO_DIP_SELECT_SPD;
  91         default:
  92                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
  93                 return 0;
  94         }
  95 }
  96
  97 static u32 g4x_infoframe_enable(struct dip_infoframe *frame)
  98 {
  99         switch (frame->type) {
 100         case DIP_TYPE_AVI:
 101                 return VIDEO_DIP_ENABLE_AVI;
 102         case DIP_TYPE_SPD:
 103                 return VIDEO_DIP_ENABLE_SPD;
 104         default:
 105                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
 106                 return 0;
 107         }
 108 }
 109
 110 static u32 hsw_infoframe_enable(struct dip_infoframe *frame)
 111 {
 112         switch (frame->type) {
 113         case DIP_TYPE_AVI:
 114                 return VIDEO_DIP_ENABLE_AVI_HSW;
 115         case DIP_TYPE_SPD:
 116                 return VIDEO_DIP_ENABLE_SPD_HSW;
 117         default:
 118                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
 119                 return 0;
 120         }
 121 }
 122
 123 static u32 hsw_infoframe_data_reg(struct dip_infoframe *frame,
 124                                   enum transcoder cpu_transcoder)
 125 {
 126         switch (frame->type) {
 127         case DIP_TYPE_AVI:
 128                 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder);
 129         case DIP_TYPE_SPD:
 130                 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder);
 131         default:
 132                 DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
 133                 return 0;
 134         }
 135 }
 136
 137 static void g4x_write_infoframe(struct drm_encoder *encoder,
 138                                 struct dip_infoframe *frame)
 139 {
 140         uint32_t *data = (uint32_t *)frame;
 141         struct drm_device *dev = encoder->dev;
 142         struct drm_i915_private *dev_priv = dev->dev_private;
 143         u32 val = I915_READ(VIDEO_DIP_CTL);
 144         unsigned i, len = DIP_HEADER_SIZE + frame->len;
 145
 146         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 147
 148         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 149         val |= g4x_infoframe_index(frame);
 150
 151         val &= ~g4x_infoframe_enable(frame);
 152
 153         I915_WRITE(VIDEO_DIP_CTL, val);
 154
 155         mmiowb();
 156         for (i = 0; i < len; i += 4) {
 157                 I915_WRITE(VIDEO_DIP_DATA, *data);
 158                 data++;
 159         }
 160         /* Write every possible data byte to force correct ECC calculation. */
 161         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 162                 I915_WRITE(VIDEO_DIP_DATA, 0);
 163         mmiowb();
 164
 165         val |= g4x_infoframe_enable(frame);
 166         val &= ~VIDEO_DIP_FREQ_MASK;
 167         val |= VIDEO_DIP_FREQ_VSYNC;
 168
 169         I915_WRITE(VIDEO_DIP_CTL, val);
 170         POSTING_READ(VIDEO_DIP_CTL);
 171 }
 172
 173 static void ibx_write_infoframe(struct drm_encoder *encoder,
 174                                 struct dip_infoframe *frame)
 175 {
 176         uint32_t *data = (uint32_t *)frame;
 177         struct drm_device *dev = encoder->dev;
 178         struct drm_i915_private *dev_priv = dev->dev_private;
 179         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 180         int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 181         unsigned i, len = DIP_HEADER_SIZE + frame->len;
 182         u32 val = I915_READ(reg);
 183
 184         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 185
 186         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 187         val |= g4x_infoframe_index(frame);
 188
 189         val &= ~g4x_infoframe_enable(frame);
 190
 191         I915_WRITE(reg, val);
 192
 193         mmiowb();
 194         for (i = 0; i < len; i += 4) {
 195                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 196                 data++;
 197         }
 198         /* Write every possible data byte to force correct ECC calculation. */
 199         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 200                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 201         mmiowb();
 202
 203         val |= g4x_infoframe_enable(frame);
 204         val &= ~VIDEO_DIP_FREQ_MASK;
 205         val |= VIDEO_DIP_FREQ_VSYNC;
 206
 207         I915_WRITE(reg, val);
 208         POSTING_READ(reg);
 209 }
 210
 211 static void cpt_write_infoframe(struct drm_encoder *encoder,
 212                                 struct dip_infoframe *frame)
 213 {
 214         uint32_t *data = (uint32_t *)frame;
 215         struct drm_device *dev = encoder->dev;
 216         struct drm_i915_private *dev_priv = dev->dev_private;
 217         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 218         int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 219         unsigned i, len = DIP_HEADER_SIZE + frame->len;
 220         u32 val = I915_READ(reg);
 221
 222         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 223
 224         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 225         val |= g4x_infoframe_index(frame);
 226
 227         /* The DIP control register spec says that we need to update the AVI
 228          * infoframe without clearing its enable bit */
 229         if (frame->type != DIP_TYPE_AVI)
 230                 val &= ~g4x_infoframe_enable(frame);
 231
 232         I915_WRITE(reg, val);
 233
 234         mmiowb();
 235         for (i = 0; i < len; i += 4) {
 236                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 237                 data++;
 238         }
 239         /* Write every possible data byte to force correct ECC calculation. */
 240         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 241                 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 242         mmiowb();
 243
 244         val |= g4x_infoframe_enable(frame);
 245         val &= ~VIDEO_DIP_FREQ_MASK;
 246         val |= VIDEO_DIP_FREQ_VSYNC;
 247
 248         I915_WRITE(reg, val);
 249         POSTING_READ(reg);
 250 }
 251
 252 static void vlv_write_infoframe(struct drm_encoder *encoder,
 253                                      struct dip_infoframe *frame)
 254 {
 255         uint32_t *data = (uint32_t *)frame;
 256         struct drm_device *dev = encoder->dev;
 257         struct drm_i915_private *dev_priv = dev->dev_private;
 258         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 259         int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 260         unsigned i, len = DIP_HEADER_SIZE + frame->len;
 261         u32 val = I915_READ(reg);
 262
 263         WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
 264
 265         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 266         val |= g4x_infoframe_index(frame);
 267
 268         val &= ~g4x_infoframe_enable(frame);
 269
 270         I915_WRITE(reg, val);
 271
 272         mmiowb();
 273         for (i = 0; i < len; i += 4) {
 274                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 275                 data++;
 276         }
 277         /* Write every possible data byte to force correct ECC calculation. */
 278         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 279                 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 280         mmiowb();
 281
 282         val |= g4x_infoframe_enable(frame);
 283         val &= ~VIDEO_DIP_FREQ_MASK;
 284         val |= VIDEO_DIP_FREQ_VSYNC;
 285
 286         I915_WRITE(reg, val);
 287         POSTING_READ(reg);
 288 }
 289
 290 static void hsw_write_infoframe(struct drm_encoder *encoder,
 291                                 struct dip_infoframe *frame)
 292 {
 293         uint32_t *data = (uint32_t *)frame;
 294         struct drm_device *dev = encoder->dev;
 295         struct drm_i915_private *dev_priv = dev->dev_private;
 296         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 297         u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder);
 298         u32 data_reg = hsw_infoframe_data_reg(frame, intel_crtc->config.cpu_transcoder);
 299         unsigned int i, len = DIP_HEADER_SIZE + frame->len;
 300         u32 val = I915_READ(ctl_reg);
 301
 302         if (data_reg == 0)
 303                 return;
 304
 305         val &= ~hsw_infoframe_enable(frame);
 306         I915_WRITE(ctl_reg, val);
 307
 308         mmiowb();
 309         for (i = 0; i < len; i += 4) {
 310                 I915_WRITE(data_reg + i, *data);
 311                 data++;
 312         }
 313         /* Write every possible data byte to force correct ECC calculation. */
 314         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 315                 I915_WRITE(data_reg + i, 0);
 316         mmiowb();
 317
 318         val |= hsw_infoframe_enable(frame);
 319         I915_WRITE(ctl_reg, val);
 320         POSTING_READ(ctl_reg);
 321 }
 322
 323 static void intel_set_infoframe(struct drm_encoder *encoder,
 324                                 struct dip_infoframe *frame)
 325 {
 326         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 327
 328         intel_dip_infoframe_csum(frame);
 329         intel_hdmi->write_infoframe(encoder, frame);
 330 }
 331
 332 static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
 333                                          struct drm_display_mode *adjusted_mode)
 334 {
 335         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 336         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 337         struct dip_infoframe avi_if = {
 338                 .type = DIP_TYPE_AVI,
 339                 .ver = DIP_VERSION_AVI,
 340                 .len = DIP_LEN_AVI,
 341         };
 342
 343         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
 344                 avi_if.body.avi.YQ_CN_PR |= DIP_AVI_PR_2;
 345
 346         if (intel_hdmi->rgb_quant_range_selectable) {
 347                 if (intel_crtc->config.limited_color_range)
 348                         avi_if.body.avi.ITC_EC_Q_SC |= DIP_AVI_RGB_QUANT_RANGE_LIMITED;
 349                 else
 350                         avi_if.body.avi.ITC_EC_Q_SC |= DIP_AVI_RGB_QUANT_RANGE_FULL;
 351         }
 352
 353         avi_if.body.avi.VIC = drm_match_cea_mode(adjusted_mode);
 354
 355         intel_set_infoframe(encoder, &avi_if);
 356 }
 357
 358 static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
 359 {
 360         struct dip_infoframe spd_if;
 361
 362         memset(&spd_if, 0, sizeof(spd_if));
 363         spd_if.type = DIP_TYPE_SPD;
 364         spd_if.ver = DIP_VERSION_SPD;
 365         spd_if.len = DIP_LEN_SPD;
 366         strcpy(spd_if.body.spd.vn, "Intel");
 367         strcpy(spd_if.body.spd.pd, "Integrated gfx");
 368         spd_if.body.spd.sdi = DIP_SPD_PC;
 369
 370         intel_set_infoframe(encoder, &spd_if);
 371 }
 372
 373 static void g4x_set_infoframes(struct drm_encoder *encoder,
 374                                struct drm_display_mode *adjusted_mode)
 375 {
 376         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 377         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 378         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
 379         u32 reg = VIDEO_DIP_CTL;
 380         u32 val = I915_READ(reg);
 381         u32 port;
 382
 383         assert_hdmi_port_disabled(intel_hdmi);
 384
 385         /* If the registers were not initialized yet, they might be zeroes,
 386          * which means we're selecting the AVI DIP and we're setting its
 387          * frequency to once. This seems to really confuse the HW and make
 388          * things stop working (the register spec says the AVI always needs to
 389          * be sent every VSync). So here we avoid writing to the register more
 390          * than we need and also explicitly select the AVI DIP and explicitly
 391          * set its frequency to every VSync. Avoiding to write it twice seems to
 392          * be enough to solve the problem, but being defensive shouldn't hurt us
 393          * either. */
 394         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 395
 396         if (!intel_hdmi->has_hdmi_sink) {
 397                 if (!(val & VIDEO_DIP_ENABLE))
 398                         return;
 399                 val &= ~VIDEO_DIP_ENABLE;
 400                 I915_WRITE(reg, val);
 401                 POSTING_READ(reg);
 402                 return;
 403         }
 404
 405         switch (intel_dig_port->port) {
 406         case PORT_B:
 407                 port = VIDEO_DIP_PORT_B;
 408                 break;
 409         case PORT_C:
 410                 port = VIDEO_DIP_PORT_C;
 411                 break;
 412         default:
 413                 BUG();
 414                 return;
 415         }
 416
 417         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 418                 if (val & VIDEO_DIP_ENABLE) {
 419                         val &= ~VIDEO_DIP_ENABLE;
 420                         I915_WRITE(reg, val);
 421                         POSTING_READ(reg);
 422                 }
 423                 val &= ~VIDEO_DIP_PORT_MASK;
 424                 val |= port;
 425         }
 426
 427         val |= VIDEO_DIP_ENABLE;
 428         val &= ~VIDEO_DIP_ENABLE_VENDOR;
 429
 430         I915_WRITE(reg, val);
 431         POSTING_READ(reg);
 432
 433         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 434         intel_hdmi_set_spd_infoframe(encoder);
 435 }
 436
 437 static void ibx_set_infoframes(struct drm_encoder *encoder,
 438                                struct drm_display_mode *adjusted_mode)
 439 {
 440         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 441         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 442         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
 443         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
 444         u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 445         u32 val = I915_READ(reg);
 446         u32 port;
 447
 448         assert_hdmi_port_disabled(intel_hdmi);
 449
 450         /* See the big comment in g4x_set_infoframes() */
 451         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 452
 453         if (!intel_hdmi->has_hdmi_sink) {
 454                 if (!(val & VIDEO_DIP_ENABLE))
 455                         return;
 456                 val &= ~VIDEO_DIP_ENABLE;
 457                 I915_WRITE(reg, val);
 458                 POSTING_READ(reg);
 459                 return;
 460         }
 461
 462         switch (intel_dig_port->port) {
 463         case PORT_B:
 464                 port = VIDEO_DIP_PORT_B;
 465                 break;
 466         case PORT_C:
 467                 port = VIDEO_DIP_PORT_C;
 468                 break;
 469         case PORT_D:
 470                 port = VIDEO_DIP_PORT_D;
 471                 break;
 472         default:
 473                 BUG();
 474                 return;
 475         }
 476
 477         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 478                 if (val & VIDEO_DIP_ENABLE) {
 479                         val &= ~VIDEO_DIP_ENABLE;
 480                         I915_WRITE(reg, val);
 481                         POSTING_READ(reg);
 482                 }
 483                 val &= ~VIDEO_DIP_PORT_MASK;
 484                 val |= port;
 485         }
 486
 487         val |= VIDEO_DIP_ENABLE;
 488         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 489                  VIDEO_DIP_ENABLE_GCP);
 490
 491         I915_WRITE(reg, val);
 492         POSTING_READ(reg);
 493
 494         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 495         intel_hdmi_set_spd_infoframe(encoder);
 496 }
 497
 498 static void cpt_set_infoframes(struct drm_encoder *encoder,
 499                                struct drm_display_mode *adjusted_mode)
 500 {
 501         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 502         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 503         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 504         u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 505         u32 val = I915_READ(reg);
 506
 507         assert_hdmi_port_disabled(intel_hdmi);
 508
 509         /* See the big comment in g4x_set_infoframes() */
 510         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 511
 512         if (!intel_hdmi->has_hdmi_sink) {
 513                 if (!(val & VIDEO_DIP_ENABLE))
 514                         return;
 515                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI);
 516                 I915_WRITE(reg, val);
 517                 POSTING_READ(reg);
 518                 return;
 519         }
 520
 521         /* Set both together, unset both together: see the spec. */
 522         val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
 523         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 524                  VIDEO_DIP_ENABLE_GCP);
 525
 526         I915_WRITE(reg, val);
 527         POSTING_READ(reg);
 528
 529         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 530         intel_hdmi_set_spd_infoframe(encoder);
 531 }
 532
 533 static void vlv_set_infoframes(struct drm_encoder *encoder,
 534                                struct drm_display_mode *adjusted_mode)
 535 {
 536         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 537         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 538         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 539         u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 540         u32 val = I915_READ(reg);
 541
 542         assert_hdmi_port_disabled(intel_hdmi);
 543
 544         /* See the big comment in g4x_set_infoframes() */
 545         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 546
 547         if (!intel_hdmi->has_hdmi_sink) {
 548                 if (!(val & VIDEO_DIP_ENABLE))
 549                         return;
 550                 val &= ~VIDEO_DIP_ENABLE;
 551                 I915_WRITE(reg, val);
 552                 POSTING_READ(reg);
 553                 return;
 554         }
 555
 556         val |= VIDEO_DIP_ENABLE;
 557         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 558                  VIDEO_DIP_ENABLE_GCP);
 559
 560         I915_WRITE(reg, val);
 561         POSTING_READ(reg);
 562
 563         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 564         intel_hdmi_set_spd_infoframe(encoder);
 565 }
 566
 567 static void hsw_set_infoframes(struct drm_encoder *encoder,
 568                                struct drm_display_mode *adjusted_mode)
 569 {
 570         struct drm_i915_private *dev_priv = encoder->dev->dev_private;
 571         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 572         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 573         u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder);
 574         u32 val = I915_READ(reg);
 575
 576         assert_hdmi_port_disabled(intel_hdmi);
 577
 578         if (!intel_hdmi->has_hdmi_sink) {
 579                 I915_WRITE(reg, 0);
 580                 POSTING_READ(reg);
 581                 return;
 582         }
 583
 584         val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
 585                  VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW);
 586
 587         I915_WRITE(reg, val);
 588         POSTING_READ(reg);
 589
 590         intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
 591         intel_hdmi_set_spd_infoframe(encoder);
 592 }
 593
 594 static void intel_hdmi_mode_set(struct drm_encoder *encoder,
 595                                 struct drm_display_mode *mode,
 596                                 struct drm_display_mode *adjusted_mode)
 597 {
 598         struct drm_device *dev = encoder->dev;
 599         struct drm_i915_private *dev_priv = dev->dev_private;
 600         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 601         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
 602         u32 hdmi_val;
 603
 604         hdmi_val = SDVO_ENCODING_HDMI;
 605         if (!HAS_PCH_SPLIT(dev))
 606                 hdmi_val |= intel_hdmi->color_range;
 607         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 608                 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
 609         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 610                 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
 611
 612         if (intel_crtc->config.pipe_bpp > 24)
 613                 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
 614         else
 615                 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
 616
 617         /* Required on CPT */
 618         if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev))
 619                 hdmi_val |= HDMI_MODE_SELECT_HDMI;
 620
 621         if (intel_hdmi->has_audio) {
 622                 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
 623                                  pipe_name(intel_crtc->pipe));
 624                 hdmi_val |= SDVO_AUDIO_ENABLE;
 625                 hdmi_val |= HDMI_MODE_SELECT_HDMI;
 626                 intel_write_eld(encoder, adjusted_mode);
 627         }
 628
 629         if (HAS_PCH_CPT(dev))
 630                 hdmi_val |= SDVO_PIPE_SEL_CPT(intel_crtc->pipe);
 631         else
 632                 hdmi_val |= SDVO_PIPE_SEL(intel_crtc->pipe);
 633
 634         I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
 635         POSTING_READ(intel_hdmi->hdmi_reg);
 636
 637         intel_hdmi->set_infoframes(encoder, adjusted_mode);
 638 }
 639
 640 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
 641                                     enum pipe *pipe)
 642 {
 643         struct drm_device *dev = encoder->base.dev;
 644         struct drm_i915_private *dev_priv = dev->dev_private;
 645         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 646         u32 tmp;
 647
 648         tmp = I915_READ(intel_hdmi->hdmi_reg);
 649
 650         if (!(tmp & SDVO_ENABLE))
 651                 return false;
 652
 653         if (HAS_PCH_CPT(dev))
 654                 *pipe = PORT_TO_PIPE_CPT(tmp);
 655         else
 656                 *pipe = PORT_TO_PIPE(tmp);
 657
 658         return true;
 659 }
 660
 661 static void intel_hdmi_get_config(struct intel_encoder *encoder,
 662                                   struct intel_crtc_config *pipe_config)
 663 {
 664         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 665         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 666         u32 tmp, flags = 0;
 667
 668         tmp = I915_READ(intel_hdmi->hdmi_reg);
 669
 670         if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
 671                 flags |= DRM_MODE_FLAG_PHSYNC;
 672         else
 673                 flags |= DRM_MODE_FLAG_NHSYNC;
 674
 675         if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
 676                 flags |= DRM_MODE_FLAG_PVSYNC;
 677         else
 678                 flags |= DRM_MODE_FLAG_NVSYNC;
 679
 680         pipe_config->adjusted_mode.flags |= flags;
 681 }
 682
 683 static void intel_enable_hdmi(struct intel_encoder *encoder)
 684 {
 685         struct drm_device *dev = encoder->base.dev;
 686         struct drm_i915_private *dev_priv = dev->dev_private;
 687         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 688         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 689         u32 temp;
 690         u32 enable_bits = SDVO_ENABLE;
 691
 692         if (intel_hdmi->has_audio)
 693                 enable_bits |= SDVO_AUDIO_ENABLE;
 694
 695         temp = I915_READ(intel_hdmi->hdmi_reg);
 696
 697         /* HW workaround for IBX, we need to move the port to transcoder A
 698          * before disabling it, so restore the transcoder select bit here. */
 699         if (HAS_PCH_IBX(dev))
 700                 enable_bits |= SDVO_PIPE_SEL(intel_crtc->pipe);
 701
 702         /* HW workaround, need to toggle enable bit off and on for 12bpc, but
 703          * we do this anyway which shows more stable in testing.
 704          */
 705         if (HAS_PCH_SPLIT(dev)) {
 706                 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
 707                 POSTING_READ(intel_hdmi->hdmi_reg);
 708         }
 709
 710         temp |= enable_bits;
 711
 712         I915_WRITE(intel_hdmi->hdmi_reg, temp);
 713         POSTING_READ(intel_hdmi->hdmi_reg);
 714
 715         /* HW workaround, need to write this twice for issue that may result
 716          * in first write getting masked.
 717          */
 718         if (HAS_PCH_SPLIT(dev)) {
 719                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
 720                 POSTING_READ(intel_hdmi->hdmi_reg);
 721         }
 722
 723         if (IS_VALLEYVIEW(dev)) {
 724                 struct intel_digital_port *dport =
 725                         enc_to_dig_port(&encoder->base);
 726                 int channel = vlv_dport_to_channel(dport);
 727
 728                 vlv_wait_port_ready(dev_priv, channel);
 729         }
 730 }
 731
 732 static void intel_disable_hdmi(struct intel_encoder *encoder)
 733 {
 734         struct drm_device *dev = encoder->base.dev;
 735         struct drm_i915_private *dev_priv = dev->dev_private;
 736         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 737         u32 temp;
 738         u32 enable_bits = SDVO_ENABLE | SDVO_AUDIO_ENABLE;
 739
 740         temp = I915_READ(intel_hdmi->hdmi_reg);
 741
 742         /* HW workaround for IBX, we need to move the port to transcoder A
 743          * before disabling it. */
 744         if (HAS_PCH_IBX(dev)) {
 745                 struct drm_crtc *crtc = encoder->base.crtc;
 746                 int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
 747
 748                 if (temp & SDVO_PIPE_B_SELECT) {
 749                         temp &= ~SDVO_PIPE_B_SELECT;
 750                         I915_WRITE(intel_hdmi->hdmi_reg, temp);
 751                         POSTING_READ(intel_hdmi->hdmi_reg);
 752
 753                         /* Again we need to write this twice. */
 754                         I915_WRITE(intel_hdmi->hdmi_reg, temp);
 755                         POSTING_READ(intel_hdmi->hdmi_reg);
 756
 757                         /* Transcoder selection bits only update
 758                          * effectively on vblank. */
 759                         if (crtc)
 760                                 intel_wait_for_vblank(dev, pipe);
 761                         else
 762                                 msleep(50);
 763                 }
 764         }
 765
 766         /* HW workaround, need to toggle enable bit off and on for 12bpc, but
 767          * we do this anyway which shows more stable in testing.
 768          */
 769         if (HAS_PCH_SPLIT(dev)) {
 770                 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
 771                 POSTING_READ(intel_hdmi->hdmi_reg);
 772         }
 773
 774         temp &= ~enable_bits;
 775
 776         I915_WRITE(intel_hdmi->hdmi_reg, temp);
 777         POSTING_READ(intel_hdmi->hdmi_reg);
 778
 779         /* HW workaround, need to write this twice for issue that may result
 780          * in first write getting masked.
 781          */
 782         if (HAS_PCH_SPLIT(dev)) {
 783                 I915_WRITE(intel_hdmi->hdmi_reg, temp);
 784                 POSTING_READ(intel_hdmi->hdmi_reg);
 785         }
 786 }
 787
 788 static int intel_hdmi_mode_valid(struct drm_connector *connector,
 789                                  struct drm_display_mode *mode)
 790 {
 791         if (mode->clock > 165000)
 792                 return MODE_CLOCK_HIGH;
 793         if (mode->clock < 20000)
 794                 return MODE_CLOCK_LOW;
 795
 796         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 797                 return MODE_NO_DBLESCAN;
 798
 799         return MODE_OK;
 800 }
 801
 802 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
 803                                struct intel_crtc_config *pipe_config)
 804 {
 805         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 806         struct drm_device *dev = encoder->base.dev;
 807         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
 808         int clock_12bpc = pipe_config->requested_mode.clock * 3 / 2;
 809         int desired_bpp;
 810
 811         if (intel_hdmi->color_range_auto) {
 812                 /* See CEA-861-E - 5.1 Default Encoding Parameters */
 813                 if (intel_hdmi->has_hdmi_sink &&
 814                     drm_match_cea_mode(adjusted_mode) > 1)
 815                         intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235;
 816                 else
 817                         intel_hdmi->color_range = 0;
 818         }
 819
 820         if (intel_hdmi->color_range)
 821                 pipe_config->limited_color_range = true;
 822
 823         if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev))
 824                 pipe_config->has_pch_encoder = true;
 825
 826         /*
 827          * HDMI is either 12 or 8, so if the display lets 10bpc sneak
 828          * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi
 829          * outputs. We also need to check that the higher clock still fits
 830          * within limits.
 831          */
 832         if (pipe_config->pipe_bpp > 8*3 && clock_12bpc <= 225000
 833             && HAS_PCH_SPLIT(dev)) {
 834                 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
 835                 desired_bpp = 12*3;
 836
 837                 /* Need to adjust the port link by 1.5x for 12bpc. */
 838                 pipe_config->port_clock = clock_12bpc;
 839         } else {
 840                 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
 841                 desired_bpp = 8*3;
 842         }
 843
 844         if (!pipe_config->bw_constrained) {
 845                 DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp);
 846                 pipe_config->pipe_bpp = desired_bpp;
 847         }
 848
 849         if (adjusted_mode->clock > 225000) {
 850                 DRM_DEBUG_KMS("too high HDMI clock, rejecting mode\n");
 851                 return false;
 852         }
 853
 854         return true;
 855 }
 856
 857 static enum drm_connector_status
 858 intel_hdmi_detect(struct drm_connector *connector, bool force)
 859 {
 860         struct drm_device *dev = connector->dev;
 861         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
 862         struct intel_digital_port *intel_dig_port =
 863                 hdmi_to_dig_port(intel_hdmi);
 864         struct intel_encoder *intel_encoder = &intel_dig_port->base;
 865         struct drm_i915_private *dev_priv = dev->dev_private;
 866         struct edid *edid;
 867         enum drm_connector_status status = connector_status_disconnected;
 868
 869         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
 870                       connector->base.id, drm_get_connector_name(connector));
 871
 872         intel_hdmi->has_hdmi_sink = false;
 873         intel_hdmi->has_audio = false;
 874         intel_hdmi->rgb_quant_range_selectable = false;
 875         edid = drm_get_edid(connector,
 876                             intel_gmbus_get_adapter(dev_priv,
 877                                                     intel_hdmi->ddc_bus));
 878
 879         if (edid) {
 880                 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
 881                         status = connector_status_connected;
 882                         if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
 883                                 intel_hdmi->has_hdmi_sink =
 884                                                 drm_detect_hdmi_monitor(edid);
 885                         intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
 886                         intel_hdmi->rgb_quant_range_selectable =
 887                                 drm_rgb_quant_range_selectable(edid);
 888                 }
 889                 kfree(edid);
 890         }
 891
 892         if (status == connector_status_connected) {
 893                 if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
 894                         intel_hdmi->has_audio =
 895                                 (intel_hdmi->force_audio == HDMI_AUDIO_ON);
 896                 intel_encoder->type = INTEL_OUTPUT_HDMI;
 897         }
 898
 899         return status;
 900 }
 901
 902 static int intel_hdmi_get_modes(struct drm_connector *connector)
 903 {
 904         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
 905         struct drm_i915_private *dev_priv = connector->dev->dev_private;
 906
 907         /* We should parse the EDID data and find out if it's an HDMI sink so
 908          * we can send audio to it.
 909          */
 910
 911         return intel_ddc_get_modes(connector,
 912                                    intel_gmbus_get_adapter(dev_priv,
 913                                                            intel_hdmi->ddc_bus));
 914 }
 915
 916 static bool
 917 intel_hdmi_detect_audio(struct drm_connector *connector)
 918 {
 919         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
 920         struct drm_i915_private *dev_priv = connector->dev->dev_private;
 921         struct edid *edid;
 922         bool has_audio = false;
 923
 924         edid = drm_get_edid(connector,
 925                             intel_gmbus_get_adapter(dev_priv,
 926                                                     intel_hdmi->ddc_bus));
 927         if (edid) {
 928                 if (edid->input & DRM_EDID_INPUT_DIGITAL)
 929                         has_audio = drm_detect_monitor_audio(edid);
 930                 kfree(edid);
 931         }
 932
 933         return has_audio;
 934 }
 935
 936 static int
 937 intel_hdmi_set_property(struct drm_connector *connector,
 938                         struct drm_property *property,
 939                         uint64_t val)
 940 {
 941         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
 942         struct intel_digital_port *intel_dig_port =
 943                 hdmi_to_dig_port(intel_hdmi);
 944         struct drm_i915_private *dev_priv = connector->dev->dev_private;
 945         int ret;
 946
 947         ret = drm_object_property_set_value(&connector->base, property, val);
 948         if (ret)
 949                 return ret;
 950
 951         if (property == dev_priv->force_audio_property) {
 952                 enum hdmi_force_audio i = val;
 953                 bool has_audio;
 954
 955                 if (i == intel_hdmi->force_audio)
 956                         return 0;
 957
 958                 intel_hdmi->force_audio = i;
 959
 960                 if (i == HDMI_AUDIO_AUTO)
 961                         has_audio = intel_hdmi_detect_audio(connector);
 962                 else
 963                         has_audio = (i == HDMI_AUDIO_ON);
 964
 965                 if (i == HDMI_AUDIO_OFF_DVI)
 966                         intel_hdmi->has_hdmi_sink = 0;
 967
 968                 intel_hdmi->has_audio = has_audio;
 969                 goto done;
 970         }
 971
 972         if (property == dev_priv->broadcast_rgb_property) {
 973                 bool old_auto = intel_hdmi->color_range_auto;
 974                 uint32_t old_range = intel_hdmi->color_range;
 975
 976                 switch (val) {
 977                 case INTEL_BROADCAST_RGB_AUTO:
 978                         intel_hdmi->color_range_auto = true;
 979                         break;
 980                 case INTEL_BROADCAST_RGB_FULL:
 981                         intel_hdmi->color_range_auto = false;
 982                         intel_hdmi->color_range = 0;
 983                         break;
 984                 case INTEL_BROADCAST_RGB_LIMITED:
 985                         intel_hdmi->color_range_auto = false;
 986                         intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235;
 987                         break;
 988                 default:
 989                         return -EINVAL;
 990                 }
 991
 992                 if (old_auto == intel_hdmi->color_range_auto &&
 993                     old_range == intel_hdmi->color_range)
 994                         return 0;
 995
 996                 goto done;
 997         }
 998
 999         return -EINVAL;
1000
1001 done:
1002         if (intel_dig_port->base.base.crtc)
1003                 intel_crtc_restore_mode(intel_dig_port->base.base.crtc);
1004
1005         return 0;
1006 }
1007
1008 static void intel_hdmi_pre_enable(struct intel_encoder *encoder)
1009 {
1010         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1011         struct drm_device *dev = encoder->base.dev;
1012         struct drm_i915_private *dev_priv = dev->dev_private;
1013         struct intel_crtc *intel_crtc =
1014                 to_intel_crtc(encoder->base.crtc);
1015         int port = vlv_dport_to_channel(dport);
1016         int pipe = intel_crtc->pipe;
1017         u32 val;
1018
1019         if (!IS_VALLEYVIEW(dev))
1020                 return;
1021
1022         /* Enable clock channels for this port */
1023         val = vlv_dpio_read(dev_priv, DPIO_DATA_LANE_A(port));
1024         val = 0;
1025         if (pipe)
1026                 val |= (1<<21);
1027         else
1028                 val &= ~(1<<21);
1029         val |= 0x001000c4;
1030         vlv_dpio_write(dev_priv, DPIO_DATA_CHANNEL(port), val);
1031
1032         /* HDMI 1.0V-2dB */
1033         vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0);
1034         vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL4(port),
1035                          0x2b245f5f);
1036         vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL2(port),
1037                          0x5578b83a);
1038         vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL3(port),
1039                          0x0c782040);
1040         vlv_dpio_write(dev_priv, DPIO_TX3_SWING_CTL4(port),
1041                          0x2b247878);
1042         vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER0(port), 0x00030000);
1043         vlv_dpio_write(dev_priv, DPIO_PCS_CTL_OVER1(port),
1044                          0x00002000);
1045         vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port),
1046                          DPIO_TX_OCALINIT_EN);
1047
1048         /* Program lane clock */
1049         vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF0(port),
1050                          0x00760018);
1051         vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF8(port),
1052                          0x00400888);
1053 }
1054
1055 static void intel_hdmi_pre_pll_enable(struct intel_encoder *encoder)
1056 {
1057         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1058         struct drm_device *dev = encoder->base.dev;
1059         struct drm_i915_private *dev_priv = dev->dev_private;
1060         int port = vlv_dport_to_channel(dport);
1061
1062         if (!IS_VALLEYVIEW(dev))
1063                 return;
1064
1065         /* Program Tx lane resets to default */
1066         vlv_dpio_write(dev_priv, DPIO_PCS_TX(port),
1067                          DPIO_PCS_TX_LANE2_RESET |
1068                          DPIO_PCS_TX_LANE1_RESET);
1069         vlv_dpio_write(dev_priv, DPIO_PCS_CLK(port),
1070                          DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1071                          DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1072                          (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1073                          DPIO_PCS_CLK_SOFT_RESET);
1074
1075         /* Fix up inter-pair skew failure */
1076         vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER1(port), 0x00750f00);
1077         vlv_dpio_write(dev_priv, DPIO_TX_CTL(port), 0x00001500);
1078         vlv_dpio_write(dev_priv, DPIO_TX_LANE(port), 0x40400000);
1079
1080         vlv_dpio_write(dev_priv, DPIO_PCS_CTL_OVER1(port),
1081                          0x00002000);
1082         vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port),
1083                          DPIO_TX_OCALINIT_EN);
1084 }
1085
1086 static void intel_hdmi_post_disable(struct intel_encoder *encoder)
1087 {
1088         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1089         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1090         int port = vlv_dport_to_channel(dport);
1091
1092         /* Reset lanes to avoid HDMI flicker (VLV w/a) */
1093         mutex_lock(&dev_priv->dpio_lock);
1094         vlv_dpio_write(dev_priv, DPIO_PCS_TX(port), 0x00000000);
1095         vlv_dpio_write(dev_priv, DPIO_PCS_CLK(port), 0x00e00060);
1096         mutex_unlock(&dev_priv->dpio_lock);
1097 }
1098
1099 static void intel_hdmi_destroy(struct drm_connector *connector)
1100 {
1101         drm_sysfs_connector_remove(connector);
1102         drm_connector_cleanup(connector);
1103         kfree(connector);
1104 }
1105
1106 static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = {
1107         .mode_set = intel_hdmi_mode_set,
1108 };
1109
1110 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
1111         .dpms = intel_connector_dpms,
1112         .detect = intel_hdmi_detect,
1113         .fill_modes = drm_helper_probe_single_connector_modes,
1114         .set_property = intel_hdmi_set_property,
1115         .destroy = intel_hdmi_destroy,
1116 };
1117
1118 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
1119         .get_modes = intel_hdmi_get_modes,
1120         .mode_valid = intel_hdmi_mode_valid,
1121         .best_encoder = intel_best_encoder,
1122 };
1123
1124 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
1125         .destroy = intel_encoder_destroy,
1126 };
1127
1128 static void
1129 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
1130 {
1131         intel_attach_force_audio_property(connector);
1132         intel_attach_broadcast_rgb_property(connector);
1133         intel_hdmi->color_range_auto = true;
1134 }
1135
1136 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1137                                struct intel_connector *intel_connector)
1138 {
1139         struct drm_connector *connector = &intel_connector->base;
1140         struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
1141         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1142         struct drm_device *dev = intel_encoder->base.dev;
1143         struct drm_i915_private *dev_priv = dev->dev_private;
1144         enum port port = intel_dig_port->port;
1145
1146         drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
1147                            DRM_MODE_CONNECTOR_HDMIA);
1148         drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
1149
1150         connector->interlace_allowed = 1;
1151         connector->doublescan_allowed = 0;
1152
1153         switch (port) {
1154         case PORT_B:
1155                 intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
1156                 intel_encoder->hpd_pin = HPD_PORT_B;
1157                 break;
1158         case PORT_C:
1159                 intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
1160                 intel_encoder->hpd_pin = HPD_PORT_C;
1161                 break;
1162         case PORT_D:
1163                 intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
1164                 intel_encoder->hpd_pin = HPD_PORT_D;
1165                 break;
1166         case PORT_A:
1167                 intel_encoder->hpd_pin = HPD_PORT_A;
1168                 /* Internal port only for eDP. */
1169         default:
1170                 BUG();
1171         }
1172
1173         if (IS_VALLEYVIEW(dev)) {
1174                 intel_hdmi->write_infoframe = vlv_write_infoframe;
1175                 intel_hdmi->set_infoframes = vlv_set_infoframes;
1176         } else if (!HAS_PCH_SPLIT(dev)) {
1177                 intel_hdmi->write_infoframe = g4x_write_infoframe;
1178                 intel_hdmi->set_infoframes = g4x_set_infoframes;
1179         } else if (HAS_DDI(dev)) {
1180                 intel_hdmi->write_infoframe = hsw_write_infoframe;
1181                 intel_hdmi->set_infoframes = hsw_set_infoframes;
1182         } else if (HAS_PCH_IBX(dev)) {
1183                 intel_hdmi->write_infoframe = ibx_write_infoframe;
1184                 intel_hdmi->set_infoframes = ibx_set_infoframes;
1185         } else {
1186                 intel_hdmi->write_infoframe = cpt_write_infoframe;
1187                 intel_hdmi->set_infoframes = cpt_set_infoframes;
1188         }
1189
1190         if (HAS_DDI(dev))
1191                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
1192         else
1193                 intel_connector->get_hw_state = intel_connector_get_hw_state;
1194
1195         intel_hdmi_add_properties(intel_hdmi, connector);
1196
1197         intel_connector_attach_encoder(intel_connector, intel_encoder);
1198         drm_sysfs_connector_add(connector);
1199
1200         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1201          * 0xd.  Failure to do so will result in spurious interrupts being
1202          * generated on the port when a cable is not attached.
1203          */
1204         if (IS_G4X(dev) && !IS_GM45(dev)) {
1205                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
1206                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
1207         }
1208 }
1209
1210 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port)
1211 {
1212         struct intel_digital_port *intel_dig_port;
1213         struct intel_encoder *intel_encoder;
1214         struct drm_encoder *encoder;
1215         struct intel_connector *intel_connector;
1216
1217         intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
1218         if (!intel_dig_port)
1219                 return;
1220
1221         intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
1222         if (!intel_connector) {
1223                 kfree(intel_dig_port);
1224                 return;
1225         }
1226
1227         intel_encoder = &intel_dig_port->base;
1228         encoder = &intel_encoder->base;
1229
1230         drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
1231                          DRM_MODE_ENCODER_TMDS);
1232         drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs);
1233
1234         intel_encoder->compute_config = intel_hdmi_compute_config;
1235         intel_encoder->enable = intel_enable_hdmi;
1236         intel_encoder->disable = intel_disable_hdmi;
1237         intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
1238         intel_encoder->get_config = intel_hdmi_get_config;
1239         if (IS_VALLEYVIEW(dev)) {
1240                 intel_encoder->pre_enable = intel_hdmi_pre_enable;
1241                 intel_encoder->pre_pll_enable = intel_hdmi_pre_pll_enable;
1242                 intel_encoder->post_disable = intel_hdmi_post_disable;
1243         }
1244
1245         intel_encoder->type = INTEL_OUTPUT_HDMI;
1246         intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
1247         intel_encoder->cloneable = false;
1248
1249         intel_dig_port->port = port;
1250         intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
1251         intel_dig_port->dp.output_reg = 0;
1252
1253         intel_hdmi_init_connector(intel_dig_port, intel_connector);
1254 }