Pileus Git - ~andy/linux/blob - drivers/gpu/drm/i915/intel_dsi.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Author: Jani Nikula <jani.nikula@intel.com>
  24  */
  25
  26 #include <drm/drmP.h>
  27 #include <drm/drm_crtc.h>
  28 #include <drm/drm_edid.h>
  29 #include <drm/i915_drm.h>
  30 #include <linux/slab.h>
  31 #include "i915_drv.h"
  32 #include "intel_drv.h"
  33 #include "intel_dsi.h"
  34 #include "intel_dsi_cmd.h"
  35
  36 /* the sub-encoders aka panel drivers */
  37 static const struct intel_dsi_device intel_dsi_devices[] = {
  38 };
  39
  40 static struct intel_dsi *intel_attached_dsi(struct drm_connector *connector)
  41 {
  42         return container_of(intel_attached_encoder(connector),
  43                             struct intel_dsi, base);
  44 }
  45
  46 static inline bool is_vid_mode(struct intel_dsi *intel_dsi)
  47 {
  48         return intel_dsi->dev.type == INTEL_DSI_VIDEO_MODE;
  49 }
  50
  51 static inline bool is_cmd_mode(struct intel_dsi *intel_dsi)
  52 {
  53         return intel_dsi->dev.type == INTEL_DSI_COMMAND_MODE;
  54 }
  55
  56 static void intel_dsi_hot_plug(struct intel_encoder *encoder)
  57 {
  58         DRM_DEBUG_KMS("\n");
  59 }
  60
  61 static bool intel_dsi_compute_config(struct intel_encoder *encoder,
  62                                      struct intel_crtc_config *config)
  63 {
  64         struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
  65                                                    base);
  66         struct intel_connector *intel_connector = intel_dsi->attached_connector;
  67         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
  68         struct drm_display_mode *adjusted_mode = &config->adjusted_mode;
  69         struct drm_display_mode *mode = &config->requested_mode;
  70
  71         DRM_DEBUG_KMS("\n");
  72
  73         if (fixed_mode)
  74                 intel_fixed_panel_mode(fixed_mode, adjusted_mode);
  75
  76         if (intel_dsi->dev.dev_ops->mode_fixup)
  77                 return intel_dsi->dev.dev_ops->mode_fixup(&intel_dsi->dev,
  78                                                           mode, adjusted_mode);
  79
  80         return true;
  81 }
  82
  83 static void intel_dsi_pre_pll_enable(struct intel_encoder *encoder)
  84 {
  85         DRM_DEBUG_KMS("\n");
  86 }
  87
  88 static void intel_dsi_pre_enable(struct intel_encoder *encoder)
  89 {
  90         DRM_DEBUG_KMS("\n");
  91 }
  92
  93 static void intel_dsi_enable(struct intel_encoder *encoder)
  94 {
  95         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
  96         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
  97         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
  98         int pipe = intel_crtc->pipe;
  99         u32 temp;
 100
 101         DRM_DEBUG_KMS("\n");
 102
 103         temp = I915_READ(MIPI_DEVICE_READY(pipe));
 104         if ((temp & DEVICE_READY) == 0) {
 105                 temp &= ~ULPS_STATE_MASK;
 106                 I915_WRITE(MIPI_DEVICE_READY(pipe), temp | DEVICE_READY);
 107         } else if (temp & ULPS_STATE_MASK) {
 108                 temp &= ~ULPS_STATE_MASK;
 109                 I915_WRITE(MIPI_DEVICE_READY(pipe), temp | ULPS_STATE_EXIT);
 110                 /*
 111                  * We need to ensure that there is a minimum of 1 ms time
 112                  * available before clearing the UPLS exit state.
 113                  */
 114                 msleep(2);
 115                 I915_WRITE(MIPI_DEVICE_READY(pipe), temp);
 116         }
 117
 118         if (is_cmd_mode(intel_dsi))
 119                 I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(pipe), 8 * 4);
 120
 121         if (is_vid_mode(intel_dsi)) {
 122                 msleep(20); /* XXX */
 123                 dpi_send_cmd(intel_dsi, TURN_ON);
 124                 msleep(100);
 125
 126                 /* assert ip_tg_enable signal */
 127                 temp = I915_READ(MIPI_PORT_CTRL(pipe));
 128                 I915_WRITE(MIPI_PORT_CTRL(pipe), temp | DPI_ENABLE);
 129                 POSTING_READ(MIPI_PORT_CTRL(pipe));
 130         }
 131
 132         intel_dsi->dev.dev_ops->enable(&intel_dsi->dev);
 133 }
 134
 135 static void intel_dsi_disable(struct intel_encoder *encoder)
 136 {
 137         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 138         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
 139         struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 140         int pipe = intel_crtc->pipe;
 141         u32 temp;
 142
 143         DRM_DEBUG_KMS("\n");
 144
 145         intel_dsi->dev.dev_ops->disable(&intel_dsi->dev);
 146
 147         if (is_vid_mode(intel_dsi)) {
 148                 dpi_send_cmd(intel_dsi, SHUTDOWN);
 149                 msleep(10);
 150
 151                 /* de-assert ip_tg_enable signal */
 152                 temp = I915_READ(MIPI_PORT_CTRL(pipe));
 153                 I915_WRITE(MIPI_PORT_CTRL(pipe), temp & ~DPI_ENABLE);
 154                 POSTING_READ(MIPI_PORT_CTRL(pipe));
 155
 156                 msleep(2);
 157         }
 158
 159         temp = I915_READ(MIPI_DEVICE_READY(pipe));
 160         if (temp & DEVICE_READY) {
 161                 temp &= ~DEVICE_READY;
 162                 temp &= ~ULPS_STATE_MASK;
 163                 I915_WRITE(MIPI_DEVICE_READY(pipe), temp);
 164         }
 165 }
 166
 167 static void intel_dsi_post_disable(struct intel_encoder *encoder)
 168 {
 169         DRM_DEBUG_KMS("\n");
 170 }
 171
 172 static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
 173                                    enum pipe *pipe)
 174 {
 175         struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 176         u32 port, func;
 177         enum pipe p;
 178
 179         DRM_DEBUG_KMS("\n");
 180
 181         /* XXX: this only works for one DSI output */
 182         for (p = PIPE_A; p <= PIPE_B; p++) {
 183                 port = I915_READ(MIPI_PORT_CTRL(p));
 184                 func = I915_READ(MIPI_DSI_FUNC_PRG(p));
 185
 186                 if ((port & DPI_ENABLE) || (func & CMD_MODE_DATA_WIDTH_MASK)) {
 187                         if (I915_READ(MIPI_DEVICE_READY(p)) & DEVICE_READY) {
 188                                 *pipe = p;
 189                                 return true;
 190                         }
 191                 }
 192         }
 193
 194         return false;
 195 }
 196
 197 static void intel_dsi_get_config(struct intel_encoder *encoder,
 198                                  struct intel_crtc_config *pipe_config)
 199 {
 200         DRM_DEBUG_KMS("\n");
 201
 202         /* XXX: read flags, set to adjusted_mode */
 203 }
 204
 205 static int intel_dsi_mode_valid(struct drm_connector *connector,
 206                                 struct drm_display_mode *mode)
 207 {
 208         struct intel_connector *intel_connector = to_intel_connector(connector);
 209         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 210         struct intel_dsi *intel_dsi = intel_attached_dsi(connector);
 211
 212         DRM_DEBUG_KMS("\n");
 213
 214         if (mode->flags & DRM_MODE_FLAG_DBLSCAN) {
 215                 DRM_DEBUG_KMS("MODE_NO_DBLESCAN\n");
 216                 return MODE_NO_DBLESCAN;
 217         }
 218
 219         if (fixed_mode) {
 220                 if (mode->hdisplay > fixed_mode->hdisplay)
 221                         return MODE_PANEL;
 222                 if (mode->vdisplay > fixed_mode->vdisplay)
 223                         return MODE_PANEL;
 224         }
 225
 226         return intel_dsi->dev.dev_ops->mode_valid(&intel_dsi->dev, mode);
 227 }
 228
 229 /* return txclkesc cycles in terms of divider and duration in us */
 230 static u16 txclkesc(u32 divider, unsigned int us)
 231 {
 232         switch (divider) {
 233         case ESCAPE_CLOCK_DIVIDER_1:
 234         default:
 235                 return 20 * us;
 236         case ESCAPE_CLOCK_DIVIDER_2:
 237                 return 10 * us;
 238         case ESCAPE_CLOCK_DIVIDER_4:
 239                 return 5 * us;
 240         }
 241 }
 242
 243 /* return pixels in terms of txbyteclkhs */
 244 static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count)
 245 {
 246         return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp, 8), lane_count);
 247 }
 248
 249 static void set_dsi_timings(struct drm_encoder *encoder,
 250                             const struct drm_display_mode *mode)
 251 {
 252         struct drm_device *dev = encoder->dev;
 253         struct drm_i915_private *dev_priv = dev->dev_private;
 254         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 255         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 256         int pipe = intel_crtc->pipe;
 257         unsigned int bpp = intel_crtc->config.pipe_bpp;
 258         unsigned int lane_count = intel_dsi->lane_count;
 259
 260         u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
 261
 262         hactive = mode->hdisplay;
 263         hfp = mode->hsync_start - mode->hdisplay;
 264         hsync = mode->hsync_end - mode->hsync_start;
 265         hbp = mode->htotal - mode->hsync_end;
 266
 267         vfp = mode->vsync_start - mode->vdisplay;
 268         vsync = mode->vsync_end - mode->vsync_start;
 269         vbp = mode->vtotal - mode->vsync_end;
 270
 271         /* horizontal values are in terms of high speed byte clock */
 272         hactive = txbyteclkhs(hactive, bpp, lane_count);
 273         hfp = txbyteclkhs(hfp, bpp, lane_count);
 274         hsync = txbyteclkhs(hsync, bpp, lane_count);
 275         hbp = txbyteclkhs(hbp, bpp, lane_count);
 276
 277         I915_WRITE(MIPI_HACTIVE_AREA_COUNT(pipe), hactive);
 278         I915_WRITE(MIPI_HFP_COUNT(pipe), hfp);
 279
 280         /* meaningful for video mode non-burst sync pulse mode only, can be zero
 281          * for non-burst sync events and burst modes */
 282         I915_WRITE(MIPI_HSYNC_PADDING_COUNT(pipe), hsync);
 283         I915_WRITE(MIPI_HBP_COUNT(pipe), hbp);
 284
 285         /* vertical values are in terms of lines */
 286         I915_WRITE(MIPI_VFP_COUNT(pipe), vfp);
 287         I915_WRITE(MIPI_VSYNC_PADDING_COUNT(pipe), vsync);
 288         I915_WRITE(MIPI_VBP_COUNT(pipe), vbp);
 289 }
 290
 291 static void intel_dsi_mode_set(struct intel_encoder *intel_encoder)
 292 {
 293         struct drm_encoder *encoder = &intel_encoder->base;
 294         struct drm_device *dev = encoder->dev;
 295         struct drm_i915_private *dev_priv = dev->dev_private;
 296         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
 297         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 298         struct drm_display_mode *adjusted_mode =
 299                 &intel_crtc->config.adjusted_mode;
 300         int pipe = intel_crtc->pipe;
 301         unsigned int bpp = intel_crtc->config.pipe_bpp;
 302         u32 val, tmp;
 303
 304         DRM_DEBUG_KMS("pipe %d\n", pipe);
 305
 306         /* escape clock divider, 20MHz, shared for A and C. device ready must be
 307          * off when doing this! txclkesc? */
 308         tmp = I915_READ(MIPI_CTRL(0));
 309         tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
 310         I915_WRITE(MIPI_CTRL(0), tmp | ESCAPE_CLOCK_DIVIDER_1);
 311
 312         /* read request priority is per pipe */
 313         tmp = I915_READ(MIPI_CTRL(pipe));
 314         tmp &= ~READ_REQUEST_PRIORITY_MASK;
 315         I915_WRITE(MIPI_CTRL(pipe), tmp | READ_REQUEST_PRIORITY_HIGH);
 316
 317         /* XXX: why here, why like this? handling in irq handler?! */
 318         I915_WRITE(MIPI_INTR_STAT(pipe), 0xffffffff);
 319         I915_WRITE(MIPI_INTR_EN(pipe), 0xffffffff);
 320
 321         I915_WRITE(MIPI_DPHY_PARAM(pipe),
 322                    0x3c << EXIT_ZERO_COUNT_SHIFT |
 323                    0x1f << TRAIL_COUNT_SHIFT |
 324                    0xc5 << CLK_ZERO_COUNT_SHIFT |
 325                    0x1f << PREPARE_COUNT_SHIFT);
 326
 327         I915_WRITE(MIPI_DPI_RESOLUTION(pipe),
 328                    adjusted_mode->vdisplay << VERTICAL_ADDRESS_SHIFT |
 329                    adjusted_mode->hdisplay << HORIZONTAL_ADDRESS_SHIFT);
 330
 331         set_dsi_timings(encoder, adjusted_mode);
 332
 333         val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT;
 334         if (is_cmd_mode(intel_dsi)) {
 335                 val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT;
 336                 val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */
 337         } else {
 338                 val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT;
 339
 340                 /* XXX: cross-check bpp vs. pixel format? */
 341                 val |= intel_dsi->pixel_format;
 342         }
 343         I915_WRITE(MIPI_DSI_FUNC_PRG(pipe), val);
 344
 345         /* timeouts for recovery. one frame IIUC. if counter expires, EOT and
 346          * stop state. */
 347
 348         /*
 349          * In burst mode, value greater than one DPI line Time in byte clock
 350          * (txbyteclkhs) To timeout this timer 1+ of the above said value is
 351          * recommended.
 352          *
 353          * In non-burst mode, Value greater than one DPI frame time in byte
 354          * clock(txbyteclkhs) To timeout this timer 1+ of the above said value
 355          * is recommended.
 356          *
 357          * In DBI only mode, value greater than one DBI frame time in byte
 358          * clock(txbyteclkhs) To timeout this timer 1+ of the above said value
 359          * is recommended.
 360          */
 361
 362         if (is_vid_mode(intel_dsi) &&
 363             intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
 364                 I915_WRITE(MIPI_HS_TX_TIMEOUT(pipe),
 365                            txbyteclkhs(adjusted_mode->htotal, bpp,
 366                                        intel_dsi->lane_count) + 1);
 367         } else {
 368                 I915_WRITE(MIPI_HS_TX_TIMEOUT(pipe),
 369                            txbyteclkhs(adjusted_mode->vtotal *
 370                                        adjusted_mode->htotal,
 371                                        bpp, intel_dsi->lane_count) + 1);
 372         }
 373         I915_WRITE(MIPI_LP_RX_TIMEOUT(pipe), 8309); /* max */
 374         I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(pipe), 0x14); /* max */
 375         I915_WRITE(MIPI_DEVICE_RESET_TIMER(pipe), 0xffff); /* max */
 376
 377         /* dphy stuff */
 378
 379         /* in terms of low power clock */
 380         I915_WRITE(MIPI_INIT_COUNT(pipe), txclkesc(ESCAPE_CLOCK_DIVIDER_1, 100));
 381
 382         /* recovery disables */
 383         I915_WRITE(MIPI_EOT_DISABLE(pipe), intel_dsi->eot_disable);
 384
 385         /* in terms of txbyteclkhs. actual high to low switch +
 386          * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
 387          *
 388          * XXX: write MIPI_STOP_STATE_STALL?
 389          */
 390         I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(pipe), 0x46);
 391
 392         /* XXX: low power clock equivalence in terms of byte clock. the number
 393          * of byte clocks occupied in one low power clock. based on txbyteclkhs
 394          * and txclkesc. txclkesc time / txbyteclk time * (105 +
 395          * MIPI_STOP_STATE_STALL) / 105.???
 396          */
 397         I915_WRITE(MIPI_LP_BYTECLK(pipe), 4);
 398
 399         /* the bw essential for transmitting 16 long packets containing 252
 400          * bytes meant for dcs write memory command is programmed in this
 401          * register in terms of byte clocks. based on dsi transfer rate and the
 402          * number of lanes configured the time taken to transmit 16 long packets
 403          * in a dsi stream varies. */
 404         I915_WRITE(MIPI_DBI_BW_CTRL(pipe), 0x820);
 405
 406         I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(pipe),
 407                    0xa << LP_HS_SSW_CNT_SHIFT |
 408                    0x14 << HS_LP_PWR_SW_CNT_SHIFT);
 409
 410         if (is_vid_mode(intel_dsi))
 411                 I915_WRITE(MIPI_VIDEO_MODE_FORMAT(pipe),
 412                            intel_dsi->video_mode_format);
 413 }
 414
 415 static enum drm_connector_status
 416 intel_dsi_detect(struct drm_connector *connector, bool force)
 417 {
 418         struct intel_dsi *intel_dsi = intel_attached_dsi(connector);
 419         DRM_DEBUG_KMS("\n");
 420         return intel_dsi->dev.dev_ops->detect(&intel_dsi->dev);
 421 }
 422
 423 static int intel_dsi_get_modes(struct drm_connector *connector)
 424 {
 425         struct intel_connector *intel_connector = to_intel_connector(connector);
 426         struct drm_display_mode *mode;
 427
 428         DRM_DEBUG_KMS("\n");
 429
 430         if (!intel_connector->panel.fixed_mode) {
 431                 DRM_DEBUG_KMS("no fixed mode\n");
 432                 return 0;
 433         }
 434
 435         mode = drm_mode_duplicate(connector->dev,
 436                                   intel_connector->panel.fixed_mode);
 437         if (!mode) {
 438                 DRM_DEBUG_KMS("drm_mode_duplicate failed\n");
 439                 return 0;
 440         }
 441
 442         drm_mode_probed_add(connector, mode);
 443         return 1;
 444 }
 445
 446 static void intel_dsi_destroy(struct drm_connector *connector)
 447 {
 448         struct intel_connector *intel_connector = to_intel_connector(connector);
 449
 450         DRM_DEBUG_KMS("\n");
 451         intel_panel_fini(&intel_connector->panel);
 452         drm_sysfs_connector_remove(connector);
 453         drm_connector_cleanup(connector);
 454         kfree(connector);
 455 }
 456
 457 static const struct drm_encoder_funcs intel_dsi_funcs = {
 458         .destroy = intel_encoder_destroy,
 459 };
 460
 461 static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = {
 462         .get_modes = intel_dsi_get_modes,
 463         .mode_valid = intel_dsi_mode_valid,
 464         .best_encoder = intel_best_encoder,
 465 };
 466
 467 static const struct drm_connector_funcs intel_dsi_connector_funcs = {
 468         .dpms = intel_connector_dpms,
 469         .detect = intel_dsi_detect,
 470         .destroy = intel_dsi_destroy,
 471         .fill_modes = drm_helper_probe_single_connector_modes,
 472 };
 473
 474 bool intel_dsi_init(struct drm_device *dev)
 475 {
 476         struct intel_dsi *intel_dsi;
 477         struct intel_encoder *intel_encoder;
 478         struct drm_encoder *encoder;
 479         struct intel_connector *intel_connector;
 480         struct drm_connector *connector;
 481         struct drm_display_mode *fixed_mode = NULL;
 482         const struct intel_dsi_device *dsi;
 483         unsigned int i;
 484
 485         DRM_DEBUG_KMS("\n");
 486
 487         intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
 488         if (!intel_dsi)
 489                 return false;
 490
 491         intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
 492         if (!intel_connector) {
 493                 kfree(intel_dsi);
 494                 return false;
 495         }
 496
 497         intel_encoder = &intel_dsi->base;
 498         encoder = &intel_encoder->base;
 499         intel_dsi->attached_connector = intel_connector;
 500
 501         connector = &intel_connector->base;
 502
 503         drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI);
 504
 505         /* XXX: very likely not all of these are needed */
 506         intel_encoder->hot_plug = intel_dsi_hot_plug;
 507         intel_encoder->compute_config = intel_dsi_compute_config;
 508         intel_encoder->pre_pll_enable = intel_dsi_pre_pll_enable;
 509         intel_encoder->pre_enable = intel_dsi_pre_enable;
 510         intel_encoder->enable = intel_dsi_enable;
 511         intel_encoder->mode_set = intel_dsi_mode_set;
 512         intel_encoder->disable = intel_dsi_disable;
 513         intel_encoder->post_disable = intel_dsi_post_disable;
 514         intel_encoder->get_hw_state = intel_dsi_get_hw_state;
 515         intel_encoder->get_config = intel_dsi_get_config;
 516
 517         intel_connector->get_hw_state = intel_connector_get_hw_state;
 518
 519         for (i = 0; i < ARRAY_SIZE(intel_dsi_devices); i++) {
 520                 dsi = &intel_dsi_devices[i];
 521                 intel_dsi->dev = *dsi;
 522
 523                 if (dsi->dev_ops->init(&intel_dsi->dev))
 524                         break;
 525         }
 526
 527         if (i == ARRAY_SIZE(intel_dsi_devices)) {
 528                 DRM_DEBUG_KMS("no device found\n");
 529                 goto err;
 530         }
 531
 532         intel_encoder->type = INTEL_OUTPUT_DSI;
 533         intel_encoder->crtc_mask = (1 << 0); /* XXX */
 534
 535         intel_encoder->cloneable = false;
 536         drm_connector_init(dev, connector, &intel_dsi_connector_funcs,
 537                            DRM_MODE_CONNECTOR_DSI);
 538
 539         drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs);
 540
 541         connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/
 542         connector->interlace_allowed = false;
 543         connector->doublescan_allowed = false;
 544
 545         intel_connector_attach_encoder(intel_connector, intel_encoder);
 546
 547         drm_sysfs_connector_add(connector);
 548
 549         fixed_mode = dsi->dev_ops->get_modes(&intel_dsi->dev);
 550         if (!fixed_mode) {
 551                 DRM_DEBUG_KMS("no fixed mode\n");
 552                 goto err;
 553         }
 554
 555         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
 556         intel_panel_init(&intel_connector->panel, fixed_mode);
 557
 558         return true;
 559
 560 err:
 561         drm_encoder_cleanup(&intel_encoder->base);
 562         kfree(intel_dsi);
 563         kfree(intel_connector);
 564
 565         return false;
 566 }