2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #ifndef __INTEL_DRV_H__
26 #define __INTEL_DRV_H__
28 #include <linux/i2c.h>
29 #include <drm/i915_drm.h>
31 #include <drm/drm_crtc.h>
32 #include <drm/drm_crtc_helper.h>
33 #include <drm/drm_fb_helper.h>
34 #include <drm/drm_dp_helper.h>
37 * _wait_for - magic (register) wait macro
39 * Does the right thing for modeset paths when run under kdgb or similar atomic
40 * contexts. Note that it's important that we check the condition again after
41 * having timed out, since the timeout could be due to preemption or similar and
42 * we've never had a chance to check the condition before the timeout.
44 #define _wait_for(COND, MS, W) ({ \
45 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \
48 if (time_after(jiffies, timeout__)) { \
53 if (W && drm_can_sleep()) { \
62 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
63 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
64 #define wait_for_atomic_us(COND, US) _wait_for((COND), \
65 DIV_ROUND_UP((US), 1000), 0)
67 #define KHz(x) (1000*x)
68 #define MHz(x) KHz(1000*x)
71 * Display related stuff
74 /* store information about an Ixxx DVO */
75 /* The i830->i865 use multiple DVOs with multiple i2cs */
76 /* the i915, i945 have a single sDVO i2c bus - which is different */
78 /* maximum connectors per crtcs in the mode set */
79 #define INTELFB_CONN_LIMIT 4
81 #define INTEL_I2C_BUS_DVO 1
82 #define INTEL_I2C_BUS_SDVO 2
84 /* these are outputs from the chip - integrated only
85 external chips are via DVO or SDVO output */
86 #define INTEL_OUTPUT_UNUSED 0
87 #define INTEL_OUTPUT_ANALOG 1
88 #define INTEL_OUTPUT_DVO 2
89 #define INTEL_OUTPUT_SDVO 3
90 #define INTEL_OUTPUT_LVDS 4
91 #define INTEL_OUTPUT_TVOUT 5
92 #define INTEL_OUTPUT_HDMI 6
93 #define INTEL_OUTPUT_DISPLAYPORT 7
94 #define INTEL_OUTPUT_EDP 8
95 #define INTEL_OUTPUT_UNKNOWN 9
97 #define INTEL_DVO_CHIP_NONE 0
98 #define INTEL_DVO_CHIP_LVDS 1
99 #define INTEL_DVO_CHIP_TMDS 2
100 #define INTEL_DVO_CHIP_TVOUT 4
102 struct intel_framebuffer {
103 struct drm_framebuffer base;
104 struct drm_i915_gem_object *obj;
108 struct drm_fb_helper helper;
109 struct intel_framebuffer ifb;
110 struct list_head fbdev_list;
111 struct drm_display_mode *our_mode;
114 struct intel_encoder {
115 struct drm_encoder base;
117 * The new crtc this encoder will be driven from. Only differs from
118 * base->crtc while a modeset is in progress.
120 struct intel_crtc *new_crtc;
124 * Intel hw has only one MUX where encoders could be clone, hence a
125 * simple flag is enough to compute the possible_clones mask.
128 bool connectors_active;
129 void (*hot_plug)(struct intel_encoder *);
130 bool (*compute_config)(struct intel_encoder *,
131 struct intel_crtc_config *);
132 void (*pre_pll_enable)(struct intel_encoder *);
133 void (*pre_enable)(struct intel_encoder *);
134 void (*enable)(struct intel_encoder *);
135 void (*mode_set)(struct intel_encoder *intel_encoder);
136 void (*disable)(struct intel_encoder *);
137 void (*post_disable)(struct intel_encoder *);
138 /* Read out the current hw state of this connector, returning true if
139 * the encoder is active. If the encoder is enabled it also set the pipe
140 * it is connected to in the pipe parameter. */
141 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
143 enum hpd_pin hpd_pin;
147 struct drm_display_mode *fixed_mode;
151 struct intel_connector {
152 struct drm_connector base;
154 * The fixed encoder this connector is connected to.
156 struct intel_encoder *encoder;
159 * The new encoder this connector will be driven. Only differs from
160 * encoder while a modeset is in progress.
162 struct intel_encoder *new_encoder;
164 /* Reads out the current hw, returning true if the connector is enabled
165 * and active (i.e. dpms ON state). */
166 bool (*get_hw_state)(struct intel_connector *);
168 /* Panel info for eDP and LVDS */
169 struct intel_panel panel;
171 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
174 /* since POLL and HPD connectors may use the same HPD line keep the native
175 state of connector->polled in case hotplug storm detection changes it */
179 typedef struct dpll {
191 struct intel_crtc_config {
192 struct drm_display_mode requested_mode;
193 struct drm_display_mode adjusted_mode;
194 /* This flag must be set by the encoder's compute_config callback if it
195 * changes the crtc timings in the mode to prevent the crtc fixup from
196 * overwriting them. Currently only lvds needs that. */
198 /* Whether to set up the PCH/FDI. Note that we never allow sharing
199 * between pch encoders and cpu encoders. */
200 bool has_pch_encoder;
202 /* CPU Transcoder for the pipe. Currently this can only differ from the
203 * pipe on Haswell (where we have a special eDP transcoder). */
204 enum transcoder cpu_transcoder;
207 * Use reduced/limited/broadcast rbg range, compressing from the full
208 * range fed into the crtcs.
210 bool limited_color_range;
212 /* DP has a bunch of special case unfortunately, so mark the pipe
217 * Enable dithering, used when the selected pipe bpp doesn't match the
222 /* Controls for the clock computation, to override various stages. */
225 /* SDVO TV has a bunch of special case. To make multifunction encoders
226 * work correctly, we need to track this at runtime.*/
230 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
231 * required. This is set in the 2nd loop of calling encoder's
232 * ->compute_config if the first pick doesn't work out.
236 /* Settings for the intel dpll used on pretty much everything but
241 struct intel_link_m_n dp_m_n;
243 * This is currently used by DP and HDMI encoders since those can have a
244 * target pixel clock != the port link clock (which is currently stored
245 * in adjusted_mode->clock).
247 int pixel_target_clock;
248 /* Used by SDVO (and if we ever fix it, HDMI). */
249 unsigned pixel_multiplier;
251 /* Panel fitter controls for gen2-gen4 + VLV */
255 u32 lvds_border_bits;
258 /* Panel fitter placement and size for Ironlake+ */
264 /* FDI configuration, only valid if has_pch_encoder is set. */
266 struct intel_link_m_n fdi_m_n;
270 struct drm_crtc base;
273 u8 lut_r[256], lut_g[256], lut_b[256];
275 * Whether the crtc and the connected output pipeline is active. Implies
276 * that crtc->enabled is set, i.e. the current mode configuration has
277 * some outputs connected to this crtc.
281 bool primary_disabled; /* is the crtc obscured by a plane? */
283 struct intel_overlay *overlay;
284 struct intel_unpin_work *unpin_work;
286 atomic_t unpin_work_count;
288 /* Display surface base address adjustement for pageflips. Note that on
289 * gen4+ this only adjusts up to a tile, offsets within a tile are
290 * handled in the hw itself (with the TILEOFF register). */
291 unsigned long dspaddr_offset;
293 struct drm_i915_gem_object *cursor_bo;
294 uint32_t cursor_addr;
295 int16_t cursor_x, cursor_y;
296 int16_t cursor_width, cursor_height;
299 struct intel_crtc_config config;
301 /* We can share PLLs across outputs if the timings match */
302 struct intel_pch_pll *pch_pll;
303 uint32_t ddi_pll_sel;
305 /* reset counter value when the last flip was submitted */
306 unsigned int reset_counter;
308 /* Access to these should be protected by dev_priv->irq_lock. */
309 bool cpu_fifo_underrun_disabled;
310 bool pch_fifo_underrun_disabled;
314 struct drm_plane base;
317 struct drm_i915_gem_object *obj;
320 u32 lut_r[1024], lut_g[1024], lut_b[1024];
322 unsigned int crtc_w, crtc_h;
323 uint32_t src_x, src_y;
324 uint32_t src_w, src_h;
325 void (*update_plane)(struct drm_plane *plane,
326 struct drm_framebuffer *fb,
327 struct drm_i915_gem_object *obj,
328 int crtc_x, int crtc_y,
329 unsigned int crtc_w, unsigned int crtc_h,
330 uint32_t x, uint32_t y,
331 uint32_t src_w, uint32_t src_h);
332 void (*disable_plane)(struct drm_plane *plane);
333 int (*update_colorkey)(struct drm_plane *plane,
334 struct drm_intel_sprite_colorkey *key);
335 void (*get_colorkey)(struct drm_plane *plane,
336 struct drm_intel_sprite_colorkey *key);
339 struct intel_watermark_params {
340 unsigned long fifo_size;
341 unsigned long max_wm;
342 unsigned long default_wm;
343 unsigned long guard_size;
344 unsigned long cacheline_size;
347 struct cxsr_latency {
350 unsigned long fsb_freq;
351 unsigned long mem_freq;
352 unsigned long display_sr;
353 unsigned long display_hpll_disable;
354 unsigned long cursor_sr;
355 unsigned long cursor_hpll_disable;
358 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
359 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
360 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
361 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
362 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
364 #define DIP_HEADER_SIZE 5
366 #define DIP_TYPE_AVI 0x82
367 #define DIP_VERSION_AVI 0x2
368 #define DIP_LEN_AVI 13
369 #define DIP_AVI_PR_1 0
370 #define DIP_AVI_PR_2 1
371 #define DIP_AVI_RGB_QUANT_RANGE_DEFAULT (0 << 2)
372 #define DIP_AVI_RGB_QUANT_RANGE_LIMITED (1 << 2)
373 #define DIP_AVI_RGB_QUANT_RANGE_FULL (2 << 2)
375 #define DIP_TYPE_SPD 0x83
376 #define DIP_VERSION_SPD 0x1
377 #define DIP_LEN_SPD 25
378 #define DIP_SPD_UNKNOWN 0
379 #define DIP_SPD_DSTB 0x1
380 #define DIP_SPD_DVDP 0x2
381 #define DIP_SPD_DVHS 0x3
382 #define DIP_SPD_HDDVR 0x4
383 #define DIP_SPD_DVC 0x5
384 #define DIP_SPD_DSC 0x6
385 #define DIP_SPD_VCD 0x7
386 #define DIP_SPD_GAME 0x8
387 #define DIP_SPD_PC 0x9
388 #define DIP_SPD_BD 0xa
389 #define DIP_SPD_SCD 0xb
391 struct dip_infoframe {
392 uint8_t type; /* HB0 */
393 uint8_t ver; /* HB1 */
394 uint8_t len; /* HB2 - body len, not including checksum */
395 uint8_t ecc; /* Header ECC */
396 uint8_t checksum; /* PB0 */
399 /* PB1 - Y 6:5, A 4:4, B 3:2, S 1:0 */
401 /* PB2 - C 7:6, M 5:4, R 3:0 */
403 /* PB3 - ITC 7:7, EC 6:4, Q 3:2, SC 1:0 */
407 /* PB5 - YQ 7:6, CN 5:4, PR 3:0 */
410 uint16_t top_bar_end;
411 uint16_t bottom_bar_start;
412 uint16_t left_bar_end;
413 uint16_t right_bar_start;
414 } __attribute__ ((packed)) avi;
419 } __attribute__ ((packed)) spd;
421 } __attribute__ ((packed)) body;
422 } __attribute__((packed));
427 uint32_t color_range;
428 bool color_range_auto;
431 enum hdmi_force_audio force_audio;
432 bool rgb_quant_range_selectable;
433 void (*write_infoframe)(struct drm_encoder *encoder,
434 struct dip_infoframe *frame);
435 void (*set_infoframes)(struct drm_encoder *encoder,
436 struct drm_display_mode *adjusted_mode);
439 #define DP_MAX_DOWNSTREAM_PORTS 0x10
440 #define DP_LINK_CONFIGURATION_SIZE 9
444 uint32_t aux_ch_ctl_reg;
446 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
448 enum hdmi_force_audio force_audio;
449 uint32_t color_range;
450 bool color_range_auto;
453 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
454 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
455 struct i2c_adapter adapter;
456 struct i2c_algo_dp_aux_data algo;
457 uint8_t train_set[4];
458 int panel_power_up_delay;
459 int panel_power_down_delay;
460 int panel_power_cycle_delay;
461 int backlight_on_delay;
462 int backlight_off_delay;
463 struct delayed_work panel_vdd_work;
465 struct intel_connector *attached_connector;
468 struct intel_digital_port {
469 struct intel_encoder base;
473 struct intel_hdmi hdmi;
477 vlv_dport_to_channel(struct intel_digital_port *dport)
479 switch (dport->port) {
489 static inline struct drm_crtc *
490 intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
492 struct drm_i915_private *dev_priv = dev->dev_private;
493 return dev_priv->pipe_to_crtc_mapping[pipe];
496 static inline struct drm_crtc *
497 intel_get_crtc_for_plane(struct drm_device *dev, int plane)
499 struct drm_i915_private *dev_priv = dev->dev_private;
500 return dev_priv->plane_to_crtc_mapping[plane];
503 struct intel_unpin_work {
504 struct work_struct work;
505 struct drm_crtc *crtc;
506 struct drm_i915_gem_object *old_fb_obj;
507 struct drm_i915_gem_object *pending_flip_obj;
508 struct drm_pending_vblank_event *event;
510 #define INTEL_FLIP_INACTIVE 0
511 #define INTEL_FLIP_PENDING 1
512 #define INTEL_FLIP_COMPLETE 2
513 bool enable_stall_check;
516 struct intel_fbc_work {
517 struct delayed_work work;
518 struct drm_crtc *crtc;
519 struct drm_framebuffer *fb;
523 int intel_pch_rawclk(struct drm_device *dev);
525 int intel_connector_update_modes(struct drm_connector *connector,
527 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
529 extern void intel_attach_force_audio_property(struct drm_connector *connector);
530 extern void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
532 extern bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
533 extern void intel_crt_init(struct drm_device *dev);
534 extern void intel_hdmi_init(struct drm_device *dev,
535 int hdmi_reg, enum port port);
536 extern void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
537 struct intel_connector *intel_connector);
538 extern struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
539 extern bool intel_hdmi_compute_config(struct intel_encoder *encoder,
540 struct intel_crtc_config *pipe_config);
541 extern void intel_dip_infoframe_csum(struct dip_infoframe *avi_if);
542 extern bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg,
544 extern void intel_dvo_init(struct drm_device *dev);
545 extern void intel_tv_init(struct drm_device *dev);
546 extern void intel_mark_busy(struct drm_device *dev);
547 extern void intel_mark_fb_busy(struct drm_i915_gem_object *obj);
548 extern void intel_mark_idle(struct drm_device *dev);
549 extern bool intel_lvds_init(struct drm_device *dev);
550 extern bool intel_is_dual_link_lvds(struct drm_device *dev);
551 extern void intel_dp_init(struct drm_device *dev, int output_reg,
553 extern void intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
554 struct intel_connector *intel_connector);
555 extern void intel_dp_init_link_config(struct intel_dp *intel_dp);
556 extern void intel_dp_start_link_train(struct intel_dp *intel_dp);
557 extern void intel_dp_complete_link_train(struct intel_dp *intel_dp);
558 extern void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
559 extern void intel_dp_encoder_destroy(struct drm_encoder *encoder);
560 extern void intel_dp_check_link_status(struct intel_dp *intel_dp);
561 extern bool intel_dp_compute_config(struct intel_encoder *encoder,
562 struct intel_crtc_config *pipe_config);
563 extern bool intel_dpd_is_edp(struct drm_device *dev);
564 extern void ironlake_edp_backlight_on(struct intel_dp *intel_dp);
565 extern void ironlake_edp_backlight_off(struct intel_dp *intel_dp);
566 extern void ironlake_edp_panel_on(struct intel_dp *intel_dp);
567 extern void ironlake_edp_panel_off(struct intel_dp *intel_dp);
568 extern void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
569 extern void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
570 extern int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
571 extern void intel_flush_display_plane(struct drm_i915_private *dev_priv,
575 extern int intel_panel_init(struct intel_panel *panel,
576 struct drm_display_mode *fixed_mode);
577 extern void intel_panel_fini(struct intel_panel *panel);
579 extern void intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
580 struct drm_display_mode *adjusted_mode);
581 extern void intel_pch_panel_fitting(struct intel_crtc *crtc,
582 struct intel_crtc_config *pipe_config,
584 extern void intel_gmch_panel_fitting(struct intel_crtc *crtc,
585 struct intel_crtc_config *pipe_config,
587 extern void intel_panel_set_backlight(struct drm_device *dev,
589 extern int intel_panel_setup_backlight(struct drm_connector *connector);
590 extern void intel_panel_enable_backlight(struct drm_device *dev,
592 extern void intel_panel_disable_backlight(struct drm_device *dev);
593 extern void intel_panel_destroy_backlight(struct drm_device *dev);
594 extern enum drm_connector_status intel_panel_detect(struct drm_device *dev);
596 struct intel_set_config {
597 struct drm_encoder **save_connector_encoders;
598 struct drm_crtc **save_encoder_crtcs;
604 extern int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
605 int x, int y, struct drm_framebuffer *old_fb);
606 extern void intel_modeset_disable(struct drm_device *dev);
607 extern void intel_crtc_restore_mode(struct drm_crtc *crtc);
608 extern void intel_crtc_load_lut(struct drm_crtc *crtc);
609 extern void intel_crtc_update_dpms(struct drm_crtc *crtc);
610 extern void intel_encoder_destroy(struct drm_encoder *encoder);
611 extern void intel_encoder_dpms(struct intel_encoder *encoder, int mode);
612 extern bool intel_encoder_check_is_cloned(struct intel_encoder *encoder);
613 extern void intel_connector_dpms(struct drm_connector *, int mode);
614 extern bool intel_connector_get_hw_state(struct intel_connector *connector);
615 extern void intel_modeset_check_state(struct drm_device *dev);
616 extern void intel_plane_restore(struct drm_plane *plane);
619 static inline struct intel_encoder *intel_attached_encoder(struct drm_connector *connector)
621 return to_intel_connector(connector)->encoder;
624 static inline struct intel_digital_port *
625 enc_to_dig_port(struct drm_encoder *encoder)
627 return container_of(encoder, struct intel_digital_port, base.base);
630 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
632 return &enc_to_dig_port(encoder)->dp;
635 static inline struct intel_digital_port *
636 dp_to_dig_port(struct intel_dp *intel_dp)
638 return container_of(intel_dp, struct intel_digital_port, dp);
641 static inline struct intel_digital_port *
642 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
644 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
647 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
648 struct intel_digital_port *port);
650 extern void intel_connector_attach_encoder(struct intel_connector *connector,
651 struct intel_encoder *encoder);
652 extern struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
654 extern struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
655 struct drm_crtc *crtc);
656 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
657 struct drm_file *file_priv);
658 extern enum transcoder
659 intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
661 extern void intel_wait_for_vblank(struct drm_device *dev, int pipe);
662 extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
663 extern int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
664 extern void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port);
666 struct intel_load_detect_pipe {
667 struct drm_framebuffer *release_fb;
668 bool load_detect_temp;
671 extern bool intel_get_load_detect_pipe(struct drm_connector *connector,
672 struct drm_display_mode *mode,
673 struct intel_load_detect_pipe *old);
674 extern void intel_release_load_detect_pipe(struct drm_connector *connector,
675 struct intel_load_detect_pipe *old);
677 extern void intelfb_restore(void);
678 extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
679 u16 blue, int regno);
680 extern void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
681 u16 *blue, int regno);
682 extern void intel_enable_clock_gating(struct drm_device *dev);
684 extern int intel_pin_and_fence_fb_obj(struct drm_device *dev,
685 struct drm_i915_gem_object *obj,
686 struct intel_ring_buffer *pipelined);
687 extern void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);
689 extern int intel_framebuffer_init(struct drm_device *dev,
690 struct intel_framebuffer *ifb,
691 struct drm_mode_fb_cmd2 *mode_cmd,
692 struct drm_i915_gem_object *obj);
693 extern int intel_fbdev_init(struct drm_device *dev);
694 extern void intel_fbdev_initial_config(struct drm_device *dev);
695 extern void intel_fbdev_fini(struct drm_device *dev);
696 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state);
697 extern void intel_prepare_page_flip(struct drm_device *dev, int plane);
698 extern void intel_finish_page_flip(struct drm_device *dev, int pipe);
699 extern void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
701 extern void intel_setup_overlay(struct drm_device *dev);
702 extern void intel_cleanup_overlay(struct drm_device *dev);
703 extern int intel_overlay_switch_off(struct intel_overlay *overlay);
704 extern int intel_overlay_put_image(struct drm_device *dev, void *data,
705 struct drm_file *file_priv);
706 extern int intel_overlay_attrs(struct drm_device *dev, void *data,
707 struct drm_file *file_priv);
709 extern void intel_fb_output_poll_changed(struct drm_device *dev);
710 extern void intel_fb_restore_mode(struct drm_device *dev);
712 extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
714 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
715 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
717 extern void intel_init_clock_gating(struct drm_device *dev);
718 extern void intel_suspend_hw(struct drm_device *dev);
719 extern void intel_write_eld(struct drm_encoder *encoder,
720 struct drm_display_mode *mode);
721 extern void intel_prepare_ddi(struct drm_device *dev);
722 extern void hsw_fdi_link_train(struct drm_crtc *crtc);
723 extern void intel_ddi_init(struct drm_device *dev, enum port port);
725 /* For use by IVB LP watermark workaround in intel_sprite.c */
726 extern void intel_update_watermarks(struct drm_device *dev);
727 extern void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
728 uint32_t sprite_width,
730 extern void intel_update_linetime_watermarks(struct drm_device *dev, int pipe,
731 struct drm_display_mode *mode);
733 extern unsigned long intel_gen4_compute_page_offset(int *x, int *y,
734 unsigned int tiling_mode,
738 extern int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
739 struct drm_file *file_priv);
740 extern int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
741 struct drm_file *file_priv);
743 extern u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg);
744 extern void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
747 /* Power-related functions, located in intel_pm.c */
748 extern void intel_init_pm(struct drm_device *dev);
750 extern bool intel_fbc_enabled(struct drm_device *dev);
751 extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval);
752 extern void intel_update_fbc(struct drm_device *dev);
754 extern void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
755 extern void intel_gpu_ips_teardown(void);
757 extern bool intel_display_power_enabled(struct drm_device *dev,
758 enum intel_display_power_domain domain);
759 extern void intel_init_power_well(struct drm_device *dev);
760 extern void intel_set_power_well(struct drm_device *dev, bool enable);
761 extern void intel_enable_gt_powersave(struct drm_device *dev);
762 extern void intel_disable_gt_powersave(struct drm_device *dev);
763 extern void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv);
764 extern void ironlake_teardown_rc6(struct drm_device *dev);
766 extern bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
768 extern int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
769 extern void intel_ddi_pll_init(struct drm_device *dev);
770 extern void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
771 extern void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
772 enum transcoder cpu_transcoder);
773 extern void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
774 extern void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
775 extern void intel_ddi_setup_hw_pll_state(struct drm_device *dev);
776 extern bool intel_ddi_pll_mode_set(struct drm_crtc *crtc, int clock);
777 extern void intel_ddi_put_crtc_pll(struct drm_crtc *crtc);
778 extern void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
779 extern void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
781 intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
782 extern void intel_ddi_fdi_disable(struct drm_crtc *crtc);
784 extern void intel_display_handle_reset(struct drm_device *dev);
785 extern bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
788 extern bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
789 enum transcoder pch_transcoder,
792 #endif /* __INTEL_DRV_H__ */