Pileus Git - ~andy/linux/blob - drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include "drmP.h"
  32 #include "drm.h"
  33 #include "drm_crtc.h"
  34 #include "drm_crtc_helper.h"
  35 #include "intel_drv.h"
  36 #include "i915_drm.h"
  37 #include "i915_drv.h"
  38 #include "drm_dp_helper.h"
  39
  40 #define DP_RECEIVER_CAP_SIZE    0xf
  41 #define DP_LINK_STATUS_SIZE     6
  42 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  43
  44 #define DP_LINK_CONFIGURATION_SIZE      9
  45
  46 struct intel_dp {
  47         struct intel_encoder base;
  48         uint32_t output_reg;
  49         uint32_t DP;
  50         uint8_t  link_configuration[DP_LINK_CONFIGURATION_SIZE];
  51         bool has_audio;
  52         enum hdmi_force_audio force_audio;
  53         uint32_t color_range;
  54         int dpms_mode;
  55         uint8_t link_bw;
  56         uint8_t lane_count;
  57         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
  58         struct i2c_adapter adapter;
  59         struct i2c_algo_dp_aux_data algo;
  60         bool is_pch_edp;
  61         uint8_t train_set[4];
  62         int panel_power_up_delay;
  63         int panel_power_down_delay;
  64         int panel_power_cycle_delay;
  65         int backlight_on_delay;
  66         int backlight_off_delay;
  67         struct drm_display_mode *panel_fixed_mode;  /* for eDP */
  68         struct delayed_work panel_vdd_work;
  69         bool want_panel_vdd;
  70 };
  71
  72 /**
  73  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  74  * @intel_dp: DP struct
  75  *
  76  * If a CPU or PCH DP output is attached to an eDP panel, this function
  77  * will return true, and false otherwise.
  78  */
  79 static bool is_edp(struct intel_dp *intel_dp)
  80 {
  81         return intel_dp->base.type == INTEL_OUTPUT_EDP;
  82 }
  83
  84 /**
  85  * is_pch_edp - is the port on the PCH and attached to an eDP panel?
  86  * @intel_dp: DP struct
  87  *
  88  * Returns true if the given DP struct corresponds to a PCH DP port attached
  89  * to an eDP panel, false otherwise.  Helpful for determining whether we
  90  * may need FDI resources for a given DP output or not.
  91  */
  92 static bool is_pch_edp(struct intel_dp *intel_dp)
  93 {
  94         return intel_dp->is_pch_edp;
  95 }
  96
  97 /**
  98  * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
  99  * @intel_dp: DP struct
 100  *
 101  * Returns true if the given DP struct corresponds to a CPU eDP port.
 102  */
 103 static bool is_cpu_edp(struct intel_dp *intel_dp)
 104 {
 105         return is_edp(intel_dp) && !is_pch_edp(intel_dp);
 106 }
 107
 108 static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
 109 {
 110         return container_of(encoder, struct intel_dp, base.base);
 111 }
 112
 113 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
 114 {
 115         return container_of(intel_attached_encoder(connector),
 116                             struct intel_dp, base);
 117 }
 118
 119 /**
 120  * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
 121  * @encoder: DRM encoder
 122  *
 123  * Return true if @encoder corresponds to a PCH attached eDP panel.  Needed
 124  * by intel_display.c.
 125  */
 126 bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
 127 {
 128         struct intel_dp *intel_dp;
 129
 130         if (!encoder)
 131                 return false;
 132
 133         intel_dp = enc_to_intel_dp(encoder);
 134
 135         return is_pch_edp(intel_dp);
 136 }
 137
 138 static void intel_dp_start_link_train(struct intel_dp *intel_dp);
 139 static void intel_dp_complete_link_train(struct intel_dp *intel_dp);
 140 static void intel_dp_link_down(struct intel_dp *intel_dp);
 141
 142 void
 143 intel_edp_link_config(struct intel_encoder *intel_encoder,
 144                        int *lane_num, int *link_bw)
 145 {
 146         struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
 147
 148         *lane_num = intel_dp->lane_count;
 149         if (intel_dp->link_bw == DP_LINK_BW_1_62)
 150                 *link_bw = 162000;
 151         else if (intel_dp->link_bw == DP_LINK_BW_2_7)
 152                 *link_bw = 270000;
 153 }
 154
 155 static int
 156 intel_dp_max_lane_count(struct intel_dp *intel_dp)
 157 {
 158         int max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
 159         switch (max_lane_count) {
 160         case 1: case 2: case 4:
 161                 break;
 162         default:
 163                 max_lane_count = 4;
 164         }
 165         return max_lane_count;
 166 }
 167
 168 static int
 169 intel_dp_max_link_bw(struct intel_dp *intel_dp)
 170 {
 171         int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
 172
 173         switch (max_link_bw) {
 174         case DP_LINK_BW_1_62:
 175         case DP_LINK_BW_2_7:
 176                 break;
 177         default:
 178                 max_link_bw = DP_LINK_BW_1_62;
 179                 break;
 180         }
 181         return max_link_bw;
 182 }
 183
 184 static int
 185 intel_dp_link_clock(uint8_t link_bw)
 186 {
 187         if (link_bw == DP_LINK_BW_2_7)
 188                 return 270000;
 189         else
 190                 return 162000;
 191 }
 192
 193 /*
 194  * The units on the numbers in the next two are... bizarre.  Examples will
 195  * make it clearer; this one parallels an example in the eDP spec.
 196  *
 197  * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
 198  *
 199  *     270000 * 1 * 8 / 10 == 216000
 200  *
 201  * The actual data capacity of that configuration is 2.16Gbit/s, so the
 202  * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 203  * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 204  * 119000.  At 18bpp that's 2142000 kilobits per second.
 205  *
 206  * Thus the strange-looking division by 10 in intel_dp_link_required, to
 207  * get the result in decakilobits instead of kilobits.
 208  */
 209
 210 static int
 211 intel_dp_link_required(int pixel_clock, int bpp)
 212 {
 213         return (pixel_clock * bpp + 9) / 10;
 214 }
 215
 216 static int
 217 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 218 {
 219         return (max_link_clock * max_lanes * 8) / 10;
 220 }
 221
 222 static bool
 223 intel_dp_adjust_dithering(struct intel_dp *intel_dp,
 224                           struct drm_display_mode *mode,
 225                           struct drm_display_mode *adjusted_mode)
 226 {
 227         int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
 228         int max_lanes = intel_dp_max_lane_count(intel_dp);
 229         int max_rate, mode_rate;
 230
 231         mode_rate = intel_dp_link_required(mode->clock, 24);
 232         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 233
 234         if (mode_rate > max_rate) {
 235                 mode_rate = intel_dp_link_required(mode->clock, 18);
 236                 if (mode_rate > max_rate)
 237                         return false;
 238
 239                 if (adjusted_mode)
 240                         adjusted_mode->private_flags
 241                                 |= INTEL_MODE_DP_FORCE_6BPC;
 242
 243                 return true;
 244         }
 245
 246         return true;
 247 }
 248
 249 static int
 250 intel_dp_mode_valid(struct drm_connector *connector,
 251                     struct drm_display_mode *mode)
 252 {
 253         struct intel_dp *intel_dp = intel_attached_dp(connector);
 254
 255         if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
 256                 if (mode->hdisplay > intel_dp->panel_fixed_mode->hdisplay)
 257                         return MODE_PANEL;
 258
 259                 if (mode->vdisplay > intel_dp->panel_fixed_mode->vdisplay)
 260                         return MODE_PANEL;
 261         }
 262
 263         if (!intel_dp_adjust_dithering(intel_dp, mode, NULL))
 264                 return MODE_CLOCK_HIGH;
 265
 266         if (mode->clock < 10000)
 267                 return MODE_CLOCK_LOW;
 268
 269         return MODE_OK;
 270 }
 271
 272 static uint32_t
 273 pack_aux(uint8_t *src, int src_bytes)
 274 {
 275         int     i;
 276         uint32_t v = 0;
 277
 278         if (src_bytes > 4)
 279                 src_bytes = 4;
 280         for (i = 0; i < src_bytes; i++)
 281                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 282         return v;
 283 }
 284
 285 static void
 286 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 287 {
 288         int i;
 289         if (dst_bytes > 4)
 290                 dst_bytes = 4;
 291         for (i = 0; i < dst_bytes; i++)
 292                 dst[i] = src >> ((3-i) * 8);
 293 }
 294
 295 /* hrawclock is 1/4 the FSB frequency */
 296 static int
 297 intel_hrawclk(struct drm_device *dev)
 298 {
 299         struct drm_i915_private *dev_priv = dev->dev_private;
 300         uint32_t clkcfg;
 301
 302         clkcfg = I915_READ(CLKCFG);
 303         switch (clkcfg & CLKCFG_FSB_MASK) {
 304         case CLKCFG_FSB_400:
 305                 return 100;
 306         case CLKCFG_FSB_533:
 307                 return 133;
 308         case CLKCFG_FSB_667:
 309                 return 166;
 310         case CLKCFG_FSB_800:
 311                 return 200;
 312         case CLKCFG_FSB_1067:
 313                 return 266;
 314         case CLKCFG_FSB_1333:
 315                 return 333;
 316         /* these two are just a guess; one of them might be right */
 317         case CLKCFG_FSB_1600:
 318         case CLKCFG_FSB_1600_ALT:
 319                 return 400;
 320         default:
 321                 return 133;
 322         }
 323 }
 324
 325 static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
 326 {
 327         struct drm_device *dev = intel_dp->base.base.dev;
 328         struct drm_i915_private *dev_priv = dev->dev_private;
 329
 330         return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
 331 }
 332
 333 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
 334 {
 335         struct drm_device *dev = intel_dp->base.base.dev;
 336         struct drm_i915_private *dev_priv = dev->dev_private;
 337
 338         return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
 339 }
 340
 341 static void
 342 intel_dp_check_edp(struct intel_dp *intel_dp)
 343 {
 344         struct drm_device *dev = intel_dp->base.base.dev;
 345         struct drm_i915_private *dev_priv = dev->dev_private;
 346
 347         if (!is_edp(intel_dp))
 348                 return;
 349         if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
 350                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 351                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 352                               I915_READ(PCH_PP_STATUS),
 353                               I915_READ(PCH_PP_CONTROL));
 354         }
 355 }
 356
 357 static int
 358 intel_dp_aux_ch(struct intel_dp *intel_dp,
 359                 uint8_t *send, int send_bytes,
 360                 uint8_t *recv, int recv_size)
 361 {
 362         uint32_t output_reg = intel_dp->output_reg;
 363         struct drm_device *dev = intel_dp->base.base.dev;
 364         struct drm_i915_private *dev_priv = dev->dev_private;
 365         uint32_t ch_ctl = output_reg + 0x10;
 366         uint32_t ch_data = ch_ctl + 4;
 367         int i;
 368         int recv_bytes;
 369         uint32_t status;
 370         uint32_t aux_clock_divider;
 371         int try, precharge = 5;
 372
 373         intel_dp_check_edp(intel_dp);
 374         /* The clock divider is based off the hrawclk,
 375          * and would like to run at 2MHz. So, take the
 376          * hrawclk value and divide by 2 and use that
 377          *
 378          * Note that PCH attached eDP panels should use a 125MHz input
 379          * clock divider.
 380          */
 381         if (is_cpu_edp(intel_dp)) {
 382                 if (IS_GEN6(dev) || IS_GEN7(dev))
 383                         aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
 384                 else
 385                         aux_clock_divider = 225; /* eDP input clock at 450Mhz */
 386         } else if (HAS_PCH_SPLIT(dev))
 387                 aux_clock_divider = 63; /* IRL input clock fixed at 125Mhz */
 388         else
 389                 aux_clock_divider = intel_hrawclk(dev) / 2;
 390
 391         /* Try to wait for any previous AUX channel activity */
 392         for (try = 0; try < 3; try++) {
 393                 status = I915_READ(ch_ctl);
 394                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 395                         break;
 396                 msleep(1);
 397         }
 398
 399         if (try == 3) {
 400                 WARN(1, "dp_aux_ch not started status 0x%08x\n",
 401                      I915_READ(ch_ctl));
 402                 return -EBUSY;
 403         }
 404
 405         /* Must try at least 3 times according to DP spec */
 406         for (try = 0; try < 5; try++) {
 407                 /* Load the send data into the aux channel data registers */
 408                 for (i = 0; i < send_bytes; i += 4)
 409                         I915_WRITE(ch_data + i,
 410                                    pack_aux(send + i, send_bytes - i));
 411
 412                 /* Send the command and wait for it to complete */
 413                 I915_WRITE(ch_ctl,
 414                            DP_AUX_CH_CTL_SEND_BUSY |
 415                            DP_AUX_CH_CTL_TIME_OUT_400us |
 416                            (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 417                            (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 418                            (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
 419                            DP_AUX_CH_CTL_DONE |
 420                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 421                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 422                 for (;;) {
 423                         status = I915_READ(ch_ctl);
 424                         if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 425                                 break;
 426                         udelay(100);
 427                 }
 428
 429                 /* Clear done status and any errors */
 430                 I915_WRITE(ch_ctl,
 431                            status |
 432                            DP_AUX_CH_CTL_DONE |
 433                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 434                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 435
 436                 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
 437                               DP_AUX_CH_CTL_RECEIVE_ERROR))
 438                         continue;
 439                 if (status & DP_AUX_CH_CTL_DONE)
 440                         break;
 441         }
 442
 443         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 444                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 445                 return -EBUSY;
 446         }
 447
 448         /* Check for timeout or receive error.
 449          * Timeouts occur when the sink is not connected
 450          */
 451         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 452                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 453                 return -EIO;
 454         }
 455
 456         /* Timeouts occur when the device isn't connected, so they're
 457          * "normal" -- don't fill the kernel log with these */
 458         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 459                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 460                 return -ETIMEDOUT;
 461         }
 462
 463         /* Unload any bytes sent back from the other side */
 464         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 465                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 466         if (recv_bytes > recv_size)
 467                 recv_bytes = recv_size;
 468
 469         for (i = 0; i < recv_bytes; i += 4)
 470                 unpack_aux(I915_READ(ch_data + i),
 471                            recv + i, recv_bytes - i);
 472
 473         return recv_bytes;
 474 }
 475
 476 /* Write data to the aux channel in native mode */
 477 static int
 478 intel_dp_aux_native_write(struct intel_dp *intel_dp,
 479                           uint16_t address, uint8_t *send, int send_bytes)
 480 {
 481         int ret;
 482         uint8_t msg[20];
 483         int msg_bytes;
 484         uint8_t ack;
 485
 486         intel_dp_check_edp(intel_dp);
 487         if (send_bytes > 16)
 488                 return -1;
 489         msg[0] = AUX_NATIVE_WRITE << 4;
 490         msg[1] = address >> 8;
 491         msg[2] = address & 0xff;
 492         msg[3] = send_bytes - 1;
 493         memcpy(&msg[4], send, send_bytes);
 494         msg_bytes = send_bytes + 4;
 495         for (;;) {
 496                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
 497                 if (ret < 0)
 498                         return ret;
 499                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
 500                         break;
 501                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 502                         udelay(100);
 503                 else
 504                         return -EIO;
 505         }
 506         return send_bytes;
 507 }
 508
 509 /* Write a single byte to the aux channel in native mode */
 510 static int
 511 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
 512                             uint16_t address, uint8_t byte)
 513 {
 514         return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
 515 }
 516
 517 /* read bytes from a native aux channel */
 518 static int
 519 intel_dp_aux_native_read(struct intel_dp *intel_dp,
 520                          uint16_t address, uint8_t *recv, int recv_bytes)
 521 {
 522         uint8_t msg[4];
 523         int msg_bytes;
 524         uint8_t reply[20];
 525         int reply_bytes;
 526         uint8_t ack;
 527         int ret;
 528
 529         intel_dp_check_edp(intel_dp);
 530         msg[0] = AUX_NATIVE_READ << 4;
 531         msg[1] = address >> 8;
 532         msg[2] = address & 0xff;
 533         msg[3] = recv_bytes - 1;
 534
 535         msg_bytes = 4;
 536         reply_bytes = recv_bytes + 1;
 537
 538         for (;;) {
 539                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
 540                                       reply, reply_bytes);
 541                 if (ret == 0)
 542                         return -EPROTO;
 543                 if (ret < 0)
 544                         return ret;
 545                 ack = reply[0];
 546                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
 547                         memcpy(recv, reply + 1, ret - 1);
 548                         return ret - 1;
 549                 }
 550                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 551                         udelay(100);
 552                 else
 553                         return -EIO;
 554         }
 555 }
 556
 557 static int
 558 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
 559                     uint8_t write_byte, uint8_t *read_byte)
 560 {
 561         struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
 562         struct intel_dp *intel_dp = container_of(adapter,
 563                                                 struct intel_dp,
 564                                                 adapter);
 565         uint16_t address = algo_data->address;
 566         uint8_t msg[5];
 567         uint8_t reply[2];
 568         unsigned retry;
 569         int msg_bytes;
 570         int reply_bytes;
 571         int ret;
 572
 573         intel_dp_check_edp(intel_dp);
 574         /* Set up the command byte */
 575         if (mode & MODE_I2C_READ)
 576                 msg[0] = AUX_I2C_READ << 4;
 577         else
 578                 msg[0] = AUX_I2C_WRITE << 4;
 579
 580         if (!(mode & MODE_I2C_STOP))
 581                 msg[0] |= AUX_I2C_MOT << 4;
 582
 583         msg[1] = address >> 8;
 584         msg[2] = address;
 585
 586         switch (mode) {
 587         case MODE_I2C_WRITE:
 588                 msg[3] = 0;
 589                 msg[4] = write_byte;
 590                 msg_bytes = 5;
 591                 reply_bytes = 1;
 592                 break;
 593         case MODE_I2C_READ:
 594                 msg[3] = 0;
 595                 msg_bytes = 4;
 596                 reply_bytes = 2;
 597                 break;
 598         default:
 599                 msg_bytes = 3;
 600                 reply_bytes = 1;
 601                 break;
 602         }
 603
 604         for (retry = 0; retry < 5; retry++) {
 605                 ret = intel_dp_aux_ch(intel_dp,
 606                                       msg, msg_bytes,
 607                                       reply, reply_bytes);
 608                 if (ret < 0) {
 609                         DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
 610                         return ret;
 611                 }
 612
 613                 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
 614                 case AUX_NATIVE_REPLY_ACK:
 615                         /* I2C-over-AUX Reply field is only valid
 616                          * when paired with AUX ACK.
 617                          */
 618                         break;
 619                 case AUX_NATIVE_REPLY_NACK:
 620                         DRM_DEBUG_KMS("aux_ch native nack\n");
 621                         return -EREMOTEIO;
 622                 case AUX_NATIVE_REPLY_DEFER:
 623                         udelay(100);
 624                         continue;
 625                 default:
 626                         DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
 627                                   reply[0]);
 628                         return -EREMOTEIO;
 629                 }
 630
 631                 switch (reply[0] & AUX_I2C_REPLY_MASK) {
 632                 case AUX_I2C_REPLY_ACK:
 633                         if (mode == MODE_I2C_READ) {
 634                                 *read_byte = reply[1];
 635                         }
 636                         return reply_bytes - 1;
 637                 case AUX_I2C_REPLY_NACK:
 638                         DRM_DEBUG_KMS("aux_i2c nack\n");
 639                         return -EREMOTEIO;
 640                 case AUX_I2C_REPLY_DEFER:
 641                         DRM_DEBUG_KMS("aux_i2c defer\n");
 642                         udelay(100);
 643                         break;
 644                 default:
 645                         DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
 646                         return -EREMOTEIO;
 647                 }
 648         }
 649
 650         DRM_ERROR("too many retries, giving up\n");
 651         return -EREMOTEIO;
 652 }
 653
 654 static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
 655 static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 656
 657 static int
 658 intel_dp_i2c_init(struct intel_dp *intel_dp,
 659                   struct intel_connector *intel_connector, const char *name)
 660 {
 661         int     ret;
 662
 663         DRM_DEBUG_KMS("i2c_init %s\n", name);
 664         intel_dp->algo.running = false;
 665         intel_dp->algo.address = 0;
 666         intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
 667
 668         memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
 669         intel_dp->adapter.owner = THIS_MODULE;
 670         intel_dp->adapter.class = I2C_CLASS_DDC;
 671         strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
 672         intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
 673         intel_dp->adapter.algo_data = &intel_dp->algo;
 674         intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
 675
 676         ironlake_edp_panel_vdd_on(intel_dp);
 677         ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
 678         ironlake_edp_panel_vdd_off(intel_dp, false);
 679         return ret;
 680 }
 681
 682 static bool
 683 intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
 684                     struct drm_display_mode *adjusted_mode)
 685 {
 686         struct drm_device *dev = encoder->dev;
 687         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 688         int lane_count, clock;
 689         int max_lane_count = intel_dp_max_lane_count(intel_dp);
 690         int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
 691         int bpp, mode_rate;
 692         static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
 693
 694         if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
 695                 intel_fixed_panel_mode(intel_dp->panel_fixed_mode, adjusted_mode);
 696                 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
 697                                         mode, adjusted_mode);
 698                 /*
 699                  * the mode->clock is used to calculate the Data&Link M/N
 700                  * of the pipe. For the eDP the fixed clock should be used.
 701                  */
 702                 mode->clock = intel_dp->panel_fixed_mode->clock;
 703         }
 704
 705         DRM_DEBUG_KMS("DP link computation with max lane count %i "
 706                       "max bw %02x pixel clock %iKHz\n",
 707                       max_lane_count, bws[max_clock], mode->clock);
 708
 709         if (!intel_dp_adjust_dithering(intel_dp, mode, adjusted_mode))
 710                 return false;
 711
 712         bpp = adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24;
 713         mode_rate = intel_dp_link_required(mode->clock, bpp);
 714
 715         for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
 716                 for (clock = 0; clock <= max_clock; clock++) {
 717                         int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
 718
 719                         if (mode_rate <= link_avail) {
 720                                 intel_dp->link_bw = bws[clock];
 721                                 intel_dp->lane_count = lane_count;
 722                                 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
 723                                 DRM_DEBUG_KMS("DP link bw %02x lane "
 724                                                 "count %d clock %d bpp %d\n",
 725                                        intel_dp->link_bw, intel_dp->lane_count,
 726                                        adjusted_mode->clock, bpp);
 727                                 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
 728                                               mode_rate, link_avail);
 729                                 return true;
 730                         }
 731                 }
 732         }
 733
 734         return false;
 735 }
 736
 737 struct intel_dp_m_n {
 738         uint32_t        tu;
 739         uint32_t        gmch_m;
 740         uint32_t        gmch_n;
 741         uint32_t        link_m;
 742         uint32_t        link_n;
 743 };
 744
 745 static void
 746 intel_reduce_ratio(uint32_t *num, uint32_t *den)
 747 {
 748         while (*num > 0xffffff || *den > 0xffffff) {
 749                 *num >>= 1;
 750                 *den >>= 1;
 751         }
 752 }
 753
 754 static void
 755 intel_dp_compute_m_n(int bpp,
 756                      int nlanes,
 757                      int pixel_clock,
 758                      int link_clock,
 759                      struct intel_dp_m_n *m_n)
 760 {
 761         m_n->tu = 64;
 762         m_n->gmch_m = (pixel_clock * bpp) >> 3;
 763         m_n->gmch_n = link_clock * nlanes;
 764         intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
 765         m_n->link_m = pixel_clock;
 766         m_n->link_n = link_clock;
 767         intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
 768 }
 769
 770 void
 771 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
 772                  struct drm_display_mode *adjusted_mode)
 773 {
 774         struct drm_device *dev = crtc->dev;
 775         struct drm_mode_config *mode_config = &dev->mode_config;
 776         struct drm_encoder *encoder;
 777         struct drm_i915_private *dev_priv = dev->dev_private;
 778         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 779         int lane_count = 4;
 780         struct intel_dp_m_n m_n;
 781         int pipe = intel_crtc->pipe;
 782
 783         /*
 784          * Find the lane count in the intel_encoder private
 785          */
 786         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
 787                 struct intel_dp *intel_dp;
 788
 789                 if (encoder->crtc != crtc)
 790                         continue;
 791
 792                 intel_dp = enc_to_intel_dp(encoder);
 793                 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
 794                     intel_dp->base.type == INTEL_OUTPUT_EDP)
 795                 {
 796                         lane_count = intel_dp->lane_count;
 797                         break;
 798                 }
 799         }
 800
 801         /*
 802          * Compute the GMCH and Link ratios. The '3' here is
 803          * the number of bytes_per_pixel post-LUT, which we always
 804          * set up for 8-bits of R/G/B, or 3 bytes total.
 805          */
 806         intel_dp_compute_m_n(intel_crtc->bpp, lane_count,
 807                              mode->clock, adjusted_mode->clock, &m_n);
 808
 809         if (HAS_PCH_SPLIT(dev)) {
 810                 I915_WRITE(TRANSDATA_M1(pipe),
 811                            ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 812                            m_n.gmch_m);
 813                 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
 814                 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
 815                 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
 816         } else {
 817                 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
 818                            ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 819                            m_n.gmch_m);
 820                 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
 821                 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
 822                 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
 823         }
 824 }
 825
 826 static void ironlake_edp_pll_on(struct drm_encoder *encoder);
 827 static void ironlake_edp_pll_off(struct drm_encoder *encoder);
 828
 829 static void
 830 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
 831                   struct drm_display_mode *adjusted_mode)
 832 {
 833         struct drm_device *dev = encoder->dev;
 834         struct drm_i915_private *dev_priv = dev->dev_private;
 835         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 836         struct drm_crtc *crtc = intel_dp->base.base.crtc;
 837         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 838
 839         /* Turn on the eDP PLL if needed */
 840         if (is_edp(intel_dp)) {
 841                 if (!is_pch_edp(intel_dp))
 842                         ironlake_edp_pll_on(encoder);
 843                 else
 844                         ironlake_edp_pll_off(encoder);
 845         }
 846
 847         /*
 848          * There are four kinds of DP registers:
 849          *
 850          *      IBX PCH
 851          *      SNB CPU
 852          *      IVB CPU
 853          *      CPT PCH
 854          *
 855          * IBX PCH and CPU are the same for almost everything,
 856          * except that the CPU DP PLL is configured in this
 857          * register
 858          *
 859          * CPT PCH is quite different, having many bits moved
 860          * to the TRANS_DP_CTL register instead. That
 861          * configuration happens (oddly) in ironlake_pch_enable
 862          */
 863
 864         /* Preserve the BIOS-computed detected bit. This is
 865          * supposed to be read-only.
 866          */
 867         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 868         intel_dp->DP |=  DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 869
 870         /* Handle DP bits in common between all three register formats */
 871
 872         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 873
 874         switch (intel_dp->lane_count) {
 875         case 1:
 876                 intel_dp->DP |= DP_PORT_WIDTH_1;
 877                 break;
 878         case 2:
 879                 intel_dp->DP |= DP_PORT_WIDTH_2;
 880                 break;
 881         case 4:
 882                 intel_dp->DP |= DP_PORT_WIDTH_4;
 883                 break;
 884         }
 885         if (intel_dp->has_audio) {
 886                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
 887                                  pipe_name(intel_crtc->pipe));
 888                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
 889                 intel_write_eld(encoder, adjusted_mode);
 890         }
 891         memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
 892         intel_dp->link_configuration[0] = intel_dp->link_bw;
 893         intel_dp->link_configuration[1] = intel_dp->lane_count;
 894         intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
 895         /*
 896          * Check for DPCD version > 1.1 and enhanced framing support
 897          */
 898         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
 899             (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
 900                 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 901         }
 902
 903         /* Split out the IBX/CPU vs CPT settings */
 904
 905         if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
 906                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 907                         intel_dp->DP |= DP_SYNC_HS_HIGH;
 908                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 909                         intel_dp->DP |= DP_SYNC_VS_HIGH;
 910                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 911
 912                 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
 913                         intel_dp->DP |= DP_ENHANCED_FRAMING;
 914
 915                 intel_dp->DP |= intel_crtc->pipe << 29;
 916
 917                 /* don't miss out required setting for eDP */
 918                 intel_dp->DP |= DP_PLL_ENABLE;
 919                 if (adjusted_mode->clock < 200000)
 920                         intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 921                 else
 922                         intel_dp->DP |= DP_PLL_FREQ_270MHZ;
 923         } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
 924                 intel_dp->DP |= intel_dp->color_range;
 925
 926                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 927                         intel_dp->DP |= DP_SYNC_HS_HIGH;
 928                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 929                         intel_dp->DP |= DP_SYNC_VS_HIGH;
 930                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
 931
 932                 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
 933                         intel_dp->DP |= DP_ENHANCED_FRAMING;
 934
 935                 if (intel_crtc->pipe == 1)
 936                         intel_dp->DP |= DP_PIPEB_SELECT;
 937
 938                 if (is_cpu_edp(intel_dp)) {
 939                         /* don't miss out required setting for eDP */
 940                         intel_dp->DP |= DP_PLL_ENABLE;
 941                         if (adjusted_mode->clock < 200000)
 942                                 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 943                         else
 944                                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
 945                 }
 946         } else {
 947                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 948         }
 949 }
 950
 951 #define IDLE_ON_MASK            (PP_ON | 0        | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
 952 #define IDLE_ON_VALUE           (PP_ON | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
 953
 954 #define IDLE_OFF_MASK           (PP_ON | 0        | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
 955 #define IDLE_OFF_VALUE          (0     | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
 956
 957 #define IDLE_CYCLE_MASK         (PP_ON | 0        | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
 958 #define IDLE_CYCLE_VALUE        (0     | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
 959
 960 static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
 961                                        u32 mask,
 962                                        u32 value)
 963 {
 964         struct drm_device *dev = intel_dp->base.base.dev;
 965         struct drm_i915_private *dev_priv = dev->dev_private;
 966
 967         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
 968                       mask, value,
 969                       I915_READ(PCH_PP_STATUS),
 970                       I915_READ(PCH_PP_CONTROL));
 971
 972         if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
 973                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
 974                           I915_READ(PCH_PP_STATUS),
 975                           I915_READ(PCH_PP_CONTROL));
 976         }
 977 }
 978
 979 static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
 980 {
 981         DRM_DEBUG_KMS("Wait for panel power on\n");
 982         ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
 983 }
 984
 985 static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
 986 {
 987         DRM_DEBUG_KMS("Wait for panel power off time\n");
 988         ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
 989 }
 990
 991 static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
 992 {
 993         DRM_DEBUG_KMS("Wait for panel power cycle\n");
 994         ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
 995 }
 996
 997
 998 /* Read the current pp_control value, unlocking the register if it
 999  * is locked
1000  */
1001
1002 static  u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
1003 {
1004         u32     control = I915_READ(PCH_PP_CONTROL);
1005
1006         control &= ~PANEL_UNLOCK_MASK;
1007         control |= PANEL_UNLOCK_REGS;
1008         return control;
1009 }
1010
1011 static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
1012 {
1013         struct drm_device *dev = intel_dp->base.base.dev;
1014         struct drm_i915_private *dev_priv = dev->dev_private;
1015         u32 pp;
1016
1017         if (!is_edp(intel_dp))
1018                 return;
1019         DRM_DEBUG_KMS("Turn eDP VDD on\n");
1020
1021         WARN(intel_dp->want_panel_vdd,
1022              "eDP VDD already requested on\n");
1023
1024         intel_dp->want_panel_vdd = true;
1025
1026         if (ironlake_edp_have_panel_vdd(intel_dp)) {
1027                 DRM_DEBUG_KMS("eDP VDD already on\n");
1028                 return;
1029         }
1030
1031         if (!ironlake_edp_have_panel_power(intel_dp))
1032                 ironlake_wait_panel_power_cycle(intel_dp);
1033
1034         pp = ironlake_get_pp_control(dev_priv);
1035         pp |= EDP_FORCE_VDD;
1036         I915_WRITE(PCH_PP_CONTROL, pp);
1037         POSTING_READ(PCH_PP_CONTROL);
1038         DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1039                       I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
1040
1041         /*
1042          * If the panel wasn't on, delay before accessing aux channel
1043          */
1044         if (!ironlake_edp_have_panel_power(intel_dp)) {
1045                 DRM_DEBUG_KMS("eDP was not running\n");
1046                 msleep(intel_dp->panel_power_up_delay);
1047         }
1048 }
1049
1050 static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
1051 {
1052         struct drm_device *dev = intel_dp->base.base.dev;
1053         struct drm_i915_private *dev_priv = dev->dev_private;
1054         u32 pp;
1055
1056         if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
1057                 pp = ironlake_get_pp_control(dev_priv);
1058                 pp &= ~EDP_FORCE_VDD;
1059                 I915_WRITE(PCH_PP_CONTROL, pp);
1060                 POSTING_READ(PCH_PP_CONTROL);
1061
1062                 /* Make sure sequencer is idle before allowing subsequent activity */
1063                 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1064                               I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
1065
1066                 msleep(intel_dp->panel_power_down_delay);
1067         }
1068 }
1069
1070 static void ironlake_panel_vdd_work(struct work_struct *__work)
1071 {
1072         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1073                                                  struct intel_dp, panel_vdd_work);
1074         struct drm_device *dev = intel_dp->base.base.dev;
1075
1076         mutex_lock(&dev->mode_config.mutex);
1077         ironlake_panel_vdd_off_sync(intel_dp);
1078         mutex_unlock(&dev->mode_config.mutex);
1079 }
1080
1081 static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1082 {
1083         if (!is_edp(intel_dp))
1084                 return;
1085
1086         DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1087         WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1088
1089         intel_dp->want_panel_vdd = false;
1090
1091         if (sync) {
1092                 ironlake_panel_vdd_off_sync(intel_dp);
1093         } else {
1094                 /*
1095                  * Queue the timer to fire a long
1096                  * time from now (relative to the power down delay)
1097                  * to keep the panel power up across a sequence of operations
1098                  */
1099                 schedule_delayed_work(&intel_dp->panel_vdd_work,
1100                                       msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1101         }
1102 }
1103
1104 static void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1105 {
1106         struct drm_device *dev = intel_dp->base.base.dev;
1107         struct drm_i915_private *dev_priv = dev->dev_private;
1108         u32 pp;
1109
1110         if (!is_edp(intel_dp))
1111                 return;
1112
1113         DRM_DEBUG_KMS("Turn eDP power on\n");
1114
1115         if (ironlake_edp_have_panel_power(intel_dp)) {
1116                 DRM_DEBUG_KMS("eDP power already on\n");
1117                 return;
1118         }
1119
1120         ironlake_wait_panel_power_cycle(intel_dp);
1121
1122         pp = ironlake_get_pp_control(dev_priv);
1123         if (IS_GEN5(dev)) {
1124                 /* ILK workaround: disable reset around power sequence */
1125                 pp &= ~PANEL_POWER_RESET;
1126                 I915_WRITE(PCH_PP_CONTROL, pp);
1127                 POSTING_READ(PCH_PP_CONTROL);
1128         }
1129
1130         pp |= POWER_TARGET_ON;
1131         if (!IS_GEN5(dev))
1132                 pp |= PANEL_POWER_RESET;
1133
1134         I915_WRITE(PCH_PP_CONTROL, pp);
1135         POSTING_READ(PCH_PP_CONTROL);
1136
1137         ironlake_wait_panel_on(intel_dp);
1138
1139         if (IS_GEN5(dev)) {
1140                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1141                 I915_WRITE(PCH_PP_CONTROL, pp);
1142                 POSTING_READ(PCH_PP_CONTROL);
1143         }
1144 }
1145
1146 static void ironlake_edp_panel_off(struct intel_dp *intel_dp)
1147 {
1148         struct drm_device *dev = intel_dp->base.base.dev;
1149         struct drm_i915_private *dev_priv = dev->dev_private;
1150         u32 pp;
1151
1152         if (!is_edp(intel_dp))
1153                 return;
1154
1155         DRM_DEBUG_KMS("Turn eDP power off\n");
1156
1157         WARN(intel_dp->want_panel_vdd, "Cannot turn power off while VDD is on\n");
1158         ironlake_panel_vdd_off_sync(intel_dp); /* finish any pending work */
1159
1160         pp = ironlake_get_pp_control(dev_priv);
1161         pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1162         I915_WRITE(PCH_PP_CONTROL, pp);
1163         POSTING_READ(PCH_PP_CONTROL);
1164
1165         ironlake_wait_panel_off(intel_dp);
1166 }
1167
1168 static void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1169 {
1170         struct drm_device *dev = intel_dp->base.base.dev;
1171         struct drm_i915_private *dev_priv = dev->dev_private;
1172         u32 pp;
1173
1174         if (!is_edp(intel_dp))
1175                 return;
1176
1177         DRM_DEBUG_KMS("\n");
1178         /*
1179          * If we enable the backlight right away following a panel power
1180          * on, we may see slight flicker as the panel syncs with the eDP
1181          * link.  So delay a bit to make sure the image is solid before
1182          * allowing it to appear.
1183          */
1184         msleep(intel_dp->backlight_on_delay);
1185         pp = ironlake_get_pp_control(dev_priv);
1186         pp |= EDP_BLC_ENABLE;
1187         I915_WRITE(PCH_PP_CONTROL, pp);
1188         POSTING_READ(PCH_PP_CONTROL);
1189 }
1190
1191 static void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1192 {
1193         struct drm_device *dev = intel_dp->base.base.dev;
1194         struct drm_i915_private *dev_priv = dev->dev_private;
1195         u32 pp;
1196
1197         if (!is_edp(intel_dp))
1198                 return;
1199
1200         DRM_DEBUG_KMS("\n");
1201         pp = ironlake_get_pp_control(dev_priv);
1202         pp &= ~EDP_BLC_ENABLE;
1203         I915_WRITE(PCH_PP_CONTROL, pp);
1204         POSTING_READ(PCH_PP_CONTROL);
1205         msleep(intel_dp->backlight_off_delay);
1206 }
1207
1208 static void ironlake_edp_pll_on(struct drm_encoder *encoder)
1209 {
1210         struct drm_device *dev = encoder->dev;
1211         struct drm_i915_private *dev_priv = dev->dev_private;
1212         u32 dpa_ctl;
1213
1214         DRM_DEBUG_KMS("\n");
1215         dpa_ctl = I915_READ(DP_A);
1216         dpa_ctl |= DP_PLL_ENABLE;
1217         I915_WRITE(DP_A, dpa_ctl);
1218         POSTING_READ(DP_A);
1219         udelay(200);
1220 }
1221
1222 static void ironlake_edp_pll_off(struct drm_encoder *encoder)
1223 {
1224         struct drm_device *dev = encoder->dev;
1225         struct drm_i915_private *dev_priv = dev->dev_private;
1226         u32 dpa_ctl;
1227
1228         dpa_ctl = I915_READ(DP_A);
1229         dpa_ctl &= ~DP_PLL_ENABLE;
1230         I915_WRITE(DP_A, dpa_ctl);
1231         POSTING_READ(DP_A);
1232         udelay(200);
1233 }
1234
1235 /* If the sink supports it, try to set the power state appropriately */
1236 static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1237 {
1238         int ret, i;
1239
1240         /* Should have a valid DPCD by this point */
1241         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1242                 return;
1243
1244         if (mode != DRM_MODE_DPMS_ON) {
1245                 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1246                                                   DP_SET_POWER_D3);
1247                 if (ret != 1)
1248                         DRM_DEBUG_DRIVER("failed to write sink power state\n");
1249         } else {
1250                 /*
1251                  * When turning on, we need to retry for 1ms to give the sink
1252                  * time to wake up.
1253                  */
1254                 for (i = 0; i < 3; i++) {
1255                         ret = intel_dp_aux_native_write_1(intel_dp,
1256                                                           DP_SET_POWER,
1257                                                           DP_SET_POWER_D0);
1258                         if (ret == 1)
1259                                 break;
1260                         msleep(1);
1261                 }
1262         }
1263 }
1264
1265 static void intel_dp_prepare(struct drm_encoder *encoder)
1266 {
1267         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1268
1269         ironlake_edp_backlight_off(intel_dp);
1270         ironlake_edp_panel_off(intel_dp);
1271
1272         /* Wake up the sink first */
1273         ironlake_edp_panel_vdd_on(intel_dp);
1274         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1275         intel_dp_link_down(intel_dp);
1276         ironlake_edp_panel_vdd_off(intel_dp, false);
1277
1278         /* Make sure the panel is off before trying to
1279          * change the mode
1280          */
1281 }
1282
1283 static void intel_dp_commit(struct drm_encoder *encoder)
1284 {
1285         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1286         struct drm_device *dev = encoder->dev;
1287         struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
1288
1289         ironlake_edp_panel_vdd_on(intel_dp);
1290         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1291         intel_dp_start_link_train(intel_dp);
1292         ironlake_edp_panel_on(intel_dp);
1293         ironlake_edp_panel_vdd_off(intel_dp, true);
1294         intel_dp_complete_link_train(intel_dp);
1295         ironlake_edp_backlight_on(intel_dp);
1296
1297         intel_dp->dpms_mode = DRM_MODE_DPMS_ON;
1298
1299         if (HAS_PCH_CPT(dev))
1300                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
1301 }
1302
1303 static void
1304 intel_dp_dpms(struct drm_encoder *encoder, int mode)
1305 {
1306         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1307         struct drm_device *dev = encoder->dev;
1308         struct drm_i915_private *dev_priv = dev->dev_private;
1309         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1310
1311         if (mode != DRM_MODE_DPMS_ON) {
1312                 ironlake_edp_backlight_off(intel_dp);
1313                 ironlake_edp_panel_off(intel_dp);
1314
1315                 ironlake_edp_panel_vdd_on(intel_dp);
1316                 intel_dp_sink_dpms(intel_dp, mode);
1317                 intel_dp_link_down(intel_dp);
1318                 ironlake_edp_panel_vdd_off(intel_dp, false);
1319
1320                 if (is_cpu_edp(intel_dp))
1321                         ironlake_edp_pll_off(encoder);
1322         } else {
1323                 if (is_cpu_edp(intel_dp))
1324                         ironlake_edp_pll_on(encoder);
1325
1326                 ironlake_edp_panel_vdd_on(intel_dp);
1327                 intel_dp_sink_dpms(intel_dp, mode);
1328                 if (!(dp_reg & DP_PORT_EN)) {
1329                         intel_dp_start_link_train(intel_dp);
1330                         ironlake_edp_panel_on(intel_dp);
1331                         ironlake_edp_panel_vdd_off(intel_dp, true);
1332                         intel_dp_complete_link_train(intel_dp);
1333                 } else
1334                         ironlake_edp_panel_vdd_off(intel_dp, false);
1335                 ironlake_edp_backlight_on(intel_dp);
1336         }
1337         intel_dp->dpms_mode = mode;
1338 }
1339
1340 /*
1341  * Native read with retry for link status and receiver capability reads for
1342  * cases where the sink may still be asleep.
1343  */
1344 static bool
1345 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1346                                uint8_t *recv, int recv_bytes)
1347 {
1348         int ret, i;
1349
1350         /*
1351          * Sinks are *supposed* to come up within 1ms from an off state,
1352          * but we're also supposed to retry 3 times per the spec.
1353          */
1354         for (i = 0; i < 3; i++) {
1355                 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1356                                                recv_bytes);
1357                 if (ret == recv_bytes)
1358                         return true;
1359                 msleep(1);
1360         }
1361
1362         return false;
1363 }
1364
1365 /*
1366  * Fetch AUX CH registers 0x202 - 0x207 which contain
1367  * link status information
1368  */
1369 static bool
1370 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1371 {
1372         return intel_dp_aux_native_read_retry(intel_dp,
1373                                               DP_LANE0_1_STATUS,
1374                                               link_status,
1375                                               DP_LINK_STATUS_SIZE);
1376 }
1377
1378 static uint8_t
1379 intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1380                      int r)
1381 {
1382         return link_status[r - DP_LANE0_1_STATUS];
1383 }
1384
1385 static uint8_t
1386 intel_get_adjust_request_voltage(uint8_t adjust_request[2],
1387                                  int lane)
1388 {
1389         int         s = ((lane & 1) ?
1390                          DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
1391                          DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
1392         uint8_t l = adjust_request[lane>>1];
1393
1394         return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
1395 }
1396
1397 static uint8_t
1398 intel_get_adjust_request_pre_emphasis(uint8_t adjust_request[2],
1399                                       int lane)
1400 {
1401         int         s = ((lane & 1) ?
1402                          DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
1403                          DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
1404         uint8_t l = adjust_request[lane>>1];
1405
1406         return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
1407 }
1408
1409
1410 #if 0
1411 static char     *voltage_names[] = {
1412         "0.4V", "0.6V", "0.8V", "1.2V"
1413 };
1414 static char     *pre_emph_names[] = {
1415         "0dB", "3.5dB", "6dB", "9.5dB"
1416 };
1417 static char     *link_train_names[] = {
1418         "pattern 1", "pattern 2", "idle", "off"
1419 };
1420 #endif
1421
1422 /*
1423  * These are source-specific values; current Intel hardware supports
1424  * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1425  */
1426
1427 static uint8_t
1428 intel_dp_voltage_max(struct intel_dp *intel_dp)
1429 {
1430         struct drm_device *dev = intel_dp->base.base.dev;
1431
1432         if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
1433                 return DP_TRAIN_VOLTAGE_SWING_800;
1434         else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1435                 return DP_TRAIN_VOLTAGE_SWING_1200;
1436         else
1437                 return DP_TRAIN_VOLTAGE_SWING_800;
1438 }
1439
1440 static uint8_t
1441 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1442 {
1443         struct drm_device *dev = intel_dp->base.base.dev;
1444
1445         if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1446                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1447                 case DP_TRAIN_VOLTAGE_SWING_400:
1448                         return DP_TRAIN_PRE_EMPHASIS_6;
1449                 case DP_TRAIN_VOLTAGE_SWING_600:
1450                 case DP_TRAIN_VOLTAGE_SWING_800:
1451                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1452                 default:
1453                         return DP_TRAIN_PRE_EMPHASIS_0;
1454                 }
1455         } else {
1456                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1457                 case DP_TRAIN_VOLTAGE_SWING_400:
1458                         return DP_TRAIN_PRE_EMPHASIS_6;
1459                 case DP_TRAIN_VOLTAGE_SWING_600:
1460                         return DP_TRAIN_PRE_EMPHASIS_6;
1461                 case DP_TRAIN_VOLTAGE_SWING_800:
1462                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1463                 case DP_TRAIN_VOLTAGE_SWING_1200:
1464                 default:
1465                         return DP_TRAIN_PRE_EMPHASIS_0;
1466                 }
1467         }
1468 }
1469
1470 static void
1471 intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1472 {
1473         uint8_t v = 0;
1474         uint8_t p = 0;
1475         int lane;
1476         uint8_t *adjust_request = link_status + (DP_ADJUST_REQUEST_LANE0_1 - DP_LANE0_1_STATUS);
1477         uint8_t voltage_max;
1478         uint8_t preemph_max;
1479
1480         for (lane = 0; lane < intel_dp->lane_count; lane++) {
1481                 uint8_t this_v = intel_get_adjust_request_voltage(adjust_request, lane);
1482                 uint8_t this_p = intel_get_adjust_request_pre_emphasis(adjust_request, lane);
1483
1484                 if (this_v > v)
1485                         v = this_v;
1486                 if (this_p > p)
1487                         p = this_p;
1488         }
1489
1490         voltage_max = intel_dp_voltage_max(intel_dp);
1491         if (v >= voltage_max)
1492                 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
1493
1494         preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1495         if (p >= preemph_max)
1496                 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1497
1498         for (lane = 0; lane < 4; lane++)
1499                 intel_dp->train_set[lane] = v | p;
1500 }
1501
1502 static uint32_t
1503 intel_dp_signal_levels(uint8_t train_set)
1504 {
1505         uint32_t        signal_levels = 0;
1506
1507         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1508         case DP_TRAIN_VOLTAGE_SWING_400:
1509         default:
1510                 signal_levels |= DP_VOLTAGE_0_4;
1511                 break;
1512         case DP_TRAIN_VOLTAGE_SWING_600:
1513                 signal_levels |= DP_VOLTAGE_0_6;
1514                 break;
1515         case DP_TRAIN_VOLTAGE_SWING_800:
1516                 signal_levels |= DP_VOLTAGE_0_8;
1517                 break;
1518         case DP_TRAIN_VOLTAGE_SWING_1200:
1519                 signal_levels |= DP_VOLTAGE_1_2;
1520                 break;
1521         }
1522         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1523         case DP_TRAIN_PRE_EMPHASIS_0:
1524         default:
1525                 signal_levels |= DP_PRE_EMPHASIS_0;
1526                 break;
1527         case DP_TRAIN_PRE_EMPHASIS_3_5:
1528                 signal_levels |= DP_PRE_EMPHASIS_3_5;
1529                 break;
1530         case DP_TRAIN_PRE_EMPHASIS_6:
1531                 signal_levels |= DP_PRE_EMPHASIS_6;
1532                 break;
1533         case DP_TRAIN_PRE_EMPHASIS_9_5:
1534                 signal_levels |= DP_PRE_EMPHASIS_9_5;
1535                 break;
1536         }
1537         return signal_levels;
1538 }
1539
1540 /* Gen6's DP voltage swing and pre-emphasis control */
1541 static uint32_t
1542 intel_gen6_edp_signal_levels(uint8_t train_set)
1543 {
1544         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1545                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1546         switch (signal_levels) {
1547         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1548         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1549                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1550         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1551                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1552         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1553         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1554                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1555         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1556         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1557                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1558         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1559         case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1560                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1561         default:
1562                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1563                               "0x%x\n", signal_levels);
1564                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1565         }
1566 }
1567
1568 /* Gen7's DP voltage swing and pre-emphasis control */
1569 static uint32_t
1570 intel_gen7_edp_signal_levels(uint8_t train_set)
1571 {
1572         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1573                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1574         switch (signal_levels) {
1575         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1576                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1577         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1578                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1579         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1580                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1581
1582         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1583                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1584         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1585                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1586
1587         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1588                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1589         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1590                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1591
1592         default:
1593                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1594                               "0x%x\n", signal_levels);
1595                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1596         }
1597 }
1598
1599 static uint8_t
1600 intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1601                       int lane)
1602 {
1603         int s = (lane & 1) * 4;
1604         uint8_t l = link_status[lane>>1];
1605
1606         return (l >> s) & 0xf;
1607 }
1608
1609 /* Check for clock recovery is done on all channels */
1610 static bool
1611 intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1612 {
1613         int lane;
1614         uint8_t lane_status;
1615
1616         for (lane = 0; lane < lane_count; lane++) {
1617                 lane_status = intel_get_lane_status(link_status, lane);
1618                 if ((lane_status & DP_LANE_CR_DONE) == 0)
1619                         return false;
1620         }
1621         return true;
1622 }
1623
1624 /* Check to see if channel eq is done on all channels */
1625 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1626                          DP_LANE_CHANNEL_EQ_DONE|\
1627                          DP_LANE_SYMBOL_LOCKED)
1628 static bool
1629 intel_channel_eq_ok(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1630 {
1631         uint8_t lane_align;
1632         uint8_t lane_status;
1633         int lane;
1634
1635         lane_align = intel_dp_link_status(link_status,
1636                                           DP_LANE_ALIGN_STATUS_UPDATED);
1637         if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
1638                 return false;
1639         for (lane = 0; lane < intel_dp->lane_count; lane++) {
1640                 lane_status = intel_get_lane_status(link_status, lane);
1641                 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
1642                         return false;
1643         }
1644         return true;
1645 }
1646
1647 static bool
1648 intel_dp_set_link_train(struct intel_dp *intel_dp,
1649                         uint32_t dp_reg_value,
1650                         uint8_t dp_train_pat)
1651 {
1652         struct drm_device *dev = intel_dp->base.base.dev;
1653         struct drm_i915_private *dev_priv = dev->dev_private;
1654         int ret;
1655
1656         I915_WRITE(intel_dp->output_reg, dp_reg_value);
1657         POSTING_READ(intel_dp->output_reg);
1658
1659         intel_dp_aux_native_write_1(intel_dp,
1660                                     DP_TRAINING_PATTERN_SET,
1661                                     dp_train_pat);
1662
1663         ret = intel_dp_aux_native_write(intel_dp,
1664                                         DP_TRAINING_LANE0_SET,
1665                                         intel_dp->train_set,
1666                                         intel_dp->lane_count);
1667         if (ret != intel_dp->lane_count)
1668                 return false;
1669
1670         return true;
1671 }
1672
1673 /* Enable corresponding port and start training pattern 1 */
1674 static void
1675 intel_dp_start_link_train(struct intel_dp *intel_dp)
1676 {
1677         struct drm_device *dev = intel_dp->base.base.dev;
1678         struct drm_i915_private *dev_priv = dev->dev_private;
1679         struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
1680         int i;
1681         uint8_t voltage;
1682         bool clock_recovery = false;
1683         int voltage_tries, loop_tries;
1684         u32 reg;
1685         uint32_t DP = intel_dp->DP;
1686
1687         /*
1688          * On CPT we have to enable the port in training pattern 1, which
1689          * will happen below in intel_dp_set_link_train.  Otherwise, enable
1690          * the port and wait for it to become active.
1691          */
1692         if (!HAS_PCH_CPT(dev)) {
1693                 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
1694                 POSTING_READ(intel_dp->output_reg);
1695                 intel_wait_for_vblank(dev, intel_crtc->pipe);
1696         }
1697
1698         /* Write the link configuration data */
1699         intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1700                                   intel_dp->link_configuration,
1701                                   DP_LINK_CONFIGURATION_SIZE);
1702
1703         DP |= DP_PORT_EN;
1704
1705         if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
1706                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1707         else
1708                 DP &= ~DP_LINK_TRAIN_MASK;
1709         memset(intel_dp->train_set, 0, 4);
1710         voltage = 0xff;
1711         voltage_tries = 0;
1712         loop_tries = 0;
1713         clock_recovery = false;
1714         for (;;) {
1715                 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1716                 uint8_t     link_status[DP_LINK_STATUS_SIZE];
1717                 uint32_t    signal_levels;
1718
1719
1720                 if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1721                         signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1722                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1723                 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1724                         signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1725                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1726                 } else {
1727                         signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
1728                         DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n", signal_levels);
1729                         DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1730                 }
1731
1732                 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
1733                         reg = DP | DP_LINK_TRAIN_PAT_1_CPT;
1734                 else
1735                         reg = DP | DP_LINK_TRAIN_PAT_1;
1736
1737                 if (!intel_dp_set_link_train(intel_dp, reg,
1738                                              DP_TRAINING_PATTERN_1 |
1739                                              DP_LINK_SCRAMBLING_DISABLE))
1740                         break;
1741                 /* Set training pattern 1 */
1742
1743                 udelay(100);
1744                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
1745                         DRM_ERROR("failed to get link status\n");
1746                         break;
1747                 }
1748
1749                 if (intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1750                         DRM_DEBUG_KMS("clock recovery OK\n");
1751                         clock_recovery = true;
1752                         break;
1753                 }
1754
1755                 /* Check to see if we've tried the max voltage */
1756                 for (i = 0; i < intel_dp->lane_count; i++)
1757                         if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1758                                 break;
1759                 if (i == intel_dp->lane_count) {
1760                         ++loop_tries;
1761                         if (loop_tries == 5) {
1762                                 DRM_DEBUG_KMS("too many full retries, give up\n");
1763                                 break;
1764                         }
1765                         memset(intel_dp->train_set, 0, 4);
1766                         voltage_tries = 0;
1767                         continue;
1768                 }
1769
1770                 /* Check to see if we've tried the same voltage 5 times */
1771                 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1772                         ++voltage_tries;
1773                         if (voltage_tries == 5) {
1774                                 DRM_DEBUG_KMS("too many voltage retries, give up\n");
1775                                 break;
1776                         }
1777                 } else
1778                         voltage_tries = 0;
1779                 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1780
1781                 /* Compute new intel_dp->train_set as requested by target */
1782                 intel_get_adjust_train(intel_dp, link_status);
1783         }
1784
1785         intel_dp->DP = DP;
1786 }
1787
1788 static void
1789 intel_dp_complete_link_train(struct intel_dp *intel_dp)
1790 {
1791         struct drm_device *dev = intel_dp->base.base.dev;
1792         struct drm_i915_private *dev_priv = dev->dev_private;
1793         bool channel_eq = false;
1794         int tries, cr_tries;
1795         u32 reg;
1796         uint32_t DP = intel_dp->DP;
1797
1798         /* channel equalization */
1799         tries = 0;
1800         cr_tries = 0;
1801         channel_eq = false;
1802         for (;;) {
1803                 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1804                 uint32_t    signal_levels;
1805                 uint8_t     link_status[DP_LINK_STATUS_SIZE];
1806
1807                 if (cr_tries > 5) {
1808                         DRM_ERROR("failed to train DP, aborting\n");
1809                         intel_dp_link_down(intel_dp);
1810                         break;
1811                 }
1812
1813                 if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1814                         signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1815                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1816                 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1817                         signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1818                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1819                 } else {
1820                         signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
1821                         DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1822                 }
1823
1824                 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
1825                         reg = DP | DP_LINK_TRAIN_PAT_2_CPT;
1826                 else
1827                         reg = DP | DP_LINK_TRAIN_PAT_2;
1828
1829                 /* channel eq pattern */
1830                 if (!intel_dp_set_link_train(intel_dp, reg,
1831                                              DP_TRAINING_PATTERN_2 |
1832                                              DP_LINK_SCRAMBLING_DISABLE))
1833                         break;
1834
1835                 udelay(400);
1836                 if (!intel_dp_get_link_status(intel_dp, link_status))
1837                         break;
1838
1839                 /* Make sure clock is still ok */
1840                 if (!intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1841                         intel_dp_start_link_train(intel_dp);
1842                         cr_tries++;
1843                         continue;
1844                 }
1845
1846                 if (intel_channel_eq_ok(intel_dp, link_status)) {
1847                         channel_eq = true;
1848                         break;
1849                 }
1850
1851                 /* Try 5 times, then try clock recovery if that fails */
1852                 if (tries > 5) {
1853                         intel_dp_link_down(intel_dp);
1854                         intel_dp_start_link_train(intel_dp);
1855                         tries = 0;
1856                         cr_tries++;
1857                         continue;
1858                 }
1859
1860                 /* Compute new intel_dp->train_set as requested by target */
1861                 intel_get_adjust_train(intel_dp, link_status);
1862                 ++tries;
1863         }
1864
1865         if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
1866                 reg = DP | DP_LINK_TRAIN_OFF_CPT;
1867         else
1868                 reg = DP | DP_LINK_TRAIN_OFF;
1869
1870         I915_WRITE(intel_dp->output_reg, reg);
1871         POSTING_READ(intel_dp->output_reg);
1872         intel_dp_aux_native_write_1(intel_dp,
1873                                     DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1874 }
1875
1876 static void
1877 intel_dp_link_down(struct intel_dp *intel_dp)
1878 {
1879         struct drm_device *dev = intel_dp->base.base.dev;
1880         struct drm_i915_private *dev_priv = dev->dev_private;
1881         uint32_t DP = intel_dp->DP;
1882
1883         if ((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)
1884                 return;
1885
1886         DRM_DEBUG_KMS("\n");
1887
1888         if (is_edp(intel_dp)) {
1889                 DP &= ~DP_PLL_ENABLE;
1890                 I915_WRITE(intel_dp->output_reg, DP);
1891                 POSTING_READ(intel_dp->output_reg);
1892                 udelay(100);
1893         }
1894
1895         if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
1896                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1897                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
1898         } else {
1899                 DP &= ~DP_LINK_TRAIN_MASK;
1900                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1901         }
1902         POSTING_READ(intel_dp->output_reg);
1903
1904         msleep(17);
1905
1906         if (is_edp(intel_dp)) {
1907                 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
1908                         DP |= DP_LINK_TRAIN_OFF_CPT;
1909                 else
1910                         DP |= DP_LINK_TRAIN_OFF;
1911         }
1912
1913         if (!HAS_PCH_CPT(dev) &&
1914             I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
1915                 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1916
1917                 /* Hardware workaround: leaving our transcoder select
1918                  * set to transcoder B while it's off will prevent the
1919                  * corresponding HDMI output on transcoder A.
1920                  *
1921                  * Combine this with another hardware workaround:
1922                  * transcoder select bit can only be cleared while the
1923                  * port is enabled.
1924                  */
1925                 DP &= ~DP_PIPEB_SELECT;
1926                 I915_WRITE(intel_dp->output_reg, DP);
1927
1928                 /* Changes to enable or select take place the vblank
1929                  * after being written.
1930                  */
1931                 if (crtc == NULL) {
1932                         /* We can arrive here never having been attached
1933                          * to a CRTC, for instance, due to inheriting
1934                          * random state from the BIOS.
1935                          *
1936                          * If the pipe is not running, play safe and
1937                          * wait for the clocks to stabilise before
1938                          * continuing.
1939                          */
1940                         POSTING_READ(intel_dp->output_reg);
1941                         msleep(50);
1942                 } else
1943                         intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
1944         }
1945
1946         DP &= ~DP_AUDIO_OUTPUT_ENABLE;
1947         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
1948         POSTING_READ(intel_dp->output_reg);
1949         msleep(intel_dp->panel_power_down_delay);
1950 }
1951
1952 static bool
1953 intel_dp_get_dpcd(struct intel_dp *intel_dp)
1954 {
1955         if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
1956                                            sizeof(intel_dp->dpcd)) &&
1957             (intel_dp->dpcd[DP_DPCD_REV] != 0)) {
1958                 return true;
1959         }
1960
1961         return false;
1962 }
1963
1964 static void
1965 intel_dp_probe_oui(struct intel_dp *intel_dp)
1966 {
1967         u8 buf[3];
1968
1969         if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
1970                 return;
1971
1972         if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
1973                 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
1974                               buf[0], buf[1], buf[2]);
1975
1976         if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
1977                 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
1978                               buf[0], buf[1], buf[2]);
1979 }
1980
1981 static bool
1982 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
1983 {
1984         int ret;
1985
1986         ret = intel_dp_aux_native_read_retry(intel_dp,
1987                                              DP_DEVICE_SERVICE_IRQ_VECTOR,
1988                                              sink_irq_vector, 1);
1989         if (!ret)
1990                 return false;
1991
1992         return true;
1993 }
1994
1995 static void
1996 intel_dp_handle_test_request(struct intel_dp *intel_dp)
1997 {
1998         /* NAK by default */
1999         intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_ACK);
2000 }
2001
2002 /*
2003  * According to DP spec
2004  * 5.1.2:
2005  *  1. Read DPCD
2006  *  2. Configure link according to Receiver Capabilities
2007  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
2008  *  4. Check link status on receipt of hot-plug interrupt
2009  */
2010
2011 static void
2012 intel_dp_check_link_status(struct intel_dp *intel_dp)
2013 {
2014         u8 sink_irq_vector;
2015         u8 link_status[DP_LINK_STATUS_SIZE];
2016
2017         if (intel_dp->dpms_mode != DRM_MODE_DPMS_ON)
2018                 return;
2019
2020         if (!intel_dp->base.base.crtc)
2021                 return;
2022
2023         /* Try to read receiver status if the link appears to be up */
2024         if (!intel_dp_get_link_status(intel_dp, link_status)) {
2025                 intel_dp_link_down(intel_dp);
2026                 return;
2027         }
2028
2029         /* Now read the DPCD to see if it's actually running */
2030         if (!intel_dp_get_dpcd(intel_dp)) {
2031                 intel_dp_link_down(intel_dp);
2032                 return;
2033         }
2034
2035         /* Try to read the source of the interrupt */
2036         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2037             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2038                 /* Clear interrupt source */
2039                 intel_dp_aux_native_write_1(intel_dp,
2040                                             DP_DEVICE_SERVICE_IRQ_VECTOR,
2041                                             sink_irq_vector);
2042
2043                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2044                         intel_dp_handle_test_request(intel_dp);
2045                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2046                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2047         }
2048
2049         if (!intel_channel_eq_ok(intel_dp, link_status)) {
2050                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2051                               drm_get_encoder_name(&intel_dp->base.base));
2052                 intel_dp_start_link_train(intel_dp);
2053                 intel_dp_complete_link_train(intel_dp);
2054         }
2055 }
2056
2057 static enum drm_connector_status
2058 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2059 {
2060         if (intel_dp_get_dpcd(intel_dp))
2061                 return connector_status_connected;
2062         return connector_status_disconnected;
2063 }
2064
2065 static enum drm_connector_status
2066 ironlake_dp_detect(struct intel_dp *intel_dp)
2067 {
2068         enum drm_connector_status status;
2069
2070         /* Can't disconnect eDP, but you can close the lid... */
2071         if (is_edp(intel_dp)) {
2072                 status = intel_panel_detect(intel_dp->base.base.dev);
2073                 if (status == connector_status_unknown)
2074                         status = connector_status_connected;
2075                 return status;
2076         }
2077
2078         return intel_dp_detect_dpcd(intel_dp);
2079 }
2080
2081 static enum drm_connector_status
2082 g4x_dp_detect(struct intel_dp *intel_dp)
2083 {
2084         struct drm_device *dev = intel_dp->base.base.dev;
2085         struct drm_i915_private *dev_priv = dev->dev_private;
2086         uint32_t temp, bit;
2087
2088         switch (intel_dp->output_reg) {
2089         case DP_B:
2090                 bit = DPB_HOTPLUG_INT_STATUS;
2091                 break;
2092         case DP_C:
2093                 bit = DPC_HOTPLUG_INT_STATUS;
2094                 break;
2095         case DP_D:
2096                 bit = DPD_HOTPLUG_INT_STATUS;
2097                 break;
2098         default:
2099                 return connector_status_unknown;
2100         }
2101
2102         temp = I915_READ(PORT_HOTPLUG_STAT);
2103
2104         if ((temp & bit) == 0)
2105                 return connector_status_disconnected;
2106
2107         return intel_dp_detect_dpcd(intel_dp);
2108 }
2109
2110 static struct edid *
2111 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2112 {
2113         struct intel_dp *intel_dp = intel_attached_dp(connector);
2114         struct edid     *edid;
2115
2116         ironlake_edp_panel_vdd_on(intel_dp);
2117         edid = drm_get_edid(connector, adapter);
2118         ironlake_edp_panel_vdd_off(intel_dp, false);
2119         return edid;
2120 }
2121
2122 static int
2123 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2124 {
2125         struct intel_dp *intel_dp = intel_attached_dp(connector);
2126         int     ret;
2127
2128         ironlake_edp_panel_vdd_on(intel_dp);
2129         ret = intel_ddc_get_modes(connector, adapter);
2130         ironlake_edp_panel_vdd_off(intel_dp, false);
2131         return ret;
2132 }
2133
2134
2135 /**
2136  * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
2137  *
2138  * \return true if DP port is connected.
2139  * \return false if DP port is disconnected.
2140  */
2141 static enum drm_connector_status
2142 intel_dp_detect(struct drm_connector *connector, bool force)
2143 {
2144         struct intel_dp *intel_dp = intel_attached_dp(connector);
2145         struct drm_device *dev = intel_dp->base.base.dev;
2146         enum drm_connector_status status;
2147         struct edid *edid = NULL;
2148
2149         intel_dp->has_audio = false;
2150
2151         if (HAS_PCH_SPLIT(dev))
2152                 status = ironlake_dp_detect(intel_dp);
2153         else
2154                 status = g4x_dp_detect(intel_dp);
2155
2156         DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
2157                       intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2],
2158                       intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5],
2159                       intel_dp->dpcd[6], intel_dp->dpcd[7]);
2160
2161         if (status != connector_status_connected)
2162                 return status;
2163
2164         intel_dp_probe_oui(intel_dp);
2165
2166         if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2167                 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
2168         } else {
2169                 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2170                 if (edid) {
2171                         intel_dp->has_audio = drm_detect_monitor_audio(edid);
2172                         connector->display_info.raw_edid = NULL;
2173                         kfree(edid);
2174                 }
2175         }
2176
2177         return connector_status_connected;
2178 }
2179
2180 static int intel_dp_get_modes(struct drm_connector *connector)
2181 {
2182         struct intel_dp *intel_dp = intel_attached_dp(connector);
2183         struct drm_device *dev = intel_dp->base.base.dev;
2184         struct drm_i915_private *dev_priv = dev->dev_private;
2185         int ret;
2186
2187         /* We should parse the EDID data and find out if it has an audio sink
2188          */
2189
2190         ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
2191         if (ret) {
2192                 if (is_edp(intel_dp) && !intel_dp->panel_fixed_mode) {
2193                         struct drm_display_mode *newmode;
2194                         list_for_each_entry(newmode, &connector->probed_modes,
2195                                             head) {
2196                                 if ((newmode->type & DRM_MODE_TYPE_PREFERRED)) {
2197                                         intel_dp->panel_fixed_mode =
2198                                                 drm_mode_duplicate(dev, newmode);
2199                                         break;
2200                                 }
2201                         }
2202                 }
2203                 return ret;
2204         }
2205
2206         /* if eDP has no EDID, try to use fixed panel mode from VBT */
2207         if (is_edp(intel_dp)) {
2208                 /* initialize panel mode from VBT if available for eDP */
2209                 if (intel_dp->panel_fixed_mode == NULL && dev_priv->lfp_lvds_vbt_mode != NULL) {
2210                         intel_dp->panel_fixed_mode =
2211                                 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
2212                         if (intel_dp->panel_fixed_mode) {
2213                                 intel_dp->panel_fixed_mode->type |=
2214                                         DRM_MODE_TYPE_PREFERRED;
2215                         }
2216                 }
2217                 if (intel_dp->panel_fixed_mode) {
2218                         struct drm_display_mode *mode;
2219                         mode = drm_mode_duplicate(dev, intel_dp->panel_fixed_mode);
2220                         drm_mode_probed_add(connector, mode);
2221                         return 1;
2222                 }
2223         }
2224         return 0;
2225 }
2226
2227 static bool
2228 intel_dp_detect_audio(struct drm_connector *connector)
2229 {
2230         struct intel_dp *intel_dp = intel_attached_dp(connector);
2231         struct edid *edid;
2232         bool has_audio = false;
2233
2234         edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2235         if (edid) {
2236                 has_audio = drm_detect_monitor_audio(edid);
2237
2238                 connector->display_info.raw_edid = NULL;
2239                 kfree(edid);
2240         }
2241
2242         return has_audio;
2243 }
2244
2245 static int
2246 intel_dp_set_property(struct drm_connector *connector,
2247                       struct drm_property *property,
2248                       uint64_t val)
2249 {
2250         struct drm_i915_private *dev_priv = connector->dev->dev_private;
2251         struct intel_dp *intel_dp = intel_attached_dp(connector);
2252         int ret;
2253
2254         ret = drm_connector_property_set_value(connector, property, val);
2255         if (ret)
2256                 return ret;
2257
2258         if (property == dev_priv->force_audio_property) {
2259                 int i = val;
2260                 bool has_audio;
2261
2262                 if (i == intel_dp->force_audio)
2263                         return 0;
2264
2265                 intel_dp->force_audio = i;
2266
2267                 if (i == HDMI_AUDIO_AUTO)
2268                         has_audio = intel_dp_detect_audio(connector);
2269                 else
2270                         has_audio = (i == HDMI_AUDIO_ON);
2271
2272                 if (has_audio == intel_dp->has_audio)
2273                         return 0;
2274
2275                 intel_dp->has_audio = has_audio;
2276                 goto done;
2277         }
2278
2279         if (property == dev_priv->broadcast_rgb_property) {
2280                 if (val == !!intel_dp->color_range)
2281                         return 0;
2282
2283                 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
2284                 goto done;
2285         }
2286
2287         return -EINVAL;
2288
2289 done:
2290         if (intel_dp->base.base.crtc) {
2291                 struct drm_crtc *crtc = intel_dp->base.base.crtc;
2292                 drm_crtc_helper_set_mode(crtc, &crtc->mode,
2293                                          crtc->x, crtc->y,
2294                                          crtc->fb);
2295         }
2296
2297         return 0;
2298 }
2299
2300 static void
2301 intel_dp_destroy(struct drm_connector *connector)
2302 {
2303         struct drm_device *dev = connector->dev;
2304
2305         if (intel_dpd_is_edp(dev))
2306                 intel_panel_destroy_backlight(dev);
2307
2308         drm_sysfs_connector_remove(connector);
2309         drm_connector_cleanup(connector);
2310         kfree(connector);
2311 }
2312
2313 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2314 {
2315         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2316
2317         i2c_del_adapter(&intel_dp->adapter);
2318         drm_encoder_cleanup(encoder);
2319         if (is_edp(intel_dp)) {
2320                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2321                 ironlake_panel_vdd_off_sync(intel_dp);
2322         }
2323         kfree(intel_dp);
2324 }
2325
2326 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
2327         .dpms = intel_dp_dpms,
2328         .mode_fixup = intel_dp_mode_fixup,
2329         .prepare = intel_dp_prepare,
2330         .mode_set = intel_dp_mode_set,
2331         .commit = intel_dp_commit,
2332 };
2333
2334 static const struct drm_connector_funcs intel_dp_connector_funcs = {
2335         .dpms = drm_helper_connector_dpms,
2336         .detect = intel_dp_detect,
2337         .fill_modes = drm_helper_probe_single_connector_modes,
2338         .set_property = intel_dp_set_property,
2339         .destroy = intel_dp_destroy,
2340 };
2341
2342 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2343         .get_modes = intel_dp_get_modes,
2344         .mode_valid = intel_dp_mode_valid,
2345         .best_encoder = intel_best_encoder,
2346 };
2347
2348 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
2349         .destroy = intel_dp_encoder_destroy,
2350 };
2351
2352 static void
2353 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
2354 {
2355         struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
2356
2357         intel_dp_check_link_status(intel_dp);
2358 }
2359
2360 /* Return which DP Port should be selected for Transcoder DP control */
2361 int
2362 intel_trans_dp_port_sel(struct drm_crtc *crtc)
2363 {
2364         struct drm_device *dev = crtc->dev;
2365         struct drm_mode_config *mode_config = &dev->mode_config;
2366         struct drm_encoder *encoder;
2367
2368         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
2369                 struct intel_dp *intel_dp;
2370
2371                 if (encoder->crtc != crtc)
2372                         continue;
2373
2374                 intel_dp = enc_to_intel_dp(encoder);
2375                 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
2376                     intel_dp->base.type == INTEL_OUTPUT_EDP)
2377                         return intel_dp->output_reg;
2378         }
2379
2380         return -1;
2381 }
2382
2383 /* check the VBT to see whether the eDP is on DP-D port */
2384 bool intel_dpd_is_edp(struct drm_device *dev)
2385 {
2386         struct drm_i915_private *dev_priv = dev->dev_private;
2387         struct child_device_config *p_child;
2388         int i;
2389
2390         if (!dev_priv->child_dev_num)
2391                 return false;
2392
2393         for (i = 0; i < dev_priv->child_dev_num; i++) {
2394                 p_child = dev_priv->child_dev + i;
2395
2396                 if (p_child->dvo_port == PORT_IDPD &&
2397                     p_child->device_type == DEVICE_TYPE_eDP)
2398                         return true;
2399         }
2400         return false;
2401 }
2402
2403 static void
2404 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2405 {
2406         intel_attach_force_audio_property(connector);
2407         intel_attach_broadcast_rgb_property(connector);
2408 }
2409
2410 void
2411 intel_dp_init(struct drm_device *dev, int output_reg)
2412 {
2413         struct drm_i915_private *dev_priv = dev->dev_private;
2414         struct drm_connector *connector;
2415         struct intel_dp *intel_dp;
2416         struct intel_encoder *intel_encoder;
2417         struct intel_connector *intel_connector;
2418         const char *name = NULL;
2419         int type;
2420
2421         intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
2422         if (!intel_dp)
2423                 return;
2424
2425         intel_dp->output_reg = output_reg;
2426         intel_dp->dpms_mode = -1;
2427
2428         intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
2429         if (!intel_connector) {
2430                 kfree(intel_dp);
2431                 return;
2432         }
2433         intel_encoder = &intel_dp->base;
2434
2435         if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
2436                 if (intel_dpd_is_edp(dev))
2437                         intel_dp->is_pch_edp = true;
2438
2439         if (output_reg == DP_A || is_pch_edp(intel_dp)) {
2440                 type = DRM_MODE_CONNECTOR_eDP;
2441                 intel_encoder->type = INTEL_OUTPUT_EDP;
2442         } else {
2443                 type = DRM_MODE_CONNECTOR_DisplayPort;
2444                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2445         }
2446
2447         connector = &intel_connector->base;
2448         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
2449         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2450
2451         connector->polled = DRM_CONNECTOR_POLL_HPD;
2452
2453         if (output_reg == DP_B || output_reg == PCH_DP_B)
2454                 intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
2455         else if (output_reg == DP_C || output_reg == PCH_DP_C)
2456                 intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
2457         else if (output_reg == DP_D || output_reg == PCH_DP_D)
2458                 intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
2459
2460         if (is_edp(intel_dp)) {
2461                 intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
2462                 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
2463                                   ironlake_panel_vdd_work);
2464         }
2465
2466         intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2467
2468         connector->interlace_allowed = true;
2469         connector->doublescan_allowed = 0;
2470
2471         drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
2472                          DRM_MODE_ENCODER_TMDS);
2473         drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
2474
2475         intel_connector_attach_encoder(intel_connector, intel_encoder);
2476         drm_sysfs_connector_add(connector);
2477
2478         /* Set up the DDC bus. */
2479         switch (output_reg) {
2480                 case DP_A:
2481                         name = "DPDDC-A";
2482                         break;
2483                 case DP_B:
2484                 case PCH_DP_B:
2485                         dev_priv->hotplug_supported_mask |=
2486                                 HDMIB_HOTPLUG_INT_STATUS;
2487                         name = "DPDDC-B";
2488                         break;
2489                 case DP_C:
2490                 case PCH_DP_C:
2491                         dev_priv->hotplug_supported_mask |=
2492                                 HDMIC_HOTPLUG_INT_STATUS;
2493                         name = "DPDDC-C";
2494                         break;
2495                 case DP_D:
2496                 case PCH_DP_D:
2497                         dev_priv->hotplug_supported_mask |=
2498                                 HDMID_HOTPLUG_INT_STATUS;
2499                         name = "DPDDC-D";
2500                         break;
2501         }
2502
2503         /* Cache some DPCD data in the eDP case */
2504         if (is_edp(intel_dp)) {
2505                 bool ret;
2506                 struct edp_power_seq    cur, vbt;
2507                 u32 pp_on, pp_off, pp_div;
2508
2509                 pp_on = I915_READ(PCH_PP_ON_DELAYS);
2510                 pp_off = I915_READ(PCH_PP_OFF_DELAYS);
2511                 pp_div = I915_READ(PCH_PP_DIVISOR);
2512
2513                 if (!pp_on || !pp_off || !pp_div) {
2514                         DRM_INFO("bad panel power sequencing delays, disabling panel\n");
2515                         intel_dp_encoder_destroy(&intel_dp->base.base);
2516                         intel_dp_destroy(&intel_connector->base);
2517                         return;
2518                 }
2519
2520                 /* Pull timing values out of registers */
2521                 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2522                         PANEL_POWER_UP_DELAY_SHIFT;
2523
2524                 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2525                         PANEL_LIGHT_ON_DELAY_SHIFT;
2526
2527                 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2528                         PANEL_LIGHT_OFF_DELAY_SHIFT;
2529
2530                 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2531                         PANEL_POWER_DOWN_DELAY_SHIFT;
2532
2533                 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2534                                PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2535
2536                 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2537                               cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2538
2539                 vbt = dev_priv->edp.pps;
2540
2541                 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2542                               vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2543
2544 #define get_delay(field)        ((max(cur.field, vbt.field) + 9) / 10)
2545
2546                 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2547                 intel_dp->backlight_on_delay = get_delay(t8);
2548                 intel_dp->backlight_off_delay = get_delay(t9);
2549                 intel_dp->panel_power_down_delay = get_delay(t10);
2550                 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2551
2552                 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2553                               intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2554                               intel_dp->panel_power_cycle_delay);
2555
2556                 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2557                               intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2558
2559                 ironlake_edp_panel_vdd_on(intel_dp);
2560                 ret = intel_dp_get_dpcd(intel_dp);
2561                 ironlake_edp_panel_vdd_off(intel_dp, false);
2562
2563                 if (ret) {
2564                         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2565                                 dev_priv->no_aux_handshake =
2566                                         intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
2567                                         DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2568                 } else {
2569                         /* if this fails, presume the device is a ghost */
2570                         DRM_INFO("failed to retrieve link info, disabling eDP\n");
2571                         intel_dp_encoder_destroy(&intel_dp->base.base);
2572                         intel_dp_destroy(&intel_connector->base);
2573                         return;
2574                 }
2575         }
2576
2577         intel_dp_i2c_init(intel_dp, intel_connector, name);
2578
2579         intel_encoder->hot_plug = intel_dp_hot_plug;
2580
2581         if (is_edp(intel_dp)) {
2582                 dev_priv->int_edp_connector = connector;
2583                 intel_panel_setup_backlight(dev);
2584         }
2585
2586         intel_dp_add_properties(intel_dp, connector);
2587
2588         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2589          * 0xd.  Failure to do so will result in spurious interrupts being
2590          * generated on the port when a cable is not attached.
2591          */
2592         if (IS_G4X(dev) && !IS_GM45(dev)) {
2593                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2594                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2595         }
2596 }