2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_edid.h>
35 #include "intel_drv.h"
36 #include <drm/i915_drm.h>
39 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
42 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
43 * @intel_dp: DP struct
45 * If a CPU or PCH DP output is attached to an eDP panel, this function
46 * will return true, and false otherwise.
48 static bool is_edp(struct intel_dp *intel_dp)
50 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
52 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
55 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
57 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
59 return intel_dig_port->base.base.dev;
62 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
64 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
67 static void intel_dp_link_down(struct intel_dp *intel_dp);
70 intel_dp_max_link_bw(struct intel_dp *intel_dp)
72 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
74 switch (max_link_bw) {
78 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
79 max_link_bw = DP_LINK_BW_2_7;
82 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
84 max_link_bw = DP_LINK_BW_1_62;
91 * The units on the numbers in the next two are... bizarre. Examples will
92 * make it clearer; this one parallels an example in the eDP spec.
94 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
96 * 270000 * 1 * 8 / 10 == 216000
98 * The actual data capacity of that configuration is 2.16Gbit/s, so the
99 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
100 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
101 * 119000. At 18bpp that's 2142000 kilobits per second.
103 * Thus the strange-looking division by 10 in intel_dp_link_required, to
104 * get the result in decakilobits instead of kilobits.
108 intel_dp_link_required(int pixel_clock, int bpp)
110 return (pixel_clock * bpp + 9) / 10;
114 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
116 return (max_link_clock * max_lanes * 8) / 10;
120 intel_dp_mode_valid(struct drm_connector *connector,
121 struct drm_display_mode *mode)
123 struct intel_dp *intel_dp = intel_attached_dp(connector);
124 struct intel_connector *intel_connector = to_intel_connector(connector);
125 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
126 int target_clock = mode->clock;
127 int max_rate, mode_rate, max_lanes, max_link_clock;
129 if (is_edp(intel_dp) && fixed_mode) {
130 if (mode->hdisplay > fixed_mode->hdisplay)
133 if (mode->vdisplay > fixed_mode->vdisplay)
136 target_clock = fixed_mode->clock;
139 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
140 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
142 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
143 mode_rate = intel_dp_link_required(target_clock, 18);
145 if (mode_rate > max_rate)
146 return MODE_CLOCK_HIGH;
148 if (mode->clock < 10000)
149 return MODE_CLOCK_LOW;
151 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
152 return MODE_H_ILLEGAL;
158 pack_aux(uint8_t *src, int src_bytes)
165 for (i = 0; i < src_bytes; i++)
166 v |= ((uint32_t) src[i]) << ((3-i) * 8);
171 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
176 for (i = 0; i < dst_bytes; i++)
177 dst[i] = src >> ((3-i) * 8);
180 /* hrawclock is 1/4 the FSB frequency */
182 intel_hrawclk(struct drm_device *dev)
184 struct drm_i915_private *dev_priv = dev->dev_private;
187 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
188 if (IS_VALLEYVIEW(dev))
191 clkcfg = I915_READ(CLKCFG);
192 switch (clkcfg & CLKCFG_FSB_MASK) {
201 case CLKCFG_FSB_1067:
203 case CLKCFG_FSB_1333:
205 /* these two are just a guess; one of them might be right */
206 case CLKCFG_FSB_1600:
207 case CLKCFG_FSB_1600_ALT:
214 static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
216 struct drm_device *dev = intel_dp_to_dev(intel_dp);
217 struct drm_i915_private *dev_priv = dev->dev_private;
220 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
221 return (I915_READ(pp_stat_reg) & PP_ON) != 0;
224 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
226 struct drm_device *dev = intel_dp_to_dev(intel_dp);
227 struct drm_i915_private *dev_priv = dev->dev_private;
230 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
231 return (I915_READ(pp_ctrl_reg) & EDP_FORCE_VDD) != 0;
235 intel_dp_check_edp(struct intel_dp *intel_dp)
237 struct drm_device *dev = intel_dp_to_dev(intel_dp);
238 struct drm_i915_private *dev_priv = dev->dev_private;
239 u32 pp_stat_reg, pp_ctrl_reg;
241 if (!is_edp(intel_dp))
244 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
245 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
247 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
248 WARN(1, "eDP powered off while attempting aux channel communication.\n");
249 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
250 I915_READ(pp_stat_reg),
251 I915_READ(pp_ctrl_reg));
256 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
258 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
259 struct drm_device *dev = intel_dig_port->base.base.dev;
260 struct drm_i915_private *dev_priv = dev->dev_private;
261 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
265 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
267 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
268 msecs_to_jiffies_timeout(10));
270 done = wait_for_atomic(C, 10) == 0;
272 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
279 static uint32_t get_aux_clock_divider(struct intel_dp *intel_dp,
282 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
283 struct drm_device *dev = intel_dig_port->base.base.dev;
284 struct drm_i915_private *dev_priv = dev->dev_private;
286 /* The clock divider is based off the hrawclk,
287 * and would like to run at 2MHz. So, take the
288 * hrawclk value and divide by 2 and use that
290 * Note that PCH attached eDP panels should use a 125MHz input
293 if (IS_VALLEYVIEW(dev)) {
294 return index ? 0 : 100;
295 } else if (intel_dig_port->port == PORT_A) {
299 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
300 else if (IS_GEN6(dev) || IS_GEN7(dev))
301 return 200; /* SNB & IVB eDP input clock at 400Mhz */
303 return 225; /* eDP input clock at 450Mhz */
304 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
305 /* Workaround for non-ULT HSW */
311 } else if (HAS_PCH_SPLIT(dev)) {
312 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
314 return index ? 0 :intel_hrawclk(dev) / 2;
319 intel_dp_aux_ch(struct intel_dp *intel_dp,
320 uint8_t *send, int send_bytes,
321 uint8_t *recv, int recv_size)
323 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
324 struct drm_device *dev = intel_dig_port->base.base.dev;
325 struct drm_i915_private *dev_priv = dev->dev_private;
326 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
327 uint32_t ch_data = ch_ctl + 4;
328 uint32_t aux_clock_divider;
329 int i, ret, recv_bytes;
331 int try, precharge, clock = 0;
332 bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);
334 /* dp aux is extremely sensitive to irq latency, hence request the
335 * lowest possible wakeup latency and so prevent the cpu from going into
338 pm_qos_update_request(&dev_priv->pm_qos, 0);
340 intel_dp_check_edp(intel_dp);
347 /* Try to wait for any previous AUX channel activity */
348 for (try = 0; try < 3; try++) {
349 status = I915_READ_NOTRACE(ch_ctl);
350 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
356 WARN(1, "dp_aux_ch not started status 0x%08x\n",
362 while ((aux_clock_divider = get_aux_clock_divider(intel_dp, clock++))) {
363 /* Must try at least 3 times according to DP spec */
364 for (try = 0; try < 5; try++) {
365 /* Load the send data into the aux channel data registers */
366 for (i = 0; i < send_bytes; i += 4)
367 I915_WRITE(ch_data + i,
368 pack_aux(send + i, send_bytes - i));
370 /* Send the command and wait for it to complete */
372 DP_AUX_CH_CTL_SEND_BUSY |
373 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
374 DP_AUX_CH_CTL_TIME_OUT_400us |
375 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
376 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
377 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
379 DP_AUX_CH_CTL_TIME_OUT_ERROR |
380 DP_AUX_CH_CTL_RECEIVE_ERROR);
382 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
384 /* Clear done status and any errors */
388 DP_AUX_CH_CTL_TIME_OUT_ERROR |
389 DP_AUX_CH_CTL_RECEIVE_ERROR);
391 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
392 DP_AUX_CH_CTL_RECEIVE_ERROR))
394 if (status & DP_AUX_CH_CTL_DONE)
397 if (status & DP_AUX_CH_CTL_DONE)
401 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
402 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
407 /* Check for timeout or receive error.
408 * Timeouts occur when the sink is not connected
410 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
411 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
416 /* Timeouts occur when the device isn't connected, so they're
417 * "normal" -- don't fill the kernel log with these */
418 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
419 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
424 /* Unload any bytes sent back from the other side */
425 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
426 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
427 if (recv_bytes > recv_size)
428 recv_bytes = recv_size;
430 for (i = 0; i < recv_bytes; i += 4)
431 unpack_aux(I915_READ(ch_data + i),
432 recv + i, recv_bytes - i);
436 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
441 /* Write data to the aux channel in native mode */
443 intel_dp_aux_native_write(struct intel_dp *intel_dp,
444 uint16_t address, uint8_t *send, int send_bytes)
451 intel_dp_check_edp(intel_dp);
454 msg[0] = AUX_NATIVE_WRITE << 4;
455 msg[1] = address >> 8;
456 msg[2] = address & 0xff;
457 msg[3] = send_bytes - 1;
458 memcpy(&msg[4], send, send_bytes);
459 msg_bytes = send_bytes + 4;
461 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
464 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
466 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
474 /* Write a single byte to the aux channel in native mode */
476 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
477 uint16_t address, uint8_t byte)
479 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
482 /* read bytes from a native aux channel */
484 intel_dp_aux_native_read(struct intel_dp *intel_dp,
485 uint16_t address, uint8_t *recv, int recv_bytes)
494 intel_dp_check_edp(intel_dp);
495 msg[0] = AUX_NATIVE_READ << 4;
496 msg[1] = address >> 8;
497 msg[2] = address & 0xff;
498 msg[3] = recv_bytes - 1;
501 reply_bytes = recv_bytes + 1;
504 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
511 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
512 memcpy(recv, reply + 1, ret - 1);
515 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
523 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
524 uint8_t write_byte, uint8_t *read_byte)
526 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
527 struct intel_dp *intel_dp = container_of(adapter,
530 uint16_t address = algo_data->address;
538 intel_dp_check_edp(intel_dp);
539 /* Set up the command byte */
540 if (mode & MODE_I2C_READ)
541 msg[0] = AUX_I2C_READ << 4;
543 msg[0] = AUX_I2C_WRITE << 4;
545 if (!(mode & MODE_I2C_STOP))
546 msg[0] |= AUX_I2C_MOT << 4;
548 msg[1] = address >> 8;
569 for (retry = 0; retry < 5; retry++) {
570 ret = intel_dp_aux_ch(intel_dp,
574 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
578 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
579 case AUX_NATIVE_REPLY_ACK:
580 /* I2C-over-AUX Reply field is only valid
581 * when paired with AUX ACK.
584 case AUX_NATIVE_REPLY_NACK:
585 DRM_DEBUG_KMS("aux_ch native nack\n");
587 case AUX_NATIVE_REPLY_DEFER:
591 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
596 switch (reply[0] & AUX_I2C_REPLY_MASK) {
597 case AUX_I2C_REPLY_ACK:
598 if (mode == MODE_I2C_READ) {
599 *read_byte = reply[1];
601 return reply_bytes - 1;
602 case AUX_I2C_REPLY_NACK:
603 DRM_DEBUG_KMS("aux_i2c nack\n");
605 case AUX_I2C_REPLY_DEFER:
606 DRM_DEBUG_KMS("aux_i2c defer\n");
610 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
615 DRM_ERROR("too many retries, giving up\n");
620 intel_dp_i2c_init(struct intel_dp *intel_dp,
621 struct intel_connector *intel_connector, const char *name)
625 DRM_DEBUG_KMS("i2c_init %s\n", name);
626 intel_dp->algo.running = false;
627 intel_dp->algo.address = 0;
628 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
630 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
631 intel_dp->adapter.owner = THIS_MODULE;
632 intel_dp->adapter.class = I2C_CLASS_DDC;
633 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
634 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
635 intel_dp->adapter.algo_data = &intel_dp->algo;
636 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
638 ironlake_edp_panel_vdd_on(intel_dp);
639 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
640 ironlake_edp_panel_vdd_off(intel_dp, false);
645 intel_dp_set_clock(struct intel_encoder *encoder,
646 struct intel_crtc_config *pipe_config, int link_bw)
648 struct drm_device *dev = encoder->base.dev;
651 if (link_bw == DP_LINK_BW_1_62) {
652 pipe_config->dpll.p1 = 2;
653 pipe_config->dpll.p2 = 10;
654 pipe_config->dpll.n = 2;
655 pipe_config->dpll.m1 = 23;
656 pipe_config->dpll.m2 = 8;
658 pipe_config->dpll.p1 = 1;
659 pipe_config->dpll.p2 = 10;
660 pipe_config->dpll.n = 1;
661 pipe_config->dpll.m1 = 14;
662 pipe_config->dpll.m2 = 2;
664 pipe_config->clock_set = true;
665 } else if (IS_HASWELL(dev)) {
666 /* Haswell has special-purpose DP DDI clocks. */
667 } else if (HAS_PCH_SPLIT(dev)) {
668 if (link_bw == DP_LINK_BW_1_62) {
669 pipe_config->dpll.n = 1;
670 pipe_config->dpll.p1 = 2;
671 pipe_config->dpll.p2 = 10;
672 pipe_config->dpll.m1 = 12;
673 pipe_config->dpll.m2 = 9;
675 pipe_config->dpll.n = 2;
676 pipe_config->dpll.p1 = 1;
677 pipe_config->dpll.p2 = 10;
678 pipe_config->dpll.m1 = 14;
679 pipe_config->dpll.m2 = 8;
681 pipe_config->clock_set = true;
682 } else if (IS_VALLEYVIEW(dev)) {
683 /* FIXME: Need to figure out optimized DP clocks for vlv. */
688 intel_dp_compute_config(struct intel_encoder *encoder,
689 struct intel_crtc_config *pipe_config)
691 struct drm_device *dev = encoder->base.dev;
692 struct drm_i915_private *dev_priv = dev->dev_private;
693 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
694 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
695 enum port port = dp_to_dig_port(intel_dp)->port;
696 struct intel_crtc *intel_crtc = encoder->new_crtc;
697 struct intel_connector *intel_connector = intel_dp->attached_connector;
698 int lane_count, clock;
699 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
700 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
702 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
703 int link_avail, link_clock;
705 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
706 pipe_config->has_pch_encoder = true;
708 pipe_config->has_dp_encoder = true;
710 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
711 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
713 if (!HAS_PCH_SPLIT(dev))
714 intel_gmch_panel_fitting(intel_crtc, pipe_config,
715 intel_connector->panel.fitting_mode);
717 intel_pch_panel_fitting(intel_crtc, pipe_config,
718 intel_connector->panel.fitting_mode);
721 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
724 DRM_DEBUG_KMS("DP link computation with max lane count %i "
725 "max bw %02x pixel clock %iKHz\n",
726 max_lane_count, bws[max_clock], adjusted_mode->clock);
728 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
730 bpp = pipe_config->pipe_bpp;
731 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp) {
732 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
733 dev_priv->vbt.edp_bpp);
734 bpp = min_t(int, bpp, dev_priv->vbt.edp_bpp);
737 for (; bpp >= 6*3; bpp -= 2*3) {
738 mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
740 for (clock = 0; clock <= max_clock; clock++) {
741 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
742 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
743 link_avail = intel_dp_max_data_rate(link_clock,
746 if (mode_rate <= link_avail) {
756 if (intel_dp->color_range_auto) {
759 * CEA-861-E - 5.1 Default Encoding Parameters
760 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
762 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
763 intel_dp->color_range = DP_COLOR_RANGE_16_235;
765 intel_dp->color_range = 0;
768 if (intel_dp->color_range)
769 pipe_config->limited_color_range = true;
771 intel_dp->link_bw = bws[clock];
772 intel_dp->lane_count = lane_count;
773 pipe_config->pipe_bpp = bpp;
774 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
776 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
777 intel_dp->link_bw, intel_dp->lane_count,
778 pipe_config->port_clock, bpp);
779 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
780 mode_rate, link_avail);
782 intel_link_compute_m_n(bpp, lane_count,
783 adjusted_mode->clock, pipe_config->port_clock,
784 &pipe_config->dp_m_n);
786 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
791 void intel_dp_init_link_config(struct intel_dp *intel_dp)
793 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
794 intel_dp->link_configuration[0] = intel_dp->link_bw;
795 intel_dp->link_configuration[1] = intel_dp->lane_count;
796 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
798 * Check for DPCD version > 1.1 and enhanced framing support
800 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
801 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
802 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
806 static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
808 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
809 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
810 struct drm_device *dev = crtc->base.dev;
811 struct drm_i915_private *dev_priv = dev->dev_private;
814 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
815 dpa_ctl = I915_READ(DP_A);
816 dpa_ctl &= ~DP_PLL_FREQ_MASK;
818 if (crtc->config.port_clock == 162000) {
819 /* For a long time we've carried around a ILK-DevA w/a for the
820 * 160MHz clock. If we're really unlucky, it's still required.
822 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
823 dpa_ctl |= DP_PLL_FREQ_160MHZ;
824 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
826 dpa_ctl |= DP_PLL_FREQ_270MHZ;
827 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
830 I915_WRITE(DP_A, dpa_ctl);
836 static void intel_dp_mode_set(struct intel_encoder *encoder)
838 struct drm_device *dev = encoder->base.dev;
839 struct drm_i915_private *dev_priv = dev->dev_private;
840 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
841 enum port port = dp_to_dig_port(intel_dp)->port;
842 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
843 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
846 * There are four kinds of DP registers:
853 * IBX PCH and CPU are the same for almost everything,
854 * except that the CPU DP PLL is configured in this
857 * CPT PCH is quite different, having many bits moved
858 * to the TRANS_DP_CTL register instead. That
859 * configuration happens (oddly) in ironlake_pch_enable
862 /* Preserve the BIOS-computed detected bit. This is
863 * supposed to be read-only.
865 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
867 /* Handle DP bits in common between all three register formats */
868 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
869 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
871 if (intel_dp->has_audio) {
872 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
873 pipe_name(crtc->pipe));
874 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
875 intel_write_eld(&encoder->base, adjusted_mode);
878 intel_dp_init_link_config(intel_dp);
880 /* Split out the IBX/CPU vs CPT settings */
882 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
883 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
884 intel_dp->DP |= DP_SYNC_HS_HIGH;
885 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
886 intel_dp->DP |= DP_SYNC_VS_HIGH;
887 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
889 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
890 intel_dp->DP |= DP_ENHANCED_FRAMING;
892 intel_dp->DP |= crtc->pipe << 29;
893 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
894 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
895 intel_dp->DP |= intel_dp->color_range;
897 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
898 intel_dp->DP |= DP_SYNC_HS_HIGH;
899 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
900 intel_dp->DP |= DP_SYNC_VS_HIGH;
901 intel_dp->DP |= DP_LINK_TRAIN_OFF;
903 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
904 intel_dp->DP |= DP_ENHANCED_FRAMING;
907 intel_dp->DP |= DP_PIPEB_SELECT;
909 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
912 if (port == PORT_A && !IS_VALLEYVIEW(dev))
913 ironlake_set_pll_cpu_edp(intel_dp);
916 #define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
917 #define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
919 #define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
920 #define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
922 #define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
923 #define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
925 static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
929 struct drm_device *dev = intel_dp_to_dev(intel_dp);
930 struct drm_i915_private *dev_priv = dev->dev_private;
931 u32 pp_stat_reg, pp_ctrl_reg;
933 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
934 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
936 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
938 I915_READ(pp_stat_reg),
939 I915_READ(pp_ctrl_reg));
941 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
942 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
943 I915_READ(pp_stat_reg),
944 I915_READ(pp_ctrl_reg));
948 static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
950 DRM_DEBUG_KMS("Wait for panel power on\n");
951 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
954 static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
956 DRM_DEBUG_KMS("Wait for panel power off time\n");
957 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
960 static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
962 DRM_DEBUG_KMS("Wait for panel power cycle\n");
963 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
967 /* Read the current pp_control value, unlocking the register if it
971 static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
973 struct drm_device *dev = intel_dp_to_dev(intel_dp);
974 struct drm_i915_private *dev_priv = dev->dev_private;
978 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
979 control = I915_READ(pp_ctrl_reg);
981 control &= ~PANEL_UNLOCK_MASK;
982 control |= PANEL_UNLOCK_REGS;
986 void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
988 struct drm_device *dev = intel_dp_to_dev(intel_dp);
989 struct drm_i915_private *dev_priv = dev->dev_private;
991 u32 pp_stat_reg, pp_ctrl_reg;
993 if (!is_edp(intel_dp))
995 DRM_DEBUG_KMS("Turn eDP VDD on\n");
997 WARN(intel_dp->want_panel_vdd,
998 "eDP VDD already requested on\n");
1000 intel_dp->want_panel_vdd = true;
1002 if (ironlake_edp_have_panel_vdd(intel_dp)) {
1003 DRM_DEBUG_KMS("eDP VDD already on\n");
1007 if (!ironlake_edp_have_panel_power(intel_dp))
1008 ironlake_wait_panel_power_cycle(intel_dp);
1010 pp = ironlake_get_pp_control(intel_dp);
1011 pp |= EDP_FORCE_VDD;
1013 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
1014 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1016 I915_WRITE(pp_ctrl_reg, pp);
1017 POSTING_READ(pp_ctrl_reg);
1018 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1019 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1021 * If the panel wasn't on, delay before accessing aux channel
1023 if (!ironlake_edp_have_panel_power(intel_dp)) {
1024 DRM_DEBUG_KMS("eDP was not running\n");
1025 msleep(intel_dp->panel_power_up_delay);
1029 static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
1031 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1032 struct drm_i915_private *dev_priv = dev->dev_private;
1034 u32 pp_stat_reg, pp_ctrl_reg;
1036 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1038 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
1039 pp = ironlake_get_pp_control(intel_dp);
1040 pp &= ~EDP_FORCE_VDD;
1042 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
1043 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1045 I915_WRITE(pp_ctrl_reg, pp);
1046 POSTING_READ(pp_ctrl_reg);
1048 /* Make sure sequencer is idle before allowing subsequent activity */
1049 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1050 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1051 msleep(intel_dp->panel_power_down_delay);
1055 static void ironlake_panel_vdd_work(struct work_struct *__work)
1057 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1058 struct intel_dp, panel_vdd_work);
1059 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1061 mutex_lock(&dev->mode_config.mutex);
1062 ironlake_panel_vdd_off_sync(intel_dp);
1063 mutex_unlock(&dev->mode_config.mutex);
1066 void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1068 if (!is_edp(intel_dp))
1071 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1072 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1074 intel_dp->want_panel_vdd = false;
1077 ironlake_panel_vdd_off_sync(intel_dp);
1080 * Queue the timer to fire a long
1081 * time from now (relative to the power down delay)
1082 * to keep the panel power up across a sequence of operations
1084 schedule_delayed_work(&intel_dp->panel_vdd_work,
1085 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1089 void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1091 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1092 struct drm_i915_private *dev_priv = dev->dev_private;
1096 if (!is_edp(intel_dp))
1099 DRM_DEBUG_KMS("Turn eDP power on\n");
1101 if (ironlake_edp_have_panel_power(intel_dp)) {
1102 DRM_DEBUG_KMS("eDP power already on\n");
1106 ironlake_wait_panel_power_cycle(intel_dp);
1108 pp = ironlake_get_pp_control(intel_dp);
1110 /* ILK workaround: disable reset around power sequence */
1111 pp &= ~PANEL_POWER_RESET;
1112 I915_WRITE(PCH_PP_CONTROL, pp);
1113 POSTING_READ(PCH_PP_CONTROL);
1116 pp |= POWER_TARGET_ON;
1118 pp |= PANEL_POWER_RESET;
1120 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1122 I915_WRITE(pp_ctrl_reg, pp);
1123 POSTING_READ(pp_ctrl_reg);
1125 ironlake_wait_panel_on(intel_dp);
1128 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1129 I915_WRITE(PCH_PP_CONTROL, pp);
1130 POSTING_READ(PCH_PP_CONTROL);
1134 void ironlake_edp_panel_off(struct intel_dp *intel_dp)
1136 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1137 struct drm_i915_private *dev_priv = dev->dev_private;
1141 if (!is_edp(intel_dp))
1144 DRM_DEBUG_KMS("Turn eDP power off\n");
1146 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1148 pp = ironlake_get_pp_control(intel_dp);
1149 /* We need to switch off panel power _and_ force vdd, for otherwise some
1150 * panels get very unhappy and cease to work. */
1151 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1153 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1155 I915_WRITE(pp_ctrl_reg, pp);
1156 POSTING_READ(pp_ctrl_reg);
1158 intel_dp->want_panel_vdd = false;
1160 ironlake_wait_panel_off(intel_dp);
1163 void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1165 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1166 struct drm_device *dev = intel_dig_port->base.base.dev;
1167 struct drm_i915_private *dev_priv = dev->dev_private;
1168 int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe;
1172 if (!is_edp(intel_dp))
1175 DRM_DEBUG_KMS("\n");
1177 * If we enable the backlight right away following a panel power
1178 * on, we may see slight flicker as the panel syncs with the eDP
1179 * link. So delay a bit to make sure the image is solid before
1180 * allowing it to appear.
1182 msleep(intel_dp->backlight_on_delay);
1183 pp = ironlake_get_pp_control(intel_dp);
1184 pp |= EDP_BLC_ENABLE;
1186 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1188 I915_WRITE(pp_ctrl_reg, pp);
1189 POSTING_READ(pp_ctrl_reg);
1191 intel_panel_enable_backlight(dev, pipe);
1194 void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1196 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1197 struct drm_i915_private *dev_priv = dev->dev_private;
1201 if (!is_edp(intel_dp))
1204 intel_panel_disable_backlight(dev);
1206 DRM_DEBUG_KMS("\n");
1207 pp = ironlake_get_pp_control(intel_dp);
1208 pp &= ~EDP_BLC_ENABLE;
1210 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1212 I915_WRITE(pp_ctrl_reg, pp);
1213 POSTING_READ(pp_ctrl_reg);
1214 msleep(intel_dp->backlight_off_delay);
1217 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1219 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1220 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1221 struct drm_device *dev = crtc->dev;
1222 struct drm_i915_private *dev_priv = dev->dev_private;
1225 assert_pipe_disabled(dev_priv,
1226 to_intel_crtc(crtc)->pipe);
1228 DRM_DEBUG_KMS("\n");
1229 dpa_ctl = I915_READ(DP_A);
1230 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1231 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1233 /* We don't adjust intel_dp->DP while tearing down the link, to
1234 * facilitate link retraining (e.g. after hotplug). Hence clear all
1235 * enable bits here to ensure that we don't enable too much. */
1236 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1237 intel_dp->DP |= DP_PLL_ENABLE;
1238 I915_WRITE(DP_A, intel_dp->DP);
1243 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1245 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1246 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1247 struct drm_device *dev = crtc->dev;
1248 struct drm_i915_private *dev_priv = dev->dev_private;
1251 assert_pipe_disabled(dev_priv,
1252 to_intel_crtc(crtc)->pipe);
1254 dpa_ctl = I915_READ(DP_A);
1255 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1256 "dp pll off, should be on\n");
1257 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1259 /* We can't rely on the value tracked for the DP register in
1260 * intel_dp->DP because link_down must not change that (otherwise link
1261 * re-training will fail. */
1262 dpa_ctl &= ~DP_PLL_ENABLE;
1263 I915_WRITE(DP_A, dpa_ctl);
1268 /* If the sink supports it, try to set the power state appropriately */
1269 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1273 /* Should have a valid DPCD by this point */
1274 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1277 if (mode != DRM_MODE_DPMS_ON) {
1278 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1281 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1284 * When turning on, we need to retry for 1ms to give the sink
1287 for (i = 0; i < 3; i++) {
1288 ret = intel_dp_aux_native_write_1(intel_dp,
1298 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1301 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1302 enum port port = dp_to_dig_port(intel_dp)->port;
1303 struct drm_device *dev = encoder->base.dev;
1304 struct drm_i915_private *dev_priv = dev->dev_private;
1305 u32 tmp = I915_READ(intel_dp->output_reg);
1307 if (!(tmp & DP_PORT_EN))
1310 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1311 *pipe = PORT_TO_PIPE_CPT(tmp);
1312 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1313 *pipe = PORT_TO_PIPE(tmp);
1319 switch (intel_dp->output_reg) {
1321 trans_sel = TRANS_DP_PORT_SEL_B;
1324 trans_sel = TRANS_DP_PORT_SEL_C;
1327 trans_sel = TRANS_DP_PORT_SEL_D;
1334 trans_dp = I915_READ(TRANS_DP_CTL(i));
1335 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1341 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1342 intel_dp->output_reg);
1348 static void intel_dp_get_config(struct intel_encoder *encoder,
1349 struct intel_crtc_config *pipe_config)
1351 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1353 struct drm_device *dev = encoder->base.dev;
1354 struct drm_i915_private *dev_priv = dev->dev_private;
1355 enum port port = dp_to_dig_port(intel_dp)->port;
1356 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1358 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
1359 tmp = I915_READ(intel_dp->output_reg);
1360 if (tmp & DP_SYNC_HS_HIGH)
1361 flags |= DRM_MODE_FLAG_PHSYNC;
1363 flags |= DRM_MODE_FLAG_NHSYNC;
1365 if (tmp & DP_SYNC_VS_HIGH)
1366 flags |= DRM_MODE_FLAG_PVSYNC;
1368 flags |= DRM_MODE_FLAG_NVSYNC;
1370 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1371 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1372 flags |= DRM_MODE_FLAG_PHSYNC;
1374 flags |= DRM_MODE_FLAG_NHSYNC;
1376 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1377 flags |= DRM_MODE_FLAG_PVSYNC;
1379 flags |= DRM_MODE_FLAG_NVSYNC;
1382 pipe_config->adjusted_mode.flags |= flags;
1384 if (dp_to_dig_port(intel_dp)->port == PORT_A) {
1385 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1386 pipe_config->port_clock = 162000;
1388 pipe_config->port_clock = 270000;
1392 static bool is_edp_psr(struct intel_dp *intel_dp)
1394 return is_edp(intel_dp) &&
1395 intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
1398 static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1400 struct drm_i915_private *dev_priv = dev->dev_private;
1402 if (!IS_HASWELL(dev))
1405 return I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
1408 static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1409 struct edp_vsc_psr *vsc_psr)
1411 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1412 struct drm_device *dev = dig_port->base.base.dev;
1413 struct drm_i915_private *dev_priv = dev->dev_private;
1414 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1415 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1416 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1417 uint32_t *data = (uint32_t *) vsc_psr;
1420 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1421 the video DIP being updated before program video DIP data buffer
1422 registers for DIP being updated. */
1423 I915_WRITE(ctl_reg, 0);
1424 POSTING_READ(ctl_reg);
1426 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1427 if (i < sizeof(struct edp_vsc_psr))
1428 I915_WRITE(data_reg + i, *data++);
1430 I915_WRITE(data_reg + i, 0);
1433 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1434 POSTING_READ(ctl_reg);
1437 static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1439 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1440 struct drm_i915_private *dev_priv = dev->dev_private;
1441 struct edp_vsc_psr psr_vsc;
1443 if (intel_dp->psr_setup_done)
1446 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1447 memset(&psr_vsc, 0, sizeof(psr_vsc));
1448 psr_vsc.sdp_header.HB0 = 0;
1449 psr_vsc.sdp_header.HB1 = 0x7;
1450 psr_vsc.sdp_header.HB2 = 0x2;
1451 psr_vsc.sdp_header.HB3 = 0x8;
1452 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1454 /* Avoid continuous PSR exit by masking memup and hpd */
1455 I915_WRITE(EDP_PSR_DEBUG_CTL, EDP_PSR_DEBUG_MASK_MEMUP |
1456 EDP_PSR_DEBUG_MASK_HPD);
1458 intel_dp->psr_setup_done = true;
1461 static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1463 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1464 struct drm_i915_private *dev_priv = dev->dev_private;
1465 uint32_t aux_clock_divider = get_aux_clock_divider(intel_dp, 0);
1466 int precharge = 0x3;
1467 int msg_size = 5; /* Header(4) + Message(1) */
1469 /* Enable PSR in sink */
1470 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT)
1471 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1473 ~DP_PSR_MAIN_LINK_ACTIVE);
1475 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1477 DP_PSR_MAIN_LINK_ACTIVE);
1479 /* Setup AUX registers */
1480 I915_WRITE(EDP_PSR_AUX_DATA1, EDP_PSR_DPCD_COMMAND);
1481 I915_WRITE(EDP_PSR_AUX_DATA2, EDP_PSR_DPCD_NORMAL_OPERATION);
1482 I915_WRITE(EDP_PSR_AUX_CTL,
1483 DP_AUX_CH_CTL_TIME_OUT_400us |
1484 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1485 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1486 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1489 static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1491 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1492 struct drm_i915_private *dev_priv = dev->dev_private;
1493 uint32_t max_sleep_time = 0x1f;
1494 uint32_t idle_frames = 1;
1497 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
1498 val |= EDP_PSR_LINK_STANDBY;
1499 val |= EDP_PSR_TP2_TP3_TIME_0us;
1500 val |= EDP_PSR_TP1_TIME_0us;
1501 val |= EDP_PSR_SKIP_AUX_EXIT;
1503 val |= EDP_PSR_LINK_DISABLE;
1505 I915_WRITE(EDP_PSR_CTL, val |
1506 EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES |
1507 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1508 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1512 static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1514 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1515 struct drm_device *dev = dig_port->base.base.dev;
1516 struct drm_i915_private *dev_priv = dev->dev_private;
1517 struct drm_crtc *crtc = dig_port->base.base.crtc;
1518 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1519 struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->fb)->obj;
1520 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
1522 if (!IS_HASWELL(dev)) {
1523 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1524 dev_priv->no_psr_reason = PSR_NO_SOURCE;
1528 if ((intel_encoder->type != INTEL_OUTPUT_EDP) ||
1529 (dig_port->port != PORT_A)) {
1530 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
1531 dev_priv->no_psr_reason = PSR_HSW_NOT_DDIA;
1535 if (!is_edp_psr(intel_dp)) {
1536 DRM_DEBUG_KMS("PSR not supported by this panel\n");
1537 dev_priv->no_psr_reason = PSR_NO_SINK;
1541 if (!i915_enable_psr) {
1542 DRM_DEBUG_KMS("PSR disable by flag\n");
1543 dev_priv->no_psr_reason = PSR_MODULE_PARAM;
1547 crtc = dig_port->base.base.crtc;
1549 DRM_DEBUG_KMS("crtc not active for PSR\n");
1550 dev_priv->no_psr_reason = PSR_CRTC_NOT_ACTIVE;
1554 intel_crtc = to_intel_crtc(crtc);
1555 if (!intel_crtc->active || !crtc->fb || !crtc->mode.clock) {
1556 DRM_DEBUG_KMS("crtc not active for PSR\n");
1557 dev_priv->no_psr_reason = PSR_CRTC_NOT_ACTIVE;
1561 obj = to_intel_framebuffer(crtc->fb)->obj;
1562 if (obj->tiling_mode != I915_TILING_X ||
1563 obj->fence_reg == I915_FENCE_REG_NONE) {
1564 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
1565 dev_priv->no_psr_reason = PSR_NOT_TILED;
1569 if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
1570 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
1571 dev_priv->no_psr_reason = PSR_SPRITE_ENABLED;
1575 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1577 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
1578 dev_priv->no_psr_reason = PSR_S3D_ENABLED;
1582 if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) {
1583 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
1584 dev_priv->no_psr_reason = PSR_INTERLACED_ENABLED;
1591 static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
1593 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1595 if (!intel_edp_psr_match_conditions(intel_dp) ||
1596 intel_edp_is_psr_enabled(dev))
1599 /* Setup PSR once */
1600 intel_edp_psr_setup(intel_dp);
1602 /* Enable PSR on the panel */
1603 intel_edp_psr_enable_sink(intel_dp);
1605 /* Enable PSR on the host */
1606 intel_edp_psr_enable_source(intel_dp);
1609 void intel_edp_psr_enable(struct intel_dp *intel_dp)
1611 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1613 if (intel_edp_psr_match_conditions(intel_dp) &&
1614 !intel_edp_is_psr_enabled(dev))
1615 intel_edp_psr_do_enable(intel_dp);
1618 void intel_edp_psr_disable(struct intel_dp *intel_dp)
1620 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1621 struct drm_i915_private *dev_priv = dev->dev_private;
1623 if (!intel_edp_is_psr_enabled(dev))
1626 I915_WRITE(EDP_PSR_CTL, I915_READ(EDP_PSR_CTL) & ~EDP_PSR_ENABLE);
1628 /* Wait till PSR is idle */
1629 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL) &
1630 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1631 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1634 void intel_edp_psr_update(struct drm_device *dev)
1636 struct intel_encoder *encoder;
1637 struct intel_dp *intel_dp = NULL;
1639 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
1640 if (encoder->type == INTEL_OUTPUT_EDP) {
1641 intel_dp = enc_to_intel_dp(&encoder->base);
1643 if (!is_edp_psr(intel_dp))
1646 if (!intel_edp_psr_match_conditions(intel_dp))
1647 intel_edp_psr_disable(intel_dp);
1649 if (!intel_edp_is_psr_enabled(dev))
1650 intel_edp_psr_do_enable(intel_dp);
1654 static void intel_disable_dp(struct intel_encoder *encoder)
1656 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1657 enum port port = dp_to_dig_port(intel_dp)->port;
1658 struct drm_device *dev = encoder->base.dev;
1660 /* Make sure the panel is off before trying to change the mode. But also
1661 * ensure that we have vdd while we switch off the panel. */
1662 ironlake_edp_panel_vdd_on(intel_dp);
1663 ironlake_edp_backlight_off(intel_dp);
1664 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1665 ironlake_edp_panel_off(intel_dp);
1667 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1668 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
1669 intel_dp_link_down(intel_dp);
1672 static void intel_post_disable_dp(struct intel_encoder *encoder)
1674 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1675 enum port port = dp_to_dig_port(intel_dp)->port;
1676 struct drm_device *dev = encoder->base.dev;
1678 if (port == PORT_A || IS_VALLEYVIEW(dev)) {
1679 intel_dp_link_down(intel_dp);
1680 if (!IS_VALLEYVIEW(dev))
1681 ironlake_edp_pll_off(intel_dp);
1685 static void intel_enable_dp(struct intel_encoder *encoder)
1687 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1688 struct drm_device *dev = encoder->base.dev;
1689 struct drm_i915_private *dev_priv = dev->dev_private;
1690 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1692 if (WARN_ON(dp_reg & DP_PORT_EN))
1695 ironlake_edp_panel_vdd_on(intel_dp);
1696 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1697 intel_dp_start_link_train(intel_dp);
1698 ironlake_edp_panel_on(intel_dp);
1699 ironlake_edp_panel_vdd_off(intel_dp, true);
1700 intel_dp_complete_link_train(intel_dp);
1701 intel_dp_stop_link_train(intel_dp);
1702 ironlake_edp_backlight_on(intel_dp);
1704 if (IS_VALLEYVIEW(dev)) {
1705 struct intel_digital_port *dport =
1706 enc_to_dig_port(&encoder->base);
1707 int channel = vlv_dport_to_channel(dport);
1709 vlv_wait_port_ready(dev_priv, channel);
1713 static void intel_pre_enable_dp(struct intel_encoder *encoder)
1715 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1716 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1717 struct drm_device *dev = encoder->base.dev;
1718 struct drm_i915_private *dev_priv = dev->dev_private;
1720 if (dport->port == PORT_A && !IS_VALLEYVIEW(dev))
1721 ironlake_edp_pll_on(intel_dp);
1723 if (IS_VALLEYVIEW(dev)) {
1724 struct intel_crtc *intel_crtc =
1725 to_intel_crtc(encoder->base.crtc);
1726 int port = vlv_dport_to_channel(dport);
1727 int pipe = intel_crtc->pipe;
1730 mutex_lock(&dev_priv->dpio_lock);
1731 val = vlv_dpio_read(dev_priv, DPIO_DATA_LANE_A(port));
1738 vlv_dpio_write(dev_priv, DPIO_DATA_CHANNEL(port), val);
1740 vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF0(port),
1742 vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF8(port),
1744 mutex_unlock(&dev_priv->dpio_lock);
1748 static void intel_dp_pre_pll_enable(struct intel_encoder *encoder)
1750 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1751 struct drm_device *dev = encoder->base.dev;
1752 struct drm_i915_private *dev_priv = dev->dev_private;
1753 int port = vlv_dport_to_channel(dport);
1755 if (!IS_VALLEYVIEW(dev))
1758 /* Program Tx lane resets to default */
1759 mutex_lock(&dev_priv->dpio_lock);
1760 vlv_dpio_write(dev_priv, DPIO_PCS_TX(port),
1761 DPIO_PCS_TX_LANE2_RESET |
1762 DPIO_PCS_TX_LANE1_RESET);
1763 vlv_dpio_write(dev_priv, DPIO_PCS_CLK(port),
1764 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1765 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1766 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1767 DPIO_PCS_CLK_SOFT_RESET);
1769 /* Fix up inter-pair skew failure */
1770 vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER1(port), 0x00750f00);
1771 vlv_dpio_write(dev_priv, DPIO_TX_CTL(port), 0x00001500);
1772 vlv_dpio_write(dev_priv, DPIO_TX_LANE(port), 0x40400000);
1773 mutex_unlock(&dev_priv->dpio_lock);
1777 * Native read with retry for link status and receiver capability reads for
1778 * cases where the sink may still be asleep.
1781 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1782 uint8_t *recv, int recv_bytes)
1787 * Sinks are *supposed* to come up within 1ms from an off state,
1788 * but we're also supposed to retry 3 times per the spec.
1790 for (i = 0; i < 3; i++) {
1791 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1793 if (ret == recv_bytes)
1802 * Fetch AUX CH registers 0x202 - 0x207 which contain
1803 * link status information
1806 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1808 return intel_dp_aux_native_read_retry(intel_dp,
1811 DP_LINK_STATUS_SIZE);
1815 static char *voltage_names[] = {
1816 "0.4V", "0.6V", "0.8V", "1.2V"
1818 static char *pre_emph_names[] = {
1819 "0dB", "3.5dB", "6dB", "9.5dB"
1821 static char *link_train_names[] = {
1822 "pattern 1", "pattern 2", "idle", "off"
1827 * These are source-specific values; current Intel hardware supports
1828 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1832 intel_dp_voltage_max(struct intel_dp *intel_dp)
1834 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1835 enum port port = dp_to_dig_port(intel_dp)->port;
1837 if (IS_VALLEYVIEW(dev))
1838 return DP_TRAIN_VOLTAGE_SWING_1200;
1839 else if (IS_GEN7(dev) && port == PORT_A)
1840 return DP_TRAIN_VOLTAGE_SWING_800;
1841 else if (HAS_PCH_CPT(dev) && port != PORT_A)
1842 return DP_TRAIN_VOLTAGE_SWING_1200;
1844 return DP_TRAIN_VOLTAGE_SWING_800;
1848 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1850 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1851 enum port port = dp_to_dig_port(intel_dp)->port;
1854 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1855 case DP_TRAIN_VOLTAGE_SWING_400:
1856 return DP_TRAIN_PRE_EMPHASIS_9_5;
1857 case DP_TRAIN_VOLTAGE_SWING_600:
1858 return DP_TRAIN_PRE_EMPHASIS_6;
1859 case DP_TRAIN_VOLTAGE_SWING_800:
1860 return DP_TRAIN_PRE_EMPHASIS_3_5;
1861 case DP_TRAIN_VOLTAGE_SWING_1200:
1863 return DP_TRAIN_PRE_EMPHASIS_0;
1865 } else if (IS_VALLEYVIEW(dev)) {
1866 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1867 case DP_TRAIN_VOLTAGE_SWING_400:
1868 return DP_TRAIN_PRE_EMPHASIS_9_5;
1869 case DP_TRAIN_VOLTAGE_SWING_600:
1870 return DP_TRAIN_PRE_EMPHASIS_6;
1871 case DP_TRAIN_VOLTAGE_SWING_800:
1872 return DP_TRAIN_PRE_EMPHASIS_3_5;
1873 case DP_TRAIN_VOLTAGE_SWING_1200:
1875 return DP_TRAIN_PRE_EMPHASIS_0;
1877 } else if (IS_GEN7(dev) && port == PORT_A) {
1878 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1879 case DP_TRAIN_VOLTAGE_SWING_400:
1880 return DP_TRAIN_PRE_EMPHASIS_6;
1881 case DP_TRAIN_VOLTAGE_SWING_600:
1882 case DP_TRAIN_VOLTAGE_SWING_800:
1883 return DP_TRAIN_PRE_EMPHASIS_3_5;
1885 return DP_TRAIN_PRE_EMPHASIS_0;
1888 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1889 case DP_TRAIN_VOLTAGE_SWING_400:
1890 return DP_TRAIN_PRE_EMPHASIS_6;
1891 case DP_TRAIN_VOLTAGE_SWING_600:
1892 return DP_TRAIN_PRE_EMPHASIS_6;
1893 case DP_TRAIN_VOLTAGE_SWING_800:
1894 return DP_TRAIN_PRE_EMPHASIS_3_5;
1895 case DP_TRAIN_VOLTAGE_SWING_1200:
1897 return DP_TRAIN_PRE_EMPHASIS_0;
1902 static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
1904 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1905 struct drm_i915_private *dev_priv = dev->dev_private;
1906 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1907 unsigned long demph_reg_value, preemph_reg_value,
1908 uniqtranscale_reg_value;
1909 uint8_t train_set = intel_dp->train_set[0];
1910 int port = vlv_dport_to_channel(dport);
1912 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1913 case DP_TRAIN_PRE_EMPHASIS_0:
1914 preemph_reg_value = 0x0004000;
1915 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1916 case DP_TRAIN_VOLTAGE_SWING_400:
1917 demph_reg_value = 0x2B405555;
1918 uniqtranscale_reg_value = 0x552AB83A;
1920 case DP_TRAIN_VOLTAGE_SWING_600:
1921 demph_reg_value = 0x2B404040;
1922 uniqtranscale_reg_value = 0x5548B83A;
1924 case DP_TRAIN_VOLTAGE_SWING_800:
1925 demph_reg_value = 0x2B245555;
1926 uniqtranscale_reg_value = 0x5560B83A;
1928 case DP_TRAIN_VOLTAGE_SWING_1200:
1929 demph_reg_value = 0x2B405555;
1930 uniqtranscale_reg_value = 0x5598DA3A;
1936 case DP_TRAIN_PRE_EMPHASIS_3_5:
1937 preemph_reg_value = 0x0002000;
1938 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1939 case DP_TRAIN_VOLTAGE_SWING_400:
1940 demph_reg_value = 0x2B404040;
1941 uniqtranscale_reg_value = 0x5552B83A;
1943 case DP_TRAIN_VOLTAGE_SWING_600:
1944 demph_reg_value = 0x2B404848;
1945 uniqtranscale_reg_value = 0x5580B83A;
1947 case DP_TRAIN_VOLTAGE_SWING_800:
1948 demph_reg_value = 0x2B404040;
1949 uniqtranscale_reg_value = 0x55ADDA3A;
1955 case DP_TRAIN_PRE_EMPHASIS_6:
1956 preemph_reg_value = 0x0000000;
1957 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1958 case DP_TRAIN_VOLTAGE_SWING_400:
1959 demph_reg_value = 0x2B305555;
1960 uniqtranscale_reg_value = 0x5570B83A;
1962 case DP_TRAIN_VOLTAGE_SWING_600:
1963 demph_reg_value = 0x2B2B4040;
1964 uniqtranscale_reg_value = 0x55ADDA3A;
1970 case DP_TRAIN_PRE_EMPHASIS_9_5:
1971 preemph_reg_value = 0x0006000;
1972 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1973 case DP_TRAIN_VOLTAGE_SWING_400:
1974 demph_reg_value = 0x1B405555;
1975 uniqtranscale_reg_value = 0x55ADDA3A;
1985 mutex_lock(&dev_priv->dpio_lock);
1986 vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x00000000);
1987 vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL4(port), demph_reg_value);
1988 vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL2(port),
1989 uniqtranscale_reg_value);
1990 vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL3(port), 0x0C782040);
1991 vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER0(port), 0x00030000);
1992 vlv_dpio_write(dev_priv, DPIO_PCS_CTL_OVER1(port), preemph_reg_value);
1993 vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x80000000);
1994 mutex_unlock(&dev_priv->dpio_lock);
2000 intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
2005 uint8_t voltage_max;
2006 uint8_t preemph_max;
2008 for (lane = 0; lane < intel_dp->lane_count; lane++) {
2009 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2010 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
2018 voltage_max = intel_dp_voltage_max(intel_dp);
2019 if (v >= voltage_max)
2020 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
2022 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2023 if (p >= preemph_max)
2024 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
2026 for (lane = 0; lane < 4; lane++)
2027 intel_dp->train_set[lane] = v | p;
2031 intel_gen4_signal_levels(uint8_t train_set)
2033 uint32_t signal_levels = 0;
2035 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2036 case DP_TRAIN_VOLTAGE_SWING_400:
2038 signal_levels |= DP_VOLTAGE_0_4;
2040 case DP_TRAIN_VOLTAGE_SWING_600:
2041 signal_levels |= DP_VOLTAGE_0_6;
2043 case DP_TRAIN_VOLTAGE_SWING_800:
2044 signal_levels |= DP_VOLTAGE_0_8;
2046 case DP_TRAIN_VOLTAGE_SWING_1200:
2047 signal_levels |= DP_VOLTAGE_1_2;
2050 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2051 case DP_TRAIN_PRE_EMPHASIS_0:
2053 signal_levels |= DP_PRE_EMPHASIS_0;
2055 case DP_TRAIN_PRE_EMPHASIS_3_5:
2056 signal_levels |= DP_PRE_EMPHASIS_3_5;
2058 case DP_TRAIN_PRE_EMPHASIS_6:
2059 signal_levels |= DP_PRE_EMPHASIS_6;
2061 case DP_TRAIN_PRE_EMPHASIS_9_5:
2062 signal_levels |= DP_PRE_EMPHASIS_9_5;
2065 return signal_levels;
2068 /* Gen6's DP voltage swing and pre-emphasis control */
2070 intel_gen6_edp_signal_levels(uint8_t train_set)
2072 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2073 DP_TRAIN_PRE_EMPHASIS_MASK);
2074 switch (signal_levels) {
2075 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2076 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2077 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2078 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2079 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
2080 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2081 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2082 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
2083 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2084 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2085 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
2086 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2087 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2088 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
2090 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2091 "0x%x\n", signal_levels);
2092 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2096 /* Gen7's DP voltage swing and pre-emphasis control */
2098 intel_gen7_edp_signal_levels(uint8_t train_set)
2100 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2101 DP_TRAIN_PRE_EMPHASIS_MASK);
2102 switch (signal_levels) {
2103 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2104 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2105 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2106 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2107 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2108 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2110 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2111 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2112 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2113 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2115 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2116 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2117 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2118 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2121 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2122 "0x%x\n", signal_levels);
2123 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2127 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2129 intel_hsw_signal_levels(uint8_t train_set)
2131 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2132 DP_TRAIN_PRE_EMPHASIS_MASK);
2133 switch (signal_levels) {
2134 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2135 return DDI_BUF_EMP_400MV_0DB_HSW;
2136 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2137 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2138 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2139 return DDI_BUF_EMP_400MV_6DB_HSW;
2140 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2141 return DDI_BUF_EMP_400MV_9_5DB_HSW;
2143 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2144 return DDI_BUF_EMP_600MV_0DB_HSW;
2145 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2146 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2147 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2148 return DDI_BUF_EMP_600MV_6DB_HSW;
2150 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2151 return DDI_BUF_EMP_800MV_0DB_HSW;
2152 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2153 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2155 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2156 "0x%x\n", signal_levels);
2157 return DDI_BUF_EMP_400MV_0DB_HSW;
2161 /* Properly updates "DP" with the correct signal levels. */
2163 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2165 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2166 enum port port = intel_dig_port->port;
2167 struct drm_device *dev = intel_dig_port->base.base.dev;
2168 uint32_t signal_levels, mask;
2169 uint8_t train_set = intel_dp->train_set[0];
2172 signal_levels = intel_hsw_signal_levels(train_set);
2173 mask = DDI_BUF_EMP_MASK;
2174 } else if (IS_VALLEYVIEW(dev)) {
2175 signal_levels = intel_vlv_signal_levels(intel_dp);
2177 } else if (IS_GEN7(dev) && port == PORT_A) {
2178 signal_levels = intel_gen7_edp_signal_levels(train_set);
2179 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
2180 } else if (IS_GEN6(dev) && port == PORT_A) {
2181 signal_levels = intel_gen6_edp_signal_levels(train_set);
2182 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2184 signal_levels = intel_gen4_signal_levels(train_set);
2185 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2188 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2190 *DP = (*DP & ~mask) | signal_levels;
2194 intel_dp_set_link_train(struct intel_dp *intel_dp,
2195 uint32_t dp_reg_value,
2196 uint8_t dp_train_pat)
2198 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2199 struct drm_device *dev = intel_dig_port->base.base.dev;
2200 struct drm_i915_private *dev_priv = dev->dev_private;
2201 enum port port = intel_dig_port->port;
2205 uint32_t temp = I915_READ(DP_TP_CTL(port));
2207 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2208 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2210 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2212 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2213 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2214 case DP_TRAINING_PATTERN_DISABLE:
2215 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2218 case DP_TRAINING_PATTERN_1:
2219 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2221 case DP_TRAINING_PATTERN_2:
2222 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2224 case DP_TRAINING_PATTERN_3:
2225 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2228 I915_WRITE(DP_TP_CTL(port), temp);
2230 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2231 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
2233 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2234 case DP_TRAINING_PATTERN_DISABLE:
2235 dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
2237 case DP_TRAINING_PATTERN_1:
2238 dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
2240 case DP_TRAINING_PATTERN_2:
2241 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
2243 case DP_TRAINING_PATTERN_3:
2244 DRM_ERROR("DP training pattern 3 not supported\n");
2245 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
2250 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
2252 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2253 case DP_TRAINING_PATTERN_DISABLE:
2254 dp_reg_value |= DP_LINK_TRAIN_OFF;
2256 case DP_TRAINING_PATTERN_1:
2257 dp_reg_value |= DP_LINK_TRAIN_PAT_1;
2259 case DP_TRAINING_PATTERN_2:
2260 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
2262 case DP_TRAINING_PATTERN_3:
2263 DRM_ERROR("DP training pattern 3 not supported\n");
2264 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
2269 I915_WRITE(intel_dp->output_reg, dp_reg_value);
2270 POSTING_READ(intel_dp->output_reg);
2272 intel_dp_aux_native_write_1(intel_dp,
2273 DP_TRAINING_PATTERN_SET,
2276 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
2277 DP_TRAINING_PATTERN_DISABLE) {
2278 ret = intel_dp_aux_native_write(intel_dp,
2279 DP_TRAINING_LANE0_SET,
2280 intel_dp->train_set,
2281 intel_dp->lane_count);
2282 if (ret != intel_dp->lane_count)
2289 static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
2291 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2292 struct drm_device *dev = intel_dig_port->base.base.dev;
2293 struct drm_i915_private *dev_priv = dev->dev_private;
2294 enum port port = intel_dig_port->port;
2300 val = I915_READ(DP_TP_CTL(port));
2301 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2302 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
2303 I915_WRITE(DP_TP_CTL(port), val);
2306 * On PORT_A we can have only eDP in SST mode. There the only reason
2307 * we need to set idle transmission mode is to work around a HW issue
2308 * where we enable the pipe while not in idle link-training mode.
2309 * In this case there is requirement to wait for a minimum number of
2310 * idle patterns to be sent.
2315 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2317 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2320 /* Enable corresponding port and start training pattern 1 */
2322 intel_dp_start_link_train(struct intel_dp *intel_dp)
2324 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
2325 struct drm_device *dev = encoder->dev;
2328 bool clock_recovery = false;
2329 int voltage_tries, loop_tries;
2330 uint32_t DP = intel_dp->DP;
2333 intel_ddi_prepare_link_retrain(encoder);
2335 /* Write the link configuration data */
2336 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
2337 intel_dp->link_configuration,
2338 DP_LINK_CONFIGURATION_SIZE);
2342 memset(intel_dp->train_set, 0, 4);
2346 clock_recovery = false;
2348 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
2349 uint8_t link_status[DP_LINK_STATUS_SIZE];
2351 intel_dp_set_signal_levels(intel_dp, &DP);
2353 /* Set training pattern 1 */
2354 if (!intel_dp_set_link_train(intel_dp, DP,
2355 DP_TRAINING_PATTERN_1 |
2356 DP_LINK_SCRAMBLING_DISABLE))
2359 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
2360 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2361 DRM_ERROR("failed to get link status\n");
2365 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2366 DRM_DEBUG_KMS("clock recovery OK\n");
2367 clock_recovery = true;
2371 /* Check to see if we've tried the max voltage */
2372 for (i = 0; i < intel_dp->lane_count; i++)
2373 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
2375 if (i == intel_dp->lane_count) {
2377 if (loop_tries == 5) {
2378 DRM_DEBUG_KMS("too many full retries, give up\n");
2381 memset(intel_dp->train_set, 0, 4);
2386 /* Check to see if we've tried the same voltage 5 times */
2387 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
2389 if (voltage_tries == 5) {
2390 DRM_DEBUG_KMS("too many voltage retries, give up\n");
2395 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
2397 /* Compute new intel_dp->train_set as requested by target */
2398 intel_get_adjust_train(intel_dp, link_status);
2405 intel_dp_complete_link_train(struct intel_dp *intel_dp)
2407 bool channel_eq = false;
2408 int tries, cr_tries;
2409 uint32_t DP = intel_dp->DP;
2411 /* channel equalization */
2416 uint8_t link_status[DP_LINK_STATUS_SIZE];
2419 DRM_ERROR("failed to train DP, aborting\n");
2420 intel_dp_link_down(intel_dp);
2424 intel_dp_set_signal_levels(intel_dp, &DP);
2426 /* channel eq pattern */
2427 if (!intel_dp_set_link_train(intel_dp, DP,
2428 DP_TRAINING_PATTERN_2 |
2429 DP_LINK_SCRAMBLING_DISABLE))
2432 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
2433 if (!intel_dp_get_link_status(intel_dp, link_status))
2436 /* Make sure clock is still ok */
2437 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2438 intel_dp_start_link_train(intel_dp);
2443 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2448 /* Try 5 times, then try clock recovery if that fails */
2450 intel_dp_link_down(intel_dp);
2451 intel_dp_start_link_train(intel_dp);
2457 /* Compute new intel_dp->train_set as requested by target */
2458 intel_get_adjust_train(intel_dp, link_status);
2462 intel_dp_set_idle_link_train(intel_dp);
2467 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
2471 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
2473 intel_dp_set_link_train(intel_dp, intel_dp->DP,
2474 DP_TRAINING_PATTERN_DISABLE);
2478 intel_dp_link_down(struct intel_dp *intel_dp)
2480 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2481 enum port port = intel_dig_port->port;
2482 struct drm_device *dev = intel_dig_port->base.base.dev;
2483 struct drm_i915_private *dev_priv = dev->dev_private;
2484 struct intel_crtc *intel_crtc =
2485 to_intel_crtc(intel_dig_port->base.base.crtc);
2486 uint32_t DP = intel_dp->DP;
2489 * DDI code has a strict mode set sequence and we should try to respect
2490 * it, otherwise we might hang the machine in many different ways. So we
2491 * really should be disabling the port only on a complete crtc_disable
2492 * sequence. This function is just called under two conditions on DDI
2494 * - Link train failed while doing crtc_enable, and on this case we
2495 * really should respect the mode set sequence and wait for a
2497 * - Someone turned the monitor off and intel_dp_check_link_status
2498 * called us. We don't need to disable the whole port on this case, so
2499 * when someone turns the monitor on again,
2500 * intel_ddi_prepare_link_retrain will take care of redoing the link
2506 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
2509 DRM_DEBUG_KMS("\n");
2511 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2512 DP &= ~DP_LINK_TRAIN_MASK_CPT;
2513 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
2515 DP &= ~DP_LINK_TRAIN_MASK;
2516 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
2518 POSTING_READ(intel_dp->output_reg);
2520 /* We don't really know why we're doing this */
2521 intel_wait_for_vblank(dev, intel_crtc->pipe);
2523 if (HAS_PCH_IBX(dev) &&
2524 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
2525 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2527 /* Hardware workaround: leaving our transcoder select
2528 * set to transcoder B while it's off will prevent the
2529 * corresponding HDMI output on transcoder A.
2531 * Combine this with another hardware workaround:
2532 * transcoder select bit can only be cleared while the
2535 DP &= ~DP_PIPEB_SELECT;
2536 I915_WRITE(intel_dp->output_reg, DP);
2538 /* Changes to enable or select take place the vblank
2539 * after being written.
2541 if (WARN_ON(crtc == NULL)) {
2542 /* We should never try to disable a port without a crtc
2543 * attached. For paranoia keep the code around for a
2545 POSTING_READ(intel_dp->output_reg);
2548 intel_wait_for_vblank(dev, intel_crtc->pipe);
2551 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
2552 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2553 POSTING_READ(intel_dp->output_reg);
2554 msleep(intel_dp->panel_power_down_delay);
2558 intel_dp_get_dpcd(struct intel_dp *intel_dp)
2560 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2562 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
2563 sizeof(intel_dp->dpcd)) == 0)
2564 return false; /* aux transfer failed */
2566 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2567 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2568 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2570 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2571 return false; /* DPCD not present */
2573 /* Check if the panel supports PSR */
2574 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
2575 intel_dp_aux_native_read_retry(intel_dp, DP_PSR_SUPPORT,
2577 sizeof(intel_dp->psr_dpcd));
2578 if (is_edp_psr(intel_dp))
2579 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
2580 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2581 DP_DWN_STRM_PORT_PRESENT))
2582 return true; /* native DP sink */
2584 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2585 return true; /* no per-port downstream info */
2587 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2588 intel_dp->downstream_ports,
2589 DP_MAX_DOWNSTREAM_PORTS) == 0)
2590 return false; /* downstream port status fetch failed */
2596 intel_dp_probe_oui(struct intel_dp *intel_dp)
2600 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2603 ironlake_edp_panel_vdd_on(intel_dp);
2605 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2606 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2607 buf[0], buf[1], buf[2]);
2609 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2610 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2611 buf[0], buf[1], buf[2]);
2613 ironlake_edp_panel_vdd_off(intel_dp, false);
2617 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2621 ret = intel_dp_aux_native_read_retry(intel_dp,
2622 DP_DEVICE_SERVICE_IRQ_VECTOR,
2623 sink_irq_vector, 1);
2631 intel_dp_handle_test_request(struct intel_dp *intel_dp)
2633 /* NAK by default */
2634 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
2638 * According to DP spec
2641 * 2. Configure link according to Receiver Capabilities
2642 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2643 * 4. Check link status on receipt of hot-plug interrupt
2647 intel_dp_check_link_status(struct intel_dp *intel_dp)
2649 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
2651 u8 link_status[DP_LINK_STATUS_SIZE];
2653 if (!intel_encoder->connectors_active)
2656 if (WARN_ON(!intel_encoder->base.crtc))
2659 /* Try to read receiver status if the link appears to be up */
2660 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2661 intel_dp_link_down(intel_dp);
2665 /* Now read the DPCD to see if it's actually running */
2666 if (!intel_dp_get_dpcd(intel_dp)) {
2667 intel_dp_link_down(intel_dp);
2671 /* Try to read the source of the interrupt */
2672 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2673 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2674 /* Clear interrupt source */
2675 intel_dp_aux_native_write_1(intel_dp,
2676 DP_DEVICE_SERVICE_IRQ_VECTOR,
2679 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2680 intel_dp_handle_test_request(intel_dp);
2681 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2682 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2685 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2686 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2687 drm_get_encoder_name(&intel_encoder->base));
2688 intel_dp_start_link_train(intel_dp);
2689 intel_dp_complete_link_train(intel_dp);
2690 intel_dp_stop_link_train(intel_dp);
2694 /* XXX this is probably wrong for multiple downstream ports */
2695 static enum drm_connector_status
2696 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2698 uint8_t *dpcd = intel_dp->dpcd;
2702 if (!intel_dp_get_dpcd(intel_dp))
2703 return connector_status_disconnected;
2705 /* if there's no downstream port, we're done */
2706 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
2707 return connector_status_connected;
2709 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2710 hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2713 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
2715 return connector_status_unknown;
2716 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2717 : connector_status_disconnected;
2720 /* If no HPD, poke DDC gently */
2721 if (drm_probe_ddc(&intel_dp->adapter))
2722 return connector_status_connected;
2724 /* Well we tried, say unknown for unreliable port types */
2725 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2726 if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2727 return connector_status_unknown;
2729 /* Anything else is out of spec, warn and ignore */
2730 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
2731 return connector_status_disconnected;
2734 static enum drm_connector_status
2735 ironlake_dp_detect(struct intel_dp *intel_dp)
2737 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2738 struct drm_i915_private *dev_priv = dev->dev_private;
2739 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2740 enum drm_connector_status status;
2742 /* Can't disconnect eDP, but you can close the lid... */
2743 if (is_edp(intel_dp)) {
2744 status = intel_panel_detect(dev);
2745 if (status == connector_status_unknown)
2746 status = connector_status_connected;
2750 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
2751 return connector_status_disconnected;
2753 return intel_dp_detect_dpcd(intel_dp);
2756 static enum drm_connector_status
2757 g4x_dp_detect(struct intel_dp *intel_dp)
2759 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2760 struct drm_i915_private *dev_priv = dev->dev_private;
2761 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2764 /* Can't disconnect eDP, but you can close the lid... */
2765 if (is_edp(intel_dp)) {
2766 enum drm_connector_status status;
2768 status = intel_panel_detect(dev);
2769 if (status == connector_status_unknown)
2770 status = connector_status_connected;
2774 switch (intel_dig_port->port) {
2776 bit = PORTB_HOTPLUG_LIVE_STATUS;
2779 bit = PORTC_HOTPLUG_LIVE_STATUS;
2782 bit = PORTD_HOTPLUG_LIVE_STATUS;
2785 return connector_status_unknown;
2788 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2789 return connector_status_disconnected;
2791 return intel_dp_detect_dpcd(intel_dp);
2794 static struct edid *
2795 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2797 struct intel_connector *intel_connector = to_intel_connector(connector);
2799 /* use cached edid if we have one */
2800 if (intel_connector->edid) {
2805 if (IS_ERR(intel_connector->edid))
2808 size = (intel_connector->edid->extensions + 1) * EDID_LENGTH;
2809 edid = kmemdup(intel_connector->edid, size, GFP_KERNEL);
2816 return drm_get_edid(connector, adapter);
2820 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2822 struct intel_connector *intel_connector = to_intel_connector(connector);
2824 /* use cached edid if we have one */
2825 if (intel_connector->edid) {
2827 if (IS_ERR(intel_connector->edid))
2830 return intel_connector_update_modes(connector,
2831 intel_connector->edid);
2834 return intel_ddc_get_modes(connector, adapter);
2837 static enum drm_connector_status
2838 intel_dp_detect(struct drm_connector *connector, bool force)
2840 struct intel_dp *intel_dp = intel_attached_dp(connector);
2841 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2842 struct intel_encoder *intel_encoder = &intel_dig_port->base;
2843 struct drm_device *dev = connector->dev;
2844 enum drm_connector_status status;
2845 struct edid *edid = NULL;
2847 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
2848 connector->base.id, drm_get_connector_name(connector));
2850 intel_dp->has_audio = false;
2852 if (HAS_PCH_SPLIT(dev))
2853 status = ironlake_dp_detect(intel_dp);
2855 status = g4x_dp_detect(intel_dp);
2857 if (status != connector_status_connected)
2860 intel_dp_probe_oui(intel_dp);
2862 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2863 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
2865 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2867 intel_dp->has_audio = drm_detect_monitor_audio(edid);
2872 if (intel_encoder->type != INTEL_OUTPUT_EDP)
2873 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2874 return connector_status_connected;
2877 static int intel_dp_get_modes(struct drm_connector *connector)
2879 struct intel_dp *intel_dp = intel_attached_dp(connector);
2880 struct intel_connector *intel_connector = to_intel_connector(connector);
2881 struct drm_device *dev = connector->dev;
2884 /* We should parse the EDID data and find out if it has an audio sink
2887 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
2891 /* if eDP has no EDID, fall back to fixed mode */
2892 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
2893 struct drm_display_mode *mode;
2894 mode = drm_mode_duplicate(dev,
2895 intel_connector->panel.fixed_mode);
2897 drm_mode_probed_add(connector, mode);
2905 intel_dp_detect_audio(struct drm_connector *connector)
2907 struct intel_dp *intel_dp = intel_attached_dp(connector);
2909 bool has_audio = false;
2911 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2913 has_audio = drm_detect_monitor_audio(edid);
2921 intel_dp_set_property(struct drm_connector *connector,
2922 struct drm_property *property,
2925 struct drm_i915_private *dev_priv = connector->dev->dev_private;
2926 struct intel_connector *intel_connector = to_intel_connector(connector);
2927 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
2928 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2931 ret = drm_object_property_set_value(&connector->base, property, val);
2935 if (property == dev_priv->force_audio_property) {
2939 if (i == intel_dp->force_audio)
2942 intel_dp->force_audio = i;
2944 if (i == HDMI_AUDIO_AUTO)
2945 has_audio = intel_dp_detect_audio(connector);
2947 has_audio = (i == HDMI_AUDIO_ON);
2949 if (has_audio == intel_dp->has_audio)
2952 intel_dp->has_audio = has_audio;
2956 if (property == dev_priv->broadcast_rgb_property) {
2957 bool old_auto = intel_dp->color_range_auto;
2958 uint32_t old_range = intel_dp->color_range;
2961 case INTEL_BROADCAST_RGB_AUTO:
2962 intel_dp->color_range_auto = true;
2964 case INTEL_BROADCAST_RGB_FULL:
2965 intel_dp->color_range_auto = false;
2966 intel_dp->color_range = 0;
2968 case INTEL_BROADCAST_RGB_LIMITED:
2969 intel_dp->color_range_auto = false;
2970 intel_dp->color_range = DP_COLOR_RANGE_16_235;
2976 if (old_auto == intel_dp->color_range_auto &&
2977 old_range == intel_dp->color_range)
2983 if (is_edp(intel_dp) &&
2984 property == connector->dev->mode_config.scaling_mode_property) {
2985 if (val == DRM_MODE_SCALE_NONE) {
2986 DRM_DEBUG_KMS("no scaling not supported\n");
2990 if (intel_connector->panel.fitting_mode == val) {
2991 /* the eDP scaling property is not changed */
2994 intel_connector->panel.fitting_mode = val;
3002 if (intel_encoder->base.crtc)
3003 intel_crtc_restore_mode(intel_encoder->base.crtc);
3009 intel_dp_connector_destroy(struct drm_connector *connector)
3011 struct intel_connector *intel_connector = to_intel_connector(connector);
3013 if (!IS_ERR_OR_NULL(intel_connector->edid))
3014 kfree(intel_connector->edid);
3016 /* Can't call is_edp() since the encoder may have been destroyed
3018 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3019 intel_panel_fini(&intel_connector->panel);
3021 drm_sysfs_connector_remove(connector);
3022 drm_connector_cleanup(connector);
3026 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
3028 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3029 struct intel_dp *intel_dp = &intel_dig_port->dp;
3030 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3032 i2c_del_adapter(&intel_dp->adapter);
3033 drm_encoder_cleanup(encoder);
3034 if (is_edp(intel_dp)) {
3035 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3036 mutex_lock(&dev->mode_config.mutex);
3037 ironlake_panel_vdd_off_sync(intel_dp);
3038 mutex_unlock(&dev->mode_config.mutex);
3040 kfree(intel_dig_port);
3043 static const struct drm_connector_funcs intel_dp_connector_funcs = {
3044 .dpms = intel_connector_dpms,
3045 .detect = intel_dp_detect,
3046 .fill_modes = drm_helper_probe_single_connector_modes,
3047 .set_property = intel_dp_set_property,
3048 .destroy = intel_dp_connector_destroy,
3051 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
3052 .get_modes = intel_dp_get_modes,
3053 .mode_valid = intel_dp_mode_valid,
3054 .best_encoder = intel_best_encoder,
3057 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
3058 .destroy = intel_dp_encoder_destroy,
3062 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
3064 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
3066 intel_dp_check_link_status(intel_dp);
3069 /* Return which DP Port should be selected for Transcoder DP control */
3071 intel_trans_dp_port_sel(struct drm_crtc *crtc)
3073 struct drm_device *dev = crtc->dev;
3074 struct intel_encoder *intel_encoder;
3075 struct intel_dp *intel_dp;
3077 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3078 intel_dp = enc_to_intel_dp(&intel_encoder->base);
3080 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
3081 intel_encoder->type == INTEL_OUTPUT_EDP)
3082 return intel_dp->output_reg;
3088 /* check the VBT to see whether the eDP is on DP-D port */
3089 bool intel_dpd_is_edp(struct drm_device *dev)
3091 struct drm_i915_private *dev_priv = dev->dev_private;
3092 struct child_device_config *p_child;
3095 if (!dev_priv->vbt.child_dev_num)
3098 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
3099 p_child = dev_priv->vbt.child_dev + i;
3101 if (p_child->dvo_port == PORT_IDPD &&
3102 p_child->device_type == DEVICE_TYPE_eDP)
3109 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
3111 struct intel_connector *intel_connector = to_intel_connector(connector);
3113 intel_attach_force_audio_property(connector);
3114 intel_attach_broadcast_rgb_property(connector);
3115 intel_dp->color_range_auto = true;
3117 if (is_edp(intel_dp)) {
3118 drm_mode_create_scaling_mode_property(connector->dev);
3119 drm_object_attach_property(
3121 connector->dev->mode_config.scaling_mode_property,
3122 DRM_MODE_SCALE_ASPECT);
3123 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
3128 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
3129 struct intel_dp *intel_dp,
3130 struct edp_power_seq *out)
3132 struct drm_i915_private *dev_priv = dev->dev_private;
3133 struct edp_power_seq cur, vbt, spec, final;
3134 u32 pp_on, pp_off, pp_div, pp;
3135 int pp_control_reg, pp_on_reg, pp_off_reg, pp_div_reg;
3137 if (HAS_PCH_SPLIT(dev)) {
3138 pp_control_reg = PCH_PP_CONTROL;
3139 pp_on_reg = PCH_PP_ON_DELAYS;
3140 pp_off_reg = PCH_PP_OFF_DELAYS;
3141 pp_div_reg = PCH_PP_DIVISOR;
3143 pp_control_reg = PIPEA_PP_CONTROL;
3144 pp_on_reg = PIPEA_PP_ON_DELAYS;
3145 pp_off_reg = PIPEA_PP_OFF_DELAYS;
3146 pp_div_reg = PIPEA_PP_DIVISOR;
3149 /* Workaround: Need to write PP_CONTROL with the unlock key as
3150 * the very first thing. */
3151 pp = ironlake_get_pp_control(intel_dp);
3152 I915_WRITE(pp_control_reg, pp);
3154 pp_on = I915_READ(pp_on_reg);
3155 pp_off = I915_READ(pp_off_reg);
3156 pp_div = I915_READ(pp_div_reg);
3158 /* Pull timing values out of registers */
3159 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
3160 PANEL_POWER_UP_DELAY_SHIFT;
3162 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
3163 PANEL_LIGHT_ON_DELAY_SHIFT;
3165 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
3166 PANEL_LIGHT_OFF_DELAY_SHIFT;
3168 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
3169 PANEL_POWER_DOWN_DELAY_SHIFT;
3171 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
3172 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
3174 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3175 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
3177 vbt = dev_priv->vbt.edp_pps;
3179 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
3180 * our hw here, which are all in 100usec. */
3181 spec.t1_t3 = 210 * 10;
3182 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
3183 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
3184 spec.t10 = 500 * 10;
3185 /* This one is special and actually in units of 100ms, but zero
3186 * based in the hw (so we need to add 100 ms). But the sw vbt
3187 * table multiplies it with 1000 to make it in units of 100usec,
3189 spec.t11_t12 = (510 + 100) * 10;
3191 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3192 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
3194 /* Use the max of the register settings and vbt. If both are
3195 * unset, fall back to the spec limits. */
3196 #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
3198 max(cur.field, vbt.field))
3199 assign_final(t1_t3);
3203 assign_final(t11_t12);
3206 #define get_delay(field) (DIV_ROUND_UP(final.field, 10))
3207 intel_dp->panel_power_up_delay = get_delay(t1_t3);
3208 intel_dp->backlight_on_delay = get_delay(t8);
3209 intel_dp->backlight_off_delay = get_delay(t9);
3210 intel_dp->panel_power_down_delay = get_delay(t10);
3211 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
3214 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
3215 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
3216 intel_dp->panel_power_cycle_delay);
3218 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
3219 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
3226 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
3227 struct intel_dp *intel_dp,
3228 struct edp_power_seq *seq)
3230 struct drm_i915_private *dev_priv = dev->dev_private;
3231 u32 pp_on, pp_off, pp_div, port_sel = 0;
3232 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
3233 int pp_on_reg, pp_off_reg, pp_div_reg;
3235 if (HAS_PCH_SPLIT(dev)) {
3236 pp_on_reg = PCH_PP_ON_DELAYS;
3237 pp_off_reg = PCH_PP_OFF_DELAYS;
3238 pp_div_reg = PCH_PP_DIVISOR;
3240 pp_on_reg = PIPEA_PP_ON_DELAYS;
3241 pp_off_reg = PIPEA_PP_OFF_DELAYS;
3242 pp_div_reg = PIPEA_PP_DIVISOR;
3245 /* And finally store the new values in the power sequencer. */
3246 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
3247 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
3248 pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
3249 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
3250 /* Compute the divisor for the pp clock, simply match the Bspec
3252 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
3253 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
3254 << PANEL_POWER_CYCLE_DELAY_SHIFT);
3256 /* Haswell doesn't have any port selection bits for the panel
3257 * power sequencer any more. */
3258 if (IS_VALLEYVIEW(dev)) {
3259 port_sel = I915_READ(pp_on_reg) & 0xc0000000;
3260 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
3261 if (dp_to_dig_port(intel_dp)->port == PORT_A)
3262 port_sel = PANEL_POWER_PORT_DP_A;
3264 port_sel = PANEL_POWER_PORT_DP_D;
3269 I915_WRITE(pp_on_reg, pp_on);
3270 I915_WRITE(pp_off_reg, pp_off);
3271 I915_WRITE(pp_div_reg, pp_div);
3273 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
3274 I915_READ(pp_on_reg),
3275 I915_READ(pp_off_reg),
3276 I915_READ(pp_div_reg));
3279 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
3280 struct intel_connector *intel_connector)
3282 struct drm_connector *connector = &intel_connector->base;
3283 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3284 struct drm_device *dev = intel_dig_port->base.base.dev;
3285 struct drm_i915_private *dev_priv = dev->dev_private;
3286 struct drm_display_mode *fixed_mode = NULL;
3287 struct edp_power_seq power_seq = { 0 };
3289 struct drm_display_mode *scan;
3292 if (!is_edp(intel_dp))
3295 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
3297 /* Cache DPCD and EDID for edp. */
3298 ironlake_edp_panel_vdd_on(intel_dp);
3299 has_dpcd = intel_dp_get_dpcd(intel_dp);
3300 ironlake_edp_panel_vdd_off(intel_dp, false);
3303 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3304 dev_priv->no_aux_handshake =
3305 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3306 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3308 /* if this fails, presume the device is a ghost */
3309 DRM_INFO("failed to retrieve link info, disabling eDP\n");
3313 /* We now know it's not a ghost, init power sequence regs. */
3314 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
3317 ironlake_edp_panel_vdd_on(intel_dp);
3318 edid = drm_get_edid(connector, &intel_dp->adapter);
3320 if (drm_add_edid_modes(connector, edid)) {
3321 drm_mode_connector_update_edid_property(connector,
3323 drm_edid_to_eld(connector, edid);
3326 edid = ERR_PTR(-EINVAL);
3329 edid = ERR_PTR(-ENOENT);
3331 intel_connector->edid = edid;
3333 /* prefer fixed mode from EDID if available */
3334 list_for_each_entry(scan, &connector->probed_modes, head) {
3335 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
3336 fixed_mode = drm_mode_duplicate(dev, scan);
3341 /* fallback to VBT if available for eDP */
3342 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
3343 fixed_mode = drm_mode_duplicate(dev,
3344 dev_priv->vbt.lfp_lvds_vbt_mode);
3346 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
3349 ironlake_edp_panel_vdd_off(intel_dp, false);
3351 intel_panel_init(&intel_connector->panel, fixed_mode);
3352 intel_panel_setup_backlight(connector);
3358 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
3359 struct intel_connector *intel_connector)
3361 struct drm_connector *connector = &intel_connector->base;
3362 struct intel_dp *intel_dp = &intel_dig_port->dp;
3363 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3364 struct drm_device *dev = intel_encoder->base.dev;
3365 struct drm_i915_private *dev_priv = dev->dev_private;
3366 enum port port = intel_dig_port->port;
3367 const char *name = NULL;
3370 /* Preserve the current hw state. */
3371 intel_dp->DP = I915_READ(intel_dp->output_reg);
3372 intel_dp->attached_connector = intel_connector;
3374 type = DRM_MODE_CONNECTOR_DisplayPort;
3376 * FIXME : We need to initialize built-in panels before external panels.
3377 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
3381 type = DRM_MODE_CONNECTOR_eDP;
3384 if (IS_VALLEYVIEW(dev))
3385 type = DRM_MODE_CONNECTOR_eDP;
3388 if (HAS_PCH_SPLIT(dev) && intel_dpd_is_edp(dev))
3389 type = DRM_MODE_CONNECTOR_eDP;
3391 default: /* silence GCC warning */
3396 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
3397 * for DP the encoder type can be set by the caller to
3398 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
3400 if (type == DRM_MODE_CONNECTOR_eDP)
3401 intel_encoder->type = INTEL_OUTPUT_EDP;
3403 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
3404 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
3407 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
3408 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
3410 connector->interlace_allowed = true;
3411 connector->doublescan_allowed = 0;
3413 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
3414 ironlake_panel_vdd_work);
3416 intel_connector_attach_encoder(intel_connector, intel_encoder);
3417 drm_sysfs_connector_add(connector);
3420 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3422 intel_connector->get_hw_state = intel_connector_get_hw_state;
3424 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
3426 switch (intel_dig_port->port) {
3428 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
3431 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
3434 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
3437 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
3444 /* Set up the DDC bus. */
3447 intel_encoder->hpd_pin = HPD_PORT_A;
3451 intel_encoder->hpd_pin = HPD_PORT_B;
3455 intel_encoder->hpd_pin = HPD_PORT_C;
3459 intel_encoder->hpd_pin = HPD_PORT_D;
3466 error = intel_dp_i2c_init(intel_dp, intel_connector, name);
3467 WARN(error, "intel_dp_i2c_init failed with error %d for port %c\n",
3468 error, port_name(port));
3470 intel_dp->psr_setup_done = false;
3472 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
3473 i2c_del_adapter(&intel_dp->adapter);
3474 if (is_edp(intel_dp)) {
3475 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3476 mutex_lock(&dev->mode_config.mutex);
3477 ironlake_panel_vdd_off_sync(intel_dp);
3478 mutex_unlock(&dev->mode_config.mutex);
3480 drm_sysfs_connector_remove(connector);
3481 drm_connector_cleanup(connector);
3485 intel_dp_add_properties(intel_dp, connector);
3487 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3488 * 0xd. Failure to do so will result in spurious interrupts being
3489 * generated on the port when a cable is not attached.
3491 if (IS_G4X(dev) && !IS_GM45(dev)) {
3492 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3493 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3500 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
3502 struct intel_digital_port *intel_dig_port;
3503 struct intel_encoder *intel_encoder;
3504 struct drm_encoder *encoder;
3505 struct intel_connector *intel_connector;
3507 intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
3508 if (!intel_dig_port)
3511 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
3512 if (!intel_connector) {
3513 kfree(intel_dig_port);
3517 intel_encoder = &intel_dig_port->base;
3518 encoder = &intel_encoder->base;
3520 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
3521 DRM_MODE_ENCODER_TMDS);
3523 intel_encoder->compute_config = intel_dp_compute_config;
3524 intel_encoder->mode_set = intel_dp_mode_set;
3525 intel_encoder->enable = intel_enable_dp;
3526 intel_encoder->pre_enable = intel_pre_enable_dp;
3527 intel_encoder->disable = intel_disable_dp;
3528 intel_encoder->post_disable = intel_post_disable_dp;
3529 intel_encoder->get_hw_state = intel_dp_get_hw_state;
3530 intel_encoder->get_config = intel_dp_get_config;
3531 if (IS_VALLEYVIEW(dev))
3532 intel_encoder->pre_pll_enable = intel_dp_pre_pll_enable;
3534 intel_dig_port->port = port;
3535 intel_dig_port->dp.output_reg = output_reg;
3537 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3538 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3539 intel_encoder->cloneable = false;
3540 intel_encoder->hot_plug = intel_dp_hot_plug;
3542 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
3543 drm_encoder_cleanup(encoder);
3544 kfree(intel_dig_port);
3545 kfree(intel_connector);