Pileus Git - ~andy/linux/blob - drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include "drmP.h"
  32 #include "drm.h"
  33 #include "drm_crtc.h"
  34 #include "drm_crtc_helper.h"
  35 #include "drm_edid.h"
  36 #include "intel_drv.h"
  37 #include "i915_drm.h"
  38 #include "i915_drv.h"
  39
  40 #define DP_LINK_STATUS_SIZE     6
  41 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  42
  43 /**
  44  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  45  * @intel_dp: DP struct
  46  *
  47  * If a CPU or PCH DP output is attached to an eDP panel, this function
  48  * will return true, and false otherwise.
  49  */
  50 static bool is_edp(struct intel_dp *intel_dp)
  51 {
  52         return intel_dp->base.type == INTEL_OUTPUT_EDP;
  53 }
  54
  55 /**
  56  * is_pch_edp - is the port on the PCH and attached to an eDP panel?
  57  * @intel_dp: DP struct
  58  *
  59  * Returns true if the given DP struct corresponds to a PCH DP port attached
  60  * to an eDP panel, false otherwise.  Helpful for determining whether we
  61  * may need FDI resources for a given DP output or not.
  62  */
  63 static bool is_pch_edp(struct intel_dp *intel_dp)
  64 {
  65         return intel_dp->is_pch_edp;
  66 }
  67
  68 /**
  69  * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
  70  * @intel_dp: DP struct
  71  *
  72  * Returns true if the given DP struct corresponds to a CPU eDP port.
  73  */
  74 static bool is_cpu_edp(struct intel_dp *intel_dp)
  75 {
  76         return is_edp(intel_dp) && !is_pch_edp(intel_dp);
  77 }
  78
  79 static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
  80 {
  81         return container_of(encoder, struct intel_dp, base.base);
  82 }
  83
  84 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
  85 {
  86         return container_of(intel_attached_encoder(connector),
  87                             struct intel_dp, base);
  88 }
  89
  90 /**
  91  * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
  92  * @encoder: DRM encoder
  93  *
  94  * Return true if @encoder corresponds to a PCH attached eDP panel.  Needed
  95  * by intel_display.c.
  96  */
  97 bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
  98 {
  99         struct intel_dp *intel_dp;
 100
 101         if (!encoder)
 102                 return false;
 103
 104         intel_dp = enc_to_intel_dp(encoder);
 105
 106         return is_pch_edp(intel_dp);
 107 }
 108
 109 static void intel_dp_start_link_train(struct intel_dp *intel_dp);
 110 static void intel_dp_complete_link_train(struct intel_dp *intel_dp);
 111 static void intel_dp_link_down(struct intel_dp *intel_dp);
 112
 113 void
 114 intel_edp_link_config(struct intel_encoder *intel_encoder,
 115                        int *lane_num, int *link_bw)
 116 {
 117         struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
 118
 119         *lane_num = intel_dp->lane_count;
 120         if (intel_dp->link_bw == DP_LINK_BW_1_62)
 121                 *link_bw = 162000;
 122         else if (intel_dp->link_bw == DP_LINK_BW_2_7)
 123                 *link_bw = 270000;
 124 }
 125
 126 int
 127 intel_edp_target_clock(struct intel_encoder *intel_encoder,
 128                        struct drm_display_mode *mode)
 129 {
 130         struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
 131
 132         if (intel_dp->panel_fixed_mode)
 133                 return intel_dp->panel_fixed_mode->clock;
 134         else
 135                 return mode->clock;
 136 }
 137
 138 static int
 139 intel_dp_max_lane_count(struct intel_dp *intel_dp)
 140 {
 141         int max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
 142         switch (max_lane_count) {
 143         case 1: case 2: case 4:
 144                 break;
 145         default:
 146                 max_lane_count = 4;
 147         }
 148         return max_lane_count;
 149 }
 150
 151 static int
 152 intel_dp_max_link_bw(struct intel_dp *intel_dp)
 153 {
 154         int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
 155
 156         switch (max_link_bw) {
 157         case DP_LINK_BW_1_62:
 158         case DP_LINK_BW_2_7:
 159                 break;
 160         default:
 161                 max_link_bw = DP_LINK_BW_1_62;
 162                 break;
 163         }
 164         return max_link_bw;
 165 }
 166
 167 static int
 168 intel_dp_link_clock(uint8_t link_bw)
 169 {
 170         if (link_bw == DP_LINK_BW_2_7)
 171                 return 270000;
 172         else
 173                 return 162000;
 174 }
 175
 176 /*
 177  * The units on the numbers in the next two are... bizarre.  Examples will
 178  * make it clearer; this one parallels an example in the eDP spec.
 179  *
 180  * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
 181  *
 182  *     270000 * 1 * 8 / 10 == 216000
 183  *
 184  * The actual data capacity of that configuration is 2.16Gbit/s, so the
 185  * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 186  * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 187  * 119000.  At 18bpp that's 2142000 kilobits per second.
 188  *
 189  * Thus the strange-looking division by 10 in intel_dp_link_required, to
 190  * get the result in decakilobits instead of kilobits.
 191  */
 192
 193 static int
 194 intel_dp_link_required(int pixel_clock, int bpp)
 195 {
 196         return (pixel_clock * bpp + 9) / 10;
 197 }
 198
 199 static int
 200 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 201 {
 202         return (max_link_clock * max_lanes * 8) / 10;
 203 }
 204
 205 static bool
 206 intel_dp_adjust_dithering(struct intel_dp *intel_dp,
 207                           struct drm_display_mode *mode,
 208                           bool adjust_mode)
 209 {
 210         int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
 211         int max_lanes = intel_dp_max_lane_count(intel_dp);
 212         int max_rate, mode_rate;
 213
 214         mode_rate = intel_dp_link_required(mode->clock, 24);
 215         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 216
 217         if (mode_rate > max_rate) {
 218                 mode_rate = intel_dp_link_required(mode->clock, 18);
 219                 if (mode_rate > max_rate)
 220                         return false;
 221
 222                 if (adjust_mode)
 223                         mode->private_flags
 224                                 |= INTEL_MODE_DP_FORCE_6BPC;
 225
 226                 return true;
 227         }
 228
 229         return true;
 230 }
 231
 232 static int
 233 intel_dp_mode_valid(struct drm_connector *connector,
 234                     struct drm_display_mode *mode)
 235 {
 236         struct intel_dp *intel_dp = intel_attached_dp(connector);
 237
 238         if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
 239                 if (mode->hdisplay > intel_dp->panel_fixed_mode->hdisplay)
 240                         return MODE_PANEL;
 241
 242                 if (mode->vdisplay > intel_dp->panel_fixed_mode->vdisplay)
 243                         return MODE_PANEL;
 244         }
 245
 246         if (!intel_dp_adjust_dithering(intel_dp, mode, false))
 247                 return MODE_CLOCK_HIGH;
 248
 249         if (mode->clock < 10000)
 250                 return MODE_CLOCK_LOW;
 251
 252         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 253                 return MODE_H_ILLEGAL;
 254
 255         return MODE_OK;
 256 }
 257
 258 static uint32_t
 259 pack_aux(uint8_t *src, int src_bytes)
 260 {
 261         int     i;
 262         uint32_t v = 0;
 263
 264         if (src_bytes > 4)
 265                 src_bytes = 4;
 266         for (i = 0; i < src_bytes; i++)
 267                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 268         return v;
 269 }
 270
 271 static void
 272 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 273 {
 274         int i;
 275         if (dst_bytes > 4)
 276                 dst_bytes = 4;
 277         for (i = 0; i < dst_bytes; i++)
 278                 dst[i] = src >> ((3-i) * 8);
 279 }
 280
 281 /* hrawclock is 1/4 the FSB frequency */
 282 static int
 283 intel_hrawclk(struct drm_device *dev)
 284 {
 285         struct drm_i915_private *dev_priv = dev->dev_private;
 286         uint32_t clkcfg;
 287
 288         clkcfg = I915_READ(CLKCFG);
 289         switch (clkcfg & CLKCFG_FSB_MASK) {
 290         case CLKCFG_FSB_400:
 291                 return 100;
 292         case CLKCFG_FSB_533:
 293                 return 133;
 294         case CLKCFG_FSB_667:
 295                 return 166;
 296         case CLKCFG_FSB_800:
 297                 return 200;
 298         case CLKCFG_FSB_1067:
 299                 return 266;
 300         case CLKCFG_FSB_1333:
 301                 return 333;
 302         /* these two are just a guess; one of them might be right */
 303         case CLKCFG_FSB_1600:
 304         case CLKCFG_FSB_1600_ALT:
 305                 return 400;
 306         default:
 307                 return 133;
 308         }
 309 }
 310
 311 static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
 312 {
 313         struct drm_device *dev = intel_dp->base.base.dev;
 314         struct drm_i915_private *dev_priv = dev->dev_private;
 315
 316         return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
 317 }
 318
 319 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
 320 {
 321         struct drm_device *dev = intel_dp->base.base.dev;
 322         struct drm_i915_private *dev_priv = dev->dev_private;
 323
 324         return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
 325 }
 326
 327 static void
 328 intel_dp_check_edp(struct intel_dp *intel_dp)
 329 {
 330         struct drm_device *dev = intel_dp->base.base.dev;
 331         struct drm_i915_private *dev_priv = dev->dev_private;
 332
 333         if (!is_edp(intel_dp))
 334                 return;
 335         if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
 336                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 337                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 338                               I915_READ(PCH_PP_STATUS),
 339                               I915_READ(PCH_PP_CONTROL));
 340         }
 341 }
 342
 343 static int
 344 intel_dp_aux_ch(struct intel_dp *intel_dp,
 345                 uint8_t *send, int send_bytes,
 346                 uint8_t *recv, int recv_size)
 347 {
 348         uint32_t output_reg = intel_dp->output_reg;
 349         struct drm_device *dev = intel_dp->base.base.dev;
 350         struct drm_i915_private *dev_priv = dev->dev_private;
 351         uint32_t ch_ctl = output_reg + 0x10;
 352         uint32_t ch_data = ch_ctl + 4;
 353         int i;
 354         int recv_bytes;
 355         uint32_t status;
 356         uint32_t aux_clock_divider;
 357         int try, precharge;
 358
 359         intel_dp_check_edp(intel_dp);
 360         /* The clock divider is based off the hrawclk,
 361          * and would like to run at 2MHz. So, take the
 362          * hrawclk value and divide by 2 and use that
 363          *
 364          * Note that PCH attached eDP panels should use a 125MHz input
 365          * clock divider.
 366          */
 367         if (is_cpu_edp(intel_dp)) {
 368                 if (IS_GEN6(dev) || IS_GEN7(dev))
 369                         aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
 370                 else
 371                         aux_clock_divider = 225; /* eDP input clock at 450Mhz */
 372         } else if (HAS_PCH_SPLIT(dev))
 373                 aux_clock_divider = 63; /* IRL input clock fixed at 125Mhz */
 374         else
 375                 aux_clock_divider = intel_hrawclk(dev) / 2;
 376
 377         if (IS_GEN6(dev))
 378                 precharge = 3;
 379         else
 380                 precharge = 5;
 381
 382         /* Try to wait for any previous AUX channel activity */
 383         for (try = 0; try < 3; try++) {
 384                 status = I915_READ(ch_ctl);
 385                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 386                         break;
 387                 msleep(1);
 388         }
 389
 390         if (try == 3) {
 391                 WARN(1, "dp_aux_ch not started status 0x%08x\n",
 392                      I915_READ(ch_ctl));
 393                 return -EBUSY;
 394         }
 395
 396         /* Must try at least 3 times according to DP spec */
 397         for (try = 0; try < 5; try++) {
 398                 /* Load the send data into the aux channel data registers */
 399                 for (i = 0; i < send_bytes; i += 4)
 400                         I915_WRITE(ch_data + i,
 401                                    pack_aux(send + i, send_bytes - i));
 402
 403                 /* Send the command and wait for it to complete */
 404                 I915_WRITE(ch_ctl,
 405                            DP_AUX_CH_CTL_SEND_BUSY |
 406                            DP_AUX_CH_CTL_TIME_OUT_400us |
 407                            (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 408                            (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 409                            (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
 410                            DP_AUX_CH_CTL_DONE |
 411                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 412                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 413                 for (;;) {
 414                         status = I915_READ(ch_ctl);
 415                         if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 416                                 break;
 417                         udelay(100);
 418                 }
 419
 420                 /* Clear done status and any errors */
 421                 I915_WRITE(ch_ctl,
 422                            status |
 423                            DP_AUX_CH_CTL_DONE |
 424                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 425                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 426
 427                 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
 428                               DP_AUX_CH_CTL_RECEIVE_ERROR))
 429                         continue;
 430                 if (status & DP_AUX_CH_CTL_DONE)
 431                         break;
 432         }
 433
 434         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 435                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 436                 return -EBUSY;
 437         }
 438
 439         /* Check for timeout or receive error.
 440          * Timeouts occur when the sink is not connected
 441          */
 442         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 443                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 444                 return -EIO;
 445         }
 446
 447         /* Timeouts occur when the device isn't connected, so they're
 448          * "normal" -- don't fill the kernel log with these */
 449         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 450                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 451                 return -ETIMEDOUT;
 452         }
 453
 454         /* Unload any bytes sent back from the other side */
 455         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 456                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 457         if (recv_bytes > recv_size)
 458                 recv_bytes = recv_size;
 459
 460         for (i = 0; i < recv_bytes; i += 4)
 461                 unpack_aux(I915_READ(ch_data + i),
 462                            recv + i, recv_bytes - i);
 463
 464         return recv_bytes;
 465 }
 466
 467 /* Write data to the aux channel in native mode */
 468 static int
 469 intel_dp_aux_native_write(struct intel_dp *intel_dp,
 470                           uint16_t address, uint8_t *send, int send_bytes)
 471 {
 472         int ret;
 473         uint8_t msg[20];
 474         int msg_bytes;
 475         uint8_t ack;
 476
 477         intel_dp_check_edp(intel_dp);
 478         if (send_bytes > 16)
 479                 return -1;
 480         msg[0] = AUX_NATIVE_WRITE << 4;
 481         msg[1] = address >> 8;
 482         msg[2] = address & 0xff;
 483         msg[3] = send_bytes - 1;
 484         memcpy(&msg[4], send, send_bytes);
 485         msg_bytes = send_bytes + 4;
 486         for (;;) {
 487                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
 488                 if (ret < 0)
 489                         return ret;
 490                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
 491                         break;
 492                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 493                         udelay(100);
 494                 else
 495                         return -EIO;
 496         }
 497         return send_bytes;
 498 }
 499
 500 /* Write a single byte to the aux channel in native mode */
 501 static int
 502 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
 503                             uint16_t address, uint8_t byte)
 504 {
 505         return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
 506 }
 507
 508 /* read bytes from a native aux channel */
 509 static int
 510 intel_dp_aux_native_read(struct intel_dp *intel_dp,
 511                          uint16_t address, uint8_t *recv, int recv_bytes)
 512 {
 513         uint8_t msg[4];
 514         int msg_bytes;
 515         uint8_t reply[20];
 516         int reply_bytes;
 517         uint8_t ack;
 518         int ret;
 519
 520         intel_dp_check_edp(intel_dp);
 521         msg[0] = AUX_NATIVE_READ << 4;
 522         msg[1] = address >> 8;
 523         msg[2] = address & 0xff;
 524         msg[3] = recv_bytes - 1;
 525
 526         msg_bytes = 4;
 527         reply_bytes = recv_bytes + 1;
 528
 529         for (;;) {
 530                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
 531                                       reply, reply_bytes);
 532                 if (ret == 0)
 533                         return -EPROTO;
 534                 if (ret < 0)
 535                         return ret;
 536                 ack = reply[0];
 537                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
 538                         memcpy(recv, reply + 1, ret - 1);
 539                         return ret - 1;
 540                 }
 541                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 542                         udelay(100);
 543                 else
 544                         return -EIO;
 545         }
 546 }
 547
 548 static int
 549 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
 550                     uint8_t write_byte, uint8_t *read_byte)
 551 {
 552         struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
 553         struct intel_dp *intel_dp = container_of(adapter,
 554                                                 struct intel_dp,
 555                                                 adapter);
 556         uint16_t address = algo_data->address;
 557         uint8_t msg[5];
 558         uint8_t reply[2];
 559         unsigned retry;
 560         int msg_bytes;
 561         int reply_bytes;
 562         int ret;
 563
 564         intel_dp_check_edp(intel_dp);
 565         /* Set up the command byte */
 566         if (mode & MODE_I2C_READ)
 567                 msg[0] = AUX_I2C_READ << 4;
 568         else
 569                 msg[0] = AUX_I2C_WRITE << 4;
 570
 571         if (!(mode & MODE_I2C_STOP))
 572                 msg[0] |= AUX_I2C_MOT << 4;
 573
 574         msg[1] = address >> 8;
 575         msg[2] = address;
 576
 577         switch (mode) {
 578         case MODE_I2C_WRITE:
 579                 msg[3] = 0;
 580                 msg[4] = write_byte;
 581                 msg_bytes = 5;
 582                 reply_bytes = 1;
 583                 break;
 584         case MODE_I2C_READ:
 585                 msg[3] = 0;
 586                 msg_bytes = 4;
 587                 reply_bytes = 2;
 588                 break;
 589         default:
 590                 msg_bytes = 3;
 591                 reply_bytes = 1;
 592                 break;
 593         }
 594
 595         for (retry = 0; retry < 5; retry++) {
 596                 ret = intel_dp_aux_ch(intel_dp,
 597                                       msg, msg_bytes,
 598                                       reply, reply_bytes);
 599                 if (ret < 0) {
 600                         DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
 601                         return ret;
 602                 }
 603
 604                 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
 605                 case AUX_NATIVE_REPLY_ACK:
 606                         /* I2C-over-AUX Reply field is only valid
 607                          * when paired with AUX ACK.
 608                          */
 609                         break;
 610                 case AUX_NATIVE_REPLY_NACK:
 611                         DRM_DEBUG_KMS("aux_ch native nack\n");
 612                         return -EREMOTEIO;
 613                 case AUX_NATIVE_REPLY_DEFER:
 614                         udelay(100);
 615                         continue;
 616                 default:
 617                         DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
 618                                   reply[0]);
 619                         return -EREMOTEIO;
 620                 }
 621
 622                 switch (reply[0] & AUX_I2C_REPLY_MASK) {
 623                 case AUX_I2C_REPLY_ACK:
 624                         if (mode == MODE_I2C_READ) {
 625                                 *read_byte = reply[1];
 626                         }
 627                         return reply_bytes - 1;
 628                 case AUX_I2C_REPLY_NACK:
 629                         DRM_DEBUG_KMS("aux_i2c nack\n");
 630                         return -EREMOTEIO;
 631                 case AUX_I2C_REPLY_DEFER:
 632                         DRM_DEBUG_KMS("aux_i2c defer\n");
 633                         udelay(100);
 634                         break;
 635                 default:
 636                         DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
 637                         return -EREMOTEIO;
 638                 }
 639         }
 640
 641         DRM_ERROR("too many retries, giving up\n");
 642         return -EREMOTEIO;
 643 }
 644
 645 static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
 646 static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 647
 648 static int
 649 intel_dp_i2c_init(struct intel_dp *intel_dp,
 650                   struct intel_connector *intel_connector, const char *name)
 651 {
 652         int     ret;
 653
 654         DRM_DEBUG_KMS("i2c_init %s\n", name);
 655         intel_dp->algo.running = false;
 656         intel_dp->algo.address = 0;
 657         intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
 658
 659         memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
 660         intel_dp->adapter.owner = THIS_MODULE;
 661         intel_dp->adapter.class = I2C_CLASS_DDC;
 662         strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
 663         intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
 664         intel_dp->adapter.algo_data = &intel_dp->algo;
 665         intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
 666
 667         ironlake_edp_panel_vdd_on(intel_dp);
 668         ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
 669         ironlake_edp_panel_vdd_off(intel_dp, false);
 670         return ret;
 671 }
 672
 673 static bool
 674 intel_dp_mode_fixup(struct drm_encoder *encoder,
 675                     const struct drm_display_mode *mode,
 676                     struct drm_display_mode *adjusted_mode)
 677 {
 678         struct drm_device *dev = encoder->dev;
 679         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 680         int lane_count, clock;
 681         int max_lane_count = intel_dp_max_lane_count(intel_dp);
 682         int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
 683         int bpp, mode_rate;
 684         static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
 685
 686         if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
 687                 intel_fixed_panel_mode(intel_dp->panel_fixed_mode, adjusted_mode);
 688                 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
 689                                         mode, adjusted_mode);
 690         }
 691
 692         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
 693                 return false;
 694
 695         DRM_DEBUG_KMS("DP link computation with max lane count %i "
 696                       "max bw %02x pixel clock %iKHz\n",
 697                       max_lane_count, bws[max_clock], adjusted_mode->clock);
 698
 699         if (!intel_dp_adjust_dithering(intel_dp, adjusted_mode, true))
 700                 return false;
 701
 702         bpp = adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24;
 703         mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
 704
 705         for (clock = 0; clock <= max_clock; clock++) {
 706                 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
 707                         int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
 708
 709                         if (mode_rate <= link_avail) {
 710                                 intel_dp->link_bw = bws[clock];
 711                                 intel_dp->lane_count = lane_count;
 712                                 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
 713                                 DRM_DEBUG_KMS("DP link bw %02x lane "
 714                                                 "count %d clock %d bpp %d\n",
 715                                        intel_dp->link_bw, intel_dp->lane_count,
 716                                        adjusted_mode->clock, bpp);
 717                                 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
 718                                               mode_rate, link_avail);
 719                                 return true;
 720                         }
 721                 }
 722         }
 723
 724         return false;
 725 }
 726
 727 struct intel_dp_m_n {
 728         uint32_t        tu;
 729         uint32_t        gmch_m;
 730         uint32_t        gmch_n;
 731         uint32_t        link_m;
 732         uint32_t        link_n;
 733 };
 734
 735 static void
 736 intel_reduce_ratio(uint32_t *num, uint32_t *den)
 737 {
 738         while (*num > 0xffffff || *den > 0xffffff) {
 739                 *num >>= 1;
 740                 *den >>= 1;
 741         }
 742 }
 743
 744 static void
 745 intel_dp_compute_m_n(int bpp,
 746                      int nlanes,
 747                      int pixel_clock,
 748                      int link_clock,
 749                      struct intel_dp_m_n *m_n)
 750 {
 751         m_n->tu = 64;
 752         m_n->gmch_m = (pixel_clock * bpp) >> 3;
 753         m_n->gmch_n = link_clock * nlanes;
 754         intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
 755         m_n->link_m = pixel_clock;
 756         m_n->link_n = link_clock;
 757         intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
 758 }
 759
 760 void
 761 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
 762                  struct drm_display_mode *adjusted_mode)
 763 {
 764         struct drm_device *dev = crtc->dev;
 765         struct intel_encoder *encoder;
 766         struct drm_i915_private *dev_priv = dev->dev_private;
 767         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 768         int lane_count = 4;
 769         struct intel_dp_m_n m_n;
 770         int pipe = intel_crtc->pipe;
 771
 772         /*
 773          * Find the lane count in the intel_encoder private
 774          */
 775         for_each_encoder_on_crtc(dev, crtc, encoder) {
 776                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 777
 778                 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
 779                     intel_dp->base.type == INTEL_OUTPUT_EDP)
 780                 {
 781                         lane_count = intel_dp->lane_count;
 782                         break;
 783                 }
 784         }
 785
 786         /*
 787          * Compute the GMCH and Link ratios. The '3' here is
 788          * the number of bytes_per_pixel post-LUT, which we always
 789          * set up for 8-bits of R/G/B, or 3 bytes total.
 790          */
 791         intel_dp_compute_m_n(intel_crtc->bpp, lane_count,
 792                              mode->clock, adjusted_mode->clock, &m_n);
 793
 794         if (HAS_PCH_SPLIT(dev)) {
 795                 I915_WRITE(TRANSDATA_M1(pipe),
 796                            ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 797                            m_n.gmch_m);
 798                 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
 799                 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
 800                 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
 801         } else {
 802                 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
 803                            ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 804                            m_n.gmch_m);
 805                 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
 806                 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
 807                 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
 808         }
 809 }
 810
 811 static void ironlake_edp_pll_on(struct drm_encoder *encoder);
 812 static void ironlake_edp_pll_off(struct drm_encoder *encoder);
 813
 814 static void
 815 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
 816                   struct drm_display_mode *adjusted_mode)
 817 {
 818         struct drm_device *dev = encoder->dev;
 819         struct drm_i915_private *dev_priv = dev->dev_private;
 820         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 821         struct drm_crtc *crtc = intel_dp->base.base.crtc;
 822         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 823
 824         /* Turn on the eDP PLL if needed */
 825         if (is_edp(intel_dp)) {
 826                 if (!is_pch_edp(intel_dp))
 827                         ironlake_edp_pll_on(encoder);
 828                 else
 829                         ironlake_edp_pll_off(encoder);
 830         }
 831
 832         /*
 833          * There are four kinds of DP registers:
 834          *
 835          *      IBX PCH
 836          *      SNB CPU
 837          *      IVB CPU
 838          *      CPT PCH
 839          *
 840          * IBX PCH and CPU are the same for almost everything,
 841          * except that the CPU DP PLL is configured in this
 842          * register
 843          *
 844          * CPT PCH is quite different, having many bits moved
 845          * to the TRANS_DP_CTL register instead. That
 846          * configuration happens (oddly) in ironlake_pch_enable
 847          */
 848
 849         /* Preserve the BIOS-computed detected bit. This is
 850          * supposed to be read-only.
 851          */
 852         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 853         intel_dp->DP |=  DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 854
 855         /* Handle DP bits in common between all three register formats */
 856
 857         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 858
 859         switch (intel_dp->lane_count) {
 860         case 1:
 861                 intel_dp->DP |= DP_PORT_WIDTH_1;
 862                 break;
 863         case 2:
 864                 intel_dp->DP |= DP_PORT_WIDTH_2;
 865                 break;
 866         case 4:
 867                 intel_dp->DP |= DP_PORT_WIDTH_4;
 868                 break;
 869         }
 870         if (intel_dp->has_audio) {
 871                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
 872                                  pipe_name(intel_crtc->pipe));
 873                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
 874                 intel_write_eld(encoder, adjusted_mode);
 875         }
 876         memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
 877         intel_dp->link_configuration[0] = intel_dp->link_bw;
 878         intel_dp->link_configuration[1] = intel_dp->lane_count;
 879         intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
 880         /*
 881          * Check for DPCD version > 1.1 and enhanced framing support
 882          */
 883         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
 884             (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
 885                 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 886         }
 887
 888         /* Split out the IBX/CPU vs CPT settings */
 889
 890         if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
 891                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 892                         intel_dp->DP |= DP_SYNC_HS_HIGH;
 893                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 894                         intel_dp->DP |= DP_SYNC_VS_HIGH;
 895                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 896
 897                 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
 898                         intel_dp->DP |= DP_ENHANCED_FRAMING;
 899
 900                 intel_dp->DP |= intel_crtc->pipe << 29;
 901
 902                 /* don't miss out required setting for eDP */
 903                 intel_dp->DP |= DP_PLL_ENABLE;
 904                 if (adjusted_mode->clock < 200000)
 905                         intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 906                 else
 907                         intel_dp->DP |= DP_PLL_FREQ_270MHZ;
 908         } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
 909                 intel_dp->DP |= intel_dp->color_range;
 910
 911                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 912                         intel_dp->DP |= DP_SYNC_HS_HIGH;
 913                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 914                         intel_dp->DP |= DP_SYNC_VS_HIGH;
 915                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
 916
 917                 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
 918                         intel_dp->DP |= DP_ENHANCED_FRAMING;
 919
 920                 if (intel_crtc->pipe == 1)
 921                         intel_dp->DP |= DP_PIPEB_SELECT;
 922
 923                 if (is_cpu_edp(intel_dp)) {
 924                         /* don't miss out required setting for eDP */
 925                         intel_dp->DP |= DP_PLL_ENABLE;
 926                         if (adjusted_mode->clock < 200000)
 927                                 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 928                         else
 929                                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
 930                 }
 931         } else {
 932                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 933         }
 934 }
 935
 936 #define IDLE_ON_MASK            (PP_ON | 0        | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
 937 #define IDLE_ON_VALUE           (PP_ON | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
 938
 939 #define IDLE_OFF_MASK           (PP_ON | 0        | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
 940 #define IDLE_OFF_VALUE          (0     | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
 941
 942 #define IDLE_CYCLE_MASK         (PP_ON | 0        | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
 943 #define IDLE_CYCLE_VALUE        (0     | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
 944
 945 static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
 946                                        u32 mask,
 947                                        u32 value)
 948 {
 949         struct drm_device *dev = intel_dp->base.base.dev;
 950         struct drm_i915_private *dev_priv = dev->dev_private;
 951
 952         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
 953                       mask, value,
 954                       I915_READ(PCH_PP_STATUS),
 955                       I915_READ(PCH_PP_CONTROL));
 956
 957         if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
 958                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
 959                           I915_READ(PCH_PP_STATUS),
 960                           I915_READ(PCH_PP_CONTROL));
 961         }
 962 }
 963
 964 static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
 965 {
 966         DRM_DEBUG_KMS("Wait for panel power on\n");
 967         ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
 968 }
 969
 970 static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
 971 {
 972         DRM_DEBUG_KMS("Wait for panel power off time\n");
 973         ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
 974 }
 975
 976 static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
 977 {
 978         DRM_DEBUG_KMS("Wait for panel power cycle\n");
 979         ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
 980 }
 981
 982
 983 /* Read the current pp_control value, unlocking the register if it
 984  * is locked
 985  */
 986
 987 static  u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
 988 {
 989         u32     control = I915_READ(PCH_PP_CONTROL);
 990
 991         control &= ~PANEL_UNLOCK_MASK;
 992         control |= PANEL_UNLOCK_REGS;
 993         return control;
 994 }
 995
 996 static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
 997 {
 998         struct drm_device *dev = intel_dp->base.base.dev;
 999         struct drm_i915_private *dev_priv = dev->dev_private;
1000         u32 pp;
1001
1002         if (!is_edp(intel_dp))
1003                 return;
1004         DRM_DEBUG_KMS("Turn eDP VDD on\n");
1005
1006         WARN(intel_dp->want_panel_vdd,
1007              "eDP VDD already requested on\n");
1008
1009         intel_dp->want_panel_vdd = true;
1010
1011         if (ironlake_edp_have_panel_vdd(intel_dp)) {
1012                 DRM_DEBUG_KMS("eDP VDD already on\n");
1013                 return;
1014         }
1015
1016         if (!ironlake_edp_have_panel_power(intel_dp))
1017                 ironlake_wait_panel_power_cycle(intel_dp);
1018
1019         pp = ironlake_get_pp_control(dev_priv);
1020         pp |= EDP_FORCE_VDD;
1021         I915_WRITE(PCH_PP_CONTROL, pp);
1022         POSTING_READ(PCH_PP_CONTROL);
1023         DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1024                       I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
1025
1026         /*
1027          * If the panel wasn't on, delay before accessing aux channel
1028          */
1029         if (!ironlake_edp_have_panel_power(intel_dp)) {
1030                 DRM_DEBUG_KMS("eDP was not running\n");
1031                 msleep(intel_dp->panel_power_up_delay);
1032         }
1033 }
1034
1035 static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
1036 {
1037         struct drm_device *dev = intel_dp->base.base.dev;
1038         struct drm_i915_private *dev_priv = dev->dev_private;
1039         u32 pp;
1040
1041         if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
1042                 pp = ironlake_get_pp_control(dev_priv);
1043                 pp &= ~EDP_FORCE_VDD;
1044                 I915_WRITE(PCH_PP_CONTROL, pp);
1045                 POSTING_READ(PCH_PP_CONTROL);
1046
1047                 /* Make sure sequencer is idle before allowing subsequent activity */
1048                 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1049                               I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
1050
1051                 msleep(intel_dp->panel_power_down_delay);
1052         }
1053 }
1054
1055 static void ironlake_panel_vdd_work(struct work_struct *__work)
1056 {
1057         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1058                                                  struct intel_dp, panel_vdd_work);
1059         struct drm_device *dev = intel_dp->base.base.dev;
1060
1061         mutex_lock(&dev->mode_config.mutex);
1062         ironlake_panel_vdd_off_sync(intel_dp);
1063         mutex_unlock(&dev->mode_config.mutex);
1064 }
1065
1066 static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1067 {
1068         if (!is_edp(intel_dp))
1069                 return;
1070
1071         DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1072         WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1073
1074         intel_dp->want_panel_vdd = false;
1075
1076         if (sync) {
1077                 ironlake_panel_vdd_off_sync(intel_dp);
1078         } else {
1079                 /*
1080                  * Queue the timer to fire a long
1081                  * time from now (relative to the power down delay)
1082                  * to keep the panel power up across a sequence of operations
1083                  */
1084                 schedule_delayed_work(&intel_dp->panel_vdd_work,
1085                                       msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1086         }
1087 }
1088
1089 static void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1090 {
1091         struct drm_device *dev = intel_dp->base.base.dev;
1092         struct drm_i915_private *dev_priv = dev->dev_private;
1093         u32 pp;
1094
1095         if (!is_edp(intel_dp))
1096                 return;
1097
1098         DRM_DEBUG_KMS("Turn eDP power on\n");
1099
1100         if (ironlake_edp_have_panel_power(intel_dp)) {
1101                 DRM_DEBUG_KMS("eDP power already on\n");
1102                 return;
1103         }
1104
1105         ironlake_wait_panel_power_cycle(intel_dp);
1106
1107         pp = ironlake_get_pp_control(dev_priv);
1108         if (IS_GEN5(dev)) {
1109                 /* ILK workaround: disable reset around power sequence */
1110                 pp &= ~PANEL_POWER_RESET;
1111                 I915_WRITE(PCH_PP_CONTROL, pp);
1112                 POSTING_READ(PCH_PP_CONTROL);
1113         }
1114
1115         pp |= POWER_TARGET_ON;
1116         if (!IS_GEN5(dev))
1117                 pp |= PANEL_POWER_RESET;
1118
1119         I915_WRITE(PCH_PP_CONTROL, pp);
1120         POSTING_READ(PCH_PP_CONTROL);
1121
1122         ironlake_wait_panel_on(intel_dp);
1123
1124         if (IS_GEN5(dev)) {
1125                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1126                 I915_WRITE(PCH_PP_CONTROL, pp);
1127                 POSTING_READ(PCH_PP_CONTROL);
1128         }
1129 }
1130
1131 static void ironlake_edp_panel_off(struct intel_dp *intel_dp)
1132 {
1133         struct drm_device *dev = intel_dp->base.base.dev;
1134         struct drm_i915_private *dev_priv = dev->dev_private;
1135         u32 pp;
1136
1137         if (!is_edp(intel_dp))
1138                 return;
1139
1140         DRM_DEBUG_KMS("Turn eDP power off\n");
1141
1142         WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1143
1144         pp = ironlake_get_pp_control(dev_priv);
1145         pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1146         I915_WRITE(PCH_PP_CONTROL, pp);
1147         POSTING_READ(PCH_PP_CONTROL);
1148
1149         ironlake_wait_panel_off(intel_dp);
1150 }
1151
1152 static void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1153 {
1154         struct drm_device *dev = intel_dp->base.base.dev;
1155         struct drm_i915_private *dev_priv = dev->dev_private;
1156         u32 pp;
1157
1158         if (!is_edp(intel_dp))
1159                 return;
1160
1161         DRM_DEBUG_KMS("\n");
1162         /*
1163          * If we enable the backlight right away following a panel power
1164          * on, we may see slight flicker as the panel syncs with the eDP
1165          * link.  So delay a bit to make sure the image is solid before
1166          * allowing it to appear.
1167          */
1168         msleep(intel_dp->backlight_on_delay);
1169         pp = ironlake_get_pp_control(dev_priv);
1170         pp |= EDP_BLC_ENABLE;
1171         I915_WRITE(PCH_PP_CONTROL, pp);
1172         POSTING_READ(PCH_PP_CONTROL);
1173 }
1174
1175 static void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1176 {
1177         struct drm_device *dev = intel_dp->base.base.dev;
1178         struct drm_i915_private *dev_priv = dev->dev_private;
1179         u32 pp;
1180
1181         if (!is_edp(intel_dp))
1182                 return;
1183
1184         DRM_DEBUG_KMS("\n");
1185         pp = ironlake_get_pp_control(dev_priv);
1186         pp &= ~EDP_BLC_ENABLE;
1187         I915_WRITE(PCH_PP_CONTROL, pp);
1188         POSTING_READ(PCH_PP_CONTROL);
1189         msleep(intel_dp->backlight_off_delay);
1190 }
1191
1192 static void ironlake_edp_pll_on(struct drm_encoder *encoder)
1193 {
1194         struct drm_device *dev = encoder->dev;
1195         struct drm_i915_private *dev_priv = dev->dev_private;
1196         u32 dpa_ctl;
1197
1198         DRM_DEBUG_KMS("\n");
1199         dpa_ctl = I915_READ(DP_A);
1200         dpa_ctl |= DP_PLL_ENABLE;
1201         I915_WRITE(DP_A, dpa_ctl);
1202         POSTING_READ(DP_A);
1203         udelay(200);
1204 }
1205
1206 static void ironlake_edp_pll_off(struct drm_encoder *encoder)
1207 {
1208         struct drm_device *dev = encoder->dev;
1209         struct drm_i915_private *dev_priv = dev->dev_private;
1210         u32 dpa_ctl;
1211
1212         dpa_ctl = I915_READ(DP_A);
1213         dpa_ctl &= ~DP_PLL_ENABLE;
1214         I915_WRITE(DP_A, dpa_ctl);
1215         POSTING_READ(DP_A);
1216         udelay(200);
1217 }
1218
1219 /* If the sink supports it, try to set the power state appropriately */
1220 static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1221 {
1222         int ret, i;
1223
1224         /* Should have a valid DPCD by this point */
1225         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1226                 return;
1227
1228         if (mode != DRM_MODE_DPMS_ON) {
1229                 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1230                                                   DP_SET_POWER_D3);
1231                 if (ret != 1)
1232                         DRM_DEBUG_DRIVER("failed to write sink power state\n");
1233         } else {
1234                 /*
1235                  * When turning on, we need to retry for 1ms to give the sink
1236                  * time to wake up.
1237                  */
1238                 for (i = 0; i < 3; i++) {
1239                         ret = intel_dp_aux_native_write_1(intel_dp,
1240                                                           DP_SET_POWER,
1241                                                           DP_SET_POWER_D0);
1242                         if (ret == 1)
1243                                 break;
1244                         msleep(1);
1245                 }
1246         }
1247 }
1248
1249 static void intel_dp_prepare(struct drm_encoder *encoder)
1250 {
1251         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1252
1253
1254         /* Make sure the panel is off before trying to change the mode. But also
1255          * ensure that we have vdd while we switch off the panel. */
1256         ironlake_edp_panel_vdd_on(intel_dp);
1257         ironlake_edp_backlight_off(intel_dp);
1258         ironlake_edp_panel_off(intel_dp);
1259
1260         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1261         intel_dp_link_down(intel_dp);
1262         ironlake_edp_panel_vdd_off(intel_dp, false);
1263 }
1264
1265 static void intel_dp_commit(struct drm_encoder *encoder)
1266 {
1267         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1268         struct drm_device *dev = encoder->dev;
1269         struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
1270
1271         ironlake_edp_panel_vdd_on(intel_dp);
1272         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1273         intel_dp_start_link_train(intel_dp);
1274         ironlake_edp_panel_on(intel_dp);
1275         ironlake_edp_panel_vdd_off(intel_dp, true);
1276         intel_dp_complete_link_train(intel_dp);
1277         ironlake_edp_backlight_on(intel_dp);
1278
1279         intel_dp->dpms_mode = DRM_MODE_DPMS_ON;
1280
1281         if (HAS_PCH_CPT(dev))
1282                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
1283 }
1284
1285 static void
1286 intel_dp_dpms(struct drm_encoder *encoder, int mode)
1287 {
1288         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1289         struct drm_device *dev = encoder->dev;
1290         struct drm_i915_private *dev_priv = dev->dev_private;
1291         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1292
1293         if (mode != DRM_MODE_DPMS_ON) {
1294                 /* Switching the panel off requires vdd. */
1295                 ironlake_edp_panel_vdd_on(intel_dp);
1296                 ironlake_edp_backlight_off(intel_dp);
1297                 ironlake_edp_panel_off(intel_dp);
1298
1299                 intel_dp_sink_dpms(intel_dp, mode);
1300                 intel_dp_link_down(intel_dp);
1301                 ironlake_edp_panel_vdd_off(intel_dp, false);
1302
1303                 if (is_cpu_edp(intel_dp))
1304                         ironlake_edp_pll_off(encoder);
1305         } else {
1306                 if (is_cpu_edp(intel_dp))
1307                         ironlake_edp_pll_on(encoder);
1308
1309                 ironlake_edp_panel_vdd_on(intel_dp);
1310                 intel_dp_sink_dpms(intel_dp, mode);
1311                 if (!(dp_reg & DP_PORT_EN)) {
1312                         intel_dp_start_link_train(intel_dp);
1313                         ironlake_edp_panel_on(intel_dp);
1314                         ironlake_edp_panel_vdd_off(intel_dp, true);
1315                         intel_dp_complete_link_train(intel_dp);
1316                 } else
1317                         ironlake_edp_panel_vdd_off(intel_dp, false);
1318                 ironlake_edp_backlight_on(intel_dp);
1319         }
1320         intel_dp->dpms_mode = mode;
1321 }
1322
1323 /*
1324  * Native read with retry for link status and receiver capability reads for
1325  * cases where the sink may still be asleep.
1326  */
1327 static bool
1328 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1329                                uint8_t *recv, int recv_bytes)
1330 {
1331         int ret, i;
1332
1333         /*
1334          * Sinks are *supposed* to come up within 1ms from an off state,
1335          * but we're also supposed to retry 3 times per the spec.
1336          */
1337         for (i = 0; i < 3; i++) {
1338                 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1339                                                recv_bytes);
1340                 if (ret == recv_bytes)
1341                         return true;
1342                 msleep(1);
1343         }
1344
1345         return false;
1346 }
1347
1348 /*
1349  * Fetch AUX CH registers 0x202 - 0x207 which contain
1350  * link status information
1351  */
1352 static bool
1353 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1354 {
1355         return intel_dp_aux_native_read_retry(intel_dp,
1356                                               DP_LANE0_1_STATUS,
1357                                               link_status,
1358                                               DP_LINK_STATUS_SIZE);
1359 }
1360
1361 static uint8_t
1362 intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1363                      int r)
1364 {
1365         return link_status[r - DP_LANE0_1_STATUS];
1366 }
1367
1368 static uint8_t
1369 intel_get_adjust_request_voltage(uint8_t adjust_request[2],
1370                                  int lane)
1371 {
1372         int         s = ((lane & 1) ?
1373                          DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
1374                          DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
1375         uint8_t l = adjust_request[lane>>1];
1376
1377         return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
1378 }
1379
1380 static uint8_t
1381 intel_get_adjust_request_pre_emphasis(uint8_t adjust_request[2],
1382                                       int lane)
1383 {
1384         int         s = ((lane & 1) ?
1385                          DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
1386                          DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
1387         uint8_t l = adjust_request[lane>>1];
1388
1389         return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
1390 }
1391
1392
1393 #if 0
1394 static char     *voltage_names[] = {
1395         "0.4V", "0.6V", "0.8V", "1.2V"
1396 };
1397 static char     *pre_emph_names[] = {
1398         "0dB", "3.5dB", "6dB", "9.5dB"
1399 };
1400 static char     *link_train_names[] = {
1401         "pattern 1", "pattern 2", "idle", "off"
1402 };
1403 #endif
1404
1405 /*
1406  * These are source-specific values; current Intel hardware supports
1407  * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1408  */
1409
1410 static uint8_t
1411 intel_dp_voltage_max(struct intel_dp *intel_dp)
1412 {
1413         struct drm_device *dev = intel_dp->base.base.dev;
1414
1415         if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
1416                 return DP_TRAIN_VOLTAGE_SWING_800;
1417         else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1418                 return DP_TRAIN_VOLTAGE_SWING_1200;
1419         else
1420                 return DP_TRAIN_VOLTAGE_SWING_800;
1421 }
1422
1423 static uint8_t
1424 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1425 {
1426         struct drm_device *dev = intel_dp->base.base.dev;
1427
1428         if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1429                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1430                 case DP_TRAIN_VOLTAGE_SWING_400:
1431                         return DP_TRAIN_PRE_EMPHASIS_6;
1432                 case DP_TRAIN_VOLTAGE_SWING_600:
1433                 case DP_TRAIN_VOLTAGE_SWING_800:
1434                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1435                 default:
1436                         return DP_TRAIN_PRE_EMPHASIS_0;
1437                 }
1438         } else {
1439                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1440                 case DP_TRAIN_VOLTAGE_SWING_400:
1441                         return DP_TRAIN_PRE_EMPHASIS_6;
1442                 case DP_TRAIN_VOLTAGE_SWING_600:
1443                         return DP_TRAIN_PRE_EMPHASIS_6;
1444                 case DP_TRAIN_VOLTAGE_SWING_800:
1445                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1446                 case DP_TRAIN_VOLTAGE_SWING_1200:
1447                 default:
1448                         return DP_TRAIN_PRE_EMPHASIS_0;
1449                 }
1450         }
1451 }
1452
1453 static void
1454 intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1455 {
1456         uint8_t v = 0;
1457         uint8_t p = 0;
1458         int lane;
1459         uint8_t *adjust_request = link_status + (DP_ADJUST_REQUEST_LANE0_1 - DP_LANE0_1_STATUS);
1460         uint8_t voltage_max;
1461         uint8_t preemph_max;
1462
1463         for (lane = 0; lane < intel_dp->lane_count; lane++) {
1464                 uint8_t this_v = intel_get_adjust_request_voltage(adjust_request, lane);
1465                 uint8_t this_p = intel_get_adjust_request_pre_emphasis(adjust_request, lane);
1466
1467                 if (this_v > v)
1468                         v = this_v;
1469                 if (this_p > p)
1470                         p = this_p;
1471         }
1472
1473         voltage_max = intel_dp_voltage_max(intel_dp);
1474         if (v >= voltage_max)
1475                 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
1476
1477         preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1478         if (p >= preemph_max)
1479                 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1480
1481         for (lane = 0; lane < 4; lane++)
1482                 intel_dp->train_set[lane] = v | p;
1483 }
1484
1485 static uint32_t
1486 intel_dp_signal_levels(uint8_t train_set)
1487 {
1488         uint32_t        signal_levels = 0;
1489
1490         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1491         case DP_TRAIN_VOLTAGE_SWING_400:
1492         default:
1493                 signal_levels |= DP_VOLTAGE_0_4;
1494                 break;
1495         case DP_TRAIN_VOLTAGE_SWING_600:
1496                 signal_levels |= DP_VOLTAGE_0_6;
1497                 break;
1498         case DP_TRAIN_VOLTAGE_SWING_800:
1499                 signal_levels |= DP_VOLTAGE_0_8;
1500                 break;
1501         case DP_TRAIN_VOLTAGE_SWING_1200:
1502                 signal_levels |= DP_VOLTAGE_1_2;
1503                 break;
1504         }
1505         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1506         case DP_TRAIN_PRE_EMPHASIS_0:
1507         default:
1508                 signal_levels |= DP_PRE_EMPHASIS_0;
1509                 break;
1510         case DP_TRAIN_PRE_EMPHASIS_3_5:
1511                 signal_levels |= DP_PRE_EMPHASIS_3_5;
1512                 break;
1513         case DP_TRAIN_PRE_EMPHASIS_6:
1514                 signal_levels |= DP_PRE_EMPHASIS_6;
1515                 break;
1516         case DP_TRAIN_PRE_EMPHASIS_9_5:
1517                 signal_levels |= DP_PRE_EMPHASIS_9_5;
1518                 break;
1519         }
1520         return signal_levels;
1521 }
1522
1523 /* Gen6's DP voltage swing and pre-emphasis control */
1524 static uint32_t
1525 intel_gen6_edp_signal_levels(uint8_t train_set)
1526 {
1527         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1528                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1529         switch (signal_levels) {
1530         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1531         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1532                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1533         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1534                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1535         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1536         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1537                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1538         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1539         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1540                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1541         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1542         case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1543                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1544         default:
1545                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1546                               "0x%x\n", signal_levels);
1547                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1548         }
1549 }
1550
1551 /* Gen7's DP voltage swing and pre-emphasis control */
1552 static uint32_t
1553 intel_gen7_edp_signal_levels(uint8_t train_set)
1554 {
1555         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1556                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1557         switch (signal_levels) {
1558         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1559                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1560         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1561                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1562         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1563                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1564
1565         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1566                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1567         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1568                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1569
1570         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1571                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1572         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1573                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1574
1575         default:
1576                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1577                               "0x%x\n", signal_levels);
1578                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1579         }
1580 }
1581
1582 static uint8_t
1583 intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1584                       int lane)
1585 {
1586         int s = (lane & 1) * 4;
1587         uint8_t l = link_status[lane>>1];
1588
1589         return (l >> s) & 0xf;
1590 }
1591
1592 /* Check for clock recovery is done on all channels */
1593 static bool
1594 intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1595 {
1596         int lane;
1597         uint8_t lane_status;
1598
1599         for (lane = 0; lane < lane_count; lane++) {
1600                 lane_status = intel_get_lane_status(link_status, lane);
1601                 if ((lane_status & DP_LANE_CR_DONE) == 0)
1602                         return false;
1603         }
1604         return true;
1605 }
1606
1607 /* Check to see if channel eq is done on all channels */
1608 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1609                          DP_LANE_CHANNEL_EQ_DONE|\
1610                          DP_LANE_SYMBOL_LOCKED)
1611 static bool
1612 intel_channel_eq_ok(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1613 {
1614         uint8_t lane_align;
1615         uint8_t lane_status;
1616         int lane;
1617
1618         lane_align = intel_dp_link_status(link_status,
1619                                           DP_LANE_ALIGN_STATUS_UPDATED);
1620         if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
1621                 return false;
1622         for (lane = 0; lane < intel_dp->lane_count; lane++) {
1623                 lane_status = intel_get_lane_status(link_status, lane);
1624                 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
1625                         return false;
1626         }
1627         return true;
1628 }
1629
1630 static bool
1631 intel_dp_set_link_train(struct intel_dp *intel_dp,
1632                         uint32_t dp_reg_value,
1633                         uint8_t dp_train_pat)
1634 {
1635         struct drm_device *dev = intel_dp->base.base.dev;
1636         struct drm_i915_private *dev_priv = dev->dev_private;
1637         int ret;
1638
1639         I915_WRITE(intel_dp->output_reg, dp_reg_value);
1640         POSTING_READ(intel_dp->output_reg);
1641
1642         intel_dp_aux_native_write_1(intel_dp,
1643                                     DP_TRAINING_PATTERN_SET,
1644                                     dp_train_pat);
1645
1646         ret = intel_dp_aux_native_write(intel_dp,
1647                                         DP_TRAINING_LANE0_SET,
1648                                         intel_dp->train_set,
1649                                         intel_dp->lane_count);
1650         if (ret != intel_dp->lane_count)
1651                 return false;
1652
1653         return true;
1654 }
1655
1656 /* Enable corresponding port and start training pattern 1 */
1657 static void
1658 intel_dp_start_link_train(struct intel_dp *intel_dp)
1659 {
1660         struct drm_device *dev = intel_dp->base.base.dev;
1661         struct drm_i915_private *dev_priv = dev->dev_private;
1662         struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
1663         int i;
1664         uint8_t voltage;
1665         bool clock_recovery = false;
1666         int voltage_tries, loop_tries;
1667         u32 reg;
1668         uint32_t DP = intel_dp->DP;
1669
1670         /*
1671          * On CPT we have to enable the port in training pattern 1, which
1672          * will happen below in intel_dp_set_link_train.  Otherwise, enable
1673          * the port and wait for it to become active.
1674          */
1675         if (!HAS_PCH_CPT(dev)) {
1676                 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
1677                 POSTING_READ(intel_dp->output_reg);
1678                 intel_wait_for_vblank(dev, intel_crtc->pipe);
1679         }
1680
1681         /* Write the link configuration data */
1682         intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1683                                   intel_dp->link_configuration,
1684                                   DP_LINK_CONFIGURATION_SIZE);
1685
1686         DP |= DP_PORT_EN;
1687
1688         if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
1689                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1690         else
1691                 DP &= ~DP_LINK_TRAIN_MASK;
1692         memset(intel_dp->train_set, 0, 4);
1693         voltage = 0xff;
1694         voltage_tries = 0;
1695         loop_tries = 0;
1696         clock_recovery = false;
1697         for (;;) {
1698                 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1699                 uint8_t     link_status[DP_LINK_STATUS_SIZE];
1700                 uint32_t    signal_levels;
1701
1702
1703                 if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1704                         signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1705                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1706                 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1707                         signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1708                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1709                 } else {
1710                         signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
1711                         DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n", signal_levels);
1712                         DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1713                 }
1714
1715                 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
1716                         reg = DP | DP_LINK_TRAIN_PAT_1_CPT;
1717                 else
1718                         reg = DP | DP_LINK_TRAIN_PAT_1;
1719
1720                 if (!intel_dp_set_link_train(intel_dp, reg,
1721                                              DP_TRAINING_PATTERN_1 |
1722                                              DP_LINK_SCRAMBLING_DISABLE))
1723                         break;
1724                 /* Set training pattern 1 */
1725
1726                 udelay(100);
1727                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
1728                         DRM_ERROR("failed to get link status\n");
1729                         break;
1730                 }
1731
1732                 if (intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1733                         DRM_DEBUG_KMS("clock recovery OK\n");
1734                         clock_recovery = true;
1735                         break;
1736                 }
1737
1738                 /* Check to see if we've tried the max voltage */
1739                 for (i = 0; i < intel_dp->lane_count; i++)
1740                         if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1741                                 break;
1742                 if (i == intel_dp->lane_count && voltage_tries == 5) {
1743                         ++loop_tries;
1744                         if (loop_tries == 5) {
1745                                 DRM_DEBUG_KMS("too many full retries, give up\n");
1746                                 break;
1747                         }
1748                         memset(intel_dp->train_set, 0, 4);
1749                         voltage_tries = 0;
1750                         continue;
1751                 }
1752
1753                 /* Check to see if we've tried the same voltage 5 times */
1754                 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1755                         ++voltage_tries;
1756                         if (voltage_tries == 5) {
1757                                 DRM_DEBUG_KMS("too many voltage retries, give up\n");
1758                                 break;
1759                         }
1760                 } else
1761                         voltage_tries = 0;
1762                 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1763
1764                 /* Compute new intel_dp->train_set as requested by target */
1765                 intel_get_adjust_train(intel_dp, link_status);
1766         }
1767
1768         intel_dp->DP = DP;
1769 }
1770
1771 static void
1772 intel_dp_complete_link_train(struct intel_dp *intel_dp)
1773 {
1774         struct drm_device *dev = intel_dp->base.base.dev;
1775         struct drm_i915_private *dev_priv = dev->dev_private;
1776         bool channel_eq = false;
1777         int tries, cr_tries;
1778         u32 reg;
1779         uint32_t DP = intel_dp->DP;
1780
1781         /* channel equalization */
1782         tries = 0;
1783         cr_tries = 0;
1784         channel_eq = false;
1785         for (;;) {
1786                 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1787                 uint32_t    signal_levels;
1788                 uint8_t     link_status[DP_LINK_STATUS_SIZE];
1789
1790                 if (cr_tries > 5) {
1791                         DRM_ERROR("failed to train DP, aborting\n");
1792                         intel_dp_link_down(intel_dp);
1793                         break;
1794                 }
1795
1796                 if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1797                         signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1798                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1799                 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1800                         signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1801                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1802                 } else {
1803                         signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
1804                         DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1805                 }
1806
1807                 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
1808                         reg = DP | DP_LINK_TRAIN_PAT_2_CPT;
1809                 else
1810                         reg = DP | DP_LINK_TRAIN_PAT_2;
1811
1812                 /* channel eq pattern */
1813                 if (!intel_dp_set_link_train(intel_dp, reg,
1814                                              DP_TRAINING_PATTERN_2 |
1815                                              DP_LINK_SCRAMBLING_DISABLE))
1816                         break;
1817
1818                 udelay(400);
1819                 if (!intel_dp_get_link_status(intel_dp, link_status))
1820                         break;
1821
1822                 /* Make sure clock is still ok */
1823                 if (!intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1824                         intel_dp_start_link_train(intel_dp);
1825                         cr_tries++;
1826                         continue;
1827                 }
1828
1829                 if (intel_channel_eq_ok(intel_dp, link_status)) {
1830                         channel_eq = true;
1831                         break;
1832                 }
1833
1834                 /* Try 5 times, then try clock recovery if that fails */
1835                 if (tries > 5) {
1836                         intel_dp_link_down(intel_dp);
1837                         intel_dp_start_link_train(intel_dp);
1838                         tries = 0;
1839                         cr_tries++;
1840                         continue;
1841                 }
1842
1843                 /* Compute new intel_dp->train_set as requested by target */
1844                 intel_get_adjust_train(intel_dp, link_status);
1845                 ++tries;
1846         }
1847
1848         if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
1849                 reg = DP | DP_LINK_TRAIN_OFF_CPT;
1850         else
1851                 reg = DP | DP_LINK_TRAIN_OFF;
1852
1853         I915_WRITE(intel_dp->output_reg, reg);
1854         POSTING_READ(intel_dp->output_reg);
1855         intel_dp_aux_native_write_1(intel_dp,
1856                                     DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1857 }
1858
1859 static void
1860 intel_dp_link_down(struct intel_dp *intel_dp)
1861 {
1862         struct drm_device *dev = intel_dp->base.base.dev;
1863         struct drm_i915_private *dev_priv = dev->dev_private;
1864         uint32_t DP = intel_dp->DP;
1865
1866         if ((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)
1867                 return;
1868
1869         DRM_DEBUG_KMS("\n");
1870
1871         if (is_edp(intel_dp)) {
1872                 DP &= ~DP_PLL_ENABLE;
1873                 I915_WRITE(intel_dp->output_reg, DP);
1874                 POSTING_READ(intel_dp->output_reg);
1875                 udelay(100);
1876         }
1877
1878         if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
1879                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1880                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
1881         } else {
1882                 DP &= ~DP_LINK_TRAIN_MASK;
1883                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1884         }
1885         POSTING_READ(intel_dp->output_reg);
1886
1887         msleep(17);
1888
1889         if (is_edp(intel_dp)) {
1890                 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
1891                         DP |= DP_LINK_TRAIN_OFF_CPT;
1892                 else
1893                         DP |= DP_LINK_TRAIN_OFF;
1894         }
1895
1896         if (HAS_PCH_IBX(dev) &&
1897             I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
1898                 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1899
1900                 /* Hardware workaround: leaving our transcoder select
1901                  * set to transcoder B while it's off will prevent the
1902                  * corresponding HDMI output on transcoder A.
1903                  *
1904                  * Combine this with another hardware workaround:
1905                  * transcoder select bit can only be cleared while the
1906                  * port is enabled.
1907                  */
1908                 DP &= ~DP_PIPEB_SELECT;
1909                 I915_WRITE(intel_dp->output_reg, DP);
1910
1911                 /* Changes to enable or select take place the vblank
1912                  * after being written.
1913                  */
1914                 if (crtc == NULL) {
1915                         /* We can arrive here never having been attached
1916                          * to a CRTC, for instance, due to inheriting
1917                          * random state from the BIOS.
1918                          *
1919                          * If the pipe is not running, play safe and
1920                          * wait for the clocks to stabilise before
1921                          * continuing.
1922                          */
1923                         POSTING_READ(intel_dp->output_reg);
1924                         msleep(50);
1925                 } else
1926                         intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
1927         }
1928
1929         DP &= ~DP_AUDIO_OUTPUT_ENABLE;
1930         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
1931         POSTING_READ(intel_dp->output_reg);
1932         msleep(intel_dp->panel_power_down_delay);
1933 }
1934
1935 static bool
1936 intel_dp_get_dpcd(struct intel_dp *intel_dp)
1937 {
1938         if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
1939                                            sizeof(intel_dp->dpcd)) &&
1940             (intel_dp->dpcd[DP_DPCD_REV] != 0)) {
1941                 return true;
1942         }
1943
1944         return false;
1945 }
1946
1947 static void
1948 intel_dp_probe_oui(struct intel_dp *intel_dp)
1949 {
1950         u8 buf[3];
1951
1952         if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
1953                 return;
1954
1955         ironlake_edp_panel_vdd_on(intel_dp);
1956
1957         if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
1958                 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
1959                               buf[0], buf[1], buf[2]);
1960
1961         if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
1962                 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
1963                               buf[0], buf[1], buf[2]);
1964
1965         ironlake_edp_panel_vdd_off(intel_dp, false);
1966 }
1967
1968 static bool
1969 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
1970 {
1971         int ret;
1972
1973         ret = intel_dp_aux_native_read_retry(intel_dp,
1974                                              DP_DEVICE_SERVICE_IRQ_VECTOR,
1975                                              sink_irq_vector, 1);
1976         if (!ret)
1977                 return false;
1978
1979         return true;
1980 }
1981
1982 static void
1983 intel_dp_handle_test_request(struct intel_dp *intel_dp)
1984 {
1985         /* NAK by default */
1986         intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_ACK);
1987 }
1988
1989 /*
1990  * According to DP spec
1991  * 5.1.2:
1992  *  1. Read DPCD
1993  *  2. Configure link according to Receiver Capabilities
1994  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
1995  *  4. Check link status on receipt of hot-plug interrupt
1996  */
1997
1998 static void
1999 intel_dp_check_link_status(struct intel_dp *intel_dp)
2000 {
2001         u8 sink_irq_vector;
2002         u8 link_status[DP_LINK_STATUS_SIZE];
2003
2004         if (intel_dp->dpms_mode != DRM_MODE_DPMS_ON)
2005                 return;
2006
2007         if (!intel_dp->base.base.crtc)
2008                 return;
2009
2010         /* Try to read receiver status if the link appears to be up */
2011         if (!intel_dp_get_link_status(intel_dp, link_status)) {
2012                 intel_dp_link_down(intel_dp);
2013                 return;
2014         }
2015
2016         /* Now read the DPCD to see if it's actually running */
2017         if (!intel_dp_get_dpcd(intel_dp)) {
2018                 intel_dp_link_down(intel_dp);
2019                 return;
2020         }
2021
2022         /* Try to read the source of the interrupt */
2023         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2024             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2025                 /* Clear interrupt source */
2026                 intel_dp_aux_native_write_1(intel_dp,
2027                                             DP_DEVICE_SERVICE_IRQ_VECTOR,
2028                                             sink_irq_vector);
2029
2030                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2031                         intel_dp_handle_test_request(intel_dp);
2032                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2033                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2034         }
2035
2036         if (!intel_channel_eq_ok(intel_dp, link_status)) {
2037                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2038                               drm_get_encoder_name(&intel_dp->base.base));
2039                 intel_dp_start_link_train(intel_dp);
2040                 intel_dp_complete_link_train(intel_dp);
2041         }
2042 }
2043
2044 static enum drm_connector_status
2045 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2046 {
2047         if (intel_dp_get_dpcd(intel_dp))
2048                 return connector_status_connected;
2049         return connector_status_disconnected;
2050 }
2051
2052 static enum drm_connector_status
2053 ironlake_dp_detect(struct intel_dp *intel_dp)
2054 {
2055         enum drm_connector_status status;
2056
2057         /* Can't disconnect eDP, but you can close the lid... */
2058         if (is_edp(intel_dp)) {
2059                 status = intel_panel_detect(intel_dp->base.base.dev);
2060                 if (status == connector_status_unknown)
2061                         status = connector_status_connected;
2062                 return status;
2063         }
2064
2065         return intel_dp_detect_dpcd(intel_dp);
2066 }
2067
2068 static enum drm_connector_status
2069 g4x_dp_detect(struct intel_dp *intel_dp)
2070 {
2071         struct drm_device *dev = intel_dp->base.base.dev;
2072         struct drm_i915_private *dev_priv = dev->dev_private;
2073         uint32_t bit;
2074
2075         switch (intel_dp->output_reg) {
2076         case DP_B:
2077                 bit = DPB_HOTPLUG_LIVE_STATUS;
2078                 break;
2079         case DP_C:
2080                 bit = DPC_HOTPLUG_LIVE_STATUS;
2081                 break;
2082         case DP_D:
2083                 bit = DPD_HOTPLUG_LIVE_STATUS;
2084                 break;
2085         default:
2086                 return connector_status_unknown;
2087         }
2088
2089         if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2090                 return connector_status_disconnected;
2091
2092         return intel_dp_detect_dpcd(intel_dp);
2093 }
2094
2095 static struct edid *
2096 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2097 {
2098         struct intel_dp *intel_dp = intel_attached_dp(connector);
2099         struct edid     *edid;
2100         int size;
2101
2102         if (is_edp(intel_dp)) {
2103                 if (!intel_dp->edid)
2104                         return NULL;
2105
2106                 size = (intel_dp->edid->extensions + 1) * EDID_LENGTH;
2107                 edid = kmalloc(size, GFP_KERNEL);
2108                 if (!edid)
2109                         return NULL;
2110
2111                 memcpy(edid, intel_dp->edid, size);
2112                 return edid;
2113         }
2114
2115         edid = drm_get_edid(connector, adapter);
2116         return edid;
2117 }
2118
2119 static int
2120 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2121 {
2122         struct intel_dp *intel_dp = intel_attached_dp(connector);
2123         int     ret;
2124
2125         if (is_edp(intel_dp)) {
2126                 drm_mode_connector_update_edid_property(connector,
2127                                                         intel_dp->edid);
2128                 ret = drm_add_edid_modes(connector, intel_dp->edid);
2129                 drm_edid_to_eld(connector,
2130                                 intel_dp->edid);
2131                 connector->display_info.raw_edid = NULL;
2132                 return intel_dp->edid_mode_count;
2133         }
2134
2135         ret = intel_ddc_get_modes(connector, adapter);
2136         return ret;
2137 }
2138
2139
2140 /**
2141  * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
2142  *
2143  * \return true if DP port is connected.
2144  * \return false if DP port is disconnected.
2145  */
2146 static enum drm_connector_status
2147 intel_dp_detect(struct drm_connector *connector, bool force)
2148 {
2149         struct intel_dp *intel_dp = intel_attached_dp(connector);
2150         struct drm_device *dev = intel_dp->base.base.dev;
2151         enum drm_connector_status status;
2152         struct edid *edid = NULL;
2153
2154         intel_dp->has_audio = false;
2155
2156         if (HAS_PCH_SPLIT(dev))
2157                 status = ironlake_dp_detect(intel_dp);
2158         else
2159                 status = g4x_dp_detect(intel_dp);
2160
2161         DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
2162                       intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2],
2163                       intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5],
2164                       intel_dp->dpcd[6], intel_dp->dpcd[7]);
2165
2166         if (status != connector_status_connected)
2167                 return status;
2168
2169         intel_dp_probe_oui(intel_dp);
2170
2171         if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2172                 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
2173         } else {
2174                 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2175                 if (edid) {
2176                         intel_dp->has_audio = drm_detect_monitor_audio(edid);
2177                         connector->display_info.raw_edid = NULL;
2178                         kfree(edid);
2179                 }
2180         }
2181
2182         return connector_status_connected;
2183 }
2184
2185 static int intel_dp_get_modes(struct drm_connector *connector)
2186 {
2187         struct intel_dp *intel_dp = intel_attached_dp(connector);
2188         struct drm_device *dev = intel_dp->base.base.dev;
2189         struct drm_i915_private *dev_priv = dev->dev_private;
2190         int ret;
2191
2192         /* We should parse the EDID data and find out if it has an audio sink
2193          */
2194
2195         ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
2196         if (ret) {
2197                 if (is_edp(intel_dp) && !intel_dp->panel_fixed_mode) {
2198                         struct drm_display_mode *newmode;
2199                         list_for_each_entry(newmode, &connector->probed_modes,
2200                                             head) {
2201                                 if ((newmode->type & DRM_MODE_TYPE_PREFERRED)) {
2202                                         intel_dp->panel_fixed_mode =
2203                                                 drm_mode_duplicate(dev, newmode);
2204                                         break;
2205                                 }
2206                         }
2207                 }
2208                 return ret;
2209         }
2210
2211         /* if eDP has no EDID, try to use fixed panel mode from VBT */
2212         if (is_edp(intel_dp)) {
2213                 /* initialize panel mode from VBT if available for eDP */
2214                 if (intel_dp->panel_fixed_mode == NULL && dev_priv->lfp_lvds_vbt_mode != NULL) {
2215                         intel_dp->panel_fixed_mode =
2216                                 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
2217                         if (intel_dp->panel_fixed_mode) {
2218                                 intel_dp->panel_fixed_mode->type |=
2219                                         DRM_MODE_TYPE_PREFERRED;
2220                         }
2221                 }
2222                 if (intel_dp->panel_fixed_mode) {
2223                         struct drm_display_mode *mode;
2224                         mode = drm_mode_duplicate(dev, intel_dp->panel_fixed_mode);
2225                         drm_mode_probed_add(connector, mode);
2226                         return 1;
2227                 }
2228         }
2229         return 0;
2230 }
2231
2232 static bool
2233 intel_dp_detect_audio(struct drm_connector *connector)
2234 {
2235         struct intel_dp *intel_dp = intel_attached_dp(connector);
2236         struct edid *edid;
2237         bool has_audio = false;
2238
2239         edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2240         if (edid) {
2241                 has_audio = drm_detect_monitor_audio(edid);
2242
2243                 connector->display_info.raw_edid = NULL;
2244                 kfree(edid);
2245         }
2246
2247         return has_audio;
2248 }
2249
2250 static int
2251 intel_dp_set_property(struct drm_connector *connector,
2252                       struct drm_property *property,
2253                       uint64_t val)
2254 {
2255         struct drm_i915_private *dev_priv = connector->dev->dev_private;
2256         struct intel_dp *intel_dp = intel_attached_dp(connector);
2257         int ret;
2258
2259         ret = drm_connector_property_set_value(connector, property, val);
2260         if (ret)
2261                 return ret;
2262
2263         if (property == dev_priv->force_audio_property) {
2264                 int i = val;
2265                 bool has_audio;
2266
2267                 if (i == intel_dp->force_audio)
2268                         return 0;
2269
2270                 intel_dp->force_audio = i;
2271
2272                 if (i == HDMI_AUDIO_AUTO)
2273                         has_audio = intel_dp_detect_audio(connector);
2274                 else
2275                         has_audio = (i == HDMI_AUDIO_ON);
2276
2277                 if (has_audio == intel_dp->has_audio)
2278                         return 0;
2279
2280                 intel_dp->has_audio = has_audio;
2281                 goto done;
2282         }
2283
2284         if (property == dev_priv->broadcast_rgb_property) {
2285                 if (val == !!intel_dp->color_range)
2286                         return 0;
2287
2288                 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
2289                 goto done;
2290         }
2291
2292         return -EINVAL;
2293
2294 done:
2295         if (intel_dp->base.base.crtc) {
2296                 struct drm_crtc *crtc = intel_dp->base.base.crtc;
2297                 drm_crtc_helper_set_mode(crtc, &crtc->mode,
2298                                          crtc->x, crtc->y,
2299                                          crtc->fb);
2300         }
2301
2302         return 0;
2303 }
2304
2305 static void
2306 intel_dp_destroy(struct drm_connector *connector)
2307 {
2308         struct drm_device *dev = connector->dev;
2309
2310         if (intel_dpd_is_edp(dev))
2311                 intel_panel_destroy_backlight(dev);
2312
2313         drm_sysfs_connector_remove(connector);
2314         drm_connector_cleanup(connector);
2315         kfree(connector);
2316 }
2317
2318 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2319 {
2320         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2321
2322         i2c_del_adapter(&intel_dp->adapter);
2323         drm_encoder_cleanup(encoder);
2324         if (is_edp(intel_dp)) {
2325                 kfree(intel_dp->edid);
2326                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2327                 ironlake_panel_vdd_off_sync(intel_dp);
2328         }
2329         kfree(intel_dp);
2330 }
2331
2332 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
2333         .dpms = intel_dp_dpms,
2334         .mode_fixup = intel_dp_mode_fixup,
2335         .prepare = intel_dp_prepare,
2336         .mode_set = intel_dp_mode_set,
2337         .commit = intel_dp_commit,
2338 };
2339
2340 static const struct drm_connector_funcs intel_dp_connector_funcs = {
2341         .dpms = drm_helper_connector_dpms,
2342         .detect = intel_dp_detect,
2343         .fill_modes = drm_helper_probe_single_connector_modes,
2344         .set_property = intel_dp_set_property,
2345         .destroy = intel_dp_destroy,
2346 };
2347
2348 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2349         .get_modes = intel_dp_get_modes,
2350         .mode_valid = intel_dp_mode_valid,
2351         .best_encoder = intel_best_encoder,
2352 };
2353
2354 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
2355         .destroy = intel_dp_encoder_destroy,
2356 };
2357
2358 static void
2359 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
2360 {
2361         struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
2362
2363         intel_dp_check_link_status(intel_dp);
2364 }
2365
2366 /* Return which DP Port should be selected for Transcoder DP control */
2367 int
2368 intel_trans_dp_port_sel(struct drm_crtc *crtc)
2369 {
2370         struct drm_device *dev = crtc->dev;
2371         struct intel_encoder *encoder;
2372
2373         for_each_encoder_on_crtc(dev, crtc, encoder) {
2374                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2375
2376                 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
2377                     intel_dp->base.type == INTEL_OUTPUT_EDP)
2378                         return intel_dp->output_reg;
2379         }
2380
2381         return -1;
2382 }
2383
2384 /* check the VBT to see whether the eDP is on DP-D port */
2385 bool intel_dpd_is_edp(struct drm_device *dev)
2386 {
2387         struct drm_i915_private *dev_priv = dev->dev_private;
2388         struct child_device_config *p_child;
2389         int i;
2390
2391         if (!dev_priv->child_dev_num)
2392                 return false;
2393
2394         for (i = 0; i < dev_priv->child_dev_num; i++) {
2395                 p_child = dev_priv->child_dev + i;
2396
2397                 if (p_child->dvo_port == PORT_IDPD &&
2398                     p_child->device_type == DEVICE_TYPE_eDP)
2399                         return true;
2400         }
2401         return false;
2402 }
2403
2404 static void
2405 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2406 {
2407         intel_attach_force_audio_property(connector);
2408         intel_attach_broadcast_rgb_property(connector);
2409 }
2410
2411 void
2412 intel_dp_init(struct drm_device *dev, int output_reg)
2413 {
2414         struct drm_i915_private *dev_priv = dev->dev_private;
2415         struct drm_connector *connector;
2416         struct intel_dp *intel_dp;
2417         struct intel_encoder *intel_encoder;
2418         struct intel_connector *intel_connector;
2419         const char *name = NULL;
2420         int type;
2421
2422         intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
2423         if (!intel_dp)
2424                 return;
2425
2426         intel_dp->output_reg = output_reg;
2427         intel_dp->dpms_mode = -1;
2428
2429         intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
2430         if (!intel_connector) {
2431                 kfree(intel_dp);
2432                 return;
2433         }
2434         intel_encoder = &intel_dp->base;
2435
2436         if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
2437                 if (intel_dpd_is_edp(dev))
2438                         intel_dp->is_pch_edp = true;
2439
2440         if (output_reg == DP_A || is_pch_edp(intel_dp)) {
2441                 type = DRM_MODE_CONNECTOR_eDP;
2442                 intel_encoder->type = INTEL_OUTPUT_EDP;
2443         } else {
2444                 type = DRM_MODE_CONNECTOR_DisplayPort;
2445                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2446         }
2447
2448         connector = &intel_connector->base;
2449         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
2450         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2451
2452         connector->polled = DRM_CONNECTOR_POLL_HPD;
2453
2454         intel_encoder->cloneable = false;
2455
2456         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
2457                           ironlake_panel_vdd_work);
2458
2459         intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2460
2461         connector->interlace_allowed = true;
2462         connector->doublescan_allowed = 0;
2463
2464         drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
2465                          DRM_MODE_ENCODER_TMDS);
2466         drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
2467
2468         intel_connector_attach_encoder(intel_connector, intel_encoder);
2469         drm_sysfs_connector_add(connector);
2470
2471         /* Set up the DDC bus. */
2472         switch (output_reg) {
2473                 case DP_A:
2474                         name = "DPDDC-A";
2475                         break;
2476                 case DP_B:
2477                 case PCH_DP_B:
2478                         dev_priv->hotplug_supported_mask |=
2479                                 DPB_HOTPLUG_INT_STATUS;
2480                         name = "DPDDC-B";
2481                         break;
2482                 case DP_C:
2483                 case PCH_DP_C:
2484                         dev_priv->hotplug_supported_mask |=
2485                                 DPC_HOTPLUG_INT_STATUS;
2486                         name = "DPDDC-C";
2487                         break;
2488                 case DP_D:
2489                 case PCH_DP_D:
2490                         dev_priv->hotplug_supported_mask |=
2491                                 DPD_HOTPLUG_INT_STATUS;
2492                         name = "DPDDC-D";
2493                         break;
2494         }
2495
2496         intel_dp_i2c_init(intel_dp, intel_connector, name);
2497
2498         /* Cache some DPCD data in the eDP case */
2499         if (is_edp(intel_dp)) {
2500                 bool ret;
2501                 struct edp_power_seq    cur, vbt;
2502                 u32 pp_on, pp_off, pp_div;
2503                 struct edid *edid;
2504
2505                 pp_on = I915_READ(PCH_PP_ON_DELAYS);
2506                 pp_off = I915_READ(PCH_PP_OFF_DELAYS);
2507                 pp_div = I915_READ(PCH_PP_DIVISOR);
2508
2509                 if (!pp_on || !pp_off || !pp_div) {
2510                         DRM_INFO("bad panel power sequencing delays, disabling panel\n");
2511                         intel_dp_encoder_destroy(&intel_dp->base.base);
2512                         intel_dp_destroy(&intel_connector->base);
2513                         return;
2514                 }
2515
2516                 /* Pull timing values out of registers */
2517                 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2518                         PANEL_POWER_UP_DELAY_SHIFT;
2519
2520                 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2521                         PANEL_LIGHT_ON_DELAY_SHIFT;
2522
2523                 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2524                         PANEL_LIGHT_OFF_DELAY_SHIFT;
2525
2526                 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2527                         PANEL_POWER_DOWN_DELAY_SHIFT;
2528
2529                 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2530                                PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2531
2532                 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2533                               cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2534
2535                 vbt = dev_priv->edp.pps;
2536
2537                 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2538                               vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2539
2540 #define get_delay(field)        ((max(cur.field, vbt.field) + 9) / 10)
2541
2542                 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2543                 intel_dp->backlight_on_delay = get_delay(t8);
2544                 intel_dp->backlight_off_delay = get_delay(t9);
2545                 intel_dp->panel_power_down_delay = get_delay(t10);
2546                 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2547
2548                 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2549                               intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2550                               intel_dp->panel_power_cycle_delay);
2551
2552                 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2553                               intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2554
2555                 ironlake_edp_panel_vdd_on(intel_dp);
2556                 ret = intel_dp_get_dpcd(intel_dp);
2557                 ironlake_edp_panel_vdd_off(intel_dp, false);
2558
2559                 if (ret) {
2560                         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2561                                 dev_priv->no_aux_handshake =
2562                                         intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
2563                                         DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2564                 } else {
2565                         /* if this fails, presume the device is a ghost */
2566                         DRM_INFO("failed to retrieve link info, disabling eDP\n");
2567                         intel_dp_encoder_destroy(&intel_dp->base.base);
2568                         intel_dp_destroy(&intel_connector->base);
2569                         return;
2570                 }
2571
2572                 ironlake_edp_panel_vdd_on(intel_dp);
2573                 edid = drm_get_edid(connector, &intel_dp->adapter);
2574                 if (edid) {
2575                         drm_mode_connector_update_edid_property(connector,
2576                                                                 edid);
2577                         intel_dp->edid_mode_count =
2578                                 drm_add_edid_modes(connector, edid);
2579                         drm_edid_to_eld(connector, edid);
2580                         intel_dp->edid = edid;
2581                 }
2582                 ironlake_edp_panel_vdd_off(intel_dp, false);
2583         }
2584
2585         intel_encoder->hot_plug = intel_dp_hot_plug;
2586
2587         if (is_edp(intel_dp)) {
2588                 dev_priv->int_edp_connector = connector;
2589                 intel_panel_setup_backlight(dev);
2590         }
2591
2592         intel_dp_add_properties(intel_dp, connector);
2593
2594         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2595          * 0xd.  Failure to do so will result in spurious interrupts being
2596          * generated on the port when a cable is not attached.
2597          */
2598         if (IS_G4X(dev) && !IS_GM45(dev)) {
2599                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2600                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2601         }
2602 }