Pileus Git - ~andy/linux/blob - drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include <drm/drmP.h>
  32 #include <drm/drm_crtc.h>
  33 #include <drm/drm_crtc_helper.h>
  34 #include <drm/drm_edid.h>
  35 #include "intel_drv.h"
  36 #include <drm/i915_drm.h>
  37 #include "i915_drv.h"
  38
  39 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  40
  41 /**
  42  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  43  * @intel_dp: DP struct
  44  *
  45  * If a CPU or PCH DP output is attached to an eDP panel, this function
  46  * will return true, and false otherwise.
  47  */
  48 static bool is_edp(struct intel_dp *intel_dp)
  49 {
  50         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  51
  52         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
  53 }
  54
  55 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
  56 {
  57         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  58
  59         return intel_dig_port->base.base.dev;
  60 }
  61
  62 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
  63 {
  64         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
  65 }
  66
  67 static void intel_dp_link_down(struct intel_dp *intel_dp);
  68
  69 static int
  70 intel_dp_max_link_bw(struct intel_dp *intel_dp)
  71 {
  72         int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
  73
  74         switch (max_link_bw) {
  75         case DP_LINK_BW_1_62:
  76         case DP_LINK_BW_2_7:
  77                 break;
  78         case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
  79                 max_link_bw = DP_LINK_BW_2_7;
  80                 break;
  81         default:
  82                 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
  83                      max_link_bw);
  84                 max_link_bw = DP_LINK_BW_1_62;
  85                 break;
  86         }
  87         return max_link_bw;
  88 }
  89
  90 /*
  91  * The units on the numbers in the next two are... bizarre.  Examples will
  92  * make it clearer; this one parallels an example in the eDP spec.
  93  *
  94  * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
  95  *
  96  *     270000 * 1 * 8 / 10 == 216000
  97  *
  98  * The actual data capacity of that configuration is 2.16Gbit/s, so the
  99  * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 100  * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 101  * 119000.  At 18bpp that's 2142000 kilobits per second.
 102  *
 103  * Thus the strange-looking division by 10 in intel_dp_link_required, to
 104  * get the result in decakilobits instead of kilobits.
 105  */
 106
 107 static int
 108 intel_dp_link_required(int pixel_clock, int bpp)
 109 {
 110         return (pixel_clock * bpp + 9) / 10;
 111 }
 112
 113 static int
 114 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 115 {
 116         return (max_link_clock * max_lanes * 8) / 10;
 117 }
 118
 119 static int
 120 intel_dp_mode_valid(struct drm_connector *connector,
 121                     struct drm_display_mode *mode)
 122 {
 123         struct intel_dp *intel_dp = intel_attached_dp(connector);
 124         struct intel_connector *intel_connector = to_intel_connector(connector);
 125         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 126         int target_clock = mode->clock;
 127         int max_rate, mode_rate, max_lanes, max_link_clock;
 128
 129         if (is_edp(intel_dp) && fixed_mode) {
 130                 if (mode->hdisplay > fixed_mode->hdisplay)
 131                         return MODE_PANEL;
 132
 133                 if (mode->vdisplay > fixed_mode->vdisplay)
 134                         return MODE_PANEL;
 135
 136                 target_clock = fixed_mode->clock;
 137         }
 138
 139         max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
 140         max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
 141
 142         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 143         mode_rate = intel_dp_link_required(target_clock, 18);
 144
 145         if (mode_rate > max_rate)
 146                 return MODE_CLOCK_HIGH;
 147
 148         if (mode->clock < 10000)
 149                 return MODE_CLOCK_LOW;
 150
 151         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 152                 return MODE_H_ILLEGAL;
 153
 154         return MODE_OK;
 155 }
 156
 157 static uint32_t
 158 pack_aux(uint8_t *src, int src_bytes)
 159 {
 160         int     i;
 161         uint32_t v = 0;
 162
 163         if (src_bytes > 4)
 164                 src_bytes = 4;
 165         for (i = 0; i < src_bytes; i++)
 166                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 167         return v;
 168 }
 169
 170 static void
 171 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 172 {
 173         int i;
 174         if (dst_bytes > 4)
 175                 dst_bytes = 4;
 176         for (i = 0; i < dst_bytes; i++)
 177                 dst[i] = src >> ((3-i) * 8);
 178 }
 179
 180 /* hrawclock is 1/4 the FSB frequency */
 181 static int
 182 intel_hrawclk(struct drm_device *dev)
 183 {
 184         struct drm_i915_private *dev_priv = dev->dev_private;
 185         uint32_t clkcfg;
 186
 187         /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
 188         if (IS_VALLEYVIEW(dev))
 189                 return 200;
 190
 191         clkcfg = I915_READ(CLKCFG);
 192         switch (clkcfg & CLKCFG_FSB_MASK) {
 193         case CLKCFG_FSB_400:
 194                 return 100;
 195         case CLKCFG_FSB_533:
 196                 return 133;
 197         case CLKCFG_FSB_667:
 198                 return 166;
 199         case CLKCFG_FSB_800:
 200                 return 200;
 201         case CLKCFG_FSB_1067:
 202                 return 266;
 203         case CLKCFG_FSB_1333:
 204                 return 333;
 205         /* these two are just a guess; one of them might be right */
 206         case CLKCFG_FSB_1600:
 207         case CLKCFG_FSB_1600_ALT:
 208                 return 400;
 209         default:
 210                 return 133;
 211         }
 212 }
 213
 214 static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
 215 {
 216         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 217         struct drm_i915_private *dev_priv = dev->dev_private;
 218         u32 pp_stat_reg;
 219
 220         pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
 221         return (I915_READ(pp_stat_reg) & PP_ON) != 0;
 222 }
 223
 224 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
 225 {
 226         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 227         struct drm_i915_private *dev_priv = dev->dev_private;
 228         u32 pp_ctrl_reg;
 229
 230         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
 231         return (I915_READ(pp_ctrl_reg) & EDP_FORCE_VDD) != 0;
 232 }
 233
 234 static void
 235 intel_dp_check_edp(struct intel_dp *intel_dp)
 236 {
 237         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 238         struct drm_i915_private *dev_priv = dev->dev_private;
 239         u32 pp_stat_reg, pp_ctrl_reg;
 240
 241         if (!is_edp(intel_dp))
 242                 return;
 243
 244         pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
 245         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
 246
 247         if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
 248                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 249                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 250                                 I915_READ(pp_stat_reg),
 251                                 I915_READ(pp_ctrl_reg));
 252         }
 253 }
 254
 255 static uint32_t
 256 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
 257 {
 258         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 259         struct drm_device *dev = intel_dig_port->base.base.dev;
 260         struct drm_i915_private *dev_priv = dev->dev_private;
 261         uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 262         uint32_t status;
 263         bool done;
 264
 265 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 266         if (has_aux_irq)
 267                 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
 268                                           msecs_to_jiffies_timeout(10));
 269         else
 270                 done = wait_for_atomic(C, 10) == 0;
 271         if (!done)
 272                 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
 273                           has_aux_irq);
 274 #undef C
 275
 276         return status;
 277 }
 278
 279 static uint32_t get_aux_clock_divider(struct intel_dp *intel_dp,
 280                                       int index)
 281 {
 282         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 283         struct drm_device *dev = intel_dig_port->base.base.dev;
 284         struct drm_i915_private *dev_priv = dev->dev_private;
 285
 286         /* The clock divider is based off the hrawclk,
 287          * and would like to run at 2MHz. So, take the
 288          * hrawclk value and divide by 2 and use that
 289          *
 290          * Note that PCH attached eDP panels should use a 125MHz input
 291          * clock divider.
 292          */
 293         if (IS_VALLEYVIEW(dev)) {
 294                 return index ? 0 : 100;
 295         } else if (intel_dig_port->port == PORT_A) {
 296                 if (index)
 297                         return 0;
 298                 if (HAS_DDI(dev))
 299                         return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
 300                 else if (IS_GEN6(dev) || IS_GEN7(dev))
 301                         return 200; /* SNB & IVB eDP input clock at 400Mhz */
 302                 else
 303                         return 225; /* eDP input clock at 450Mhz */
 304         } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 305                 /* Workaround for non-ULT HSW */
 306                 switch (index) {
 307                 case 0: return 63;
 308                 case 1: return 72;
 309                 default: return 0;
 310                 }
 311         } else if (HAS_PCH_SPLIT(dev)) {
 312                 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
 313         } else {
 314                 return index ? 0 :intel_hrawclk(dev) / 2;
 315         }
 316 }
 317
 318 static int
 319 intel_dp_aux_ch(struct intel_dp *intel_dp,
 320                 uint8_t *send, int send_bytes,
 321                 uint8_t *recv, int recv_size)
 322 {
 323         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 324         struct drm_device *dev = intel_dig_port->base.base.dev;
 325         struct drm_i915_private *dev_priv = dev->dev_private;
 326         uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 327         uint32_t ch_data = ch_ctl + 4;
 328         uint32_t aux_clock_divider;
 329         int i, ret, recv_bytes;
 330         uint32_t status;
 331         int try, precharge, clock = 0;
 332         bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);
 333
 334         /* dp aux is extremely sensitive to irq latency, hence request the
 335          * lowest possible wakeup latency and so prevent the cpu from going into
 336          * deep sleep states.
 337          */
 338         pm_qos_update_request(&dev_priv->pm_qos, 0);
 339
 340         intel_dp_check_edp(intel_dp);
 341
 342         if (IS_GEN6(dev))
 343                 precharge = 3;
 344         else
 345                 precharge = 5;
 346
 347         /* Try to wait for any previous AUX channel activity */
 348         for (try = 0; try < 3; try++) {
 349                 status = I915_READ_NOTRACE(ch_ctl);
 350                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 351                         break;
 352                 msleep(1);
 353         }
 354
 355         if (try == 3) {
 356                 WARN(1, "dp_aux_ch not started status 0x%08x\n",
 357                      I915_READ(ch_ctl));
 358                 ret = -EBUSY;
 359                 goto out;
 360         }
 361
 362         while ((aux_clock_divider = get_aux_clock_divider(intel_dp, clock++))) {
 363                 /* Must try at least 3 times according to DP spec */
 364                 for (try = 0; try < 5; try++) {
 365                         /* Load the send data into the aux channel data registers */
 366                         for (i = 0; i < send_bytes; i += 4)
 367                                 I915_WRITE(ch_data + i,
 368                                            pack_aux(send + i, send_bytes - i));
 369
 370                         /* Send the command and wait for it to complete */
 371                         I915_WRITE(ch_ctl,
 372                                    DP_AUX_CH_CTL_SEND_BUSY |
 373                                    (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
 374                                    DP_AUX_CH_CTL_TIME_OUT_400us |
 375                                    (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 376                                    (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 377                                    (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
 378                                    DP_AUX_CH_CTL_DONE |
 379                                    DP_AUX_CH_CTL_TIME_OUT_ERROR |
 380                                    DP_AUX_CH_CTL_RECEIVE_ERROR);
 381
 382                         status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
 383
 384                         /* Clear done status and any errors */
 385                         I915_WRITE(ch_ctl,
 386                                    status |
 387                                    DP_AUX_CH_CTL_DONE |
 388                                    DP_AUX_CH_CTL_TIME_OUT_ERROR |
 389                                    DP_AUX_CH_CTL_RECEIVE_ERROR);
 390
 391                         if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
 392                                       DP_AUX_CH_CTL_RECEIVE_ERROR))
 393                                 continue;
 394                         if (status & DP_AUX_CH_CTL_DONE)
 395                                 break;
 396                 }
 397                 if (status & DP_AUX_CH_CTL_DONE)
 398                         break;
 399         }
 400
 401         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 402                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 403                 ret = -EBUSY;
 404                 goto out;
 405         }
 406
 407         /* Check for timeout or receive error.
 408          * Timeouts occur when the sink is not connected
 409          */
 410         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 411                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 412                 ret = -EIO;
 413                 goto out;
 414         }
 415
 416         /* Timeouts occur when the device isn't connected, so they're
 417          * "normal" -- don't fill the kernel log with these */
 418         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 419                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 420                 ret = -ETIMEDOUT;
 421                 goto out;
 422         }
 423
 424         /* Unload any bytes sent back from the other side */
 425         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 426                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 427         if (recv_bytes > recv_size)
 428                 recv_bytes = recv_size;
 429
 430         for (i = 0; i < recv_bytes; i += 4)
 431                 unpack_aux(I915_READ(ch_data + i),
 432                            recv + i, recv_bytes - i);
 433
 434         ret = recv_bytes;
 435 out:
 436         pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
 437
 438         return ret;
 439 }
 440
 441 /* Write data to the aux channel in native mode */
 442 static int
 443 intel_dp_aux_native_write(struct intel_dp *intel_dp,
 444                           uint16_t address, uint8_t *send, int send_bytes)
 445 {
 446         int ret;
 447         uint8_t msg[20];
 448         int msg_bytes;
 449         uint8_t ack;
 450
 451         intel_dp_check_edp(intel_dp);
 452         if (send_bytes > 16)
 453                 return -1;
 454         msg[0] = AUX_NATIVE_WRITE << 4;
 455         msg[1] = address >> 8;
 456         msg[2] = address & 0xff;
 457         msg[3] = send_bytes - 1;
 458         memcpy(&msg[4], send, send_bytes);
 459         msg_bytes = send_bytes + 4;
 460         for (;;) {
 461                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
 462                 if (ret < 0)
 463                         return ret;
 464                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
 465                         break;
 466                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 467                         udelay(100);
 468                 else
 469                         return -EIO;
 470         }
 471         return send_bytes;
 472 }
 473
 474 /* Write a single byte to the aux channel in native mode */
 475 static int
 476 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
 477                             uint16_t address, uint8_t byte)
 478 {
 479         return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
 480 }
 481
 482 /* read bytes from a native aux channel */
 483 static int
 484 intel_dp_aux_native_read(struct intel_dp *intel_dp,
 485                          uint16_t address, uint8_t *recv, int recv_bytes)
 486 {
 487         uint8_t msg[4];
 488         int msg_bytes;
 489         uint8_t reply[20];
 490         int reply_bytes;
 491         uint8_t ack;
 492         int ret;
 493
 494         intel_dp_check_edp(intel_dp);
 495         msg[0] = AUX_NATIVE_READ << 4;
 496         msg[1] = address >> 8;
 497         msg[2] = address & 0xff;
 498         msg[3] = recv_bytes - 1;
 499
 500         msg_bytes = 4;
 501         reply_bytes = recv_bytes + 1;
 502
 503         for (;;) {
 504                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
 505                                       reply, reply_bytes);
 506                 if (ret == 0)
 507                         return -EPROTO;
 508                 if (ret < 0)
 509                         return ret;
 510                 ack = reply[0];
 511                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
 512                         memcpy(recv, reply + 1, ret - 1);
 513                         return ret - 1;
 514                 }
 515                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 516                         udelay(100);
 517                 else
 518                         return -EIO;
 519         }
 520 }
 521
 522 static int
 523 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
 524                     uint8_t write_byte, uint8_t *read_byte)
 525 {
 526         struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
 527         struct intel_dp *intel_dp = container_of(adapter,
 528                                                 struct intel_dp,
 529                                                 adapter);
 530         uint16_t address = algo_data->address;
 531         uint8_t msg[5];
 532         uint8_t reply[2];
 533         unsigned retry;
 534         int msg_bytes;
 535         int reply_bytes;
 536         int ret;
 537
 538         intel_dp_check_edp(intel_dp);
 539         /* Set up the command byte */
 540         if (mode & MODE_I2C_READ)
 541                 msg[0] = AUX_I2C_READ << 4;
 542         else
 543                 msg[0] = AUX_I2C_WRITE << 4;
 544
 545         if (!(mode & MODE_I2C_STOP))
 546                 msg[0] |= AUX_I2C_MOT << 4;
 547
 548         msg[1] = address >> 8;
 549         msg[2] = address;
 550
 551         switch (mode) {
 552         case MODE_I2C_WRITE:
 553                 msg[3] = 0;
 554                 msg[4] = write_byte;
 555                 msg_bytes = 5;
 556                 reply_bytes = 1;
 557                 break;
 558         case MODE_I2C_READ:
 559                 msg[3] = 0;
 560                 msg_bytes = 4;
 561                 reply_bytes = 2;
 562                 break;
 563         default:
 564                 msg_bytes = 3;
 565                 reply_bytes = 1;
 566                 break;
 567         }
 568
 569         for (retry = 0; retry < 5; retry++) {
 570                 ret = intel_dp_aux_ch(intel_dp,
 571                                       msg, msg_bytes,
 572                                       reply, reply_bytes);
 573                 if (ret < 0) {
 574                         DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
 575                         return ret;
 576                 }
 577
 578                 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
 579                 case AUX_NATIVE_REPLY_ACK:
 580                         /* I2C-over-AUX Reply field is only valid
 581                          * when paired with AUX ACK.
 582                          */
 583                         break;
 584                 case AUX_NATIVE_REPLY_NACK:
 585                         DRM_DEBUG_KMS("aux_ch native nack\n");
 586                         return -EREMOTEIO;
 587                 case AUX_NATIVE_REPLY_DEFER:
 588                         udelay(100);
 589                         continue;
 590                 default:
 591                         DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
 592                                   reply[0]);
 593                         return -EREMOTEIO;
 594                 }
 595
 596                 switch (reply[0] & AUX_I2C_REPLY_MASK) {
 597                 case AUX_I2C_REPLY_ACK:
 598                         if (mode == MODE_I2C_READ) {
 599                                 *read_byte = reply[1];
 600                         }
 601                         return reply_bytes - 1;
 602                 case AUX_I2C_REPLY_NACK:
 603                         DRM_DEBUG_KMS("aux_i2c nack\n");
 604                         return -EREMOTEIO;
 605                 case AUX_I2C_REPLY_DEFER:
 606                         DRM_DEBUG_KMS("aux_i2c defer\n");
 607                         udelay(100);
 608                         break;
 609                 default:
 610                         DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
 611                         return -EREMOTEIO;
 612                 }
 613         }
 614
 615         DRM_ERROR("too many retries, giving up\n");
 616         return -EREMOTEIO;
 617 }
 618
 619 static int
 620 intel_dp_i2c_init(struct intel_dp *intel_dp,
 621                   struct intel_connector *intel_connector, const char *name)
 622 {
 623         int     ret;
 624
 625         DRM_DEBUG_KMS("i2c_init %s\n", name);
 626         intel_dp->algo.running = false;
 627         intel_dp->algo.address = 0;
 628         intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
 629
 630         memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
 631         intel_dp->adapter.owner = THIS_MODULE;
 632         intel_dp->adapter.class = I2C_CLASS_DDC;
 633         strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
 634         intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
 635         intel_dp->adapter.algo_data = &intel_dp->algo;
 636         intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
 637
 638         ironlake_edp_panel_vdd_on(intel_dp);
 639         ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
 640         ironlake_edp_panel_vdd_off(intel_dp, false);
 641         return ret;
 642 }
 643
 644 static void
 645 intel_dp_set_clock(struct intel_encoder *encoder,
 646                    struct intel_crtc_config *pipe_config, int link_bw)
 647 {
 648         struct drm_device *dev = encoder->base.dev;
 649
 650         if (IS_G4X(dev)) {
 651                 if (link_bw == DP_LINK_BW_1_62) {
 652                         pipe_config->dpll.p1 = 2;
 653                         pipe_config->dpll.p2 = 10;
 654                         pipe_config->dpll.n = 2;
 655                         pipe_config->dpll.m1 = 23;
 656                         pipe_config->dpll.m2 = 8;
 657                 } else {
 658                         pipe_config->dpll.p1 = 1;
 659                         pipe_config->dpll.p2 = 10;
 660                         pipe_config->dpll.n = 1;
 661                         pipe_config->dpll.m1 = 14;
 662                         pipe_config->dpll.m2 = 2;
 663                 }
 664                 pipe_config->clock_set = true;
 665         } else if (IS_HASWELL(dev)) {
 666                 /* Haswell has special-purpose DP DDI clocks. */
 667         } else if (HAS_PCH_SPLIT(dev)) {
 668                 if (link_bw == DP_LINK_BW_1_62) {
 669                         pipe_config->dpll.n = 1;
 670                         pipe_config->dpll.p1 = 2;
 671                         pipe_config->dpll.p2 = 10;
 672                         pipe_config->dpll.m1 = 12;
 673                         pipe_config->dpll.m2 = 9;
 674                 } else {
 675                         pipe_config->dpll.n = 2;
 676                         pipe_config->dpll.p1 = 1;
 677                         pipe_config->dpll.p2 = 10;
 678                         pipe_config->dpll.m1 = 14;
 679                         pipe_config->dpll.m2 = 8;
 680                 }
 681                 pipe_config->clock_set = true;
 682         } else if (IS_VALLEYVIEW(dev)) {
 683                 /* FIXME: Need to figure out optimized DP clocks for vlv. */
 684         }
 685 }
 686
 687 bool
 688 intel_dp_compute_config(struct intel_encoder *encoder,
 689                         struct intel_crtc_config *pipe_config)
 690 {
 691         struct drm_device *dev = encoder->base.dev;
 692         struct drm_i915_private *dev_priv = dev->dev_private;
 693         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
 694         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 695         enum port port = dp_to_dig_port(intel_dp)->port;
 696         struct intel_crtc *intel_crtc = encoder->new_crtc;
 697         struct intel_connector *intel_connector = intel_dp->attached_connector;
 698         int lane_count, clock;
 699         int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
 700         int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
 701         int bpp, mode_rate;
 702         static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
 703         int link_avail, link_clock;
 704
 705         if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
 706                 pipe_config->has_pch_encoder = true;
 707
 708         pipe_config->has_dp_encoder = true;
 709
 710         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
 711                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
 712                                        adjusted_mode);
 713                 if (!HAS_PCH_SPLIT(dev))
 714                         intel_gmch_panel_fitting(intel_crtc, pipe_config,
 715                                                  intel_connector->panel.fitting_mode);
 716                 else
 717                         intel_pch_panel_fitting(intel_crtc, pipe_config,
 718                                                 intel_connector->panel.fitting_mode);
 719         }
 720
 721         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
 722                 return false;
 723
 724         DRM_DEBUG_KMS("DP link computation with max lane count %i "
 725                       "max bw %02x pixel clock %iKHz\n",
 726                       max_lane_count, bws[max_clock], adjusted_mode->clock);
 727
 728         /* Walk through all bpp values. Luckily they're all nicely spaced with 2
 729          * bpc in between. */
 730         bpp = pipe_config->pipe_bpp;
 731         if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp) {
 732                 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
 733                               dev_priv->vbt.edp_bpp);
 734                 bpp = min_t(int, bpp, dev_priv->vbt.edp_bpp);
 735         }
 736
 737         for (; bpp >= 6*3; bpp -= 2*3) {
 738                 mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
 739
 740                 for (clock = 0; clock <= max_clock; clock++) {
 741                         for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
 742                                 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
 743                                 link_avail = intel_dp_max_data_rate(link_clock,
 744                                                                     lane_count);
 745
 746                                 if (mode_rate <= link_avail) {
 747                                         goto found;
 748                                 }
 749                         }
 750                 }
 751         }
 752
 753         return false;
 754
 755 found:
 756         if (intel_dp->color_range_auto) {
 757                 /*
 758                  * See:
 759                  * CEA-861-E - 5.1 Default Encoding Parameters
 760                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
 761                  */
 762                 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
 763                         intel_dp->color_range = DP_COLOR_RANGE_16_235;
 764                 else
 765                         intel_dp->color_range = 0;
 766         }
 767
 768         if (intel_dp->color_range)
 769                 pipe_config->limited_color_range = true;
 770
 771         intel_dp->link_bw = bws[clock];
 772         intel_dp->lane_count = lane_count;
 773         pipe_config->pipe_bpp = bpp;
 774         pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
 775
 776         DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
 777                       intel_dp->link_bw, intel_dp->lane_count,
 778                       pipe_config->port_clock, bpp);
 779         DRM_DEBUG_KMS("DP link bw required %i available %i\n",
 780                       mode_rate, link_avail);
 781
 782         intel_link_compute_m_n(bpp, lane_count,
 783                                adjusted_mode->clock, pipe_config->port_clock,
 784                                &pipe_config->dp_m_n);
 785
 786         intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
 787
 788         return true;
 789 }
 790
 791 void intel_dp_init_link_config(struct intel_dp *intel_dp)
 792 {
 793         memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
 794         intel_dp->link_configuration[0] = intel_dp->link_bw;
 795         intel_dp->link_configuration[1] = intel_dp->lane_count;
 796         intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
 797         /*
 798          * Check for DPCD version > 1.1 and enhanced framing support
 799          */
 800         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
 801             (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
 802                 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 803         }
 804 }
 805
 806 static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
 807 {
 808         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 809         struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
 810         struct drm_device *dev = crtc->base.dev;
 811         struct drm_i915_private *dev_priv = dev->dev_private;
 812         u32 dpa_ctl;
 813
 814         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
 815         dpa_ctl = I915_READ(DP_A);
 816         dpa_ctl &= ~DP_PLL_FREQ_MASK;
 817
 818         if (crtc->config.port_clock == 162000) {
 819                 /* For a long time we've carried around a ILK-DevA w/a for the
 820                  * 160MHz clock. If we're really unlucky, it's still required.
 821                  */
 822                 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
 823                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
 824                 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 825         } else {
 826                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
 827                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
 828         }
 829
 830         I915_WRITE(DP_A, dpa_ctl);
 831
 832         POSTING_READ(DP_A);
 833         udelay(500);
 834 }
 835
 836 static void intel_dp_mode_set(struct intel_encoder *encoder)
 837 {
 838         struct drm_device *dev = encoder->base.dev;
 839         struct drm_i915_private *dev_priv = dev->dev_private;
 840         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 841         enum port port = dp_to_dig_port(intel_dp)->port;
 842         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
 843         struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
 844
 845         /*
 846          * There are four kinds of DP registers:
 847          *
 848          *      IBX PCH
 849          *      SNB CPU
 850          *      IVB CPU
 851          *      CPT PCH
 852          *
 853          * IBX PCH and CPU are the same for almost everything,
 854          * except that the CPU DP PLL is configured in this
 855          * register
 856          *
 857          * CPT PCH is quite different, having many bits moved
 858          * to the TRANS_DP_CTL register instead. That
 859          * configuration happens (oddly) in ironlake_pch_enable
 860          */
 861
 862         /* Preserve the BIOS-computed detected bit. This is
 863          * supposed to be read-only.
 864          */
 865         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 866
 867         /* Handle DP bits in common between all three register formats */
 868         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 869         intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
 870
 871         if (intel_dp->has_audio) {
 872                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
 873                                  pipe_name(crtc->pipe));
 874                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
 875                 intel_write_eld(&encoder->base, adjusted_mode);
 876         }
 877
 878         intel_dp_init_link_config(intel_dp);
 879
 880         /* Split out the IBX/CPU vs CPT settings */
 881
 882         if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
 883                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 884                         intel_dp->DP |= DP_SYNC_HS_HIGH;
 885                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 886                         intel_dp->DP |= DP_SYNC_VS_HIGH;
 887                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 888
 889                 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
 890                         intel_dp->DP |= DP_ENHANCED_FRAMING;
 891
 892                 intel_dp->DP |= crtc->pipe << 29;
 893         } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
 894                 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
 895                         intel_dp->DP |= intel_dp->color_range;
 896
 897                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 898                         intel_dp->DP |= DP_SYNC_HS_HIGH;
 899                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 900                         intel_dp->DP |= DP_SYNC_VS_HIGH;
 901                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
 902
 903                 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
 904                         intel_dp->DP |= DP_ENHANCED_FRAMING;
 905
 906                 if (crtc->pipe == 1)
 907                         intel_dp->DP |= DP_PIPEB_SELECT;
 908         } else {
 909                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 910         }
 911
 912         if (port == PORT_A && !IS_VALLEYVIEW(dev))
 913                 ironlake_set_pll_cpu_edp(intel_dp);
 914 }
 915
 916 #define IDLE_ON_MASK            (PP_ON | 0        | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
 917 #define IDLE_ON_VALUE           (PP_ON | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
 918
 919 #define IDLE_OFF_MASK           (PP_ON | 0        | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
 920 #define IDLE_OFF_VALUE          (0     | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
 921
 922 #define IDLE_CYCLE_MASK         (PP_ON | 0        | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
 923 #define IDLE_CYCLE_VALUE        (0     | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
 924
 925 static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
 926                                        u32 mask,
 927                                        u32 value)
 928 {
 929         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 930         struct drm_i915_private *dev_priv = dev->dev_private;
 931         u32 pp_stat_reg, pp_ctrl_reg;
 932
 933         pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
 934         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
 935
 936         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
 937                         mask, value,
 938                         I915_READ(pp_stat_reg),
 939                         I915_READ(pp_ctrl_reg));
 940
 941         if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
 942                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
 943                                 I915_READ(pp_stat_reg),
 944                                 I915_READ(pp_ctrl_reg));
 945         }
 946 }
 947
 948 static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
 949 {
 950         DRM_DEBUG_KMS("Wait for panel power on\n");
 951         ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
 952 }
 953
 954 static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
 955 {
 956         DRM_DEBUG_KMS("Wait for panel power off time\n");
 957         ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
 958 }
 959
 960 static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
 961 {
 962         DRM_DEBUG_KMS("Wait for panel power cycle\n");
 963         ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
 964 }
 965
 966
 967 /* Read the current pp_control value, unlocking the register if it
 968  * is locked
 969  */
 970
 971 static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
 972 {
 973         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 974         struct drm_i915_private *dev_priv = dev->dev_private;
 975         u32 control;
 976         u32 pp_ctrl_reg;
 977
 978         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
 979         control = I915_READ(pp_ctrl_reg);
 980
 981         control &= ~PANEL_UNLOCK_MASK;
 982         control |= PANEL_UNLOCK_REGS;
 983         return control;
 984 }
 985
 986 void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
 987 {
 988         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 989         struct drm_i915_private *dev_priv = dev->dev_private;
 990         u32 pp;
 991         u32 pp_stat_reg, pp_ctrl_reg;
 992
 993         if (!is_edp(intel_dp))
 994                 return;
 995         DRM_DEBUG_KMS("Turn eDP VDD on\n");
 996
 997         WARN(intel_dp->want_panel_vdd,
 998              "eDP VDD already requested on\n");
 999
1000         intel_dp->want_panel_vdd = true;
1001
1002         if (ironlake_edp_have_panel_vdd(intel_dp)) {
1003                 DRM_DEBUG_KMS("eDP VDD already on\n");
1004                 return;
1005         }
1006
1007         if (!ironlake_edp_have_panel_power(intel_dp))
1008                 ironlake_wait_panel_power_cycle(intel_dp);
1009
1010         pp = ironlake_get_pp_control(intel_dp);
1011         pp |= EDP_FORCE_VDD;
1012
1013         pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
1014         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1015
1016         I915_WRITE(pp_ctrl_reg, pp);
1017         POSTING_READ(pp_ctrl_reg);
1018         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1019                         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1020         /*
1021          * If the panel wasn't on, delay before accessing aux channel
1022          */
1023         if (!ironlake_edp_have_panel_power(intel_dp)) {
1024                 DRM_DEBUG_KMS("eDP was not running\n");
1025                 msleep(intel_dp->panel_power_up_delay);
1026         }
1027 }
1028
1029 static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
1030 {
1031         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1032         struct drm_i915_private *dev_priv = dev->dev_private;
1033         u32 pp;
1034         u32 pp_stat_reg, pp_ctrl_reg;
1035
1036         WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1037
1038         if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
1039                 pp = ironlake_get_pp_control(intel_dp);
1040                 pp &= ~EDP_FORCE_VDD;
1041
1042                 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
1043                 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1044
1045                 I915_WRITE(pp_ctrl_reg, pp);
1046                 POSTING_READ(pp_ctrl_reg);
1047
1048                 /* Make sure sequencer is idle before allowing subsequent activity */
1049                 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1050                 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1051                 msleep(intel_dp->panel_power_down_delay);
1052         }
1053 }
1054
1055 static void ironlake_panel_vdd_work(struct work_struct *__work)
1056 {
1057         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1058                                                  struct intel_dp, panel_vdd_work);
1059         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1060
1061         mutex_lock(&dev->mode_config.mutex);
1062         ironlake_panel_vdd_off_sync(intel_dp);
1063         mutex_unlock(&dev->mode_config.mutex);
1064 }
1065
1066 void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1067 {
1068         if (!is_edp(intel_dp))
1069                 return;
1070
1071         DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1072         WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1073
1074         intel_dp->want_panel_vdd = false;
1075
1076         if (sync) {
1077                 ironlake_panel_vdd_off_sync(intel_dp);
1078         } else {
1079                 /*
1080                  * Queue the timer to fire a long
1081                  * time from now (relative to the power down delay)
1082                  * to keep the panel power up across a sequence of operations
1083                  */
1084                 schedule_delayed_work(&intel_dp->panel_vdd_work,
1085                                       msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1086         }
1087 }
1088
1089 void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1090 {
1091         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1092         struct drm_i915_private *dev_priv = dev->dev_private;
1093         u32 pp;
1094         u32 pp_ctrl_reg;
1095
1096         if (!is_edp(intel_dp))
1097                 return;
1098
1099         DRM_DEBUG_KMS("Turn eDP power on\n");
1100
1101         if (ironlake_edp_have_panel_power(intel_dp)) {
1102                 DRM_DEBUG_KMS("eDP power already on\n");
1103                 return;
1104         }
1105
1106         ironlake_wait_panel_power_cycle(intel_dp);
1107
1108         pp = ironlake_get_pp_control(intel_dp);
1109         if (IS_GEN5(dev)) {
1110                 /* ILK workaround: disable reset around power sequence */
1111                 pp &= ~PANEL_POWER_RESET;
1112                 I915_WRITE(PCH_PP_CONTROL, pp);
1113                 POSTING_READ(PCH_PP_CONTROL);
1114         }
1115
1116         pp |= POWER_TARGET_ON;
1117         if (!IS_GEN5(dev))
1118                 pp |= PANEL_POWER_RESET;
1119
1120         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1121
1122         I915_WRITE(pp_ctrl_reg, pp);
1123         POSTING_READ(pp_ctrl_reg);
1124
1125         ironlake_wait_panel_on(intel_dp);
1126
1127         if (IS_GEN5(dev)) {
1128                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1129                 I915_WRITE(PCH_PP_CONTROL, pp);
1130                 POSTING_READ(PCH_PP_CONTROL);
1131         }
1132 }
1133
1134 void ironlake_edp_panel_off(struct intel_dp *intel_dp)
1135 {
1136         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1137         struct drm_i915_private *dev_priv = dev->dev_private;
1138         u32 pp;
1139         u32 pp_ctrl_reg;
1140
1141         if (!is_edp(intel_dp))
1142                 return;
1143
1144         DRM_DEBUG_KMS("Turn eDP power off\n");
1145
1146         WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1147
1148         pp = ironlake_get_pp_control(intel_dp);
1149         /* We need to switch off panel power _and_ force vdd, for otherwise some
1150          * panels get very unhappy and cease to work. */
1151         pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1152
1153         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1154
1155         I915_WRITE(pp_ctrl_reg, pp);
1156         POSTING_READ(pp_ctrl_reg);
1157
1158         intel_dp->want_panel_vdd = false;
1159
1160         ironlake_wait_panel_off(intel_dp);
1161 }
1162
1163 void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1164 {
1165         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1166         struct drm_device *dev = intel_dig_port->base.base.dev;
1167         struct drm_i915_private *dev_priv = dev->dev_private;
1168         int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe;
1169         u32 pp;
1170         u32 pp_ctrl_reg;
1171
1172         if (!is_edp(intel_dp))
1173                 return;
1174
1175         DRM_DEBUG_KMS("\n");
1176         /*
1177          * If we enable the backlight right away following a panel power
1178          * on, we may see slight flicker as the panel syncs with the eDP
1179          * link.  So delay a bit to make sure the image is solid before
1180          * allowing it to appear.
1181          */
1182         msleep(intel_dp->backlight_on_delay);
1183         pp = ironlake_get_pp_control(intel_dp);
1184         pp |= EDP_BLC_ENABLE;
1185
1186         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1187
1188         I915_WRITE(pp_ctrl_reg, pp);
1189         POSTING_READ(pp_ctrl_reg);
1190
1191         intel_panel_enable_backlight(dev, pipe);
1192 }
1193
1194 void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1195 {
1196         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1197         struct drm_i915_private *dev_priv = dev->dev_private;
1198         u32 pp;
1199         u32 pp_ctrl_reg;
1200
1201         if (!is_edp(intel_dp))
1202                 return;
1203
1204         intel_panel_disable_backlight(dev);
1205
1206         DRM_DEBUG_KMS("\n");
1207         pp = ironlake_get_pp_control(intel_dp);
1208         pp &= ~EDP_BLC_ENABLE;
1209
1210         pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1211
1212         I915_WRITE(pp_ctrl_reg, pp);
1213         POSTING_READ(pp_ctrl_reg);
1214         msleep(intel_dp->backlight_off_delay);
1215 }
1216
1217 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1218 {
1219         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1220         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1221         struct drm_device *dev = crtc->dev;
1222         struct drm_i915_private *dev_priv = dev->dev_private;
1223         u32 dpa_ctl;
1224
1225         assert_pipe_disabled(dev_priv,
1226                              to_intel_crtc(crtc)->pipe);
1227
1228         DRM_DEBUG_KMS("\n");
1229         dpa_ctl = I915_READ(DP_A);
1230         WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1231         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1232
1233         /* We don't adjust intel_dp->DP while tearing down the link, to
1234          * facilitate link retraining (e.g. after hotplug). Hence clear all
1235          * enable bits here to ensure that we don't enable too much. */
1236         intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1237         intel_dp->DP |= DP_PLL_ENABLE;
1238         I915_WRITE(DP_A, intel_dp->DP);
1239         POSTING_READ(DP_A);
1240         udelay(200);
1241 }
1242
1243 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1244 {
1245         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1246         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1247         struct drm_device *dev = crtc->dev;
1248         struct drm_i915_private *dev_priv = dev->dev_private;
1249         u32 dpa_ctl;
1250
1251         assert_pipe_disabled(dev_priv,
1252                              to_intel_crtc(crtc)->pipe);
1253
1254         dpa_ctl = I915_READ(DP_A);
1255         WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1256              "dp pll off, should be on\n");
1257         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1258
1259         /* We can't rely on the value tracked for the DP register in
1260          * intel_dp->DP because link_down must not change that (otherwise link
1261          * re-training will fail. */
1262         dpa_ctl &= ~DP_PLL_ENABLE;
1263         I915_WRITE(DP_A, dpa_ctl);
1264         POSTING_READ(DP_A);
1265         udelay(200);
1266 }
1267
1268 /* If the sink supports it, try to set the power state appropriately */
1269 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1270 {
1271         int ret, i;
1272
1273         /* Should have a valid DPCD by this point */
1274         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1275                 return;
1276
1277         if (mode != DRM_MODE_DPMS_ON) {
1278                 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1279                                                   DP_SET_POWER_D3);
1280                 if (ret != 1)
1281                         DRM_DEBUG_DRIVER("failed to write sink power state\n");
1282         } else {
1283                 /*
1284                  * When turning on, we need to retry for 1ms to give the sink
1285                  * time to wake up.
1286                  */
1287                 for (i = 0; i < 3; i++) {
1288                         ret = intel_dp_aux_native_write_1(intel_dp,
1289                                                           DP_SET_POWER,
1290                                                           DP_SET_POWER_D0);
1291                         if (ret == 1)
1292                                 break;
1293                         msleep(1);
1294                 }
1295         }
1296 }
1297
1298 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1299                                   enum pipe *pipe)
1300 {
1301         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1302         enum port port = dp_to_dig_port(intel_dp)->port;
1303         struct drm_device *dev = encoder->base.dev;
1304         struct drm_i915_private *dev_priv = dev->dev_private;
1305         u32 tmp = I915_READ(intel_dp->output_reg);
1306
1307         if (!(tmp & DP_PORT_EN))
1308                 return false;
1309
1310         if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1311                 *pipe = PORT_TO_PIPE_CPT(tmp);
1312         } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1313                 *pipe = PORT_TO_PIPE(tmp);
1314         } else {
1315                 u32 trans_sel;
1316                 u32 trans_dp;
1317                 int i;
1318
1319                 switch (intel_dp->output_reg) {
1320                 case PCH_DP_B:
1321                         trans_sel = TRANS_DP_PORT_SEL_B;
1322                         break;
1323                 case PCH_DP_C:
1324                         trans_sel = TRANS_DP_PORT_SEL_C;
1325                         break;
1326                 case PCH_DP_D:
1327                         trans_sel = TRANS_DP_PORT_SEL_D;
1328                         break;
1329                 default:
1330                         return true;
1331                 }
1332
1333                 for_each_pipe(i) {
1334                         trans_dp = I915_READ(TRANS_DP_CTL(i));
1335                         if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1336                                 *pipe = i;
1337                                 return true;
1338                         }
1339                 }
1340
1341                 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1342                               intel_dp->output_reg);
1343         }
1344
1345         return true;
1346 }
1347
1348 static void intel_dp_get_config(struct intel_encoder *encoder,
1349                                 struct intel_crtc_config *pipe_config)
1350 {
1351         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1352         u32 tmp, flags = 0;
1353         struct drm_device *dev = encoder->base.dev;
1354         struct drm_i915_private *dev_priv = dev->dev_private;
1355         enum port port = dp_to_dig_port(intel_dp)->port;
1356         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1357
1358         if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
1359                 tmp = I915_READ(intel_dp->output_reg);
1360                 if (tmp & DP_SYNC_HS_HIGH)
1361                         flags |= DRM_MODE_FLAG_PHSYNC;
1362                 else
1363                         flags |= DRM_MODE_FLAG_NHSYNC;
1364
1365                 if (tmp & DP_SYNC_VS_HIGH)
1366                         flags |= DRM_MODE_FLAG_PVSYNC;
1367                 else
1368                         flags |= DRM_MODE_FLAG_NVSYNC;
1369         } else {
1370                 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1371                 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1372                         flags |= DRM_MODE_FLAG_PHSYNC;
1373                 else
1374                         flags |= DRM_MODE_FLAG_NHSYNC;
1375
1376                 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1377                         flags |= DRM_MODE_FLAG_PVSYNC;
1378                 else
1379                         flags |= DRM_MODE_FLAG_NVSYNC;
1380         }
1381
1382         pipe_config->adjusted_mode.flags |= flags;
1383
1384         if (dp_to_dig_port(intel_dp)->port == PORT_A) {
1385                 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1386                         pipe_config->port_clock = 162000;
1387                 else
1388                         pipe_config->port_clock = 270000;
1389         }
1390 }
1391
1392 static bool is_edp_psr(struct intel_dp *intel_dp)
1393 {
1394         return is_edp(intel_dp) &&
1395                 intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
1396 }
1397
1398 static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1399 {
1400         struct drm_i915_private *dev_priv = dev->dev_private;
1401
1402         if (!IS_HASWELL(dev))
1403                 return false;
1404
1405         return I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
1406 }
1407
1408 static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1409                                     struct edp_vsc_psr *vsc_psr)
1410 {
1411         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1412         struct drm_device *dev = dig_port->base.base.dev;
1413         struct drm_i915_private *dev_priv = dev->dev_private;
1414         struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1415         u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1416         u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1417         uint32_t *data = (uint32_t *) vsc_psr;
1418         unsigned int i;
1419
1420         /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1421            the video DIP being updated before program video DIP data buffer
1422            registers for DIP being updated. */
1423         I915_WRITE(ctl_reg, 0);
1424         POSTING_READ(ctl_reg);
1425
1426         for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1427                 if (i < sizeof(struct edp_vsc_psr))
1428                         I915_WRITE(data_reg + i, *data++);
1429                 else
1430                         I915_WRITE(data_reg + i, 0);
1431         }
1432
1433         I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1434         POSTING_READ(ctl_reg);
1435 }
1436
1437 static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1438 {
1439         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1440         struct drm_i915_private *dev_priv = dev->dev_private;
1441         struct edp_vsc_psr psr_vsc;
1442
1443         if (intel_dp->psr_setup_done)
1444                 return;
1445
1446         /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1447         memset(&psr_vsc, 0, sizeof(psr_vsc));
1448         psr_vsc.sdp_header.HB0 = 0;
1449         psr_vsc.sdp_header.HB1 = 0x7;
1450         psr_vsc.sdp_header.HB2 = 0x2;
1451         psr_vsc.sdp_header.HB3 = 0x8;
1452         intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1453
1454         /* Avoid continuous PSR exit by masking memup and hpd */
1455         I915_WRITE(EDP_PSR_DEBUG_CTL, EDP_PSR_DEBUG_MASK_MEMUP |
1456                    EDP_PSR_DEBUG_MASK_HPD);
1457
1458         intel_dp->psr_setup_done = true;
1459 }
1460
1461 static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1462 {
1463         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1464         struct drm_i915_private *dev_priv = dev->dev_private;
1465         uint32_t aux_clock_divider = get_aux_clock_divider(intel_dp, 0);
1466         int precharge = 0x3;
1467         int msg_size = 5;       /* Header(4) + Message(1) */
1468
1469         /* Enable PSR in sink */
1470         if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT)
1471                 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1472                                             DP_PSR_ENABLE &
1473                                             ~DP_PSR_MAIN_LINK_ACTIVE);
1474         else
1475                 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1476                                             DP_PSR_ENABLE |
1477                                             DP_PSR_MAIN_LINK_ACTIVE);
1478
1479         /* Setup AUX registers */
1480         I915_WRITE(EDP_PSR_AUX_DATA1, EDP_PSR_DPCD_COMMAND);
1481         I915_WRITE(EDP_PSR_AUX_DATA2, EDP_PSR_DPCD_NORMAL_OPERATION);
1482         I915_WRITE(EDP_PSR_AUX_CTL,
1483                    DP_AUX_CH_CTL_TIME_OUT_400us |
1484                    (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1485                    (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1486                    (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1487 }
1488
1489 static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1490 {
1491         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1492         struct drm_i915_private *dev_priv = dev->dev_private;
1493         uint32_t max_sleep_time = 0x1f;
1494         uint32_t idle_frames = 1;
1495         uint32_t val = 0x0;
1496
1497         if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
1498                 val |= EDP_PSR_LINK_STANDBY;
1499                 val |= EDP_PSR_TP2_TP3_TIME_0us;
1500                 val |= EDP_PSR_TP1_TIME_0us;
1501                 val |= EDP_PSR_SKIP_AUX_EXIT;
1502         } else
1503                 val |= EDP_PSR_LINK_DISABLE;
1504
1505         I915_WRITE(EDP_PSR_CTL, val |
1506                    EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES |
1507                    max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1508                    idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1509                    EDP_PSR_ENABLE);
1510 }
1511
1512 static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1513 {
1514         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1515         struct drm_device *dev = dig_port->base.base.dev;
1516         struct drm_i915_private *dev_priv = dev->dev_private;
1517         struct drm_crtc *crtc = dig_port->base.base.crtc;
1518         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1519         struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->fb)->obj;
1520         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
1521
1522         if (!IS_HASWELL(dev)) {
1523                 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1524                 dev_priv->no_psr_reason = PSR_NO_SOURCE;
1525                 return false;
1526         }
1527
1528         if ((intel_encoder->type != INTEL_OUTPUT_EDP) ||
1529             (dig_port->port != PORT_A)) {
1530                 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
1531                 dev_priv->no_psr_reason = PSR_HSW_NOT_DDIA;
1532                 return false;
1533         }
1534
1535         if (!is_edp_psr(intel_dp)) {
1536                 DRM_DEBUG_KMS("PSR not supported by this panel\n");
1537                 dev_priv->no_psr_reason = PSR_NO_SINK;
1538                 return false;
1539         }
1540
1541         if (!i915_enable_psr) {
1542                 DRM_DEBUG_KMS("PSR disable by flag\n");
1543                 dev_priv->no_psr_reason = PSR_MODULE_PARAM;
1544                 return false;
1545         }
1546
1547         crtc = dig_port->base.base.crtc;
1548         if (crtc == NULL) {
1549                 DRM_DEBUG_KMS("crtc not active for PSR\n");
1550                 dev_priv->no_psr_reason = PSR_CRTC_NOT_ACTIVE;
1551                 return false;
1552         }
1553
1554         intel_crtc = to_intel_crtc(crtc);
1555         if (!intel_crtc->active || !crtc->fb || !crtc->mode.clock) {
1556                 DRM_DEBUG_KMS("crtc not active for PSR\n");
1557                 dev_priv->no_psr_reason = PSR_CRTC_NOT_ACTIVE;
1558                 return false;
1559         }
1560
1561         obj = to_intel_framebuffer(crtc->fb)->obj;
1562         if (obj->tiling_mode != I915_TILING_X ||
1563             obj->fence_reg == I915_FENCE_REG_NONE) {
1564                 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
1565                 dev_priv->no_psr_reason = PSR_NOT_TILED;
1566                 return false;
1567         }
1568
1569         if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
1570                 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
1571                 dev_priv->no_psr_reason = PSR_SPRITE_ENABLED;
1572                 return false;
1573         }
1574
1575         if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1576             S3D_ENABLE) {
1577                 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
1578                 dev_priv->no_psr_reason = PSR_S3D_ENABLED;
1579                 return false;
1580         }
1581
1582         if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) {
1583                 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
1584                 dev_priv->no_psr_reason = PSR_INTERLACED_ENABLED;
1585                 return false;
1586         }
1587
1588         return true;
1589 }
1590
1591 static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
1592 {
1593         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1594
1595         if (!intel_edp_psr_match_conditions(intel_dp) ||
1596             intel_edp_is_psr_enabled(dev))
1597                 return;
1598
1599         /* Setup PSR once */
1600         intel_edp_psr_setup(intel_dp);
1601
1602         /* Enable PSR on the panel */
1603         intel_edp_psr_enable_sink(intel_dp);
1604
1605         /* Enable PSR on the host */
1606         intel_edp_psr_enable_source(intel_dp);
1607 }
1608
1609 void intel_edp_psr_enable(struct intel_dp *intel_dp)
1610 {
1611         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1612
1613         if (intel_edp_psr_match_conditions(intel_dp) &&
1614             !intel_edp_is_psr_enabled(dev))
1615                 intel_edp_psr_do_enable(intel_dp);
1616 }
1617
1618 void intel_edp_psr_disable(struct intel_dp *intel_dp)
1619 {
1620         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1621         struct drm_i915_private *dev_priv = dev->dev_private;
1622
1623         if (!intel_edp_is_psr_enabled(dev))
1624                 return;
1625
1626         I915_WRITE(EDP_PSR_CTL, I915_READ(EDP_PSR_CTL) & ~EDP_PSR_ENABLE);
1627
1628         /* Wait till PSR is idle */
1629         if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL) &
1630                        EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1631                 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1632 }
1633
1634 void intel_edp_psr_update(struct drm_device *dev)
1635 {
1636         struct intel_encoder *encoder;
1637         struct intel_dp *intel_dp = NULL;
1638
1639         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
1640                 if (encoder->type == INTEL_OUTPUT_EDP) {
1641                         intel_dp = enc_to_intel_dp(&encoder->base);
1642
1643                         if (!is_edp_psr(intel_dp))
1644                                 return;
1645
1646                         if (!intel_edp_psr_match_conditions(intel_dp))
1647                                 intel_edp_psr_disable(intel_dp);
1648                         else
1649                                 if (!intel_edp_is_psr_enabled(dev))
1650                                         intel_edp_psr_do_enable(intel_dp);
1651                 }
1652 }
1653
1654 static void intel_disable_dp(struct intel_encoder *encoder)
1655 {
1656         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1657         enum port port = dp_to_dig_port(intel_dp)->port;
1658         struct drm_device *dev = encoder->base.dev;
1659
1660         /* Make sure the panel is off before trying to change the mode. But also
1661          * ensure that we have vdd while we switch off the panel. */
1662         ironlake_edp_panel_vdd_on(intel_dp);
1663         ironlake_edp_backlight_off(intel_dp);
1664         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1665         ironlake_edp_panel_off(intel_dp);
1666
1667         /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1668         if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
1669                 intel_dp_link_down(intel_dp);
1670 }
1671
1672 static void intel_post_disable_dp(struct intel_encoder *encoder)
1673 {
1674         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1675         enum port port = dp_to_dig_port(intel_dp)->port;
1676         struct drm_device *dev = encoder->base.dev;
1677
1678         if (port == PORT_A || IS_VALLEYVIEW(dev)) {
1679                 intel_dp_link_down(intel_dp);
1680                 if (!IS_VALLEYVIEW(dev))
1681                         ironlake_edp_pll_off(intel_dp);
1682         }
1683 }
1684
1685 static void intel_enable_dp(struct intel_encoder *encoder)
1686 {
1687         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1688         struct drm_device *dev = encoder->base.dev;
1689         struct drm_i915_private *dev_priv = dev->dev_private;
1690         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1691
1692         if (WARN_ON(dp_reg & DP_PORT_EN))
1693                 return;
1694
1695         ironlake_edp_panel_vdd_on(intel_dp);
1696         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1697         intel_dp_start_link_train(intel_dp);
1698         ironlake_edp_panel_on(intel_dp);
1699         ironlake_edp_panel_vdd_off(intel_dp, true);
1700         intel_dp_complete_link_train(intel_dp);
1701         intel_dp_stop_link_train(intel_dp);
1702         ironlake_edp_backlight_on(intel_dp);
1703 }
1704
1705 static void vlv_enable_dp(struct intel_encoder *encoder)
1706 {
1707 }
1708
1709 static void intel_pre_enable_dp(struct intel_encoder *encoder)
1710 {
1711         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1712         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1713
1714         if (dport->port == PORT_A)
1715                 ironlake_edp_pll_on(intel_dp);
1716 }
1717
1718 static void vlv_pre_enable_dp(struct intel_encoder *encoder)
1719 {
1720         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1721         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1722         struct drm_device *dev = encoder->base.dev;
1723         struct drm_i915_private *dev_priv = dev->dev_private;
1724         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1725         int port = vlv_dport_to_channel(dport);
1726         int pipe = intel_crtc->pipe;
1727         u32 val;
1728
1729         mutex_lock(&dev_priv->dpio_lock);
1730
1731         val = vlv_dpio_read(dev_priv, DPIO_DATA_LANE_A(port));
1732         val = 0;
1733         if (pipe)
1734                 val |= (1<<21);
1735         else
1736                 val &= ~(1<<21);
1737         val |= 0x001000c4;
1738         vlv_dpio_write(dev_priv, DPIO_DATA_CHANNEL(port), val);
1739         vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF0(port), 0x00760018);
1740         vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF8(port), 0x00400888);
1741
1742         mutex_unlock(&dev_priv->dpio_lock);
1743
1744         intel_enable_dp(encoder);
1745
1746         vlv_wait_port_ready(dev_priv, port);
1747 }
1748
1749 static void intel_dp_pre_pll_enable(struct intel_encoder *encoder)
1750 {
1751         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1752         struct drm_device *dev = encoder->base.dev;
1753         struct drm_i915_private *dev_priv = dev->dev_private;
1754         int port = vlv_dport_to_channel(dport);
1755
1756         if (!IS_VALLEYVIEW(dev))
1757                 return;
1758
1759         /* Program Tx lane resets to default */
1760         mutex_lock(&dev_priv->dpio_lock);
1761         vlv_dpio_write(dev_priv, DPIO_PCS_TX(port),
1762                          DPIO_PCS_TX_LANE2_RESET |
1763                          DPIO_PCS_TX_LANE1_RESET);
1764         vlv_dpio_write(dev_priv, DPIO_PCS_CLK(port),
1765                          DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1766                          DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1767                          (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1768                                  DPIO_PCS_CLK_SOFT_RESET);
1769
1770         /* Fix up inter-pair skew failure */
1771         vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER1(port), 0x00750f00);
1772         vlv_dpio_write(dev_priv, DPIO_TX_CTL(port), 0x00001500);
1773         vlv_dpio_write(dev_priv, DPIO_TX_LANE(port), 0x40400000);
1774         mutex_unlock(&dev_priv->dpio_lock);
1775 }
1776
1777 /*
1778  * Native read with retry for link status and receiver capability reads for
1779  * cases where the sink may still be asleep.
1780  */
1781 static bool
1782 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1783                                uint8_t *recv, int recv_bytes)
1784 {
1785         int ret, i;
1786
1787         /*
1788          * Sinks are *supposed* to come up within 1ms from an off state,
1789          * but we're also supposed to retry 3 times per the spec.
1790          */
1791         for (i = 0; i < 3; i++) {
1792                 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1793                                                recv_bytes);
1794                 if (ret == recv_bytes)
1795                         return true;
1796                 msleep(1);
1797         }
1798
1799         return false;
1800 }
1801
1802 /*
1803  * Fetch AUX CH registers 0x202 - 0x207 which contain
1804  * link status information
1805  */
1806 static bool
1807 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1808 {
1809         return intel_dp_aux_native_read_retry(intel_dp,
1810                                               DP_LANE0_1_STATUS,
1811                                               link_status,
1812                                               DP_LINK_STATUS_SIZE);
1813 }
1814
1815 #if 0
1816 static char     *voltage_names[] = {
1817         "0.4V", "0.6V", "0.8V", "1.2V"
1818 };
1819 static char     *pre_emph_names[] = {
1820         "0dB", "3.5dB", "6dB", "9.5dB"
1821 };
1822 static char     *link_train_names[] = {
1823         "pattern 1", "pattern 2", "idle", "off"
1824 };
1825 #endif
1826
1827 /*
1828  * These are source-specific values; current Intel hardware supports
1829  * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1830  */
1831
1832 static uint8_t
1833 intel_dp_voltage_max(struct intel_dp *intel_dp)
1834 {
1835         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1836         enum port port = dp_to_dig_port(intel_dp)->port;
1837
1838         if (IS_VALLEYVIEW(dev))
1839                 return DP_TRAIN_VOLTAGE_SWING_1200;
1840         else if (IS_GEN7(dev) && port == PORT_A)
1841                 return DP_TRAIN_VOLTAGE_SWING_800;
1842         else if (HAS_PCH_CPT(dev) && port != PORT_A)
1843                 return DP_TRAIN_VOLTAGE_SWING_1200;
1844         else
1845                 return DP_TRAIN_VOLTAGE_SWING_800;
1846 }
1847
1848 static uint8_t
1849 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1850 {
1851         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1852         enum port port = dp_to_dig_port(intel_dp)->port;
1853
1854         if (HAS_DDI(dev)) {
1855                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1856                 case DP_TRAIN_VOLTAGE_SWING_400:
1857                         return DP_TRAIN_PRE_EMPHASIS_9_5;
1858                 case DP_TRAIN_VOLTAGE_SWING_600:
1859                         return DP_TRAIN_PRE_EMPHASIS_6;
1860                 case DP_TRAIN_VOLTAGE_SWING_800:
1861                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1862                 case DP_TRAIN_VOLTAGE_SWING_1200:
1863                 default:
1864                         return DP_TRAIN_PRE_EMPHASIS_0;
1865                 }
1866         } else if (IS_VALLEYVIEW(dev)) {
1867                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1868                 case DP_TRAIN_VOLTAGE_SWING_400:
1869                         return DP_TRAIN_PRE_EMPHASIS_9_5;
1870                 case DP_TRAIN_VOLTAGE_SWING_600:
1871                         return DP_TRAIN_PRE_EMPHASIS_6;
1872                 case DP_TRAIN_VOLTAGE_SWING_800:
1873                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1874                 case DP_TRAIN_VOLTAGE_SWING_1200:
1875                 default:
1876                         return DP_TRAIN_PRE_EMPHASIS_0;
1877                 }
1878         } else if (IS_GEN7(dev) && port == PORT_A) {
1879                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1880                 case DP_TRAIN_VOLTAGE_SWING_400:
1881                         return DP_TRAIN_PRE_EMPHASIS_6;
1882                 case DP_TRAIN_VOLTAGE_SWING_600:
1883                 case DP_TRAIN_VOLTAGE_SWING_800:
1884                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1885                 default:
1886                         return DP_TRAIN_PRE_EMPHASIS_0;
1887                 }
1888         } else {
1889                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1890                 case DP_TRAIN_VOLTAGE_SWING_400:
1891                         return DP_TRAIN_PRE_EMPHASIS_6;
1892                 case DP_TRAIN_VOLTAGE_SWING_600:
1893                         return DP_TRAIN_PRE_EMPHASIS_6;
1894                 case DP_TRAIN_VOLTAGE_SWING_800:
1895                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1896                 case DP_TRAIN_VOLTAGE_SWING_1200:
1897                 default:
1898                         return DP_TRAIN_PRE_EMPHASIS_0;
1899                 }
1900         }
1901 }
1902
1903 static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
1904 {
1905         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1906         struct drm_i915_private *dev_priv = dev->dev_private;
1907         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1908         unsigned long demph_reg_value, preemph_reg_value,
1909                 uniqtranscale_reg_value;
1910         uint8_t train_set = intel_dp->train_set[0];
1911         int port = vlv_dport_to_channel(dport);
1912
1913         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1914         case DP_TRAIN_PRE_EMPHASIS_0:
1915                 preemph_reg_value = 0x0004000;
1916                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1917                 case DP_TRAIN_VOLTAGE_SWING_400:
1918                         demph_reg_value = 0x2B405555;
1919                         uniqtranscale_reg_value = 0x552AB83A;
1920                         break;
1921                 case DP_TRAIN_VOLTAGE_SWING_600:
1922                         demph_reg_value = 0x2B404040;
1923                         uniqtranscale_reg_value = 0x5548B83A;
1924                         break;
1925                 case DP_TRAIN_VOLTAGE_SWING_800:
1926                         demph_reg_value = 0x2B245555;
1927                         uniqtranscale_reg_value = 0x5560B83A;
1928                         break;
1929                 case DP_TRAIN_VOLTAGE_SWING_1200:
1930                         demph_reg_value = 0x2B405555;
1931                         uniqtranscale_reg_value = 0x5598DA3A;
1932                         break;
1933                 default:
1934                         return 0;
1935                 }
1936                 break;
1937         case DP_TRAIN_PRE_EMPHASIS_3_5:
1938                 preemph_reg_value = 0x0002000;
1939                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1940                 case DP_TRAIN_VOLTAGE_SWING_400:
1941                         demph_reg_value = 0x2B404040;
1942                         uniqtranscale_reg_value = 0x5552B83A;
1943                         break;
1944                 case DP_TRAIN_VOLTAGE_SWING_600:
1945                         demph_reg_value = 0x2B404848;
1946                         uniqtranscale_reg_value = 0x5580B83A;
1947                         break;
1948                 case DP_TRAIN_VOLTAGE_SWING_800:
1949                         demph_reg_value = 0x2B404040;
1950                         uniqtranscale_reg_value = 0x55ADDA3A;
1951                         break;
1952                 default:
1953                         return 0;
1954                 }
1955                 break;
1956         case DP_TRAIN_PRE_EMPHASIS_6:
1957                 preemph_reg_value = 0x0000000;
1958                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1959                 case DP_TRAIN_VOLTAGE_SWING_400:
1960                         demph_reg_value = 0x2B305555;
1961                         uniqtranscale_reg_value = 0x5570B83A;
1962                         break;
1963                 case DP_TRAIN_VOLTAGE_SWING_600:
1964                         demph_reg_value = 0x2B2B4040;
1965                         uniqtranscale_reg_value = 0x55ADDA3A;
1966                         break;
1967                 default:
1968                         return 0;
1969                 }
1970                 break;
1971         case DP_TRAIN_PRE_EMPHASIS_9_5:
1972                 preemph_reg_value = 0x0006000;
1973                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1974                 case DP_TRAIN_VOLTAGE_SWING_400:
1975                         demph_reg_value = 0x1B405555;
1976                         uniqtranscale_reg_value = 0x55ADDA3A;
1977                         break;
1978                 default:
1979                         return 0;
1980                 }
1981                 break;
1982         default:
1983                 return 0;
1984         }
1985
1986         mutex_lock(&dev_priv->dpio_lock);
1987         vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x00000000);
1988         vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL4(port), demph_reg_value);
1989         vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL2(port),
1990                          uniqtranscale_reg_value);
1991         vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL3(port), 0x0C782040);
1992         vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER0(port), 0x00030000);
1993         vlv_dpio_write(dev_priv, DPIO_PCS_CTL_OVER1(port), preemph_reg_value);
1994         vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x80000000);
1995         mutex_unlock(&dev_priv->dpio_lock);
1996
1997         return 0;
1998 }
1999
2000 static void
2001 intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
2002 {
2003         uint8_t v = 0;
2004         uint8_t p = 0;
2005         int lane;
2006         uint8_t voltage_max;
2007         uint8_t preemph_max;
2008
2009         for (lane = 0; lane < intel_dp->lane_count; lane++) {
2010                 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2011                 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
2012
2013                 if (this_v > v)
2014                         v = this_v;
2015                 if (this_p > p)
2016                         p = this_p;
2017         }
2018
2019         voltage_max = intel_dp_voltage_max(intel_dp);
2020         if (v >= voltage_max)
2021                 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
2022
2023         preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2024         if (p >= preemph_max)
2025                 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
2026
2027         for (lane = 0; lane < 4; lane++)
2028                 intel_dp->train_set[lane] = v | p;
2029 }
2030
2031 static uint32_t
2032 intel_gen4_signal_levels(uint8_t train_set)
2033 {
2034         uint32_t        signal_levels = 0;
2035
2036         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2037         case DP_TRAIN_VOLTAGE_SWING_400:
2038         default:
2039                 signal_levels |= DP_VOLTAGE_0_4;
2040                 break;
2041         case DP_TRAIN_VOLTAGE_SWING_600:
2042                 signal_levels |= DP_VOLTAGE_0_6;
2043                 break;
2044         case DP_TRAIN_VOLTAGE_SWING_800:
2045                 signal_levels |= DP_VOLTAGE_0_8;
2046                 break;
2047         case DP_TRAIN_VOLTAGE_SWING_1200:
2048                 signal_levels |= DP_VOLTAGE_1_2;
2049                 break;
2050         }
2051         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2052         case DP_TRAIN_PRE_EMPHASIS_0:
2053         default:
2054                 signal_levels |= DP_PRE_EMPHASIS_0;
2055                 break;
2056         case DP_TRAIN_PRE_EMPHASIS_3_5:
2057                 signal_levels |= DP_PRE_EMPHASIS_3_5;
2058                 break;
2059         case DP_TRAIN_PRE_EMPHASIS_6:
2060                 signal_levels |= DP_PRE_EMPHASIS_6;
2061                 break;
2062         case DP_TRAIN_PRE_EMPHASIS_9_5:
2063                 signal_levels |= DP_PRE_EMPHASIS_9_5;
2064                 break;
2065         }
2066         return signal_levels;
2067 }
2068
2069 /* Gen6's DP voltage swing and pre-emphasis control */
2070 static uint32_t
2071 intel_gen6_edp_signal_levels(uint8_t train_set)
2072 {
2073         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2074                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2075         switch (signal_levels) {
2076         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2077         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2078                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2079         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2080                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
2081         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2082         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2083                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
2084         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2085         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2086                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
2087         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2088         case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2089                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
2090         default:
2091                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2092                               "0x%x\n", signal_levels);
2093                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2094         }
2095 }
2096
2097 /* Gen7's DP voltage swing and pre-emphasis control */
2098 static uint32_t
2099 intel_gen7_edp_signal_levels(uint8_t train_set)
2100 {
2101         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2102                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2103         switch (signal_levels) {
2104         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2105                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2106         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2107                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2108         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2109                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2110
2111         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2112                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2113         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2114                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2115
2116         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2117                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2118         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2119                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2120
2121         default:
2122                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2123                               "0x%x\n", signal_levels);
2124                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2125         }
2126 }
2127
2128 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2129 static uint32_t
2130 intel_hsw_signal_levels(uint8_t train_set)
2131 {
2132         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2133                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2134         switch (signal_levels) {
2135         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2136                 return DDI_BUF_EMP_400MV_0DB_HSW;
2137         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2138                 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2139         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2140                 return DDI_BUF_EMP_400MV_6DB_HSW;
2141         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2142                 return DDI_BUF_EMP_400MV_9_5DB_HSW;
2143
2144         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2145                 return DDI_BUF_EMP_600MV_0DB_HSW;
2146         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2147                 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2148         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2149                 return DDI_BUF_EMP_600MV_6DB_HSW;
2150
2151         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2152                 return DDI_BUF_EMP_800MV_0DB_HSW;
2153         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2154                 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2155         default:
2156                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2157                               "0x%x\n", signal_levels);
2158                 return DDI_BUF_EMP_400MV_0DB_HSW;
2159         }
2160 }
2161
2162 /* Properly updates "DP" with the correct signal levels. */
2163 static void
2164 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2165 {
2166         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2167         enum port port = intel_dig_port->port;
2168         struct drm_device *dev = intel_dig_port->base.base.dev;
2169         uint32_t signal_levels, mask;
2170         uint8_t train_set = intel_dp->train_set[0];
2171
2172         if (HAS_DDI(dev)) {
2173                 signal_levels = intel_hsw_signal_levels(train_set);
2174                 mask = DDI_BUF_EMP_MASK;
2175         } else if (IS_VALLEYVIEW(dev)) {
2176                 signal_levels = intel_vlv_signal_levels(intel_dp);
2177                 mask = 0;
2178         } else if (IS_GEN7(dev) && port == PORT_A) {
2179                 signal_levels = intel_gen7_edp_signal_levels(train_set);
2180                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
2181         } else if (IS_GEN6(dev) && port == PORT_A) {
2182                 signal_levels = intel_gen6_edp_signal_levels(train_set);
2183                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2184         } else {
2185                 signal_levels = intel_gen4_signal_levels(train_set);
2186                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2187         }
2188
2189         DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2190
2191         *DP = (*DP & ~mask) | signal_levels;
2192 }
2193
2194 static bool
2195 intel_dp_set_link_train(struct intel_dp *intel_dp,
2196                         uint32_t dp_reg_value,
2197                         uint8_t dp_train_pat)
2198 {
2199         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2200         struct drm_device *dev = intel_dig_port->base.base.dev;
2201         struct drm_i915_private *dev_priv = dev->dev_private;
2202         enum port port = intel_dig_port->port;
2203         int ret;
2204
2205         if (HAS_DDI(dev)) {
2206                 uint32_t temp = I915_READ(DP_TP_CTL(port));
2207
2208                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2209                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2210                 else
2211                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2212
2213                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2214                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2215                 case DP_TRAINING_PATTERN_DISABLE:
2216                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2217
2218                         break;
2219                 case DP_TRAINING_PATTERN_1:
2220                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2221                         break;
2222                 case DP_TRAINING_PATTERN_2:
2223                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2224                         break;
2225                 case DP_TRAINING_PATTERN_3:
2226                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2227                         break;
2228                 }
2229                 I915_WRITE(DP_TP_CTL(port), temp);
2230
2231         } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2232                 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
2233
2234                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2235                 case DP_TRAINING_PATTERN_DISABLE:
2236                         dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
2237                         break;
2238                 case DP_TRAINING_PATTERN_1:
2239                         dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
2240                         break;
2241                 case DP_TRAINING_PATTERN_2:
2242                         dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
2243                         break;
2244                 case DP_TRAINING_PATTERN_3:
2245                         DRM_ERROR("DP training pattern 3 not supported\n");
2246                         dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
2247                         break;
2248                 }
2249
2250         } else {
2251                 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
2252
2253                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2254                 case DP_TRAINING_PATTERN_DISABLE:
2255                         dp_reg_value |= DP_LINK_TRAIN_OFF;
2256                         break;
2257                 case DP_TRAINING_PATTERN_1:
2258                         dp_reg_value |= DP_LINK_TRAIN_PAT_1;
2259                         break;
2260                 case DP_TRAINING_PATTERN_2:
2261                         dp_reg_value |= DP_LINK_TRAIN_PAT_2;
2262                         break;
2263                 case DP_TRAINING_PATTERN_3:
2264                         DRM_ERROR("DP training pattern 3 not supported\n");
2265                         dp_reg_value |= DP_LINK_TRAIN_PAT_2;
2266                         break;
2267                 }
2268         }
2269
2270         I915_WRITE(intel_dp->output_reg, dp_reg_value);
2271         POSTING_READ(intel_dp->output_reg);
2272
2273         intel_dp_aux_native_write_1(intel_dp,
2274                                     DP_TRAINING_PATTERN_SET,
2275                                     dp_train_pat);
2276
2277         if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
2278             DP_TRAINING_PATTERN_DISABLE) {
2279                 ret = intel_dp_aux_native_write(intel_dp,
2280                                                 DP_TRAINING_LANE0_SET,
2281                                                 intel_dp->train_set,
2282                                                 intel_dp->lane_count);
2283                 if (ret != intel_dp->lane_count)
2284                         return false;
2285         }
2286
2287         return true;
2288 }
2289
2290 static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
2291 {
2292         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2293         struct drm_device *dev = intel_dig_port->base.base.dev;
2294         struct drm_i915_private *dev_priv = dev->dev_private;
2295         enum port port = intel_dig_port->port;
2296         uint32_t val;
2297
2298         if (!HAS_DDI(dev))
2299                 return;
2300
2301         val = I915_READ(DP_TP_CTL(port));
2302         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2303         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
2304         I915_WRITE(DP_TP_CTL(port), val);
2305
2306         /*
2307          * On PORT_A we can have only eDP in SST mode. There the only reason
2308          * we need to set idle transmission mode is to work around a HW issue
2309          * where we enable the pipe while not in idle link-training mode.
2310          * In this case there is requirement to wait for a minimum number of
2311          * idle patterns to be sent.
2312          */
2313         if (port == PORT_A)
2314                 return;
2315
2316         if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2317                      1))
2318                 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2319 }
2320
2321 /* Enable corresponding port and start training pattern 1 */
2322 void
2323 intel_dp_start_link_train(struct intel_dp *intel_dp)
2324 {
2325         struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
2326         struct drm_device *dev = encoder->dev;
2327         int i;
2328         uint8_t voltage;
2329         bool clock_recovery = false;
2330         int voltage_tries, loop_tries;
2331         uint32_t DP = intel_dp->DP;
2332
2333         if (HAS_DDI(dev))
2334                 intel_ddi_prepare_link_retrain(encoder);
2335
2336         /* Write the link configuration data */
2337         intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
2338                                   intel_dp->link_configuration,
2339                                   DP_LINK_CONFIGURATION_SIZE);
2340
2341         DP |= DP_PORT_EN;
2342
2343         memset(intel_dp->train_set, 0, 4);
2344         voltage = 0xff;
2345         voltage_tries = 0;
2346         loop_tries = 0;
2347         clock_recovery = false;
2348         for (;;) {
2349                 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
2350                 uint8_t     link_status[DP_LINK_STATUS_SIZE];
2351
2352                 intel_dp_set_signal_levels(intel_dp, &DP);
2353
2354                 /* Set training pattern 1 */
2355                 if (!intel_dp_set_link_train(intel_dp, DP,
2356                                              DP_TRAINING_PATTERN_1 |
2357                                              DP_LINK_SCRAMBLING_DISABLE))
2358                         break;
2359
2360                 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
2361                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2362                         DRM_ERROR("failed to get link status\n");
2363                         break;
2364                 }
2365
2366                 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2367                         DRM_DEBUG_KMS("clock recovery OK\n");
2368                         clock_recovery = true;
2369                         break;
2370                 }
2371
2372                 /* Check to see if we've tried the max voltage */
2373                 for (i = 0; i < intel_dp->lane_count; i++)
2374                         if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
2375                                 break;
2376                 if (i == intel_dp->lane_count) {
2377                         ++loop_tries;
2378                         if (loop_tries == 5) {
2379                                 DRM_DEBUG_KMS("too many full retries, give up\n");
2380                                 break;
2381                         }
2382                         memset(intel_dp->train_set, 0, 4);
2383                         voltage_tries = 0;
2384                         continue;
2385                 }
2386
2387                 /* Check to see if we've tried the same voltage 5 times */
2388                 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
2389                         ++voltage_tries;
2390                         if (voltage_tries == 5) {
2391                                 DRM_DEBUG_KMS("too many voltage retries, give up\n");
2392                                 break;
2393                         }
2394                 } else
2395                         voltage_tries = 0;
2396                 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
2397
2398                 /* Compute new intel_dp->train_set as requested by target */
2399                 intel_get_adjust_train(intel_dp, link_status);
2400         }
2401
2402         intel_dp->DP = DP;
2403 }
2404
2405 void
2406 intel_dp_complete_link_train(struct intel_dp *intel_dp)
2407 {
2408         bool channel_eq = false;
2409         int tries, cr_tries;
2410         uint32_t DP = intel_dp->DP;
2411
2412         /* channel equalization */
2413         tries = 0;
2414         cr_tries = 0;
2415         channel_eq = false;
2416         for (;;) {
2417                 uint8_t     link_status[DP_LINK_STATUS_SIZE];
2418
2419                 if (cr_tries > 5) {
2420                         DRM_ERROR("failed to train DP, aborting\n");
2421                         intel_dp_link_down(intel_dp);
2422                         break;
2423                 }
2424
2425                 intel_dp_set_signal_levels(intel_dp, &DP);
2426
2427                 /* channel eq pattern */
2428                 if (!intel_dp_set_link_train(intel_dp, DP,
2429                                              DP_TRAINING_PATTERN_2 |
2430                                              DP_LINK_SCRAMBLING_DISABLE))
2431                         break;
2432
2433                 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
2434                 if (!intel_dp_get_link_status(intel_dp, link_status))
2435                         break;
2436
2437                 /* Make sure clock is still ok */
2438                 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2439                         intel_dp_start_link_train(intel_dp);
2440                         cr_tries++;
2441                         continue;
2442                 }
2443
2444                 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2445                         channel_eq = true;
2446                         break;
2447                 }
2448
2449                 /* Try 5 times, then try clock recovery if that fails */
2450                 if (tries > 5) {
2451                         intel_dp_link_down(intel_dp);
2452                         intel_dp_start_link_train(intel_dp);
2453                         tries = 0;
2454                         cr_tries++;
2455                         continue;
2456                 }
2457
2458                 /* Compute new intel_dp->train_set as requested by target */
2459                 intel_get_adjust_train(intel_dp, link_status);
2460                 ++tries;
2461         }
2462
2463         intel_dp_set_idle_link_train(intel_dp);
2464
2465         intel_dp->DP = DP;
2466
2467         if (channel_eq)
2468                 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
2469
2470 }
2471
2472 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
2473 {
2474         intel_dp_set_link_train(intel_dp, intel_dp->DP,
2475                                 DP_TRAINING_PATTERN_DISABLE);
2476 }
2477
2478 static void
2479 intel_dp_link_down(struct intel_dp *intel_dp)
2480 {
2481         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2482         enum port port = intel_dig_port->port;
2483         struct drm_device *dev = intel_dig_port->base.base.dev;
2484         struct drm_i915_private *dev_priv = dev->dev_private;
2485         struct intel_crtc *intel_crtc =
2486                 to_intel_crtc(intel_dig_port->base.base.crtc);
2487         uint32_t DP = intel_dp->DP;
2488
2489         /*
2490          * DDI code has a strict mode set sequence and we should try to respect
2491          * it, otherwise we might hang the machine in many different ways. So we
2492          * really should be disabling the port only on a complete crtc_disable
2493          * sequence. This function is just called under two conditions on DDI
2494          * code:
2495          * - Link train failed while doing crtc_enable, and on this case we
2496          *   really should respect the mode set sequence and wait for a
2497          *   crtc_disable.
2498          * - Someone turned the monitor off and intel_dp_check_link_status
2499          *   called us. We don't need to disable the whole port on this case, so
2500          *   when someone turns the monitor on again,
2501          *   intel_ddi_prepare_link_retrain will take care of redoing the link
2502          *   train.
2503          */
2504         if (HAS_DDI(dev))
2505                 return;
2506
2507         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
2508                 return;
2509
2510         DRM_DEBUG_KMS("\n");
2511
2512         if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2513                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
2514                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
2515         } else {
2516                 DP &= ~DP_LINK_TRAIN_MASK;
2517                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
2518         }
2519         POSTING_READ(intel_dp->output_reg);
2520
2521         /* We don't really know why we're doing this */
2522         intel_wait_for_vblank(dev, intel_crtc->pipe);
2523
2524         if (HAS_PCH_IBX(dev) &&
2525             I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
2526                 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2527
2528                 /* Hardware workaround: leaving our transcoder select
2529                  * set to transcoder B while it's off will prevent the
2530                  * corresponding HDMI output on transcoder A.
2531                  *
2532                  * Combine this with another hardware workaround:
2533                  * transcoder select bit can only be cleared while the
2534                  * port is enabled.
2535                  */
2536                 DP &= ~DP_PIPEB_SELECT;
2537                 I915_WRITE(intel_dp->output_reg, DP);
2538
2539                 /* Changes to enable or select take place the vblank
2540                  * after being written.
2541                  */
2542                 if (WARN_ON(crtc == NULL)) {
2543                         /* We should never try to disable a port without a crtc
2544                          * attached. For paranoia keep the code around for a
2545                          * bit. */
2546                         POSTING_READ(intel_dp->output_reg);
2547                         msleep(50);
2548                 } else
2549                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2550         }
2551
2552         DP &= ~DP_AUDIO_OUTPUT_ENABLE;
2553         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2554         POSTING_READ(intel_dp->output_reg);
2555         msleep(intel_dp->panel_power_down_delay);
2556 }
2557
2558 static bool
2559 intel_dp_get_dpcd(struct intel_dp *intel_dp)
2560 {
2561         char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2562
2563         if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
2564                                            sizeof(intel_dp->dpcd)) == 0)
2565                 return false; /* aux transfer failed */
2566
2567         hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2568                            32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2569         DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2570
2571         if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2572                 return false; /* DPCD not present */
2573
2574         /* Check if the panel supports PSR */
2575         memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
2576         intel_dp_aux_native_read_retry(intel_dp, DP_PSR_SUPPORT,
2577                                        intel_dp->psr_dpcd,
2578                                        sizeof(intel_dp->psr_dpcd));
2579         if (is_edp_psr(intel_dp))
2580                 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
2581         if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2582               DP_DWN_STRM_PORT_PRESENT))
2583                 return true; /* native DP sink */
2584
2585         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2586                 return true; /* no per-port downstream info */
2587
2588         if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2589                                            intel_dp->downstream_ports,
2590                                            DP_MAX_DOWNSTREAM_PORTS) == 0)
2591                 return false; /* downstream port status fetch failed */
2592
2593         return true;
2594 }
2595
2596 static void
2597 intel_dp_probe_oui(struct intel_dp *intel_dp)
2598 {
2599         u8 buf[3];
2600
2601         if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2602                 return;
2603
2604         ironlake_edp_panel_vdd_on(intel_dp);
2605
2606         if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2607                 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2608                               buf[0], buf[1], buf[2]);
2609
2610         if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2611                 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2612                               buf[0], buf[1], buf[2]);
2613
2614         ironlake_edp_panel_vdd_off(intel_dp, false);
2615 }
2616
2617 static bool
2618 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2619 {
2620         int ret;
2621
2622         ret = intel_dp_aux_native_read_retry(intel_dp,
2623                                              DP_DEVICE_SERVICE_IRQ_VECTOR,
2624                                              sink_irq_vector, 1);
2625         if (!ret)
2626                 return false;
2627
2628         return true;
2629 }
2630
2631 static void
2632 intel_dp_handle_test_request(struct intel_dp *intel_dp)
2633 {
2634         /* NAK by default */
2635         intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
2636 }
2637
2638 /*
2639  * According to DP spec
2640  * 5.1.2:
2641  *  1. Read DPCD
2642  *  2. Configure link according to Receiver Capabilities
2643  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
2644  *  4. Check link status on receipt of hot-plug interrupt
2645  */
2646
2647 void
2648 intel_dp_check_link_status(struct intel_dp *intel_dp)
2649 {
2650         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
2651         u8 sink_irq_vector;
2652         u8 link_status[DP_LINK_STATUS_SIZE];
2653
2654         if (!intel_encoder->connectors_active)
2655                 return;
2656
2657         if (WARN_ON(!intel_encoder->base.crtc))
2658                 return;
2659
2660         /* Try to read receiver status if the link appears to be up */
2661         if (!intel_dp_get_link_status(intel_dp, link_status)) {
2662                 intel_dp_link_down(intel_dp);
2663                 return;
2664         }
2665
2666         /* Now read the DPCD to see if it's actually running */
2667         if (!intel_dp_get_dpcd(intel_dp)) {
2668                 intel_dp_link_down(intel_dp);
2669                 return;
2670         }
2671
2672         /* Try to read the source of the interrupt */
2673         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2674             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2675                 /* Clear interrupt source */
2676                 intel_dp_aux_native_write_1(intel_dp,
2677                                             DP_DEVICE_SERVICE_IRQ_VECTOR,
2678                                             sink_irq_vector);
2679
2680                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2681                         intel_dp_handle_test_request(intel_dp);
2682                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2683                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2684         }
2685
2686         if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2687                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2688                               drm_get_encoder_name(&intel_encoder->base));
2689                 intel_dp_start_link_train(intel_dp);
2690                 intel_dp_complete_link_train(intel_dp);
2691                 intel_dp_stop_link_train(intel_dp);
2692         }
2693 }
2694
2695 /* XXX this is probably wrong for multiple downstream ports */
2696 static enum drm_connector_status
2697 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2698 {
2699         uint8_t *dpcd = intel_dp->dpcd;
2700         bool hpd;
2701         uint8_t type;
2702
2703         if (!intel_dp_get_dpcd(intel_dp))
2704                 return connector_status_disconnected;
2705
2706         /* if there's no downstream port, we're done */
2707         if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
2708                 return connector_status_connected;
2709
2710         /* If we're HPD-aware, SINK_COUNT changes dynamically */
2711         hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2712         if (hpd) {
2713                 uint8_t reg;
2714                 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
2715                                                     &reg, 1))
2716                         return connector_status_unknown;
2717                 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2718                                               : connector_status_disconnected;
2719         }
2720
2721         /* If no HPD, poke DDC gently */
2722         if (drm_probe_ddc(&intel_dp->adapter))
2723                 return connector_status_connected;
2724
2725         /* Well we tried, say unknown for unreliable port types */
2726         type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2727         if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2728                 return connector_status_unknown;
2729
2730         /* Anything else is out of spec, warn and ignore */
2731         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
2732         return connector_status_disconnected;
2733 }
2734
2735 static enum drm_connector_status
2736 ironlake_dp_detect(struct intel_dp *intel_dp)
2737 {
2738         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2739         struct drm_i915_private *dev_priv = dev->dev_private;
2740         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2741         enum drm_connector_status status;
2742
2743         /* Can't disconnect eDP, but you can close the lid... */
2744         if (is_edp(intel_dp)) {
2745                 status = intel_panel_detect(dev);
2746                 if (status == connector_status_unknown)
2747                         status = connector_status_connected;
2748                 return status;
2749         }
2750
2751         if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
2752                 return connector_status_disconnected;
2753
2754         return intel_dp_detect_dpcd(intel_dp);
2755 }
2756
2757 static enum drm_connector_status
2758 g4x_dp_detect(struct intel_dp *intel_dp)
2759 {
2760         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2761         struct drm_i915_private *dev_priv = dev->dev_private;
2762         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2763         uint32_t bit;
2764
2765         /* Can't disconnect eDP, but you can close the lid... */
2766         if (is_edp(intel_dp)) {
2767                 enum drm_connector_status status;
2768
2769                 status = intel_panel_detect(dev);
2770                 if (status == connector_status_unknown)
2771                         status = connector_status_connected;
2772                 return status;
2773         }
2774
2775         switch (intel_dig_port->port) {
2776         case PORT_B:
2777                 bit = PORTB_HOTPLUG_LIVE_STATUS;
2778                 break;
2779         case PORT_C:
2780                 bit = PORTC_HOTPLUG_LIVE_STATUS;
2781                 break;
2782         case PORT_D:
2783                 bit = PORTD_HOTPLUG_LIVE_STATUS;
2784                 break;
2785         default:
2786                 return connector_status_unknown;
2787         }
2788
2789         if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2790                 return connector_status_disconnected;
2791
2792         return intel_dp_detect_dpcd(intel_dp);
2793 }
2794
2795 static struct edid *
2796 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2797 {
2798         struct intel_connector *intel_connector = to_intel_connector(connector);
2799
2800         /* use cached edid if we have one */
2801         if (intel_connector->edid) {
2802                 struct edid *edid;
2803                 int size;
2804
2805                 /* invalid edid */
2806                 if (IS_ERR(intel_connector->edid))
2807                         return NULL;
2808
2809                 size = (intel_connector->edid->extensions + 1) * EDID_LENGTH;
2810                 edid = kmemdup(intel_connector->edid, size, GFP_KERNEL);
2811                 if (!edid)
2812                         return NULL;
2813
2814                 return edid;
2815         }
2816
2817         return drm_get_edid(connector, adapter);
2818 }
2819
2820 static int
2821 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2822 {
2823         struct intel_connector *intel_connector = to_intel_connector(connector);
2824
2825         /* use cached edid if we have one */
2826         if (intel_connector->edid) {
2827                 /* invalid edid */
2828                 if (IS_ERR(intel_connector->edid))
2829                         return 0;
2830
2831                 return intel_connector_update_modes(connector,
2832                                                     intel_connector->edid);
2833         }
2834
2835         return intel_ddc_get_modes(connector, adapter);
2836 }
2837
2838 static enum drm_connector_status
2839 intel_dp_detect(struct drm_connector *connector, bool force)
2840 {
2841         struct intel_dp *intel_dp = intel_attached_dp(connector);
2842         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2843         struct intel_encoder *intel_encoder = &intel_dig_port->base;
2844         struct drm_device *dev = connector->dev;
2845         enum drm_connector_status status;
2846         struct edid *edid = NULL;
2847
2848         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
2849                       connector->base.id, drm_get_connector_name(connector));
2850
2851         intel_dp->has_audio = false;
2852
2853         if (HAS_PCH_SPLIT(dev))
2854                 status = ironlake_dp_detect(intel_dp);
2855         else
2856                 status = g4x_dp_detect(intel_dp);
2857
2858         if (status != connector_status_connected)
2859                 return status;
2860
2861         intel_dp_probe_oui(intel_dp);
2862
2863         if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2864                 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
2865         } else {
2866                 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2867                 if (edid) {
2868                         intel_dp->has_audio = drm_detect_monitor_audio(edid);
2869                         kfree(edid);
2870                 }
2871         }
2872
2873         if (intel_encoder->type != INTEL_OUTPUT_EDP)
2874                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2875         return connector_status_connected;
2876 }
2877
2878 static int intel_dp_get_modes(struct drm_connector *connector)
2879 {
2880         struct intel_dp *intel_dp = intel_attached_dp(connector);
2881         struct intel_connector *intel_connector = to_intel_connector(connector);
2882         struct drm_device *dev = connector->dev;
2883         int ret;
2884
2885         /* We should parse the EDID data and find out if it has an audio sink
2886          */
2887
2888         ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
2889         if (ret)
2890                 return ret;
2891
2892         /* if eDP has no EDID, fall back to fixed mode */
2893         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
2894                 struct drm_display_mode *mode;
2895                 mode = drm_mode_duplicate(dev,
2896                                           intel_connector->panel.fixed_mode);
2897                 if (mode) {
2898                         drm_mode_probed_add(connector, mode);
2899                         return 1;
2900                 }
2901         }
2902         return 0;
2903 }
2904
2905 static bool
2906 intel_dp_detect_audio(struct drm_connector *connector)
2907 {
2908         struct intel_dp *intel_dp = intel_attached_dp(connector);
2909         struct edid *edid;
2910         bool has_audio = false;
2911
2912         edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2913         if (edid) {
2914                 has_audio = drm_detect_monitor_audio(edid);
2915                 kfree(edid);
2916         }
2917
2918         return has_audio;
2919 }
2920
2921 static int
2922 intel_dp_set_property(struct drm_connector *connector,
2923                       struct drm_property *property,
2924                       uint64_t val)
2925 {
2926         struct drm_i915_private *dev_priv = connector->dev->dev_private;
2927         struct intel_connector *intel_connector = to_intel_connector(connector);
2928         struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
2929         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2930         int ret;
2931
2932         ret = drm_object_property_set_value(&connector->base, property, val);
2933         if (ret)
2934                 return ret;
2935
2936         if (property == dev_priv->force_audio_property) {
2937                 int i = val;
2938                 bool has_audio;
2939
2940                 if (i == intel_dp->force_audio)
2941                         return 0;
2942
2943                 intel_dp->force_audio = i;
2944
2945                 if (i == HDMI_AUDIO_AUTO)
2946                         has_audio = intel_dp_detect_audio(connector);
2947                 else
2948                         has_audio = (i == HDMI_AUDIO_ON);
2949
2950                 if (has_audio == intel_dp->has_audio)
2951                         return 0;
2952
2953                 intel_dp->has_audio = has_audio;
2954                 goto done;
2955         }
2956
2957         if (property == dev_priv->broadcast_rgb_property) {
2958                 bool old_auto = intel_dp->color_range_auto;
2959                 uint32_t old_range = intel_dp->color_range;
2960
2961                 switch (val) {
2962                 case INTEL_BROADCAST_RGB_AUTO:
2963                         intel_dp->color_range_auto = true;
2964                         break;
2965                 case INTEL_BROADCAST_RGB_FULL:
2966                         intel_dp->color_range_auto = false;
2967                         intel_dp->color_range = 0;
2968                         break;
2969                 case INTEL_BROADCAST_RGB_LIMITED:
2970                         intel_dp->color_range_auto = false;
2971                         intel_dp->color_range = DP_COLOR_RANGE_16_235;
2972                         break;
2973                 default:
2974                         return -EINVAL;
2975                 }
2976
2977                 if (old_auto == intel_dp->color_range_auto &&
2978                     old_range == intel_dp->color_range)
2979                         return 0;
2980
2981                 goto done;
2982         }
2983
2984         if (is_edp(intel_dp) &&
2985             property == connector->dev->mode_config.scaling_mode_property) {
2986                 if (val == DRM_MODE_SCALE_NONE) {
2987                         DRM_DEBUG_KMS("no scaling not supported\n");
2988                         return -EINVAL;
2989                 }
2990
2991                 if (intel_connector->panel.fitting_mode == val) {
2992                         /* the eDP scaling property is not changed */
2993                         return 0;
2994                 }
2995                 intel_connector->panel.fitting_mode = val;
2996
2997                 goto done;
2998         }
2999
3000         return -EINVAL;
3001
3002 done:
3003         if (intel_encoder->base.crtc)
3004                 intel_crtc_restore_mode(intel_encoder->base.crtc);
3005
3006         return 0;
3007 }
3008
3009 static void
3010 intel_dp_connector_destroy(struct drm_connector *connector)
3011 {
3012         struct intel_connector *intel_connector = to_intel_connector(connector);
3013
3014         if (!IS_ERR_OR_NULL(intel_connector->edid))
3015                 kfree(intel_connector->edid);
3016
3017         /* Can't call is_edp() since the encoder may have been destroyed
3018          * already. */
3019         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3020                 intel_panel_fini(&intel_connector->panel);
3021
3022         drm_sysfs_connector_remove(connector);
3023         drm_connector_cleanup(connector);
3024         kfree(connector);
3025 }
3026
3027 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
3028 {
3029         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3030         struct intel_dp *intel_dp = &intel_dig_port->dp;
3031         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3032
3033         i2c_del_adapter(&intel_dp->adapter);
3034         drm_encoder_cleanup(encoder);
3035         if (is_edp(intel_dp)) {
3036                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3037                 mutex_lock(&dev->mode_config.mutex);
3038                 ironlake_panel_vdd_off_sync(intel_dp);
3039                 mutex_unlock(&dev->mode_config.mutex);
3040         }
3041         kfree(intel_dig_port);
3042 }
3043
3044 static const struct drm_connector_funcs intel_dp_connector_funcs = {
3045         .dpms = intel_connector_dpms,
3046         .detect = intel_dp_detect,
3047         .fill_modes = drm_helper_probe_single_connector_modes,
3048         .set_property = intel_dp_set_property,
3049         .destroy = intel_dp_connector_destroy,
3050 };
3051
3052 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
3053         .get_modes = intel_dp_get_modes,
3054         .mode_valid = intel_dp_mode_valid,
3055         .best_encoder = intel_best_encoder,
3056 };
3057
3058 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
3059         .destroy = intel_dp_encoder_destroy,
3060 };
3061
3062 static void
3063 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
3064 {
3065         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
3066
3067         intel_dp_check_link_status(intel_dp);
3068 }
3069
3070 /* Return which DP Port should be selected for Transcoder DP control */
3071 int
3072 intel_trans_dp_port_sel(struct drm_crtc *crtc)
3073 {
3074         struct drm_device *dev = crtc->dev;
3075         struct intel_encoder *intel_encoder;
3076         struct intel_dp *intel_dp;
3077
3078         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3079                 intel_dp = enc_to_intel_dp(&intel_encoder->base);
3080
3081                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
3082                     intel_encoder->type == INTEL_OUTPUT_EDP)
3083                         return intel_dp->output_reg;
3084         }
3085
3086         return -1;
3087 }
3088
3089 /* check the VBT to see whether the eDP is on DP-D port */
3090 bool intel_dpd_is_edp(struct drm_device *dev)
3091 {
3092         struct drm_i915_private *dev_priv = dev->dev_private;
3093         struct child_device_config *p_child;
3094         int i;
3095
3096         if (!dev_priv->vbt.child_dev_num)
3097                 return false;
3098
3099         for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
3100                 p_child = dev_priv->vbt.child_dev + i;
3101
3102                 if (p_child->dvo_port == PORT_IDPD &&
3103                     p_child->device_type == DEVICE_TYPE_eDP)
3104                         return true;
3105         }
3106         return false;
3107 }
3108
3109 static void
3110 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
3111 {
3112         struct intel_connector *intel_connector = to_intel_connector(connector);
3113
3114         intel_attach_force_audio_property(connector);
3115         intel_attach_broadcast_rgb_property(connector);
3116         intel_dp->color_range_auto = true;
3117
3118         if (is_edp(intel_dp)) {
3119                 drm_mode_create_scaling_mode_property(connector->dev);
3120                 drm_object_attach_property(
3121                         &connector->base,
3122                         connector->dev->mode_config.scaling_mode_property,
3123                         DRM_MODE_SCALE_ASPECT);
3124                 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
3125         }
3126 }
3127
3128 static void
3129 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
3130                                     struct intel_dp *intel_dp,
3131                                     struct edp_power_seq *out)
3132 {
3133         struct drm_i915_private *dev_priv = dev->dev_private;
3134         struct edp_power_seq cur, vbt, spec, final;
3135         u32 pp_on, pp_off, pp_div, pp;
3136         int pp_control_reg, pp_on_reg, pp_off_reg, pp_div_reg;
3137
3138         if (HAS_PCH_SPLIT(dev)) {
3139                 pp_control_reg = PCH_PP_CONTROL;
3140                 pp_on_reg = PCH_PP_ON_DELAYS;
3141                 pp_off_reg = PCH_PP_OFF_DELAYS;
3142                 pp_div_reg = PCH_PP_DIVISOR;
3143         } else {
3144                 pp_control_reg = PIPEA_PP_CONTROL;
3145                 pp_on_reg = PIPEA_PP_ON_DELAYS;
3146                 pp_off_reg = PIPEA_PP_OFF_DELAYS;
3147                 pp_div_reg = PIPEA_PP_DIVISOR;
3148         }
3149
3150         /* Workaround: Need to write PP_CONTROL with the unlock key as
3151          * the very first thing. */
3152         pp = ironlake_get_pp_control(intel_dp);
3153         I915_WRITE(pp_control_reg, pp);
3154
3155         pp_on = I915_READ(pp_on_reg);
3156         pp_off = I915_READ(pp_off_reg);
3157         pp_div = I915_READ(pp_div_reg);
3158
3159         /* Pull timing values out of registers */
3160         cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
3161                 PANEL_POWER_UP_DELAY_SHIFT;
3162
3163         cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
3164                 PANEL_LIGHT_ON_DELAY_SHIFT;
3165
3166         cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
3167                 PANEL_LIGHT_OFF_DELAY_SHIFT;
3168
3169         cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
3170                 PANEL_POWER_DOWN_DELAY_SHIFT;
3171
3172         cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
3173                        PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
3174
3175         DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3176                       cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
3177
3178         vbt = dev_priv->vbt.edp_pps;
3179
3180         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
3181          * our hw here, which are all in 100usec. */
3182         spec.t1_t3 = 210 * 10;
3183         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
3184         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
3185         spec.t10 = 500 * 10;
3186         /* This one is special and actually in units of 100ms, but zero
3187          * based in the hw (so we need to add 100 ms). But the sw vbt
3188          * table multiplies it with 1000 to make it in units of 100usec,
3189          * too. */
3190         spec.t11_t12 = (510 + 100) * 10;
3191
3192         DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3193                       vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
3194
3195         /* Use the max of the register settings and vbt. If both are
3196          * unset, fall back to the spec limits. */
3197 #define assign_final(field)     final.field = (max(cur.field, vbt.field) == 0 ? \
3198                                        spec.field : \
3199                                        max(cur.field, vbt.field))
3200         assign_final(t1_t3);
3201         assign_final(t8);
3202         assign_final(t9);
3203         assign_final(t10);
3204         assign_final(t11_t12);
3205 #undef assign_final
3206
3207 #define get_delay(field)        (DIV_ROUND_UP(final.field, 10))
3208         intel_dp->panel_power_up_delay = get_delay(t1_t3);
3209         intel_dp->backlight_on_delay = get_delay(t8);
3210         intel_dp->backlight_off_delay = get_delay(t9);
3211         intel_dp->panel_power_down_delay = get_delay(t10);
3212         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
3213 #undef get_delay
3214
3215         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
3216                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
3217                       intel_dp->panel_power_cycle_delay);
3218
3219         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
3220                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
3221
3222         if (out)
3223                 *out = final;
3224 }
3225
3226 static void
3227 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
3228                                               struct intel_dp *intel_dp,
3229                                               struct edp_power_seq *seq)
3230 {
3231         struct drm_i915_private *dev_priv = dev->dev_private;
3232         u32 pp_on, pp_off, pp_div, port_sel = 0;
3233         int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
3234         int pp_on_reg, pp_off_reg, pp_div_reg;
3235
3236         if (HAS_PCH_SPLIT(dev)) {
3237                 pp_on_reg = PCH_PP_ON_DELAYS;
3238                 pp_off_reg = PCH_PP_OFF_DELAYS;
3239                 pp_div_reg = PCH_PP_DIVISOR;
3240         } else {
3241                 pp_on_reg = PIPEA_PP_ON_DELAYS;
3242                 pp_off_reg = PIPEA_PP_OFF_DELAYS;
3243                 pp_div_reg = PIPEA_PP_DIVISOR;
3244         }
3245
3246         /* And finally store the new values in the power sequencer. */
3247         pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
3248                 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
3249         pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
3250                  (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
3251         /* Compute the divisor for the pp clock, simply match the Bspec
3252          * formula. */
3253         pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
3254         pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
3255                         << PANEL_POWER_CYCLE_DELAY_SHIFT);
3256
3257         /* Haswell doesn't have any port selection bits for the panel
3258          * power sequencer any more. */
3259         if (IS_VALLEYVIEW(dev)) {
3260                 port_sel = I915_READ(pp_on_reg) & 0xc0000000;
3261         } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
3262                 if (dp_to_dig_port(intel_dp)->port == PORT_A)
3263                         port_sel = PANEL_POWER_PORT_DP_A;
3264                 else
3265                         port_sel = PANEL_POWER_PORT_DP_D;
3266         }
3267
3268         pp_on |= port_sel;
3269
3270         I915_WRITE(pp_on_reg, pp_on);
3271         I915_WRITE(pp_off_reg, pp_off);
3272         I915_WRITE(pp_div_reg, pp_div);
3273
3274         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
3275                       I915_READ(pp_on_reg),
3276                       I915_READ(pp_off_reg),
3277                       I915_READ(pp_div_reg));
3278 }
3279
3280 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
3281                                      struct intel_connector *intel_connector)
3282 {
3283         struct drm_connector *connector = &intel_connector->base;
3284         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3285         struct drm_device *dev = intel_dig_port->base.base.dev;
3286         struct drm_i915_private *dev_priv = dev->dev_private;
3287         struct drm_display_mode *fixed_mode = NULL;
3288         struct edp_power_seq power_seq = { 0 };
3289         bool has_dpcd;
3290         struct drm_display_mode *scan;
3291         struct edid *edid;
3292
3293         if (!is_edp(intel_dp))
3294                 return true;
3295
3296         intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
3297
3298         /* Cache DPCD and EDID for edp. */
3299         ironlake_edp_panel_vdd_on(intel_dp);
3300         has_dpcd = intel_dp_get_dpcd(intel_dp);
3301         ironlake_edp_panel_vdd_off(intel_dp, false);
3302
3303         if (has_dpcd) {
3304                 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3305                         dev_priv->no_aux_handshake =
3306                                 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3307                                 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3308         } else {
3309                 /* if this fails, presume the device is a ghost */
3310                 DRM_INFO("failed to retrieve link info, disabling eDP\n");
3311                 return false;
3312         }
3313
3314         /* We now know it's not a ghost, init power sequence regs. */
3315         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
3316                                                       &power_seq);
3317
3318         ironlake_edp_panel_vdd_on(intel_dp);
3319         edid = drm_get_edid(connector, &intel_dp->adapter);
3320         if (edid) {
3321                 if (drm_add_edid_modes(connector, edid)) {
3322                         drm_mode_connector_update_edid_property(connector,
3323                                                                 edid);
3324                         drm_edid_to_eld(connector, edid);
3325                 } else {
3326                         kfree(edid);
3327                         edid = ERR_PTR(-EINVAL);
3328                 }
3329         } else {
3330                 edid = ERR_PTR(-ENOENT);
3331         }
3332         intel_connector->edid = edid;
3333
3334         /* prefer fixed mode from EDID if available */
3335         list_for_each_entry(scan, &connector->probed_modes, head) {
3336                 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
3337                         fixed_mode = drm_mode_duplicate(dev, scan);
3338                         break;
3339                 }
3340         }
3341
3342         /* fallback to VBT if available for eDP */
3343         if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
3344                 fixed_mode = drm_mode_duplicate(dev,
3345                                         dev_priv->vbt.lfp_lvds_vbt_mode);
3346                 if (fixed_mode)
3347                         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
3348         }
3349
3350         ironlake_edp_panel_vdd_off(intel_dp, false);
3351
3352         intel_panel_init(&intel_connector->panel, fixed_mode);
3353         intel_panel_setup_backlight(connector);
3354
3355         return true;
3356 }
3357
3358 bool
3359 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
3360                         struct intel_connector *intel_connector)
3361 {
3362         struct drm_connector *connector = &intel_connector->base;
3363         struct intel_dp *intel_dp = &intel_dig_port->dp;
3364         struct intel_encoder *intel_encoder = &intel_dig_port->base;
3365         struct drm_device *dev = intel_encoder->base.dev;
3366         struct drm_i915_private *dev_priv = dev->dev_private;
3367         enum port port = intel_dig_port->port;
3368         const char *name = NULL;
3369         int type, error;
3370
3371         /* Preserve the current hw state. */
3372         intel_dp->DP = I915_READ(intel_dp->output_reg);
3373         intel_dp->attached_connector = intel_connector;
3374
3375         type = DRM_MODE_CONNECTOR_DisplayPort;
3376         /*
3377          * FIXME : We need to initialize built-in panels before external panels.
3378          * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
3379          */
3380         switch (port) {
3381         case PORT_A:
3382                 type = DRM_MODE_CONNECTOR_eDP;
3383                 break;
3384         case PORT_C:
3385                 if (IS_VALLEYVIEW(dev))
3386                         type = DRM_MODE_CONNECTOR_eDP;
3387                 break;
3388         case PORT_D:
3389                 if (HAS_PCH_SPLIT(dev) && intel_dpd_is_edp(dev))
3390                         type = DRM_MODE_CONNECTOR_eDP;
3391                 break;
3392         default:        /* silence GCC warning */
3393                 break;
3394         }
3395
3396         /*
3397          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
3398          * for DP the encoder type can be set by the caller to
3399          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
3400          */
3401         if (type == DRM_MODE_CONNECTOR_eDP)
3402                 intel_encoder->type = INTEL_OUTPUT_EDP;
3403
3404         DRM_DEBUG_KMS("Adding %s connector on port %c\n",
3405                         type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
3406                         port_name(port));
3407
3408         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
3409         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
3410
3411         connector->interlace_allowed = true;
3412         connector->doublescan_allowed = 0;
3413
3414         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
3415                           ironlake_panel_vdd_work);
3416
3417         intel_connector_attach_encoder(intel_connector, intel_encoder);
3418         drm_sysfs_connector_add(connector);
3419
3420         if (HAS_DDI(dev))
3421                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3422         else
3423                 intel_connector->get_hw_state = intel_connector_get_hw_state;
3424
3425         intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
3426         if (HAS_DDI(dev)) {
3427                 switch (intel_dig_port->port) {
3428                 case PORT_A:
3429                         intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
3430                         break;
3431                 case PORT_B:
3432                         intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
3433                         break;
3434                 case PORT_C:
3435                         intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
3436                         break;
3437                 case PORT_D:
3438                         intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
3439                         break;
3440                 default:
3441                         BUG();
3442                 }
3443         }
3444
3445         /* Set up the DDC bus. */
3446         switch (port) {
3447         case PORT_A:
3448                 intel_encoder->hpd_pin = HPD_PORT_A;
3449                 name = "DPDDC-A";
3450                 break;
3451         case PORT_B:
3452                 intel_encoder->hpd_pin = HPD_PORT_B;
3453                 name = "DPDDC-B";
3454                 break;
3455         case PORT_C:
3456                 intel_encoder->hpd_pin = HPD_PORT_C;
3457                 name = "DPDDC-C";
3458                 break;
3459         case PORT_D:
3460                 intel_encoder->hpd_pin = HPD_PORT_D;
3461                 name = "DPDDC-D";
3462                 break;
3463         default:
3464                 BUG();
3465         }
3466
3467         error = intel_dp_i2c_init(intel_dp, intel_connector, name);
3468         WARN(error, "intel_dp_i2c_init failed with error %d for port %c\n",
3469              error, port_name(port));
3470
3471         intel_dp->psr_setup_done = false;
3472
3473         if (!intel_edp_init_connector(intel_dp, intel_connector)) {
3474                 i2c_del_adapter(&intel_dp->adapter);
3475                 if (is_edp(intel_dp)) {
3476                         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3477                         mutex_lock(&dev->mode_config.mutex);
3478                         ironlake_panel_vdd_off_sync(intel_dp);
3479                         mutex_unlock(&dev->mode_config.mutex);
3480                 }
3481                 drm_sysfs_connector_remove(connector);
3482                 drm_connector_cleanup(connector);
3483                 return false;
3484         }
3485
3486         intel_dp_add_properties(intel_dp, connector);
3487
3488         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3489          * 0xd.  Failure to do so will result in spurious interrupts being
3490          * generated on the port when a cable is not attached.
3491          */
3492         if (IS_G4X(dev) && !IS_GM45(dev)) {
3493                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3494                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3495         }
3496
3497         return true;
3498 }
3499
3500 void
3501 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
3502 {
3503         struct intel_digital_port *intel_dig_port;
3504         struct intel_encoder *intel_encoder;
3505         struct drm_encoder *encoder;
3506         struct intel_connector *intel_connector;
3507
3508         intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
3509         if (!intel_dig_port)
3510                 return;
3511
3512         intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
3513         if (!intel_connector) {
3514                 kfree(intel_dig_port);
3515                 return;
3516         }
3517
3518         intel_encoder = &intel_dig_port->base;
3519         encoder = &intel_encoder->base;
3520
3521         drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
3522                          DRM_MODE_ENCODER_TMDS);
3523
3524         intel_encoder->compute_config = intel_dp_compute_config;
3525         intel_encoder->mode_set = intel_dp_mode_set;
3526         intel_encoder->disable = intel_disable_dp;
3527         intel_encoder->post_disable = intel_post_disable_dp;
3528         intel_encoder->get_hw_state = intel_dp_get_hw_state;
3529         intel_encoder->get_config = intel_dp_get_config;
3530         if (IS_VALLEYVIEW(dev)) {
3531                 intel_encoder->pre_pll_enable = intel_dp_pre_pll_enable;
3532                 intel_encoder->pre_enable = vlv_pre_enable_dp;
3533                 intel_encoder->enable = vlv_enable_dp;
3534         } else {
3535                 intel_encoder->pre_enable = intel_pre_enable_dp;
3536                 intel_encoder->enable = intel_enable_dp;
3537         }
3538
3539         intel_dig_port->port = port;
3540         intel_dig_port->dp.output_reg = output_reg;
3541
3542         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3543         intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3544         intel_encoder->cloneable = false;
3545         intel_encoder->hot_plug = intel_dp_hot_plug;
3546
3547         if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
3548                 drm_encoder_cleanup(encoder);
3549                 kfree(intel_dig_port);
3550                 kfree(intel_connector);
3551         }
3552 }