Pileus Git - ~andy/linux/blob - drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include <drm/drmP.h>
  32 #include <drm/drm_crtc.h>
  33 #include <drm/drm_crtc_helper.h>
  34 #include <drm/drm_edid.h>
  35 #include "intel_drv.h"
  36 #include <drm/i915_drm.h>
  37 #include "i915_drv.h"
  38
  39 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  40
  41 struct dp_link_dpll {
  42         int link_bw;
  43         struct dpll dpll;
  44 };
  45
  46 static const struct dp_link_dpll gen4_dpll[] = {
  47         { DP_LINK_BW_1_62,
  48                 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
  49         { DP_LINK_BW_2_7,
  50                 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
  51 };
  52
  53 static const struct dp_link_dpll pch_dpll[] = {
  54         { DP_LINK_BW_1_62,
  55                 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
  56         { DP_LINK_BW_2_7,
  57                 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
  58 };
  59
  60 static const struct dp_link_dpll vlv_dpll[] = {
  61         { DP_LINK_BW_1_62,
  62                 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
  63         { DP_LINK_BW_2_7,
  64                 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
  65 };
  66
  67 /**
  68  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  69  * @intel_dp: DP struct
  70  *
  71  * If a CPU or PCH DP output is attached to an eDP panel, this function
  72  * will return true, and false otherwise.
  73  */
  74 static bool is_edp(struct intel_dp *intel_dp)
  75 {
  76         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  77
  78         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
  79 }
  80
  81 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
  82 {
  83         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  84
  85         return intel_dig_port->base.base.dev;
  86 }
  87
  88 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
  89 {
  90         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
  91 }
  92
  93 static void intel_dp_link_down(struct intel_dp *intel_dp);
  94
  95 static int
  96 intel_dp_max_link_bw(struct intel_dp *intel_dp)
  97 {
  98         int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
  99
 100         switch (max_link_bw) {
 101         case DP_LINK_BW_1_62:
 102         case DP_LINK_BW_2_7:
 103                 break;
 104         case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
 105                 max_link_bw = DP_LINK_BW_2_7;
 106                 break;
 107         default:
 108                 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
 109                      max_link_bw);
 110                 max_link_bw = DP_LINK_BW_1_62;
 111                 break;
 112         }
 113         return max_link_bw;
 114 }
 115
 116 /*
 117  * The units on the numbers in the next two are... bizarre.  Examples will
 118  * make it clearer; this one parallels an example in the eDP spec.
 119  *
 120  * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
 121  *
 122  *     270000 * 1 * 8 / 10 == 216000
 123  *
 124  * The actual data capacity of that configuration is 2.16Gbit/s, so the
 125  * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 126  * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 127  * 119000.  At 18bpp that's 2142000 kilobits per second.
 128  *
 129  * Thus the strange-looking division by 10 in intel_dp_link_required, to
 130  * get the result in decakilobits instead of kilobits.
 131  */
 132
 133 static int
 134 intel_dp_link_required(int pixel_clock, int bpp)
 135 {
 136         return (pixel_clock * bpp + 9) / 10;
 137 }
 138
 139 static int
 140 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 141 {
 142         return (max_link_clock * max_lanes * 8) / 10;
 143 }
 144
 145 static enum drm_mode_status
 146 intel_dp_mode_valid(struct drm_connector *connector,
 147                     struct drm_display_mode *mode)
 148 {
 149         struct intel_dp *intel_dp = intel_attached_dp(connector);
 150         struct intel_connector *intel_connector = to_intel_connector(connector);
 151         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 152         int target_clock = mode->clock;
 153         int max_rate, mode_rate, max_lanes, max_link_clock;
 154
 155         if (is_edp(intel_dp) && fixed_mode) {
 156                 if (mode->hdisplay > fixed_mode->hdisplay)
 157                         return MODE_PANEL;
 158
 159                 if (mode->vdisplay > fixed_mode->vdisplay)
 160                         return MODE_PANEL;
 161
 162                 target_clock = fixed_mode->clock;
 163         }
 164
 165         max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
 166         max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
 167
 168         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 169         mode_rate = intel_dp_link_required(target_clock, 18);
 170
 171         if (mode_rate > max_rate)
 172                 return MODE_CLOCK_HIGH;
 173
 174         if (mode->clock < 10000)
 175                 return MODE_CLOCK_LOW;
 176
 177         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 178                 return MODE_H_ILLEGAL;
 179
 180         return MODE_OK;
 181 }
 182
 183 static uint32_t
 184 pack_aux(uint8_t *src, int src_bytes)
 185 {
 186         int     i;
 187         uint32_t v = 0;
 188
 189         if (src_bytes > 4)
 190                 src_bytes = 4;
 191         for (i = 0; i < src_bytes; i++)
 192                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 193         return v;
 194 }
 195
 196 static void
 197 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 198 {
 199         int i;
 200         if (dst_bytes > 4)
 201                 dst_bytes = 4;
 202         for (i = 0; i < dst_bytes; i++)
 203                 dst[i] = src >> ((3-i) * 8);
 204 }
 205
 206 /* hrawclock is 1/4 the FSB frequency */
 207 static int
 208 intel_hrawclk(struct drm_device *dev)
 209 {
 210         struct drm_i915_private *dev_priv = dev->dev_private;
 211         uint32_t clkcfg;
 212
 213         /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
 214         if (IS_VALLEYVIEW(dev))
 215                 return 200;
 216
 217         clkcfg = I915_READ(CLKCFG);
 218         switch (clkcfg & CLKCFG_FSB_MASK) {
 219         case CLKCFG_FSB_400:
 220                 return 100;
 221         case CLKCFG_FSB_533:
 222                 return 133;
 223         case CLKCFG_FSB_667:
 224                 return 166;
 225         case CLKCFG_FSB_800:
 226                 return 200;
 227         case CLKCFG_FSB_1067:
 228                 return 266;
 229         case CLKCFG_FSB_1333:
 230                 return 333;
 231         /* these two are just a guess; one of them might be right */
 232         case CLKCFG_FSB_1600:
 233         case CLKCFG_FSB_1600_ALT:
 234                 return 400;
 235         default:
 236                 return 133;
 237         }
 238 }
 239
 240 static void
 241 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
 242                                     struct intel_dp *intel_dp,
 243                                     struct edp_power_seq *out);
 244 static void
 245 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
 246                                               struct intel_dp *intel_dp,
 247                                               struct edp_power_seq *out);
 248
 249 static enum pipe
 250 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
 251 {
 252         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 253         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
 254         struct drm_device *dev = intel_dig_port->base.base.dev;
 255         struct drm_i915_private *dev_priv = dev->dev_private;
 256         enum port port = intel_dig_port->port;
 257         enum pipe pipe;
 258
 259         /* modeset should have pipe */
 260         if (crtc)
 261                 return to_intel_crtc(crtc)->pipe;
 262
 263         /* init time, try to find a pipe with this port selected */
 264         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
 265                 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
 266                         PANEL_PORT_SELECT_MASK;
 267                 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
 268                         return pipe;
 269                 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
 270                         return pipe;
 271         }
 272
 273         /* shrug */
 274         return PIPE_A;
 275 }
 276
 277 static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
 278 {
 279         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 280
 281         if (HAS_PCH_SPLIT(dev))
 282                 return PCH_PP_CONTROL;
 283         else
 284                 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
 285 }
 286
 287 static u32 _pp_stat_reg(struct intel_dp *intel_dp)
 288 {
 289         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 290
 291         if (HAS_PCH_SPLIT(dev))
 292                 return PCH_PP_STATUS;
 293         else
 294                 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
 295 }
 296
 297 static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
 298 {
 299         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 300         struct drm_i915_private *dev_priv = dev->dev_private;
 301
 302         return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
 303 }
 304
 305 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
 306 {
 307         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 308         struct drm_i915_private *dev_priv = dev->dev_private;
 309
 310         return (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
 311 }
 312
 313 static void
 314 intel_dp_check_edp(struct intel_dp *intel_dp)
 315 {
 316         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 317         struct drm_i915_private *dev_priv = dev->dev_private;
 318
 319         if (!is_edp(intel_dp))
 320                 return;
 321
 322         if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
 323                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 324                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 325                               I915_READ(_pp_stat_reg(intel_dp)),
 326                               I915_READ(_pp_ctrl_reg(intel_dp)));
 327         }
 328 }
 329
 330 static uint32_t
 331 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
 332 {
 333         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 334         struct drm_device *dev = intel_dig_port->base.base.dev;
 335         struct drm_i915_private *dev_priv = dev->dev_private;
 336         uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 337         uint32_t status;
 338         bool done;
 339
 340 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 341         if (has_aux_irq)
 342                 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
 343                                           msecs_to_jiffies_timeout(10));
 344         else
 345                 done = wait_for_atomic(C, 10) == 0;
 346         if (!done)
 347                 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
 348                           has_aux_irq);
 349 #undef C
 350
 351         return status;
 352 }
 353
 354 static uint32_t get_aux_clock_divider(struct intel_dp *intel_dp,
 355                                       int index)
 356 {
 357         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 358         struct drm_device *dev = intel_dig_port->base.base.dev;
 359         struct drm_i915_private *dev_priv = dev->dev_private;
 360
 361         /* The clock divider is based off the hrawclk,
 362          * and would like to run at 2MHz. So, take the
 363          * hrawclk value and divide by 2 and use that
 364          *
 365          * Note that PCH attached eDP panels should use a 125MHz input
 366          * clock divider.
 367          */
 368         if (IS_VALLEYVIEW(dev)) {
 369                 return index ? 0 : 100;
 370         } else if (intel_dig_port->port == PORT_A) {
 371                 if (index)
 372                         return 0;
 373                 if (HAS_DDI(dev))
 374                         return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
 375                 else if (IS_GEN6(dev) || IS_GEN7(dev))
 376                         return 200; /* SNB & IVB eDP input clock at 400Mhz */
 377                 else
 378                         return 225; /* eDP input clock at 450Mhz */
 379         } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 380                 /* Workaround for non-ULT HSW */
 381                 switch (index) {
 382                 case 0: return 63;
 383                 case 1: return 72;
 384                 default: return 0;
 385                 }
 386         } else if (HAS_PCH_SPLIT(dev)) {
 387                 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
 388         } else {
 389                 return index ? 0 :intel_hrawclk(dev) / 2;
 390         }
 391 }
 392
 393 static int
 394 intel_dp_aux_ch(struct intel_dp *intel_dp,
 395                 uint8_t *send, int send_bytes,
 396                 uint8_t *recv, int recv_size)
 397 {
 398         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 399         struct drm_device *dev = intel_dig_port->base.base.dev;
 400         struct drm_i915_private *dev_priv = dev->dev_private;
 401         uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 402         uint32_t ch_data = ch_ctl + 4;
 403         uint32_t aux_clock_divider;
 404         int i, ret, recv_bytes;
 405         uint32_t status;
 406         int try, precharge, clock = 0;
 407         bool has_aux_irq = HAS_AUX_IRQ(dev);
 408         uint32_t timeout;
 409
 410         /* dp aux is extremely sensitive to irq latency, hence request the
 411          * lowest possible wakeup latency and so prevent the cpu from going into
 412          * deep sleep states.
 413          */
 414         pm_qos_update_request(&dev_priv->pm_qos, 0);
 415
 416         intel_dp_check_edp(intel_dp);
 417
 418         if (IS_GEN6(dev))
 419                 precharge = 3;
 420         else
 421                 precharge = 5;
 422
 423         if (IS_BROADWELL(dev) && ch_ctl == DPA_AUX_CH_CTL)
 424                 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
 425         else
 426                 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
 427
 428         intel_aux_display_runtime_get(dev_priv);
 429
 430         /* Try to wait for any previous AUX channel activity */
 431         for (try = 0; try < 3; try++) {
 432                 status = I915_READ_NOTRACE(ch_ctl);
 433                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 434                         break;
 435                 msleep(1);
 436         }
 437
 438         if (try == 3) {
 439                 WARN(1, "dp_aux_ch not started status 0x%08x\n",
 440                      I915_READ(ch_ctl));
 441                 ret = -EBUSY;
 442                 goto out;
 443         }
 444
 445         /* Only 5 data registers! */
 446         if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
 447                 ret = -E2BIG;
 448                 goto out;
 449         }
 450
 451         while ((aux_clock_divider = get_aux_clock_divider(intel_dp, clock++))) {
 452                 /* Must try at least 3 times according to DP spec */
 453                 for (try = 0; try < 5; try++) {
 454                         /* Load the send data into the aux channel data registers */
 455                         for (i = 0; i < send_bytes; i += 4)
 456                                 I915_WRITE(ch_data + i,
 457                                            pack_aux(send + i, send_bytes - i));
 458
 459                         /* Send the command and wait for it to complete */
 460                         I915_WRITE(ch_ctl,
 461                                    DP_AUX_CH_CTL_SEND_BUSY |
 462                                    (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
 463                                    timeout |
 464                                    (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 465                                    (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 466                                    (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
 467                                    DP_AUX_CH_CTL_DONE |
 468                                    DP_AUX_CH_CTL_TIME_OUT_ERROR |
 469                                    DP_AUX_CH_CTL_RECEIVE_ERROR);
 470
 471                         status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
 472
 473                         /* Clear done status and any errors */
 474                         I915_WRITE(ch_ctl,
 475                                    status |
 476                                    DP_AUX_CH_CTL_DONE |
 477                                    DP_AUX_CH_CTL_TIME_OUT_ERROR |
 478                                    DP_AUX_CH_CTL_RECEIVE_ERROR);
 479
 480                         if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
 481                                       DP_AUX_CH_CTL_RECEIVE_ERROR))
 482                                 continue;
 483                         if (status & DP_AUX_CH_CTL_DONE)
 484                                 break;
 485                 }
 486                 if (status & DP_AUX_CH_CTL_DONE)
 487                         break;
 488         }
 489
 490         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 491                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 492                 ret = -EBUSY;
 493                 goto out;
 494         }
 495
 496         /* Check for timeout or receive error.
 497          * Timeouts occur when the sink is not connected
 498          */
 499         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 500                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 501                 ret = -EIO;
 502                 goto out;
 503         }
 504
 505         /* Timeouts occur when the device isn't connected, so they're
 506          * "normal" -- don't fill the kernel log with these */
 507         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 508                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 509                 ret = -ETIMEDOUT;
 510                 goto out;
 511         }
 512
 513         /* Unload any bytes sent back from the other side */
 514         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 515                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 516         if (recv_bytes > recv_size)
 517                 recv_bytes = recv_size;
 518
 519         for (i = 0; i < recv_bytes; i += 4)
 520                 unpack_aux(I915_READ(ch_data + i),
 521                            recv + i, recv_bytes - i);
 522
 523         ret = recv_bytes;
 524 out:
 525         pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
 526         intel_aux_display_runtime_put(dev_priv);
 527
 528         return ret;
 529 }
 530
 531 /* Write data to the aux channel in native mode */
 532 static int
 533 intel_dp_aux_native_write(struct intel_dp *intel_dp,
 534                           uint16_t address, uint8_t *send, int send_bytes)
 535 {
 536         int ret;
 537         uint8_t msg[20];
 538         int msg_bytes;
 539         uint8_t ack;
 540
 541         if (WARN_ON(send_bytes > 16))
 542                 return -E2BIG;
 543
 544         intel_dp_check_edp(intel_dp);
 545         msg[0] = DP_AUX_NATIVE_WRITE << 4;
 546         msg[1] = address >> 8;
 547         msg[2] = address & 0xff;
 548         msg[3] = send_bytes - 1;
 549         memcpy(&msg[4], send, send_bytes);
 550         msg_bytes = send_bytes + 4;
 551         for (;;) {
 552                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
 553                 if (ret < 0)
 554                         return ret;
 555                 ack >>= 4;
 556                 if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK)
 557                         break;
 558                 else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER)
 559                         udelay(100);
 560                 else
 561                         return -EIO;
 562         }
 563         return send_bytes;
 564 }
 565
 566 /* Write a single byte to the aux channel in native mode */
 567 static int
 568 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
 569                             uint16_t address, uint8_t byte)
 570 {
 571         return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
 572 }
 573
 574 /* read bytes from a native aux channel */
 575 static int
 576 intel_dp_aux_native_read(struct intel_dp *intel_dp,
 577                          uint16_t address, uint8_t *recv, int recv_bytes)
 578 {
 579         uint8_t msg[4];
 580         int msg_bytes;
 581         uint8_t reply[20];
 582         int reply_bytes;
 583         uint8_t ack;
 584         int ret;
 585
 586         if (WARN_ON(recv_bytes > 19))
 587                 return -E2BIG;
 588
 589         intel_dp_check_edp(intel_dp);
 590         msg[0] = DP_AUX_NATIVE_READ << 4;
 591         msg[1] = address >> 8;
 592         msg[2] = address & 0xff;
 593         msg[3] = recv_bytes - 1;
 594
 595         msg_bytes = 4;
 596         reply_bytes = recv_bytes + 1;
 597
 598         for (;;) {
 599                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
 600                                       reply, reply_bytes);
 601                 if (ret == 0)
 602                         return -EPROTO;
 603                 if (ret < 0)
 604                         return ret;
 605                 ack = reply[0] >> 4;
 606                 if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK) {
 607                         memcpy(recv, reply + 1, ret - 1);
 608                         return ret - 1;
 609                 }
 610                 else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER)
 611                         udelay(100);
 612                 else
 613                         return -EIO;
 614         }
 615 }
 616
 617 static int
 618 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
 619                     uint8_t write_byte, uint8_t *read_byte)
 620 {
 621         struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
 622         struct intel_dp *intel_dp = container_of(adapter,
 623                                                 struct intel_dp,
 624                                                 adapter);
 625         uint16_t address = algo_data->address;
 626         uint8_t msg[5];
 627         uint8_t reply[2];
 628         unsigned retry;
 629         int msg_bytes;
 630         int reply_bytes;
 631         int ret;
 632
 633         ironlake_edp_panel_vdd_on(intel_dp);
 634         intel_dp_check_edp(intel_dp);
 635         /* Set up the command byte */
 636         if (mode & MODE_I2C_READ)
 637                 msg[0] = DP_AUX_I2C_READ << 4;
 638         else
 639                 msg[0] = DP_AUX_I2C_WRITE << 4;
 640
 641         if (!(mode & MODE_I2C_STOP))
 642                 msg[0] |= DP_AUX_I2C_MOT << 4;
 643
 644         msg[1] = address >> 8;
 645         msg[2] = address;
 646
 647         switch (mode) {
 648         case MODE_I2C_WRITE:
 649                 msg[3] = 0;
 650                 msg[4] = write_byte;
 651                 msg_bytes = 5;
 652                 reply_bytes = 1;
 653                 break;
 654         case MODE_I2C_READ:
 655                 msg[3] = 0;
 656                 msg_bytes = 4;
 657                 reply_bytes = 2;
 658                 break;
 659         default:
 660                 msg_bytes = 3;
 661                 reply_bytes = 1;
 662                 break;
 663         }
 664
 665         /*
 666          * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device is
 667          * required to retry at least seven times upon receiving AUX_DEFER
 668          * before giving up the AUX transaction.
 669          */
 670         for (retry = 0; retry < 7; retry++) {
 671                 ret = intel_dp_aux_ch(intel_dp,
 672                                       msg, msg_bytes,
 673                                       reply, reply_bytes);
 674                 if (ret < 0) {
 675                         DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
 676                         goto out;
 677                 }
 678
 679                 switch ((reply[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK) {
 680                 case DP_AUX_NATIVE_REPLY_ACK:
 681                         /* I2C-over-AUX Reply field is only valid
 682                          * when paired with AUX ACK.
 683                          */
 684                         break;
 685                 case DP_AUX_NATIVE_REPLY_NACK:
 686                         DRM_DEBUG_KMS("aux_ch native nack\n");
 687                         ret = -EREMOTEIO;
 688                         goto out;
 689                 case DP_AUX_NATIVE_REPLY_DEFER:
 690                         /*
 691                          * For now, just give more slack to branch devices. We
 692                          * could check the DPCD for I2C bit rate capabilities,
 693                          * and if available, adjust the interval. We could also
 694                          * be more careful with DP-to-Legacy adapters where a
 695                          * long legacy cable may force very low I2C bit rates.
 696                          */
 697                         if (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
 698                             DP_DWN_STRM_PORT_PRESENT)
 699                                 usleep_range(500, 600);
 700                         else
 701                                 usleep_range(300, 400);
 702                         continue;
 703                 default:
 704                         DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
 705                                   reply[0]);
 706                         ret = -EREMOTEIO;
 707                         goto out;
 708                 }
 709
 710                 switch ((reply[0] >> 4) & DP_AUX_I2C_REPLY_MASK) {
 711                 case DP_AUX_I2C_REPLY_ACK:
 712                         if (mode == MODE_I2C_READ) {
 713                                 *read_byte = reply[1];
 714                         }
 715                         ret = reply_bytes - 1;
 716                         goto out;
 717                 case DP_AUX_I2C_REPLY_NACK:
 718                         DRM_DEBUG_KMS("aux_i2c nack\n");
 719                         ret = -EREMOTEIO;
 720                         goto out;
 721                 case DP_AUX_I2C_REPLY_DEFER:
 722                         DRM_DEBUG_KMS("aux_i2c defer\n");
 723                         udelay(100);
 724                         break;
 725                 default:
 726                         DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
 727                         ret = -EREMOTEIO;
 728                         goto out;
 729                 }
 730         }
 731
 732         DRM_ERROR("too many retries, giving up\n");
 733         ret = -EREMOTEIO;
 734
 735 out:
 736         ironlake_edp_panel_vdd_off(intel_dp, false);
 737         return ret;
 738 }
 739
 740 static int
 741 intel_dp_i2c_init(struct intel_dp *intel_dp,
 742                   struct intel_connector *intel_connector, const char *name)
 743 {
 744         int     ret;
 745
 746         DRM_DEBUG_KMS("i2c_init %s\n", name);
 747         intel_dp->algo.running = false;
 748         intel_dp->algo.address = 0;
 749         intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
 750
 751         memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
 752         intel_dp->adapter.owner = THIS_MODULE;
 753         intel_dp->adapter.class = I2C_CLASS_DDC;
 754         strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
 755         intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
 756         intel_dp->adapter.algo_data = &intel_dp->algo;
 757         intel_dp->adapter.dev.parent = intel_connector->base.kdev;
 758
 759         ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
 760         return ret;
 761 }
 762
 763 static void
 764 intel_dp_set_clock(struct intel_encoder *encoder,
 765                    struct intel_crtc_config *pipe_config, int link_bw)
 766 {
 767         struct drm_device *dev = encoder->base.dev;
 768         const struct dp_link_dpll *divisor = NULL;
 769         int i, count = 0;
 770
 771         if (IS_G4X(dev)) {
 772                 divisor = gen4_dpll;
 773                 count = ARRAY_SIZE(gen4_dpll);
 774         } else if (IS_HASWELL(dev)) {
 775                 /* Haswell has special-purpose DP DDI clocks. */
 776         } else if (HAS_PCH_SPLIT(dev)) {
 777                 divisor = pch_dpll;
 778                 count = ARRAY_SIZE(pch_dpll);
 779         } else if (IS_VALLEYVIEW(dev)) {
 780                 divisor = vlv_dpll;
 781                 count = ARRAY_SIZE(vlv_dpll);
 782         }
 783
 784         if (divisor && count) {
 785                 for (i = 0; i < count; i++) {
 786                         if (link_bw == divisor[i].link_bw) {
 787                                 pipe_config->dpll = divisor[i].dpll;
 788                                 pipe_config->clock_set = true;
 789                                 break;
 790                         }
 791                 }
 792         }
 793 }
 794
 795 bool
 796 intel_dp_compute_config(struct intel_encoder *encoder,
 797                         struct intel_crtc_config *pipe_config)
 798 {
 799         struct drm_device *dev = encoder->base.dev;
 800         struct drm_i915_private *dev_priv = dev->dev_private;
 801         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
 802         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 803         enum port port = dp_to_dig_port(intel_dp)->port;
 804         struct intel_crtc *intel_crtc = encoder->new_crtc;
 805         struct intel_connector *intel_connector = intel_dp->attached_connector;
 806         int lane_count, clock;
 807         int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
 808         int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
 809         int bpp, mode_rate;
 810         static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
 811         int link_avail, link_clock;
 812
 813         if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
 814                 pipe_config->has_pch_encoder = true;
 815
 816         pipe_config->has_dp_encoder = true;
 817
 818         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
 819                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
 820                                        adjusted_mode);
 821                 if (!HAS_PCH_SPLIT(dev))
 822                         intel_gmch_panel_fitting(intel_crtc, pipe_config,
 823                                                  intel_connector->panel.fitting_mode);
 824                 else
 825                         intel_pch_panel_fitting(intel_crtc, pipe_config,
 826                                                 intel_connector->panel.fitting_mode);
 827         }
 828
 829         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
 830                 return false;
 831
 832         DRM_DEBUG_KMS("DP link computation with max lane count %i "
 833                       "max bw %02x pixel clock %iKHz\n",
 834                       max_lane_count, bws[max_clock],
 835                       adjusted_mode->crtc_clock);
 836
 837         /* Walk through all bpp values. Luckily they're all nicely spaced with 2
 838          * bpc in between. */
 839         bpp = pipe_config->pipe_bpp;
 840         if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
 841             dev_priv->vbt.edp_bpp < bpp) {
 842                 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
 843                               dev_priv->vbt.edp_bpp);
 844                 bpp = dev_priv->vbt.edp_bpp;
 845         }
 846
 847         for (; bpp >= 6*3; bpp -= 2*3) {
 848                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
 849                                                    bpp);
 850
 851                 for (clock = 0; clock <= max_clock; clock++) {
 852                         for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
 853                                 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
 854                                 link_avail = intel_dp_max_data_rate(link_clock,
 855                                                                     lane_count);
 856
 857                                 if (mode_rate <= link_avail) {
 858                                         goto found;
 859                                 }
 860                         }
 861                 }
 862         }
 863
 864         return false;
 865
 866 found:
 867         if (intel_dp->color_range_auto) {
 868                 /*
 869                  * See:
 870                  * CEA-861-E - 5.1 Default Encoding Parameters
 871                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
 872                  */
 873                 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
 874                         intel_dp->color_range = DP_COLOR_RANGE_16_235;
 875                 else
 876                         intel_dp->color_range = 0;
 877         }
 878
 879         if (intel_dp->color_range)
 880                 pipe_config->limited_color_range = true;
 881
 882         intel_dp->link_bw = bws[clock];
 883         intel_dp->lane_count = lane_count;
 884         pipe_config->pipe_bpp = bpp;
 885         pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
 886
 887         DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
 888                       intel_dp->link_bw, intel_dp->lane_count,
 889                       pipe_config->port_clock, bpp);
 890         DRM_DEBUG_KMS("DP link bw required %i available %i\n",
 891                       mode_rate, link_avail);
 892
 893         intel_link_compute_m_n(bpp, lane_count,
 894                                adjusted_mode->crtc_clock,
 895                                pipe_config->port_clock,
 896                                &pipe_config->dp_m_n);
 897
 898         intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
 899
 900         return true;
 901 }
 902
 903 static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
 904 {
 905         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 906         struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
 907         struct drm_device *dev = crtc->base.dev;
 908         struct drm_i915_private *dev_priv = dev->dev_private;
 909         u32 dpa_ctl;
 910
 911         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
 912         dpa_ctl = I915_READ(DP_A);
 913         dpa_ctl &= ~DP_PLL_FREQ_MASK;
 914
 915         if (crtc->config.port_clock == 162000) {
 916                 /* For a long time we've carried around a ILK-DevA w/a for the
 917                  * 160MHz clock. If we're really unlucky, it's still required.
 918                  */
 919                 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
 920                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
 921                 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 922         } else {
 923                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
 924                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
 925         }
 926
 927         I915_WRITE(DP_A, dpa_ctl);
 928
 929         POSTING_READ(DP_A);
 930         udelay(500);
 931 }
 932
 933 static void intel_dp_mode_set(struct intel_encoder *encoder)
 934 {
 935         struct drm_device *dev = encoder->base.dev;
 936         struct drm_i915_private *dev_priv = dev->dev_private;
 937         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 938         enum port port = dp_to_dig_port(intel_dp)->port;
 939         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
 940         struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
 941
 942         /*
 943          * There are four kinds of DP registers:
 944          *
 945          *      IBX PCH
 946          *      SNB CPU
 947          *      IVB CPU
 948          *      CPT PCH
 949          *
 950          * IBX PCH and CPU are the same for almost everything,
 951          * except that the CPU DP PLL is configured in this
 952          * register
 953          *
 954          * CPT PCH is quite different, having many bits moved
 955          * to the TRANS_DP_CTL register instead. That
 956          * configuration happens (oddly) in ironlake_pch_enable
 957          */
 958
 959         /* Preserve the BIOS-computed detected bit. This is
 960          * supposed to be read-only.
 961          */
 962         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 963
 964         /* Handle DP bits in common between all three register formats */
 965         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 966         intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
 967
 968         if (intel_dp->has_audio) {
 969                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
 970                                  pipe_name(crtc->pipe));
 971                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
 972                 intel_write_eld(&encoder->base, adjusted_mode);
 973         }
 974
 975         /* Split out the IBX/CPU vs CPT settings */
 976
 977         if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
 978                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 979                         intel_dp->DP |= DP_SYNC_HS_HIGH;
 980                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 981                         intel_dp->DP |= DP_SYNC_VS_HIGH;
 982                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 983
 984                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
 985                         intel_dp->DP |= DP_ENHANCED_FRAMING;
 986
 987                 intel_dp->DP |= crtc->pipe << 29;
 988         } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
 989                 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
 990                         intel_dp->DP |= intel_dp->color_range;
 991
 992                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 993                         intel_dp->DP |= DP_SYNC_HS_HIGH;
 994                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 995                         intel_dp->DP |= DP_SYNC_VS_HIGH;
 996                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
 997
 998                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
 999                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1000
1001                 if (crtc->pipe == 1)
1002                         intel_dp->DP |= DP_PIPEB_SELECT;
1003         } else {
1004                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1005         }
1006
1007         if (port == PORT_A && !IS_VALLEYVIEW(dev))
1008                 ironlake_set_pll_cpu_edp(intel_dp);
1009 }
1010
1011 #define IDLE_ON_MASK            (PP_ON | 0        | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
1012 #define IDLE_ON_VALUE           (PP_ON | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
1013
1014 #define IDLE_OFF_MASK           (PP_ON | 0        | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
1015 #define IDLE_OFF_VALUE          (0     | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
1016
1017 #define IDLE_CYCLE_MASK         (PP_ON | 0        | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1018 #define IDLE_CYCLE_VALUE        (0     | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
1019
1020 static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
1021                                        u32 mask,
1022                                        u32 value)
1023 {
1024         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1025         struct drm_i915_private *dev_priv = dev->dev_private;
1026         u32 pp_stat_reg, pp_ctrl_reg;
1027
1028         pp_stat_reg = _pp_stat_reg(intel_dp);
1029         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1030
1031         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1032                         mask, value,
1033                         I915_READ(pp_stat_reg),
1034                         I915_READ(pp_ctrl_reg));
1035
1036         if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
1037                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1038                                 I915_READ(pp_stat_reg),
1039                                 I915_READ(pp_ctrl_reg));
1040         }
1041
1042         DRM_DEBUG_KMS("Wait complete\n");
1043 }
1044
1045 static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
1046 {
1047         DRM_DEBUG_KMS("Wait for panel power on\n");
1048         ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1049 }
1050
1051 static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
1052 {
1053         DRM_DEBUG_KMS("Wait for panel power off time\n");
1054         ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1055 }
1056
1057 static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
1058 {
1059         DRM_DEBUG_KMS("Wait for panel power cycle\n");
1060         ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1061 }
1062
1063
1064 /* Read the current pp_control value, unlocking the register if it
1065  * is locked
1066  */
1067
1068 static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1069 {
1070         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1071         struct drm_i915_private *dev_priv = dev->dev_private;
1072         u32 control;
1073
1074         control = I915_READ(_pp_ctrl_reg(intel_dp));
1075         control &= ~PANEL_UNLOCK_MASK;
1076         control |= PANEL_UNLOCK_REGS;
1077         return control;
1078 }
1079
1080 void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
1081 {
1082         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1083         struct drm_i915_private *dev_priv = dev->dev_private;
1084         u32 pp;
1085         u32 pp_stat_reg, pp_ctrl_reg;
1086
1087         if (!is_edp(intel_dp))
1088                 return;
1089
1090         WARN(intel_dp->want_panel_vdd,
1091              "eDP VDD already requested on\n");
1092
1093         intel_dp->want_panel_vdd = true;
1094
1095         if (ironlake_edp_have_panel_vdd(intel_dp))
1096                 return;
1097
1098         intel_runtime_pm_get(dev_priv);
1099
1100         DRM_DEBUG_KMS("Turning eDP VDD on\n");
1101
1102         if (!ironlake_edp_have_panel_power(intel_dp))
1103                 ironlake_wait_panel_power_cycle(intel_dp);
1104
1105         pp = ironlake_get_pp_control(intel_dp);
1106         pp |= EDP_FORCE_VDD;
1107
1108         pp_stat_reg = _pp_stat_reg(intel_dp);
1109         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1110
1111         I915_WRITE(pp_ctrl_reg, pp);
1112         POSTING_READ(pp_ctrl_reg);
1113         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1114                         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1115         /*
1116          * If the panel wasn't on, delay before accessing aux channel
1117          */
1118         if (!ironlake_edp_have_panel_power(intel_dp)) {
1119                 DRM_DEBUG_KMS("eDP was not running\n");
1120                 msleep(intel_dp->panel_power_up_delay);
1121         }
1122 }
1123
1124 static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
1125 {
1126         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1127         struct drm_i915_private *dev_priv = dev->dev_private;
1128         u32 pp;
1129         u32 pp_stat_reg, pp_ctrl_reg;
1130
1131         WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1132
1133         if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
1134                 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1135
1136                 pp = ironlake_get_pp_control(intel_dp);
1137                 pp &= ~EDP_FORCE_VDD;
1138
1139                 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1140                 pp_stat_reg = _pp_stat_reg(intel_dp);
1141
1142                 I915_WRITE(pp_ctrl_reg, pp);
1143                 POSTING_READ(pp_ctrl_reg);
1144
1145                 /* Make sure sequencer is idle before allowing subsequent activity */
1146                 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1147                 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1148
1149                 if ((pp & POWER_TARGET_ON) == 0)
1150                         msleep(intel_dp->panel_power_cycle_delay);
1151
1152                 intel_runtime_pm_put(dev_priv);
1153         }
1154 }
1155
1156 static void ironlake_panel_vdd_work(struct work_struct *__work)
1157 {
1158         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1159                                                  struct intel_dp, panel_vdd_work);
1160         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1161
1162         mutex_lock(&dev->mode_config.mutex);
1163         ironlake_panel_vdd_off_sync(intel_dp);
1164         mutex_unlock(&dev->mode_config.mutex);
1165 }
1166
1167 void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1168 {
1169         if (!is_edp(intel_dp))
1170                 return;
1171
1172         WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1173
1174         intel_dp->want_panel_vdd = false;
1175
1176         if (sync) {
1177                 ironlake_panel_vdd_off_sync(intel_dp);
1178         } else {
1179                 /*
1180                  * Queue the timer to fire a long
1181                  * time from now (relative to the power down delay)
1182                  * to keep the panel power up across a sequence of operations
1183                  */
1184                 schedule_delayed_work(&intel_dp->panel_vdd_work,
1185                                       msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1186         }
1187 }
1188
1189 void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1190 {
1191         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1192         struct drm_i915_private *dev_priv = dev->dev_private;
1193         u32 pp;
1194         u32 pp_ctrl_reg;
1195
1196         if (!is_edp(intel_dp))
1197                 return;
1198
1199         DRM_DEBUG_KMS("Turn eDP power on\n");
1200
1201         if (ironlake_edp_have_panel_power(intel_dp)) {
1202                 DRM_DEBUG_KMS("eDP power already on\n");
1203                 return;
1204         }
1205
1206         ironlake_wait_panel_power_cycle(intel_dp);
1207
1208         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1209         pp = ironlake_get_pp_control(intel_dp);
1210         if (IS_GEN5(dev)) {
1211                 /* ILK workaround: disable reset around power sequence */
1212                 pp &= ~PANEL_POWER_RESET;
1213                 I915_WRITE(pp_ctrl_reg, pp);
1214                 POSTING_READ(pp_ctrl_reg);
1215         }
1216
1217         pp |= POWER_TARGET_ON;
1218         if (!IS_GEN5(dev))
1219                 pp |= PANEL_POWER_RESET;
1220
1221         I915_WRITE(pp_ctrl_reg, pp);
1222         POSTING_READ(pp_ctrl_reg);
1223
1224         ironlake_wait_panel_on(intel_dp);
1225
1226         if (IS_GEN5(dev)) {
1227                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1228                 I915_WRITE(pp_ctrl_reg, pp);
1229                 POSTING_READ(pp_ctrl_reg);
1230         }
1231 }
1232
1233 void ironlake_edp_panel_off(struct intel_dp *intel_dp)
1234 {
1235         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1236         struct drm_i915_private *dev_priv = dev->dev_private;
1237         u32 pp;
1238         u32 pp_ctrl_reg;
1239
1240         if (!is_edp(intel_dp))
1241                 return;
1242
1243         DRM_DEBUG_KMS("Turn eDP power off\n");
1244
1245         pp = ironlake_get_pp_control(intel_dp);
1246         /* We need to switch off panel power _and_ force vdd, for otherwise some
1247          * panels get very unhappy and cease to work. */
1248         pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1249
1250         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1251
1252         I915_WRITE(pp_ctrl_reg, pp);
1253         POSTING_READ(pp_ctrl_reg);
1254
1255         ironlake_wait_panel_off(intel_dp);
1256 }
1257
1258 void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1259 {
1260         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1261         struct drm_device *dev = intel_dig_port->base.base.dev;
1262         struct drm_i915_private *dev_priv = dev->dev_private;
1263         u32 pp;
1264         u32 pp_ctrl_reg;
1265
1266         if (!is_edp(intel_dp))
1267                 return;
1268
1269         DRM_DEBUG_KMS("\n");
1270         /*
1271          * If we enable the backlight right away following a panel power
1272          * on, we may see slight flicker as the panel syncs with the eDP
1273          * link.  So delay a bit to make sure the image is solid before
1274          * allowing it to appear.
1275          */
1276         msleep(intel_dp->backlight_on_delay);
1277         pp = ironlake_get_pp_control(intel_dp);
1278         pp |= EDP_BLC_ENABLE;
1279
1280         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1281
1282         I915_WRITE(pp_ctrl_reg, pp);
1283         POSTING_READ(pp_ctrl_reg);
1284
1285         intel_panel_enable_backlight(intel_dp->attached_connector);
1286 }
1287
1288 void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1289 {
1290         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1291         struct drm_i915_private *dev_priv = dev->dev_private;
1292         u32 pp;
1293         u32 pp_ctrl_reg;
1294
1295         if (!is_edp(intel_dp))
1296                 return;
1297
1298         intel_panel_disable_backlight(intel_dp->attached_connector);
1299
1300         DRM_DEBUG_KMS("\n");
1301         pp = ironlake_get_pp_control(intel_dp);
1302         pp &= ~EDP_BLC_ENABLE;
1303
1304         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1305
1306         I915_WRITE(pp_ctrl_reg, pp);
1307         POSTING_READ(pp_ctrl_reg);
1308         msleep(intel_dp->backlight_off_delay);
1309 }
1310
1311 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1312 {
1313         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1314         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1315         struct drm_device *dev = crtc->dev;
1316         struct drm_i915_private *dev_priv = dev->dev_private;
1317         u32 dpa_ctl;
1318
1319         assert_pipe_disabled(dev_priv,
1320                              to_intel_crtc(crtc)->pipe);
1321
1322         DRM_DEBUG_KMS("\n");
1323         dpa_ctl = I915_READ(DP_A);
1324         WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1325         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1326
1327         /* We don't adjust intel_dp->DP while tearing down the link, to
1328          * facilitate link retraining (e.g. after hotplug). Hence clear all
1329          * enable bits here to ensure that we don't enable too much. */
1330         intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1331         intel_dp->DP |= DP_PLL_ENABLE;
1332         I915_WRITE(DP_A, intel_dp->DP);
1333         POSTING_READ(DP_A);
1334         udelay(200);
1335 }
1336
1337 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1338 {
1339         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1340         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1341         struct drm_device *dev = crtc->dev;
1342         struct drm_i915_private *dev_priv = dev->dev_private;
1343         u32 dpa_ctl;
1344
1345         assert_pipe_disabled(dev_priv,
1346                              to_intel_crtc(crtc)->pipe);
1347
1348         dpa_ctl = I915_READ(DP_A);
1349         WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1350              "dp pll off, should be on\n");
1351         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1352
1353         /* We can't rely on the value tracked for the DP register in
1354          * intel_dp->DP because link_down must not change that (otherwise link
1355          * re-training will fail. */
1356         dpa_ctl &= ~DP_PLL_ENABLE;
1357         I915_WRITE(DP_A, dpa_ctl);
1358         POSTING_READ(DP_A);
1359         udelay(200);
1360 }
1361
1362 /* If the sink supports it, try to set the power state appropriately */
1363 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1364 {
1365         int ret, i;
1366
1367         /* Should have a valid DPCD by this point */
1368         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1369                 return;
1370
1371         if (mode != DRM_MODE_DPMS_ON) {
1372                 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1373                                                   DP_SET_POWER_D3);
1374                 if (ret != 1)
1375                         DRM_DEBUG_DRIVER("failed to write sink power state\n");
1376         } else {
1377                 /*
1378                  * When turning on, we need to retry for 1ms to give the sink
1379                  * time to wake up.
1380                  */
1381                 for (i = 0; i < 3; i++) {
1382                         ret = intel_dp_aux_native_write_1(intel_dp,
1383                                                           DP_SET_POWER,
1384                                                           DP_SET_POWER_D0);
1385                         if (ret == 1)
1386                                 break;
1387                         msleep(1);
1388                 }
1389         }
1390 }
1391
1392 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1393                                   enum pipe *pipe)
1394 {
1395         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1396         enum port port = dp_to_dig_port(intel_dp)->port;
1397         struct drm_device *dev = encoder->base.dev;
1398         struct drm_i915_private *dev_priv = dev->dev_private;
1399         u32 tmp = I915_READ(intel_dp->output_reg);
1400
1401         if (!(tmp & DP_PORT_EN))
1402                 return false;
1403
1404         if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1405                 *pipe = PORT_TO_PIPE_CPT(tmp);
1406         } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1407                 *pipe = PORT_TO_PIPE(tmp);
1408         } else {
1409                 u32 trans_sel;
1410                 u32 trans_dp;
1411                 int i;
1412
1413                 switch (intel_dp->output_reg) {
1414                 case PCH_DP_B:
1415                         trans_sel = TRANS_DP_PORT_SEL_B;
1416                         break;
1417                 case PCH_DP_C:
1418                         trans_sel = TRANS_DP_PORT_SEL_C;
1419                         break;
1420                 case PCH_DP_D:
1421                         trans_sel = TRANS_DP_PORT_SEL_D;
1422                         break;
1423                 default:
1424                         return true;
1425                 }
1426
1427                 for_each_pipe(i) {
1428                         trans_dp = I915_READ(TRANS_DP_CTL(i));
1429                         if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1430                                 *pipe = i;
1431                                 return true;
1432                         }
1433                 }
1434
1435                 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1436                               intel_dp->output_reg);
1437         }
1438
1439         return true;
1440 }
1441
1442 static void intel_dp_get_config(struct intel_encoder *encoder,
1443                                 struct intel_crtc_config *pipe_config)
1444 {
1445         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1446         u32 tmp, flags = 0;
1447         struct drm_device *dev = encoder->base.dev;
1448         struct drm_i915_private *dev_priv = dev->dev_private;
1449         enum port port = dp_to_dig_port(intel_dp)->port;
1450         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1451         int dotclock;
1452
1453         if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
1454                 tmp = I915_READ(intel_dp->output_reg);
1455                 if (tmp & DP_SYNC_HS_HIGH)
1456                         flags |= DRM_MODE_FLAG_PHSYNC;
1457                 else
1458                         flags |= DRM_MODE_FLAG_NHSYNC;
1459
1460                 if (tmp & DP_SYNC_VS_HIGH)
1461                         flags |= DRM_MODE_FLAG_PVSYNC;
1462                 else
1463                         flags |= DRM_MODE_FLAG_NVSYNC;
1464         } else {
1465                 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1466                 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1467                         flags |= DRM_MODE_FLAG_PHSYNC;
1468                 else
1469                         flags |= DRM_MODE_FLAG_NHSYNC;
1470
1471                 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1472                         flags |= DRM_MODE_FLAG_PVSYNC;
1473                 else
1474                         flags |= DRM_MODE_FLAG_NVSYNC;
1475         }
1476
1477         pipe_config->adjusted_mode.flags |= flags;
1478
1479         pipe_config->has_dp_encoder = true;
1480
1481         intel_dp_get_m_n(crtc, pipe_config);
1482
1483         if (port == PORT_A) {
1484                 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1485                         pipe_config->port_clock = 162000;
1486                 else
1487                         pipe_config->port_clock = 270000;
1488         }
1489
1490         dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1491                                             &pipe_config->dp_m_n);
1492
1493         if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1494                 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1495
1496         pipe_config->adjusted_mode.crtc_clock = dotclock;
1497
1498         if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1499             pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1500                 /*
1501                  * This is a big fat ugly hack.
1502                  *
1503                  * Some machines in UEFI boot mode provide us a VBT that has 18
1504                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1505                  * unknown we fail to light up. Yet the same BIOS boots up with
1506                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1507                  * max, not what it tells us to use.
1508                  *
1509                  * Note: This will still be broken if the eDP panel is not lit
1510                  * up by the BIOS, and thus we can't get the mode at module
1511                  * load.
1512                  */
1513                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1514                               pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1515                 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1516         }
1517 }
1518
1519 static bool is_edp_psr(struct drm_device *dev)
1520 {
1521         struct drm_i915_private *dev_priv = dev->dev_private;
1522
1523         return dev_priv->psr.sink_support;
1524 }
1525
1526 static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1527 {
1528         struct drm_i915_private *dev_priv = dev->dev_private;
1529
1530         if (!HAS_PSR(dev))
1531                 return false;
1532
1533         return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
1534 }
1535
1536 static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1537                                     struct edp_vsc_psr *vsc_psr)
1538 {
1539         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1540         struct drm_device *dev = dig_port->base.base.dev;
1541         struct drm_i915_private *dev_priv = dev->dev_private;
1542         struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1543         u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1544         u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1545         uint32_t *data = (uint32_t *) vsc_psr;
1546         unsigned int i;
1547
1548         /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1549            the video DIP being updated before program video DIP data buffer
1550            registers for DIP being updated. */
1551         I915_WRITE(ctl_reg, 0);
1552         POSTING_READ(ctl_reg);
1553
1554         for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1555                 if (i < sizeof(struct edp_vsc_psr))
1556                         I915_WRITE(data_reg + i, *data++);
1557                 else
1558                         I915_WRITE(data_reg + i, 0);
1559         }
1560
1561         I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1562         POSTING_READ(ctl_reg);
1563 }
1564
1565 static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1566 {
1567         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1568         struct drm_i915_private *dev_priv = dev->dev_private;
1569         struct edp_vsc_psr psr_vsc;
1570
1571         if (intel_dp->psr_setup_done)
1572                 return;
1573
1574         /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1575         memset(&psr_vsc, 0, sizeof(psr_vsc));
1576         psr_vsc.sdp_header.HB0 = 0;
1577         psr_vsc.sdp_header.HB1 = 0x7;
1578         psr_vsc.sdp_header.HB2 = 0x2;
1579         psr_vsc.sdp_header.HB3 = 0x8;
1580         intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1581
1582         /* Avoid continuous PSR exit by masking memup and hpd */
1583         I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
1584                    EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
1585
1586         intel_dp->psr_setup_done = true;
1587 }
1588
1589 static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1590 {
1591         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1592         struct drm_i915_private *dev_priv = dev->dev_private;
1593         uint32_t aux_clock_divider = get_aux_clock_divider(intel_dp, 0);
1594         int precharge = 0x3;
1595         int msg_size = 5;       /* Header(4) + Message(1) */
1596
1597         /* Enable PSR in sink */
1598         if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT)
1599                 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1600                                             DP_PSR_ENABLE &
1601                                             ~DP_PSR_MAIN_LINK_ACTIVE);
1602         else
1603                 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1604                                             DP_PSR_ENABLE |
1605                                             DP_PSR_MAIN_LINK_ACTIVE);
1606
1607         /* Setup AUX registers */
1608         I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
1609         I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
1610         I915_WRITE(EDP_PSR_AUX_CTL(dev),
1611                    DP_AUX_CH_CTL_TIME_OUT_400us |
1612                    (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1613                    (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1614                    (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1615 }
1616
1617 static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1618 {
1619         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1620         struct drm_i915_private *dev_priv = dev->dev_private;
1621         uint32_t max_sleep_time = 0x1f;
1622         uint32_t idle_frames = 1;
1623         uint32_t val = 0x0;
1624         const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
1625
1626         if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
1627                 val |= EDP_PSR_LINK_STANDBY;
1628                 val |= EDP_PSR_TP2_TP3_TIME_0us;
1629                 val |= EDP_PSR_TP1_TIME_0us;
1630                 val |= EDP_PSR_SKIP_AUX_EXIT;
1631         } else
1632                 val |= EDP_PSR_LINK_DISABLE;
1633
1634         I915_WRITE(EDP_PSR_CTL(dev), val |
1635                    IS_BROADWELL(dev) ? 0 : link_entry_time |
1636                    max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1637                    idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1638                    EDP_PSR_ENABLE);
1639 }
1640
1641 static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1642 {
1643         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1644         struct drm_device *dev = dig_port->base.base.dev;
1645         struct drm_i915_private *dev_priv = dev->dev_private;
1646         struct drm_crtc *crtc = dig_port->base.base.crtc;
1647         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1648         struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->fb)->obj;
1649         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
1650
1651         dev_priv->psr.source_ok = false;
1652
1653         if (!HAS_PSR(dev)) {
1654                 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1655                 return false;
1656         }
1657
1658         if ((intel_encoder->type != INTEL_OUTPUT_EDP) ||
1659             (dig_port->port != PORT_A)) {
1660                 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
1661                 return false;
1662         }
1663
1664         if (!i915_enable_psr) {
1665                 DRM_DEBUG_KMS("PSR disable by flag\n");
1666                 return false;
1667         }
1668
1669         crtc = dig_port->base.base.crtc;
1670         if (crtc == NULL) {
1671                 DRM_DEBUG_KMS("crtc not active for PSR\n");
1672                 return false;
1673         }
1674
1675         intel_crtc = to_intel_crtc(crtc);
1676         if (!intel_crtc_active(crtc)) {
1677                 DRM_DEBUG_KMS("crtc not active for PSR\n");
1678                 return false;
1679         }
1680
1681         obj = to_intel_framebuffer(crtc->fb)->obj;
1682         if (obj->tiling_mode != I915_TILING_X ||
1683             obj->fence_reg == I915_FENCE_REG_NONE) {
1684                 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
1685                 return false;
1686         }
1687
1688         if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
1689                 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
1690                 return false;
1691         }
1692
1693         if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1694             S3D_ENABLE) {
1695                 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
1696                 return false;
1697         }
1698
1699         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
1700                 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
1701                 return false;
1702         }
1703
1704         dev_priv->psr.source_ok = true;
1705         return true;
1706 }
1707
1708 static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
1709 {
1710         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1711
1712         if (!intel_edp_psr_match_conditions(intel_dp) ||
1713             intel_edp_is_psr_enabled(dev))
1714                 return;
1715
1716         /* Setup PSR once */
1717         intel_edp_psr_setup(intel_dp);
1718
1719         /* Enable PSR on the panel */
1720         intel_edp_psr_enable_sink(intel_dp);
1721
1722         /* Enable PSR on the host */
1723         intel_edp_psr_enable_source(intel_dp);
1724 }
1725
1726 void intel_edp_psr_enable(struct intel_dp *intel_dp)
1727 {
1728         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1729
1730         if (intel_edp_psr_match_conditions(intel_dp) &&
1731             !intel_edp_is_psr_enabled(dev))
1732                 intel_edp_psr_do_enable(intel_dp);
1733 }
1734
1735 void intel_edp_psr_disable(struct intel_dp *intel_dp)
1736 {
1737         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1738         struct drm_i915_private *dev_priv = dev->dev_private;
1739
1740         if (!intel_edp_is_psr_enabled(dev))
1741                 return;
1742
1743         I915_WRITE(EDP_PSR_CTL(dev),
1744                    I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
1745
1746         /* Wait till PSR is idle */
1747         if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
1748                        EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1749                 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1750 }
1751
1752 void intel_edp_psr_update(struct drm_device *dev)
1753 {
1754         struct intel_encoder *encoder;
1755         struct intel_dp *intel_dp = NULL;
1756
1757         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
1758                 if (encoder->type == INTEL_OUTPUT_EDP) {
1759                         intel_dp = enc_to_intel_dp(&encoder->base);
1760
1761                         if (!is_edp_psr(dev))
1762                                 return;
1763
1764                         if (!intel_edp_psr_match_conditions(intel_dp))
1765                                 intel_edp_psr_disable(intel_dp);
1766                         else
1767                                 if (!intel_edp_is_psr_enabled(dev))
1768                                         intel_edp_psr_do_enable(intel_dp);
1769                 }
1770 }
1771
1772 static void intel_disable_dp(struct intel_encoder *encoder)
1773 {
1774         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1775         enum port port = dp_to_dig_port(intel_dp)->port;
1776         struct drm_device *dev = encoder->base.dev;
1777
1778         /* Make sure the panel is off before trying to change the mode. But also
1779          * ensure that we have vdd while we switch off the panel. */
1780         ironlake_edp_backlight_off(intel_dp);
1781         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
1782         ironlake_edp_panel_off(intel_dp);
1783
1784         /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1785         if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
1786                 intel_dp_link_down(intel_dp);
1787 }
1788
1789 static void intel_post_disable_dp(struct intel_encoder *encoder)
1790 {
1791         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1792         enum port port = dp_to_dig_port(intel_dp)->port;
1793         struct drm_device *dev = encoder->base.dev;
1794
1795         if (port == PORT_A || IS_VALLEYVIEW(dev)) {
1796                 intel_dp_link_down(intel_dp);
1797                 if (!IS_VALLEYVIEW(dev))
1798                         ironlake_edp_pll_off(intel_dp);
1799         }
1800 }
1801
1802 static void intel_enable_dp(struct intel_encoder *encoder)
1803 {
1804         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1805         struct drm_device *dev = encoder->base.dev;
1806         struct drm_i915_private *dev_priv = dev->dev_private;
1807         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1808
1809         if (WARN_ON(dp_reg & DP_PORT_EN))
1810                 return;
1811
1812         ironlake_edp_panel_vdd_on(intel_dp);
1813         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1814         intel_dp_start_link_train(intel_dp);
1815         ironlake_edp_panel_on(intel_dp);
1816         ironlake_edp_panel_vdd_off(intel_dp, true);
1817         intel_dp_complete_link_train(intel_dp);
1818         intel_dp_stop_link_train(intel_dp);
1819 }
1820
1821 static void g4x_enable_dp(struct intel_encoder *encoder)
1822 {
1823         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1824
1825         intel_enable_dp(encoder);
1826         ironlake_edp_backlight_on(intel_dp);
1827 }
1828
1829 static void vlv_enable_dp(struct intel_encoder *encoder)
1830 {
1831         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1832
1833         ironlake_edp_backlight_on(intel_dp);
1834 }
1835
1836 static void g4x_pre_enable_dp(struct intel_encoder *encoder)
1837 {
1838         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1839         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1840
1841         if (dport->port == PORT_A)
1842                 ironlake_edp_pll_on(intel_dp);
1843 }
1844
1845 static void vlv_pre_enable_dp(struct intel_encoder *encoder)
1846 {
1847         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1848         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1849         struct drm_device *dev = encoder->base.dev;
1850         struct drm_i915_private *dev_priv = dev->dev_private;
1851         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1852         enum dpio_channel port = vlv_dport_to_channel(dport);
1853         int pipe = intel_crtc->pipe;
1854         struct edp_power_seq power_seq;
1855         u32 val;
1856
1857         mutex_lock(&dev_priv->dpio_lock);
1858
1859         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
1860         val = 0;
1861         if (pipe)
1862                 val |= (1<<21);
1863         else
1864                 val &= ~(1<<21);
1865         val |= 0x001000c4;
1866         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1867         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1868         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
1869
1870         mutex_unlock(&dev_priv->dpio_lock);
1871
1872         if (is_edp(intel_dp)) {
1873                 /* init power sequencer on this pipe and port */
1874                 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
1875                 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
1876                                                               &power_seq);
1877         }
1878
1879         intel_enable_dp(encoder);
1880
1881         vlv_wait_port_ready(dev_priv, dport);
1882 }
1883
1884 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
1885 {
1886         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1887         struct drm_device *dev = encoder->base.dev;
1888         struct drm_i915_private *dev_priv = dev->dev_private;
1889         struct intel_crtc *intel_crtc =
1890                 to_intel_crtc(encoder->base.crtc);
1891         enum dpio_channel port = vlv_dport_to_channel(dport);
1892         int pipe = intel_crtc->pipe;
1893
1894         /* Program Tx lane resets to default */
1895         mutex_lock(&dev_priv->dpio_lock);
1896         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
1897                          DPIO_PCS_TX_LANE2_RESET |
1898                          DPIO_PCS_TX_LANE1_RESET);
1899         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
1900                          DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1901                          DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1902                          (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1903                                  DPIO_PCS_CLK_SOFT_RESET);
1904
1905         /* Fix up inter-pair skew failure */
1906         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
1907         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
1908         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
1909         mutex_unlock(&dev_priv->dpio_lock);
1910 }
1911
1912 /*
1913  * Native read with retry for link status and receiver capability reads for
1914  * cases where the sink may still be asleep.
1915  */
1916 static bool
1917 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1918                                uint8_t *recv, int recv_bytes)
1919 {
1920         int ret, i;
1921
1922         /*
1923          * Sinks are *supposed* to come up within 1ms from an off state,
1924          * but we're also supposed to retry 3 times per the spec.
1925          */
1926         for (i = 0; i < 3; i++) {
1927                 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1928                                                recv_bytes);
1929                 if (ret == recv_bytes)
1930                         return true;
1931                 msleep(1);
1932         }
1933
1934         return false;
1935 }
1936
1937 /*
1938  * Fetch AUX CH registers 0x202 - 0x207 which contain
1939  * link status information
1940  */
1941 static bool
1942 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1943 {
1944         return intel_dp_aux_native_read_retry(intel_dp,
1945                                               DP_LANE0_1_STATUS,
1946                                               link_status,
1947                                               DP_LINK_STATUS_SIZE);
1948 }
1949
1950 /*
1951  * These are source-specific values; current Intel hardware supports
1952  * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1953  */
1954
1955 static uint8_t
1956 intel_dp_voltage_max(struct intel_dp *intel_dp)
1957 {
1958         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1959         enum port port = dp_to_dig_port(intel_dp)->port;
1960
1961         if (IS_VALLEYVIEW(dev) || IS_BROADWELL(dev))
1962                 return DP_TRAIN_VOLTAGE_SWING_1200;
1963         else if (IS_GEN7(dev) && port == PORT_A)
1964                 return DP_TRAIN_VOLTAGE_SWING_800;
1965         else if (HAS_PCH_CPT(dev) && port != PORT_A)
1966                 return DP_TRAIN_VOLTAGE_SWING_1200;
1967         else
1968                 return DP_TRAIN_VOLTAGE_SWING_800;
1969 }
1970
1971 static uint8_t
1972 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1973 {
1974         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1975         enum port port = dp_to_dig_port(intel_dp)->port;
1976
1977         if (IS_BROADWELL(dev)) {
1978                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1979                 case DP_TRAIN_VOLTAGE_SWING_400:
1980                 case DP_TRAIN_VOLTAGE_SWING_600:
1981                         return DP_TRAIN_PRE_EMPHASIS_6;
1982                 case DP_TRAIN_VOLTAGE_SWING_800:
1983                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1984                 case DP_TRAIN_VOLTAGE_SWING_1200:
1985                 default:
1986                         return DP_TRAIN_PRE_EMPHASIS_0;
1987                 }
1988         } else if (IS_HASWELL(dev)) {
1989                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1990                 case DP_TRAIN_VOLTAGE_SWING_400:
1991                         return DP_TRAIN_PRE_EMPHASIS_9_5;
1992                 case DP_TRAIN_VOLTAGE_SWING_600:
1993                         return DP_TRAIN_PRE_EMPHASIS_6;
1994                 case DP_TRAIN_VOLTAGE_SWING_800:
1995                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1996                 case DP_TRAIN_VOLTAGE_SWING_1200:
1997                 default:
1998                         return DP_TRAIN_PRE_EMPHASIS_0;
1999                 }
2000         } else if (IS_VALLEYVIEW(dev)) {
2001                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2002                 case DP_TRAIN_VOLTAGE_SWING_400:
2003                         return DP_TRAIN_PRE_EMPHASIS_9_5;
2004                 case DP_TRAIN_VOLTAGE_SWING_600:
2005                         return DP_TRAIN_PRE_EMPHASIS_6;
2006                 case DP_TRAIN_VOLTAGE_SWING_800:
2007                         return DP_TRAIN_PRE_EMPHASIS_3_5;
2008                 case DP_TRAIN_VOLTAGE_SWING_1200:
2009                 default:
2010                         return DP_TRAIN_PRE_EMPHASIS_0;
2011                 }
2012         } else if (IS_GEN7(dev) && port == PORT_A) {
2013                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2014                 case DP_TRAIN_VOLTAGE_SWING_400:
2015                         return DP_TRAIN_PRE_EMPHASIS_6;
2016                 case DP_TRAIN_VOLTAGE_SWING_600:
2017                 case DP_TRAIN_VOLTAGE_SWING_800:
2018                         return DP_TRAIN_PRE_EMPHASIS_3_5;
2019                 default:
2020                         return DP_TRAIN_PRE_EMPHASIS_0;
2021                 }
2022         } else {
2023                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2024                 case DP_TRAIN_VOLTAGE_SWING_400:
2025                         return DP_TRAIN_PRE_EMPHASIS_6;
2026                 case DP_TRAIN_VOLTAGE_SWING_600:
2027                         return DP_TRAIN_PRE_EMPHASIS_6;
2028                 case DP_TRAIN_VOLTAGE_SWING_800:
2029                         return DP_TRAIN_PRE_EMPHASIS_3_5;
2030                 case DP_TRAIN_VOLTAGE_SWING_1200:
2031                 default:
2032                         return DP_TRAIN_PRE_EMPHASIS_0;
2033                 }
2034         }
2035 }
2036
2037 static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2038 {
2039         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2040         struct drm_i915_private *dev_priv = dev->dev_private;
2041         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2042         struct intel_crtc *intel_crtc =
2043                 to_intel_crtc(dport->base.base.crtc);
2044         unsigned long demph_reg_value, preemph_reg_value,
2045                 uniqtranscale_reg_value;
2046         uint8_t train_set = intel_dp->train_set[0];
2047         enum dpio_channel port = vlv_dport_to_channel(dport);
2048         int pipe = intel_crtc->pipe;
2049
2050         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2051         case DP_TRAIN_PRE_EMPHASIS_0:
2052                 preemph_reg_value = 0x0004000;
2053                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2054                 case DP_TRAIN_VOLTAGE_SWING_400:
2055                         demph_reg_value = 0x2B405555;
2056                         uniqtranscale_reg_value = 0x552AB83A;
2057                         break;
2058                 case DP_TRAIN_VOLTAGE_SWING_600:
2059                         demph_reg_value = 0x2B404040;
2060                         uniqtranscale_reg_value = 0x5548B83A;
2061                         break;
2062                 case DP_TRAIN_VOLTAGE_SWING_800:
2063                         demph_reg_value = 0x2B245555;
2064                         uniqtranscale_reg_value = 0x5560B83A;
2065                         break;
2066                 case DP_TRAIN_VOLTAGE_SWING_1200:
2067                         demph_reg_value = 0x2B405555;
2068                         uniqtranscale_reg_value = 0x5598DA3A;
2069                         break;
2070                 default:
2071                         return 0;
2072                 }
2073                 break;
2074         case DP_TRAIN_PRE_EMPHASIS_3_5:
2075                 preemph_reg_value = 0x0002000;
2076                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2077                 case DP_TRAIN_VOLTAGE_SWING_400:
2078                         demph_reg_value = 0x2B404040;
2079                         uniqtranscale_reg_value = 0x5552B83A;
2080                         break;
2081                 case DP_TRAIN_VOLTAGE_SWING_600:
2082                         demph_reg_value = 0x2B404848;
2083                         uniqtranscale_reg_value = 0x5580B83A;
2084                         break;
2085                 case DP_TRAIN_VOLTAGE_SWING_800:
2086                         demph_reg_value = 0x2B404040;
2087                         uniqtranscale_reg_value = 0x55ADDA3A;
2088                         break;
2089                 default:
2090                         return 0;
2091                 }
2092                 break;
2093         case DP_TRAIN_PRE_EMPHASIS_6:
2094                 preemph_reg_value = 0x0000000;
2095                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2096                 case DP_TRAIN_VOLTAGE_SWING_400:
2097                         demph_reg_value = 0x2B305555;
2098                         uniqtranscale_reg_value = 0x5570B83A;
2099                         break;
2100                 case DP_TRAIN_VOLTAGE_SWING_600:
2101                         demph_reg_value = 0x2B2B4040;
2102                         uniqtranscale_reg_value = 0x55ADDA3A;
2103                         break;
2104                 default:
2105                         return 0;
2106                 }
2107                 break;
2108         case DP_TRAIN_PRE_EMPHASIS_9_5:
2109                 preemph_reg_value = 0x0006000;
2110                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2111                 case DP_TRAIN_VOLTAGE_SWING_400:
2112                         demph_reg_value = 0x1B405555;
2113                         uniqtranscale_reg_value = 0x55ADDA3A;
2114                         break;
2115                 default:
2116                         return 0;
2117                 }
2118                 break;
2119         default:
2120                 return 0;
2121         }
2122
2123         mutex_lock(&dev_priv->dpio_lock);
2124         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2125         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2126         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
2127                          uniqtranscale_reg_value);
2128         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2129         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2130         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2131         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
2132         mutex_unlock(&dev_priv->dpio_lock);
2133
2134         return 0;
2135 }
2136
2137 static void
2138 intel_get_adjust_train(struct intel_dp *intel_dp,
2139                        const uint8_t link_status[DP_LINK_STATUS_SIZE])
2140 {
2141         uint8_t v = 0;
2142         uint8_t p = 0;
2143         int lane;
2144         uint8_t voltage_max;
2145         uint8_t preemph_max;
2146
2147         for (lane = 0; lane < intel_dp->lane_count; lane++) {
2148                 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2149                 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
2150
2151                 if (this_v > v)
2152                         v = this_v;
2153                 if (this_p > p)
2154                         p = this_p;
2155         }
2156
2157         voltage_max = intel_dp_voltage_max(intel_dp);
2158         if (v >= voltage_max)
2159                 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
2160
2161         preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2162         if (p >= preemph_max)
2163                 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
2164
2165         for (lane = 0; lane < 4; lane++)
2166                 intel_dp->train_set[lane] = v | p;
2167 }
2168
2169 static uint32_t
2170 intel_gen4_signal_levels(uint8_t train_set)
2171 {
2172         uint32_t        signal_levels = 0;
2173
2174         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2175         case DP_TRAIN_VOLTAGE_SWING_400:
2176         default:
2177                 signal_levels |= DP_VOLTAGE_0_4;
2178                 break;
2179         case DP_TRAIN_VOLTAGE_SWING_600:
2180                 signal_levels |= DP_VOLTAGE_0_6;
2181                 break;
2182         case DP_TRAIN_VOLTAGE_SWING_800:
2183                 signal_levels |= DP_VOLTAGE_0_8;
2184                 break;
2185         case DP_TRAIN_VOLTAGE_SWING_1200:
2186                 signal_levels |= DP_VOLTAGE_1_2;
2187                 break;
2188         }
2189         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2190         case DP_TRAIN_PRE_EMPHASIS_0:
2191         default:
2192                 signal_levels |= DP_PRE_EMPHASIS_0;
2193                 break;
2194         case DP_TRAIN_PRE_EMPHASIS_3_5:
2195                 signal_levels |= DP_PRE_EMPHASIS_3_5;
2196                 break;
2197         case DP_TRAIN_PRE_EMPHASIS_6:
2198                 signal_levels |= DP_PRE_EMPHASIS_6;
2199                 break;
2200         case DP_TRAIN_PRE_EMPHASIS_9_5:
2201                 signal_levels |= DP_PRE_EMPHASIS_9_5;
2202                 break;
2203         }
2204         return signal_levels;
2205 }
2206
2207 /* Gen6's DP voltage swing and pre-emphasis control */
2208 static uint32_t
2209 intel_gen6_edp_signal_levels(uint8_t train_set)
2210 {
2211         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2212                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2213         switch (signal_levels) {
2214         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2215         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2216                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2217         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2218                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
2219         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2220         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2221                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
2222         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2223         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2224                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
2225         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2226         case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2227                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
2228         default:
2229                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2230                               "0x%x\n", signal_levels);
2231                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2232         }
2233 }
2234
2235 /* Gen7's DP voltage swing and pre-emphasis control */
2236 static uint32_t
2237 intel_gen7_edp_signal_levels(uint8_t train_set)
2238 {
2239         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2240                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2241         switch (signal_levels) {
2242         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2243                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2244         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2245                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2246         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2247                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2248
2249         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2250                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2251         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2252                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2253
2254         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2255                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2256         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2257                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2258
2259         default:
2260                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2261                               "0x%x\n", signal_levels);
2262                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2263         }
2264 }
2265
2266 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2267 static uint32_t
2268 intel_hsw_signal_levels(uint8_t train_set)
2269 {
2270         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2271                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2272         switch (signal_levels) {
2273         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2274                 return DDI_BUF_EMP_400MV_0DB_HSW;
2275         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2276                 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2277         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2278                 return DDI_BUF_EMP_400MV_6DB_HSW;
2279         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2280                 return DDI_BUF_EMP_400MV_9_5DB_HSW;
2281
2282         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2283                 return DDI_BUF_EMP_600MV_0DB_HSW;
2284         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2285                 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2286         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2287                 return DDI_BUF_EMP_600MV_6DB_HSW;
2288
2289         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2290                 return DDI_BUF_EMP_800MV_0DB_HSW;
2291         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2292                 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2293         default:
2294                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2295                               "0x%x\n", signal_levels);
2296                 return DDI_BUF_EMP_400MV_0DB_HSW;
2297         }
2298 }
2299
2300 static uint32_t
2301 intel_bdw_signal_levels(uint8_t train_set)
2302 {
2303         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2304                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2305         switch (signal_levels) {
2306         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2307                 return DDI_BUF_EMP_400MV_0DB_BDW;       /* Sel0 */
2308         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2309                 return DDI_BUF_EMP_400MV_3_5DB_BDW;     /* Sel1 */
2310         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2311                 return DDI_BUF_EMP_400MV_6DB_BDW;       /* Sel2 */
2312
2313         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2314                 return DDI_BUF_EMP_600MV_0DB_BDW;       /* Sel3 */
2315         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2316                 return DDI_BUF_EMP_600MV_3_5DB_BDW;     /* Sel4 */
2317         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2318                 return DDI_BUF_EMP_600MV_6DB_BDW;       /* Sel5 */
2319
2320         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2321                 return DDI_BUF_EMP_800MV_0DB_BDW;       /* Sel6 */
2322         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2323                 return DDI_BUF_EMP_800MV_3_5DB_BDW;     /* Sel7 */
2324
2325         case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2326                 return DDI_BUF_EMP_1200MV_0DB_BDW;      /* Sel8 */
2327
2328         default:
2329                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2330                               "0x%x\n", signal_levels);
2331                 return DDI_BUF_EMP_400MV_0DB_BDW;       /* Sel0 */
2332         }
2333 }
2334
2335 /* Properly updates "DP" with the correct signal levels. */
2336 static void
2337 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2338 {
2339         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2340         enum port port = intel_dig_port->port;
2341         struct drm_device *dev = intel_dig_port->base.base.dev;
2342         uint32_t signal_levels, mask;
2343         uint8_t train_set = intel_dp->train_set[0];
2344
2345         if (IS_BROADWELL(dev)) {
2346                 signal_levels = intel_bdw_signal_levels(train_set);
2347                 mask = DDI_BUF_EMP_MASK;
2348         } else if (IS_HASWELL(dev)) {
2349                 signal_levels = intel_hsw_signal_levels(train_set);
2350                 mask = DDI_BUF_EMP_MASK;
2351         } else if (IS_VALLEYVIEW(dev)) {
2352                 signal_levels = intel_vlv_signal_levels(intel_dp);
2353                 mask = 0;
2354         } else if (IS_GEN7(dev) && port == PORT_A) {
2355                 signal_levels = intel_gen7_edp_signal_levels(train_set);
2356                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
2357         } else if (IS_GEN6(dev) && port == PORT_A) {
2358                 signal_levels = intel_gen6_edp_signal_levels(train_set);
2359                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2360         } else {
2361                 signal_levels = intel_gen4_signal_levels(train_set);
2362                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2363         }
2364
2365         DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2366
2367         *DP = (*DP & ~mask) | signal_levels;
2368 }
2369
2370 static bool
2371 intel_dp_set_link_train(struct intel_dp *intel_dp,
2372                         uint32_t *DP,
2373                         uint8_t dp_train_pat)
2374 {
2375         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2376         struct drm_device *dev = intel_dig_port->base.base.dev;
2377         struct drm_i915_private *dev_priv = dev->dev_private;
2378         enum port port = intel_dig_port->port;
2379         uint8_t buf[sizeof(intel_dp->train_set) + 1];
2380         int ret, len;
2381
2382         if (HAS_DDI(dev)) {
2383                 uint32_t temp = I915_READ(DP_TP_CTL(port));
2384
2385                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2386                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2387                 else
2388                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2389
2390                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2391                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2392                 case DP_TRAINING_PATTERN_DISABLE:
2393                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2394
2395                         break;
2396                 case DP_TRAINING_PATTERN_1:
2397                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2398                         break;
2399                 case DP_TRAINING_PATTERN_2:
2400                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2401                         break;
2402                 case DP_TRAINING_PATTERN_3:
2403                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2404                         break;
2405                 }
2406                 I915_WRITE(DP_TP_CTL(port), temp);
2407
2408         } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2409                 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2410
2411                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2412                 case DP_TRAINING_PATTERN_DISABLE:
2413                         *DP |= DP_LINK_TRAIN_OFF_CPT;
2414                         break;
2415                 case DP_TRAINING_PATTERN_1:
2416                         *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2417                         break;
2418                 case DP_TRAINING_PATTERN_2:
2419                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2420                         break;
2421                 case DP_TRAINING_PATTERN_3:
2422                         DRM_ERROR("DP training pattern 3 not supported\n");
2423                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2424                         break;
2425                 }
2426
2427         } else {
2428                 *DP &= ~DP_LINK_TRAIN_MASK;
2429
2430                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2431                 case DP_TRAINING_PATTERN_DISABLE:
2432                         *DP |= DP_LINK_TRAIN_OFF;
2433                         break;
2434                 case DP_TRAINING_PATTERN_1:
2435                         *DP |= DP_LINK_TRAIN_PAT_1;
2436                         break;
2437                 case DP_TRAINING_PATTERN_2:
2438                         *DP |= DP_LINK_TRAIN_PAT_2;
2439                         break;
2440                 case DP_TRAINING_PATTERN_3:
2441                         DRM_ERROR("DP training pattern 3 not supported\n");
2442                         *DP |= DP_LINK_TRAIN_PAT_2;
2443                         break;
2444                 }
2445         }
2446
2447         I915_WRITE(intel_dp->output_reg, *DP);
2448         POSTING_READ(intel_dp->output_reg);
2449
2450         buf[0] = dp_train_pat;
2451         if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
2452             DP_TRAINING_PATTERN_DISABLE) {
2453                 /* don't write DP_TRAINING_LANEx_SET on disable */
2454                 len = 1;
2455         } else {
2456                 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
2457                 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
2458                 len = intel_dp->lane_count + 1;
2459         }
2460
2461         ret = intel_dp_aux_native_write(intel_dp, DP_TRAINING_PATTERN_SET,
2462                                         buf, len);
2463
2464         return ret == len;
2465 }
2466
2467 static bool
2468 intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2469                         uint8_t dp_train_pat)
2470 {
2471         memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
2472         intel_dp_set_signal_levels(intel_dp, DP);
2473         return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
2474 }
2475
2476 static bool
2477 intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2478                            const uint8_t link_status[DP_LINK_STATUS_SIZE])
2479 {
2480         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2481         struct drm_device *dev = intel_dig_port->base.base.dev;
2482         struct drm_i915_private *dev_priv = dev->dev_private;
2483         int ret;
2484
2485         intel_get_adjust_train(intel_dp, link_status);
2486         intel_dp_set_signal_levels(intel_dp, DP);
2487
2488         I915_WRITE(intel_dp->output_reg, *DP);
2489         POSTING_READ(intel_dp->output_reg);
2490
2491         ret = intel_dp_aux_native_write(intel_dp, DP_TRAINING_LANE0_SET,
2492                                         intel_dp->train_set,
2493                                         intel_dp->lane_count);
2494
2495         return ret == intel_dp->lane_count;
2496 }
2497
2498 static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
2499 {
2500         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2501         struct drm_device *dev = intel_dig_port->base.base.dev;
2502         struct drm_i915_private *dev_priv = dev->dev_private;
2503         enum port port = intel_dig_port->port;
2504         uint32_t val;
2505
2506         if (!HAS_DDI(dev))
2507                 return;
2508
2509         val = I915_READ(DP_TP_CTL(port));
2510         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2511         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
2512         I915_WRITE(DP_TP_CTL(port), val);
2513
2514         /*
2515          * On PORT_A we can have only eDP in SST mode. There the only reason
2516          * we need to set idle transmission mode is to work around a HW issue
2517          * where we enable the pipe while not in idle link-training mode.
2518          * In this case there is requirement to wait for a minimum number of
2519          * idle patterns to be sent.
2520          */
2521         if (port == PORT_A)
2522                 return;
2523
2524         if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2525                      1))
2526                 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2527 }
2528
2529 /* Enable corresponding port and start training pattern 1 */
2530 void
2531 intel_dp_start_link_train(struct intel_dp *intel_dp)
2532 {
2533         struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
2534         struct drm_device *dev = encoder->dev;
2535         int i;
2536         uint8_t voltage;
2537         int voltage_tries, loop_tries;
2538         uint32_t DP = intel_dp->DP;
2539         uint8_t link_config[2];
2540
2541         if (HAS_DDI(dev))
2542                 intel_ddi_prepare_link_retrain(encoder);
2543
2544         /* Write the link configuration data */
2545         link_config[0] = intel_dp->link_bw;
2546         link_config[1] = intel_dp->lane_count;
2547         if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2548                 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
2549         intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, link_config, 2);
2550
2551         link_config[0] = 0;
2552         link_config[1] = DP_SET_ANSI_8B10B;
2553         intel_dp_aux_native_write(intel_dp, DP_DOWNSPREAD_CTRL, link_config, 2);
2554
2555         DP |= DP_PORT_EN;
2556
2557         /* clock recovery */
2558         if (!intel_dp_reset_link_train(intel_dp, &DP,
2559                                        DP_TRAINING_PATTERN_1 |
2560                                        DP_LINK_SCRAMBLING_DISABLE)) {
2561                 DRM_ERROR("failed to enable link training\n");
2562                 return;
2563         }
2564
2565         voltage = 0xff;
2566         voltage_tries = 0;
2567         loop_tries = 0;
2568         for (;;) {
2569                 uint8_t link_status[DP_LINK_STATUS_SIZE];
2570
2571                 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
2572                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2573                         DRM_ERROR("failed to get link status\n");
2574                         break;
2575                 }
2576
2577                 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2578                         DRM_DEBUG_KMS("clock recovery OK\n");
2579                         break;
2580                 }
2581
2582                 /* Check to see if we've tried the max voltage */
2583                 for (i = 0; i < intel_dp->lane_count; i++)
2584                         if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
2585                                 break;
2586                 if (i == intel_dp->lane_count) {
2587                         ++loop_tries;
2588                         if (loop_tries == 5) {
2589                                 DRM_ERROR("too many full retries, give up\n");
2590                                 break;
2591                         }
2592                         intel_dp_reset_link_train(intel_dp, &DP,
2593                                                   DP_TRAINING_PATTERN_1 |
2594                                                   DP_LINK_SCRAMBLING_DISABLE);
2595                         voltage_tries = 0;
2596                         continue;
2597                 }
2598
2599                 /* Check to see if we've tried the same voltage 5 times */
2600                 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
2601                         ++voltage_tries;
2602                         if (voltage_tries == 5) {
2603                                 DRM_ERROR("too many voltage retries, give up\n");
2604                                 break;
2605                         }
2606                 } else
2607                         voltage_tries = 0;
2608                 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
2609
2610                 /* Update training set as requested by target */
2611                 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2612                         DRM_ERROR("failed to update link training\n");
2613                         break;
2614                 }
2615         }
2616
2617         intel_dp->DP = DP;
2618 }
2619
2620 void
2621 intel_dp_complete_link_train(struct intel_dp *intel_dp)
2622 {
2623         bool channel_eq = false;
2624         int tries, cr_tries;
2625         uint32_t DP = intel_dp->DP;
2626
2627         /* channel equalization */
2628         if (!intel_dp_set_link_train(intel_dp, &DP,
2629                                      DP_TRAINING_PATTERN_2 |
2630                                      DP_LINK_SCRAMBLING_DISABLE)) {
2631                 DRM_ERROR("failed to start channel equalization\n");
2632                 return;
2633         }
2634
2635         tries = 0;
2636         cr_tries = 0;
2637         channel_eq = false;
2638         for (;;) {
2639                 uint8_t link_status[DP_LINK_STATUS_SIZE];
2640
2641                 if (cr_tries > 5) {
2642                         DRM_ERROR("failed to train DP, aborting\n");
2643                         break;
2644                 }
2645
2646                 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
2647                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2648                         DRM_ERROR("failed to get link status\n");
2649                         break;
2650                 }
2651
2652                 /* Make sure clock is still ok */
2653                 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2654                         intel_dp_start_link_train(intel_dp);
2655                         intel_dp_set_link_train(intel_dp, &DP,
2656                                                 DP_TRAINING_PATTERN_2 |
2657                                                 DP_LINK_SCRAMBLING_DISABLE);
2658                         cr_tries++;
2659                         continue;
2660                 }
2661
2662                 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2663                         channel_eq = true;
2664                         break;
2665                 }
2666
2667                 /* Try 5 times, then try clock recovery if that fails */
2668                 if (tries > 5) {
2669                         intel_dp_link_down(intel_dp);
2670                         intel_dp_start_link_train(intel_dp);
2671                         intel_dp_set_link_train(intel_dp, &DP,
2672                                                 DP_TRAINING_PATTERN_2 |
2673                                                 DP_LINK_SCRAMBLING_DISABLE);
2674                         tries = 0;
2675                         cr_tries++;
2676                         continue;
2677                 }
2678
2679                 /* Update training set as requested by target */
2680                 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2681                         DRM_ERROR("failed to update link training\n");
2682                         break;
2683                 }
2684                 ++tries;
2685         }
2686
2687         intel_dp_set_idle_link_train(intel_dp);
2688
2689         intel_dp->DP = DP;
2690
2691         if (channel_eq)
2692                 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
2693
2694 }
2695
2696 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
2697 {
2698         intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2699                                 DP_TRAINING_PATTERN_DISABLE);
2700 }
2701
2702 static void
2703 intel_dp_link_down(struct intel_dp *intel_dp)
2704 {
2705         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2706         enum port port = intel_dig_port->port;
2707         struct drm_device *dev = intel_dig_port->base.base.dev;
2708         struct drm_i915_private *dev_priv = dev->dev_private;
2709         struct intel_crtc *intel_crtc =
2710                 to_intel_crtc(intel_dig_port->base.base.crtc);
2711         uint32_t DP = intel_dp->DP;
2712
2713         /*
2714          * DDI code has a strict mode set sequence and we should try to respect
2715          * it, otherwise we might hang the machine in many different ways. So we
2716          * really should be disabling the port only on a complete crtc_disable
2717          * sequence. This function is just called under two conditions on DDI
2718          * code:
2719          * - Link train failed while doing crtc_enable, and on this case we
2720          *   really should respect the mode set sequence and wait for a
2721          *   crtc_disable.
2722          * - Someone turned the monitor off and intel_dp_check_link_status
2723          *   called us. We don't need to disable the whole port on this case, so
2724          *   when someone turns the monitor on again,
2725          *   intel_ddi_prepare_link_retrain will take care of redoing the link
2726          *   train.
2727          */
2728         if (HAS_DDI(dev))
2729                 return;
2730
2731         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
2732                 return;
2733
2734         DRM_DEBUG_KMS("\n");
2735
2736         if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2737                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
2738                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
2739         } else {
2740                 DP &= ~DP_LINK_TRAIN_MASK;
2741                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
2742         }
2743         POSTING_READ(intel_dp->output_reg);
2744
2745         /* We don't really know why we're doing this */
2746         intel_wait_for_vblank(dev, intel_crtc->pipe);
2747
2748         if (HAS_PCH_IBX(dev) &&
2749             I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
2750                 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2751
2752                 /* Hardware workaround: leaving our transcoder select
2753                  * set to transcoder B while it's off will prevent the
2754                  * corresponding HDMI output on transcoder A.
2755                  *
2756                  * Combine this with another hardware workaround:
2757                  * transcoder select bit can only be cleared while the
2758                  * port is enabled.
2759                  */
2760                 DP &= ~DP_PIPEB_SELECT;
2761                 I915_WRITE(intel_dp->output_reg, DP);
2762
2763                 /* Changes to enable or select take place the vblank
2764                  * after being written.
2765                  */
2766                 if (WARN_ON(crtc == NULL)) {
2767                         /* We should never try to disable a port without a crtc
2768                          * attached. For paranoia keep the code around for a
2769                          * bit. */
2770                         POSTING_READ(intel_dp->output_reg);
2771                         msleep(50);
2772                 } else
2773                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2774         }
2775
2776         DP &= ~DP_AUDIO_OUTPUT_ENABLE;
2777         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2778         POSTING_READ(intel_dp->output_reg);
2779         msleep(intel_dp->panel_power_down_delay);
2780 }
2781
2782 static bool
2783 intel_dp_get_dpcd(struct intel_dp *intel_dp)
2784 {
2785         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2786         struct drm_device *dev = dig_port->base.base.dev;
2787         struct drm_i915_private *dev_priv = dev->dev_private;
2788
2789         char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2790
2791         if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
2792                                            sizeof(intel_dp->dpcd)) == 0)
2793                 return false; /* aux transfer failed */
2794
2795         hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2796                            32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2797         DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2798
2799         if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2800                 return false; /* DPCD not present */
2801
2802         /* Check if the panel supports PSR */
2803         memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
2804         if (is_edp(intel_dp)) {
2805                 intel_dp_aux_native_read_retry(intel_dp, DP_PSR_SUPPORT,
2806                                                intel_dp->psr_dpcd,
2807                                                sizeof(intel_dp->psr_dpcd));
2808                 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
2809                         dev_priv->psr.sink_support = true;
2810                         DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
2811                 }
2812         }
2813
2814         if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2815               DP_DWN_STRM_PORT_PRESENT))
2816                 return true; /* native DP sink */
2817
2818         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2819                 return true; /* no per-port downstream info */
2820
2821         if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2822                                            intel_dp->downstream_ports,
2823                                            DP_MAX_DOWNSTREAM_PORTS) == 0)
2824                 return false; /* downstream port status fetch failed */
2825
2826         return true;
2827 }
2828
2829 static void
2830 intel_dp_probe_oui(struct intel_dp *intel_dp)
2831 {
2832         u8 buf[3];
2833
2834         if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2835                 return;
2836
2837         ironlake_edp_panel_vdd_on(intel_dp);
2838
2839         if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2840                 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2841                               buf[0], buf[1], buf[2]);
2842
2843         if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2844                 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2845                               buf[0], buf[1], buf[2]);
2846
2847         ironlake_edp_panel_vdd_off(intel_dp, false);
2848 }
2849
2850 static bool
2851 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2852 {
2853         int ret;
2854
2855         ret = intel_dp_aux_native_read_retry(intel_dp,
2856                                              DP_DEVICE_SERVICE_IRQ_VECTOR,
2857                                              sink_irq_vector, 1);
2858         if (!ret)
2859                 return false;
2860
2861         return true;
2862 }
2863
2864 static void
2865 intel_dp_handle_test_request(struct intel_dp *intel_dp)
2866 {
2867         /* NAK by default */
2868         intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
2869 }
2870
2871 /*
2872  * According to DP spec
2873  * 5.1.2:
2874  *  1. Read DPCD
2875  *  2. Configure link according to Receiver Capabilities
2876  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
2877  *  4. Check link status on receipt of hot-plug interrupt
2878  */
2879
2880 void
2881 intel_dp_check_link_status(struct intel_dp *intel_dp)
2882 {
2883         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
2884         u8 sink_irq_vector;
2885         u8 link_status[DP_LINK_STATUS_SIZE];
2886
2887         if (!intel_encoder->connectors_active)
2888                 return;
2889
2890         if (WARN_ON(!intel_encoder->base.crtc))
2891                 return;
2892
2893         /* Try to read receiver status if the link appears to be up */
2894         if (!intel_dp_get_link_status(intel_dp, link_status)) {
2895                 return;
2896         }
2897
2898         /* Now read the DPCD to see if it's actually running */
2899         if (!intel_dp_get_dpcd(intel_dp)) {
2900                 return;
2901         }
2902
2903         /* Try to read the source of the interrupt */
2904         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2905             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2906                 /* Clear interrupt source */
2907                 intel_dp_aux_native_write_1(intel_dp,
2908                                             DP_DEVICE_SERVICE_IRQ_VECTOR,
2909                                             sink_irq_vector);
2910
2911                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2912                         intel_dp_handle_test_request(intel_dp);
2913                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2914                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2915         }
2916
2917         if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2918                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2919                               drm_get_encoder_name(&intel_encoder->base));
2920                 intel_dp_start_link_train(intel_dp);
2921                 intel_dp_complete_link_train(intel_dp);
2922                 intel_dp_stop_link_train(intel_dp);
2923         }
2924 }
2925
2926 /* XXX this is probably wrong for multiple downstream ports */
2927 static enum drm_connector_status
2928 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2929 {
2930         uint8_t *dpcd = intel_dp->dpcd;
2931         uint8_t type;
2932
2933         if (!intel_dp_get_dpcd(intel_dp))
2934                 return connector_status_disconnected;
2935
2936         /* if there's no downstream port, we're done */
2937         if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
2938                 return connector_status_connected;
2939
2940         /* If we're HPD-aware, SINK_COUNT changes dynamically */
2941         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2942             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
2943                 uint8_t reg;
2944                 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
2945                                                     &reg, 1))
2946                         return connector_status_unknown;
2947                 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2948                                               : connector_status_disconnected;
2949         }
2950
2951         /* If no HPD, poke DDC gently */
2952         if (drm_probe_ddc(&intel_dp->adapter))
2953                 return connector_status_connected;
2954
2955         /* Well we tried, say unknown for unreliable port types */
2956         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
2957                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2958                 if (type == DP_DS_PORT_TYPE_VGA ||
2959                     type == DP_DS_PORT_TYPE_NON_EDID)
2960                         return connector_status_unknown;
2961         } else {
2962                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2963                         DP_DWN_STRM_PORT_TYPE_MASK;
2964                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
2965                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
2966                         return connector_status_unknown;
2967         }
2968
2969         /* Anything else is out of spec, warn and ignore */
2970         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
2971         return connector_status_disconnected;
2972 }
2973
2974 static enum drm_connector_status
2975 ironlake_dp_detect(struct intel_dp *intel_dp)
2976 {
2977         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2978         struct drm_i915_private *dev_priv = dev->dev_private;
2979         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2980         enum drm_connector_status status;
2981
2982         /* Can't disconnect eDP, but you can close the lid... */
2983         if (is_edp(intel_dp)) {
2984                 status = intel_panel_detect(dev);
2985                 if (status == connector_status_unknown)
2986                         status = connector_status_connected;
2987                 return status;
2988         }
2989
2990         if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
2991                 return connector_status_disconnected;
2992
2993         return intel_dp_detect_dpcd(intel_dp);
2994 }
2995
2996 static enum drm_connector_status
2997 g4x_dp_detect(struct intel_dp *intel_dp)
2998 {
2999         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3000         struct drm_i915_private *dev_priv = dev->dev_private;
3001         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3002         uint32_t bit;
3003
3004         /* Can't disconnect eDP, but you can close the lid... */
3005         if (is_edp(intel_dp)) {
3006                 enum drm_connector_status status;
3007
3008                 status = intel_panel_detect(dev);
3009                 if (status == connector_status_unknown)
3010                         status = connector_status_connected;
3011                 return status;
3012         }
3013
3014         if (IS_VALLEYVIEW(dev)) {
3015                 switch (intel_dig_port->port) {
3016                 case PORT_B:
3017                         bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
3018                         break;
3019                 case PORT_C:
3020                         bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
3021                         break;
3022                 case PORT_D:
3023                         bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
3024                         break;
3025                 default:
3026                         return connector_status_unknown;
3027                 }
3028         } else {
3029                 switch (intel_dig_port->port) {
3030                 case PORT_B:
3031                         bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
3032                         break;
3033                 case PORT_C:
3034                         bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
3035                         break;
3036                 case PORT_D:
3037                         bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
3038                         break;
3039                 default:
3040                         return connector_status_unknown;
3041                 }
3042         }
3043
3044         if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
3045                 return connector_status_disconnected;
3046
3047         return intel_dp_detect_dpcd(intel_dp);
3048 }
3049
3050 static struct edid *
3051 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
3052 {
3053         struct intel_connector *intel_connector = to_intel_connector(connector);
3054
3055         /* use cached edid if we have one */
3056         if (intel_connector->edid) {
3057                 /* invalid edid */
3058                 if (IS_ERR(intel_connector->edid))
3059                         return NULL;
3060
3061                 return drm_edid_duplicate(intel_connector->edid);
3062         }
3063
3064         return drm_get_edid(connector, adapter);
3065 }
3066
3067 static int
3068 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
3069 {
3070         struct intel_connector *intel_connector = to_intel_connector(connector);
3071
3072         /* use cached edid if we have one */
3073         if (intel_connector->edid) {
3074                 /* invalid edid */
3075                 if (IS_ERR(intel_connector->edid))
3076                         return 0;
3077
3078                 return intel_connector_update_modes(connector,
3079                                                     intel_connector->edid);
3080         }
3081
3082         return intel_ddc_get_modes(connector, adapter);
3083 }
3084
3085 static enum drm_connector_status
3086 intel_dp_detect(struct drm_connector *connector, bool force)
3087 {
3088         struct intel_dp *intel_dp = intel_attached_dp(connector);
3089         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3090         struct intel_encoder *intel_encoder = &intel_dig_port->base;
3091         struct drm_device *dev = connector->dev;
3092         struct drm_i915_private *dev_priv = dev->dev_private;
3093         enum drm_connector_status status;
3094         struct edid *edid = NULL;
3095
3096         intel_runtime_pm_get(dev_priv);
3097
3098         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3099                       connector->base.id, drm_get_connector_name(connector));
3100
3101         intel_dp->has_audio = false;
3102
3103         if (HAS_PCH_SPLIT(dev))
3104                 status = ironlake_dp_detect(intel_dp);
3105         else
3106                 status = g4x_dp_detect(intel_dp);
3107
3108         if (status != connector_status_connected)
3109                 goto out;
3110
3111         intel_dp_probe_oui(intel_dp);
3112
3113         if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
3114                 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
3115         } else {
3116                 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
3117                 if (edid) {
3118                         intel_dp->has_audio = drm_detect_monitor_audio(edid);
3119                         kfree(edid);
3120                 }
3121         }
3122
3123         if (intel_encoder->type != INTEL_OUTPUT_EDP)
3124                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3125         status = connector_status_connected;
3126
3127 out:
3128         intel_runtime_pm_put(dev_priv);
3129         return status;
3130 }
3131
3132 static int intel_dp_get_modes(struct drm_connector *connector)
3133 {
3134         struct intel_dp *intel_dp = intel_attached_dp(connector);
3135         struct intel_connector *intel_connector = to_intel_connector(connector);
3136         struct drm_device *dev = connector->dev;
3137         int ret;
3138
3139         /* We should parse the EDID data and find out if it has an audio sink
3140          */
3141
3142         ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
3143         if (ret)
3144                 return ret;
3145
3146         /* if eDP has no EDID, fall back to fixed mode */
3147         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
3148                 struct drm_display_mode *mode;
3149                 mode = drm_mode_duplicate(dev,
3150                                           intel_connector->panel.fixed_mode);
3151                 if (mode) {
3152                         drm_mode_probed_add(connector, mode);
3153                         return 1;
3154                 }
3155         }
3156         return 0;
3157 }
3158
3159 static bool
3160 intel_dp_detect_audio(struct drm_connector *connector)
3161 {
3162         struct intel_dp *intel_dp = intel_attached_dp(connector);
3163         struct edid *edid;
3164         bool has_audio = false;
3165
3166         edid = intel_dp_get_edid(connector, &intel_dp->adapter);
3167         if (edid) {
3168                 has_audio = drm_detect_monitor_audio(edid);
3169                 kfree(edid);
3170         }
3171
3172         return has_audio;
3173 }
3174
3175 static int
3176 intel_dp_set_property(struct drm_connector *connector,
3177                       struct drm_property *property,
3178                       uint64_t val)
3179 {
3180         struct drm_i915_private *dev_priv = connector->dev->dev_private;
3181         struct intel_connector *intel_connector = to_intel_connector(connector);
3182         struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
3183         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
3184         int ret;
3185
3186         ret = drm_object_property_set_value(&connector->base, property, val);
3187         if (ret)
3188                 return ret;
3189
3190         if (property == dev_priv->force_audio_property) {
3191                 int i = val;
3192                 bool has_audio;
3193
3194                 if (i == intel_dp->force_audio)
3195                         return 0;
3196
3197                 intel_dp->force_audio = i;
3198
3199                 if (i == HDMI_AUDIO_AUTO)
3200                         has_audio = intel_dp_detect_audio(connector);
3201                 else
3202                         has_audio = (i == HDMI_AUDIO_ON);
3203
3204                 if (has_audio == intel_dp->has_audio)
3205                         return 0;
3206
3207                 intel_dp->has_audio = has_audio;
3208                 goto done;
3209         }
3210
3211         if (property == dev_priv->broadcast_rgb_property) {
3212                 bool old_auto = intel_dp->color_range_auto;
3213                 uint32_t old_range = intel_dp->color_range;
3214
3215                 switch (val) {
3216                 case INTEL_BROADCAST_RGB_AUTO:
3217                         intel_dp->color_range_auto = true;
3218                         break;
3219                 case INTEL_BROADCAST_RGB_FULL:
3220                         intel_dp->color_range_auto = false;
3221                         intel_dp->color_range = 0;
3222                         break;
3223                 case INTEL_BROADCAST_RGB_LIMITED:
3224                         intel_dp->color_range_auto = false;
3225                         intel_dp->color_range = DP_COLOR_RANGE_16_235;
3226                         break;
3227                 default:
3228                         return -EINVAL;
3229                 }
3230
3231                 if (old_auto == intel_dp->color_range_auto &&
3232                     old_range == intel_dp->color_range)
3233                         return 0;
3234
3235                 goto done;
3236         }
3237
3238         if (is_edp(intel_dp) &&
3239             property == connector->dev->mode_config.scaling_mode_property) {
3240                 if (val == DRM_MODE_SCALE_NONE) {
3241                         DRM_DEBUG_KMS("no scaling not supported\n");
3242                         return -EINVAL;
3243                 }
3244
3245                 if (intel_connector->panel.fitting_mode == val) {
3246                         /* the eDP scaling property is not changed */
3247                         return 0;
3248                 }
3249                 intel_connector->panel.fitting_mode = val;
3250
3251                 goto done;
3252         }
3253
3254         return -EINVAL;
3255
3256 done:
3257         if (intel_encoder->base.crtc)
3258                 intel_crtc_restore_mode(intel_encoder->base.crtc);
3259
3260         return 0;
3261 }
3262
3263 static void
3264 intel_dp_connector_destroy(struct drm_connector *connector)
3265 {
3266         struct intel_connector *intel_connector = to_intel_connector(connector);
3267
3268         if (!IS_ERR_OR_NULL(intel_connector->edid))
3269                 kfree(intel_connector->edid);
3270
3271         /* Can't call is_edp() since the encoder may have been destroyed
3272          * already. */
3273         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3274                 intel_panel_fini(&intel_connector->panel);
3275
3276         drm_connector_cleanup(connector);
3277         kfree(connector);
3278 }
3279
3280 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
3281 {
3282         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3283         struct intel_dp *intel_dp = &intel_dig_port->dp;
3284         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3285
3286         i2c_del_adapter(&intel_dp->adapter);
3287         drm_encoder_cleanup(encoder);
3288         if (is_edp(intel_dp)) {
3289                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3290                 mutex_lock(&dev->mode_config.mutex);
3291                 ironlake_panel_vdd_off_sync(intel_dp);
3292                 mutex_unlock(&dev->mode_config.mutex);
3293         }
3294         kfree(intel_dig_port);
3295 }
3296
3297 static const struct drm_connector_funcs intel_dp_connector_funcs = {
3298         .dpms = intel_connector_dpms,
3299         .detect = intel_dp_detect,
3300         .fill_modes = drm_helper_probe_single_connector_modes,
3301         .set_property = intel_dp_set_property,
3302         .destroy = intel_dp_connector_destroy,
3303 };
3304
3305 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
3306         .get_modes = intel_dp_get_modes,
3307         .mode_valid = intel_dp_mode_valid,
3308         .best_encoder = intel_best_encoder,
3309 };
3310
3311 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
3312         .destroy = intel_dp_encoder_destroy,
3313 };
3314
3315 static void
3316 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
3317 {
3318         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
3319
3320         intel_dp_check_link_status(intel_dp);
3321 }
3322
3323 /* Return which DP Port should be selected for Transcoder DP control */
3324 int
3325 intel_trans_dp_port_sel(struct drm_crtc *crtc)
3326 {
3327         struct drm_device *dev = crtc->dev;
3328         struct intel_encoder *intel_encoder;
3329         struct intel_dp *intel_dp;
3330
3331         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3332                 intel_dp = enc_to_intel_dp(&intel_encoder->base);
3333
3334                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
3335                     intel_encoder->type == INTEL_OUTPUT_EDP)
3336                         return intel_dp->output_reg;
3337         }
3338
3339         return -1;
3340 }
3341
3342 /* check the VBT to see whether the eDP is on DP-D port */
3343 bool intel_dp_is_edp(struct drm_device *dev, enum port port)
3344 {
3345         struct drm_i915_private *dev_priv = dev->dev_private;
3346         union child_device_config *p_child;
3347         int i;
3348         static const short port_mapping[] = {
3349                 [PORT_B] = PORT_IDPB,
3350                 [PORT_C] = PORT_IDPC,
3351                 [PORT_D] = PORT_IDPD,
3352         };
3353
3354         if (port == PORT_A)
3355                 return true;
3356
3357         if (!dev_priv->vbt.child_dev_num)
3358                 return false;
3359
3360         for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
3361                 p_child = dev_priv->vbt.child_dev + i;
3362
3363                 if (p_child->common.dvo_port == port_mapping[port] &&
3364                     (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
3365                     (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
3366                         return true;
3367         }
3368         return false;
3369 }
3370
3371 static void
3372 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
3373 {
3374         struct intel_connector *intel_connector = to_intel_connector(connector);
3375
3376         intel_attach_force_audio_property(connector);
3377         intel_attach_broadcast_rgb_property(connector);
3378         intel_dp->color_range_auto = true;
3379
3380         if (is_edp(intel_dp)) {
3381                 drm_mode_create_scaling_mode_property(connector->dev);
3382                 drm_object_attach_property(
3383                         &connector->base,
3384                         connector->dev->mode_config.scaling_mode_property,
3385                         DRM_MODE_SCALE_ASPECT);
3386                 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
3387         }
3388 }
3389
3390 static void
3391 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
3392                                     struct intel_dp *intel_dp,
3393                                     struct edp_power_seq *out)
3394 {
3395         struct drm_i915_private *dev_priv = dev->dev_private;
3396         struct edp_power_seq cur, vbt, spec, final;
3397         u32 pp_on, pp_off, pp_div, pp;
3398         int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
3399
3400         if (HAS_PCH_SPLIT(dev)) {
3401                 pp_ctrl_reg = PCH_PP_CONTROL;
3402                 pp_on_reg = PCH_PP_ON_DELAYS;
3403                 pp_off_reg = PCH_PP_OFF_DELAYS;
3404                 pp_div_reg = PCH_PP_DIVISOR;
3405         } else {
3406                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3407
3408                 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
3409                 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3410                 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3411                 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
3412         }
3413
3414         /* Workaround: Need to write PP_CONTROL with the unlock key as
3415          * the very first thing. */
3416         pp = ironlake_get_pp_control(intel_dp);
3417         I915_WRITE(pp_ctrl_reg, pp);
3418
3419         pp_on = I915_READ(pp_on_reg);
3420         pp_off = I915_READ(pp_off_reg);
3421         pp_div = I915_READ(pp_div_reg);
3422
3423         /* Pull timing values out of registers */
3424         cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
3425                 PANEL_POWER_UP_DELAY_SHIFT;
3426
3427         cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
3428                 PANEL_LIGHT_ON_DELAY_SHIFT;
3429
3430         cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
3431                 PANEL_LIGHT_OFF_DELAY_SHIFT;
3432
3433         cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
3434                 PANEL_POWER_DOWN_DELAY_SHIFT;
3435
3436         cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
3437                        PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
3438
3439         DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3440                       cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
3441
3442         vbt = dev_priv->vbt.edp_pps;
3443
3444         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
3445          * our hw here, which are all in 100usec. */
3446         spec.t1_t3 = 210 * 10;
3447         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
3448         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
3449         spec.t10 = 500 * 10;
3450         /* This one is special and actually in units of 100ms, but zero
3451          * based in the hw (so we need to add 100 ms). But the sw vbt
3452          * table multiplies it with 1000 to make it in units of 100usec,
3453          * too. */
3454         spec.t11_t12 = (510 + 100) * 10;
3455
3456         DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3457                       vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
3458
3459         /* Use the max of the register settings and vbt. If both are
3460          * unset, fall back to the spec limits. */
3461 #define assign_final(field)     final.field = (max(cur.field, vbt.field) == 0 ? \
3462                                        spec.field : \
3463                                        max(cur.field, vbt.field))
3464         assign_final(t1_t3);
3465         assign_final(t8);
3466         assign_final(t9);
3467         assign_final(t10);
3468         assign_final(t11_t12);
3469 #undef assign_final
3470
3471 #define get_delay(field)        (DIV_ROUND_UP(final.field, 10))
3472         intel_dp->panel_power_up_delay = get_delay(t1_t3);
3473         intel_dp->backlight_on_delay = get_delay(t8);
3474         intel_dp->backlight_off_delay = get_delay(t9);
3475         intel_dp->panel_power_down_delay = get_delay(t10);
3476         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
3477 #undef get_delay
3478
3479         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
3480                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
3481                       intel_dp->panel_power_cycle_delay);
3482
3483         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
3484                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
3485
3486         if (out)
3487                 *out = final;
3488 }
3489
3490 static void
3491 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
3492                                               struct intel_dp *intel_dp,
3493                                               struct edp_power_seq *seq)
3494 {
3495         struct drm_i915_private *dev_priv = dev->dev_private;
3496         u32 pp_on, pp_off, pp_div, port_sel = 0;
3497         int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
3498         int pp_on_reg, pp_off_reg, pp_div_reg;
3499
3500         if (HAS_PCH_SPLIT(dev)) {
3501                 pp_on_reg = PCH_PP_ON_DELAYS;
3502                 pp_off_reg = PCH_PP_OFF_DELAYS;
3503                 pp_div_reg = PCH_PP_DIVISOR;
3504         } else {
3505                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3506
3507                 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3508                 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3509                 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
3510         }
3511
3512         /* And finally store the new values in the power sequencer. */
3513         pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
3514                 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
3515         pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
3516                  (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
3517         /* Compute the divisor for the pp clock, simply match the Bspec
3518          * formula. */
3519         pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
3520         pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
3521                         << PANEL_POWER_CYCLE_DELAY_SHIFT);
3522
3523         /* Haswell doesn't have any port selection bits for the panel
3524          * power sequencer any more. */
3525         if (IS_VALLEYVIEW(dev)) {
3526                 if (dp_to_dig_port(intel_dp)->port == PORT_B)
3527                         port_sel = PANEL_PORT_SELECT_DPB_VLV;
3528                 else
3529                         port_sel = PANEL_PORT_SELECT_DPC_VLV;
3530         } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
3531                 if (dp_to_dig_port(intel_dp)->port == PORT_A)
3532                         port_sel = PANEL_PORT_SELECT_DPA;
3533                 else
3534                         port_sel = PANEL_PORT_SELECT_DPD;
3535         }
3536
3537         pp_on |= port_sel;
3538
3539         I915_WRITE(pp_on_reg, pp_on);
3540         I915_WRITE(pp_off_reg, pp_off);
3541         I915_WRITE(pp_div_reg, pp_div);
3542
3543         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
3544                       I915_READ(pp_on_reg),
3545                       I915_READ(pp_off_reg),
3546                       I915_READ(pp_div_reg));
3547 }
3548
3549 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
3550                                      struct intel_connector *intel_connector)
3551 {
3552         struct drm_connector *connector = &intel_connector->base;
3553         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3554         struct drm_device *dev = intel_dig_port->base.base.dev;
3555         struct drm_i915_private *dev_priv = dev->dev_private;
3556         struct drm_display_mode *fixed_mode = NULL;
3557         struct edp_power_seq power_seq = { 0 };
3558         bool has_dpcd;
3559         struct drm_display_mode *scan;
3560         struct edid *edid;
3561
3562         if (!is_edp(intel_dp))
3563                 return true;
3564
3565         intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
3566
3567         /* Cache DPCD and EDID for edp. */
3568         ironlake_edp_panel_vdd_on(intel_dp);
3569         has_dpcd = intel_dp_get_dpcd(intel_dp);
3570         ironlake_edp_panel_vdd_off(intel_dp, false);
3571
3572         if (has_dpcd) {
3573                 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3574                         dev_priv->no_aux_handshake =
3575                                 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3576                                 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3577         } else {
3578                 /* if this fails, presume the device is a ghost */
3579                 DRM_INFO("failed to retrieve link info, disabling eDP\n");
3580                 return false;
3581         }
3582
3583         /* We now know it's not a ghost, init power sequence regs. */
3584         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
3585                                                       &power_seq);
3586
3587         edid = drm_get_edid(connector, &intel_dp->adapter);
3588         if (edid) {
3589                 if (drm_add_edid_modes(connector, edid)) {
3590                         drm_mode_connector_update_edid_property(connector,
3591                                                                 edid);
3592                         drm_edid_to_eld(connector, edid);
3593                 } else {
3594                         kfree(edid);
3595                         edid = ERR_PTR(-EINVAL);
3596                 }
3597         } else {
3598                 edid = ERR_PTR(-ENOENT);
3599         }
3600         intel_connector->edid = edid;
3601
3602         /* prefer fixed mode from EDID if available */
3603         list_for_each_entry(scan, &connector->probed_modes, head) {
3604                 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
3605                         fixed_mode = drm_mode_duplicate(dev, scan);
3606                         break;
3607                 }
3608         }
3609
3610         /* fallback to VBT if available for eDP */
3611         if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
3612                 fixed_mode = drm_mode_duplicate(dev,
3613                                         dev_priv->vbt.lfp_lvds_vbt_mode);
3614                 if (fixed_mode)
3615                         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
3616         }
3617
3618         intel_panel_init(&intel_connector->panel, fixed_mode);
3619         intel_panel_setup_backlight(connector);
3620
3621         return true;
3622 }
3623
3624 bool
3625 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
3626                         struct intel_connector *intel_connector)
3627 {
3628         struct drm_connector *connector = &intel_connector->base;
3629         struct intel_dp *intel_dp = &intel_dig_port->dp;
3630         struct intel_encoder *intel_encoder = &intel_dig_port->base;
3631         struct drm_device *dev = intel_encoder->base.dev;
3632         struct drm_i915_private *dev_priv = dev->dev_private;
3633         enum port port = intel_dig_port->port;
3634         const char *name = NULL;
3635         int type, error;
3636
3637         /* Preserve the current hw state. */
3638         intel_dp->DP = I915_READ(intel_dp->output_reg);
3639         intel_dp->attached_connector = intel_connector;
3640
3641         if (intel_dp_is_edp(dev, port))
3642                 type = DRM_MODE_CONNECTOR_eDP;
3643         else
3644                 type = DRM_MODE_CONNECTOR_DisplayPort;
3645
3646         /*
3647          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
3648          * for DP the encoder type can be set by the caller to
3649          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
3650          */
3651         if (type == DRM_MODE_CONNECTOR_eDP)
3652                 intel_encoder->type = INTEL_OUTPUT_EDP;
3653
3654         DRM_DEBUG_KMS("Adding %s connector on port %c\n",
3655                         type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
3656                         port_name(port));
3657
3658         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
3659         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
3660
3661         connector->interlace_allowed = true;
3662         connector->doublescan_allowed = 0;
3663
3664         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
3665                           ironlake_panel_vdd_work);
3666
3667         intel_connector_attach_encoder(intel_connector, intel_encoder);
3668         drm_sysfs_connector_add(connector);
3669
3670         if (HAS_DDI(dev))
3671                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3672         else
3673                 intel_connector->get_hw_state = intel_connector_get_hw_state;
3674
3675         intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
3676         if (HAS_DDI(dev)) {
3677                 switch (intel_dig_port->port) {
3678                 case PORT_A:
3679                         intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
3680                         break;
3681                 case PORT_B:
3682                         intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
3683                         break;
3684                 case PORT_C:
3685                         intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
3686                         break;
3687                 case PORT_D:
3688                         intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
3689                         break;
3690                 default:
3691                         BUG();
3692                 }
3693         }
3694
3695         /* Set up the DDC bus. */
3696         switch (port) {
3697         case PORT_A:
3698                 intel_encoder->hpd_pin = HPD_PORT_A;
3699                 name = "DPDDC-A";
3700                 break;
3701         case PORT_B:
3702                 intel_encoder->hpd_pin = HPD_PORT_B;
3703                 name = "DPDDC-B";
3704                 break;
3705         case PORT_C:
3706                 intel_encoder->hpd_pin = HPD_PORT_C;
3707                 name = "DPDDC-C";
3708                 break;
3709         case PORT_D:
3710                 intel_encoder->hpd_pin = HPD_PORT_D;
3711                 name = "DPDDC-D";
3712                 break;
3713         default:
3714                 BUG();
3715         }
3716
3717         error = intel_dp_i2c_init(intel_dp, intel_connector, name);
3718         WARN(error, "intel_dp_i2c_init failed with error %d for port %c\n",
3719              error, port_name(port));
3720
3721         intel_dp->psr_setup_done = false;
3722
3723         if (!intel_edp_init_connector(intel_dp, intel_connector)) {
3724                 i2c_del_adapter(&intel_dp->adapter);
3725                 if (is_edp(intel_dp)) {
3726                         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3727                         mutex_lock(&dev->mode_config.mutex);
3728                         ironlake_panel_vdd_off_sync(intel_dp);
3729                         mutex_unlock(&dev->mode_config.mutex);
3730                 }
3731                 drm_sysfs_connector_remove(connector);
3732                 drm_connector_cleanup(connector);
3733                 return false;
3734         }
3735
3736         intel_dp_add_properties(intel_dp, connector);
3737
3738         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3739          * 0xd.  Failure to do so will result in spurious interrupts being
3740          * generated on the port when a cable is not attached.
3741          */
3742         if (IS_G4X(dev) && !IS_GM45(dev)) {
3743                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3744                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3745         }
3746
3747         return true;
3748 }
3749
3750 void
3751 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
3752 {
3753         struct intel_digital_port *intel_dig_port;
3754         struct intel_encoder *intel_encoder;
3755         struct drm_encoder *encoder;
3756         struct intel_connector *intel_connector;
3757
3758         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
3759         if (!intel_dig_port)
3760                 return;
3761
3762         intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
3763         if (!intel_connector) {
3764                 kfree(intel_dig_port);
3765                 return;
3766         }
3767
3768         intel_encoder = &intel_dig_port->base;
3769         encoder = &intel_encoder->base;
3770
3771         drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
3772                          DRM_MODE_ENCODER_TMDS);
3773
3774         intel_encoder->compute_config = intel_dp_compute_config;
3775         intel_encoder->mode_set = intel_dp_mode_set;
3776         intel_encoder->disable = intel_disable_dp;
3777         intel_encoder->post_disable = intel_post_disable_dp;
3778         intel_encoder->get_hw_state = intel_dp_get_hw_state;
3779         intel_encoder->get_config = intel_dp_get_config;
3780         if (IS_VALLEYVIEW(dev)) {
3781                 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
3782                 intel_encoder->pre_enable = vlv_pre_enable_dp;
3783                 intel_encoder->enable = vlv_enable_dp;
3784         } else {
3785                 intel_encoder->pre_enable = g4x_pre_enable_dp;
3786                 intel_encoder->enable = g4x_enable_dp;
3787         }
3788
3789         intel_dig_port->port = port;
3790         intel_dig_port->dp.output_reg = output_reg;
3791
3792         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3793         intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3794         intel_encoder->cloneable = false;
3795         intel_encoder->hot_plug = intel_dp_hot_plug;
3796
3797         if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
3798                 drm_encoder_cleanup(encoder);
3799                 kfree(intel_dig_port);
3800                 kfree(intel_connector);
3801         }
3802 }