Pileus Git - ~andy/linux/blob - drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include "drmP.h"
  32 #include "drm.h"
  33 #include "drm_crtc.h"
  34 #include "drm_crtc_helper.h"
  35 #include "intel_drv.h"
  36 #include "i915_drm.h"
  37 #include "i915_drv.h"
  38 #include "drm_dp_helper.h"
  39
  40 #define DP_RECEIVER_CAP_SIZE    0xf
  41 #define DP_LINK_STATUS_SIZE     6
  42 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  43
  44 #define DP_LINK_CONFIGURATION_SIZE      9
  45
  46 struct intel_dp {
  47         struct intel_encoder base;
  48         uint32_t output_reg;
  49         uint32_t DP;
  50         uint8_t  link_configuration[DP_LINK_CONFIGURATION_SIZE];
  51         bool has_audio;
  52         int force_audio;
  53         uint32_t color_range;
  54         int dpms_mode;
  55         uint8_t link_bw;
  56         uint8_t lane_count;
  57         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
  58         struct i2c_adapter adapter;
  59         struct i2c_algo_dp_aux_data algo;
  60         bool is_pch_edp;
  61         uint8_t train_set[4];
  62         uint8_t link_status[DP_LINK_STATUS_SIZE];
  63         int panel_power_up_delay;
  64         int panel_power_down_delay;
  65         int panel_power_cycle_delay;
  66         int backlight_on_delay;
  67         int backlight_off_delay;
  68         struct drm_display_mode *panel_fixed_mode;  /* for eDP */
  69         struct delayed_work panel_vdd_work;
  70         bool want_panel_vdd;
  71         unsigned long panel_off_jiffies;
  72 };
  73
  74 /**
  75  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  76  * @intel_dp: DP struct
  77  *
  78  * If a CPU or PCH DP output is attached to an eDP panel, this function
  79  * will return true, and false otherwise.
  80  */
  81 static bool is_edp(struct intel_dp *intel_dp)
  82 {
  83         return intel_dp->base.type == INTEL_OUTPUT_EDP;
  84 }
  85
  86 /**
  87  * is_pch_edp - is the port on the PCH and attached to an eDP panel?
  88  * @intel_dp: DP struct
  89  *
  90  * Returns true if the given DP struct corresponds to a PCH DP port attached
  91  * to an eDP panel, false otherwise.  Helpful for determining whether we
  92  * may need FDI resources for a given DP output or not.
  93  */
  94 static bool is_pch_edp(struct intel_dp *intel_dp)
  95 {
  96         return intel_dp->is_pch_edp;
  97 }
  98
  99 /**
 100  * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
 101  * @intel_dp: DP struct
 102  *
 103  * Returns true if the given DP struct corresponds to a CPU eDP port.
 104  */
 105 static bool is_cpu_edp(struct intel_dp *intel_dp)
 106 {
 107         return is_edp(intel_dp) && !is_pch_edp(intel_dp);
 108 }
 109
 110 static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
 111 {
 112         return container_of(encoder, struct intel_dp, base.base);
 113 }
 114
 115 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
 116 {
 117         return container_of(intel_attached_encoder(connector),
 118                             struct intel_dp, base);
 119 }
 120
 121 /**
 122  * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
 123  * @encoder: DRM encoder
 124  *
 125  * Return true if @encoder corresponds to a PCH attached eDP panel.  Needed
 126  * by intel_display.c.
 127  */
 128 bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
 129 {
 130         struct intel_dp *intel_dp;
 131
 132         if (!encoder)
 133                 return false;
 134
 135         intel_dp = enc_to_intel_dp(encoder);
 136
 137         return is_pch_edp(intel_dp);
 138 }
 139
 140 static void intel_dp_start_link_train(struct intel_dp *intel_dp);
 141 static void intel_dp_complete_link_train(struct intel_dp *intel_dp);
 142 static void intel_dp_link_down(struct intel_dp *intel_dp);
 143
 144 void
 145 intel_edp_link_config(struct intel_encoder *intel_encoder,
 146                        int *lane_num, int *link_bw)
 147 {
 148         struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
 149
 150         *lane_num = intel_dp->lane_count;
 151         if (intel_dp->link_bw == DP_LINK_BW_1_62)
 152                 *link_bw = 162000;
 153         else if (intel_dp->link_bw == DP_LINK_BW_2_7)
 154                 *link_bw = 270000;
 155 }
 156
 157 static int
 158 intel_dp_max_lane_count(struct intel_dp *intel_dp)
 159 {
 160         int max_lane_count = 4;
 161
 162         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
 163                 max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
 164                 switch (max_lane_count) {
 165                 case 1: case 2: case 4:
 166                         break;
 167                 default:
 168                         max_lane_count = 4;
 169                 }
 170         }
 171         return max_lane_count;
 172 }
 173
 174 static int
 175 intel_dp_max_link_bw(struct intel_dp *intel_dp)
 176 {
 177         int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
 178
 179         switch (max_link_bw) {
 180         case DP_LINK_BW_1_62:
 181         case DP_LINK_BW_2_7:
 182                 break;
 183         default:
 184                 max_link_bw = DP_LINK_BW_1_62;
 185                 break;
 186         }
 187         return max_link_bw;
 188 }
 189
 190 static int
 191 intel_dp_link_clock(uint8_t link_bw)
 192 {
 193         if (link_bw == DP_LINK_BW_2_7)
 194                 return 270000;
 195         else
 196                 return 162000;
 197 }
 198
 199 /*
 200  * The units on the numbers in the next two are... bizarre.  Examples will
 201  * make it clearer; this one parallels an example in the eDP spec.
 202  *
 203  * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
 204  *
 205  *     270000 * 1 * 8 / 10 == 216000
 206  *
 207  * The actual data capacity of that configuration is 2.16Gbit/s, so the
 208  * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 209  * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 210  * 119000.  At 18bpp that's 2142000 kilobits per second.
 211  *
 212  * Thus the strange-looking division by 10 in intel_dp_link_required, to
 213  * get the result in decakilobits instead of kilobits.
 214  */
 215
 216 static int
 217 intel_dp_link_required(struct intel_dp *intel_dp, int pixel_clock)
 218 {
 219         struct drm_crtc *crtc = intel_dp->base.base.crtc;
 220         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 221         int bpp = 24;
 222
 223         if (intel_crtc)
 224                 bpp = intel_crtc->bpp;
 225
 226         return (pixel_clock * bpp + 9) / 10;
 227 }
 228
 229 static int
 230 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 231 {
 232         return (max_link_clock * max_lanes * 8) / 10;
 233 }
 234
 235 static int
 236 intel_dp_mode_valid(struct drm_connector *connector,
 237                     struct drm_display_mode *mode)
 238 {
 239         struct intel_dp *intel_dp = intel_attached_dp(connector);
 240         int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
 241         int max_lanes = intel_dp_max_lane_count(intel_dp);
 242
 243         if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
 244                 if (mode->hdisplay > intel_dp->panel_fixed_mode->hdisplay)
 245                         return MODE_PANEL;
 246
 247                 if (mode->vdisplay > intel_dp->panel_fixed_mode->vdisplay)
 248                         return MODE_PANEL;
 249         }
 250
 251         if (intel_dp_link_required(intel_dp, mode->clock)
 252             > intel_dp_max_data_rate(max_link_clock, max_lanes))
 253                 return MODE_CLOCK_HIGH;
 254
 255         if (mode->clock < 10000)
 256                 return MODE_CLOCK_LOW;
 257
 258         return MODE_OK;
 259 }
 260
 261 static uint32_t
 262 pack_aux(uint8_t *src, int src_bytes)
 263 {
 264         int     i;
 265         uint32_t v = 0;
 266
 267         if (src_bytes > 4)
 268                 src_bytes = 4;
 269         for (i = 0; i < src_bytes; i++)
 270                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 271         return v;
 272 }
 273
 274 static void
 275 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 276 {
 277         int i;
 278         if (dst_bytes > 4)
 279                 dst_bytes = 4;
 280         for (i = 0; i < dst_bytes; i++)
 281                 dst[i] = src >> ((3-i) * 8);
 282 }
 283
 284 /* hrawclock is 1/4 the FSB frequency */
 285 static int
 286 intel_hrawclk(struct drm_device *dev)
 287 {
 288         struct drm_i915_private *dev_priv = dev->dev_private;
 289         uint32_t clkcfg;
 290
 291         clkcfg = I915_READ(CLKCFG);
 292         switch (clkcfg & CLKCFG_FSB_MASK) {
 293         case CLKCFG_FSB_400:
 294                 return 100;
 295         case CLKCFG_FSB_533:
 296                 return 133;
 297         case CLKCFG_FSB_667:
 298                 return 166;
 299         case CLKCFG_FSB_800:
 300                 return 200;
 301         case CLKCFG_FSB_1067:
 302                 return 266;
 303         case CLKCFG_FSB_1333:
 304                 return 333;
 305         /* these two are just a guess; one of them might be right */
 306         case CLKCFG_FSB_1600:
 307         case CLKCFG_FSB_1600_ALT:
 308                 return 400;
 309         default:
 310                 return 133;
 311         }
 312 }
 313
 314 static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
 315 {
 316         struct drm_device *dev = intel_dp->base.base.dev;
 317         struct drm_i915_private *dev_priv = dev->dev_private;
 318
 319         return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
 320 }
 321
 322 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
 323 {
 324         struct drm_device *dev = intel_dp->base.base.dev;
 325         struct drm_i915_private *dev_priv = dev->dev_private;
 326
 327         return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
 328 }
 329
 330 static void
 331 intel_dp_check_edp(struct intel_dp *intel_dp)
 332 {
 333         struct drm_device *dev = intel_dp->base.base.dev;
 334         struct drm_i915_private *dev_priv = dev->dev_private;
 335
 336         if (!is_edp(intel_dp))
 337                 return;
 338         if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
 339                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 340                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 341                               I915_READ(PCH_PP_STATUS),
 342                               I915_READ(PCH_PP_CONTROL));
 343         }
 344 }
 345
 346 static int
 347 intel_dp_aux_ch(struct intel_dp *intel_dp,
 348                 uint8_t *send, int send_bytes,
 349                 uint8_t *recv, int recv_size)
 350 {
 351         uint32_t output_reg = intel_dp->output_reg;
 352         struct drm_device *dev = intel_dp->base.base.dev;
 353         struct drm_i915_private *dev_priv = dev->dev_private;
 354         uint32_t ch_ctl = output_reg + 0x10;
 355         uint32_t ch_data = ch_ctl + 4;
 356         int i;
 357         int recv_bytes;
 358         uint32_t status;
 359         uint32_t aux_clock_divider;
 360         int try, precharge;
 361
 362         intel_dp_check_edp(intel_dp);
 363         /* The clock divider is based off the hrawclk,
 364          * and would like to run at 2MHz. So, take the
 365          * hrawclk value and divide by 2 and use that
 366          *
 367          * Note that PCH attached eDP panels should use a 125MHz input
 368          * clock divider.
 369          */
 370         if (is_cpu_edp(intel_dp)) {
 371                 if (IS_GEN6(dev))
 372                         aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */
 373                 else
 374                         aux_clock_divider = 225; /* eDP input clock at 450Mhz */
 375         } else if (HAS_PCH_SPLIT(dev))
 376                 aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */
 377         else
 378                 aux_clock_divider = intel_hrawclk(dev) / 2;
 379
 380         if (IS_GEN6(dev))
 381                 precharge = 3;
 382         else
 383                 precharge = 5;
 384
 385         /* Try to wait for any previous AUX channel activity */
 386         for (try = 0; try < 3; try++) {
 387                 status = I915_READ(ch_ctl);
 388                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 389                         break;
 390                 msleep(1);
 391         }
 392
 393         if (try == 3) {
 394                 WARN(1, "dp_aux_ch not started status 0x%08x\n",
 395                      I915_READ(ch_ctl));
 396                 return -EBUSY;
 397         }
 398
 399         /* Must try at least 3 times according to DP spec */
 400         for (try = 0; try < 5; try++) {
 401                 /* Load the send data into the aux channel data registers */
 402                 for (i = 0; i < send_bytes; i += 4)
 403                         I915_WRITE(ch_data + i,
 404                                    pack_aux(send + i, send_bytes - i));
 405
 406                 /* Send the command and wait for it to complete */
 407                 I915_WRITE(ch_ctl,
 408                            DP_AUX_CH_CTL_SEND_BUSY |
 409                            DP_AUX_CH_CTL_TIME_OUT_400us |
 410                            (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 411                            (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 412                            (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
 413                            DP_AUX_CH_CTL_DONE |
 414                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 415                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 416                 for (;;) {
 417                         status = I915_READ(ch_ctl);
 418                         if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 419                                 break;
 420                         udelay(100);
 421                 }
 422
 423                 /* Clear done status and any errors */
 424                 I915_WRITE(ch_ctl,
 425                            status |
 426                            DP_AUX_CH_CTL_DONE |
 427                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 428                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 429                 if (status & DP_AUX_CH_CTL_DONE)
 430                         break;
 431         }
 432
 433         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 434                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 435                 return -EBUSY;
 436         }
 437
 438         /* Check for timeout or receive error.
 439          * Timeouts occur when the sink is not connected
 440          */
 441         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 442                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 443                 return -EIO;
 444         }
 445
 446         /* Timeouts occur when the device isn't connected, so they're
 447          * "normal" -- don't fill the kernel log with these */
 448         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 449                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 450                 return -ETIMEDOUT;
 451         }
 452
 453         /* Unload any bytes sent back from the other side */
 454         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 455                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 456         if (recv_bytes > recv_size)
 457                 recv_bytes = recv_size;
 458
 459         for (i = 0; i < recv_bytes; i += 4)
 460                 unpack_aux(I915_READ(ch_data + i),
 461                            recv + i, recv_bytes - i);
 462
 463         return recv_bytes;
 464 }
 465
 466 /* Write data to the aux channel in native mode */
 467 static int
 468 intel_dp_aux_native_write(struct intel_dp *intel_dp,
 469                           uint16_t address, uint8_t *send, int send_bytes)
 470 {
 471         int ret;
 472         uint8_t msg[20];
 473         int msg_bytes;
 474         uint8_t ack;
 475
 476         intel_dp_check_edp(intel_dp);
 477         if (send_bytes > 16)
 478                 return -1;
 479         msg[0] = AUX_NATIVE_WRITE << 4;
 480         msg[1] = address >> 8;
 481         msg[2] = address & 0xff;
 482         msg[3] = send_bytes - 1;
 483         memcpy(&msg[4], send, send_bytes);
 484         msg_bytes = send_bytes + 4;
 485         for (;;) {
 486                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
 487                 if (ret < 0)
 488                         return ret;
 489                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
 490                         break;
 491                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 492                         udelay(100);
 493                 else
 494                         return -EIO;
 495         }
 496         return send_bytes;
 497 }
 498
 499 /* Write a single byte to the aux channel in native mode */
 500 static int
 501 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
 502                             uint16_t address, uint8_t byte)
 503 {
 504         return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
 505 }
 506
 507 /* read bytes from a native aux channel */
 508 static int
 509 intel_dp_aux_native_read(struct intel_dp *intel_dp,
 510                          uint16_t address, uint8_t *recv, int recv_bytes)
 511 {
 512         uint8_t msg[4];
 513         int msg_bytes;
 514         uint8_t reply[20];
 515         int reply_bytes;
 516         uint8_t ack;
 517         int ret;
 518
 519         intel_dp_check_edp(intel_dp);
 520         msg[0] = AUX_NATIVE_READ << 4;
 521         msg[1] = address >> 8;
 522         msg[2] = address & 0xff;
 523         msg[3] = recv_bytes - 1;
 524
 525         msg_bytes = 4;
 526         reply_bytes = recv_bytes + 1;
 527
 528         for (;;) {
 529                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
 530                                       reply, reply_bytes);
 531                 if (ret == 0)
 532                         return -EPROTO;
 533                 if (ret < 0)
 534                         return ret;
 535                 ack = reply[0];
 536                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
 537                         memcpy(recv, reply + 1, ret - 1);
 538                         return ret - 1;
 539                 }
 540                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 541                         udelay(100);
 542                 else
 543                         return -EIO;
 544         }
 545 }
 546
 547 static int
 548 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
 549                     uint8_t write_byte, uint8_t *read_byte)
 550 {
 551         struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
 552         struct intel_dp *intel_dp = container_of(adapter,
 553                                                 struct intel_dp,
 554                                                 adapter);
 555         uint16_t address = algo_data->address;
 556         uint8_t msg[5];
 557         uint8_t reply[2];
 558         unsigned retry;
 559         int msg_bytes;
 560         int reply_bytes;
 561         int ret;
 562
 563         intel_dp_check_edp(intel_dp);
 564         /* Set up the command byte */
 565         if (mode & MODE_I2C_READ)
 566                 msg[0] = AUX_I2C_READ << 4;
 567         else
 568                 msg[0] = AUX_I2C_WRITE << 4;
 569
 570         if (!(mode & MODE_I2C_STOP))
 571                 msg[0] |= AUX_I2C_MOT << 4;
 572
 573         msg[1] = address >> 8;
 574         msg[2] = address;
 575
 576         switch (mode) {
 577         case MODE_I2C_WRITE:
 578                 msg[3] = 0;
 579                 msg[4] = write_byte;
 580                 msg_bytes = 5;
 581                 reply_bytes = 1;
 582                 break;
 583         case MODE_I2C_READ:
 584                 msg[3] = 0;
 585                 msg_bytes = 4;
 586                 reply_bytes = 2;
 587                 break;
 588         default:
 589                 msg_bytes = 3;
 590                 reply_bytes = 1;
 591                 break;
 592         }
 593
 594         for (retry = 0; retry < 5; retry++) {
 595                 ret = intel_dp_aux_ch(intel_dp,
 596                                       msg, msg_bytes,
 597                                       reply, reply_bytes);
 598                 if (ret < 0) {
 599                         DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
 600                         return ret;
 601                 }
 602
 603                 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
 604                 case AUX_NATIVE_REPLY_ACK:
 605                         /* I2C-over-AUX Reply field is only valid
 606                          * when paired with AUX ACK.
 607                          */
 608                         break;
 609                 case AUX_NATIVE_REPLY_NACK:
 610                         DRM_DEBUG_KMS("aux_ch native nack\n");
 611                         return -EREMOTEIO;
 612                 case AUX_NATIVE_REPLY_DEFER:
 613                         udelay(100);
 614                         continue;
 615                 default:
 616                         DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
 617                                   reply[0]);
 618                         return -EREMOTEIO;
 619                 }
 620
 621                 switch (reply[0] & AUX_I2C_REPLY_MASK) {
 622                 case AUX_I2C_REPLY_ACK:
 623                         if (mode == MODE_I2C_READ) {
 624                                 *read_byte = reply[1];
 625                         }
 626                         return reply_bytes - 1;
 627                 case AUX_I2C_REPLY_NACK:
 628                         DRM_DEBUG_KMS("aux_i2c nack\n");
 629                         return -EREMOTEIO;
 630                 case AUX_I2C_REPLY_DEFER:
 631                         DRM_DEBUG_KMS("aux_i2c defer\n");
 632                         udelay(100);
 633                         break;
 634                 default:
 635                         DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
 636                         return -EREMOTEIO;
 637                 }
 638         }
 639
 640         DRM_ERROR("too many retries, giving up\n");
 641         return -EREMOTEIO;
 642 }
 643
 644 static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
 645 static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 646
 647 static int
 648 intel_dp_i2c_init(struct intel_dp *intel_dp,
 649                   struct intel_connector *intel_connector, const char *name)
 650 {
 651         int     ret;
 652
 653         DRM_DEBUG_KMS("i2c_init %s\n", name);
 654         intel_dp->algo.running = false;
 655         intel_dp->algo.address = 0;
 656         intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
 657
 658         memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
 659         intel_dp->adapter.owner = THIS_MODULE;
 660         intel_dp->adapter.class = I2C_CLASS_DDC;
 661         strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
 662         intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
 663         intel_dp->adapter.algo_data = &intel_dp->algo;
 664         intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
 665
 666         ironlake_edp_panel_vdd_on(intel_dp);
 667         ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
 668         ironlake_edp_panel_vdd_off(intel_dp, false);
 669         return ret;
 670 }
 671
 672 static bool
 673 intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
 674                     struct drm_display_mode *adjusted_mode)
 675 {
 676         struct drm_device *dev = encoder->dev;
 677         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 678         int lane_count, clock;
 679         int max_lane_count = intel_dp_max_lane_count(intel_dp);
 680         int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
 681         static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
 682
 683         if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
 684                 intel_fixed_panel_mode(intel_dp->panel_fixed_mode, adjusted_mode);
 685                 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
 686                                         mode, adjusted_mode);
 687                 /*
 688                  * the mode->clock is used to calculate the Data&Link M/N
 689                  * of the pipe. For the eDP the fixed clock should be used.
 690                  */
 691                 mode->clock = intel_dp->panel_fixed_mode->clock;
 692         }
 693
 694         for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
 695                 for (clock = 0; clock <= max_clock; clock++) {
 696                         int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
 697
 698                         if (intel_dp_link_required(intel_dp, mode->clock)
 699                                         <= link_avail) {
 700                                 intel_dp->link_bw = bws[clock];
 701                                 intel_dp->lane_count = lane_count;
 702                                 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
 703                                 DRM_DEBUG_KMS("Display port link bw %02x lane "
 704                                                 "count %d clock %d\n",
 705                                        intel_dp->link_bw, intel_dp->lane_count,
 706                                        adjusted_mode->clock);
 707                                 return true;
 708                         }
 709                 }
 710         }
 711
 712         return false;
 713 }
 714
 715 struct intel_dp_m_n {
 716         uint32_t        tu;
 717         uint32_t        gmch_m;
 718         uint32_t        gmch_n;
 719         uint32_t        link_m;
 720         uint32_t        link_n;
 721 };
 722
 723 static void
 724 intel_reduce_ratio(uint32_t *num, uint32_t *den)
 725 {
 726         while (*num > 0xffffff || *den > 0xffffff) {
 727                 *num >>= 1;
 728                 *den >>= 1;
 729         }
 730 }
 731
 732 static void
 733 intel_dp_compute_m_n(int bpp,
 734                      int nlanes,
 735                      int pixel_clock,
 736                      int link_clock,
 737                      struct intel_dp_m_n *m_n)
 738 {
 739         m_n->tu = 64;
 740         m_n->gmch_m = (pixel_clock * bpp) >> 3;
 741         m_n->gmch_n = link_clock * nlanes;
 742         intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
 743         m_n->link_m = pixel_clock;
 744         m_n->link_n = link_clock;
 745         intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
 746 }
 747
 748 void
 749 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
 750                  struct drm_display_mode *adjusted_mode)
 751 {
 752         struct drm_device *dev = crtc->dev;
 753         struct drm_mode_config *mode_config = &dev->mode_config;
 754         struct drm_encoder *encoder;
 755         struct drm_i915_private *dev_priv = dev->dev_private;
 756         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 757         int lane_count = 4;
 758         struct intel_dp_m_n m_n;
 759         int pipe = intel_crtc->pipe;
 760
 761         /*
 762          * Find the lane count in the intel_encoder private
 763          */
 764         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
 765                 struct intel_dp *intel_dp;
 766
 767                 if (encoder->crtc != crtc)
 768                         continue;
 769
 770                 intel_dp = enc_to_intel_dp(encoder);
 771                 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) {
 772                         lane_count = intel_dp->lane_count;
 773                         break;
 774                 } else if (is_edp(intel_dp)) {
 775                         lane_count = dev_priv->edp.lanes;
 776                         break;
 777                 }
 778         }
 779
 780         /*
 781          * Compute the GMCH and Link ratios. The '3' here is
 782          * the number of bytes_per_pixel post-LUT, which we always
 783          * set up for 8-bits of R/G/B, or 3 bytes total.
 784          */
 785         intel_dp_compute_m_n(intel_crtc->bpp, lane_count,
 786                              mode->clock, adjusted_mode->clock, &m_n);
 787
 788         if (HAS_PCH_SPLIT(dev)) {
 789                 I915_WRITE(TRANSDATA_M1(pipe),
 790                            ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 791                            m_n.gmch_m);
 792                 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
 793                 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
 794                 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
 795         } else {
 796                 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
 797                            ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 798                            m_n.gmch_m);
 799                 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
 800                 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
 801                 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
 802         }
 803 }
 804
 805 static void ironlake_edp_pll_on(struct drm_encoder *encoder);
 806 static void ironlake_edp_pll_off(struct drm_encoder *encoder);
 807
 808 static void
 809 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
 810                   struct drm_display_mode *adjusted_mode)
 811 {
 812         struct drm_device *dev = encoder->dev;
 813         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 814         struct drm_crtc *crtc = intel_dp->base.base.crtc;
 815         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 816
 817         /* Turn on the eDP PLL if needed */
 818         if (is_edp(intel_dp)) {
 819                 if (!is_pch_edp(intel_dp))
 820                         ironlake_edp_pll_on(encoder);
 821                 else
 822                         ironlake_edp_pll_off(encoder);
 823         }
 824
 825         intel_dp->DP = DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 826         intel_dp->DP |= intel_dp->color_range;
 827
 828         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 829                 intel_dp->DP |= DP_SYNC_HS_HIGH;
 830         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 831                 intel_dp->DP |= DP_SYNC_VS_HIGH;
 832
 833         if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
 834                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 835         else
 836                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
 837
 838         switch (intel_dp->lane_count) {
 839         case 1:
 840                 intel_dp->DP |= DP_PORT_WIDTH_1;
 841                 break;
 842         case 2:
 843                 intel_dp->DP |= DP_PORT_WIDTH_2;
 844                 break;
 845         case 4:
 846                 intel_dp->DP |= DP_PORT_WIDTH_4;
 847                 break;
 848         }
 849         if (intel_dp->has_audio) {
 850                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
 851                                  pipe_name(intel_crtc->pipe));
 852                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
 853                 intel_write_eld(encoder, adjusted_mode);
 854         }
 855
 856         memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
 857         intel_dp->link_configuration[0] = intel_dp->link_bw;
 858         intel_dp->link_configuration[1] = intel_dp->lane_count;
 859         intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
 860
 861         /*
 862          * Check for DPCD version > 1.1 and enhanced framing support
 863          */
 864         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
 865             (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
 866                 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 867                 intel_dp->DP |= DP_ENHANCED_FRAMING;
 868         }
 869
 870         /* CPT DP's pipe select is decided in TRANS_DP_CTL */
 871         if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev))
 872                 intel_dp->DP |= DP_PIPEB_SELECT;
 873
 874         if (is_cpu_edp(intel_dp)) {
 875                 /* don't miss out required setting for eDP */
 876                 intel_dp->DP |= DP_PLL_ENABLE;
 877                 if (adjusted_mode->clock < 200000)
 878                         intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 879                 else
 880                         intel_dp->DP |= DP_PLL_FREQ_270MHZ;
 881         }
 882 }
 883
 884 static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
 885 {
 886         unsigned long   off_time;
 887         unsigned long   delay;
 888
 889         DRM_DEBUG_KMS("Wait for panel power off time\n");
 890
 891         if (ironlake_edp_have_panel_power(intel_dp) ||
 892             ironlake_edp_have_panel_vdd(intel_dp))
 893         {
 894                 DRM_DEBUG_KMS("Panel still on, no delay needed\n");
 895                 return;
 896         }
 897
 898         off_time = intel_dp->panel_off_jiffies + msecs_to_jiffies(intel_dp->panel_power_down_delay);
 899         if (time_after(jiffies, off_time)) {
 900                 DRM_DEBUG_KMS("Time already passed");
 901                 return;
 902         }
 903         delay = jiffies_to_msecs(off_time - jiffies);
 904         if (delay > intel_dp->panel_power_down_delay)
 905                 delay = intel_dp->panel_power_down_delay;
 906         DRM_DEBUG_KMS("Waiting an additional %ld ms\n", delay);
 907         msleep(delay);
 908 }
 909
 910 static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
 911 {
 912         struct drm_device *dev = intel_dp->base.base.dev;
 913         struct drm_i915_private *dev_priv = dev->dev_private;
 914         u32 pp;
 915
 916         if (!is_edp(intel_dp))
 917                 return;
 918         DRM_DEBUG_KMS("Turn eDP VDD on\n");
 919
 920         WARN(intel_dp->want_panel_vdd,
 921              "eDP VDD already requested on\n");
 922
 923         intel_dp->want_panel_vdd = true;
 924         if (ironlake_edp_have_panel_vdd(intel_dp)) {
 925                 DRM_DEBUG_KMS("eDP VDD already on\n");
 926                 return;
 927         }
 928
 929         ironlake_wait_panel_off(intel_dp);
 930         pp = I915_READ(PCH_PP_CONTROL);
 931         pp &= ~PANEL_UNLOCK_MASK;
 932         pp |= PANEL_UNLOCK_REGS;
 933         pp |= EDP_FORCE_VDD;
 934         I915_WRITE(PCH_PP_CONTROL, pp);
 935         POSTING_READ(PCH_PP_CONTROL);
 936         DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
 937                       I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
 938
 939         /*
 940          * If the panel wasn't on, delay before accessing aux channel
 941          */
 942         if (!ironlake_edp_have_panel_power(intel_dp)) {
 943                 DRM_DEBUG_KMS("eDP was not running\n");
 944                 msleep(intel_dp->panel_power_up_delay);
 945         }
 946 }
 947
 948 static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
 949 {
 950         struct drm_device *dev = intel_dp->base.base.dev;
 951         struct drm_i915_private *dev_priv = dev->dev_private;
 952         u32 pp;
 953
 954         if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
 955                 pp = I915_READ(PCH_PP_CONTROL);
 956                 pp &= ~PANEL_UNLOCK_MASK;
 957                 pp |= PANEL_UNLOCK_REGS;
 958                 pp &= ~EDP_FORCE_VDD;
 959                 I915_WRITE(PCH_PP_CONTROL, pp);
 960                 POSTING_READ(PCH_PP_CONTROL);
 961
 962                 /* Make sure sequencer is idle before allowing subsequent activity */
 963                 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
 964                               I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
 965                 intel_dp->panel_off_jiffies = jiffies;
 966         }
 967 }
 968
 969 static void ironlake_panel_vdd_work(struct work_struct *__work)
 970 {
 971         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
 972                                                  struct intel_dp, panel_vdd_work);
 973         struct drm_device *dev = intel_dp->base.base.dev;
 974
 975         mutex_lock(&dev->struct_mutex);
 976         ironlake_panel_vdd_off_sync(intel_dp);
 977         mutex_unlock(&dev->struct_mutex);
 978 }
 979
 980 static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
 981 {
 982         if (!is_edp(intel_dp))
 983                 return;
 984
 985         DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
 986         WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
 987
 988         intel_dp->want_panel_vdd = false;
 989
 990         if (sync) {
 991                 ironlake_panel_vdd_off_sync(intel_dp);
 992         } else {
 993                 /*
 994                  * Queue the timer to fire a long
 995                  * time from now (relative to the power down delay)
 996                  * to keep the panel power up across a sequence of operations
 997                  */
 998                 schedule_delayed_work(&intel_dp->panel_vdd_work,
 999                                       msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1000         }
1001 }
1002
1003 /* Returns true if the panel was already on when called */
1004 static void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1005 {
1006         struct drm_device *dev = intel_dp->base.base.dev;
1007         struct drm_i915_private *dev_priv = dev->dev_private;
1008         u32 pp, idle_on_mask = PP_ON | PP_SEQUENCE_STATE_ON_IDLE;
1009
1010         if (!is_edp(intel_dp))
1011                 return;
1012         if (ironlake_edp_have_panel_power(intel_dp))
1013                 return;
1014
1015         ironlake_wait_panel_off(intel_dp);
1016         pp = I915_READ(PCH_PP_CONTROL);
1017         pp &= ~PANEL_UNLOCK_MASK;
1018         pp |= PANEL_UNLOCK_REGS;
1019
1020         if (IS_GEN5(dev)) {
1021                 /* ILK workaround: disable reset around power sequence */
1022                 pp &= ~PANEL_POWER_RESET;
1023                 I915_WRITE(PCH_PP_CONTROL, pp);
1024                 POSTING_READ(PCH_PP_CONTROL);
1025         }
1026
1027         pp |= POWER_TARGET_ON;
1028         I915_WRITE(PCH_PP_CONTROL, pp);
1029         POSTING_READ(PCH_PP_CONTROL);
1030
1031         if (wait_for((I915_READ(PCH_PP_STATUS) & idle_on_mask) == idle_on_mask,
1032                      5000))
1033                 DRM_ERROR("panel on wait timed out: 0x%08x\n",
1034                           I915_READ(PCH_PP_STATUS));
1035
1036         if (IS_GEN5(dev)) {
1037                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1038                 I915_WRITE(PCH_PP_CONTROL, pp);
1039                 POSTING_READ(PCH_PP_CONTROL);
1040         }
1041 }
1042
1043 static void ironlake_edp_panel_off(struct drm_encoder *encoder)
1044 {
1045         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1046         struct drm_device *dev = encoder->dev;
1047         struct drm_i915_private *dev_priv = dev->dev_private;
1048         u32 pp, idle_off_mask = PP_ON | PP_SEQUENCE_MASK |
1049                 PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK;
1050
1051         if (!is_edp(intel_dp))
1052                 return;
1053         pp = I915_READ(PCH_PP_CONTROL);
1054         pp &= ~PANEL_UNLOCK_MASK;
1055         pp |= PANEL_UNLOCK_REGS;
1056
1057         if (IS_GEN5(dev)) {
1058                 /* ILK workaround: disable reset around power sequence */
1059                 pp &= ~PANEL_POWER_RESET;
1060                 I915_WRITE(PCH_PP_CONTROL, pp);
1061                 POSTING_READ(PCH_PP_CONTROL);
1062         }
1063
1064         intel_dp->panel_off_jiffies = jiffies;
1065
1066         if (IS_GEN5(dev)) {
1067                 pp &= ~POWER_TARGET_ON;
1068                 I915_WRITE(PCH_PP_CONTROL, pp);
1069                 POSTING_READ(PCH_PP_CONTROL);
1070                 pp &= ~POWER_TARGET_ON;
1071                 I915_WRITE(PCH_PP_CONTROL, pp);
1072                 POSTING_READ(PCH_PP_CONTROL);
1073                 msleep(intel_dp->panel_power_cycle_delay);
1074
1075                 if (wait_for((I915_READ(PCH_PP_STATUS) & idle_off_mask) == 0, 5000))
1076                         DRM_ERROR("panel off wait timed out: 0x%08x\n",
1077                                   I915_READ(PCH_PP_STATUS));
1078
1079                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1080                 I915_WRITE(PCH_PP_CONTROL, pp);
1081                 POSTING_READ(PCH_PP_CONTROL);
1082         }
1083 }
1084
1085 static void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1086 {
1087         struct drm_device *dev = intel_dp->base.base.dev;
1088         struct drm_i915_private *dev_priv = dev->dev_private;
1089         u32 pp;
1090
1091         if (!is_edp(intel_dp))
1092                 return;
1093
1094         DRM_DEBUG_KMS("\n");
1095         /*
1096          * If we enable the backlight right away following a panel power
1097          * on, we may see slight flicker as the panel syncs with the eDP
1098          * link.  So delay a bit to make sure the image is solid before
1099          * allowing it to appear.
1100          */
1101         msleep(intel_dp->backlight_on_delay);
1102         pp = I915_READ(PCH_PP_CONTROL);
1103         pp &= ~PANEL_UNLOCK_MASK;
1104         pp |= PANEL_UNLOCK_REGS;
1105         pp |= EDP_BLC_ENABLE;
1106         I915_WRITE(PCH_PP_CONTROL, pp);
1107         POSTING_READ(PCH_PP_CONTROL);
1108 }
1109
1110 static void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1111 {
1112         struct drm_device *dev = intel_dp->base.base.dev;
1113         struct drm_i915_private *dev_priv = dev->dev_private;
1114         u32 pp;
1115
1116         if (!is_edp(intel_dp))
1117                 return;
1118
1119         DRM_DEBUG_KMS("\n");
1120         pp = I915_READ(PCH_PP_CONTROL);
1121         pp &= ~PANEL_UNLOCK_MASK;
1122         pp |= PANEL_UNLOCK_REGS;
1123         pp &= ~EDP_BLC_ENABLE;
1124         I915_WRITE(PCH_PP_CONTROL, pp);
1125         POSTING_READ(PCH_PP_CONTROL);
1126         msleep(intel_dp->backlight_off_delay);
1127 }
1128
1129 static void ironlake_edp_pll_on(struct drm_encoder *encoder)
1130 {
1131         struct drm_device *dev = encoder->dev;
1132         struct drm_i915_private *dev_priv = dev->dev_private;
1133         u32 dpa_ctl;
1134
1135         DRM_DEBUG_KMS("\n");
1136         dpa_ctl = I915_READ(DP_A);
1137         dpa_ctl |= DP_PLL_ENABLE;
1138         I915_WRITE(DP_A, dpa_ctl);
1139         POSTING_READ(DP_A);
1140         udelay(200);
1141 }
1142
1143 static void ironlake_edp_pll_off(struct drm_encoder *encoder)
1144 {
1145         struct drm_device *dev = encoder->dev;
1146         struct drm_i915_private *dev_priv = dev->dev_private;
1147         u32 dpa_ctl;
1148
1149         dpa_ctl = I915_READ(DP_A);
1150         dpa_ctl &= ~DP_PLL_ENABLE;
1151         I915_WRITE(DP_A, dpa_ctl);
1152         POSTING_READ(DP_A);
1153         udelay(200);
1154 }
1155
1156 /* If the sink supports it, try to set the power state appropriately */
1157 static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1158 {
1159         int ret, i;
1160
1161         /* Should have a valid DPCD by this point */
1162         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1163                 return;
1164
1165         if (mode != DRM_MODE_DPMS_ON) {
1166                 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1167                                                   DP_SET_POWER_D3);
1168                 if (ret != 1)
1169                         DRM_DEBUG_DRIVER("failed to write sink power state\n");
1170         } else {
1171                 /*
1172                  * When turning on, we need to retry for 1ms to give the sink
1173                  * time to wake up.
1174                  */
1175                 for (i = 0; i < 3; i++) {
1176                         ret = intel_dp_aux_native_write_1(intel_dp,
1177                                                           DP_SET_POWER,
1178                                                           DP_SET_POWER_D0);
1179                         if (ret == 1)
1180                                 break;
1181                         msleep(1);
1182                 }
1183         }
1184 }
1185
1186 static void intel_dp_prepare(struct drm_encoder *encoder)
1187 {
1188         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1189
1190         /* Wake up the sink first */
1191         ironlake_edp_panel_vdd_on(intel_dp);
1192         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1193         ironlake_edp_panel_vdd_off(intel_dp, false);
1194
1195         /* Make sure the panel is off before trying to
1196          * change the mode
1197          */
1198         ironlake_edp_backlight_off(intel_dp);
1199         intel_dp_link_down(intel_dp);
1200         ironlake_edp_panel_off(encoder);
1201 }
1202
1203 static void intel_dp_commit(struct drm_encoder *encoder)
1204 {
1205         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1206         struct drm_device *dev = encoder->dev;
1207         struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
1208
1209         ironlake_edp_panel_vdd_on(intel_dp);
1210         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1211         intel_dp_start_link_train(intel_dp);
1212         ironlake_edp_panel_on(intel_dp);
1213         ironlake_edp_panel_vdd_off(intel_dp, true);
1214
1215         intel_dp_complete_link_train(intel_dp);
1216         ironlake_edp_backlight_on(intel_dp);
1217
1218         intel_dp->dpms_mode = DRM_MODE_DPMS_ON;
1219
1220         if (HAS_PCH_CPT(dev))
1221                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
1222 }
1223
1224 static void
1225 intel_dp_dpms(struct drm_encoder *encoder, int mode)
1226 {
1227         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1228         struct drm_device *dev = encoder->dev;
1229         struct drm_i915_private *dev_priv = dev->dev_private;
1230         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1231
1232         if (mode != DRM_MODE_DPMS_ON) {
1233                 ironlake_edp_panel_vdd_on(intel_dp);
1234                 if (is_edp(intel_dp))
1235                         ironlake_edp_backlight_off(intel_dp);
1236                 intel_dp_sink_dpms(intel_dp, mode);
1237                 intel_dp_link_down(intel_dp);
1238                 ironlake_edp_panel_off(encoder);
1239                 if (is_edp(intel_dp) && !is_pch_edp(intel_dp))
1240                         ironlake_edp_pll_off(encoder);
1241                 ironlake_edp_panel_vdd_off(intel_dp, false);
1242         } else {
1243                 ironlake_edp_panel_vdd_on(intel_dp);
1244                 intel_dp_sink_dpms(intel_dp, mode);
1245                 if (!(dp_reg & DP_PORT_EN)) {
1246                         intel_dp_start_link_train(intel_dp);
1247                         ironlake_edp_panel_on(intel_dp);
1248                         ironlake_edp_panel_vdd_off(intel_dp, true);
1249                         intel_dp_complete_link_train(intel_dp);
1250                         ironlake_edp_backlight_on(intel_dp);
1251                 } else
1252                         ironlake_edp_panel_vdd_off(intel_dp, false);
1253                 ironlake_edp_backlight_on(intel_dp);
1254         }
1255         intel_dp->dpms_mode = mode;
1256 }
1257
1258 /*
1259  * Native read with retry for link status and receiver capability reads for
1260  * cases where the sink may still be asleep.
1261  */
1262 static bool
1263 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1264                                uint8_t *recv, int recv_bytes)
1265 {
1266         int ret, i;
1267
1268         /*
1269          * Sinks are *supposed* to come up within 1ms from an off state,
1270          * but we're also supposed to retry 3 times per the spec.
1271          */
1272         for (i = 0; i < 3; i++) {
1273                 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1274                                                recv_bytes);
1275                 if (ret == recv_bytes)
1276                         return true;
1277                 msleep(1);
1278         }
1279
1280         return false;
1281 }
1282
1283 /*
1284  * Fetch AUX CH registers 0x202 - 0x207 which contain
1285  * link status information
1286  */
1287 static bool
1288 intel_dp_get_link_status(struct intel_dp *intel_dp)
1289 {
1290         return intel_dp_aux_native_read_retry(intel_dp,
1291                                               DP_LANE0_1_STATUS,
1292                                               intel_dp->link_status,
1293                                               DP_LINK_STATUS_SIZE);
1294 }
1295
1296 static uint8_t
1297 intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1298                      int r)
1299 {
1300         return link_status[r - DP_LANE0_1_STATUS];
1301 }
1302
1303 static uint8_t
1304 intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
1305                                  int lane)
1306 {
1307         int         i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
1308         int         s = ((lane & 1) ?
1309                          DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
1310                          DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
1311         uint8_t l = intel_dp_link_status(link_status, i);
1312
1313         return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
1314 }
1315
1316 static uint8_t
1317 intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
1318                                       int lane)
1319 {
1320         int         i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
1321         int         s = ((lane & 1) ?
1322                          DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
1323                          DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
1324         uint8_t l = intel_dp_link_status(link_status, i);
1325
1326         return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
1327 }
1328
1329
1330 #if 0
1331 static char     *voltage_names[] = {
1332         "0.4V", "0.6V", "0.8V", "1.2V"
1333 };
1334 static char     *pre_emph_names[] = {
1335         "0dB", "3.5dB", "6dB", "9.5dB"
1336 };
1337 static char     *link_train_names[] = {
1338         "pattern 1", "pattern 2", "idle", "off"
1339 };
1340 #endif
1341
1342 /*
1343  * These are source-specific values; current Intel hardware supports
1344  * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1345  */
1346 #define I830_DP_VOLTAGE_MAX         DP_TRAIN_VOLTAGE_SWING_800
1347
1348 static uint8_t
1349 intel_dp_pre_emphasis_max(uint8_t voltage_swing)
1350 {
1351         switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1352         case DP_TRAIN_VOLTAGE_SWING_400:
1353                 return DP_TRAIN_PRE_EMPHASIS_6;
1354         case DP_TRAIN_VOLTAGE_SWING_600:
1355                 return DP_TRAIN_PRE_EMPHASIS_6;
1356         case DP_TRAIN_VOLTAGE_SWING_800:
1357                 return DP_TRAIN_PRE_EMPHASIS_3_5;
1358         case DP_TRAIN_VOLTAGE_SWING_1200:
1359         default:
1360                 return DP_TRAIN_PRE_EMPHASIS_0;
1361         }
1362 }
1363
1364 static void
1365 intel_get_adjust_train(struct intel_dp *intel_dp)
1366 {
1367         uint8_t v = 0;
1368         uint8_t p = 0;
1369         int lane;
1370
1371         for (lane = 0; lane < intel_dp->lane_count; lane++) {
1372                 uint8_t this_v = intel_get_adjust_request_voltage(intel_dp->link_status, lane);
1373                 uint8_t this_p = intel_get_adjust_request_pre_emphasis(intel_dp->link_status, lane);
1374
1375                 if (this_v > v)
1376                         v = this_v;
1377                 if (this_p > p)
1378                         p = this_p;
1379         }
1380
1381         if (v >= I830_DP_VOLTAGE_MAX)
1382                 v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED;
1383
1384         if (p >= intel_dp_pre_emphasis_max(v))
1385                 p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1386
1387         for (lane = 0; lane < 4; lane++)
1388                 intel_dp->train_set[lane] = v | p;
1389 }
1390
1391 static uint32_t
1392 intel_dp_signal_levels(uint8_t train_set, int lane_count)
1393 {
1394         uint32_t        signal_levels = 0;
1395
1396         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1397         case DP_TRAIN_VOLTAGE_SWING_400:
1398         default:
1399                 signal_levels |= DP_VOLTAGE_0_4;
1400                 break;
1401         case DP_TRAIN_VOLTAGE_SWING_600:
1402                 signal_levels |= DP_VOLTAGE_0_6;
1403                 break;
1404         case DP_TRAIN_VOLTAGE_SWING_800:
1405                 signal_levels |= DP_VOLTAGE_0_8;
1406                 break;
1407         case DP_TRAIN_VOLTAGE_SWING_1200:
1408                 signal_levels |= DP_VOLTAGE_1_2;
1409                 break;
1410         }
1411         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1412         case DP_TRAIN_PRE_EMPHASIS_0:
1413         default:
1414                 signal_levels |= DP_PRE_EMPHASIS_0;
1415                 break;
1416         case DP_TRAIN_PRE_EMPHASIS_3_5:
1417                 signal_levels |= DP_PRE_EMPHASIS_3_5;
1418                 break;
1419         case DP_TRAIN_PRE_EMPHASIS_6:
1420                 signal_levels |= DP_PRE_EMPHASIS_6;
1421                 break;
1422         case DP_TRAIN_PRE_EMPHASIS_9_5:
1423                 signal_levels |= DP_PRE_EMPHASIS_9_5;
1424                 break;
1425         }
1426         return signal_levels;
1427 }
1428
1429 /* Gen6's DP voltage swing and pre-emphasis control */
1430 static uint32_t
1431 intel_gen6_edp_signal_levels(uint8_t train_set)
1432 {
1433         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1434                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1435         switch (signal_levels) {
1436         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1437         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1438                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1439         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1440                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1441         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1442         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1443                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1444         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1445         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1446                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1447         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1448         case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1449                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1450         default:
1451                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1452                               "0x%x\n", signal_levels);
1453                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1454         }
1455 }
1456
1457 static uint8_t
1458 intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1459                       int lane)
1460 {
1461         int i = DP_LANE0_1_STATUS + (lane >> 1);
1462         int s = (lane & 1) * 4;
1463         uint8_t l = intel_dp_link_status(link_status, i);
1464
1465         return (l >> s) & 0xf;
1466 }
1467
1468 /* Check for clock recovery is done on all channels */
1469 static bool
1470 intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1471 {
1472         int lane;
1473         uint8_t lane_status;
1474
1475         for (lane = 0; lane < lane_count; lane++) {
1476                 lane_status = intel_get_lane_status(link_status, lane);
1477                 if ((lane_status & DP_LANE_CR_DONE) == 0)
1478                         return false;
1479         }
1480         return true;
1481 }
1482
1483 /* Check to see if channel eq is done on all channels */
1484 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1485                          DP_LANE_CHANNEL_EQ_DONE|\
1486                          DP_LANE_SYMBOL_LOCKED)
1487 static bool
1488 intel_channel_eq_ok(struct intel_dp *intel_dp)
1489 {
1490         uint8_t lane_align;
1491         uint8_t lane_status;
1492         int lane;
1493
1494         lane_align = intel_dp_link_status(intel_dp->link_status,
1495                                           DP_LANE_ALIGN_STATUS_UPDATED);
1496         if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
1497                 return false;
1498         for (lane = 0; lane < intel_dp->lane_count; lane++) {
1499                 lane_status = intel_get_lane_status(intel_dp->link_status, lane);
1500                 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
1501                         return false;
1502         }
1503         return true;
1504 }
1505
1506 static bool
1507 intel_dp_set_link_train(struct intel_dp *intel_dp,
1508                         uint32_t dp_reg_value,
1509                         uint8_t dp_train_pat)
1510 {
1511         struct drm_device *dev = intel_dp->base.base.dev;
1512         struct drm_i915_private *dev_priv = dev->dev_private;
1513         int ret;
1514
1515         I915_WRITE(intel_dp->output_reg, dp_reg_value);
1516         POSTING_READ(intel_dp->output_reg);
1517
1518         intel_dp_aux_native_write_1(intel_dp,
1519                                     DP_TRAINING_PATTERN_SET,
1520                                     dp_train_pat);
1521
1522         ret = intel_dp_aux_native_write(intel_dp,
1523                                         DP_TRAINING_LANE0_SET,
1524                                         intel_dp->train_set, 4);
1525         if (ret != 4)
1526                 return false;
1527
1528         return true;
1529 }
1530
1531 /* Enable corresponding port and start training pattern 1 */
1532 static void
1533 intel_dp_start_link_train(struct intel_dp *intel_dp)
1534 {
1535         struct drm_device *dev = intel_dp->base.base.dev;
1536         struct drm_i915_private *dev_priv = dev->dev_private;
1537         struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
1538         int i;
1539         uint8_t voltage;
1540         bool clock_recovery = false;
1541         int tries;
1542         u32 reg;
1543         uint32_t DP = intel_dp->DP;
1544
1545         /*
1546          * On CPT we have to enable the port in training pattern 1, which
1547          * will happen below in intel_dp_set_link_train.  Otherwise, enable
1548          * the port and wait for it to become active.
1549          */
1550         if (!HAS_PCH_CPT(dev)) {
1551                 I915_WRITE(intel_dp->output_reg, intel_dp->DP);
1552                 POSTING_READ(intel_dp->output_reg);
1553                 intel_wait_for_vblank(dev, intel_crtc->pipe);
1554         }
1555
1556         /* Write the link configuration data */
1557         intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1558                                   intel_dp->link_configuration,
1559                                   DP_LINK_CONFIGURATION_SIZE);
1560
1561         DP |= DP_PORT_EN;
1562         if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1563                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1564         else
1565                 DP &= ~DP_LINK_TRAIN_MASK;
1566         memset(intel_dp->train_set, 0, 4);
1567         voltage = 0xff;
1568         tries = 0;
1569         clock_recovery = false;
1570         for (;;) {
1571                 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1572                 uint32_t    signal_levels;
1573                 if (IS_GEN6(dev) && is_edp(intel_dp)) {
1574                         signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1575                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1576                 } else {
1577                         signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count);
1578                         DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1579                 }
1580
1581                 if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1582                         reg = DP | DP_LINK_TRAIN_PAT_1_CPT;
1583                 else
1584                         reg = DP | DP_LINK_TRAIN_PAT_1;
1585
1586                 if (!intel_dp_set_link_train(intel_dp, reg,
1587                                              DP_TRAINING_PATTERN_1 |
1588                                              DP_LINK_SCRAMBLING_DISABLE))
1589                         break;
1590                 /* Set training pattern 1 */
1591
1592                 udelay(100);
1593                 if (!intel_dp_get_link_status(intel_dp))
1594                         break;
1595
1596                 if (intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
1597                         clock_recovery = true;
1598                         break;
1599                 }
1600
1601                 /* Check to see if we've tried the max voltage */
1602                 for (i = 0; i < intel_dp->lane_count; i++)
1603                         if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1604                                 break;
1605                 if (i == intel_dp->lane_count)
1606                         break;
1607
1608                 /* Check to see if we've tried the same voltage 5 times */
1609                 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1610                         ++tries;
1611                         if (tries == 5)
1612                                 break;
1613                 } else
1614                         tries = 0;
1615                 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1616
1617                 /* Compute new intel_dp->train_set as requested by target */
1618                 intel_get_adjust_train(intel_dp);
1619         }
1620
1621         intel_dp->DP = DP;
1622 }
1623
1624 static void
1625 intel_dp_complete_link_train(struct intel_dp *intel_dp)
1626 {
1627         struct drm_device *dev = intel_dp->base.base.dev;
1628         struct drm_i915_private *dev_priv = dev->dev_private;
1629         bool channel_eq = false;
1630         int tries, cr_tries;
1631         u32 reg;
1632         uint32_t DP = intel_dp->DP;
1633
1634         /* channel equalization */
1635         tries = 0;
1636         cr_tries = 0;
1637         channel_eq = false;
1638         for (;;) {
1639                 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1640                 uint32_t    signal_levels;
1641
1642                 if (cr_tries > 5) {
1643                         DRM_ERROR("failed to train DP, aborting\n");
1644                         intel_dp_link_down(intel_dp);
1645                         break;
1646                 }
1647
1648                 if (IS_GEN6(dev) && is_edp(intel_dp)) {
1649                         signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1650                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1651                 } else {
1652                         signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count);
1653                         DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1654                 }
1655
1656                 if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1657                         reg = DP | DP_LINK_TRAIN_PAT_2_CPT;
1658                 else
1659                         reg = DP | DP_LINK_TRAIN_PAT_2;
1660
1661                 /* channel eq pattern */
1662                 if (!intel_dp_set_link_train(intel_dp, reg,
1663                                              DP_TRAINING_PATTERN_2 |
1664                                              DP_LINK_SCRAMBLING_DISABLE))
1665                         break;
1666
1667                 udelay(400);
1668                 if (!intel_dp_get_link_status(intel_dp))
1669                         break;
1670
1671                 /* Make sure clock is still ok */
1672                 if (!intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
1673                         intel_dp_start_link_train(intel_dp);
1674                         cr_tries++;
1675                         continue;
1676                 }
1677
1678                 if (intel_channel_eq_ok(intel_dp)) {
1679                         channel_eq = true;
1680                         break;
1681                 }
1682
1683                 /* Try 5 times, then try clock recovery if that fails */
1684                 if (tries > 5) {
1685                         intel_dp_link_down(intel_dp);
1686                         intel_dp_start_link_train(intel_dp);
1687                         tries = 0;
1688                         cr_tries++;
1689                         continue;
1690                 }
1691
1692                 /* Compute new intel_dp->train_set as requested by target */
1693                 intel_get_adjust_train(intel_dp);
1694                 ++tries;
1695         }
1696
1697         if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1698                 reg = DP | DP_LINK_TRAIN_OFF_CPT;
1699         else
1700                 reg = DP | DP_LINK_TRAIN_OFF;
1701
1702         I915_WRITE(intel_dp->output_reg, reg);
1703         POSTING_READ(intel_dp->output_reg);
1704         intel_dp_aux_native_write_1(intel_dp,
1705                                     DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1706 }
1707
1708 static void
1709 intel_dp_link_down(struct intel_dp *intel_dp)
1710 {
1711         struct drm_device *dev = intel_dp->base.base.dev;
1712         struct drm_i915_private *dev_priv = dev->dev_private;
1713         uint32_t DP = intel_dp->DP;
1714
1715         if ((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)
1716                 return;
1717
1718         DRM_DEBUG_KMS("\n");
1719
1720         if (is_edp(intel_dp)) {
1721                 DP &= ~DP_PLL_ENABLE;
1722                 I915_WRITE(intel_dp->output_reg, DP);
1723                 POSTING_READ(intel_dp->output_reg);
1724                 udelay(100);
1725         }
1726
1727         if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp)) {
1728                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1729                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
1730         } else {
1731                 DP &= ~DP_LINK_TRAIN_MASK;
1732                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1733         }
1734         POSTING_READ(intel_dp->output_reg);
1735
1736         msleep(17);
1737
1738         if (is_edp(intel_dp))
1739                 DP |= DP_LINK_TRAIN_OFF;
1740
1741         if (!HAS_PCH_CPT(dev) &&
1742             I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
1743                 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1744
1745                 /* Hardware workaround: leaving our transcoder select
1746                  * set to transcoder B while it's off will prevent the
1747                  * corresponding HDMI output on transcoder A.
1748                  *
1749                  * Combine this with another hardware workaround:
1750                  * transcoder select bit can only be cleared while the
1751                  * port is enabled.
1752                  */
1753                 DP &= ~DP_PIPEB_SELECT;
1754                 I915_WRITE(intel_dp->output_reg, DP);
1755
1756                 /* Changes to enable or select take place the vblank
1757                  * after being written.
1758                  */
1759                 if (crtc == NULL) {
1760                         /* We can arrive here never having been attached
1761                          * to a CRTC, for instance, due to inheriting
1762                          * random state from the BIOS.
1763                          *
1764                          * If the pipe is not running, play safe and
1765                          * wait for the clocks to stabilise before
1766                          * continuing.
1767                          */
1768                         POSTING_READ(intel_dp->output_reg);
1769                         msleep(50);
1770                 } else
1771                         intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
1772         }
1773
1774         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
1775         POSTING_READ(intel_dp->output_reg);
1776         msleep(intel_dp->panel_power_down_delay);
1777 }
1778
1779 static bool
1780 intel_dp_get_dpcd(struct intel_dp *intel_dp)
1781 {
1782         if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
1783                                            sizeof(intel_dp->dpcd)) &&
1784             (intel_dp->dpcd[DP_DPCD_REV] != 0)) {
1785                 return true;
1786         }
1787
1788         return false;
1789 }
1790
1791 static bool
1792 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
1793 {
1794         int ret;
1795
1796         ret = intel_dp_aux_native_read_retry(intel_dp,
1797                                              DP_DEVICE_SERVICE_IRQ_VECTOR,
1798                                              sink_irq_vector, 1);
1799         if (!ret)
1800                 return false;
1801
1802         return true;
1803 }
1804
1805 static void
1806 intel_dp_handle_test_request(struct intel_dp *intel_dp)
1807 {
1808         /* NAK by default */
1809         intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_ACK);
1810 }
1811
1812 /*
1813  * According to DP spec
1814  * 5.1.2:
1815  *  1. Read DPCD
1816  *  2. Configure link according to Receiver Capabilities
1817  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
1818  *  4. Check link status on receipt of hot-plug interrupt
1819  */
1820
1821 static void
1822 intel_dp_check_link_status(struct intel_dp *intel_dp)
1823 {
1824         u8 sink_irq_vector;
1825
1826         if (intel_dp->dpms_mode != DRM_MODE_DPMS_ON)
1827                 return;
1828
1829         if (!intel_dp->base.base.crtc)
1830                 return;
1831
1832         /* Try to read receiver status if the link appears to be up */
1833         if (!intel_dp_get_link_status(intel_dp)) {
1834                 intel_dp_link_down(intel_dp);
1835                 return;
1836         }
1837
1838         /* Now read the DPCD to see if it's actually running */
1839         if (!intel_dp_get_dpcd(intel_dp)) {
1840                 intel_dp_link_down(intel_dp);
1841                 return;
1842         }
1843
1844         /* Try to read the source of the interrupt */
1845         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
1846             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
1847                 /* Clear interrupt source */
1848                 intel_dp_aux_native_write_1(intel_dp,
1849                                             DP_DEVICE_SERVICE_IRQ_VECTOR,
1850                                             sink_irq_vector);
1851
1852                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
1853                         intel_dp_handle_test_request(intel_dp);
1854                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
1855                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
1856         }
1857
1858         if (!intel_channel_eq_ok(intel_dp)) {
1859                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
1860                               drm_get_encoder_name(&intel_dp->base.base));
1861                 intel_dp_start_link_train(intel_dp);
1862                 intel_dp_complete_link_train(intel_dp);
1863         }
1864 }
1865
1866 static enum drm_connector_status
1867 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
1868 {
1869         if (intel_dp_get_dpcd(intel_dp))
1870                 return connector_status_connected;
1871         return connector_status_disconnected;
1872 }
1873
1874 static enum drm_connector_status
1875 ironlake_dp_detect(struct intel_dp *intel_dp)
1876 {
1877         enum drm_connector_status status;
1878
1879         /* Can't disconnect eDP, but you can close the lid... */
1880         if (is_edp(intel_dp)) {
1881                 status = intel_panel_detect(intel_dp->base.base.dev);
1882                 if (status == connector_status_unknown)
1883                         status = connector_status_connected;
1884                 return status;
1885         }
1886
1887         return intel_dp_detect_dpcd(intel_dp);
1888 }
1889
1890 static enum drm_connector_status
1891 g4x_dp_detect(struct intel_dp *intel_dp)
1892 {
1893         struct drm_device *dev = intel_dp->base.base.dev;
1894         struct drm_i915_private *dev_priv = dev->dev_private;
1895         uint32_t temp, bit;
1896
1897         switch (intel_dp->output_reg) {
1898         case DP_B:
1899                 bit = DPB_HOTPLUG_INT_STATUS;
1900                 break;
1901         case DP_C:
1902                 bit = DPC_HOTPLUG_INT_STATUS;
1903                 break;
1904         case DP_D:
1905                 bit = DPD_HOTPLUG_INT_STATUS;
1906                 break;
1907         default:
1908                 return connector_status_unknown;
1909         }
1910
1911         temp = I915_READ(PORT_HOTPLUG_STAT);
1912
1913         if ((temp & bit) == 0)
1914                 return connector_status_disconnected;
1915
1916         return intel_dp_detect_dpcd(intel_dp);
1917 }
1918
1919 static struct edid *
1920 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
1921 {
1922         struct intel_dp *intel_dp = intel_attached_dp(connector);
1923         struct edid     *edid;
1924
1925         ironlake_edp_panel_vdd_on(intel_dp);
1926         edid = drm_get_edid(connector, adapter);
1927         ironlake_edp_panel_vdd_off(intel_dp, false);
1928         return edid;
1929 }
1930
1931 static int
1932 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
1933 {
1934         struct intel_dp *intel_dp = intel_attached_dp(connector);
1935         int     ret;
1936
1937         ironlake_edp_panel_vdd_on(intel_dp);
1938         ret = intel_ddc_get_modes(connector, adapter);
1939         ironlake_edp_panel_vdd_off(intel_dp, false);
1940         return ret;
1941 }
1942
1943
1944 /**
1945  * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
1946  *
1947  * \return true if DP port is connected.
1948  * \return false if DP port is disconnected.
1949  */
1950 static enum drm_connector_status
1951 intel_dp_detect(struct drm_connector *connector, bool force)
1952 {
1953         struct intel_dp *intel_dp = intel_attached_dp(connector);
1954         struct drm_device *dev = intel_dp->base.base.dev;
1955         enum drm_connector_status status;
1956         struct edid *edid = NULL;
1957
1958         intel_dp->has_audio = false;
1959
1960         if (HAS_PCH_SPLIT(dev))
1961                 status = ironlake_dp_detect(intel_dp);
1962         else
1963                 status = g4x_dp_detect(intel_dp);
1964
1965         DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
1966                       intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2],
1967                       intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5],
1968                       intel_dp->dpcd[6], intel_dp->dpcd[7]);
1969
1970         if (status != connector_status_connected)
1971                 return status;
1972
1973         if (intel_dp->force_audio) {
1974                 intel_dp->has_audio = intel_dp->force_audio > 0;
1975         } else {
1976                 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
1977                 if (edid) {
1978                         intel_dp->has_audio = drm_detect_monitor_audio(edid);
1979                         connector->display_info.raw_edid = NULL;
1980                         kfree(edid);
1981                 }
1982         }
1983
1984         return connector_status_connected;
1985 }
1986
1987 static int intel_dp_get_modes(struct drm_connector *connector)
1988 {
1989         struct intel_dp *intel_dp = intel_attached_dp(connector);
1990         struct drm_device *dev = intel_dp->base.base.dev;
1991         struct drm_i915_private *dev_priv = dev->dev_private;
1992         int ret;
1993
1994         /* We should parse the EDID data and find out if it has an audio sink
1995          */
1996
1997         ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
1998         if (ret) {
1999                 if (is_edp(intel_dp) && !intel_dp->panel_fixed_mode) {
2000                         struct drm_display_mode *newmode;
2001                         list_for_each_entry(newmode, &connector->probed_modes,
2002                                             head) {
2003                                 if ((newmode->type & DRM_MODE_TYPE_PREFERRED)) {
2004                                         intel_dp->panel_fixed_mode =
2005                                                 drm_mode_duplicate(dev, newmode);
2006                                         break;
2007                                 }
2008                         }
2009                 }
2010                 return ret;
2011         }
2012
2013         /* if eDP has no EDID, try to use fixed panel mode from VBT */
2014         if (is_edp(intel_dp)) {
2015                 /* initialize panel mode from VBT if available for eDP */
2016                 if (intel_dp->panel_fixed_mode == NULL && dev_priv->lfp_lvds_vbt_mode != NULL) {
2017                         intel_dp->panel_fixed_mode =
2018                                 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
2019                         if (intel_dp->panel_fixed_mode) {
2020                                 intel_dp->panel_fixed_mode->type |=
2021                                         DRM_MODE_TYPE_PREFERRED;
2022                         }
2023                 }
2024                 if (intel_dp->panel_fixed_mode) {
2025                         struct drm_display_mode *mode;
2026                         mode = drm_mode_duplicate(dev, intel_dp->panel_fixed_mode);
2027                         drm_mode_probed_add(connector, mode);
2028                         return 1;
2029                 }
2030         }
2031         return 0;
2032 }
2033
2034 static bool
2035 intel_dp_detect_audio(struct drm_connector *connector)
2036 {
2037         struct intel_dp *intel_dp = intel_attached_dp(connector);
2038         struct edid *edid;
2039         bool has_audio = false;
2040
2041         edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2042         if (edid) {
2043                 has_audio = drm_detect_monitor_audio(edid);
2044
2045                 connector->display_info.raw_edid = NULL;
2046                 kfree(edid);
2047         }
2048
2049         return has_audio;
2050 }
2051
2052 static int
2053 intel_dp_set_property(struct drm_connector *connector,
2054                       struct drm_property *property,
2055                       uint64_t val)
2056 {
2057         struct drm_i915_private *dev_priv = connector->dev->dev_private;
2058         struct intel_dp *intel_dp = intel_attached_dp(connector);
2059         int ret;
2060
2061         ret = drm_connector_property_set_value(connector, property, val);
2062         if (ret)
2063                 return ret;
2064
2065         if (property == dev_priv->force_audio_property) {
2066                 int i = val;
2067                 bool has_audio;
2068
2069                 if (i == intel_dp->force_audio)
2070                         return 0;
2071
2072                 intel_dp->force_audio = i;
2073
2074                 if (i == 0)
2075                         has_audio = intel_dp_detect_audio(connector);
2076                 else
2077                         has_audio = i > 0;
2078
2079                 if (has_audio == intel_dp->has_audio)
2080                         return 0;
2081
2082                 intel_dp->has_audio = has_audio;
2083                 goto done;
2084         }
2085
2086         if (property == dev_priv->broadcast_rgb_property) {
2087                 if (val == !!intel_dp->color_range)
2088                         return 0;
2089
2090                 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
2091                 goto done;
2092         }
2093
2094         return -EINVAL;
2095
2096 done:
2097         if (intel_dp->base.base.crtc) {
2098                 struct drm_crtc *crtc = intel_dp->base.base.crtc;
2099                 drm_crtc_helper_set_mode(crtc, &crtc->mode,
2100                                          crtc->x, crtc->y,
2101                                          crtc->fb);
2102         }
2103
2104         return 0;
2105 }
2106
2107 static void
2108 intel_dp_destroy(struct drm_connector *connector)
2109 {
2110         struct drm_device *dev = connector->dev;
2111
2112         if (intel_dpd_is_edp(dev))
2113                 intel_panel_destroy_backlight(dev);
2114
2115         drm_sysfs_connector_remove(connector);
2116         drm_connector_cleanup(connector);
2117         kfree(connector);
2118 }
2119
2120 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2121 {
2122         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2123
2124         i2c_del_adapter(&intel_dp->adapter);
2125         drm_encoder_cleanup(encoder);
2126         if (is_edp(intel_dp)) {
2127                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2128                 ironlake_panel_vdd_off_sync(intel_dp);
2129         }
2130         kfree(intel_dp);
2131 }
2132
2133 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
2134         .dpms = intel_dp_dpms,
2135         .mode_fixup = intel_dp_mode_fixup,
2136         .prepare = intel_dp_prepare,
2137         .mode_set = intel_dp_mode_set,
2138         .commit = intel_dp_commit,
2139 };
2140
2141 static const struct drm_connector_funcs intel_dp_connector_funcs = {
2142         .dpms = drm_helper_connector_dpms,
2143         .detect = intel_dp_detect,
2144         .fill_modes = drm_helper_probe_single_connector_modes,
2145         .set_property = intel_dp_set_property,
2146         .destroy = intel_dp_destroy,
2147 };
2148
2149 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2150         .get_modes = intel_dp_get_modes,
2151         .mode_valid = intel_dp_mode_valid,
2152         .best_encoder = intel_best_encoder,
2153 };
2154
2155 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
2156         .destroy = intel_dp_encoder_destroy,
2157 };
2158
2159 static void
2160 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
2161 {
2162         struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
2163
2164         intel_dp_check_link_status(intel_dp);
2165 }
2166
2167 /* Return which DP Port should be selected for Transcoder DP control */
2168 int
2169 intel_trans_dp_port_sel(struct drm_crtc *crtc)
2170 {
2171         struct drm_device *dev = crtc->dev;
2172         struct drm_mode_config *mode_config = &dev->mode_config;
2173         struct drm_encoder *encoder;
2174
2175         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
2176                 struct intel_dp *intel_dp;
2177
2178                 if (encoder->crtc != crtc)
2179                         continue;
2180
2181                 intel_dp = enc_to_intel_dp(encoder);
2182                 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT)
2183                         return intel_dp->output_reg;
2184         }
2185
2186         return -1;
2187 }
2188
2189 /* check the VBT to see whether the eDP is on DP-D port */
2190 bool intel_dpd_is_edp(struct drm_device *dev)
2191 {
2192         struct drm_i915_private *dev_priv = dev->dev_private;
2193         struct child_device_config *p_child;
2194         int i;
2195
2196         if (!dev_priv->child_dev_num)
2197                 return false;
2198
2199         for (i = 0; i < dev_priv->child_dev_num; i++) {
2200                 p_child = dev_priv->child_dev + i;
2201
2202                 if (p_child->dvo_port == PORT_IDPD &&
2203                     p_child->device_type == DEVICE_TYPE_eDP)
2204                         return true;
2205         }
2206         return false;
2207 }
2208
2209 static void
2210 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2211 {
2212         intel_attach_force_audio_property(connector);
2213         intel_attach_broadcast_rgb_property(connector);
2214 }
2215
2216 void
2217 intel_dp_init(struct drm_device *dev, int output_reg)
2218 {
2219         struct drm_i915_private *dev_priv = dev->dev_private;
2220         struct drm_connector *connector;
2221         struct intel_dp *intel_dp;
2222         struct intel_encoder *intel_encoder;
2223         struct intel_connector *intel_connector;
2224         const char *name = NULL;
2225         int type;
2226
2227         intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
2228         if (!intel_dp)
2229                 return;
2230
2231         intel_dp->output_reg = output_reg;
2232         intel_dp->dpms_mode = -1;
2233
2234         intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
2235         if (!intel_connector) {
2236                 kfree(intel_dp);
2237                 return;
2238         }
2239         intel_encoder = &intel_dp->base;
2240
2241         if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
2242                 if (intel_dpd_is_edp(dev))
2243                         intel_dp->is_pch_edp = true;
2244
2245         if (output_reg == DP_A || is_pch_edp(intel_dp)) {
2246                 type = DRM_MODE_CONNECTOR_eDP;
2247                 intel_encoder->type = INTEL_OUTPUT_EDP;
2248         } else {
2249                 type = DRM_MODE_CONNECTOR_DisplayPort;
2250                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2251         }
2252
2253         connector = &intel_connector->base;
2254         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
2255         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2256
2257         connector->polled = DRM_CONNECTOR_POLL_HPD;
2258
2259         if (output_reg == DP_B || output_reg == PCH_DP_B)
2260                 intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
2261         else if (output_reg == DP_C || output_reg == PCH_DP_C)
2262                 intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
2263         else if (output_reg == DP_D || output_reg == PCH_DP_D)
2264                 intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
2265
2266         if (is_edp(intel_dp)) {
2267                 intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
2268                 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
2269                                   ironlake_panel_vdd_work);
2270         }
2271
2272         intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2273         connector->interlace_allowed = true;
2274         connector->doublescan_allowed = 0;
2275
2276         drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
2277                          DRM_MODE_ENCODER_TMDS);
2278         drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
2279
2280         intel_connector_attach_encoder(intel_connector, intel_encoder);
2281         drm_sysfs_connector_add(connector);
2282
2283         /* Set up the DDC bus. */
2284         switch (output_reg) {
2285                 case DP_A:
2286                         name = "DPDDC-A";
2287                         break;
2288                 case DP_B:
2289                 case PCH_DP_B:
2290                         dev_priv->hotplug_supported_mask |=
2291                                 HDMIB_HOTPLUG_INT_STATUS;
2292                         name = "DPDDC-B";
2293                         break;
2294                 case DP_C:
2295                 case PCH_DP_C:
2296                         dev_priv->hotplug_supported_mask |=
2297                                 HDMIC_HOTPLUG_INT_STATUS;
2298                         name = "DPDDC-C";
2299                         break;
2300                 case DP_D:
2301                 case PCH_DP_D:
2302                         dev_priv->hotplug_supported_mask |=
2303                                 HDMID_HOTPLUG_INT_STATUS;
2304                         name = "DPDDC-D";
2305                         break;
2306         }
2307
2308         /* Cache some DPCD data in the eDP case */
2309         if (is_edp(intel_dp)) {
2310                 bool ret;
2311                 struct edp_power_seq    cur, vbt;
2312                 u32 pp_on, pp_off, pp_div;
2313
2314                 pp_on = I915_READ(PCH_PP_ON_DELAYS);
2315                 pp_off = I915_READ(PCH_PP_OFF_DELAYS);
2316                 pp_div = I915_READ(PCH_PP_DIVISOR);
2317
2318                 /* Pull timing values out of registers */
2319                 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2320                         PANEL_POWER_UP_DELAY_SHIFT;
2321
2322                 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2323                         PANEL_LIGHT_ON_DELAY_SHIFT;
2324
2325                 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2326                         PANEL_LIGHT_OFF_DELAY_SHIFT;
2327
2328                 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2329                         PANEL_POWER_DOWN_DELAY_SHIFT;
2330
2331                 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2332                                PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2333
2334                 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2335                               cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2336
2337                 vbt = dev_priv->edp.pps;
2338
2339                 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2340                               vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2341
2342 #define get_delay(field)        ((max(cur.field, vbt.field) + 9) / 10)
2343
2344                 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2345                 intel_dp->backlight_on_delay = get_delay(t8);
2346                 intel_dp->backlight_off_delay = get_delay(t9);
2347                 intel_dp->panel_power_down_delay = get_delay(t10);
2348                 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2349
2350                 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2351                               intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2352                               intel_dp->panel_power_cycle_delay);
2353
2354                 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2355                               intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2356
2357                 intel_dp->panel_off_jiffies = jiffies - intel_dp->panel_power_down_delay;
2358
2359                 ironlake_edp_panel_vdd_on(intel_dp);
2360                 ret = intel_dp_get_dpcd(intel_dp);
2361                 ironlake_edp_panel_vdd_off(intel_dp, false);
2362                 if (ret) {
2363                         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2364                                 dev_priv->no_aux_handshake =
2365                                         intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
2366                                         DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2367                 } else {
2368                         /* if this fails, presume the device is a ghost */
2369                         DRM_INFO("failed to retrieve link info, disabling eDP\n");
2370                         intel_dp_encoder_destroy(&intel_dp->base.base);
2371                         intel_dp_destroy(&intel_connector->base);
2372                         return;
2373                 }
2374         }
2375
2376         intel_dp_i2c_init(intel_dp, intel_connector, name);
2377
2378         intel_encoder->hot_plug = intel_dp_hot_plug;
2379
2380         if (is_edp(intel_dp)) {
2381                 dev_priv->int_edp_connector = connector;
2382                 intel_panel_setup_backlight(dev);
2383         }
2384
2385         intel_dp_add_properties(intel_dp, connector);
2386
2387         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2388          * 0xd.  Failure to do so will result in spurious interrupts being
2389          * generated on the port when a cable is not attached.
2390          */
2391         if (IS_G4X(dev) && !IS_GM45(dev)) {
2392                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2393                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2394         }
2395 }