Pileus Git - ~andy/linux/blob - drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  45
  46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  47 static void intel_increase_pllclock(struct drm_crtc *crtc);
  48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  49
  50 typedef struct {
  51         /* given values */
  52         int n;
  53         int m1, m2;
  54         int p1, p2;
  55         /* derived values */
  56         int     dot;
  57         int     vco;
  58         int     m;
  59         int     p;
  60 } intel_clock_t;
  61
  62 typedef struct {
  63         int     min, max;
  64 } intel_range_t;
  65
  66 typedef struct {
  67         int     dot_limit;
  68         int     p2_slow, p2_fast;
  69 } intel_p2_t;
  70
  71 #define INTEL_P2_NUM                  2
  72 typedef struct intel_limit intel_limit_t;
  73 struct intel_limit {
  74         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  75         intel_p2_t          p2;
  76         bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  77                         int, int, intel_clock_t *, intel_clock_t *);
  78 };
  79
  80 /* FDI */
  81 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  82
  83 int
  84 intel_pch_rawclk(struct drm_device *dev)
  85 {
  86         struct drm_i915_private *dev_priv = dev->dev_private;
  87
  88         WARN_ON(!HAS_PCH_SPLIT(dev));
  89
  90         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  91 }
  92
  93 static bool
  94 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  95                     int target, int refclk, intel_clock_t *match_clock,
  96                     intel_clock_t *best_clock);
  97 static bool
  98 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  99                         int target, int refclk, intel_clock_t *match_clock,
 100                         intel_clock_t *best_clock);
 101
 102 static bool
 103 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 104                       int target, int refclk, intel_clock_t *match_clock,
 105                       intel_clock_t *best_clock);
 106 static bool
 107 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 108                            int target, int refclk, intel_clock_t *match_clock,
 109                            intel_clock_t *best_clock);
 110
 111 static bool
 112 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 113                         int target, int refclk, intel_clock_t *match_clock,
 114                         intel_clock_t *best_clock);
 115
 116 static inline u32 /* units of 100MHz */
 117 intel_fdi_link_freq(struct drm_device *dev)
 118 {
 119         if (IS_GEN5(dev)) {
 120                 struct drm_i915_private *dev_priv = dev->dev_private;
 121                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 122         } else
 123                 return 27;
 124 }
 125
 126 static const intel_limit_t intel_limits_i8xx_dvo = {
 127         .dot = { .min = 25000, .max = 350000 },
 128         .vco = { .min = 930000, .max = 1400000 },
 129         .n = { .min = 3, .max = 16 },
 130         .m = { .min = 96, .max = 140 },
 131         .m1 = { .min = 18, .max = 26 },
 132         .m2 = { .min = 6, .max = 16 },
 133         .p = { .min = 4, .max = 128 },
 134         .p1 = { .min = 2, .max = 33 },
 135         .p2 = { .dot_limit = 165000,
 136                 .p2_slow = 4, .p2_fast = 2 },
 137         .find_pll = intel_find_best_PLL,
 138 };
 139
 140 static const intel_limit_t intel_limits_i8xx_lvds = {
 141         .dot = { .min = 25000, .max = 350000 },
 142         .vco = { .min = 930000, .max = 1400000 },
 143         .n = { .min = 3, .max = 16 },
 144         .m = { .min = 96, .max = 140 },
 145         .m1 = { .min = 18, .max = 26 },
 146         .m2 = { .min = 6, .max = 16 },
 147         .p = { .min = 4, .max = 128 },
 148         .p1 = { .min = 1, .max = 6 },
 149         .p2 = { .dot_limit = 165000,
 150                 .p2_slow = 14, .p2_fast = 7 },
 151         .find_pll = intel_find_best_PLL,
 152 };
 153
 154 static const intel_limit_t intel_limits_i9xx_sdvo = {
 155         .dot = { .min = 20000, .max = 400000 },
 156         .vco = { .min = 1400000, .max = 2800000 },
 157         .n = { .min = 1, .max = 6 },
 158         .m = { .min = 70, .max = 120 },
 159         .m1 = { .min = 10, .max = 22 },
 160         .m2 = { .min = 5, .max = 9 },
 161         .p = { .min = 5, .max = 80 },
 162         .p1 = { .min = 1, .max = 8 },
 163         .p2 = { .dot_limit = 200000,
 164                 .p2_slow = 10, .p2_fast = 5 },
 165         .find_pll = intel_find_best_PLL,
 166 };
 167
 168 static const intel_limit_t intel_limits_i9xx_lvds = {
 169         .dot = { .min = 20000, .max = 400000 },
 170         .vco = { .min = 1400000, .max = 2800000 },
 171         .n = { .min = 1, .max = 6 },
 172         .m = { .min = 70, .max = 120 },
 173         .m1 = { .min = 10, .max = 22 },
 174         .m2 = { .min = 5, .max = 9 },
 175         .p = { .min = 7, .max = 98 },
 176         .p1 = { .min = 1, .max = 8 },
 177         .p2 = { .dot_limit = 112000,
 178                 .p2_slow = 14, .p2_fast = 7 },
 179         .find_pll = intel_find_best_PLL,
 180 };
 181
 182
 183 static const intel_limit_t intel_limits_g4x_sdvo = {
 184         .dot = { .min = 25000, .max = 270000 },
 185         .vco = { .min = 1750000, .max = 3500000},
 186         .n = { .min = 1, .max = 4 },
 187         .m = { .min = 104, .max = 138 },
 188         .m1 = { .min = 17, .max = 23 },
 189         .m2 = { .min = 5, .max = 11 },
 190         .p = { .min = 10, .max = 30 },
 191         .p1 = { .min = 1, .max = 3},
 192         .p2 = { .dot_limit = 270000,
 193                 .p2_slow = 10,
 194                 .p2_fast = 10
 195         },
 196         .find_pll = intel_g4x_find_best_PLL,
 197 };
 198
 199 static const intel_limit_t intel_limits_g4x_hdmi = {
 200         .dot = { .min = 22000, .max = 400000 },
 201         .vco = { .min = 1750000, .max = 3500000},
 202         .n = { .min = 1, .max = 4 },
 203         .m = { .min = 104, .max = 138 },
 204         .m1 = { .min = 16, .max = 23 },
 205         .m2 = { .min = 5, .max = 11 },
 206         .p = { .min = 5, .max = 80 },
 207         .p1 = { .min = 1, .max = 8},
 208         .p2 = { .dot_limit = 165000,
 209                 .p2_slow = 10, .p2_fast = 5 },
 210         .find_pll = intel_g4x_find_best_PLL,
 211 };
 212
 213 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 214         .dot = { .min = 20000, .max = 115000 },
 215         .vco = { .min = 1750000, .max = 3500000 },
 216         .n = { .min = 1, .max = 3 },
 217         .m = { .min = 104, .max = 138 },
 218         .m1 = { .min = 17, .max = 23 },
 219         .m2 = { .min = 5, .max = 11 },
 220         .p = { .min = 28, .max = 112 },
 221         .p1 = { .min = 2, .max = 8 },
 222         .p2 = { .dot_limit = 0,
 223                 .p2_slow = 14, .p2_fast = 14
 224         },
 225         .find_pll = intel_g4x_find_best_PLL,
 226 };
 227
 228 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 229         .dot = { .min = 80000, .max = 224000 },
 230         .vco = { .min = 1750000, .max = 3500000 },
 231         .n = { .min = 1, .max = 3 },
 232         .m = { .min = 104, .max = 138 },
 233         .m1 = { .min = 17, .max = 23 },
 234         .m2 = { .min = 5, .max = 11 },
 235         .p = { .min = 14, .max = 42 },
 236         .p1 = { .min = 2, .max = 6 },
 237         .p2 = { .dot_limit = 0,
 238                 .p2_slow = 7, .p2_fast = 7
 239         },
 240         .find_pll = intel_g4x_find_best_PLL,
 241 };
 242
 243 static const intel_limit_t intel_limits_g4x_display_port = {
 244         .dot = { .min = 161670, .max = 227000 },
 245         .vco = { .min = 1750000, .max = 3500000},
 246         .n = { .min = 1, .max = 2 },
 247         .m = { .min = 97, .max = 108 },
 248         .m1 = { .min = 0x10, .max = 0x12 },
 249         .m2 = { .min = 0x05, .max = 0x06 },
 250         .p = { .min = 10, .max = 20 },
 251         .p1 = { .min = 1, .max = 2},
 252         .p2 = { .dot_limit = 0,
 253                 .p2_slow = 10, .p2_fast = 10 },
 254         .find_pll = intel_find_pll_g4x_dp,
 255 };
 256
 257 static const intel_limit_t intel_limits_pineview_sdvo = {
 258         .dot = { .min = 20000, .max = 400000},
 259         .vco = { .min = 1700000, .max = 3500000 },
 260         /* Pineview's Ncounter is a ring counter */
 261         .n = { .min = 3, .max = 6 },
 262         .m = { .min = 2, .max = 256 },
 263         /* Pineview only has one combined m divider, which we treat as m2. */
 264         .m1 = { .min = 0, .max = 0 },
 265         .m2 = { .min = 0, .max = 254 },
 266         .p = { .min = 5, .max = 80 },
 267         .p1 = { .min = 1, .max = 8 },
 268         .p2 = { .dot_limit = 200000,
 269                 .p2_slow = 10, .p2_fast = 5 },
 270         .find_pll = intel_find_best_PLL,
 271 };
 272
 273 static const intel_limit_t intel_limits_pineview_lvds = {
 274         .dot = { .min = 20000, .max = 400000 },
 275         .vco = { .min = 1700000, .max = 3500000 },
 276         .n = { .min = 3, .max = 6 },
 277         .m = { .min = 2, .max = 256 },
 278         .m1 = { .min = 0, .max = 0 },
 279         .m2 = { .min = 0, .max = 254 },
 280         .p = { .min = 7, .max = 112 },
 281         .p1 = { .min = 1, .max = 8 },
 282         .p2 = { .dot_limit = 112000,
 283                 .p2_slow = 14, .p2_fast = 14 },
 284         .find_pll = intel_find_best_PLL,
 285 };
 286
 287 /* Ironlake / Sandybridge
 288  *
 289  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 290  * the range value for them is (actual_value - 2).
 291  */
 292 static const intel_limit_t intel_limits_ironlake_dac = {
 293         .dot = { .min = 25000, .max = 350000 },
 294         .vco = { .min = 1760000, .max = 3510000 },
 295         .n = { .min = 1, .max = 5 },
 296         .m = { .min = 79, .max = 127 },
 297         .m1 = { .min = 12, .max = 22 },
 298         .m2 = { .min = 5, .max = 9 },
 299         .p = { .min = 5, .max = 80 },
 300         .p1 = { .min = 1, .max = 8 },
 301         .p2 = { .dot_limit = 225000,
 302                 .p2_slow = 10, .p2_fast = 5 },
 303         .find_pll = intel_g4x_find_best_PLL,
 304 };
 305
 306 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 307         .dot = { .min = 25000, .max = 350000 },
 308         .vco = { .min = 1760000, .max = 3510000 },
 309         .n = { .min = 1, .max = 3 },
 310         .m = { .min = 79, .max = 118 },
 311         .m1 = { .min = 12, .max = 22 },
 312         .m2 = { .min = 5, .max = 9 },
 313         .p = { .min = 28, .max = 112 },
 314         .p1 = { .min = 2, .max = 8 },
 315         .p2 = { .dot_limit = 225000,
 316                 .p2_slow = 14, .p2_fast = 14 },
 317         .find_pll = intel_g4x_find_best_PLL,
 318 };
 319
 320 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 321         .dot = { .min = 25000, .max = 350000 },
 322         .vco = { .min = 1760000, .max = 3510000 },
 323         .n = { .min = 1, .max = 3 },
 324         .m = { .min = 79, .max = 127 },
 325         .m1 = { .min = 12, .max = 22 },
 326         .m2 = { .min = 5, .max = 9 },
 327         .p = { .min = 14, .max = 56 },
 328         .p1 = { .min = 2, .max = 8 },
 329         .p2 = { .dot_limit = 225000,
 330                 .p2_slow = 7, .p2_fast = 7 },
 331         .find_pll = intel_g4x_find_best_PLL,
 332 };
 333
 334 /* LVDS 100mhz refclk limits. */
 335 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 336         .dot = { .min = 25000, .max = 350000 },
 337         .vco = { .min = 1760000, .max = 3510000 },
 338         .n = { .min = 1, .max = 2 },
 339         .m = { .min = 79, .max = 126 },
 340         .m1 = { .min = 12, .max = 22 },
 341         .m2 = { .min = 5, .max = 9 },
 342         .p = { .min = 28, .max = 112 },
 343         .p1 = { .min = 2, .max = 8 },
 344         .p2 = { .dot_limit = 225000,
 345                 .p2_slow = 14, .p2_fast = 14 },
 346         .find_pll = intel_g4x_find_best_PLL,
 347 };
 348
 349 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 350         .dot = { .min = 25000, .max = 350000 },
 351         .vco = { .min = 1760000, .max = 3510000 },
 352         .n = { .min = 1, .max = 3 },
 353         .m = { .min = 79, .max = 126 },
 354         .m1 = { .min = 12, .max = 22 },
 355         .m2 = { .min = 5, .max = 9 },
 356         .p = { .min = 14, .max = 42 },
 357         .p1 = { .min = 2, .max = 6 },
 358         .p2 = { .dot_limit = 225000,
 359                 .p2_slow = 7, .p2_fast = 7 },
 360         .find_pll = intel_g4x_find_best_PLL,
 361 };
 362
 363 static const intel_limit_t intel_limits_ironlake_display_port = {
 364         .dot = { .min = 25000, .max = 350000 },
 365         .vco = { .min = 1760000, .max = 3510000},
 366         .n = { .min = 1, .max = 2 },
 367         .m = { .min = 81, .max = 90 },
 368         .m1 = { .min = 12, .max = 22 },
 369         .m2 = { .min = 5, .max = 9 },
 370         .p = { .min = 10, .max = 20 },
 371         .p1 = { .min = 1, .max = 2},
 372         .p2 = { .dot_limit = 0,
 373                 .p2_slow = 10, .p2_fast = 10 },
 374         .find_pll = intel_find_pll_ironlake_dp,
 375 };
 376
 377 static const intel_limit_t intel_limits_vlv_dac = {
 378         .dot = { .min = 25000, .max = 270000 },
 379         .vco = { .min = 4000000, .max = 6000000 },
 380         .n = { .min = 1, .max = 7 },
 381         .m = { .min = 22, .max = 450 }, /* guess */
 382         .m1 = { .min = 2, .max = 3 },
 383         .m2 = { .min = 11, .max = 156 },
 384         .p = { .min = 10, .max = 30 },
 385         .p1 = { .min = 2, .max = 3 },
 386         .p2 = { .dot_limit = 270000,
 387                 .p2_slow = 2, .p2_fast = 20 },
 388         .find_pll = intel_vlv_find_best_pll,
 389 };
 390
 391 static const intel_limit_t intel_limits_vlv_hdmi = {
 392         .dot = { .min = 20000, .max = 165000 },
 393         .vco = { .min = 4000000, .max = 5994000},
 394         .n = { .min = 1, .max = 7 },
 395         .m = { .min = 60, .max = 300 }, /* guess */
 396         .m1 = { .min = 2, .max = 3 },
 397         .m2 = { .min = 11, .max = 156 },
 398         .p = { .min = 10, .max = 30 },
 399         .p1 = { .min = 2, .max = 3 },
 400         .p2 = { .dot_limit = 270000,
 401                 .p2_slow = 2, .p2_fast = 20 },
 402         .find_pll = intel_vlv_find_best_pll,
 403 };
 404
 405 static const intel_limit_t intel_limits_vlv_dp = {
 406         .dot = { .min = 25000, .max = 270000 },
 407         .vco = { .min = 4000000, .max = 6000000 },
 408         .n = { .min = 1, .max = 7 },
 409         .m = { .min = 22, .max = 450 },
 410         .m1 = { .min = 2, .max = 3 },
 411         .m2 = { .min = 11, .max = 156 },
 412         .p = { .min = 10, .max = 30 },
 413         .p1 = { .min = 2, .max = 3 },
 414         .p2 = { .dot_limit = 270000,
 415                 .p2_slow = 2, .p2_fast = 20 },
 416         .find_pll = intel_vlv_find_best_pll,
 417 };
 418
 419 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
 420 {
 421         unsigned long flags;
 422         u32 val = 0;
 423
 424         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
 425         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 426                 DRM_ERROR("DPIO idle wait timed out\n");
 427                 goto out_unlock;
 428         }
 429
 430         I915_WRITE(DPIO_REG, reg);
 431         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
 432                    DPIO_BYTE);
 433         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 434                 DRM_ERROR("DPIO read wait timed out\n");
 435                 goto out_unlock;
 436         }
 437         val = I915_READ(DPIO_DATA);
 438
 439 out_unlock:
 440         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
 441         return val;
 442 }
 443
 444 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
 445                              u32 val)
 446 {
 447         unsigned long flags;
 448
 449         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
 450         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 451                 DRM_ERROR("DPIO idle wait timed out\n");
 452                 goto out_unlock;
 453         }
 454
 455         I915_WRITE(DPIO_DATA, val);
 456         I915_WRITE(DPIO_REG, reg);
 457         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
 458                    DPIO_BYTE);
 459         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
 460                 DRM_ERROR("DPIO write wait timed out\n");
 461
 462 out_unlock:
 463        spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
 464 }
 465
 466 static void vlv_init_dpio(struct drm_device *dev)
 467 {
 468         struct drm_i915_private *dev_priv = dev->dev_private;
 469
 470         /* Reset the DPIO config */
 471         I915_WRITE(DPIO_CTL, 0);
 472         POSTING_READ(DPIO_CTL);
 473         I915_WRITE(DPIO_CTL, 1);
 474         POSTING_READ(DPIO_CTL);
 475 }
 476
 477 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
 478 {
 479         DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
 480         return 1;
 481 }
 482
 483 static const struct dmi_system_id intel_dual_link_lvds[] = {
 484         {
 485                 .callback = intel_dual_link_lvds_callback,
 486                 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
 487                 .matches = {
 488                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 489                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
 490                 },
 491         },
 492         { }     /* terminating entry */
 493 };
 494
 495 static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
 496                               unsigned int reg)
 497 {
 498         unsigned int val;
 499
 500         /* use the module option value if specified */
 501         if (i915_lvds_channel_mode > 0)
 502                 return i915_lvds_channel_mode == 2;
 503
 504         if (dmi_check_system(intel_dual_link_lvds))
 505                 return true;
 506
 507         if (dev_priv->lvds_val)
 508                 val = dev_priv->lvds_val;
 509         else {
 510                 /* BIOS should set the proper LVDS register value at boot, but
 511                  * in reality, it doesn't set the value when the lid is closed;
 512                  * we need to check "the value to be set" in VBT when LVDS
 513                  * register is uninitialized.
 514                  */
 515                 val = I915_READ(reg);
 516                 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
 517                         val = dev_priv->bios_lvds_val;
 518                 dev_priv->lvds_val = val;
 519         }
 520         return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
 521 }
 522
 523 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 524                                                 int refclk)
 525 {
 526         struct drm_device *dev = crtc->dev;
 527         struct drm_i915_private *dev_priv = dev->dev_private;
 528         const intel_limit_t *limit;
 529
 530         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 531                 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
 532                         /* LVDS dual channel */
 533                         if (refclk == 100000)
 534                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 535                         else
 536                                 limit = &intel_limits_ironlake_dual_lvds;
 537                 } else {
 538                         if (refclk == 100000)
 539                                 limit = &intel_limits_ironlake_single_lvds_100m;
 540                         else
 541                                 limit = &intel_limits_ironlake_single_lvds;
 542                 }
 543         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 544                         HAS_eDP)
 545                 limit = &intel_limits_ironlake_display_port;
 546         else
 547                 limit = &intel_limits_ironlake_dac;
 548
 549         return limit;
 550 }
 551
 552 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 553 {
 554         struct drm_device *dev = crtc->dev;
 555         struct drm_i915_private *dev_priv = dev->dev_private;
 556         const intel_limit_t *limit;
 557
 558         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 559                 if (is_dual_link_lvds(dev_priv, LVDS))
 560                         /* LVDS with dual channel */
 561                         limit = &intel_limits_g4x_dual_channel_lvds;
 562                 else
 563                         /* LVDS with dual channel */
 564                         limit = &intel_limits_g4x_single_channel_lvds;
 565         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 566                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 567                 limit = &intel_limits_g4x_hdmi;
 568         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 569                 limit = &intel_limits_g4x_sdvo;
 570         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 571                 limit = &intel_limits_g4x_display_port;
 572         } else /* The option is for other outputs */
 573                 limit = &intel_limits_i9xx_sdvo;
 574
 575         return limit;
 576 }
 577
 578 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 579 {
 580         struct drm_device *dev = crtc->dev;
 581         const intel_limit_t *limit;
 582
 583         if (HAS_PCH_SPLIT(dev))
 584                 limit = intel_ironlake_limit(crtc, refclk);
 585         else if (IS_G4X(dev)) {
 586                 limit = intel_g4x_limit(crtc);
 587         } else if (IS_PINEVIEW(dev)) {
 588                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 589                         limit = &intel_limits_pineview_lvds;
 590                 else
 591                         limit = &intel_limits_pineview_sdvo;
 592         } else if (IS_VALLEYVIEW(dev)) {
 593                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
 594                         limit = &intel_limits_vlv_dac;
 595                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
 596                         limit = &intel_limits_vlv_hdmi;
 597                 else
 598                         limit = &intel_limits_vlv_dp;
 599         } else if (!IS_GEN2(dev)) {
 600                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 601                         limit = &intel_limits_i9xx_lvds;
 602                 else
 603                         limit = &intel_limits_i9xx_sdvo;
 604         } else {
 605                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 606                         limit = &intel_limits_i8xx_lvds;
 607                 else
 608                         limit = &intel_limits_i8xx_dvo;
 609         }
 610         return limit;
 611 }
 612
 613 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 614 static void pineview_clock(int refclk, intel_clock_t *clock)
 615 {
 616         clock->m = clock->m2 + 2;
 617         clock->p = clock->p1 * clock->p2;
 618         clock->vco = refclk * clock->m / clock->n;
 619         clock->dot = clock->vco / clock->p;
 620 }
 621
 622 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 623 {
 624         if (IS_PINEVIEW(dev)) {
 625                 pineview_clock(refclk, clock);
 626                 return;
 627         }
 628         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 629         clock->p = clock->p1 * clock->p2;
 630         clock->vco = refclk * clock->m / (clock->n + 2);
 631         clock->dot = clock->vco / clock->p;
 632 }
 633
 634 /**
 635  * Returns whether any output on the specified pipe is of the specified type
 636  */
 637 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 638 {
 639         struct drm_device *dev = crtc->dev;
 640         struct intel_encoder *encoder;
 641
 642         for_each_encoder_on_crtc(dev, crtc, encoder)
 643                 if (encoder->type == type)
 644                         return true;
 645
 646         return false;
 647 }
 648
 649 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 650 /**
 651  * Returns whether the given set of divisors are valid for a given refclk with
 652  * the given connectors.
 653  */
 654
 655 static bool intel_PLL_is_valid(struct drm_device *dev,
 656                                const intel_limit_t *limit,
 657                                const intel_clock_t *clock)
 658 {
 659         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 660                 INTELPllInvalid("p1 out of range\n");
 661         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 662                 INTELPllInvalid("p out of range\n");
 663         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 664                 INTELPllInvalid("m2 out of range\n");
 665         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 666                 INTELPllInvalid("m1 out of range\n");
 667         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 668                 INTELPllInvalid("m1 <= m2\n");
 669         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 670                 INTELPllInvalid("m out of range\n");
 671         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 672                 INTELPllInvalid("n out of range\n");
 673         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 674                 INTELPllInvalid("vco out of range\n");
 675         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 676          * connector, etc., rather than just a single range.
 677          */
 678         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 679                 INTELPllInvalid("dot out of range\n");
 680
 681         return true;
 682 }
 683
 684 static bool
 685 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 686                     int target, int refclk, intel_clock_t *match_clock,
 687                     intel_clock_t *best_clock)
 688
 689 {
 690         struct drm_device *dev = crtc->dev;
 691         struct drm_i915_private *dev_priv = dev->dev_private;
 692         intel_clock_t clock;
 693         int err = target;
 694
 695         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 696             (I915_READ(LVDS)) != 0) {
 697                 /*
 698                  * For LVDS, if the panel is on, just rely on its current
 699                  * settings for dual-channel.  We haven't figured out how to
 700                  * reliably set up different single/dual channel state, if we
 701                  * even can.
 702                  */
 703                 if (is_dual_link_lvds(dev_priv, LVDS))
 704                         clock.p2 = limit->p2.p2_fast;
 705                 else
 706                         clock.p2 = limit->p2.p2_slow;
 707         } else {
 708                 if (target < limit->p2.dot_limit)
 709                         clock.p2 = limit->p2.p2_slow;
 710                 else
 711                         clock.p2 = limit->p2.p2_fast;
 712         }
 713
 714         memset(best_clock, 0, sizeof(*best_clock));
 715
 716         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 717              clock.m1++) {
 718                 for (clock.m2 = limit->m2.min;
 719                      clock.m2 <= limit->m2.max; clock.m2++) {
 720                         /* m1 is always 0 in Pineview */
 721                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 722                                 break;
 723                         for (clock.n = limit->n.min;
 724                              clock.n <= limit->n.max; clock.n++) {
 725                                 for (clock.p1 = limit->p1.min;
 726                                         clock.p1 <= limit->p1.max; clock.p1++) {
 727                                         int this_err;
 728
 729                                         intel_clock(dev, refclk, &clock);
 730                                         if (!intel_PLL_is_valid(dev, limit,
 731                                                                 &clock))
 732                                                 continue;
 733                                         if (match_clock &&
 734                                             clock.p != match_clock->p)
 735                                                 continue;
 736
 737                                         this_err = abs(clock.dot - target);
 738                                         if (this_err < err) {
 739                                                 *best_clock = clock;
 740                                                 err = this_err;
 741                                         }
 742                                 }
 743                         }
 744                 }
 745         }
 746
 747         return (err != target);
 748 }
 749
 750 static bool
 751 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 752                         int target, int refclk, intel_clock_t *match_clock,
 753                         intel_clock_t *best_clock)
 754 {
 755         struct drm_device *dev = crtc->dev;
 756         struct drm_i915_private *dev_priv = dev->dev_private;
 757         intel_clock_t clock;
 758         int max_n;
 759         bool found;
 760         /* approximately equals target * 0.00585 */
 761         int err_most = (target >> 8) + (target >> 9);
 762         found = false;
 763
 764         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 765                 int lvds_reg;
 766
 767                 if (HAS_PCH_SPLIT(dev))
 768                         lvds_reg = PCH_LVDS;
 769                 else
 770                         lvds_reg = LVDS;
 771                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 772                     LVDS_CLKB_POWER_UP)
 773                         clock.p2 = limit->p2.p2_fast;
 774                 else
 775                         clock.p2 = limit->p2.p2_slow;
 776         } else {
 777                 if (target < limit->p2.dot_limit)
 778                         clock.p2 = limit->p2.p2_slow;
 779                 else
 780                         clock.p2 = limit->p2.p2_fast;
 781         }
 782
 783         memset(best_clock, 0, sizeof(*best_clock));
 784         max_n = limit->n.max;
 785         /* based on hardware requirement, prefer smaller n to precision */
 786         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 787                 /* based on hardware requirement, prefere larger m1,m2 */
 788                 for (clock.m1 = limit->m1.max;
 789                      clock.m1 >= limit->m1.min; clock.m1--) {
 790                         for (clock.m2 = limit->m2.max;
 791                              clock.m2 >= limit->m2.min; clock.m2--) {
 792                                 for (clock.p1 = limit->p1.max;
 793                                      clock.p1 >= limit->p1.min; clock.p1--) {
 794                                         int this_err;
 795
 796                                         intel_clock(dev, refclk, &clock);
 797                                         if (!intel_PLL_is_valid(dev, limit,
 798                                                                 &clock))
 799                                                 continue;
 800                                         if (match_clock &&
 801                                             clock.p != match_clock->p)
 802                                                 continue;
 803
 804                                         this_err = abs(clock.dot - target);
 805                                         if (this_err < err_most) {
 806                                                 *best_clock = clock;
 807                                                 err_most = this_err;
 808                                                 max_n = clock.n;
 809                                                 found = true;
 810                                         }
 811                                 }
 812                         }
 813                 }
 814         }
 815         return found;
 816 }
 817
 818 static bool
 819 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 820                            int target, int refclk, intel_clock_t *match_clock,
 821                            intel_clock_t *best_clock)
 822 {
 823         struct drm_device *dev = crtc->dev;
 824         intel_clock_t clock;
 825
 826         if (target < 200000) {
 827                 clock.n = 1;
 828                 clock.p1 = 2;
 829                 clock.p2 = 10;
 830                 clock.m1 = 12;
 831                 clock.m2 = 9;
 832         } else {
 833                 clock.n = 2;
 834                 clock.p1 = 1;
 835                 clock.p2 = 10;
 836                 clock.m1 = 14;
 837                 clock.m2 = 8;
 838         }
 839         intel_clock(dev, refclk, &clock);
 840         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 841         return true;
 842 }
 843
 844 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 845 static bool
 846 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 847                       int target, int refclk, intel_clock_t *match_clock,
 848                       intel_clock_t *best_clock)
 849 {
 850         intel_clock_t clock;
 851         if (target < 200000) {
 852                 clock.p1 = 2;
 853                 clock.p2 = 10;
 854                 clock.n = 2;
 855                 clock.m1 = 23;
 856                 clock.m2 = 8;
 857         } else {
 858                 clock.p1 = 1;
 859                 clock.p2 = 10;
 860                 clock.n = 1;
 861                 clock.m1 = 14;
 862                 clock.m2 = 2;
 863         }
 864         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 865         clock.p = (clock.p1 * clock.p2);
 866         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 867         clock.vco = 0;
 868         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 869         return true;
 870 }
 871 static bool
 872 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 873                         int target, int refclk, intel_clock_t *match_clock,
 874                         intel_clock_t *best_clock)
 875 {
 876         u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
 877         u32 m, n, fastclk;
 878         u32 updrate, minupdate, fracbits, p;
 879         unsigned long bestppm, ppm, absppm;
 880         int dotclk, flag;
 881
 882         flag = 0;
 883         dotclk = target * 1000;
 884         bestppm = 1000000;
 885         ppm = absppm = 0;
 886         fastclk = dotclk / (2*100);
 887         updrate = 0;
 888         minupdate = 19200;
 889         fracbits = 1;
 890         n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
 891         bestm1 = bestm2 = bestp1 = bestp2 = 0;
 892
 893         /* based on hardware requirement, prefer smaller n to precision */
 894         for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
 895                 updrate = refclk / n;
 896                 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
 897                         for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
 898                                 if (p2 > 10)
 899                                         p2 = p2 - 1;
 900                                 p = p1 * p2;
 901                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 902                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
 903                                         m2 = (((2*(fastclk * p * n / m1 )) +
 904                                                refclk) / (2*refclk));
 905                                         m = m1 * m2;
 906                                         vco = updrate * m;
 907                                         if (vco >= limit->vco.min && vco < limit->vco.max) {
 908                                                 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
 909                                                 absppm = (ppm > 0) ? ppm : (-ppm);
 910                                                 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
 911                                                         bestppm = 0;
 912                                                         flag = 1;
 913                                                 }
 914                                                 if (absppm < bestppm - 10) {
 915                                                         bestppm = absppm;
 916                                                         flag = 1;
 917                                                 }
 918                                                 if (flag) {
 919                                                         bestn = n;
 920                                                         bestm1 = m1;
 921                                                         bestm2 = m2;
 922                                                         bestp1 = p1;
 923                                                         bestp2 = p2;
 924                                                         flag = 0;
 925                                                 }
 926                                         }
 927                                 }
 928                         }
 929                 }
 930         }
 931         best_clock->n = bestn;
 932         best_clock->m1 = bestm1;
 933         best_clock->m2 = bestm2;
 934         best_clock->p1 = bestp1;
 935         best_clock->p2 = bestp2;
 936
 937         return true;
 938 }
 939
 940 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 941                                              enum pipe pipe)
 942 {
 943         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 944         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 945
 946         return intel_crtc->cpu_transcoder;
 947 }
 948
 949 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 950 {
 951         struct drm_i915_private *dev_priv = dev->dev_private;
 952         u32 frame, frame_reg = PIPEFRAME(pipe);
 953
 954         frame = I915_READ(frame_reg);
 955
 956         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 957                 DRM_DEBUG_KMS("vblank wait timed out\n");
 958 }
 959
 960 /**
 961  * intel_wait_for_vblank - wait for vblank on a given pipe
 962  * @dev: drm device
 963  * @pipe: pipe to wait for
 964  *
 965  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 966  * mode setting code.
 967  */
 968 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 969 {
 970         struct drm_i915_private *dev_priv = dev->dev_private;
 971         int pipestat_reg = PIPESTAT(pipe);
 972
 973         if (INTEL_INFO(dev)->gen >= 5) {
 974                 ironlake_wait_for_vblank(dev, pipe);
 975                 return;
 976         }
 977
 978         /* Clear existing vblank status. Note this will clear any other
 979          * sticky status fields as well.
 980          *
 981          * This races with i915_driver_irq_handler() with the result
 982          * that either function could miss a vblank event.  Here it is not
 983          * fatal, as we will either wait upon the next vblank interrupt or
 984          * timeout.  Generally speaking intel_wait_for_vblank() is only
 985          * called during modeset at which time the GPU should be idle and
 986          * should *not* be performing page flips and thus not waiting on
 987          * vblanks...
 988          * Currently, the result of us stealing a vblank from the irq
 989          * handler is that a single frame will be skipped during swapbuffers.
 990          */
 991         I915_WRITE(pipestat_reg,
 992                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 993
 994         /* Wait for vblank interrupt bit to set */
 995         if (wait_for(I915_READ(pipestat_reg) &
 996                      PIPE_VBLANK_INTERRUPT_STATUS,
 997                      50))
 998                 DRM_DEBUG_KMS("vblank wait timed out\n");
 999 }
1000
1001 /*
1002  * intel_wait_for_pipe_off - wait for pipe to turn off
1003  * @dev: drm device
1004  * @pipe: pipe to wait for
1005  *
1006  * After disabling a pipe, we can't wait for vblank in the usual way,
1007  * spinning on the vblank interrupt status bit, since we won't actually
1008  * see an interrupt when the pipe is disabled.
1009  *
1010  * On Gen4 and above:
1011  *   wait for the pipe register state bit to turn off
1012  *
1013  * Otherwise:
1014  *   wait for the display line value to settle (it usually
1015  *   ends up stopping at the start of the next frame).
1016  *
1017  */
1018 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1019 {
1020         struct drm_i915_private *dev_priv = dev->dev_private;
1021         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1022                                                                       pipe);
1023
1024         if (INTEL_INFO(dev)->gen >= 4) {
1025                 int reg = PIPECONF(cpu_transcoder);
1026
1027                 /* Wait for the Pipe State to go off */
1028                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1029                              100))
1030                         WARN(1, "pipe_off wait timed out\n");
1031         } else {
1032                 u32 last_line, line_mask;
1033                 int reg = PIPEDSL(pipe);
1034                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1035
1036                 if (IS_GEN2(dev))
1037                         line_mask = DSL_LINEMASK_GEN2;
1038                 else
1039                         line_mask = DSL_LINEMASK_GEN3;
1040
1041                 /* Wait for the display line to settle */
1042                 do {
1043                         last_line = I915_READ(reg) & line_mask;
1044                         mdelay(5);
1045                 } while (((I915_READ(reg) & line_mask) != last_line) &&
1046                          time_after(timeout, jiffies));
1047                 if (time_after(jiffies, timeout))
1048                         WARN(1, "pipe_off wait timed out\n");
1049         }
1050 }
1051
1052 static const char *state_string(bool enabled)
1053 {
1054         return enabled ? "on" : "off";
1055 }
1056
1057 /* Only for pre-ILK configs */
1058 static void assert_pll(struct drm_i915_private *dev_priv,
1059                        enum pipe pipe, bool state)
1060 {
1061         int reg;
1062         u32 val;
1063         bool cur_state;
1064
1065         reg = DPLL(pipe);
1066         val = I915_READ(reg);
1067         cur_state = !!(val & DPLL_VCO_ENABLE);
1068         WARN(cur_state != state,
1069              "PLL state assertion failure (expected %s, current %s)\n",
1070              state_string(state), state_string(cur_state));
1071 }
1072 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1073 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1074
1075 /* For ILK+ */
1076 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1077                            struct intel_pch_pll *pll,
1078                            struct intel_crtc *crtc,
1079                            bool state)
1080 {
1081         u32 val;
1082         bool cur_state;
1083
1084         if (HAS_PCH_LPT(dev_priv->dev)) {
1085                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1086                 return;
1087         }
1088
1089         if (WARN (!pll,
1090                   "asserting PCH PLL %s with no PLL\n", state_string(state)))
1091                 return;
1092
1093         val = I915_READ(pll->pll_reg);
1094         cur_state = !!(val & DPLL_VCO_ENABLE);
1095         WARN(cur_state != state,
1096              "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1097              pll->pll_reg, state_string(state), state_string(cur_state), val);
1098
1099         /* Make sure the selected PLL is correctly attached to the transcoder */
1100         if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
1101                 u32 pch_dpll;
1102
1103                 pch_dpll = I915_READ(PCH_DPLL_SEL);
1104                 cur_state = pll->pll_reg == _PCH_DPLL_B;
1105                 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1106                           "PLL[%d] not attached to this transcoder %d: %08x\n",
1107                           cur_state, crtc->pipe, pch_dpll)) {
1108                         cur_state = !!(val >> (4*crtc->pipe + 3));
1109                         WARN(cur_state != state,
1110                              "PLL[%d] not %s on this transcoder %d: %08x\n",
1111                              pll->pll_reg == _PCH_DPLL_B,
1112                              state_string(state),
1113                              crtc->pipe,
1114                              val);
1115                 }
1116         }
1117 }
1118 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1119 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1120
1121 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1122                           enum pipe pipe, bool state)
1123 {
1124         int reg;
1125         u32 val;
1126         bool cur_state;
1127         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1128                                                                       pipe);
1129
1130         if (IS_HASWELL(dev_priv->dev)) {
1131                 /* On Haswell, DDI is used instead of FDI_TX_CTL */
1132                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1133                 val = I915_READ(reg);
1134                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1135         } else {
1136                 reg = FDI_TX_CTL(pipe);
1137                 val = I915_READ(reg);
1138                 cur_state = !!(val & FDI_TX_ENABLE);
1139         }
1140         WARN(cur_state != state,
1141              "FDI TX state assertion failure (expected %s, current %s)\n",
1142              state_string(state), state_string(cur_state));
1143 }
1144 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1145 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1146
1147 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1148                           enum pipe pipe, bool state)
1149 {
1150         int reg;
1151         u32 val;
1152         bool cur_state;
1153
1154         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1155                         DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1156                         return;
1157         } else {
1158                 reg = FDI_RX_CTL(pipe);
1159                 val = I915_READ(reg);
1160                 cur_state = !!(val & FDI_RX_ENABLE);
1161         }
1162         WARN(cur_state != state,
1163              "FDI RX state assertion failure (expected %s, current %s)\n",
1164              state_string(state), state_string(cur_state));
1165 }
1166 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1167 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1168
1169 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1170                                       enum pipe pipe)
1171 {
1172         int reg;
1173         u32 val;
1174
1175         /* ILK FDI PLL is always enabled */
1176         if (dev_priv->info->gen == 5)
1177                 return;
1178
1179         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1180         if (IS_HASWELL(dev_priv->dev))
1181                 return;
1182
1183         reg = FDI_TX_CTL(pipe);
1184         val = I915_READ(reg);
1185         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1186 }
1187
1188 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1189                                       enum pipe pipe)
1190 {
1191         int reg;
1192         u32 val;
1193
1194         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1195                 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1196                 return;
1197         }
1198         reg = FDI_RX_CTL(pipe);
1199         val = I915_READ(reg);
1200         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1201 }
1202
1203 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1204                                   enum pipe pipe)
1205 {
1206         int pp_reg, lvds_reg;
1207         u32 val;
1208         enum pipe panel_pipe = PIPE_A;
1209         bool locked = true;
1210
1211         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1212                 pp_reg = PCH_PP_CONTROL;
1213                 lvds_reg = PCH_LVDS;
1214         } else {
1215                 pp_reg = PP_CONTROL;
1216                 lvds_reg = LVDS;
1217         }
1218
1219         val = I915_READ(pp_reg);
1220         if (!(val & PANEL_POWER_ON) ||
1221             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1222                 locked = false;
1223
1224         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1225                 panel_pipe = PIPE_B;
1226
1227         WARN(panel_pipe == pipe && locked,
1228              "panel assertion failure, pipe %c regs locked\n",
1229              pipe_name(pipe));
1230 }
1231
1232 void assert_pipe(struct drm_i915_private *dev_priv,
1233                  enum pipe pipe, bool state)
1234 {
1235         int reg;
1236         u32 val;
1237         bool cur_state;
1238         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1239                                                                       pipe);
1240
1241         /* if we need the pipe A quirk it must be always on */
1242         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1243                 state = true;
1244
1245         reg = PIPECONF(cpu_transcoder);
1246         val = I915_READ(reg);
1247         cur_state = !!(val & PIPECONF_ENABLE);
1248         WARN(cur_state != state,
1249              "pipe %c assertion failure (expected %s, current %s)\n",
1250              pipe_name(pipe), state_string(state), state_string(cur_state));
1251 }
1252
1253 static void assert_plane(struct drm_i915_private *dev_priv,
1254                          enum plane plane, bool state)
1255 {
1256         int reg;
1257         u32 val;
1258         bool cur_state;
1259
1260         reg = DSPCNTR(plane);
1261         val = I915_READ(reg);
1262         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1263         WARN(cur_state != state,
1264              "plane %c assertion failure (expected %s, current %s)\n",
1265              plane_name(plane), state_string(state), state_string(cur_state));
1266 }
1267
1268 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1269 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1270
1271 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1272                                    enum pipe pipe)
1273 {
1274         int reg, i;
1275         u32 val;
1276         int cur_pipe;
1277
1278         /* Planes are fixed to pipes on ILK+ */
1279         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1280                 reg = DSPCNTR(pipe);
1281                 val = I915_READ(reg);
1282                 WARN((val & DISPLAY_PLANE_ENABLE),
1283                      "plane %c assertion failure, should be disabled but not\n",
1284                      plane_name(pipe));
1285                 return;
1286         }
1287
1288         /* Need to check both planes against the pipe */
1289         for (i = 0; i < 2; i++) {
1290                 reg = DSPCNTR(i);
1291                 val = I915_READ(reg);
1292                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1293                         DISPPLANE_SEL_PIPE_SHIFT;
1294                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1295                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1296                      plane_name(i), pipe_name(pipe));
1297         }
1298 }
1299
1300 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1301 {
1302         u32 val;
1303         bool enabled;
1304
1305         if (HAS_PCH_LPT(dev_priv->dev)) {
1306                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1307                 return;
1308         }
1309
1310         val = I915_READ(PCH_DREF_CONTROL);
1311         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1312                             DREF_SUPERSPREAD_SOURCE_MASK));
1313         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1314 }
1315
1316 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1317                                        enum pipe pipe)
1318 {
1319         int reg;
1320         u32 val;
1321         bool enabled;
1322
1323         reg = TRANSCONF(pipe);
1324         val = I915_READ(reg);
1325         enabled = !!(val & TRANS_ENABLE);
1326         WARN(enabled,
1327              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1328              pipe_name(pipe));
1329 }
1330
1331 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1332                             enum pipe pipe, u32 port_sel, u32 val)
1333 {
1334         if ((val & DP_PORT_EN) == 0)
1335                 return false;
1336
1337         if (HAS_PCH_CPT(dev_priv->dev)) {
1338                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1339                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1340                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1341                         return false;
1342         } else {
1343                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1344                         return false;
1345         }
1346         return true;
1347 }
1348
1349 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1350                               enum pipe pipe, u32 val)
1351 {
1352         if ((val & PORT_ENABLE) == 0)
1353                 return false;
1354
1355         if (HAS_PCH_CPT(dev_priv->dev)) {
1356                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1357                         return false;
1358         } else {
1359                 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1360                         return false;
1361         }
1362         return true;
1363 }
1364
1365 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1366                               enum pipe pipe, u32 val)
1367 {
1368         if ((val & LVDS_PORT_EN) == 0)
1369                 return false;
1370
1371         if (HAS_PCH_CPT(dev_priv->dev)) {
1372                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1373                         return false;
1374         } else {
1375                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1376                         return false;
1377         }
1378         return true;
1379 }
1380
1381 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1382                               enum pipe pipe, u32 val)
1383 {
1384         if ((val & ADPA_DAC_ENABLE) == 0)
1385                 return false;
1386         if (HAS_PCH_CPT(dev_priv->dev)) {
1387                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1388                         return false;
1389         } else {
1390                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1391                         return false;
1392         }
1393         return true;
1394 }
1395
1396 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1397                                    enum pipe pipe, int reg, u32 port_sel)
1398 {
1399         u32 val = I915_READ(reg);
1400         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1401              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1402              reg, pipe_name(pipe));
1403
1404         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1405              && (val & DP_PIPEB_SELECT),
1406              "IBX PCH dp port still using transcoder B\n");
1407 }
1408
1409 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1410                                      enum pipe pipe, int reg)
1411 {
1412         u32 val = I915_READ(reg);
1413         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1414              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1415              reg, pipe_name(pipe));
1416
1417         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1418              && (val & SDVO_PIPE_B_SELECT),
1419              "IBX PCH hdmi port still using transcoder B\n");
1420 }
1421
1422 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1423                                       enum pipe pipe)
1424 {
1425         int reg;
1426         u32 val;
1427
1428         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1429         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1430         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1431
1432         reg = PCH_ADPA;
1433         val = I915_READ(reg);
1434         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1435              "PCH VGA enabled on transcoder %c, should be disabled\n",
1436              pipe_name(pipe));
1437
1438         reg = PCH_LVDS;
1439         val = I915_READ(reg);
1440         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1441              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1442              pipe_name(pipe));
1443
1444         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1445         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1446         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1447 }
1448
1449 /**
1450  * intel_enable_pll - enable a PLL
1451  * @dev_priv: i915 private structure
1452  * @pipe: pipe PLL to enable
1453  *
1454  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1455  * make sure the PLL reg is writable first though, since the panel write
1456  * protect mechanism may be enabled.
1457  *
1458  * Note!  This is for pre-ILK only.
1459  *
1460  * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1461  */
1462 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1463 {
1464         int reg;
1465         u32 val;
1466
1467         /* No really, not for ILK+ */
1468         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1469
1470         /* PLL is protected by panel, make sure we can write it */
1471         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1472                 assert_panel_unlocked(dev_priv, pipe);
1473
1474         reg = DPLL(pipe);
1475         val = I915_READ(reg);
1476         val |= DPLL_VCO_ENABLE;
1477
1478         /* We do this three times for luck */
1479         I915_WRITE(reg, val);
1480         POSTING_READ(reg);
1481         udelay(150); /* wait for warmup */
1482         I915_WRITE(reg, val);
1483         POSTING_READ(reg);
1484         udelay(150); /* wait for warmup */
1485         I915_WRITE(reg, val);
1486         POSTING_READ(reg);
1487         udelay(150); /* wait for warmup */
1488 }
1489
1490 /**
1491  * intel_disable_pll - disable a PLL
1492  * @dev_priv: i915 private structure
1493  * @pipe: pipe PLL to disable
1494  *
1495  * Disable the PLL for @pipe, making sure the pipe is off first.
1496  *
1497  * Note!  This is for pre-ILK only.
1498  */
1499 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1500 {
1501         int reg;
1502         u32 val;
1503
1504         /* Don't disable pipe A or pipe A PLLs if needed */
1505         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1506                 return;
1507
1508         /* Make sure the pipe isn't still relying on us */
1509         assert_pipe_disabled(dev_priv, pipe);
1510
1511         reg = DPLL(pipe);
1512         val = I915_READ(reg);
1513         val &= ~DPLL_VCO_ENABLE;
1514         I915_WRITE(reg, val);
1515         POSTING_READ(reg);
1516 }
1517
1518 /* SBI access */
1519 static void
1520 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1521 {
1522         unsigned long flags;
1523
1524         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1525         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1526                                 100)) {
1527                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1528                 goto out_unlock;
1529         }
1530
1531         I915_WRITE(SBI_ADDR,
1532                         (reg << 16));
1533         I915_WRITE(SBI_DATA,
1534                         value);
1535         I915_WRITE(SBI_CTL_STAT,
1536                         SBI_BUSY |
1537                         SBI_CTL_OP_CRWR);
1538
1539         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1540                                 100)) {
1541                 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1542                 goto out_unlock;
1543         }
1544
1545 out_unlock:
1546         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1547 }
1548
1549 static u32
1550 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1551 {
1552         unsigned long flags;
1553         u32 value = 0;
1554
1555         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1556         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1557                                 100)) {
1558                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1559                 goto out_unlock;
1560         }
1561
1562         I915_WRITE(SBI_ADDR,
1563                         (reg << 16));
1564         I915_WRITE(SBI_CTL_STAT,
1565                         SBI_BUSY |
1566                         SBI_CTL_OP_CRRD);
1567
1568         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1569                                 100)) {
1570                 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1571                 goto out_unlock;
1572         }
1573
1574         value = I915_READ(SBI_DATA);
1575
1576 out_unlock:
1577         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1578         return value;
1579 }
1580
1581 /**
1582  * intel_enable_pch_pll - enable PCH PLL
1583  * @dev_priv: i915 private structure
1584  * @pipe: pipe PLL to enable
1585  *
1586  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1587  * drives the transcoder clock.
1588  */
1589 static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
1590 {
1591         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1592         struct intel_pch_pll *pll;
1593         int reg;
1594         u32 val;
1595
1596         /* PCH PLLs only available on ILK, SNB and IVB */
1597         BUG_ON(dev_priv->info->gen < 5);
1598         pll = intel_crtc->pch_pll;
1599         if (pll == NULL)
1600                 return;
1601
1602         if (WARN_ON(pll->refcount == 0))
1603                 return;
1604
1605         DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1606                       pll->pll_reg, pll->active, pll->on,
1607                       intel_crtc->base.base.id);
1608
1609         /* PCH refclock must be enabled first */
1610         assert_pch_refclk_enabled(dev_priv);
1611
1612         if (pll->active++ && pll->on) {
1613                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1614                 return;
1615         }
1616
1617         DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1618
1619         reg = pll->pll_reg;
1620         val = I915_READ(reg);
1621         val |= DPLL_VCO_ENABLE;
1622         I915_WRITE(reg, val);
1623         POSTING_READ(reg);
1624         udelay(200);
1625
1626         pll->on = true;
1627 }
1628
1629 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1630 {
1631         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1632         struct intel_pch_pll *pll = intel_crtc->pch_pll;
1633         int reg;
1634         u32 val;
1635
1636         /* PCH only available on ILK+ */
1637         BUG_ON(dev_priv->info->gen < 5);
1638         if (pll == NULL)
1639                return;
1640
1641         if (WARN_ON(pll->refcount == 0))
1642                 return;
1643
1644         DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1645                       pll->pll_reg, pll->active, pll->on,
1646                       intel_crtc->base.base.id);
1647
1648         if (WARN_ON(pll->active == 0)) {
1649                 assert_pch_pll_disabled(dev_priv, pll, NULL);
1650                 return;
1651         }
1652
1653         if (--pll->active) {
1654                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1655                 return;
1656         }
1657
1658         DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1659
1660         /* Make sure transcoder isn't still depending on us */
1661         assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1662
1663         reg = pll->pll_reg;
1664         val = I915_READ(reg);
1665         val &= ~DPLL_VCO_ENABLE;
1666         I915_WRITE(reg, val);
1667         POSTING_READ(reg);
1668         udelay(200);
1669
1670         pll->on = false;
1671 }
1672
1673 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1674                                     enum pipe pipe)
1675 {
1676         int reg;
1677         u32 val, pipeconf_val;
1678         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1679
1680         /* PCH only available on ILK+ */
1681         BUG_ON(dev_priv->info->gen < 5);
1682
1683         /* Make sure PCH DPLL is enabled */
1684         assert_pch_pll_enabled(dev_priv,
1685                                to_intel_crtc(crtc)->pch_pll,
1686                                to_intel_crtc(crtc));
1687
1688         /* FDI must be feeding us bits for PCH ports */
1689         assert_fdi_tx_enabled(dev_priv, pipe);
1690         assert_fdi_rx_enabled(dev_priv, pipe);
1691
1692         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1693                 DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
1694                 return;
1695         }
1696         reg = TRANSCONF(pipe);
1697         val = I915_READ(reg);
1698         pipeconf_val = I915_READ(PIPECONF(pipe));
1699
1700         if (HAS_PCH_IBX(dev_priv->dev)) {
1701                 /*
1702                  * make the BPC in transcoder be consistent with
1703                  * that in pipeconf reg.
1704                  */
1705                 val &= ~PIPE_BPC_MASK;
1706                 val |= pipeconf_val & PIPE_BPC_MASK;
1707         }
1708
1709         val &= ~TRANS_INTERLACE_MASK;
1710         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1711                 if (HAS_PCH_IBX(dev_priv->dev) &&
1712                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1713                         val |= TRANS_LEGACY_INTERLACED_ILK;
1714                 else
1715                         val |= TRANS_INTERLACED;
1716         else
1717                 val |= TRANS_PROGRESSIVE;
1718
1719         I915_WRITE(reg, val | TRANS_ENABLE);
1720         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1721                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1722 }
1723
1724 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1725                                      enum pipe pipe)
1726 {
1727         int reg;
1728         u32 val;
1729
1730         /* FDI relies on the transcoder */
1731         assert_fdi_tx_disabled(dev_priv, pipe);
1732         assert_fdi_rx_disabled(dev_priv, pipe);
1733
1734         /* Ports must be off as well */
1735         assert_pch_ports_disabled(dev_priv, pipe);
1736
1737         reg = TRANSCONF(pipe);
1738         val = I915_READ(reg);
1739         val &= ~TRANS_ENABLE;
1740         I915_WRITE(reg, val);
1741         /* wait for PCH transcoder off, transcoder state */
1742         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1743                 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1744 }
1745
1746 /**
1747  * intel_enable_pipe - enable a pipe, asserting requirements
1748  * @dev_priv: i915 private structure
1749  * @pipe: pipe to enable
1750  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1751  *
1752  * Enable @pipe, making sure that various hardware specific requirements
1753  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1754  *
1755  * @pipe should be %PIPE_A or %PIPE_B.
1756  *
1757  * Will wait until the pipe is actually running (i.e. first vblank) before
1758  * returning.
1759  */
1760 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1761                               bool pch_port)
1762 {
1763         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1764                                                                       pipe);
1765         int reg;
1766         u32 val;
1767
1768         /*
1769          * A pipe without a PLL won't actually be able to drive bits from
1770          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1771          * need the check.
1772          */
1773         if (!HAS_PCH_SPLIT(dev_priv->dev))
1774                 assert_pll_enabled(dev_priv, pipe);
1775         else {
1776                 if (pch_port) {
1777                         /* if driving the PCH, we need FDI enabled */
1778                         assert_fdi_rx_pll_enabled(dev_priv, pipe);
1779                         assert_fdi_tx_pll_enabled(dev_priv, pipe);
1780                 }
1781                 /* FIXME: assert CPU port conditions for SNB+ */
1782         }
1783
1784         reg = PIPECONF(cpu_transcoder);
1785         val = I915_READ(reg);
1786         if (val & PIPECONF_ENABLE)
1787                 return;
1788
1789         I915_WRITE(reg, val | PIPECONF_ENABLE);
1790         intel_wait_for_vblank(dev_priv->dev, pipe);
1791 }
1792
1793 /**
1794  * intel_disable_pipe - disable a pipe, asserting requirements
1795  * @dev_priv: i915 private structure
1796  * @pipe: pipe to disable
1797  *
1798  * Disable @pipe, making sure that various hardware specific requirements
1799  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1800  *
1801  * @pipe should be %PIPE_A or %PIPE_B.
1802  *
1803  * Will wait until the pipe has shut down before returning.
1804  */
1805 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1806                                enum pipe pipe)
1807 {
1808         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1809                                                                       pipe);
1810         int reg;
1811         u32 val;
1812
1813         /*
1814          * Make sure planes won't keep trying to pump pixels to us,
1815          * or we might hang the display.
1816          */
1817         assert_planes_disabled(dev_priv, pipe);
1818
1819         /* Don't disable pipe A or pipe A PLLs if needed */
1820         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1821                 return;
1822
1823         reg = PIPECONF(cpu_transcoder);
1824         val = I915_READ(reg);
1825         if ((val & PIPECONF_ENABLE) == 0)
1826                 return;
1827
1828         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1829         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1830 }
1831
1832 /*
1833  * Plane regs are double buffered, going from enabled->disabled needs a
1834  * trigger in order to latch.  The display address reg provides this.
1835  */
1836 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1837                                       enum plane plane)
1838 {
1839         I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1840         I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1841 }
1842
1843 /**
1844  * intel_enable_plane - enable a display plane on a given pipe
1845  * @dev_priv: i915 private structure
1846  * @plane: plane to enable
1847  * @pipe: pipe being fed
1848  *
1849  * Enable @plane on @pipe, making sure that @pipe is running first.
1850  */
1851 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1852                                enum plane plane, enum pipe pipe)
1853 {
1854         int reg;
1855         u32 val;
1856
1857         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1858         assert_pipe_enabled(dev_priv, pipe);
1859
1860         reg = DSPCNTR(plane);
1861         val = I915_READ(reg);
1862         if (val & DISPLAY_PLANE_ENABLE)
1863                 return;
1864
1865         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1866         intel_flush_display_plane(dev_priv, plane);
1867         intel_wait_for_vblank(dev_priv->dev, pipe);
1868 }
1869
1870 /**
1871  * intel_disable_plane - disable a display plane
1872  * @dev_priv: i915 private structure
1873  * @plane: plane to disable
1874  * @pipe: pipe consuming the data
1875  *
1876  * Disable @plane; should be an independent operation.
1877  */
1878 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1879                                 enum plane plane, enum pipe pipe)
1880 {
1881         int reg;
1882         u32 val;
1883
1884         reg = DSPCNTR(plane);
1885         val = I915_READ(reg);
1886         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1887                 return;
1888
1889         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1890         intel_flush_display_plane(dev_priv, plane);
1891         intel_wait_for_vblank(dev_priv->dev, pipe);
1892 }
1893
1894 int
1895 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1896                            struct drm_i915_gem_object *obj,
1897                            struct intel_ring_buffer *pipelined)
1898 {
1899         struct drm_i915_private *dev_priv = dev->dev_private;
1900         u32 alignment;
1901         int ret;
1902
1903         switch (obj->tiling_mode) {
1904         case I915_TILING_NONE:
1905                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1906                         alignment = 128 * 1024;
1907                 else if (INTEL_INFO(dev)->gen >= 4)
1908                         alignment = 4 * 1024;
1909                 else
1910                         alignment = 64 * 1024;
1911                 break;
1912         case I915_TILING_X:
1913                 /* pin() will align the object as required by fence */
1914                 alignment = 0;
1915                 break;
1916         case I915_TILING_Y:
1917                 /* FIXME: Is this true? */
1918                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1919                 return -EINVAL;
1920         default:
1921                 BUG();
1922         }
1923
1924         dev_priv->mm.interruptible = false;
1925         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1926         if (ret)
1927                 goto err_interruptible;
1928
1929         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1930          * fence, whereas 965+ only requires a fence if using
1931          * framebuffer compression.  For simplicity, we always install
1932          * a fence as the cost is not that onerous.
1933          */
1934         ret = i915_gem_object_get_fence(obj);
1935         if (ret)
1936                 goto err_unpin;
1937
1938         i915_gem_object_pin_fence(obj);
1939
1940         dev_priv->mm.interruptible = true;
1941         return 0;
1942
1943 err_unpin:
1944         i915_gem_object_unpin(obj);
1945 err_interruptible:
1946         dev_priv->mm.interruptible = true;
1947         return ret;
1948 }
1949
1950 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1951 {
1952         i915_gem_object_unpin_fence(obj);
1953         i915_gem_object_unpin(obj);
1954 }
1955
1956 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1957  * is assumed to be a power-of-two. */
1958 static unsigned long gen4_compute_dspaddr_offset_xtiled(int *x, int *y,
1959                                                         unsigned int bpp,
1960                                                         unsigned int pitch)
1961 {
1962         int tile_rows, tiles;
1963
1964         tile_rows = *y / 8;
1965         *y %= 8;
1966         tiles = *x / (512/bpp);
1967         *x %= 512/bpp;
1968
1969         return tile_rows * pitch * 8 + tiles * 4096;
1970 }
1971
1972 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1973                              int x, int y)
1974 {
1975         struct drm_device *dev = crtc->dev;
1976         struct drm_i915_private *dev_priv = dev->dev_private;
1977         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1978         struct intel_framebuffer *intel_fb;
1979         struct drm_i915_gem_object *obj;
1980         int plane = intel_crtc->plane;
1981         unsigned long linear_offset;
1982         u32 dspcntr;
1983         u32 reg;
1984
1985         switch (plane) {
1986         case 0:
1987         case 1:
1988                 break;
1989         default:
1990                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1991                 return -EINVAL;
1992         }
1993
1994         intel_fb = to_intel_framebuffer(fb);
1995         obj = intel_fb->obj;
1996
1997         reg = DSPCNTR(plane);
1998         dspcntr = I915_READ(reg);
1999         /* Mask out pixel format bits in case we change it */
2000         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2001         switch (fb->bits_per_pixel) {
2002         case 8:
2003                 dspcntr |= DISPPLANE_8BPP;
2004                 break;
2005         case 16:
2006                 if (fb->depth == 15)
2007                         dspcntr |= DISPPLANE_15_16BPP;
2008                 else
2009                         dspcntr |= DISPPLANE_16BPP;
2010                 break;
2011         case 24:
2012         case 32:
2013                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2014                 break;
2015         default:
2016                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2017                 return -EINVAL;
2018         }
2019         if (INTEL_INFO(dev)->gen >= 4) {
2020                 if (obj->tiling_mode != I915_TILING_NONE)
2021                         dspcntr |= DISPPLANE_TILED;
2022                 else
2023                         dspcntr &= ~DISPPLANE_TILED;
2024         }
2025
2026         I915_WRITE(reg, dspcntr);
2027
2028         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2029
2030         if (INTEL_INFO(dev)->gen >= 4) {
2031                 intel_crtc->dspaddr_offset =
2032                         gen4_compute_dspaddr_offset_xtiled(&x, &y,
2033                                                            fb->bits_per_pixel / 8,
2034                                                            fb->pitches[0]);
2035                 linear_offset -= intel_crtc->dspaddr_offset;
2036         } else {
2037                 intel_crtc->dspaddr_offset = linear_offset;
2038         }
2039
2040         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2041                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2042         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2043         if (INTEL_INFO(dev)->gen >= 4) {
2044                 I915_MODIFY_DISPBASE(DSPSURF(plane),
2045                                      obj->gtt_offset + intel_crtc->dspaddr_offset);
2046                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2047                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2048         } else
2049                 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2050         POSTING_READ(reg);
2051
2052         return 0;
2053 }
2054
2055 static int ironlake_update_plane(struct drm_crtc *crtc,
2056                                  struct drm_framebuffer *fb, int x, int y)
2057 {
2058         struct drm_device *dev = crtc->dev;
2059         struct drm_i915_private *dev_priv = dev->dev_private;
2060         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2061         struct intel_framebuffer *intel_fb;
2062         struct drm_i915_gem_object *obj;
2063         int plane = intel_crtc->plane;
2064         unsigned long linear_offset;
2065         u32 dspcntr;
2066         u32 reg;
2067
2068         switch (plane) {
2069         case 0:
2070         case 1:
2071         case 2:
2072                 break;
2073         default:
2074                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2075                 return -EINVAL;
2076         }
2077
2078         intel_fb = to_intel_framebuffer(fb);
2079         obj = intel_fb->obj;
2080
2081         reg = DSPCNTR(plane);
2082         dspcntr = I915_READ(reg);
2083         /* Mask out pixel format bits in case we change it */
2084         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2085         switch (fb->bits_per_pixel) {
2086         case 8:
2087                 dspcntr |= DISPPLANE_8BPP;
2088                 break;
2089         case 16:
2090                 if (fb->depth != 16)
2091                         return -EINVAL;
2092
2093                 dspcntr |= DISPPLANE_16BPP;
2094                 break;
2095         case 24:
2096         case 32:
2097                 if (fb->depth == 24)
2098                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2099                 else if (fb->depth == 30)
2100                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2101                 else
2102                         return -EINVAL;
2103                 break;
2104         default:
2105                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2106                 return -EINVAL;
2107         }
2108
2109         if (obj->tiling_mode != I915_TILING_NONE)
2110                 dspcntr |= DISPPLANE_TILED;
2111         else
2112                 dspcntr &= ~DISPPLANE_TILED;
2113
2114         /* must disable */
2115         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2116
2117         I915_WRITE(reg, dspcntr);
2118
2119         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2120         intel_crtc->dspaddr_offset =
2121                 gen4_compute_dspaddr_offset_xtiled(&x, &y,
2122                                                    fb->bits_per_pixel / 8,
2123                                                    fb->pitches[0]);
2124         linear_offset -= intel_crtc->dspaddr_offset;
2125
2126         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2127                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2128         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2129         I915_MODIFY_DISPBASE(DSPSURF(plane),
2130                              obj->gtt_offset + intel_crtc->dspaddr_offset);
2131         I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2132         I915_WRITE(DSPLINOFF(plane), linear_offset);
2133         POSTING_READ(reg);
2134
2135         return 0;
2136 }
2137
2138 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2139 static int
2140 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2141                            int x, int y, enum mode_set_atomic state)
2142 {
2143         struct drm_device *dev = crtc->dev;
2144         struct drm_i915_private *dev_priv = dev->dev_private;
2145
2146         if (dev_priv->display.disable_fbc)
2147                 dev_priv->display.disable_fbc(dev);
2148         intel_increase_pllclock(crtc);
2149
2150         return dev_priv->display.update_plane(crtc, fb, x, y);
2151 }
2152
2153 static int
2154 intel_finish_fb(struct drm_framebuffer *old_fb)
2155 {
2156         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2157         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2158         bool was_interruptible = dev_priv->mm.interruptible;
2159         int ret;
2160
2161         wait_event(dev_priv->pending_flip_queue,
2162                    atomic_read(&dev_priv->mm.wedged) ||
2163                    atomic_read(&obj->pending_flip) == 0);
2164
2165         /* Big Hammer, we also need to ensure that any pending
2166          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2167          * current scanout is retired before unpinning the old
2168          * framebuffer.
2169          *
2170          * This should only fail upon a hung GPU, in which case we
2171          * can safely continue.
2172          */
2173         dev_priv->mm.interruptible = false;
2174         ret = i915_gem_object_finish_gpu(obj);
2175         dev_priv->mm.interruptible = was_interruptible;
2176
2177         return ret;
2178 }
2179
2180 static int
2181 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2182                     struct drm_framebuffer *fb)
2183 {
2184         struct drm_device *dev = crtc->dev;
2185         struct drm_i915_private *dev_priv = dev->dev_private;
2186         struct drm_i915_master_private *master_priv;
2187         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2188         struct drm_framebuffer *old_fb;
2189         int ret;
2190
2191         /* no fb bound */
2192         if (!fb) {
2193                 DRM_ERROR("No FB bound\n");
2194                 return 0;
2195         }
2196
2197         if(intel_crtc->plane > dev_priv->num_pipe) {
2198                 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2199                                 intel_crtc->plane,
2200                                 dev_priv->num_pipe);
2201                 return -EINVAL;
2202         }
2203
2204         mutex_lock(&dev->struct_mutex);
2205         ret = intel_pin_and_fence_fb_obj(dev,
2206                                          to_intel_framebuffer(fb)->obj,
2207                                          NULL);
2208         if (ret != 0) {
2209                 mutex_unlock(&dev->struct_mutex);
2210                 DRM_ERROR("pin & fence failed\n");
2211                 return ret;
2212         }
2213
2214         if (crtc->fb)
2215                 intel_finish_fb(crtc->fb);
2216
2217         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2218         if (ret) {
2219                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2220                 mutex_unlock(&dev->struct_mutex);
2221                 DRM_ERROR("failed to update base address\n");
2222                 return ret;
2223         }
2224
2225         old_fb = crtc->fb;
2226         crtc->fb = fb;
2227         crtc->x = x;
2228         crtc->y = y;
2229
2230         if (old_fb) {
2231                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2232                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2233         }
2234
2235         intel_update_fbc(dev);
2236         mutex_unlock(&dev->struct_mutex);
2237
2238         if (!dev->primary->master)
2239                 return 0;
2240
2241         master_priv = dev->primary->master->driver_priv;
2242         if (!master_priv->sarea_priv)
2243                 return 0;
2244
2245         if (intel_crtc->pipe) {
2246                 master_priv->sarea_priv->pipeB_x = x;
2247                 master_priv->sarea_priv->pipeB_y = y;
2248         } else {
2249                 master_priv->sarea_priv->pipeA_x = x;
2250                 master_priv->sarea_priv->pipeA_y = y;
2251         }
2252
2253         return 0;
2254 }
2255
2256 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2257 {
2258         struct drm_device *dev = crtc->dev;
2259         struct drm_i915_private *dev_priv = dev->dev_private;
2260         u32 dpa_ctl;
2261
2262         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2263         dpa_ctl = I915_READ(DP_A);
2264         dpa_ctl &= ~DP_PLL_FREQ_MASK;
2265
2266         if (clock < 200000) {
2267                 u32 temp;
2268                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2269                 /* workaround for 160Mhz:
2270                    1) program 0x4600c bits 15:0 = 0x8124
2271                    2) program 0x46010 bit 0 = 1
2272                    3) program 0x46034 bit 24 = 1
2273                    4) program 0x64000 bit 14 = 1
2274                    */
2275                 temp = I915_READ(0x4600c);
2276                 temp &= 0xffff0000;
2277                 I915_WRITE(0x4600c, temp | 0x8124);
2278
2279                 temp = I915_READ(0x46010);
2280                 I915_WRITE(0x46010, temp | 1);
2281
2282                 temp = I915_READ(0x46034);
2283                 I915_WRITE(0x46034, temp | (1 << 24));
2284         } else {
2285                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2286         }
2287         I915_WRITE(DP_A, dpa_ctl);
2288
2289         POSTING_READ(DP_A);
2290         udelay(500);
2291 }
2292
2293 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2294 {
2295         struct drm_device *dev = crtc->dev;
2296         struct drm_i915_private *dev_priv = dev->dev_private;
2297         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2298         int pipe = intel_crtc->pipe;
2299         u32 reg, temp;
2300
2301         /* enable normal train */
2302         reg = FDI_TX_CTL(pipe);
2303         temp = I915_READ(reg);
2304         if (IS_IVYBRIDGE(dev)) {
2305                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2306                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2307         } else {
2308                 temp &= ~FDI_LINK_TRAIN_NONE;
2309                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2310         }
2311         I915_WRITE(reg, temp);
2312
2313         reg = FDI_RX_CTL(pipe);
2314         temp = I915_READ(reg);
2315         if (HAS_PCH_CPT(dev)) {
2316                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2317                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2318         } else {
2319                 temp &= ~FDI_LINK_TRAIN_NONE;
2320                 temp |= FDI_LINK_TRAIN_NONE;
2321         }
2322         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2323
2324         /* wait one idle pattern time */
2325         POSTING_READ(reg);
2326         udelay(1000);
2327
2328         /* IVB wants error correction enabled */
2329         if (IS_IVYBRIDGE(dev))
2330                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2331                            FDI_FE_ERRC_ENABLE);
2332 }
2333
2334 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2335 {
2336         struct drm_i915_private *dev_priv = dev->dev_private;
2337         u32 flags = I915_READ(SOUTH_CHICKEN1);
2338
2339         flags |= FDI_PHASE_SYNC_OVR(pipe);
2340         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2341         flags |= FDI_PHASE_SYNC_EN(pipe);
2342         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2343         POSTING_READ(SOUTH_CHICKEN1);
2344 }
2345
2346 /* The FDI link training functions for ILK/Ibexpeak. */
2347 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2348 {
2349         struct drm_device *dev = crtc->dev;
2350         struct drm_i915_private *dev_priv = dev->dev_private;
2351         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2352         int pipe = intel_crtc->pipe;
2353         int plane = intel_crtc->plane;
2354         u32 reg, temp, tries;
2355
2356         /* FDI needs bits from pipe & plane first */
2357         assert_pipe_enabled(dev_priv, pipe);
2358         assert_plane_enabled(dev_priv, plane);
2359
2360         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2361            for train result */
2362         reg = FDI_RX_IMR(pipe);
2363         temp = I915_READ(reg);
2364         temp &= ~FDI_RX_SYMBOL_LOCK;
2365         temp &= ~FDI_RX_BIT_LOCK;
2366         I915_WRITE(reg, temp);
2367         I915_READ(reg);
2368         udelay(150);
2369
2370         /* enable CPU FDI TX and PCH FDI RX */
2371         reg = FDI_TX_CTL(pipe);
2372         temp = I915_READ(reg);
2373         temp &= ~(7 << 19);
2374         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2375         temp &= ~FDI_LINK_TRAIN_NONE;
2376         temp |= FDI_LINK_TRAIN_PATTERN_1;
2377         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2378
2379         reg = FDI_RX_CTL(pipe);
2380         temp = I915_READ(reg);
2381         temp &= ~FDI_LINK_TRAIN_NONE;
2382         temp |= FDI_LINK_TRAIN_PATTERN_1;
2383         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2384
2385         POSTING_READ(reg);
2386         udelay(150);
2387
2388         /* Ironlake workaround, enable clock pointer after FDI enable*/
2389         if (HAS_PCH_IBX(dev)) {
2390                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2391                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2392                            FDI_RX_PHASE_SYNC_POINTER_EN);
2393         }
2394
2395         reg = FDI_RX_IIR(pipe);
2396         for (tries = 0; tries < 5; tries++) {
2397                 temp = I915_READ(reg);
2398                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2399
2400                 if ((temp & FDI_RX_BIT_LOCK)) {
2401                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2402                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2403                         break;
2404                 }
2405         }
2406         if (tries == 5)
2407                 DRM_ERROR("FDI train 1 fail!\n");
2408
2409         /* Train 2 */
2410         reg = FDI_TX_CTL(pipe);
2411         temp = I915_READ(reg);
2412         temp &= ~FDI_LINK_TRAIN_NONE;
2413         temp |= FDI_LINK_TRAIN_PATTERN_2;
2414         I915_WRITE(reg, temp);
2415
2416         reg = FDI_RX_CTL(pipe);
2417         temp = I915_READ(reg);
2418         temp &= ~FDI_LINK_TRAIN_NONE;
2419         temp |= FDI_LINK_TRAIN_PATTERN_2;
2420         I915_WRITE(reg, temp);
2421
2422         POSTING_READ(reg);
2423         udelay(150);
2424
2425         reg = FDI_RX_IIR(pipe);
2426         for (tries = 0; tries < 5; tries++) {
2427                 temp = I915_READ(reg);
2428                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2429
2430                 if (temp & FDI_RX_SYMBOL_LOCK) {
2431                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2432                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2433                         break;
2434                 }
2435         }
2436         if (tries == 5)
2437                 DRM_ERROR("FDI train 2 fail!\n");
2438
2439         DRM_DEBUG_KMS("FDI train done\n");
2440
2441 }
2442
2443 static const int snb_b_fdi_train_param[] = {
2444         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2445         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2446         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2447         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2448 };
2449
2450 /* The FDI link training functions for SNB/Cougarpoint. */
2451 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2452 {
2453         struct drm_device *dev = crtc->dev;
2454         struct drm_i915_private *dev_priv = dev->dev_private;
2455         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2456         int pipe = intel_crtc->pipe;
2457         u32 reg, temp, i, retry;
2458
2459         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2460            for train result */
2461         reg = FDI_RX_IMR(pipe);
2462         temp = I915_READ(reg);
2463         temp &= ~FDI_RX_SYMBOL_LOCK;
2464         temp &= ~FDI_RX_BIT_LOCK;
2465         I915_WRITE(reg, temp);
2466
2467         POSTING_READ(reg);
2468         udelay(150);
2469
2470         /* enable CPU FDI TX and PCH FDI RX */
2471         reg = FDI_TX_CTL(pipe);
2472         temp = I915_READ(reg);
2473         temp &= ~(7 << 19);
2474         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2475         temp &= ~FDI_LINK_TRAIN_NONE;
2476         temp |= FDI_LINK_TRAIN_PATTERN_1;
2477         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2478         /* SNB-B */
2479         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2480         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2481
2482         reg = FDI_RX_CTL(pipe);
2483         temp = I915_READ(reg);
2484         if (HAS_PCH_CPT(dev)) {
2485                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2486                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2487         } else {
2488                 temp &= ~FDI_LINK_TRAIN_NONE;
2489                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2490         }
2491         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2492
2493         POSTING_READ(reg);
2494         udelay(150);
2495
2496         if (HAS_PCH_CPT(dev))
2497                 cpt_phase_pointer_enable(dev, pipe);
2498
2499         for (i = 0; i < 4; i++) {
2500                 reg = FDI_TX_CTL(pipe);
2501                 temp = I915_READ(reg);
2502                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2503                 temp |= snb_b_fdi_train_param[i];
2504                 I915_WRITE(reg, temp);
2505
2506                 POSTING_READ(reg);
2507                 udelay(500);
2508
2509                 for (retry = 0; retry < 5; retry++) {
2510                         reg = FDI_RX_IIR(pipe);
2511                         temp = I915_READ(reg);
2512                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2513                         if (temp & FDI_RX_BIT_LOCK) {
2514                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2515                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2516                                 break;
2517                         }
2518                         udelay(50);
2519                 }
2520                 if (retry < 5)
2521                         break;
2522         }
2523         if (i == 4)
2524                 DRM_ERROR("FDI train 1 fail!\n");
2525
2526         /* Train 2 */
2527         reg = FDI_TX_CTL(pipe);
2528         temp = I915_READ(reg);
2529         temp &= ~FDI_LINK_TRAIN_NONE;
2530         temp |= FDI_LINK_TRAIN_PATTERN_2;
2531         if (IS_GEN6(dev)) {
2532                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2533                 /* SNB-B */
2534                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2535         }
2536         I915_WRITE(reg, temp);
2537
2538         reg = FDI_RX_CTL(pipe);
2539         temp = I915_READ(reg);
2540         if (HAS_PCH_CPT(dev)) {
2541                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2542                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2543         } else {
2544                 temp &= ~FDI_LINK_TRAIN_NONE;
2545                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2546         }
2547         I915_WRITE(reg, temp);
2548
2549         POSTING_READ(reg);
2550         udelay(150);
2551
2552         for (i = 0; i < 4; i++) {
2553                 reg = FDI_TX_CTL(pipe);
2554                 temp = I915_READ(reg);
2555                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2556                 temp |= snb_b_fdi_train_param[i];
2557                 I915_WRITE(reg, temp);
2558
2559                 POSTING_READ(reg);
2560                 udelay(500);
2561
2562                 for (retry = 0; retry < 5; retry++) {
2563                         reg = FDI_RX_IIR(pipe);
2564                         temp = I915_READ(reg);
2565                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2566                         if (temp & FDI_RX_SYMBOL_LOCK) {
2567                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2568                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2569                                 break;
2570                         }
2571                         udelay(50);
2572                 }
2573                 if (retry < 5)
2574                         break;
2575         }
2576         if (i == 4)
2577                 DRM_ERROR("FDI train 2 fail!\n");
2578
2579         DRM_DEBUG_KMS("FDI train done.\n");
2580 }
2581
2582 /* Manual link training for Ivy Bridge A0 parts */
2583 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2584 {
2585         struct drm_device *dev = crtc->dev;
2586         struct drm_i915_private *dev_priv = dev->dev_private;
2587         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2588         int pipe = intel_crtc->pipe;
2589         u32 reg, temp, i;
2590
2591         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2592            for train result */
2593         reg = FDI_RX_IMR(pipe);
2594         temp = I915_READ(reg);
2595         temp &= ~FDI_RX_SYMBOL_LOCK;
2596         temp &= ~FDI_RX_BIT_LOCK;
2597         I915_WRITE(reg, temp);
2598
2599         POSTING_READ(reg);
2600         udelay(150);
2601
2602         /* enable CPU FDI TX and PCH FDI RX */
2603         reg = FDI_TX_CTL(pipe);
2604         temp = I915_READ(reg);
2605         temp &= ~(7 << 19);
2606         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2607         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2608         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2609         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2610         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2611         temp |= FDI_COMPOSITE_SYNC;
2612         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2613
2614         reg = FDI_RX_CTL(pipe);
2615         temp = I915_READ(reg);
2616         temp &= ~FDI_LINK_TRAIN_AUTO;
2617         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2618         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2619         temp |= FDI_COMPOSITE_SYNC;
2620         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2621
2622         POSTING_READ(reg);
2623         udelay(150);
2624
2625         if (HAS_PCH_CPT(dev))
2626                 cpt_phase_pointer_enable(dev, pipe);
2627
2628         for (i = 0; i < 4; i++) {
2629                 reg = FDI_TX_CTL(pipe);
2630                 temp = I915_READ(reg);
2631                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2632                 temp |= snb_b_fdi_train_param[i];
2633                 I915_WRITE(reg, temp);
2634
2635                 POSTING_READ(reg);
2636                 udelay(500);
2637
2638                 reg = FDI_RX_IIR(pipe);
2639                 temp = I915_READ(reg);
2640                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2641
2642                 if (temp & FDI_RX_BIT_LOCK ||
2643                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2644                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2645                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2646                         break;
2647                 }
2648         }
2649         if (i == 4)
2650                 DRM_ERROR("FDI train 1 fail!\n");
2651
2652         /* Train 2 */
2653         reg = FDI_TX_CTL(pipe);
2654         temp = I915_READ(reg);
2655         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2656         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2657         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2658         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2659         I915_WRITE(reg, temp);
2660
2661         reg = FDI_RX_CTL(pipe);
2662         temp = I915_READ(reg);
2663         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2664         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2665         I915_WRITE(reg, temp);
2666
2667         POSTING_READ(reg);
2668         udelay(150);
2669
2670         for (i = 0; i < 4; i++) {
2671                 reg = FDI_TX_CTL(pipe);
2672                 temp = I915_READ(reg);
2673                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2674                 temp |= snb_b_fdi_train_param[i];
2675                 I915_WRITE(reg, temp);
2676
2677                 POSTING_READ(reg);
2678                 udelay(500);
2679
2680                 reg = FDI_RX_IIR(pipe);
2681                 temp = I915_READ(reg);
2682                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2683
2684                 if (temp & FDI_RX_SYMBOL_LOCK) {
2685                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2686                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2687                         break;
2688                 }
2689         }
2690         if (i == 4)
2691                 DRM_ERROR("FDI train 2 fail!\n");
2692
2693         DRM_DEBUG_KMS("FDI train done.\n");
2694 }
2695
2696 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2697 {
2698         struct drm_device *dev = intel_crtc->base.dev;
2699         struct drm_i915_private *dev_priv = dev->dev_private;
2700         int pipe = intel_crtc->pipe;
2701         u32 reg, temp;
2702
2703
2704         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2705         reg = FDI_RX_CTL(pipe);
2706         temp = I915_READ(reg);
2707         temp &= ~((0x7 << 19) | (0x7 << 16));
2708         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2709         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2710         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2711
2712         POSTING_READ(reg);
2713         udelay(200);
2714
2715         /* Switch from Rawclk to PCDclk */
2716         temp = I915_READ(reg);
2717         I915_WRITE(reg, temp | FDI_PCDCLK);
2718
2719         POSTING_READ(reg);
2720         udelay(200);
2721
2722         /* On Haswell, the PLL configuration for ports and pipes is handled
2723          * separately, as part of DDI setup */
2724         if (!IS_HASWELL(dev)) {
2725                 /* Enable CPU FDI TX PLL, always on for Ironlake */
2726                 reg = FDI_TX_CTL(pipe);
2727                 temp = I915_READ(reg);
2728                 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2729                         I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2730
2731                         POSTING_READ(reg);
2732                         udelay(100);
2733                 }
2734         }
2735 }
2736
2737 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2738 {
2739         struct drm_device *dev = intel_crtc->base.dev;
2740         struct drm_i915_private *dev_priv = dev->dev_private;
2741         int pipe = intel_crtc->pipe;
2742         u32 reg, temp;
2743
2744         /* Switch from PCDclk to Rawclk */
2745         reg = FDI_RX_CTL(pipe);
2746         temp = I915_READ(reg);
2747         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2748
2749         /* Disable CPU FDI TX PLL */
2750         reg = FDI_TX_CTL(pipe);
2751         temp = I915_READ(reg);
2752         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2753
2754         POSTING_READ(reg);
2755         udelay(100);
2756
2757         reg = FDI_RX_CTL(pipe);
2758         temp = I915_READ(reg);
2759         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2760
2761         /* Wait for the clocks to turn off. */
2762         POSTING_READ(reg);
2763         udelay(100);
2764 }
2765
2766 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2767 {
2768         struct drm_i915_private *dev_priv = dev->dev_private;
2769         u32 flags = I915_READ(SOUTH_CHICKEN1);
2770
2771         flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2772         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2773         flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2774         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2775         POSTING_READ(SOUTH_CHICKEN1);
2776 }
2777 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2778 {
2779         struct drm_device *dev = crtc->dev;
2780         struct drm_i915_private *dev_priv = dev->dev_private;
2781         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2782         int pipe = intel_crtc->pipe;
2783         u32 reg, temp;
2784
2785         /* disable CPU FDI tx and PCH FDI rx */
2786         reg = FDI_TX_CTL(pipe);
2787         temp = I915_READ(reg);
2788         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2789         POSTING_READ(reg);
2790
2791         reg = FDI_RX_CTL(pipe);
2792         temp = I915_READ(reg);
2793         temp &= ~(0x7 << 16);
2794         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2795         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2796
2797         POSTING_READ(reg);
2798         udelay(100);
2799
2800         /* Ironlake workaround, disable clock pointer after downing FDI */
2801         if (HAS_PCH_IBX(dev)) {
2802                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2803                 I915_WRITE(FDI_RX_CHICKEN(pipe),
2804                            I915_READ(FDI_RX_CHICKEN(pipe) &
2805                                      ~FDI_RX_PHASE_SYNC_POINTER_EN));
2806         } else if (HAS_PCH_CPT(dev)) {
2807                 cpt_phase_pointer_disable(dev, pipe);
2808         }
2809
2810         /* still set train pattern 1 */
2811         reg = FDI_TX_CTL(pipe);
2812         temp = I915_READ(reg);
2813         temp &= ~FDI_LINK_TRAIN_NONE;
2814         temp |= FDI_LINK_TRAIN_PATTERN_1;
2815         I915_WRITE(reg, temp);
2816
2817         reg = FDI_RX_CTL(pipe);
2818         temp = I915_READ(reg);
2819         if (HAS_PCH_CPT(dev)) {
2820                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2821                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2822         } else {
2823                 temp &= ~FDI_LINK_TRAIN_NONE;
2824                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2825         }
2826         /* BPC in FDI rx is consistent with that in PIPECONF */
2827         temp &= ~(0x07 << 16);
2828         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2829         I915_WRITE(reg, temp);
2830
2831         POSTING_READ(reg);
2832         udelay(100);
2833 }
2834
2835 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2836 {
2837         struct drm_device *dev = crtc->dev;
2838         struct drm_i915_private *dev_priv = dev->dev_private;
2839         unsigned long flags;
2840         bool pending;
2841
2842         if (atomic_read(&dev_priv->mm.wedged))
2843                 return false;
2844
2845         spin_lock_irqsave(&dev->event_lock, flags);
2846         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2847         spin_unlock_irqrestore(&dev->event_lock, flags);
2848
2849         return pending;
2850 }
2851
2852 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2853 {
2854         struct drm_device *dev = crtc->dev;
2855         struct drm_i915_private *dev_priv = dev->dev_private;
2856
2857         if (crtc->fb == NULL)
2858                 return;
2859
2860         wait_event(dev_priv->pending_flip_queue,
2861                    !intel_crtc_has_pending_flip(crtc));
2862
2863         mutex_lock(&dev->struct_mutex);
2864         intel_finish_fb(crtc->fb);
2865         mutex_unlock(&dev->struct_mutex);
2866 }
2867
2868 static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
2869 {
2870         struct drm_device *dev = crtc->dev;
2871         struct intel_encoder *intel_encoder;
2872
2873         /*
2874          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2875          * must be driven by its own crtc; no sharing is possible.
2876          */
2877         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2878                 switch (intel_encoder->type) {
2879                 case INTEL_OUTPUT_EDP:
2880                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
2881                                 return false;
2882                         continue;
2883                 }
2884         }
2885
2886         return true;
2887 }
2888
2889 static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
2890 {
2891         return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
2892 }
2893
2894 /* Program iCLKIP clock to the desired frequency */
2895 static void lpt_program_iclkip(struct drm_crtc *crtc)
2896 {
2897         struct drm_device *dev = crtc->dev;
2898         struct drm_i915_private *dev_priv = dev->dev_private;
2899         u32 divsel, phaseinc, auxdiv, phasedir = 0;
2900         u32 temp;
2901
2902         /* It is necessary to ungate the pixclk gate prior to programming
2903          * the divisors, and gate it back when it is done.
2904          */
2905         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2906
2907         /* Disable SSCCTL */
2908         intel_sbi_write(dev_priv, SBI_SSCCTL6,
2909                                 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
2910                                         SBI_SSCCTL_DISABLE);
2911
2912         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2913         if (crtc->mode.clock == 20000) {
2914                 auxdiv = 1;
2915                 divsel = 0x41;
2916                 phaseinc = 0x20;
2917         } else {
2918                 /* The iCLK virtual clock root frequency is in MHz,
2919                  * but the crtc->mode.clock in in KHz. To get the divisors,
2920                  * it is necessary to divide one by another, so we
2921                  * convert the virtual clock precision to KHz here for higher
2922                  * precision.
2923                  */
2924                 u32 iclk_virtual_root_freq = 172800 * 1000;
2925                 u32 iclk_pi_range = 64;
2926                 u32 desired_divisor, msb_divisor_value, pi_value;
2927
2928                 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2929                 msb_divisor_value = desired_divisor / iclk_pi_range;
2930                 pi_value = desired_divisor % iclk_pi_range;
2931
2932                 auxdiv = 0;
2933                 divsel = msb_divisor_value - 2;
2934                 phaseinc = pi_value;
2935         }
2936
2937         /* This should not happen with any sane values */
2938         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2939                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2940         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2941                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2942
2943         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2944                         crtc->mode.clock,
2945                         auxdiv,
2946                         divsel,
2947                         phasedir,
2948                         phaseinc);
2949
2950         /* Program SSCDIVINTPHASE6 */
2951         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
2952         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2953         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2954         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2955         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2956         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2957         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2958
2959         intel_sbi_write(dev_priv,
2960                         SBI_SSCDIVINTPHASE6,
2961                         temp);
2962
2963         /* Program SSCAUXDIV */
2964         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
2965         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2966         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2967         intel_sbi_write(dev_priv,
2968                         SBI_SSCAUXDIV6,
2969                         temp);
2970
2971
2972         /* Enable modulator and associated divider */
2973         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
2974         temp &= ~SBI_SSCCTL_DISABLE;
2975         intel_sbi_write(dev_priv,
2976                         SBI_SSCCTL6,
2977                         temp);
2978
2979         /* Wait for initialization time */
2980         udelay(24);
2981
2982         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2983 }
2984
2985 /*
2986  * Enable PCH resources required for PCH ports:
2987  *   - PCH PLLs
2988  *   - FDI training & RX/TX
2989  *   - update transcoder timings
2990  *   - DP transcoding bits
2991  *   - transcoder
2992  */
2993 static void ironlake_pch_enable(struct drm_crtc *crtc)
2994 {
2995         struct drm_device *dev = crtc->dev;
2996         struct drm_i915_private *dev_priv = dev->dev_private;
2997         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2998         int pipe = intel_crtc->pipe;
2999         u32 reg, temp;
3000
3001         assert_transcoder_disabled(dev_priv, pipe);
3002
3003         /* Write the TU size bits before fdi link training, so that error
3004          * detection works. */
3005         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3006                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3007
3008         /* For PCH output, training FDI link */
3009         dev_priv->display.fdi_link_train(crtc);
3010
3011         intel_enable_pch_pll(intel_crtc);
3012
3013         if (HAS_PCH_LPT(dev)) {
3014                 DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
3015                 lpt_program_iclkip(crtc);
3016         } else if (HAS_PCH_CPT(dev)) {
3017                 u32 sel;
3018
3019                 temp = I915_READ(PCH_DPLL_SEL);
3020                 switch (pipe) {
3021                 default:
3022                 case 0:
3023                         temp |= TRANSA_DPLL_ENABLE;
3024                         sel = TRANSA_DPLLB_SEL;
3025                         break;
3026                 case 1:
3027                         temp |= TRANSB_DPLL_ENABLE;
3028                         sel = TRANSB_DPLLB_SEL;
3029                         break;
3030                 case 2:
3031                         temp |= TRANSC_DPLL_ENABLE;
3032                         sel = TRANSC_DPLLB_SEL;
3033                         break;
3034                 }
3035                 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3036                         temp |= sel;
3037                 else
3038                         temp &= ~sel;
3039                 I915_WRITE(PCH_DPLL_SEL, temp);
3040         }
3041
3042         /* set transcoder timing, panel must allow it */
3043         assert_panel_unlocked(dev_priv, pipe);
3044         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3045         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3046         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
3047
3048         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3049         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3050         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
3051         I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));
3052
3053         if (!IS_HASWELL(dev))
3054                 intel_fdi_normal_train(crtc);
3055
3056         /* For PCH DP, enable TRANS_DP_CTL */
3057         if (HAS_PCH_CPT(dev) &&
3058             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3059              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3060                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
3061                 reg = TRANS_DP_CTL(pipe);
3062                 temp = I915_READ(reg);
3063                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3064                           TRANS_DP_SYNC_MASK |
3065                           TRANS_DP_BPC_MASK);
3066                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3067                          TRANS_DP_ENH_FRAMING);
3068                 temp |= bpc << 9; /* same format but at 11:9 */
3069
3070                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3071                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3072                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3073                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3074
3075                 switch (intel_trans_dp_port_sel(crtc)) {
3076                 case PCH_DP_B:
3077                         temp |= TRANS_DP_PORT_SEL_B;
3078                         break;
3079                 case PCH_DP_C:
3080                         temp |= TRANS_DP_PORT_SEL_C;
3081                         break;
3082                 case PCH_DP_D:
3083                         temp |= TRANS_DP_PORT_SEL_D;
3084                         break;
3085                 default:
3086                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
3087                         temp |= TRANS_DP_PORT_SEL_B;
3088                         break;
3089                 }
3090
3091                 I915_WRITE(reg, temp);
3092         }
3093
3094         intel_enable_transcoder(dev_priv, pipe);
3095 }
3096
3097 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3098 {
3099         struct intel_pch_pll *pll = intel_crtc->pch_pll;
3100
3101         if (pll == NULL)
3102                 return;
3103
3104         if (pll->refcount == 0) {
3105                 WARN(1, "bad PCH PLL refcount\n");
3106                 return;
3107         }
3108
3109         --pll->refcount;
3110         intel_crtc->pch_pll = NULL;
3111 }
3112
3113 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3114 {
3115         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3116         struct intel_pch_pll *pll;
3117         int i;
3118
3119         pll = intel_crtc->pch_pll;
3120         if (pll) {
3121                 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3122                               intel_crtc->base.base.id, pll->pll_reg);
3123                 goto prepare;
3124         }
3125
3126         if (HAS_PCH_IBX(dev_priv->dev)) {
3127                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3128                 i = intel_crtc->pipe;
3129                 pll = &dev_priv->pch_plls[i];
3130
3131                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3132                               intel_crtc->base.base.id, pll->pll_reg);
3133
3134                 goto found;
3135         }
3136
3137         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3138                 pll = &dev_priv->pch_plls[i];
3139
3140                 /* Only want to check enabled timings first */
3141                 if (pll->refcount == 0)
3142                         continue;
3143
3144                 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3145                     fp == I915_READ(pll->fp0_reg)) {
3146                         DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3147                                       intel_crtc->base.base.id,
3148                                       pll->pll_reg, pll->refcount, pll->active);
3149
3150                         goto found;
3151                 }
3152         }
3153
3154         /* Ok no matching timings, maybe there's a free one? */
3155         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3156                 pll = &dev_priv->pch_plls[i];
3157                 if (pll->refcount == 0) {
3158                         DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3159                                       intel_crtc->base.base.id, pll->pll_reg);
3160                         goto found;
3161                 }
3162         }
3163
3164         return NULL;
3165
3166 found:
3167         intel_crtc->pch_pll = pll;
3168         pll->refcount++;
3169         DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3170 prepare: /* separate function? */
3171         DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3172
3173         /* Wait for the clocks to stabilize before rewriting the regs */
3174         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3175         POSTING_READ(pll->pll_reg);
3176         udelay(150);
3177
3178         I915_WRITE(pll->fp0_reg, fp);
3179         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3180         pll->on = false;
3181         return pll;
3182 }
3183
3184 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3185 {
3186         struct drm_i915_private *dev_priv = dev->dev_private;
3187         int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3188         u32 temp;
3189
3190         temp = I915_READ(dslreg);
3191         udelay(500);
3192         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3193                 /* Without this, mode sets may fail silently on FDI */
3194                 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3195                 udelay(250);
3196                 I915_WRITE(tc2reg, 0);
3197                 if (wait_for(I915_READ(dslreg) != temp, 5))
3198                         DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3199         }
3200 }
3201
3202 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3203 {
3204         struct drm_device *dev = crtc->dev;
3205         struct drm_i915_private *dev_priv = dev->dev_private;
3206         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3207         struct intel_encoder *encoder;
3208         int pipe = intel_crtc->pipe;
3209         int plane = intel_crtc->plane;
3210         u32 temp;
3211         bool is_pch_port;
3212
3213         WARN_ON(!crtc->enabled);
3214
3215         if (intel_crtc->active)
3216                 return;
3217
3218         intel_crtc->active = true;
3219         intel_update_watermarks(dev);
3220
3221         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3222                 temp = I915_READ(PCH_LVDS);
3223                 if ((temp & LVDS_PORT_EN) == 0)
3224                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3225         }
3226
3227         is_pch_port = ironlake_crtc_driving_pch(crtc);
3228
3229         if (is_pch_port) {
3230                 /* Note: FDI PLL enabling _must_ be done before we enable the
3231                  * cpu pipes, hence this is separate from all the other fdi/pch
3232                  * enabling. */
3233                 ironlake_fdi_pll_enable(intel_crtc);
3234         } else {
3235                 assert_fdi_tx_disabled(dev_priv, pipe);
3236                 assert_fdi_rx_disabled(dev_priv, pipe);
3237         }
3238
3239         for_each_encoder_on_crtc(dev, crtc, encoder)
3240                 if (encoder->pre_enable)
3241                         encoder->pre_enable(encoder);
3242
3243         /* Enable panel fitting for LVDS */
3244         if (dev_priv->pch_pf_size &&
3245             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3246                 /* Force use of hard-coded filter coefficients
3247                  * as some pre-programmed values are broken,
3248                  * e.g. x201.
3249                  */
3250                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3251                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3252                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3253         }
3254
3255         /*
3256          * On ILK+ LUT must be loaded before the pipe is running but with
3257          * clocks enabled
3258          */
3259         intel_crtc_load_lut(crtc);
3260
3261         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3262         intel_enable_plane(dev_priv, plane, pipe);
3263
3264         if (is_pch_port)
3265                 ironlake_pch_enable(crtc);
3266
3267         mutex_lock(&dev->struct_mutex);
3268         intel_update_fbc(dev);
3269         mutex_unlock(&dev->struct_mutex);
3270
3271         intel_crtc_update_cursor(crtc, true);
3272
3273         for_each_encoder_on_crtc(dev, crtc, encoder)
3274                 encoder->enable(encoder);
3275
3276         if (HAS_PCH_CPT(dev))
3277                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3278
3279         /*
3280          * There seems to be a race in PCH platform hw (at least on some
3281          * outputs) where an enabled pipe still completes any pageflip right
3282          * away (as if the pipe is off) instead of waiting for vblank. As soon
3283          * as the first vblank happend, everything works as expected. Hence just
3284          * wait for one vblank before returning to avoid strange things
3285          * happening.
3286          */
3287         intel_wait_for_vblank(dev, intel_crtc->pipe);
3288 }
3289
3290 static void haswell_crtc_enable(struct drm_crtc *crtc)
3291 {
3292         struct drm_device *dev = crtc->dev;
3293         struct drm_i915_private *dev_priv = dev->dev_private;
3294         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3295         struct intel_encoder *encoder;
3296         int pipe = intel_crtc->pipe;
3297         int plane = intel_crtc->plane;
3298         bool is_pch_port;
3299
3300         WARN_ON(!crtc->enabled);
3301
3302         if (intel_crtc->active)
3303                 return;
3304
3305         intel_crtc->active = true;
3306         intel_update_watermarks(dev);
3307
3308         is_pch_port = haswell_crtc_driving_pch(crtc);
3309
3310         if (is_pch_port)
3311                 ironlake_fdi_pll_enable(intel_crtc);
3312
3313         for_each_encoder_on_crtc(dev, crtc, encoder)
3314                 if (encoder->pre_enable)
3315                         encoder->pre_enable(encoder);
3316
3317         intel_ddi_enable_pipe_clock(intel_crtc);
3318
3319         /* Enable panel fitting for eDP */
3320         if (dev_priv->pch_pf_size && HAS_eDP) {
3321                 /* Force use of hard-coded filter coefficients
3322                  * as some pre-programmed values are broken,
3323                  * e.g. x201.
3324                  */
3325                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3326                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3327                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3328         }
3329
3330         /*
3331          * On ILK+ LUT must be loaded before the pipe is running but with
3332          * clocks enabled
3333          */
3334         intel_crtc_load_lut(crtc);
3335
3336         intel_ddi_set_pipe_settings(crtc);
3337         intel_ddi_enable_pipe_func(crtc);
3338
3339         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3340         intel_enable_plane(dev_priv, plane, pipe);
3341
3342         if (is_pch_port)
3343                 ironlake_pch_enable(crtc);
3344
3345         mutex_lock(&dev->struct_mutex);
3346         intel_update_fbc(dev);
3347         mutex_unlock(&dev->struct_mutex);
3348
3349         intel_crtc_update_cursor(crtc, true);
3350
3351         for_each_encoder_on_crtc(dev, crtc, encoder)
3352                 encoder->enable(encoder);
3353
3354         /*
3355          * There seems to be a race in PCH platform hw (at least on some
3356          * outputs) where an enabled pipe still completes any pageflip right
3357          * away (as if the pipe is off) instead of waiting for vblank. As soon
3358          * as the first vblank happend, everything works as expected. Hence just
3359          * wait for one vblank before returning to avoid strange things
3360          * happening.
3361          */
3362         intel_wait_for_vblank(dev, intel_crtc->pipe);
3363 }
3364
3365 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3366 {
3367         struct drm_device *dev = crtc->dev;
3368         struct drm_i915_private *dev_priv = dev->dev_private;
3369         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3370         struct intel_encoder *encoder;
3371         int pipe = intel_crtc->pipe;
3372         int plane = intel_crtc->plane;
3373         u32 reg, temp;
3374
3375
3376         if (!intel_crtc->active)
3377                 return;
3378
3379         for_each_encoder_on_crtc(dev, crtc, encoder)
3380                 encoder->disable(encoder);
3381
3382         intel_crtc_wait_for_pending_flips(crtc);
3383         drm_vblank_off(dev, pipe);
3384         intel_crtc_update_cursor(crtc, false);
3385
3386         intel_disable_plane(dev_priv, plane, pipe);
3387
3388         if (dev_priv->cfb_plane == plane)
3389                 intel_disable_fbc(dev);
3390
3391         intel_disable_pipe(dev_priv, pipe);
3392
3393         /* Disable PF */
3394         I915_WRITE(PF_CTL(pipe), 0);
3395         I915_WRITE(PF_WIN_SZ(pipe), 0);
3396
3397         for_each_encoder_on_crtc(dev, crtc, encoder)
3398                 if (encoder->post_disable)
3399                         encoder->post_disable(encoder);
3400
3401         ironlake_fdi_disable(crtc);
3402
3403         intel_disable_transcoder(dev_priv, pipe);
3404
3405         if (HAS_PCH_CPT(dev)) {
3406                 /* disable TRANS_DP_CTL */
3407                 reg = TRANS_DP_CTL(pipe);
3408                 temp = I915_READ(reg);
3409                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3410                 temp |= TRANS_DP_PORT_SEL_NONE;
3411                 I915_WRITE(reg, temp);
3412
3413                 /* disable DPLL_SEL */
3414                 temp = I915_READ(PCH_DPLL_SEL);
3415                 switch (pipe) {
3416                 case 0:
3417                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3418                         break;
3419                 case 1:
3420                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3421                         break;
3422                 case 2:
3423                         /* C shares PLL A or B */
3424                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3425                         break;
3426                 default:
3427                         BUG(); /* wtf */
3428                 }
3429                 I915_WRITE(PCH_DPLL_SEL, temp);
3430         }
3431
3432         /* disable PCH DPLL */
3433         intel_disable_pch_pll(intel_crtc);
3434
3435         ironlake_fdi_pll_disable(intel_crtc);
3436
3437         intel_crtc->active = false;
3438         intel_update_watermarks(dev);
3439
3440         mutex_lock(&dev->struct_mutex);
3441         intel_update_fbc(dev);
3442         mutex_unlock(&dev->struct_mutex);
3443 }
3444
3445 static void haswell_crtc_disable(struct drm_crtc *crtc)
3446 {
3447         struct drm_device *dev = crtc->dev;
3448         struct drm_i915_private *dev_priv = dev->dev_private;
3449         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3450         struct intel_encoder *encoder;
3451         int pipe = intel_crtc->pipe;
3452         int plane = intel_crtc->plane;
3453         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3454         bool is_pch_port;
3455
3456         if (!intel_crtc->active)
3457                 return;
3458
3459         is_pch_port = haswell_crtc_driving_pch(crtc);
3460
3461         for_each_encoder_on_crtc(dev, crtc, encoder)
3462                 encoder->disable(encoder);
3463
3464         intel_crtc_wait_for_pending_flips(crtc);
3465         drm_vblank_off(dev, pipe);
3466         intel_crtc_update_cursor(crtc, false);
3467
3468         intel_disable_plane(dev_priv, plane, pipe);
3469
3470         if (dev_priv->cfb_plane == plane)
3471                 intel_disable_fbc(dev);
3472
3473         intel_disable_pipe(dev_priv, pipe);
3474
3475         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3476
3477         /* Disable PF */
3478         I915_WRITE(PF_CTL(pipe), 0);
3479         I915_WRITE(PF_WIN_SZ(pipe), 0);
3480
3481         intel_ddi_disable_pipe_clock(intel_crtc);
3482
3483         for_each_encoder_on_crtc(dev, crtc, encoder)
3484                 if (encoder->post_disable)
3485                         encoder->post_disable(encoder);
3486
3487         if (is_pch_port) {
3488                 ironlake_fdi_disable(crtc);
3489                 intel_disable_transcoder(dev_priv, pipe);
3490                 intel_disable_pch_pll(intel_crtc);
3491                 ironlake_fdi_pll_disable(intel_crtc);
3492         }
3493
3494         intel_crtc->active = false;
3495         intel_update_watermarks(dev);
3496
3497         mutex_lock(&dev->struct_mutex);
3498         intel_update_fbc(dev);
3499         mutex_unlock(&dev->struct_mutex);
3500 }
3501
3502 static void ironlake_crtc_off(struct drm_crtc *crtc)
3503 {
3504         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3505         intel_put_pch_pll(intel_crtc);
3506 }
3507
3508 static void haswell_crtc_off(struct drm_crtc *crtc)
3509 {
3510         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3511
3512         /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3513          * start using it. */
3514         intel_crtc->cpu_transcoder = intel_crtc->pipe;
3515
3516         intel_ddi_put_crtc_pll(crtc);
3517 }
3518
3519 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3520 {
3521         if (!enable && intel_crtc->overlay) {
3522                 struct drm_device *dev = intel_crtc->base.dev;
3523                 struct drm_i915_private *dev_priv = dev->dev_private;
3524
3525                 mutex_lock(&dev->struct_mutex);
3526                 dev_priv->mm.interruptible = false;
3527                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3528                 dev_priv->mm.interruptible = true;
3529                 mutex_unlock(&dev->struct_mutex);
3530         }
3531
3532         /* Let userspace switch the overlay on again. In most cases userspace
3533          * has to recompute where to put it anyway.
3534          */
3535 }
3536
3537 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3538 {
3539         struct drm_device *dev = crtc->dev;
3540         struct drm_i915_private *dev_priv = dev->dev_private;
3541         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3542         struct intel_encoder *encoder;
3543         int pipe = intel_crtc->pipe;
3544         int plane = intel_crtc->plane;
3545
3546         WARN_ON(!crtc->enabled);
3547
3548         if (intel_crtc->active)
3549                 return;
3550
3551         intel_crtc->active = true;
3552         intel_update_watermarks(dev);
3553
3554         intel_enable_pll(dev_priv, pipe);
3555         intel_enable_pipe(dev_priv, pipe, false);
3556         intel_enable_plane(dev_priv, plane, pipe);
3557
3558         intel_crtc_load_lut(crtc);
3559         intel_update_fbc(dev);
3560
3561         /* Give the overlay scaler a chance to enable if it's on this pipe */
3562         intel_crtc_dpms_overlay(intel_crtc, true);
3563         intel_crtc_update_cursor(crtc, true);
3564
3565         for_each_encoder_on_crtc(dev, crtc, encoder)
3566                 encoder->enable(encoder);
3567 }
3568
3569 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3570 {
3571         struct drm_device *dev = crtc->dev;
3572         struct drm_i915_private *dev_priv = dev->dev_private;
3573         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3574         struct intel_encoder *encoder;
3575         int pipe = intel_crtc->pipe;
3576         int plane = intel_crtc->plane;
3577
3578
3579         if (!intel_crtc->active)
3580                 return;
3581
3582         for_each_encoder_on_crtc(dev, crtc, encoder)
3583                 encoder->disable(encoder);
3584
3585         /* Give the overlay scaler a chance to disable if it's on this pipe */
3586         intel_crtc_wait_for_pending_flips(crtc);
3587         drm_vblank_off(dev, pipe);
3588         intel_crtc_dpms_overlay(intel_crtc, false);
3589         intel_crtc_update_cursor(crtc, false);
3590
3591         if (dev_priv->cfb_plane == plane)
3592                 intel_disable_fbc(dev);
3593
3594         intel_disable_plane(dev_priv, plane, pipe);
3595         intel_disable_pipe(dev_priv, pipe);
3596         intel_disable_pll(dev_priv, pipe);
3597
3598         intel_crtc->active = false;
3599         intel_update_fbc(dev);
3600         intel_update_watermarks(dev);
3601 }
3602
3603 static void i9xx_crtc_off(struct drm_crtc *crtc)
3604 {
3605 }
3606
3607 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3608                                     bool enabled)
3609 {
3610         struct drm_device *dev = crtc->dev;
3611         struct drm_i915_master_private *master_priv;
3612         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3613         int pipe = intel_crtc->pipe;
3614
3615         if (!dev->primary->master)
3616                 return;
3617
3618         master_priv = dev->primary->master->driver_priv;
3619         if (!master_priv->sarea_priv)
3620                 return;
3621
3622         switch (pipe) {
3623         case 0:
3624                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3625                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3626                 break;
3627         case 1:
3628                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3629                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3630                 break;
3631         default:
3632                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3633                 break;
3634         }
3635 }
3636
3637 /**
3638  * Sets the power management mode of the pipe and plane.
3639  */
3640 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3641 {
3642         struct drm_device *dev = crtc->dev;
3643         struct drm_i915_private *dev_priv = dev->dev_private;
3644         struct intel_encoder *intel_encoder;
3645         bool enable = false;
3646
3647         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3648                 enable |= intel_encoder->connectors_active;
3649
3650         if (enable)
3651                 dev_priv->display.crtc_enable(crtc);
3652         else
3653                 dev_priv->display.crtc_disable(crtc);
3654
3655         intel_crtc_update_sarea(crtc, enable);
3656 }
3657
3658 static void intel_crtc_noop(struct drm_crtc *crtc)
3659 {
3660 }
3661
3662 static void intel_crtc_disable(struct drm_crtc *crtc)
3663 {
3664         struct drm_device *dev = crtc->dev;
3665         struct drm_connector *connector;
3666         struct drm_i915_private *dev_priv = dev->dev_private;
3667
3668         /* crtc should still be enabled when we disable it. */
3669         WARN_ON(!crtc->enabled);
3670
3671         dev_priv->display.crtc_disable(crtc);
3672         intel_crtc_update_sarea(crtc, false);
3673         dev_priv->display.off(crtc);
3674
3675         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3676         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3677
3678         if (crtc->fb) {
3679                 mutex_lock(&dev->struct_mutex);
3680                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3681                 mutex_unlock(&dev->struct_mutex);
3682                 crtc->fb = NULL;
3683         }
3684
3685         /* Update computed state. */
3686         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3687                 if (!connector->encoder || !connector->encoder->crtc)
3688                         continue;
3689
3690                 if (connector->encoder->crtc != crtc)
3691                         continue;
3692
3693                 connector->dpms = DRM_MODE_DPMS_OFF;
3694                 to_intel_encoder(connector->encoder)->connectors_active = false;
3695         }
3696 }
3697
3698 void intel_modeset_disable(struct drm_device *dev)
3699 {
3700         struct drm_crtc *crtc;
3701
3702         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3703                 if (crtc->enabled)
3704                         intel_crtc_disable(crtc);
3705         }
3706 }
3707
3708 void intel_encoder_noop(struct drm_encoder *encoder)
3709 {
3710 }
3711
3712 void intel_encoder_destroy(struct drm_encoder *encoder)
3713 {
3714         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3715
3716         drm_encoder_cleanup(encoder);
3717         kfree(intel_encoder);
3718 }
3719
3720 /* Simple dpms helper for encodres with just one connector, no cloning and only
3721  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3722  * state of the entire output pipe. */
3723 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3724 {
3725         if (mode == DRM_MODE_DPMS_ON) {
3726                 encoder->connectors_active = true;
3727
3728                 intel_crtc_update_dpms(encoder->base.crtc);
3729         } else {
3730                 encoder->connectors_active = false;
3731
3732                 intel_crtc_update_dpms(encoder->base.crtc);
3733         }
3734 }
3735
3736 /* Cross check the actual hw state with our own modeset state tracking (and it's
3737  * internal consistency). */
3738 static void intel_connector_check_state(struct intel_connector *connector)
3739 {
3740         if (connector->get_hw_state(connector)) {
3741                 struct intel_encoder *encoder = connector->encoder;
3742                 struct drm_crtc *crtc;
3743                 bool encoder_enabled;
3744                 enum pipe pipe;
3745
3746                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3747                               connector->base.base.id,
3748                               drm_get_connector_name(&connector->base));
3749
3750                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3751                      "wrong connector dpms state\n");
3752                 WARN(connector->base.encoder != &encoder->base,
3753                      "active connector not linked to encoder\n");
3754                 WARN(!encoder->connectors_active,
3755                      "encoder->connectors_active not set\n");
3756
3757                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3758                 WARN(!encoder_enabled, "encoder not enabled\n");
3759                 if (WARN_ON(!encoder->base.crtc))
3760                         return;
3761
3762                 crtc = encoder->base.crtc;
3763
3764                 WARN(!crtc->enabled, "crtc not enabled\n");
3765                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3766                 WARN(pipe != to_intel_crtc(crtc)->pipe,
3767                      "encoder active on the wrong pipe\n");
3768         }
3769 }
3770
3771 /* Even simpler default implementation, if there's really no special case to
3772  * consider. */
3773 void intel_connector_dpms(struct drm_connector *connector, int mode)
3774 {
3775         struct intel_encoder *encoder = intel_attached_encoder(connector);
3776
3777         /* All the simple cases only support two dpms states. */
3778         if (mode != DRM_MODE_DPMS_ON)
3779                 mode = DRM_MODE_DPMS_OFF;
3780
3781         if (mode == connector->dpms)
3782                 return;
3783
3784         connector->dpms = mode;
3785
3786         /* Only need to change hw state when actually enabled */
3787         if (encoder->base.crtc)
3788                 intel_encoder_dpms(encoder, mode);
3789         else
3790                 WARN_ON(encoder->connectors_active != false);
3791
3792         intel_modeset_check_state(connector->dev);
3793 }
3794
3795 /* Simple connector->get_hw_state implementation for encoders that support only
3796  * one connector and no cloning and hence the encoder state determines the state
3797  * of the connector. */
3798 bool intel_connector_get_hw_state(struct intel_connector *connector)
3799 {
3800         enum pipe pipe = 0;
3801         struct intel_encoder *encoder = connector->encoder;
3802
3803         return encoder->get_hw_state(encoder, &pipe);
3804 }
3805
3806 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3807                                   const struct drm_display_mode *mode,
3808                                   struct drm_display_mode *adjusted_mode)
3809 {
3810         struct drm_device *dev = crtc->dev;
3811
3812         if (HAS_PCH_SPLIT(dev)) {
3813                 /* FDI link clock is fixed at 2.7G */
3814                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3815                         return false;
3816         }
3817
3818         /* All interlaced capable intel hw wants timings in frames. Note though
3819          * that intel_lvds_mode_fixup does some funny tricks with the crtc
3820          * timings, so we need to be careful not to clobber these.*/
3821         if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3822                 drm_mode_set_crtcinfo(adjusted_mode, 0);
3823
3824         /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3825          * with a hsync front porch of 0.
3826          */
3827         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3828                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3829                 return false;
3830
3831         return true;
3832 }
3833
3834 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3835 {
3836         return 400000; /* FIXME */
3837 }
3838
3839 static int i945_get_display_clock_speed(struct drm_device *dev)
3840 {
3841         return 400000;
3842 }
3843
3844 static int i915_get_display_clock_speed(struct drm_device *dev)
3845 {
3846         return 333000;
3847 }
3848
3849 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3850 {
3851         return 200000;
3852 }
3853
3854 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3855 {
3856         u16 gcfgc = 0;
3857
3858         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3859
3860         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3861                 return 133000;
3862         else {
3863                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3864                 case GC_DISPLAY_CLOCK_333_MHZ:
3865                         return 333000;
3866                 default:
3867                 case GC_DISPLAY_CLOCK_190_200_MHZ:
3868                         return 190000;
3869                 }
3870         }
3871 }
3872
3873 static int i865_get_display_clock_speed(struct drm_device *dev)
3874 {
3875         return 266000;
3876 }
3877
3878 static int i855_get_display_clock_speed(struct drm_device *dev)
3879 {
3880         u16 hpllcc = 0;
3881         /* Assume that the hardware is in the high speed state.  This
3882          * should be the default.
3883          */
3884         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3885         case GC_CLOCK_133_200:
3886         case GC_CLOCK_100_200:
3887                 return 200000;
3888         case GC_CLOCK_166_250:
3889                 return 250000;
3890         case GC_CLOCK_100_133:
3891                 return 133000;
3892         }
3893
3894         /* Shouldn't happen */
3895         return 0;
3896 }
3897
3898 static int i830_get_display_clock_speed(struct drm_device *dev)
3899 {
3900         return 133000;
3901 }
3902
3903 struct fdi_m_n {
3904         u32        tu;
3905         u32        gmch_m;
3906         u32        gmch_n;
3907         u32        link_m;
3908         u32        link_n;
3909 };
3910
3911 static void
3912 fdi_reduce_ratio(u32 *num, u32 *den)
3913 {
3914         while (*num > 0xffffff || *den > 0xffffff) {
3915                 *num >>= 1;
3916                 *den >>= 1;
3917         }
3918 }
3919
3920 static void
3921 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3922                      int link_clock, struct fdi_m_n *m_n)
3923 {
3924         m_n->tu = 64; /* default size */
3925
3926         /* BUG_ON(pixel_clock > INT_MAX / 36); */
3927         m_n->gmch_m = bits_per_pixel * pixel_clock;
3928         m_n->gmch_n = link_clock * nlanes * 8;
3929         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3930
3931         m_n->link_m = pixel_clock;
3932         m_n->link_n = link_clock;
3933         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3934 }
3935
3936 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3937 {
3938         if (i915_panel_use_ssc >= 0)
3939                 return i915_panel_use_ssc != 0;
3940         return dev_priv->lvds_use_ssc
3941                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
3942 }
3943
3944 /**
3945  * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3946  * @crtc: CRTC structure
3947  * @mode: requested mode
3948  *
3949  * A pipe may be connected to one or more outputs.  Based on the depth of the
3950  * attached framebuffer, choose a good color depth to use on the pipe.
3951  *
3952  * If possible, match the pipe depth to the fb depth.  In some cases, this
3953  * isn't ideal, because the connected output supports a lesser or restricted
3954  * set of depths.  Resolve that here:
3955  *    LVDS typically supports only 6bpc, so clamp down in that case
3956  *    HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
3957  *    Displays may support a restricted set as well, check EDID and clamp as
3958  *      appropriate.
3959  *    DP may want to dither down to 6bpc to fit larger modes
3960  *
3961  * RETURNS:
3962  * Dithering requirement (i.e. false if display bpc and pipe bpc match,
3963  * true if they don't match).
3964  */
3965 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
3966                                          struct drm_framebuffer *fb,
3967                                          unsigned int *pipe_bpp,
3968                                          struct drm_display_mode *mode)
3969 {
3970         struct drm_device *dev = crtc->dev;
3971         struct drm_i915_private *dev_priv = dev->dev_private;
3972         struct drm_connector *connector;
3973         struct intel_encoder *intel_encoder;
3974         unsigned int display_bpc = UINT_MAX, bpc;
3975
3976         /* Walk the encoders & connectors on this crtc, get min bpc */
3977         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3978
3979                 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
3980                         unsigned int lvds_bpc;
3981
3982                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
3983                             LVDS_A3_POWER_UP)
3984                                 lvds_bpc = 8;
3985                         else
3986                                 lvds_bpc = 6;
3987
3988                         if (lvds_bpc < display_bpc) {
3989                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
3990                                 display_bpc = lvds_bpc;
3991                         }
3992                         continue;
3993                 }
3994
3995                 /* Not one of the known troublemakers, check the EDID */
3996                 list_for_each_entry(connector, &dev->mode_config.connector_list,
3997                                     head) {
3998                         if (connector->encoder != &intel_encoder->base)
3999                                 continue;
4000
4001                         /* Don't use an invalid EDID bpc value */
4002                         if (connector->display_info.bpc &&
4003                             connector->display_info.bpc < display_bpc) {
4004                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4005                                 display_bpc = connector->display_info.bpc;
4006                         }
4007                 }
4008
4009                 /*
4010                  * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4011                  * through, clamp it down.  (Note: >12bpc will be caught below.)
4012                  */
4013                 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4014                         if (display_bpc > 8 && display_bpc < 12) {
4015                                 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
4016                                 display_bpc = 12;
4017                         } else {
4018                                 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
4019                                 display_bpc = 8;
4020                         }
4021                 }
4022         }
4023
4024         if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4025                 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4026                 display_bpc = 6;
4027         }
4028
4029         /*
4030          * We could just drive the pipe at the highest bpc all the time and
4031          * enable dithering as needed, but that costs bandwidth.  So choose
4032          * the minimum value that expresses the full color range of the fb but
4033          * also stays within the max display bpc discovered above.
4034          */
4035
4036         switch (fb->depth) {
4037         case 8:
4038                 bpc = 8; /* since we go through a colormap */
4039                 break;
4040         case 15:
4041         case 16:
4042                 bpc = 6; /* min is 18bpp */
4043                 break;
4044         case 24:
4045                 bpc = 8;
4046                 break;
4047         case 30:
4048                 bpc = 10;
4049                 break;
4050         case 48:
4051                 bpc = 12;
4052                 break;
4053         default:
4054                 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4055                 bpc = min((unsigned int)8, display_bpc);
4056                 break;
4057         }
4058
4059         display_bpc = min(display_bpc, bpc);
4060
4061         DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4062                       bpc, display_bpc);
4063
4064         *pipe_bpp = display_bpc * 3;
4065
4066         return display_bpc != bpc;
4067 }
4068
4069 static int vlv_get_refclk(struct drm_crtc *crtc)
4070 {
4071         struct drm_device *dev = crtc->dev;
4072         struct drm_i915_private *dev_priv = dev->dev_private;
4073         int refclk = 27000; /* for DP & HDMI */
4074
4075         return 100000; /* only one validated so far */
4076
4077         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4078                 refclk = 96000;
4079         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4080                 if (intel_panel_use_ssc(dev_priv))
4081                         refclk = 100000;
4082                 else
4083                         refclk = 96000;
4084         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4085                 refclk = 100000;
4086         }
4087
4088         return refclk;
4089 }
4090
4091 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4092 {
4093         struct drm_device *dev = crtc->dev;
4094         struct drm_i915_private *dev_priv = dev->dev_private;
4095         int refclk;
4096
4097         if (IS_VALLEYVIEW(dev)) {
4098                 refclk = vlv_get_refclk(crtc);
4099         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4100             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4101                 refclk = dev_priv->lvds_ssc_freq * 1000;
4102                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4103                               refclk / 1000);
4104         } else if (!IS_GEN2(dev)) {
4105                 refclk = 96000;
4106         } else {
4107                 refclk = 48000;
4108         }
4109
4110         return refclk;
4111 }
4112
4113 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4114                                       intel_clock_t *clock)
4115 {
4116         /* SDVO TV has fixed PLL values depend on its clock range,
4117            this mirrors vbios setting. */
4118         if (adjusted_mode->clock >= 100000
4119             && adjusted_mode->clock < 140500) {
4120                 clock->p1 = 2;
4121                 clock->p2 = 10;
4122                 clock->n = 3;
4123                 clock->m1 = 16;
4124                 clock->m2 = 8;
4125         } else if (adjusted_mode->clock >= 140500
4126                    && adjusted_mode->clock <= 200000) {
4127                 clock->p1 = 1;
4128                 clock->p2 = 10;
4129                 clock->n = 6;
4130                 clock->m1 = 12;
4131                 clock->m2 = 8;
4132         }
4133 }
4134
4135 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4136                                      intel_clock_t *clock,
4137                                      intel_clock_t *reduced_clock)
4138 {
4139         struct drm_device *dev = crtc->dev;
4140         struct drm_i915_private *dev_priv = dev->dev_private;
4141         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4142         int pipe = intel_crtc->pipe;
4143         u32 fp, fp2 = 0;
4144
4145         if (IS_PINEVIEW(dev)) {
4146                 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4147                 if (reduced_clock)
4148                         fp2 = (1 << reduced_clock->n) << 16 |
4149                                 reduced_clock->m1 << 8 | reduced_clock->m2;
4150         } else {
4151                 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4152                 if (reduced_clock)
4153                         fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4154                                 reduced_clock->m2;
4155         }
4156
4157         I915_WRITE(FP0(pipe), fp);
4158
4159         intel_crtc->lowfreq_avail = false;
4160         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4161             reduced_clock && i915_powersave) {
4162                 I915_WRITE(FP1(pipe), fp2);
4163                 intel_crtc->lowfreq_avail = true;
4164         } else {
4165                 I915_WRITE(FP1(pipe), fp);
4166         }
4167 }
4168
4169 static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
4170                               struct drm_display_mode *adjusted_mode)
4171 {
4172         struct drm_device *dev = crtc->dev;
4173         struct drm_i915_private *dev_priv = dev->dev_private;
4174         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4175         int pipe = intel_crtc->pipe;
4176         u32 temp;
4177
4178         temp = I915_READ(LVDS);
4179         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4180         if (pipe == 1) {
4181                 temp |= LVDS_PIPEB_SELECT;
4182         } else {
4183                 temp &= ~LVDS_PIPEB_SELECT;
4184         }
4185         /* set the corresponsding LVDS_BORDER bit */
4186         temp |= dev_priv->lvds_border_bits;
4187         /* Set the B0-B3 data pairs corresponding to whether we're going to
4188          * set the DPLLs for dual-channel mode or not.
4189          */
4190         if (clock->p2 == 7)
4191                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4192         else
4193                 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4194
4195         /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4196          * appropriately here, but we need to look more thoroughly into how
4197          * panels behave in the two modes.
4198          */
4199         /* set the dithering flag on LVDS as needed */
4200         if (INTEL_INFO(dev)->gen >= 4) {
4201                 if (dev_priv->lvds_dither)
4202                         temp |= LVDS_ENABLE_DITHER;
4203                 else
4204                         temp &= ~LVDS_ENABLE_DITHER;
4205         }
4206         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4207         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4208                 temp |= LVDS_HSYNC_POLARITY;
4209         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4210                 temp |= LVDS_VSYNC_POLARITY;
4211         I915_WRITE(LVDS, temp);
4212 }
4213
4214 static void vlv_update_pll(struct drm_crtc *crtc,
4215                            struct drm_display_mode *mode,
4216                            struct drm_display_mode *adjusted_mode,
4217                            intel_clock_t *clock, intel_clock_t *reduced_clock,
4218                            int num_connectors)
4219 {
4220         struct drm_device *dev = crtc->dev;
4221         struct drm_i915_private *dev_priv = dev->dev_private;
4222         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4223         int pipe = intel_crtc->pipe;
4224         u32 dpll, mdiv, pdiv;
4225         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4226         bool is_sdvo;
4227         u32 temp;
4228
4229         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4230                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4231
4232         dpll = DPLL_VGA_MODE_DIS;
4233         dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4234         dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4235         dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4236
4237         I915_WRITE(DPLL(pipe), dpll);
4238         POSTING_READ(DPLL(pipe));
4239
4240         bestn = clock->n;
4241         bestm1 = clock->m1;
4242         bestm2 = clock->m2;
4243         bestp1 = clock->p1;
4244         bestp2 = clock->p2;
4245
4246         /*
4247          * In Valleyview PLL and program lane counter registers are exposed
4248          * through DPIO interface
4249          */
4250         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4251         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4252         mdiv |= ((bestn << DPIO_N_SHIFT));
4253         mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4254         mdiv |= (1 << DPIO_K_SHIFT);
4255         mdiv |= DPIO_ENABLE_CALIBRATION;
4256         intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4257
4258         intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4259
4260         pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
4261                 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4262                 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4263                 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4264         intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4265
4266         intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
4267
4268         dpll |= DPLL_VCO_ENABLE;
4269         I915_WRITE(DPLL(pipe), dpll);
4270         POSTING_READ(DPLL(pipe));
4271         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4272                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4273
4274         intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4275
4276         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4277                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4278
4279         I915_WRITE(DPLL(pipe), dpll);
4280
4281         /* Wait for the clocks to stabilize. */
4282         POSTING_READ(DPLL(pipe));
4283         udelay(150);
4284
4285         temp = 0;
4286         if (is_sdvo) {
4287                 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4288                 if (temp > 1)
4289                         temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4290                 else
4291                         temp = 0;
4292         }
4293         I915_WRITE(DPLL_MD(pipe), temp);
4294         POSTING_READ(DPLL_MD(pipe));
4295
4296         /* Now program lane control registers */
4297         if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4298                         || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4299         {
4300                 temp = 0x1000C4;
4301                 if(pipe == 1)
4302                         temp |= (1 << 21);
4303                 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4304         }
4305         if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4306         {
4307                 temp = 0x1000C4;
4308                 if(pipe == 1)
4309                         temp |= (1 << 21);
4310                 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4311         }
4312 }
4313
4314 static void i9xx_update_pll(struct drm_crtc *crtc,
4315                             struct drm_display_mode *mode,
4316                             struct drm_display_mode *adjusted_mode,
4317                             intel_clock_t *clock, intel_clock_t *reduced_clock,
4318                             int num_connectors)
4319 {
4320         struct drm_device *dev = crtc->dev;
4321         struct drm_i915_private *dev_priv = dev->dev_private;
4322         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4323         int pipe = intel_crtc->pipe;
4324         u32 dpll;
4325         bool is_sdvo;
4326
4327         i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4328
4329         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4330                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4331
4332         dpll = DPLL_VGA_MODE_DIS;
4333
4334         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4335                 dpll |= DPLLB_MODE_LVDS;
4336         else
4337                 dpll |= DPLLB_MODE_DAC_SERIAL;
4338         if (is_sdvo) {
4339                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4340                 if (pixel_multiplier > 1) {
4341                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4342                                 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4343                 }
4344                 dpll |= DPLL_DVO_HIGH_SPEED;
4345         }
4346         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4347                 dpll |= DPLL_DVO_HIGH_SPEED;
4348
4349         /* compute bitmask from p1 value */
4350         if (IS_PINEVIEW(dev))
4351                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4352         else {
4353                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4354                 if (IS_G4X(dev) && reduced_clock)
4355                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4356         }
4357         switch (clock->p2) {
4358         case 5:
4359                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4360                 break;
4361         case 7:
4362                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4363                 break;
4364         case 10:
4365                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4366                 break;
4367         case 14:
4368                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4369                 break;
4370         }
4371         if (INTEL_INFO(dev)->gen >= 4)
4372                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4373
4374         if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4375                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4376         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4377                 /* XXX: just matching BIOS for now */
4378                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4379                 dpll |= 3;
4380         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4381                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4382                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4383         else
4384                 dpll |= PLL_REF_INPUT_DREFCLK;
4385
4386         dpll |= DPLL_VCO_ENABLE;
4387         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4388         POSTING_READ(DPLL(pipe));
4389         udelay(150);
4390
4391         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4392          * This is an exception to the general rule that mode_set doesn't turn
4393          * things on.
4394          */
4395         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4396                 intel_update_lvds(crtc, clock, adjusted_mode);
4397
4398         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4399                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4400
4401         I915_WRITE(DPLL(pipe), dpll);
4402
4403         /* Wait for the clocks to stabilize. */
4404         POSTING_READ(DPLL(pipe));
4405         udelay(150);
4406
4407         if (INTEL_INFO(dev)->gen >= 4) {
4408                 u32 temp = 0;
4409                 if (is_sdvo) {
4410                         temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4411                         if (temp > 1)
4412                                 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4413                         else
4414                                 temp = 0;
4415                 }
4416                 I915_WRITE(DPLL_MD(pipe), temp);
4417         } else {
4418                 /* The pixel multiplier can only be updated once the
4419                  * DPLL is enabled and the clocks are stable.
4420                  *
4421                  * So write it again.
4422                  */
4423                 I915_WRITE(DPLL(pipe), dpll);
4424         }
4425 }
4426
4427 static void i8xx_update_pll(struct drm_crtc *crtc,
4428                             struct drm_display_mode *adjusted_mode,
4429                             intel_clock_t *clock, intel_clock_t *reduced_clock,
4430                             int num_connectors)
4431 {
4432         struct drm_device *dev = crtc->dev;
4433         struct drm_i915_private *dev_priv = dev->dev_private;
4434         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4435         int pipe = intel_crtc->pipe;
4436         u32 dpll;
4437
4438         i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4439
4440         dpll = DPLL_VGA_MODE_DIS;
4441
4442         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4443                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4444         } else {
4445                 if (clock->p1 == 2)
4446                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4447                 else
4448                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4449                 if (clock->p2 == 4)
4450                         dpll |= PLL_P2_DIVIDE_BY_4;
4451         }
4452
4453         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4454                 /* XXX: just matching BIOS for now */
4455                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4456                 dpll |= 3;
4457         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4458                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4459                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4460         else
4461                 dpll |= PLL_REF_INPUT_DREFCLK;
4462
4463         dpll |= DPLL_VCO_ENABLE;
4464         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4465         POSTING_READ(DPLL(pipe));
4466         udelay(150);
4467
4468         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4469          * This is an exception to the general rule that mode_set doesn't turn
4470          * things on.
4471          */
4472         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4473                 intel_update_lvds(crtc, clock, adjusted_mode);
4474
4475         I915_WRITE(DPLL(pipe), dpll);
4476
4477         /* Wait for the clocks to stabilize. */
4478         POSTING_READ(DPLL(pipe));
4479         udelay(150);
4480
4481         /* The pixel multiplier can only be updated once the
4482          * DPLL is enabled and the clocks are stable.
4483          *
4484          * So write it again.
4485          */
4486         I915_WRITE(DPLL(pipe), dpll);
4487 }
4488
4489 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4490                                    struct drm_display_mode *mode,
4491                                    struct drm_display_mode *adjusted_mode)
4492 {
4493         struct drm_device *dev = intel_crtc->base.dev;
4494         struct drm_i915_private *dev_priv = dev->dev_private;
4495         enum pipe pipe = intel_crtc->pipe;
4496         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
4497         uint32_t vsyncshift;
4498
4499         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4500                 /* the chip adds 2 halflines automatically */
4501                 adjusted_mode->crtc_vtotal -= 1;
4502                 adjusted_mode->crtc_vblank_end -= 1;
4503                 vsyncshift = adjusted_mode->crtc_hsync_start
4504                              - adjusted_mode->crtc_htotal / 2;
4505         } else {
4506                 vsyncshift = 0;
4507         }
4508
4509         if (INTEL_INFO(dev)->gen > 3)
4510                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4511
4512         I915_WRITE(HTOTAL(cpu_transcoder),
4513                    (adjusted_mode->crtc_hdisplay - 1) |
4514                    ((adjusted_mode->crtc_htotal - 1) << 16));
4515         I915_WRITE(HBLANK(cpu_transcoder),
4516                    (adjusted_mode->crtc_hblank_start - 1) |
4517                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4518         I915_WRITE(HSYNC(cpu_transcoder),
4519                    (adjusted_mode->crtc_hsync_start - 1) |
4520                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4521
4522         I915_WRITE(VTOTAL(cpu_transcoder),
4523                    (adjusted_mode->crtc_vdisplay - 1) |
4524                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4525         I915_WRITE(VBLANK(cpu_transcoder),
4526                    (adjusted_mode->crtc_vblank_start - 1) |
4527                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4528         I915_WRITE(VSYNC(cpu_transcoder),
4529                    (adjusted_mode->crtc_vsync_start - 1) |
4530                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4531
4532         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4533          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4534          * documented on the DDI_FUNC_CTL register description, EDP Input Select
4535          * bits. */
4536         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4537             (pipe == PIPE_B || pipe == PIPE_C))
4538                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4539
4540         /* pipesrc controls the size that is scaled from, which should
4541          * always be the user's requested size.
4542          */
4543         I915_WRITE(PIPESRC(pipe),
4544                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4545 }
4546
4547 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4548                               struct drm_display_mode *mode,
4549                               struct drm_display_mode *adjusted_mode,
4550                               int x, int y,
4551                               struct drm_framebuffer *fb)
4552 {
4553         struct drm_device *dev = crtc->dev;
4554         struct drm_i915_private *dev_priv = dev->dev_private;
4555         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4556         int pipe = intel_crtc->pipe;
4557         int plane = intel_crtc->plane;
4558         int refclk, num_connectors = 0;
4559         intel_clock_t clock, reduced_clock;
4560         u32 dspcntr, pipeconf;
4561         bool ok, has_reduced_clock = false, is_sdvo = false;
4562         bool is_lvds = false, is_tv = false, is_dp = false;
4563         struct intel_encoder *encoder;
4564         const intel_limit_t *limit;
4565         int ret;
4566
4567         for_each_encoder_on_crtc(dev, crtc, encoder) {
4568                 switch (encoder->type) {
4569                 case INTEL_OUTPUT_LVDS:
4570                         is_lvds = true;
4571                         break;
4572                 case INTEL_OUTPUT_SDVO:
4573                 case INTEL_OUTPUT_HDMI:
4574                         is_sdvo = true;
4575                         if (encoder->needs_tv_clock)
4576                                 is_tv = true;
4577                         break;
4578                 case INTEL_OUTPUT_TVOUT:
4579                         is_tv = true;
4580                         break;
4581                 case INTEL_OUTPUT_DISPLAYPORT:
4582                         is_dp = true;
4583                         break;
4584                 }
4585
4586                 num_connectors++;
4587         }
4588
4589         refclk = i9xx_get_refclk(crtc, num_connectors);
4590
4591         /*
4592          * Returns a set of divisors for the desired target clock with the given
4593          * refclk, or FALSE.  The returned values represent the clock equation:
4594          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4595          */
4596         limit = intel_limit(crtc, refclk);
4597         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4598                              &clock);
4599         if (!ok) {
4600                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4601                 return -EINVAL;
4602         }
4603
4604         /* Ensure that the cursor is valid for the new mode before changing... */
4605         intel_crtc_update_cursor(crtc, true);
4606
4607         if (is_lvds && dev_priv->lvds_downclock_avail) {
4608                 /*
4609                  * Ensure we match the reduced clock's P to the target clock.
4610                  * If the clocks don't match, we can't switch the display clock
4611                  * by using the FP0/FP1. In such case we will disable the LVDS
4612                  * downclock feature.
4613                 */
4614                 has_reduced_clock = limit->find_pll(limit, crtc,
4615                                                     dev_priv->lvds_downclock,
4616                                                     refclk,
4617                                                     &clock,
4618                                                     &reduced_clock);
4619         }
4620
4621         if (is_sdvo && is_tv)
4622                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4623
4624         if (IS_GEN2(dev))
4625                 i8xx_update_pll(crtc, adjusted_mode, &clock,
4626                                 has_reduced_clock ? &reduced_clock : NULL,
4627                                 num_connectors);
4628         else if (IS_VALLEYVIEW(dev))
4629                 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4630                                 has_reduced_clock ? &reduced_clock : NULL,
4631                                 num_connectors);
4632         else
4633                 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4634                                 has_reduced_clock ? &reduced_clock : NULL,
4635                                 num_connectors);
4636
4637         /* setup pipeconf */
4638         pipeconf = I915_READ(PIPECONF(pipe));
4639
4640         /* Set up the display plane register */
4641         dspcntr = DISPPLANE_GAMMA_ENABLE;
4642
4643         if (pipe == 0)
4644                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4645         else
4646                 dspcntr |= DISPPLANE_SEL_PIPE_B;
4647
4648         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4649                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4650                  * core speed.
4651                  *
4652                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4653                  * pipe == 0 check?
4654                  */
4655                 if (mode->clock >
4656                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4657                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4658                 else
4659                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4660         }
4661
4662         /* default to 8bpc */
4663         pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4664         if (is_dp) {
4665                 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4666                         pipeconf |= PIPECONF_BPP_6 |
4667                                     PIPECONF_DITHER_EN |
4668                                     PIPECONF_DITHER_TYPE_SP;
4669                 }
4670         }
4671
4672         if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4673                 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4674                         pipeconf |= PIPECONF_BPP_6 |
4675                                         PIPECONF_ENABLE |
4676                                         I965_PIPECONF_ACTIVE;
4677                 }
4678         }
4679
4680         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4681         drm_mode_debug_printmodeline(mode);
4682
4683         if (HAS_PIPE_CXSR(dev)) {
4684                 if (intel_crtc->lowfreq_avail) {
4685                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4686                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4687                 } else {
4688                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4689                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4690                 }
4691         }
4692
4693         pipeconf &= ~PIPECONF_INTERLACE_MASK;
4694         if (!IS_GEN2(dev) &&
4695             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4696                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4697         else
4698                 pipeconf |= PIPECONF_PROGRESSIVE;
4699
4700         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
4701
4702         /* pipesrc and dspsize control the size that is scaled from,
4703          * which should always be the user's requested size.
4704          */
4705         I915_WRITE(DSPSIZE(plane),
4706                    ((mode->vdisplay - 1) << 16) |
4707                    (mode->hdisplay - 1));
4708         I915_WRITE(DSPPOS(plane), 0);
4709
4710         I915_WRITE(PIPECONF(pipe), pipeconf);
4711         POSTING_READ(PIPECONF(pipe));
4712         intel_enable_pipe(dev_priv, pipe, false);
4713
4714         intel_wait_for_vblank(dev, pipe);
4715
4716         I915_WRITE(DSPCNTR(plane), dspcntr);
4717         POSTING_READ(DSPCNTR(plane));
4718
4719         ret = intel_pipe_set_base(crtc, x, y, fb);
4720
4721         intel_update_watermarks(dev);
4722
4723         return ret;
4724 }
4725
4726 /*
4727  * Initialize reference clocks when the driver loads
4728  */
4729 void ironlake_init_pch_refclk(struct drm_device *dev)
4730 {
4731         struct drm_i915_private *dev_priv = dev->dev_private;
4732         struct drm_mode_config *mode_config = &dev->mode_config;
4733         struct intel_encoder *encoder;
4734         u32 temp;
4735         bool has_lvds = false;
4736         bool has_cpu_edp = false;
4737         bool has_pch_edp = false;
4738         bool has_panel = false;
4739         bool has_ck505 = false;
4740         bool can_ssc = false;
4741
4742         /* We need to take the global config into account */
4743         list_for_each_entry(encoder, &mode_config->encoder_list,
4744                             base.head) {
4745                 switch (encoder->type) {
4746                 case INTEL_OUTPUT_LVDS:
4747                         has_panel = true;
4748                         has_lvds = true;
4749                         break;
4750                 case INTEL_OUTPUT_EDP:
4751                         has_panel = true;
4752                         if (intel_encoder_is_pch_edp(&encoder->base))
4753                                 has_pch_edp = true;
4754                         else
4755                                 has_cpu_edp = true;
4756                         break;
4757                 }
4758         }
4759
4760         if (HAS_PCH_IBX(dev)) {
4761                 has_ck505 = dev_priv->display_clock_mode;
4762                 can_ssc = has_ck505;
4763         } else {
4764                 has_ck505 = false;
4765                 can_ssc = true;
4766         }
4767
4768         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4769                       has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4770                       has_ck505);
4771
4772         /* Ironlake: try to setup display ref clock before DPLL
4773          * enabling. This is only under driver's control after
4774          * PCH B stepping, previous chipset stepping should be
4775          * ignoring this setting.
4776          */
4777         temp = I915_READ(PCH_DREF_CONTROL);
4778         /* Always enable nonspread source */
4779         temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4780
4781         if (has_ck505)
4782                 temp |= DREF_NONSPREAD_CK505_ENABLE;
4783         else
4784                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4785
4786         if (has_panel) {
4787                 temp &= ~DREF_SSC_SOURCE_MASK;
4788                 temp |= DREF_SSC_SOURCE_ENABLE;
4789
4790                 /* SSC must be turned on before enabling the CPU output  */
4791                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4792                         DRM_DEBUG_KMS("Using SSC on panel\n");
4793                         temp |= DREF_SSC1_ENABLE;
4794                 } else
4795                         temp &= ~DREF_SSC1_ENABLE;
4796
4797                 /* Get SSC going before enabling the outputs */
4798                 I915_WRITE(PCH_DREF_CONTROL, temp);
4799                 POSTING_READ(PCH_DREF_CONTROL);
4800                 udelay(200);
4801
4802                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4803
4804                 /* Enable CPU source on CPU attached eDP */
4805                 if (has_cpu_edp) {
4806                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4807                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
4808                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4809                         }
4810                         else
4811                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4812                 } else
4813                         temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4814
4815                 I915_WRITE(PCH_DREF_CONTROL, temp);
4816                 POSTING_READ(PCH_DREF_CONTROL);
4817                 udelay(200);
4818         } else {
4819                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4820
4821                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4822
4823                 /* Turn off CPU output */
4824                 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4825
4826                 I915_WRITE(PCH_DREF_CONTROL, temp);
4827                 POSTING_READ(PCH_DREF_CONTROL);
4828                 udelay(200);
4829
4830                 /* Turn off the SSC source */
4831                 temp &= ~DREF_SSC_SOURCE_MASK;
4832                 temp |= DREF_SSC_SOURCE_DISABLE;
4833
4834                 /* Turn off SSC1 */
4835                 temp &= ~ DREF_SSC1_ENABLE;
4836
4837                 I915_WRITE(PCH_DREF_CONTROL, temp);
4838                 POSTING_READ(PCH_DREF_CONTROL);
4839                 udelay(200);
4840         }
4841 }
4842
4843 static int ironlake_get_refclk(struct drm_crtc *crtc)
4844 {
4845         struct drm_device *dev = crtc->dev;
4846         struct drm_i915_private *dev_priv = dev->dev_private;
4847         struct intel_encoder *encoder;
4848         struct intel_encoder *edp_encoder = NULL;
4849         int num_connectors = 0;
4850         bool is_lvds = false;
4851
4852         for_each_encoder_on_crtc(dev, crtc, encoder) {
4853                 switch (encoder->type) {
4854                 case INTEL_OUTPUT_LVDS:
4855                         is_lvds = true;
4856                         break;
4857                 case INTEL_OUTPUT_EDP:
4858                         edp_encoder = encoder;
4859                         break;
4860                 }
4861                 num_connectors++;
4862         }
4863
4864         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4865                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4866                               dev_priv->lvds_ssc_freq);
4867                 return dev_priv->lvds_ssc_freq * 1000;
4868         }
4869
4870         return 120000;
4871 }
4872
4873 static void ironlake_set_pipeconf(struct drm_crtc *crtc,
4874                                   struct drm_display_mode *adjusted_mode,
4875                                   bool dither)
4876 {
4877         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4878         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4879         int pipe = intel_crtc->pipe;
4880         uint32_t val;
4881
4882         val = I915_READ(PIPECONF(pipe));
4883
4884         val &= ~PIPE_BPC_MASK;
4885         switch (intel_crtc->bpp) {
4886         case 18:
4887                 val |= PIPE_6BPC;
4888                 break;
4889         case 24:
4890                 val |= PIPE_8BPC;
4891                 break;
4892         case 30:
4893                 val |= PIPE_10BPC;
4894                 break;
4895         case 36:
4896                 val |= PIPE_12BPC;
4897                 break;
4898         default:
4899                 /* Case prevented by intel_choose_pipe_bpp_dither. */
4900                 BUG();
4901         }
4902
4903         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4904         if (dither)
4905                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
4906
4907         val &= ~PIPECONF_INTERLACE_MASK;
4908         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4909                 val |= PIPECONF_INTERLACED_ILK;
4910         else
4911                 val |= PIPECONF_PROGRESSIVE;
4912
4913         I915_WRITE(PIPECONF(pipe), val);
4914         POSTING_READ(PIPECONF(pipe));
4915 }
4916
4917 static void haswell_set_pipeconf(struct drm_crtc *crtc,
4918                                  struct drm_display_mode *adjusted_mode,
4919                                  bool dither)
4920 {
4921         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4922         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4923         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
4924         uint32_t val;
4925
4926         val = I915_READ(PIPECONF(cpu_transcoder));
4927
4928         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4929         if (dither)
4930                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
4931
4932         val &= ~PIPECONF_INTERLACE_MASK_HSW;
4933         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4934                 val |= PIPECONF_INTERLACED_ILK;
4935         else
4936                 val |= PIPECONF_PROGRESSIVE;
4937
4938         I915_WRITE(PIPECONF(cpu_transcoder), val);
4939         POSTING_READ(PIPECONF(cpu_transcoder));
4940 }
4941
4942 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
4943                                     struct drm_display_mode *adjusted_mode,
4944                                     intel_clock_t *clock,
4945                                     bool *has_reduced_clock,
4946                                     intel_clock_t *reduced_clock)
4947 {
4948         struct drm_device *dev = crtc->dev;
4949         struct drm_i915_private *dev_priv = dev->dev_private;
4950         struct intel_encoder *intel_encoder;
4951         int refclk;
4952         const intel_limit_t *limit;
4953         bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
4954
4955         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4956                 switch (intel_encoder->type) {
4957                 case INTEL_OUTPUT_LVDS:
4958                         is_lvds = true;
4959                         break;
4960                 case INTEL_OUTPUT_SDVO:
4961                 case INTEL_OUTPUT_HDMI:
4962                         is_sdvo = true;
4963                         if (intel_encoder->needs_tv_clock)
4964                                 is_tv = true;
4965                         break;
4966                 case INTEL_OUTPUT_TVOUT:
4967                         is_tv = true;
4968                         break;
4969                 }
4970         }
4971
4972         refclk = ironlake_get_refclk(crtc);
4973
4974         /*
4975          * Returns a set of divisors for the desired target clock with the given
4976          * refclk, or FALSE.  The returned values represent the clock equation:
4977          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4978          */
4979         limit = intel_limit(crtc, refclk);
4980         ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4981                               clock);
4982         if (!ret)
4983                 return false;
4984
4985         if (is_lvds && dev_priv->lvds_downclock_avail) {
4986                 /*
4987                  * Ensure we match the reduced clock's P to the target clock.
4988                  * If the clocks don't match, we can't switch the display clock
4989                  * by using the FP0/FP1. In such case we will disable the LVDS
4990                  * downclock feature.
4991                 */
4992                 *has_reduced_clock = limit->find_pll(limit, crtc,
4993                                                      dev_priv->lvds_downclock,
4994                                                      refclk,
4995                                                      clock,
4996                                                      reduced_clock);
4997         }
4998
4999         if (is_sdvo && is_tv)
5000                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5001
5002         return true;
5003 }
5004
5005 static void ironlake_set_m_n(struct drm_crtc *crtc,
5006                              struct drm_display_mode *mode,
5007                              struct drm_display_mode *adjusted_mode)
5008 {
5009         struct drm_device *dev = crtc->dev;
5010         struct drm_i915_private *dev_priv = dev->dev_private;
5011         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5012         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5013         struct intel_encoder *intel_encoder, *edp_encoder = NULL;
5014         struct fdi_m_n m_n = {0};
5015         int target_clock, pixel_multiplier, lane, link_bw;
5016         bool is_dp = false, is_cpu_edp = false;
5017
5018         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5019                 switch (intel_encoder->type) {
5020                 case INTEL_OUTPUT_DISPLAYPORT:
5021                         is_dp = true;
5022                         break;
5023                 case INTEL_OUTPUT_EDP:
5024                         is_dp = true;
5025                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5026                                 is_cpu_edp = true;
5027                         edp_encoder = intel_encoder;
5028                         break;
5029                 }
5030         }
5031
5032         /* FDI link */
5033         pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5034         lane = 0;
5035         /* CPU eDP doesn't require FDI link, so just set DP M/N
5036            according to current link config */
5037         if (is_cpu_edp) {
5038                 intel_edp_link_config(edp_encoder, &lane, &link_bw);
5039         } else {
5040                 /* FDI is a binary signal running at ~2.7GHz, encoding
5041                  * each output octet as 10 bits. The actual frequency
5042                  * is stored as a divider into a 100MHz clock, and the
5043                  * mode pixel clock is stored in units of 1KHz.
5044                  * Hence the bw of each lane in terms of the mode signal
5045                  * is:
5046                  */
5047                 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5048         }
5049
5050         /* [e]DP over FDI requires target mode clock instead of link clock. */
5051         if (edp_encoder)
5052                 target_clock = intel_edp_target_clock(edp_encoder, mode);
5053         else if (is_dp)
5054                 target_clock = mode->clock;
5055         else
5056                 target_clock = adjusted_mode->clock;
5057
5058         if (!lane) {
5059                 /*
5060                  * Account for spread spectrum to avoid
5061                  * oversubscribing the link. Max center spread
5062                  * is 2.5%; use 5% for safety's sake.
5063                  */
5064                 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5065                 lane = bps / (link_bw * 8) + 1;
5066         }
5067
5068         intel_crtc->fdi_lanes = lane;
5069
5070         if (pixel_multiplier > 1)
5071                 link_bw *= pixel_multiplier;
5072         ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5073                              &m_n);
5074
5075         I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
5076         I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
5077         I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
5078         I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
5079 }
5080
5081 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5082                                       struct drm_display_mode *adjusted_mode,
5083                                       intel_clock_t *clock, u32 fp)
5084 {
5085         struct drm_crtc *crtc = &intel_crtc->base;
5086         struct drm_device *dev = crtc->dev;
5087         struct drm_i915_private *dev_priv = dev->dev_private;
5088         struct intel_encoder *intel_encoder;
5089         uint32_t dpll;
5090         int factor, pixel_multiplier, num_connectors = 0;
5091         bool is_lvds = false, is_sdvo = false, is_tv = false;
5092         bool is_dp = false, is_cpu_edp = false;
5093
5094         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5095                 switch (intel_encoder->type) {
5096                 case INTEL_OUTPUT_LVDS:
5097                         is_lvds = true;
5098                         break;
5099                 case INTEL_OUTPUT_SDVO:
5100                 case INTEL_OUTPUT_HDMI:
5101                         is_sdvo = true;
5102                         if (intel_encoder->needs_tv_clock)
5103                                 is_tv = true;
5104                         break;
5105                 case INTEL_OUTPUT_TVOUT:
5106                         is_tv = true;
5107                         break;
5108                 case INTEL_OUTPUT_DISPLAYPORT:
5109                         is_dp = true;
5110                         break;
5111                 case INTEL_OUTPUT_EDP:
5112                         is_dp = true;
5113                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5114                                 is_cpu_edp = true;
5115                         break;
5116                 }
5117
5118                 num_connectors++;
5119         }
5120
5121         /* Enable autotuning of the PLL clock (if permissible) */
5122         factor = 21;
5123         if (is_lvds) {
5124                 if ((intel_panel_use_ssc(dev_priv) &&
5125                      dev_priv->lvds_ssc_freq == 100) ||
5126                     (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5127                         factor = 25;
5128         } else if (is_sdvo && is_tv)
5129                 factor = 20;
5130
5131         if (clock->m < factor * clock->n)
5132                 fp |= FP_CB_TUNE;
5133
5134         dpll = 0;
5135
5136         if (is_lvds)
5137                 dpll |= DPLLB_MODE_LVDS;
5138         else
5139                 dpll |= DPLLB_MODE_DAC_SERIAL;
5140         if (is_sdvo) {
5141                 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5142                 if (pixel_multiplier > 1) {
5143                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5144                 }
5145                 dpll |= DPLL_DVO_HIGH_SPEED;
5146         }
5147         if (is_dp && !is_cpu_edp)
5148                 dpll |= DPLL_DVO_HIGH_SPEED;
5149
5150         /* compute bitmask from p1 value */
5151         dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5152         /* also FPA1 */
5153         dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5154
5155         switch (clock->p2) {
5156         case 5:
5157                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5158                 break;
5159         case 7:
5160                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5161                 break;
5162         case 10:
5163                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5164                 break;
5165         case 14:
5166                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5167                 break;
5168         }
5169
5170         if (is_sdvo && is_tv)
5171                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5172         else if (is_tv)
5173                 /* XXX: just matching BIOS for now */
5174                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5175                 dpll |= 3;
5176         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5177                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5178         else
5179                 dpll |= PLL_REF_INPUT_DREFCLK;
5180
5181         return dpll;
5182 }
5183
5184 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5185                                   struct drm_display_mode *mode,
5186                                   struct drm_display_mode *adjusted_mode,
5187                                   int x, int y,
5188                                   struct drm_framebuffer *fb)
5189 {
5190         struct drm_device *dev = crtc->dev;
5191         struct drm_i915_private *dev_priv = dev->dev_private;
5192         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5193         int pipe = intel_crtc->pipe;
5194         int plane = intel_crtc->plane;
5195         int num_connectors = 0;
5196         intel_clock_t clock, reduced_clock;
5197         u32 dpll, fp = 0, fp2 = 0;
5198         bool ok, has_reduced_clock = false;
5199         bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5200         struct intel_encoder *encoder;
5201         u32 temp;
5202         int ret;
5203         bool dither;
5204
5205         for_each_encoder_on_crtc(dev, crtc, encoder) {
5206                 switch (encoder->type) {
5207                 case INTEL_OUTPUT_LVDS:
5208                         is_lvds = true;
5209                         break;
5210                 case INTEL_OUTPUT_DISPLAYPORT:
5211                         is_dp = true;
5212                         break;
5213                 case INTEL_OUTPUT_EDP:
5214                         is_dp = true;
5215                         if (!intel_encoder_is_pch_edp(&encoder->base))
5216                                 is_cpu_edp = true;
5217                         break;
5218                 }
5219
5220                 num_connectors++;
5221         }
5222
5223         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5224              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5225
5226         ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5227                                      &has_reduced_clock, &reduced_clock);
5228         if (!ok) {
5229                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5230                 return -EINVAL;
5231         }
5232
5233         /* Ensure that the cursor is valid for the new mode before changing... */
5234         intel_crtc_update_cursor(crtc, true);
5235
5236         /* determine panel color depth */
5237         dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5238                                               adjusted_mode);
5239         if (is_lvds && dev_priv->lvds_dither)
5240                 dither = true;
5241
5242         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5243         if (has_reduced_clock)
5244                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5245                         reduced_clock.m2;
5246
5247         dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
5248
5249         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5250         drm_mode_debug_printmodeline(mode);
5251
5252         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5253         if (!is_cpu_edp) {
5254                 struct intel_pch_pll *pll;
5255
5256                 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5257                 if (pll == NULL) {
5258                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5259                                          pipe);
5260                         return -EINVAL;
5261                 }
5262         } else
5263                 intel_put_pch_pll(intel_crtc);
5264
5265         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5266          * This is an exception to the general rule that mode_set doesn't turn
5267          * things on.
5268          */
5269         if (is_lvds) {
5270                 temp = I915_READ(PCH_LVDS);
5271                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5272                 if (HAS_PCH_CPT(dev)) {
5273                         temp &= ~PORT_TRANS_SEL_MASK;
5274                         temp |= PORT_TRANS_SEL_CPT(pipe);
5275                 } else {
5276                         if (pipe == 1)
5277                                 temp |= LVDS_PIPEB_SELECT;
5278                         else
5279                                 temp &= ~LVDS_PIPEB_SELECT;
5280                 }
5281
5282                 /* set the corresponsding LVDS_BORDER bit */
5283                 temp |= dev_priv->lvds_border_bits;
5284                 /* Set the B0-B3 data pairs corresponding to whether we're going to
5285                  * set the DPLLs for dual-channel mode or not.
5286                  */
5287                 if (clock.p2 == 7)
5288                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5289                 else
5290                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5291
5292                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5293                  * appropriately here, but we need to look more thoroughly into how
5294                  * panels behave in the two modes.
5295                  */
5296                 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5297                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5298                         temp |= LVDS_HSYNC_POLARITY;
5299                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5300                         temp |= LVDS_VSYNC_POLARITY;
5301                 I915_WRITE(PCH_LVDS, temp);
5302         }
5303
5304         if (is_dp && !is_cpu_edp) {
5305                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5306         } else {
5307                 /* For non-DP output, clear any trans DP clock recovery setting.*/
5308                 I915_WRITE(TRANSDATA_M1(pipe), 0);
5309                 I915_WRITE(TRANSDATA_N1(pipe), 0);
5310                 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5311                 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5312         }
5313
5314         if (intel_crtc->pch_pll) {
5315                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5316
5317                 /* Wait for the clocks to stabilize. */
5318                 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5319                 udelay(150);
5320
5321                 /* The pixel multiplier can only be updated once the
5322                  * DPLL is enabled and the clocks are stable.
5323                  *
5324                  * So write it again.
5325                  */
5326                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5327         }
5328
5329         intel_crtc->lowfreq_avail = false;
5330         if (intel_crtc->pch_pll) {
5331                 if (is_lvds && has_reduced_clock && i915_powersave) {
5332                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5333                         intel_crtc->lowfreq_avail = true;
5334                 } else {
5335                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5336                 }
5337         }
5338
5339         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5340
5341         ironlake_set_m_n(crtc, mode, adjusted_mode);
5342
5343         if (is_cpu_edp)
5344                 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5345
5346         ironlake_set_pipeconf(crtc, adjusted_mode, dither);
5347
5348         intel_wait_for_vblank(dev, pipe);
5349
5350         /* Set up the display plane register */
5351         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5352         POSTING_READ(DSPCNTR(plane));
5353
5354         ret = intel_pipe_set_base(crtc, x, y, fb);
5355
5356         intel_update_watermarks(dev);
5357
5358         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5359
5360         return ret;
5361 }
5362
5363 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5364                                  struct drm_display_mode *mode,
5365                                  struct drm_display_mode *adjusted_mode,
5366                                  int x, int y,
5367                                  struct drm_framebuffer *fb)
5368 {
5369         struct drm_device *dev = crtc->dev;
5370         struct drm_i915_private *dev_priv = dev->dev_private;
5371         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5372         int pipe = intel_crtc->pipe;
5373         int plane = intel_crtc->plane;
5374         int num_connectors = 0;
5375         intel_clock_t clock, reduced_clock;
5376         u32 dpll = 0, fp = 0, fp2 = 0;
5377         bool ok, has_reduced_clock = false;
5378         bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5379         struct intel_encoder *encoder;
5380         u32 temp;
5381         int ret;
5382         bool dither;
5383
5384         for_each_encoder_on_crtc(dev, crtc, encoder) {
5385                 switch (encoder->type) {
5386                 case INTEL_OUTPUT_LVDS:
5387                         is_lvds = true;
5388                         break;
5389                 case INTEL_OUTPUT_DISPLAYPORT:
5390                         is_dp = true;
5391                         break;
5392                 case INTEL_OUTPUT_EDP:
5393                         is_dp = true;
5394                         if (!intel_encoder_is_pch_edp(&encoder->base))
5395                                 is_cpu_edp = true;
5396                         break;
5397                 }
5398
5399                 num_connectors++;
5400         }
5401
5402         if (is_cpu_edp)
5403                 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5404         else
5405                 intel_crtc->cpu_transcoder = pipe;
5406
5407         /* We are not sure yet this won't happen. */
5408         WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5409              INTEL_PCH_TYPE(dev));
5410
5411         WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5412              num_connectors, pipe_name(pipe));
5413
5414         WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
5415                 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5416
5417         WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5418
5419         if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5420                 return -EINVAL;
5421
5422         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5423                 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5424                                              &has_reduced_clock,
5425                                              &reduced_clock);
5426                 if (!ok) {
5427                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
5428                         return -EINVAL;
5429                 }
5430         }
5431
5432         /* Ensure that the cursor is valid for the new mode before changing... */
5433         intel_crtc_update_cursor(crtc, true);
5434
5435         /* determine panel color depth */
5436         dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5437                                               adjusted_mode);
5438         if (is_lvds && dev_priv->lvds_dither)
5439                 dither = true;
5440
5441         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5442         drm_mode_debug_printmodeline(mode);
5443
5444         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5445                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5446                 if (has_reduced_clock)
5447                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5448                               reduced_clock.m2;
5449
5450                 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock,
5451                                              fp);
5452
5453                 /* CPU eDP is the only output that doesn't need a PCH PLL of its
5454                  * own on pre-Haswell/LPT generation */
5455                 if (!is_cpu_edp) {
5456                         struct intel_pch_pll *pll;
5457
5458                         pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5459                         if (pll == NULL) {
5460                                 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5461                                                  pipe);
5462                                 return -EINVAL;
5463                         }
5464                 } else
5465                         intel_put_pch_pll(intel_crtc);
5466
5467                 /* The LVDS pin pair needs to be on before the DPLLs are
5468                  * enabled.  This is an exception to the general rule that
5469                  * mode_set doesn't turn things on.
5470                  */
5471                 if (is_lvds) {
5472                         temp = I915_READ(PCH_LVDS);
5473                         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5474                         if (HAS_PCH_CPT(dev)) {
5475                                 temp &= ~PORT_TRANS_SEL_MASK;
5476                                 temp |= PORT_TRANS_SEL_CPT(pipe);
5477                         } else {
5478                                 if (pipe == 1)
5479                                         temp |= LVDS_PIPEB_SELECT;
5480                                 else
5481                                         temp &= ~LVDS_PIPEB_SELECT;
5482                         }
5483
5484                         /* set the corresponsding LVDS_BORDER bit */
5485                         temp |= dev_priv->lvds_border_bits;
5486                         /* Set the B0-B3 data pairs corresponding to whether
5487                          * we're going to set the DPLLs for dual-channel mode or
5488                          * not.
5489                          */
5490                         if (clock.p2 == 7)
5491                                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5492                         else
5493                                 temp &= ~(LVDS_B0B3_POWER_UP |
5494                                           LVDS_CLKB_POWER_UP);
5495
5496                         /* It would be nice to set 24 vs 18-bit mode
5497                          * (LVDS_A3_POWER_UP) appropriately here, but we need to
5498                          * look more thoroughly into how panels behave in the
5499                          * two modes.
5500                          */
5501                         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5502                         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5503                                 temp |= LVDS_HSYNC_POLARITY;
5504                         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5505                                 temp |= LVDS_VSYNC_POLARITY;
5506                         I915_WRITE(PCH_LVDS, temp);
5507                 }
5508         }
5509
5510         if (is_dp && !is_cpu_edp) {
5511                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5512         } else {
5513                 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5514                         /* For non-DP output, clear any trans DP clock recovery
5515                          * setting.*/
5516                         I915_WRITE(TRANSDATA_M1(pipe), 0);
5517                         I915_WRITE(TRANSDATA_N1(pipe), 0);
5518                         I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5519                         I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5520                 }
5521         }
5522
5523         intel_crtc->lowfreq_avail = false;
5524         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5525                 if (intel_crtc->pch_pll) {
5526                         I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5527
5528                         /* Wait for the clocks to stabilize. */
5529                         POSTING_READ(intel_crtc->pch_pll->pll_reg);
5530                         udelay(150);
5531
5532                         /* The pixel multiplier can only be updated once the
5533                          * DPLL is enabled and the clocks are stable.
5534                          *
5535                          * So write it again.
5536                          */
5537                         I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5538                 }
5539
5540                 if (intel_crtc->pch_pll) {
5541                         if (is_lvds && has_reduced_clock && i915_powersave) {
5542                                 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5543                                 intel_crtc->lowfreq_avail = true;
5544                         } else {
5545                                 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5546                         }
5547                 }
5548         }
5549
5550         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5551
5552         if (!is_dp || is_cpu_edp)
5553                 ironlake_set_m_n(crtc, mode, adjusted_mode);
5554
5555         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5556                 if (is_cpu_edp)
5557                         ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5558
5559         haswell_set_pipeconf(crtc, adjusted_mode, dither);
5560
5561         /* Set up the display plane register */
5562         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5563         POSTING_READ(DSPCNTR(plane));
5564
5565         ret = intel_pipe_set_base(crtc, x, y, fb);
5566
5567         intel_update_watermarks(dev);
5568
5569         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5570
5571         return ret;
5572 }
5573
5574 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5575                                struct drm_display_mode *mode,
5576                                struct drm_display_mode *adjusted_mode,
5577                                int x, int y,
5578                                struct drm_framebuffer *fb)
5579 {
5580         struct drm_device *dev = crtc->dev;
5581         struct drm_i915_private *dev_priv = dev->dev_private;
5582         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5583         int pipe = intel_crtc->pipe;
5584         int ret;
5585
5586         drm_vblank_pre_modeset(dev, pipe);
5587
5588         ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5589                                               x, y, fb);
5590         drm_vblank_post_modeset(dev, pipe);
5591
5592         return ret;
5593 }
5594
5595 static bool intel_eld_uptodate(struct drm_connector *connector,
5596                                int reg_eldv, uint32_t bits_eldv,
5597                                int reg_elda, uint32_t bits_elda,
5598                                int reg_edid)
5599 {
5600         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5601         uint8_t *eld = connector->eld;
5602         uint32_t i;
5603
5604         i = I915_READ(reg_eldv);
5605         i &= bits_eldv;
5606
5607         if (!eld[0])
5608                 return !i;
5609
5610         if (!i)
5611                 return false;
5612
5613         i = I915_READ(reg_elda);
5614         i &= ~bits_elda;
5615         I915_WRITE(reg_elda, i);
5616
5617         for (i = 0; i < eld[2]; i++)
5618                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5619                         return false;
5620
5621         return true;
5622 }
5623
5624 static void g4x_write_eld(struct drm_connector *connector,
5625                           struct drm_crtc *crtc)
5626 {
5627         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5628         uint8_t *eld = connector->eld;
5629         uint32_t eldv;
5630         uint32_t len;
5631         uint32_t i;
5632
5633         i = I915_READ(G4X_AUD_VID_DID);
5634
5635         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5636                 eldv = G4X_ELDV_DEVCL_DEVBLC;
5637         else
5638                 eldv = G4X_ELDV_DEVCTG;
5639
5640         if (intel_eld_uptodate(connector,
5641                                G4X_AUD_CNTL_ST, eldv,
5642                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5643                                G4X_HDMIW_HDMIEDID))
5644                 return;
5645
5646         i = I915_READ(G4X_AUD_CNTL_ST);
5647         i &= ~(eldv | G4X_ELD_ADDR);
5648         len = (i >> 9) & 0x1f;          /* ELD buffer size */
5649         I915_WRITE(G4X_AUD_CNTL_ST, i);
5650
5651         if (!eld[0])
5652                 return;
5653
5654         len = min_t(uint8_t, eld[2], len);
5655         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5656         for (i = 0; i < len; i++)
5657                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5658
5659         i = I915_READ(G4X_AUD_CNTL_ST);
5660         i |= eldv;
5661         I915_WRITE(G4X_AUD_CNTL_ST, i);
5662 }
5663
5664 static void haswell_write_eld(struct drm_connector *connector,
5665                                      struct drm_crtc *crtc)
5666 {
5667         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5668         uint8_t *eld = connector->eld;
5669         struct drm_device *dev = crtc->dev;
5670         uint32_t eldv;
5671         uint32_t i;
5672         int len;
5673         int pipe = to_intel_crtc(crtc)->pipe;
5674         int tmp;
5675
5676         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5677         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5678         int aud_config = HSW_AUD_CFG(pipe);
5679         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5680
5681
5682         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5683
5684         /* Audio output enable */
5685         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5686         tmp = I915_READ(aud_cntrl_st2);
5687         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5688         I915_WRITE(aud_cntrl_st2, tmp);
5689
5690         /* Wait for 1 vertical blank */
5691         intel_wait_for_vblank(dev, pipe);
5692
5693         /* Set ELD valid state */
5694         tmp = I915_READ(aud_cntrl_st2);
5695         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5696         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5697         I915_WRITE(aud_cntrl_st2, tmp);
5698         tmp = I915_READ(aud_cntrl_st2);
5699         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5700
5701         /* Enable HDMI mode */
5702         tmp = I915_READ(aud_config);
5703         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5704         /* clear N_programing_enable and N_value_index */
5705         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5706         I915_WRITE(aud_config, tmp);
5707
5708         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5709
5710         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5711
5712         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5713                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5714                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
5715                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5716         } else
5717                 I915_WRITE(aud_config, 0);
5718
5719         if (intel_eld_uptodate(connector,
5720                                aud_cntrl_st2, eldv,
5721                                aud_cntl_st, IBX_ELD_ADDRESS,
5722                                hdmiw_hdmiedid))
5723                 return;
5724
5725         i = I915_READ(aud_cntrl_st2);
5726         i &= ~eldv;
5727         I915_WRITE(aud_cntrl_st2, i);
5728
5729         if (!eld[0])
5730                 return;
5731
5732         i = I915_READ(aud_cntl_st);
5733         i &= ~IBX_ELD_ADDRESS;
5734         I915_WRITE(aud_cntl_st, i);
5735         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
5736         DRM_DEBUG_DRIVER("port num:%d\n", i);
5737
5738         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
5739         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5740         for (i = 0; i < len; i++)
5741                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5742
5743         i = I915_READ(aud_cntrl_st2);
5744         i |= eldv;
5745         I915_WRITE(aud_cntrl_st2, i);
5746
5747 }
5748
5749 static void ironlake_write_eld(struct drm_connector *connector,
5750                                      struct drm_crtc *crtc)
5751 {
5752         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5753         uint8_t *eld = connector->eld;
5754         uint32_t eldv;
5755         uint32_t i;
5756         int len;
5757         int hdmiw_hdmiedid;
5758         int aud_config;
5759         int aud_cntl_st;
5760         int aud_cntrl_st2;
5761         int pipe = to_intel_crtc(crtc)->pipe;
5762
5763         if (HAS_PCH_IBX(connector->dev)) {
5764                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
5765                 aud_config = IBX_AUD_CFG(pipe);
5766                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
5767                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
5768         } else {
5769                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
5770                 aud_config = CPT_AUD_CFG(pipe);
5771                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
5772                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
5773         }
5774
5775         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5776
5777         i = I915_READ(aud_cntl_st);
5778         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
5779         if (!i) {
5780                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5781                 /* operate blindly on all ports */
5782                 eldv = IBX_ELD_VALIDB;
5783                 eldv |= IBX_ELD_VALIDB << 4;
5784                 eldv |= IBX_ELD_VALIDB << 8;
5785         } else {
5786                 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
5787                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
5788         }
5789
5790         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5791                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5792                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
5793                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5794         } else
5795                 I915_WRITE(aud_config, 0);
5796
5797         if (intel_eld_uptodate(connector,
5798                                aud_cntrl_st2, eldv,
5799                                aud_cntl_st, IBX_ELD_ADDRESS,
5800                                hdmiw_hdmiedid))
5801                 return;
5802
5803         i = I915_READ(aud_cntrl_st2);
5804         i &= ~eldv;
5805         I915_WRITE(aud_cntrl_st2, i);
5806
5807         if (!eld[0])
5808                 return;
5809
5810         i = I915_READ(aud_cntl_st);
5811         i &= ~IBX_ELD_ADDRESS;
5812         I915_WRITE(aud_cntl_st, i);
5813
5814         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
5815         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5816         for (i = 0; i < len; i++)
5817                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5818
5819         i = I915_READ(aud_cntrl_st2);
5820         i |= eldv;
5821         I915_WRITE(aud_cntrl_st2, i);
5822 }
5823
5824 void intel_write_eld(struct drm_encoder *encoder,
5825                      struct drm_display_mode *mode)
5826 {
5827         struct drm_crtc *crtc = encoder->crtc;
5828         struct drm_connector *connector;
5829         struct drm_device *dev = encoder->dev;
5830         struct drm_i915_private *dev_priv = dev->dev_private;
5831
5832         connector = drm_select_eld(encoder, mode);
5833         if (!connector)
5834                 return;
5835
5836         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5837                          connector->base.id,
5838                          drm_get_connector_name(connector),
5839                          connector->encoder->base.id,
5840                          drm_get_encoder_name(connector->encoder));
5841
5842         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
5843
5844         if (dev_priv->display.write_eld)
5845                 dev_priv->display.write_eld(connector, crtc);
5846 }
5847
5848 /** Loads the palette/gamma unit for the CRTC with the prepared values */
5849 void intel_crtc_load_lut(struct drm_crtc *crtc)
5850 {
5851         struct drm_device *dev = crtc->dev;
5852         struct drm_i915_private *dev_priv = dev->dev_private;
5853         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5854         int palreg = PALETTE(intel_crtc->pipe);
5855         int i;
5856
5857         /* The clocks have to be on to load the palette. */
5858         if (!crtc->enabled || !intel_crtc->active)
5859                 return;
5860
5861         /* use legacy palette for Ironlake */
5862         if (HAS_PCH_SPLIT(dev))
5863                 palreg = LGC_PALETTE(intel_crtc->pipe);
5864
5865         for (i = 0; i < 256; i++) {
5866                 I915_WRITE(palreg + 4 * i,
5867                            (intel_crtc->lut_r[i] << 16) |
5868                            (intel_crtc->lut_g[i] << 8) |
5869                            intel_crtc->lut_b[i]);
5870         }
5871 }
5872
5873 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5874 {
5875         struct drm_device *dev = crtc->dev;
5876         struct drm_i915_private *dev_priv = dev->dev_private;
5877         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5878         bool visible = base != 0;
5879         u32 cntl;
5880
5881         if (intel_crtc->cursor_visible == visible)
5882                 return;
5883
5884         cntl = I915_READ(_CURACNTR);
5885         if (visible) {
5886                 /* On these chipsets we can only modify the base whilst
5887                  * the cursor is disabled.
5888                  */
5889                 I915_WRITE(_CURABASE, base);
5890
5891                 cntl &= ~(CURSOR_FORMAT_MASK);
5892                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5893                 cntl |= CURSOR_ENABLE |
5894                         CURSOR_GAMMA_ENABLE |
5895                         CURSOR_FORMAT_ARGB;
5896         } else
5897                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
5898         I915_WRITE(_CURACNTR, cntl);
5899
5900         intel_crtc->cursor_visible = visible;
5901 }
5902
5903 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5904 {
5905         struct drm_device *dev = crtc->dev;
5906         struct drm_i915_private *dev_priv = dev->dev_private;
5907         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5908         int pipe = intel_crtc->pipe;
5909         bool visible = base != 0;
5910
5911         if (intel_crtc->cursor_visible != visible) {
5912                 uint32_t cntl = I915_READ(CURCNTR(pipe));
5913                 if (base) {
5914                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5915                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5916                         cntl |= pipe << 28; /* Connect to correct pipe */
5917                 } else {
5918                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5919                         cntl |= CURSOR_MODE_DISABLE;
5920                 }
5921                 I915_WRITE(CURCNTR(pipe), cntl);
5922
5923                 intel_crtc->cursor_visible = visible;
5924         }
5925         /* and commit changes on next vblank */
5926         I915_WRITE(CURBASE(pipe), base);
5927 }
5928
5929 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
5930 {
5931         struct drm_device *dev = crtc->dev;
5932         struct drm_i915_private *dev_priv = dev->dev_private;
5933         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5934         int pipe = intel_crtc->pipe;
5935         bool visible = base != 0;
5936
5937         if (intel_crtc->cursor_visible != visible) {
5938                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
5939                 if (base) {
5940                         cntl &= ~CURSOR_MODE;
5941                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5942                 } else {
5943                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5944                         cntl |= CURSOR_MODE_DISABLE;
5945                 }
5946                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
5947
5948                 intel_crtc->cursor_visible = visible;
5949         }
5950         /* and commit changes on next vblank */
5951         I915_WRITE(CURBASE_IVB(pipe), base);
5952 }
5953
5954 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
5955 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5956                                      bool on)
5957 {
5958         struct drm_device *dev = crtc->dev;
5959         struct drm_i915_private *dev_priv = dev->dev_private;
5960         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5961         int pipe = intel_crtc->pipe;
5962         int x = intel_crtc->cursor_x;
5963         int y = intel_crtc->cursor_y;
5964         u32 base, pos;
5965         bool visible;
5966
5967         pos = 0;
5968
5969         if (on && crtc->enabled && crtc->fb) {
5970                 base = intel_crtc->cursor_addr;
5971                 if (x > (int) crtc->fb->width)
5972                         base = 0;
5973
5974                 if (y > (int) crtc->fb->height)
5975                         base = 0;
5976         } else
5977                 base = 0;
5978
5979         if (x < 0) {
5980                 if (x + intel_crtc->cursor_width < 0)
5981                         base = 0;
5982
5983                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5984                 x = -x;
5985         }
5986         pos |= x << CURSOR_X_SHIFT;
5987
5988         if (y < 0) {
5989                 if (y + intel_crtc->cursor_height < 0)
5990                         base = 0;
5991
5992                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5993                 y = -y;
5994         }
5995         pos |= y << CURSOR_Y_SHIFT;
5996
5997         visible = base != 0;
5998         if (!visible && !intel_crtc->cursor_visible)
5999                 return;
6000
6001         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6002                 I915_WRITE(CURPOS_IVB(pipe), pos);
6003                 ivb_update_cursor(crtc, base);
6004         } else {
6005                 I915_WRITE(CURPOS(pipe), pos);
6006                 if (IS_845G(dev) || IS_I865G(dev))
6007                         i845_update_cursor(crtc, base);
6008                 else
6009                         i9xx_update_cursor(crtc, base);
6010         }
6011 }
6012
6013 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6014                                  struct drm_file *file,
6015                                  uint32_t handle,
6016                                  uint32_t width, uint32_t height)
6017 {
6018         struct drm_device *dev = crtc->dev;
6019         struct drm_i915_private *dev_priv = dev->dev_private;
6020         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6021         struct drm_i915_gem_object *obj;
6022         uint32_t addr;
6023         int ret;
6024
6025         /* if we want to turn off the cursor ignore width and height */
6026         if (!handle) {
6027                 DRM_DEBUG_KMS("cursor off\n");
6028                 addr = 0;
6029                 obj = NULL;
6030                 mutex_lock(&dev->struct_mutex);
6031                 goto finish;
6032         }
6033
6034         /* Currently we only support 64x64 cursors */
6035         if (width != 64 || height != 64) {
6036                 DRM_ERROR("we currently only support 64x64 cursors\n");
6037                 return -EINVAL;
6038         }
6039
6040         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6041         if (&obj->base == NULL)
6042                 return -ENOENT;
6043
6044         if (obj->base.size < width * height * 4) {
6045                 DRM_ERROR("buffer is to small\n");
6046                 ret = -ENOMEM;
6047                 goto fail;
6048         }
6049
6050         /* we only need to pin inside GTT if cursor is non-phy */
6051         mutex_lock(&dev->struct_mutex);
6052         if (!dev_priv->info->cursor_needs_physical) {
6053                 if (obj->tiling_mode) {
6054                         DRM_ERROR("cursor cannot be tiled\n");
6055                         ret = -EINVAL;
6056                         goto fail_locked;
6057                 }
6058
6059                 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
6060                 if (ret) {
6061                         DRM_ERROR("failed to move cursor bo into the GTT\n");
6062                         goto fail_locked;
6063                 }
6064
6065                 ret = i915_gem_object_put_fence(obj);
6066                 if (ret) {
6067                         DRM_ERROR("failed to release fence for cursor");
6068                         goto fail_unpin;
6069                 }
6070
6071                 addr = obj->gtt_offset;
6072         } else {
6073                 int align = IS_I830(dev) ? 16 * 1024 : 256;
6074                 ret = i915_gem_attach_phys_object(dev, obj,
6075                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6076                                                   align);
6077                 if (ret) {
6078                         DRM_ERROR("failed to attach phys object\n");
6079                         goto fail_locked;
6080                 }
6081                 addr = obj->phys_obj->handle->busaddr;
6082         }
6083
6084         if (IS_GEN2(dev))
6085                 I915_WRITE(CURSIZE, (height << 12) | width);
6086
6087  finish:
6088         if (intel_crtc->cursor_bo) {
6089                 if (dev_priv->info->cursor_needs_physical) {
6090                         if (intel_crtc->cursor_bo != obj)
6091                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6092                 } else
6093                         i915_gem_object_unpin(intel_crtc->cursor_bo);
6094                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6095         }
6096
6097         mutex_unlock(&dev->struct_mutex);
6098
6099         intel_crtc->cursor_addr = addr;
6100         intel_crtc->cursor_bo = obj;
6101         intel_crtc->cursor_width = width;
6102         intel_crtc->cursor_height = height;
6103
6104         intel_crtc_update_cursor(crtc, true);
6105
6106         return 0;
6107 fail_unpin:
6108         i915_gem_object_unpin(obj);
6109 fail_locked:
6110         mutex_unlock(&dev->struct_mutex);
6111 fail:
6112         drm_gem_object_unreference_unlocked(&obj->base);
6113         return ret;
6114 }
6115
6116 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6117 {
6118         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6119
6120         intel_crtc->cursor_x = x;
6121         intel_crtc->cursor_y = y;
6122
6123         intel_crtc_update_cursor(crtc, true);
6124
6125         return 0;
6126 }
6127
6128 /** Sets the color ramps on behalf of RandR */
6129 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6130                                  u16 blue, int regno)
6131 {
6132         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6133
6134         intel_crtc->lut_r[regno] = red >> 8;
6135         intel_crtc->lut_g[regno] = green >> 8;
6136         intel_crtc->lut_b[regno] = blue >> 8;
6137 }
6138
6139 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6140                              u16 *blue, int regno)
6141 {
6142         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6143
6144         *red = intel_crtc->lut_r[regno] << 8;
6145         *green = intel_crtc->lut_g[regno] << 8;
6146         *blue = intel_crtc->lut_b[regno] << 8;
6147 }
6148
6149 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6150                                  u16 *blue, uint32_t start, uint32_t size)
6151 {
6152         int end = (start + size > 256) ? 256 : start + size, i;
6153         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6154
6155         for (i = start; i < end; i++) {
6156                 intel_crtc->lut_r[i] = red[i] >> 8;
6157                 intel_crtc->lut_g[i] = green[i] >> 8;
6158                 intel_crtc->lut_b[i] = blue[i] >> 8;
6159         }
6160
6161         intel_crtc_load_lut(crtc);
6162 }
6163
6164 /**
6165  * Get a pipe with a simple mode set on it for doing load-based monitor
6166  * detection.
6167  *
6168  * It will be up to the load-detect code to adjust the pipe as appropriate for
6169  * its requirements.  The pipe will be connected to no other encoders.
6170  *
6171  * Currently this code will only succeed if there is a pipe with no encoders
6172  * configured for it.  In the future, it could choose to temporarily disable
6173  * some outputs to free up a pipe for its use.
6174  *
6175  * \return crtc, or NULL if no pipes are available.
6176  */
6177
6178 /* VESA 640x480x72Hz mode to set on the pipe */
6179 static struct drm_display_mode load_detect_mode = {
6180         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6181                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6182 };
6183
6184 static struct drm_framebuffer *
6185 intel_framebuffer_create(struct drm_device *dev,
6186                          struct drm_mode_fb_cmd2 *mode_cmd,
6187                          struct drm_i915_gem_object *obj)
6188 {
6189         struct intel_framebuffer *intel_fb;
6190         int ret;
6191
6192         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6193         if (!intel_fb) {
6194                 drm_gem_object_unreference_unlocked(&obj->base);
6195                 return ERR_PTR(-ENOMEM);
6196         }
6197
6198         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6199         if (ret) {
6200                 drm_gem_object_unreference_unlocked(&obj->base);
6201                 kfree(intel_fb);
6202                 return ERR_PTR(ret);
6203         }
6204
6205         return &intel_fb->base;
6206 }
6207
6208 static u32
6209 intel_framebuffer_pitch_for_width(int width, int bpp)
6210 {
6211         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6212         return ALIGN(pitch, 64);
6213 }
6214
6215 static u32
6216 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6217 {
6218         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6219         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6220 }
6221
6222 static struct drm_framebuffer *
6223 intel_framebuffer_create_for_mode(struct drm_device *dev,
6224                                   struct drm_display_mode *mode,
6225                                   int depth, int bpp)
6226 {
6227         struct drm_i915_gem_object *obj;
6228         struct drm_mode_fb_cmd2 mode_cmd;
6229
6230         obj = i915_gem_alloc_object(dev,
6231                                     intel_framebuffer_size_for_mode(mode, bpp));
6232         if (obj == NULL)
6233                 return ERR_PTR(-ENOMEM);
6234
6235         mode_cmd.width = mode->hdisplay;
6236         mode_cmd.height = mode->vdisplay;
6237         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6238                                                                 bpp);
6239         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6240
6241         return intel_framebuffer_create(dev, &mode_cmd, obj);
6242 }
6243
6244 static struct drm_framebuffer *
6245 mode_fits_in_fbdev(struct drm_device *dev,
6246                    struct drm_display_mode *mode)
6247 {
6248         struct drm_i915_private *dev_priv = dev->dev_private;
6249         struct drm_i915_gem_object *obj;
6250         struct drm_framebuffer *fb;
6251
6252         if (dev_priv->fbdev == NULL)
6253                 return NULL;
6254
6255         obj = dev_priv->fbdev->ifb.obj;
6256         if (obj == NULL)
6257                 return NULL;
6258
6259         fb = &dev_priv->fbdev->ifb.base;
6260         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6261                                                                fb->bits_per_pixel))
6262                 return NULL;
6263
6264         if (obj->base.size < mode->vdisplay * fb->pitches[0])
6265                 return NULL;
6266
6267         return fb;
6268 }
6269
6270 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6271                                 struct drm_display_mode *mode,
6272                                 struct intel_load_detect_pipe *old)
6273 {
6274         struct intel_crtc *intel_crtc;
6275         struct intel_encoder *intel_encoder =
6276                 intel_attached_encoder(connector);
6277         struct drm_crtc *possible_crtc;
6278         struct drm_encoder *encoder = &intel_encoder->base;
6279         struct drm_crtc *crtc = NULL;
6280         struct drm_device *dev = encoder->dev;
6281         struct drm_framebuffer *fb;
6282         int i = -1;
6283
6284         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6285                       connector->base.id, drm_get_connector_name(connector),
6286                       encoder->base.id, drm_get_encoder_name(encoder));
6287
6288         /*
6289          * Algorithm gets a little messy:
6290          *
6291          *   - if the connector already has an assigned crtc, use it (but make
6292          *     sure it's on first)
6293          *
6294          *   - try to find the first unused crtc that can drive this connector,
6295          *     and use that if we find one
6296          */
6297
6298         /* See if we already have a CRTC for this connector */
6299         if (encoder->crtc) {
6300                 crtc = encoder->crtc;
6301
6302                 old->dpms_mode = connector->dpms;
6303                 old->load_detect_temp = false;
6304
6305                 /* Make sure the crtc and connector are running */
6306                 if (connector->dpms != DRM_MODE_DPMS_ON)
6307                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6308
6309                 return true;
6310         }
6311
6312         /* Find an unused one (if possible) */
6313         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6314                 i++;
6315                 if (!(encoder->possible_crtcs & (1 << i)))
6316                         continue;
6317                 if (!possible_crtc->enabled) {
6318                         crtc = possible_crtc;
6319                         break;
6320                 }
6321         }
6322
6323         /*
6324          * If we didn't find an unused CRTC, don't use any.
6325          */
6326         if (!crtc) {
6327                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6328                 return false;
6329         }
6330
6331         intel_encoder->new_crtc = to_intel_crtc(crtc);
6332         to_intel_connector(connector)->new_encoder = intel_encoder;
6333
6334         intel_crtc = to_intel_crtc(crtc);
6335         old->dpms_mode = connector->dpms;
6336         old->load_detect_temp = true;
6337         old->release_fb = NULL;
6338
6339         if (!mode)
6340                 mode = &load_detect_mode;
6341
6342         /* We need a framebuffer large enough to accommodate all accesses
6343          * that the plane may generate whilst we perform load detection.
6344          * We can not rely on the fbcon either being present (we get called
6345          * during its initialisation to detect all boot displays, or it may
6346          * not even exist) or that it is large enough to satisfy the
6347          * requested mode.
6348          */
6349         fb = mode_fits_in_fbdev(dev, mode);
6350         if (fb == NULL) {
6351                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6352                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6353                 old->release_fb = fb;
6354         } else
6355                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6356         if (IS_ERR(fb)) {
6357                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6358                 goto fail;
6359         }
6360
6361         if (!intel_set_mode(crtc, mode, 0, 0, fb)) {
6362                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6363                 if (old->release_fb)
6364                         old->release_fb->funcs->destroy(old->release_fb);
6365                 goto fail;
6366         }
6367
6368         /* let the connector get through one full cycle before testing */
6369         intel_wait_for_vblank(dev, intel_crtc->pipe);
6370
6371         return true;
6372 fail:
6373         connector->encoder = NULL;
6374         encoder->crtc = NULL;
6375         return false;
6376 }
6377
6378 void intel_release_load_detect_pipe(struct drm_connector *connector,
6379                                     struct intel_load_detect_pipe *old)
6380 {
6381         struct intel_encoder *intel_encoder =
6382                 intel_attached_encoder(connector);
6383         struct drm_encoder *encoder = &intel_encoder->base;
6384
6385         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6386                       connector->base.id, drm_get_connector_name(connector),
6387                       encoder->base.id, drm_get_encoder_name(encoder));
6388
6389         if (old->load_detect_temp) {
6390                 struct drm_crtc *crtc = encoder->crtc;
6391
6392                 to_intel_connector(connector)->new_encoder = NULL;
6393                 intel_encoder->new_crtc = NULL;
6394                 intel_set_mode(crtc, NULL, 0, 0, NULL);
6395
6396                 if (old->release_fb)
6397                         old->release_fb->funcs->destroy(old->release_fb);
6398
6399                 return;
6400         }
6401
6402         /* Switch crtc and encoder back off if necessary */
6403         if (old->dpms_mode != DRM_MODE_DPMS_ON)
6404                 connector->funcs->dpms(connector, old->dpms_mode);
6405 }
6406
6407 /* Returns the clock of the currently programmed mode of the given pipe. */
6408 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6409 {
6410         struct drm_i915_private *dev_priv = dev->dev_private;
6411         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6412         int pipe = intel_crtc->pipe;
6413         u32 dpll = I915_READ(DPLL(pipe));
6414         u32 fp;
6415         intel_clock_t clock;
6416
6417         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6418                 fp = I915_READ(FP0(pipe));
6419         else
6420                 fp = I915_READ(FP1(pipe));
6421
6422         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6423         if (IS_PINEVIEW(dev)) {
6424                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6425                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6426         } else {
6427                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6428                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6429         }
6430
6431         if (!IS_GEN2(dev)) {
6432                 if (IS_PINEVIEW(dev))
6433                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6434                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6435                 else
6436                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6437                                DPLL_FPA01_P1_POST_DIV_SHIFT);
6438
6439                 switch (dpll & DPLL_MODE_MASK) {
6440                 case DPLLB_MODE_DAC_SERIAL:
6441                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6442                                 5 : 10;
6443                         break;
6444                 case DPLLB_MODE_LVDS:
6445                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6446                                 7 : 14;
6447                         break;
6448                 default:
6449                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6450                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
6451                         return 0;
6452                 }
6453
6454                 /* XXX: Handle the 100Mhz refclk */
6455                 intel_clock(dev, 96000, &clock);
6456         } else {
6457                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6458
6459                 if (is_lvds) {
6460                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6461                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
6462                         clock.p2 = 14;
6463
6464                         if ((dpll & PLL_REF_INPUT_MASK) ==
6465                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6466                                 /* XXX: might not be 66MHz */
6467                                 intel_clock(dev, 66000, &clock);
6468                         } else
6469                                 intel_clock(dev, 48000, &clock);
6470                 } else {
6471                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
6472                                 clock.p1 = 2;
6473                         else {
6474                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6475                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6476                         }
6477                         if (dpll & PLL_P2_DIVIDE_BY_4)
6478                                 clock.p2 = 4;
6479                         else
6480                                 clock.p2 = 2;
6481
6482                         intel_clock(dev, 48000, &clock);
6483                 }
6484         }
6485
6486         /* XXX: It would be nice to validate the clocks, but we can't reuse
6487          * i830PllIsValid() because it relies on the xf86_config connector
6488          * configuration being accurate, which it isn't necessarily.
6489          */
6490
6491         return clock.dot;
6492 }
6493
6494 /** Returns the currently programmed mode of the given pipe. */
6495 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6496                                              struct drm_crtc *crtc)
6497 {
6498         struct drm_i915_private *dev_priv = dev->dev_private;
6499         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6500         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
6501         struct drm_display_mode *mode;
6502         int htot = I915_READ(HTOTAL(cpu_transcoder));
6503         int hsync = I915_READ(HSYNC(cpu_transcoder));
6504         int vtot = I915_READ(VTOTAL(cpu_transcoder));
6505         int vsync = I915_READ(VSYNC(cpu_transcoder));
6506
6507         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6508         if (!mode)
6509                 return NULL;
6510
6511         mode->clock = intel_crtc_clock_get(dev, crtc);
6512         mode->hdisplay = (htot & 0xffff) + 1;
6513         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6514         mode->hsync_start = (hsync & 0xffff) + 1;
6515         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6516         mode->vdisplay = (vtot & 0xffff) + 1;
6517         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6518         mode->vsync_start = (vsync & 0xffff) + 1;
6519         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6520
6521         drm_mode_set_name(mode);
6522
6523         return mode;
6524 }
6525
6526 static void intel_increase_pllclock(struct drm_crtc *crtc)
6527 {
6528         struct drm_device *dev = crtc->dev;
6529         drm_i915_private_t *dev_priv = dev->dev_private;
6530         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6531         int pipe = intel_crtc->pipe;
6532         int dpll_reg = DPLL(pipe);
6533         int dpll;
6534
6535         if (HAS_PCH_SPLIT(dev))
6536                 return;
6537
6538         if (!dev_priv->lvds_downclock_avail)
6539                 return;
6540
6541         dpll = I915_READ(dpll_reg);
6542         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6543                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6544
6545                 assert_panel_unlocked(dev_priv, pipe);
6546
6547                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6548                 I915_WRITE(dpll_reg, dpll);
6549                 intel_wait_for_vblank(dev, pipe);
6550
6551                 dpll = I915_READ(dpll_reg);
6552                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6553                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6554         }
6555 }
6556
6557 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6558 {
6559         struct drm_device *dev = crtc->dev;
6560         drm_i915_private_t *dev_priv = dev->dev_private;
6561         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6562
6563         if (HAS_PCH_SPLIT(dev))
6564                 return;
6565
6566         if (!dev_priv->lvds_downclock_avail)
6567                 return;
6568
6569         /*
6570          * Since this is called by a timer, we should never get here in
6571          * the manual case.
6572          */
6573         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6574                 int pipe = intel_crtc->pipe;
6575                 int dpll_reg = DPLL(pipe);
6576                 int dpll;
6577
6578                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6579
6580                 assert_panel_unlocked(dev_priv, pipe);
6581
6582                 dpll = I915_READ(dpll_reg);
6583                 dpll |= DISPLAY_RATE_SELECT_FPA1;
6584                 I915_WRITE(dpll_reg, dpll);
6585                 intel_wait_for_vblank(dev, pipe);
6586                 dpll = I915_READ(dpll_reg);
6587                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6588                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6589         }
6590
6591 }
6592
6593 void intel_mark_busy(struct drm_device *dev)
6594 {
6595         i915_update_gfx_val(dev->dev_private);
6596 }
6597
6598 void intel_mark_idle(struct drm_device *dev)
6599 {
6600 }
6601
6602 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6603 {
6604         struct drm_device *dev = obj->base.dev;
6605         struct drm_crtc *crtc;
6606
6607         if (!i915_powersave)
6608                 return;
6609
6610         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6611                 if (!crtc->fb)
6612                         continue;
6613
6614                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6615                         intel_increase_pllclock(crtc);
6616         }
6617 }
6618
6619 void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
6620 {
6621         struct drm_device *dev = obj->base.dev;
6622         struct drm_crtc *crtc;
6623
6624         if (!i915_powersave)
6625                 return;
6626
6627         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6628                 if (!crtc->fb)
6629                         continue;
6630
6631                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6632                         intel_decrease_pllclock(crtc);
6633         }
6634 }
6635
6636 static void intel_crtc_destroy(struct drm_crtc *crtc)
6637 {
6638         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6639         struct drm_device *dev = crtc->dev;
6640         struct intel_unpin_work *work;
6641         unsigned long flags;
6642
6643         spin_lock_irqsave(&dev->event_lock, flags);
6644         work = intel_crtc->unpin_work;
6645         intel_crtc->unpin_work = NULL;
6646         spin_unlock_irqrestore(&dev->event_lock, flags);
6647
6648         if (work) {
6649                 cancel_work_sync(&work->work);
6650                 kfree(work);
6651         }
6652
6653         drm_crtc_cleanup(crtc);
6654
6655         kfree(intel_crtc);
6656 }
6657
6658 static void intel_unpin_work_fn(struct work_struct *__work)
6659 {
6660         struct intel_unpin_work *work =
6661                 container_of(__work, struct intel_unpin_work, work);
6662
6663         mutex_lock(&work->dev->struct_mutex);
6664         intel_unpin_fb_obj(work->old_fb_obj);
6665         drm_gem_object_unreference(&work->pending_flip_obj->base);
6666         drm_gem_object_unreference(&work->old_fb_obj->base);
6667
6668         intel_update_fbc(work->dev);
6669         mutex_unlock(&work->dev->struct_mutex);
6670         kfree(work);
6671 }
6672
6673 static void do_intel_finish_page_flip(struct drm_device *dev,
6674                                       struct drm_crtc *crtc)
6675 {
6676         drm_i915_private_t *dev_priv = dev->dev_private;
6677         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6678         struct intel_unpin_work *work;
6679         struct drm_i915_gem_object *obj;
6680         struct drm_pending_vblank_event *e;
6681         struct timeval tvbl;
6682         unsigned long flags;
6683
6684         /* Ignore early vblank irqs */
6685         if (intel_crtc == NULL)
6686                 return;
6687
6688         spin_lock_irqsave(&dev->event_lock, flags);
6689         work = intel_crtc->unpin_work;
6690         if (work == NULL || !work->pending) {
6691                 spin_unlock_irqrestore(&dev->event_lock, flags);
6692                 return;
6693         }
6694
6695         intel_crtc->unpin_work = NULL;
6696
6697         if (work->event) {
6698                 e = work->event;
6699                 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
6700
6701                 e->event.tv_sec = tvbl.tv_sec;
6702                 e->event.tv_usec = tvbl.tv_usec;
6703
6704                 list_add_tail(&e->base.link,
6705                               &e->base.file_priv->event_list);
6706                 wake_up_interruptible(&e->base.file_priv->event_wait);
6707         }
6708
6709         drm_vblank_put(dev, intel_crtc->pipe);
6710
6711         spin_unlock_irqrestore(&dev->event_lock, flags);
6712
6713         obj = work->old_fb_obj;
6714
6715         atomic_clear_mask(1 << intel_crtc->plane,
6716                           &obj->pending_flip.counter);
6717
6718         wake_up(&dev_priv->pending_flip_queue);
6719         schedule_work(&work->work);
6720
6721         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6722 }
6723
6724 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6725 {
6726         drm_i915_private_t *dev_priv = dev->dev_private;
6727         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6728
6729         do_intel_finish_page_flip(dev, crtc);
6730 }
6731
6732 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6733 {
6734         drm_i915_private_t *dev_priv = dev->dev_private;
6735         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6736
6737         do_intel_finish_page_flip(dev, crtc);
6738 }
6739
6740 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6741 {
6742         drm_i915_private_t *dev_priv = dev->dev_private;
6743         struct intel_crtc *intel_crtc =
6744                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6745         unsigned long flags;
6746
6747         spin_lock_irqsave(&dev->event_lock, flags);
6748         if (intel_crtc->unpin_work) {
6749                 if ((++intel_crtc->unpin_work->pending) > 1)
6750                         DRM_ERROR("Prepared flip multiple times\n");
6751         } else {
6752                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6753         }
6754         spin_unlock_irqrestore(&dev->event_lock, flags);
6755 }
6756
6757 static int intel_gen2_queue_flip(struct drm_device *dev,
6758                                  struct drm_crtc *crtc,
6759                                  struct drm_framebuffer *fb,
6760                                  struct drm_i915_gem_object *obj)
6761 {
6762         struct drm_i915_private *dev_priv = dev->dev_private;
6763         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6764         u32 flip_mask;
6765         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6766         int ret;
6767
6768         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6769         if (ret)
6770                 goto err;
6771
6772         ret = intel_ring_begin(ring, 6);
6773         if (ret)
6774                 goto err_unpin;
6775
6776         /* Can't queue multiple flips, so wait for the previous
6777          * one to finish before executing the next.
6778          */
6779         if (intel_crtc->plane)
6780                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6781         else
6782                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6783         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6784         intel_ring_emit(ring, MI_NOOP);
6785         intel_ring_emit(ring, MI_DISPLAY_FLIP |
6786                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6787         intel_ring_emit(ring, fb->pitches[0]);
6788         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6789         intel_ring_emit(ring, 0); /* aux display base address, unused */
6790         intel_ring_advance(ring);
6791         return 0;
6792
6793 err_unpin:
6794         intel_unpin_fb_obj(obj);
6795 err:
6796         return ret;
6797 }
6798
6799 static int intel_gen3_queue_flip(struct drm_device *dev,
6800                                  struct drm_crtc *crtc,
6801                                  struct drm_framebuffer *fb,
6802                                  struct drm_i915_gem_object *obj)
6803 {
6804         struct drm_i915_private *dev_priv = dev->dev_private;
6805         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6806         u32 flip_mask;
6807         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6808         int ret;
6809
6810         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6811         if (ret)
6812                 goto err;
6813
6814         ret = intel_ring_begin(ring, 6);
6815         if (ret)
6816                 goto err_unpin;
6817
6818         if (intel_crtc->plane)
6819                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6820         else
6821                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6822         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6823         intel_ring_emit(ring, MI_NOOP);
6824         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
6825                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6826         intel_ring_emit(ring, fb->pitches[0]);
6827         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6828         intel_ring_emit(ring, MI_NOOP);
6829
6830         intel_ring_advance(ring);
6831         return 0;
6832
6833 err_unpin:
6834         intel_unpin_fb_obj(obj);
6835 err:
6836         return ret;
6837 }
6838
6839 static int intel_gen4_queue_flip(struct drm_device *dev,
6840                                  struct drm_crtc *crtc,
6841                                  struct drm_framebuffer *fb,
6842                                  struct drm_i915_gem_object *obj)
6843 {
6844         struct drm_i915_private *dev_priv = dev->dev_private;
6845         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6846         uint32_t pf, pipesrc;
6847         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6848         int ret;
6849
6850         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6851         if (ret)
6852                 goto err;
6853
6854         ret = intel_ring_begin(ring, 4);
6855         if (ret)
6856                 goto err_unpin;
6857
6858         /* i965+ uses the linear or tiled offsets from the
6859          * Display Registers (which do not change across a page-flip)
6860          * so we need only reprogram the base address.
6861          */
6862         intel_ring_emit(ring, MI_DISPLAY_FLIP |
6863                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6864         intel_ring_emit(ring, fb->pitches[0]);
6865         intel_ring_emit(ring,
6866                         (obj->gtt_offset + intel_crtc->dspaddr_offset) |
6867                         obj->tiling_mode);
6868
6869         /* XXX Enabling the panel-fitter across page-flip is so far
6870          * untested on non-native modes, so ignore it for now.
6871          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6872          */
6873         pf = 0;
6874         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6875         intel_ring_emit(ring, pf | pipesrc);
6876         intel_ring_advance(ring);
6877         return 0;
6878
6879 err_unpin:
6880         intel_unpin_fb_obj(obj);
6881 err:
6882         return ret;
6883 }
6884
6885 static int intel_gen6_queue_flip(struct drm_device *dev,
6886                                  struct drm_crtc *crtc,
6887                                  struct drm_framebuffer *fb,
6888                                  struct drm_i915_gem_object *obj)
6889 {
6890         struct drm_i915_private *dev_priv = dev->dev_private;
6891         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6892         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6893         uint32_t pf, pipesrc;
6894         int ret;
6895
6896         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6897         if (ret)
6898                 goto err;
6899
6900         ret = intel_ring_begin(ring, 4);
6901         if (ret)
6902                 goto err_unpin;
6903
6904         intel_ring_emit(ring, MI_DISPLAY_FLIP |
6905                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6906         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
6907         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6908
6909         /* Contrary to the suggestions in the documentation,
6910          * "Enable Panel Fitter" does not seem to be required when page
6911          * flipping with a non-native mode, and worse causes a normal
6912          * modeset to fail.
6913          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6914          */
6915         pf = 0;
6916         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6917         intel_ring_emit(ring, pf | pipesrc);
6918         intel_ring_advance(ring);
6919         return 0;
6920
6921 err_unpin:
6922         intel_unpin_fb_obj(obj);
6923 err:
6924         return ret;
6925 }
6926
6927 /*
6928  * On gen7 we currently use the blit ring because (in early silicon at least)
6929  * the render ring doesn't give us interrpts for page flip completion, which
6930  * means clients will hang after the first flip is queued.  Fortunately the
6931  * blit ring generates interrupts properly, so use it instead.
6932  */
6933 static int intel_gen7_queue_flip(struct drm_device *dev,
6934                                  struct drm_crtc *crtc,
6935                                  struct drm_framebuffer *fb,
6936                                  struct drm_i915_gem_object *obj)
6937 {
6938         struct drm_i915_private *dev_priv = dev->dev_private;
6939         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6940         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
6941         uint32_t plane_bit = 0;
6942         int ret;
6943
6944         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6945         if (ret)
6946                 goto err;
6947
6948         switch(intel_crtc->plane) {
6949         case PLANE_A:
6950                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
6951                 break;
6952         case PLANE_B:
6953                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
6954                 break;
6955         case PLANE_C:
6956                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
6957                 break;
6958         default:
6959                 WARN_ONCE(1, "unknown plane in flip command\n");
6960                 ret = -ENODEV;
6961                 goto err_unpin;
6962         }
6963
6964         ret = intel_ring_begin(ring, 4);
6965         if (ret)
6966                 goto err_unpin;
6967
6968         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
6969         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
6970         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6971         intel_ring_emit(ring, (MI_NOOP));
6972         intel_ring_advance(ring);
6973         return 0;
6974
6975 err_unpin:
6976         intel_unpin_fb_obj(obj);
6977 err:
6978         return ret;
6979 }
6980
6981 static int intel_default_queue_flip(struct drm_device *dev,
6982                                     struct drm_crtc *crtc,
6983                                     struct drm_framebuffer *fb,
6984                                     struct drm_i915_gem_object *obj)
6985 {
6986         return -ENODEV;
6987 }
6988
6989 static int intel_crtc_page_flip(struct drm_crtc *crtc,
6990                                 struct drm_framebuffer *fb,
6991                                 struct drm_pending_vblank_event *event)
6992 {
6993         struct drm_device *dev = crtc->dev;
6994         struct drm_i915_private *dev_priv = dev->dev_private;
6995         struct intel_framebuffer *intel_fb;
6996         struct drm_i915_gem_object *obj;
6997         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6998         struct intel_unpin_work *work;
6999         unsigned long flags;
7000         int ret;
7001
7002         /* Can't change pixel format via MI display flips. */
7003         if (fb->pixel_format != crtc->fb->pixel_format)
7004                 return -EINVAL;
7005
7006         /*
7007          * TILEOFF/LINOFF registers can't be changed via MI display flips.
7008          * Note that pitch changes could also affect these register.
7009          */
7010         if (INTEL_INFO(dev)->gen > 3 &&
7011             (fb->offsets[0] != crtc->fb->offsets[0] ||
7012              fb->pitches[0] != crtc->fb->pitches[0]))
7013                 return -EINVAL;
7014
7015         work = kzalloc(sizeof *work, GFP_KERNEL);
7016         if (work == NULL)
7017                 return -ENOMEM;
7018
7019         work->event = event;
7020         work->dev = crtc->dev;
7021         intel_fb = to_intel_framebuffer(crtc->fb);
7022         work->old_fb_obj = intel_fb->obj;
7023         INIT_WORK(&work->work, intel_unpin_work_fn);
7024
7025         ret = drm_vblank_get(dev, intel_crtc->pipe);
7026         if (ret)
7027                 goto free_work;
7028
7029         /* We borrow the event spin lock for protecting unpin_work */
7030         spin_lock_irqsave(&dev->event_lock, flags);
7031         if (intel_crtc->unpin_work) {
7032                 spin_unlock_irqrestore(&dev->event_lock, flags);
7033                 kfree(work);
7034                 drm_vblank_put(dev, intel_crtc->pipe);
7035
7036                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7037                 return -EBUSY;
7038         }
7039         intel_crtc->unpin_work = work;
7040         spin_unlock_irqrestore(&dev->event_lock, flags);
7041
7042         intel_fb = to_intel_framebuffer(fb);
7043         obj = intel_fb->obj;
7044
7045         ret = i915_mutex_lock_interruptible(dev);
7046         if (ret)
7047                 goto cleanup;
7048
7049         /* Reference the objects for the scheduled work. */
7050         drm_gem_object_reference(&work->old_fb_obj->base);
7051         drm_gem_object_reference(&obj->base);
7052
7053         crtc->fb = fb;
7054
7055         work->pending_flip_obj = obj;
7056
7057         work->enable_stall_check = true;
7058
7059         /* Block clients from rendering to the new back buffer until
7060          * the flip occurs and the object is no longer visible.
7061          */
7062         atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7063
7064         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7065         if (ret)
7066                 goto cleanup_pending;
7067
7068         intel_disable_fbc(dev);
7069         intel_mark_fb_busy(obj);
7070         mutex_unlock(&dev->struct_mutex);
7071
7072         trace_i915_flip_request(intel_crtc->plane, obj);
7073
7074         return 0;
7075
7076 cleanup_pending:
7077         atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7078         drm_gem_object_unreference(&work->old_fb_obj->base);
7079         drm_gem_object_unreference(&obj->base);
7080         mutex_unlock(&dev->struct_mutex);
7081
7082 cleanup:
7083         spin_lock_irqsave(&dev->event_lock, flags);
7084         intel_crtc->unpin_work = NULL;
7085         spin_unlock_irqrestore(&dev->event_lock, flags);
7086
7087         drm_vblank_put(dev, intel_crtc->pipe);
7088 free_work:
7089         kfree(work);
7090
7091         return ret;
7092 }
7093
7094 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7095         .mode_set_base_atomic = intel_pipe_set_base_atomic,
7096         .load_lut = intel_crtc_load_lut,
7097         .disable = intel_crtc_noop,
7098 };
7099
7100 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
7101 {
7102         struct intel_encoder *other_encoder;
7103         struct drm_crtc *crtc = &encoder->new_crtc->base;
7104
7105         if (WARN_ON(!crtc))
7106                 return false;
7107
7108         list_for_each_entry(other_encoder,
7109                             &crtc->dev->mode_config.encoder_list,
7110                             base.head) {
7111
7112                 if (&other_encoder->new_crtc->base != crtc ||
7113                     encoder == other_encoder)
7114                         continue;
7115                 else
7116                         return true;
7117         }
7118
7119         return false;
7120 }
7121
7122 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7123                                   struct drm_crtc *crtc)
7124 {
7125         struct drm_device *dev;
7126         struct drm_crtc *tmp;
7127         int crtc_mask = 1;
7128
7129         WARN(!crtc, "checking null crtc?\n");
7130
7131         dev = crtc->dev;
7132
7133         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7134                 if (tmp == crtc)
7135                         break;
7136                 crtc_mask <<= 1;
7137         }
7138
7139         if (encoder->possible_crtcs & crtc_mask)
7140                 return true;
7141         return false;
7142 }
7143
7144 /**
7145  * intel_modeset_update_staged_output_state
7146  *
7147  * Updates the staged output configuration state, e.g. after we've read out the
7148  * current hw state.
7149  */
7150 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7151 {
7152         struct intel_encoder *encoder;
7153         struct intel_connector *connector;
7154
7155         list_for_each_entry(connector, &dev->mode_config.connector_list,
7156                             base.head) {
7157                 connector->new_encoder =
7158                         to_intel_encoder(connector->base.encoder);
7159         }
7160
7161         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7162                             base.head) {
7163                 encoder->new_crtc =
7164                         to_intel_crtc(encoder->base.crtc);
7165         }
7166 }
7167
7168 /**
7169  * intel_modeset_commit_output_state
7170  *
7171  * This function copies the stage display pipe configuration to the real one.
7172  */
7173 static void intel_modeset_commit_output_state(struct drm_device *dev)
7174 {
7175         struct intel_encoder *encoder;
7176         struct intel_connector *connector;
7177
7178         list_for_each_entry(connector, &dev->mode_config.connector_list,
7179                             base.head) {
7180                 connector->base.encoder = &connector->new_encoder->base;
7181         }
7182
7183         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7184                             base.head) {
7185                 encoder->base.crtc = &encoder->new_crtc->base;
7186         }
7187 }
7188
7189 static struct drm_display_mode *
7190 intel_modeset_adjusted_mode(struct drm_crtc *crtc,
7191                             struct drm_display_mode *mode)
7192 {
7193         struct drm_device *dev = crtc->dev;
7194         struct drm_display_mode *adjusted_mode;
7195         struct drm_encoder_helper_funcs *encoder_funcs;
7196         struct intel_encoder *encoder;
7197
7198         adjusted_mode = drm_mode_duplicate(dev, mode);
7199         if (!adjusted_mode)
7200                 return ERR_PTR(-ENOMEM);
7201
7202         /* Pass our mode to the connectors and the CRTC to give them a chance to
7203          * adjust it according to limitations or connector properties, and also
7204          * a chance to reject the mode entirely.
7205          */
7206         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7207                             base.head) {
7208
7209                 if (&encoder->new_crtc->base != crtc)
7210                         continue;
7211                 encoder_funcs = encoder->base.helper_private;
7212                 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
7213                                                 adjusted_mode))) {
7214                         DRM_DEBUG_KMS("Encoder fixup failed\n");
7215                         goto fail;
7216                 }
7217         }
7218
7219         if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
7220                 DRM_DEBUG_KMS("CRTC fixup failed\n");
7221                 goto fail;
7222         }
7223         DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7224
7225         return adjusted_mode;
7226 fail:
7227         drm_mode_destroy(dev, adjusted_mode);
7228         return ERR_PTR(-EINVAL);
7229 }
7230
7231 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7232  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7233 static void
7234 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7235                              unsigned *prepare_pipes, unsigned *disable_pipes)
7236 {
7237         struct intel_crtc *intel_crtc;
7238         struct drm_device *dev = crtc->dev;
7239         struct intel_encoder *encoder;
7240         struct intel_connector *connector;
7241         struct drm_crtc *tmp_crtc;
7242
7243         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7244
7245         /* Check which crtcs have changed outputs connected to them, these need
7246          * to be part of the prepare_pipes mask. We don't (yet) support global
7247          * modeset across multiple crtcs, so modeset_pipes will only have one
7248          * bit set at most. */
7249         list_for_each_entry(connector, &dev->mode_config.connector_list,
7250                             base.head) {
7251                 if (connector->base.encoder == &connector->new_encoder->base)
7252                         continue;
7253
7254                 if (connector->base.encoder) {
7255                         tmp_crtc = connector->base.encoder->crtc;
7256
7257                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7258                 }
7259
7260                 if (connector->new_encoder)
7261                         *prepare_pipes |=
7262                                 1 << connector->new_encoder->new_crtc->pipe;
7263         }
7264
7265         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7266                             base.head) {
7267                 if (encoder->base.crtc == &encoder->new_crtc->base)
7268                         continue;
7269
7270                 if (encoder->base.crtc) {
7271                         tmp_crtc = encoder->base.crtc;
7272
7273                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7274                 }
7275
7276                 if (encoder->new_crtc)
7277                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7278         }
7279
7280         /* Check for any pipes that will be fully disabled ... */
7281         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7282                             base.head) {
7283                 bool used = false;
7284
7285                 /* Don't try to disable disabled crtcs. */
7286                 if (!intel_crtc->base.enabled)
7287                         continue;
7288
7289                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7290                                     base.head) {
7291                         if (encoder->new_crtc == intel_crtc)
7292                                 used = true;
7293                 }
7294
7295                 if (!used)
7296                         *disable_pipes |= 1 << intel_crtc->pipe;
7297         }
7298
7299
7300         /* set_mode is also used to update properties on life display pipes. */
7301         intel_crtc = to_intel_crtc(crtc);
7302         if (crtc->enabled)
7303                 *prepare_pipes |= 1 << intel_crtc->pipe;
7304
7305         /* We only support modeset on one single crtc, hence we need to do that
7306          * only for the passed in crtc iff we change anything else than just
7307          * disable crtcs.
7308          *
7309          * This is actually not true, to be fully compatible with the old crtc
7310          * helper we automatically disable _any_ output (i.e. doesn't need to be
7311          * connected to the crtc we're modesetting on) if it's disconnected.
7312          * Which is a rather nutty api (since changed the output configuration
7313          * without userspace's explicit request can lead to confusion), but
7314          * alas. Hence we currently need to modeset on all pipes we prepare. */
7315         if (*prepare_pipes)
7316                 *modeset_pipes = *prepare_pipes;
7317
7318         /* ... and mask these out. */
7319         *modeset_pipes &= ~(*disable_pipes);
7320         *prepare_pipes &= ~(*disable_pipes);
7321 }
7322
7323 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7324 {
7325         struct drm_encoder *encoder;
7326         struct drm_device *dev = crtc->dev;
7327
7328         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7329                 if (encoder->crtc == crtc)
7330                         return true;
7331
7332         return false;
7333 }
7334
7335 static void
7336 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7337 {
7338         struct intel_encoder *intel_encoder;
7339         struct intel_crtc *intel_crtc;
7340         struct drm_connector *connector;
7341
7342         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7343                             base.head) {
7344                 if (!intel_encoder->base.crtc)
7345                         continue;
7346
7347                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7348
7349                 if (prepare_pipes & (1 << intel_crtc->pipe))
7350                         intel_encoder->connectors_active = false;
7351         }
7352
7353         intel_modeset_commit_output_state(dev);
7354
7355         /* Update computed state. */
7356         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7357                             base.head) {
7358                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7359         }
7360
7361         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7362                 if (!connector->encoder || !connector->encoder->crtc)
7363                         continue;
7364
7365                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7366
7367                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
7368                         struct drm_property *dpms_property =
7369                                 dev->mode_config.dpms_property;
7370
7371                         connector->dpms = DRM_MODE_DPMS_ON;
7372                         drm_connector_property_set_value(connector,
7373                                                          dpms_property,
7374                                                          DRM_MODE_DPMS_ON);
7375
7376                         intel_encoder = to_intel_encoder(connector->encoder);
7377                         intel_encoder->connectors_active = true;
7378                 }
7379         }
7380
7381 }
7382
7383 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7384         list_for_each_entry((intel_crtc), \
7385                             &(dev)->mode_config.crtc_list, \
7386                             base.head) \
7387                 if (mask & (1 <<(intel_crtc)->pipe)) \
7388
7389 void
7390 intel_modeset_check_state(struct drm_device *dev)
7391 {
7392         struct intel_crtc *crtc;
7393         struct intel_encoder *encoder;
7394         struct intel_connector *connector;
7395
7396         list_for_each_entry(connector, &dev->mode_config.connector_list,
7397                             base.head) {
7398                 /* This also checks the encoder/connector hw state with the
7399                  * ->get_hw_state callbacks. */
7400                 intel_connector_check_state(connector);
7401
7402                 WARN(&connector->new_encoder->base != connector->base.encoder,
7403                      "connector's staged encoder doesn't match current encoder\n");
7404         }
7405
7406         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7407                             base.head) {
7408                 bool enabled = false;
7409                 bool active = false;
7410                 enum pipe pipe, tracked_pipe;
7411
7412                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7413                               encoder->base.base.id,
7414                               drm_get_encoder_name(&encoder->base));
7415
7416                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7417                      "encoder's stage crtc doesn't match current crtc\n");
7418                 WARN(encoder->connectors_active && !encoder->base.crtc,
7419                      "encoder's active_connectors set, but no crtc\n");
7420
7421                 list_for_each_entry(connector, &dev->mode_config.connector_list,
7422                                     base.head) {
7423                         if (connector->base.encoder != &encoder->base)
7424                                 continue;
7425                         enabled = true;
7426                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7427                                 active = true;
7428                 }
7429                 WARN(!!encoder->base.crtc != enabled,
7430                      "encoder's enabled state mismatch "
7431                      "(expected %i, found %i)\n",
7432                      !!encoder->base.crtc, enabled);
7433                 WARN(active && !encoder->base.crtc,
7434                      "active encoder with no crtc\n");
7435
7436                 WARN(encoder->connectors_active != active,
7437                      "encoder's computed active state doesn't match tracked active state "
7438                      "(expected %i, found %i)\n", active, encoder->connectors_active);
7439
7440                 active = encoder->get_hw_state(encoder, &pipe);
7441                 WARN(active != encoder->connectors_active,
7442                      "encoder's hw state doesn't match sw tracking "
7443                      "(expected %i, found %i)\n",
7444                      encoder->connectors_active, active);
7445
7446                 if (!encoder->base.crtc)
7447                         continue;
7448
7449                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7450                 WARN(active && pipe != tracked_pipe,
7451                      "active encoder's pipe doesn't match"
7452                      "(expected %i, found %i)\n",
7453                      tracked_pipe, pipe);
7454
7455         }
7456
7457         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7458                             base.head) {
7459                 bool enabled = false;
7460                 bool active = false;
7461
7462                 DRM_DEBUG_KMS("[CRTC:%d]\n",
7463                               crtc->base.base.id);
7464
7465                 WARN(crtc->active && !crtc->base.enabled,
7466                      "active crtc, but not enabled in sw tracking\n");
7467
7468                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7469                                     base.head) {
7470                         if (encoder->base.crtc != &crtc->base)
7471                                 continue;
7472                         enabled = true;
7473                         if (encoder->connectors_active)
7474                                 active = true;
7475                 }
7476                 WARN(active != crtc->active,
7477                      "crtc's computed active state doesn't match tracked active state "
7478                      "(expected %i, found %i)\n", active, crtc->active);
7479                 WARN(enabled != crtc->base.enabled,
7480                      "crtc's computed enabled state doesn't match tracked enabled state "
7481                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7482
7483                 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7484         }
7485 }
7486
7487 bool intel_set_mode(struct drm_crtc *crtc,
7488                     struct drm_display_mode *mode,
7489                     int x, int y, struct drm_framebuffer *fb)
7490 {
7491         struct drm_device *dev = crtc->dev;
7492         drm_i915_private_t *dev_priv = dev->dev_private;
7493         struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
7494         struct drm_encoder_helper_funcs *encoder_funcs;
7495         struct drm_encoder *encoder;
7496         struct intel_crtc *intel_crtc;
7497         unsigned disable_pipes, prepare_pipes, modeset_pipes;
7498         bool ret = true;
7499
7500         intel_modeset_affected_pipes(crtc, &modeset_pipes,
7501                                      &prepare_pipes, &disable_pipes);
7502
7503         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7504                       modeset_pipes, prepare_pipes, disable_pipes);
7505
7506         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7507                 intel_crtc_disable(&intel_crtc->base);
7508
7509         saved_hwmode = crtc->hwmode;
7510         saved_mode = crtc->mode;
7511
7512         /* Hack: Because we don't (yet) support global modeset on multiple
7513          * crtcs, we don't keep track of the new mode for more than one crtc.
7514          * Hence simply check whether any bit is set in modeset_pipes in all the
7515          * pieces of code that are not yet converted to deal with mutliple crtcs
7516          * changing their mode at the same time. */
7517         adjusted_mode = NULL;
7518         if (modeset_pipes) {
7519                 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7520                 if (IS_ERR(adjusted_mode)) {
7521                         return false;
7522                 }
7523         }
7524
7525         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7526                 if (intel_crtc->base.enabled)
7527                         dev_priv->display.crtc_disable(&intel_crtc->base);
7528         }
7529
7530         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7531          * to set it here already despite that we pass it down the callchain.
7532          */
7533         if (modeset_pipes)
7534                 crtc->mode = *mode;
7535
7536         /* Only after disabling all output pipelines that will be changed can we
7537          * update the the output configuration. */
7538         intel_modeset_update_state(dev, prepare_pipes);
7539
7540         /* Set up the DPLL and any encoders state that needs to adjust or depend
7541          * on the DPLL.
7542          */
7543         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7544                 ret = !intel_crtc_mode_set(&intel_crtc->base,
7545                                            mode, adjusted_mode,
7546                                            x, y, fb);
7547                 if (!ret)
7548                     goto done;
7549
7550                 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
7551
7552                         if (encoder->crtc != &intel_crtc->base)
7553                                 continue;
7554
7555                         DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
7556                                 encoder->base.id, drm_get_encoder_name(encoder),
7557                                 mode->base.id, mode->name);
7558                         encoder_funcs = encoder->helper_private;
7559                         encoder_funcs->mode_set(encoder, mode, adjusted_mode);
7560                 }
7561         }
7562
7563         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7564         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7565                 dev_priv->display.crtc_enable(&intel_crtc->base);
7566
7567         if (modeset_pipes) {
7568                 /* Store real post-adjustment hardware mode. */
7569                 crtc->hwmode = *adjusted_mode;
7570
7571                 /* Calculate and store various constants which
7572                  * are later needed by vblank and swap-completion
7573                  * timestamping. They are derived from true hwmode.
7574                  */
7575                 drm_calc_timestamping_constants(crtc);
7576         }
7577
7578         /* FIXME: add subpixel order */
7579 done:
7580         drm_mode_destroy(dev, adjusted_mode);
7581         if (!ret && crtc->enabled) {
7582                 crtc->hwmode = saved_hwmode;
7583                 crtc->mode = saved_mode;
7584         } else {
7585                 intel_modeset_check_state(dev);
7586         }
7587
7588         return ret;
7589 }
7590
7591 #undef for_each_intel_crtc_masked
7592
7593 static void intel_set_config_free(struct intel_set_config *config)
7594 {
7595         if (!config)
7596                 return;
7597
7598         kfree(config->save_connector_encoders);
7599         kfree(config->save_encoder_crtcs);
7600         kfree(config);
7601 }
7602
7603 static int intel_set_config_save_state(struct drm_device *dev,
7604                                        struct intel_set_config *config)
7605 {
7606         struct drm_encoder *encoder;
7607         struct drm_connector *connector;
7608         int count;
7609
7610         config->save_encoder_crtcs =
7611                 kcalloc(dev->mode_config.num_encoder,
7612                         sizeof(struct drm_crtc *), GFP_KERNEL);
7613         if (!config->save_encoder_crtcs)
7614                 return -ENOMEM;
7615
7616         config->save_connector_encoders =
7617                 kcalloc(dev->mode_config.num_connector,
7618                         sizeof(struct drm_encoder *), GFP_KERNEL);
7619         if (!config->save_connector_encoders)
7620                 return -ENOMEM;
7621
7622         /* Copy data. Note that driver private data is not affected.
7623          * Should anything bad happen only the expected state is
7624          * restored, not the drivers personal bookkeeping.
7625          */
7626         count = 0;
7627         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
7628                 config->save_encoder_crtcs[count++] = encoder->crtc;
7629         }
7630
7631         count = 0;
7632         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7633                 config->save_connector_encoders[count++] = connector->encoder;
7634         }
7635
7636         return 0;
7637 }
7638
7639 static void intel_set_config_restore_state(struct drm_device *dev,
7640                                            struct intel_set_config *config)
7641 {
7642         struct intel_encoder *encoder;
7643         struct intel_connector *connector;
7644         int count;
7645
7646         count = 0;
7647         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7648                 encoder->new_crtc =
7649                         to_intel_crtc(config->save_encoder_crtcs[count++]);
7650         }
7651
7652         count = 0;
7653         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7654                 connector->new_encoder =
7655                         to_intel_encoder(config->save_connector_encoders[count++]);
7656         }
7657 }
7658
7659 static void
7660 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7661                                       struct intel_set_config *config)
7662 {
7663
7664         /* We should be able to check here if the fb has the same properties
7665          * and then just flip_or_move it */
7666         if (set->crtc->fb != set->fb) {
7667                 /* If we have no fb then treat it as a full mode set */
7668                 if (set->crtc->fb == NULL) {
7669                         DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7670                         config->mode_changed = true;
7671                 } else if (set->fb == NULL) {
7672                         config->mode_changed = true;
7673                 } else if (set->fb->depth != set->crtc->fb->depth) {
7674                         config->mode_changed = true;
7675                 } else if (set->fb->bits_per_pixel !=
7676                            set->crtc->fb->bits_per_pixel) {
7677                         config->mode_changed = true;
7678                 } else
7679                         config->fb_changed = true;
7680         }
7681
7682         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
7683                 config->fb_changed = true;
7684
7685         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7686                 DRM_DEBUG_KMS("modes are different, full mode set\n");
7687                 drm_mode_debug_printmodeline(&set->crtc->mode);
7688                 drm_mode_debug_printmodeline(set->mode);
7689                 config->mode_changed = true;
7690         }
7691 }
7692
7693 static int
7694 intel_modeset_stage_output_state(struct drm_device *dev,
7695                                  struct drm_mode_set *set,
7696                                  struct intel_set_config *config)
7697 {
7698         struct drm_crtc *new_crtc;
7699         struct intel_connector *connector;
7700         struct intel_encoder *encoder;
7701         int count, ro;
7702
7703         /* The upper layers ensure that we either disabl a crtc or have a list
7704          * of connectors. For paranoia, double-check this. */
7705         WARN_ON(!set->fb && (set->num_connectors != 0));
7706         WARN_ON(set->fb && (set->num_connectors == 0));
7707
7708         count = 0;
7709         list_for_each_entry(connector, &dev->mode_config.connector_list,
7710                             base.head) {
7711                 /* Otherwise traverse passed in connector list and get encoders
7712                  * for them. */
7713                 for (ro = 0; ro < set->num_connectors; ro++) {
7714                         if (set->connectors[ro] == &connector->base) {
7715                                 connector->new_encoder = connector->encoder;
7716                                 break;
7717                         }
7718                 }
7719
7720                 /* If we disable the crtc, disable all its connectors. Also, if
7721                  * the connector is on the changing crtc but not on the new
7722                  * connector list, disable it. */
7723                 if ((!set->fb || ro == set->num_connectors) &&
7724                     connector->base.encoder &&
7725                     connector->base.encoder->crtc == set->crtc) {
7726                         connector->new_encoder = NULL;
7727
7728                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7729                                 connector->base.base.id,
7730                                 drm_get_connector_name(&connector->base));
7731                 }
7732
7733
7734                 if (&connector->new_encoder->base != connector->base.encoder) {
7735                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
7736                         config->mode_changed = true;
7737                 }
7738
7739                 /* Disable all disconnected encoders. */
7740                 if (connector->base.status == connector_status_disconnected)
7741                         connector->new_encoder = NULL;
7742         }
7743         /* connector->new_encoder is now updated for all connectors. */
7744
7745         /* Update crtc of enabled connectors. */
7746         count = 0;
7747         list_for_each_entry(connector, &dev->mode_config.connector_list,
7748                             base.head) {
7749                 if (!connector->new_encoder)
7750                         continue;
7751
7752                 new_crtc = connector->new_encoder->base.crtc;
7753
7754                 for (ro = 0; ro < set->num_connectors; ro++) {
7755                         if (set->connectors[ro] == &connector->base)
7756                                 new_crtc = set->crtc;
7757                 }
7758
7759                 /* Make sure the new CRTC will work with the encoder */
7760                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
7761                                            new_crtc)) {
7762                         return -EINVAL;
7763                 }
7764                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
7765
7766                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
7767                         connector->base.base.id,
7768                         drm_get_connector_name(&connector->base),
7769                         new_crtc->base.id);
7770         }
7771
7772         /* Check for any encoders that needs to be disabled. */
7773         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7774                             base.head) {
7775                 list_for_each_entry(connector,
7776                                     &dev->mode_config.connector_list,
7777                                     base.head) {
7778                         if (connector->new_encoder == encoder) {
7779                                 WARN_ON(!connector->new_encoder->new_crtc);
7780
7781                                 goto next_encoder;
7782                         }
7783                 }
7784                 encoder->new_crtc = NULL;
7785 next_encoder:
7786                 /* Only now check for crtc changes so we don't miss encoders
7787                  * that will be disabled. */
7788                 if (&encoder->new_crtc->base != encoder->base.crtc) {
7789                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
7790                         config->mode_changed = true;
7791                 }
7792         }
7793         /* Now we've also updated encoder->new_crtc for all encoders. */
7794
7795         return 0;
7796 }
7797
7798 static int intel_crtc_set_config(struct drm_mode_set *set)
7799 {
7800         struct drm_device *dev;
7801         struct drm_mode_set save_set;
7802         struct intel_set_config *config;
7803         int ret;
7804
7805         BUG_ON(!set);
7806         BUG_ON(!set->crtc);
7807         BUG_ON(!set->crtc->helper_private);
7808
7809         if (!set->mode)
7810                 set->fb = NULL;
7811
7812         /* The fb helper likes to play gross jokes with ->mode_set_config.
7813          * Unfortunately the crtc helper doesn't do much at all for this case,
7814          * so we have to cope with this madness until the fb helper is fixed up. */
7815         if (set->fb && set->num_connectors == 0)
7816                 return 0;
7817
7818         if (set->fb) {
7819                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
7820                                 set->crtc->base.id, set->fb->base.id,
7821                                 (int)set->num_connectors, set->x, set->y);
7822         } else {
7823                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
7824         }
7825
7826         dev = set->crtc->dev;
7827
7828         ret = -ENOMEM;
7829         config = kzalloc(sizeof(*config), GFP_KERNEL);
7830         if (!config)
7831                 goto out_config;
7832
7833         ret = intel_set_config_save_state(dev, config);
7834         if (ret)
7835                 goto out_config;
7836
7837         save_set.crtc = set->crtc;
7838         save_set.mode = &set->crtc->mode;
7839         save_set.x = set->crtc->x;
7840         save_set.y = set->crtc->y;
7841         save_set.fb = set->crtc->fb;
7842
7843         /* Compute whether we need a full modeset, only an fb base update or no
7844          * change at all. In the future we might also check whether only the
7845          * mode changed, e.g. for LVDS where we only change the panel fitter in
7846          * such cases. */
7847         intel_set_config_compute_mode_changes(set, config);
7848
7849         ret = intel_modeset_stage_output_state(dev, set, config);
7850         if (ret)
7851                 goto fail;
7852
7853         if (config->mode_changed) {
7854                 if (set->mode) {
7855                         DRM_DEBUG_KMS("attempting to set mode from"
7856                                         " userspace\n");
7857                         drm_mode_debug_printmodeline(set->mode);
7858                 }
7859
7860                 if (!intel_set_mode(set->crtc, set->mode,
7861                                     set->x, set->y, set->fb)) {
7862                         DRM_ERROR("failed to set mode on [CRTC:%d]\n",
7863                                   set->crtc->base.id);
7864                         ret = -EINVAL;
7865                         goto fail;
7866                 }
7867         } else if (config->fb_changed) {
7868                 ret = intel_pipe_set_base(set->crtc,
7869                                           set->x, set->y, set->fb);
7870         }
7871
7872         intel_set_config_free(config);
7873
7874         return 0;
7875
7876 fail:
7877         intel_set_config_restore_state(dev, config);
7878
7879         /* Try to restore the config */
7880         if (config->mode_changed &&
7881             !intel_set_mode(save_set.crtc, save_set.mode,
7882                             save_set.x, save_set.y, save_set.fb))
7883                 DRM_ERROR("failed to restore config after modeset failure\n");
7884
7885 out_config:
7886         intel_set_config_free(config);
7887         return ret;
7888 }
7889
7890 static const struct drm_crtc_funcs intel_crtc_funcs = {
7891         .cursor_set = intel_crtc_cursor_set,
7892         .cursor_move = intel_crtc_cursor_move,
7893         .gamma_set = intel_crtc_gamma_set,
7894         .set_config = intel_crtc_set_config,
7895         .destroy = intel_crtc_destroy,
7896         .page_flip = intel_crtc_page_flip,
7897 };
7898
7899 static void intel_cpu_pll_init(struct drm_device *dev)
7900 {
7901         if (IS_HASWELL(dev))
7902                 intel_ddi_pll_init(dev);
7903 }
7904
7905 static void intel_pch_pll_init(struct drm_device *dev)
7906 {
7907         drm_i915_private_t *dev_priv = dev->dev_private;
7908         int i;
7909
7910         if (dev_priv->num_pch_pll == 0) {
7911                 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
7912                 return;
7913         }
7914
7915         for (i = 0; i < dev_priv->num_pch_pll; i++) {
7916                 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
7917                 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
7918                 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
7919         }
7920 }
7921
7922 static void intel_crtc_init(struct drm_device *dev, int pipe)
7923 {
7924         drm_i915_private_t *dev_priv = dev->dev_private;
7925         struct intel_crtc *intel_crtc;
7926         int i;
7927
7928         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7929         if (intel_crtc == NULL)
7930                 return;
7931
7932         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7933
7934         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
7935         for (i = 0; i < 256; i++) {
7936                 intel_crtc->lut_r[i] = i;
7937                 intel_crtc->lut_g[i] = i;
7938                 intel_crtc->lut_b[i] = i;
7939         }
7940
7941         /* Swap pipes & planes for FBC on pre-965 */
7942         intel_crtc->pipe = pipe;
7943         intel_crtc->plane = pipe;
7944         intel_crtc->cpu_transcoder = pipe;
7945         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
7946                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
7947                 intel_crtc->plane = !pipe;
7948         }
7949
7950         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7951                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7952         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7953         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7954
7955         intel_crtc->bpp = 24; /* default for pre-Ironlake */
7956
7957         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
7958 }
7959
7960 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
7961                                 struct drm_file *file)
7962 {
7963         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7964         struct drm_mode_object *drmmode_obj;
7965         struct intel_crtc *crtc;
7966
7967         if (!drm_core_check_feature(dev, DRIVER_MODESET))
7968                 return -ENODEV;
7969
7970         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7971                         DRM_MODE_OBJECT_CRTC);
7972
7973         if (!drmmode_obj) {
7974                 DRM_ERROR("no such CRTC id\n");
7975                 return -EINVAL;
7976         }
7977
7978         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7979         pipe_from_crtc_id->pipe = crtc->pipe;
7980
7981         return 0;
7982 }
7983
7984 static int intel_encoder_clones(struct intel_encoder *encoder)
7985 {
7986         struct drm_device *dev = encoder->base.dev;
7987         struct intel_encoder *source_encoder;
7988         int index_mask = 0;
7989         int entry = 0;
7990
7991         list_for_each_entry(source_encoder,
7992                             &dev->mode_config.encoder_list, base.head) {
7993
7994                 if (encoder == source_encoder)
7995                         index_mask |= (1 << entry);
7996
7997                 /* Intel hw has only one MUX where enocoders could be cloned. */
7998                 if (encoder->cloneable && source_encoder->cloneable)
7999                         index_mask |= (1 << entry);
8000
8001                 entry++;
8002         }
8003
8004         return index_mask;
8005 }
8006
8007 static bool has_edp_a(struct drm_device *dev)
8008 {
8009         struct drm_i915_private *dev_priv = dev->dev_private;
8010
8011         if (!IS_MOBILE(dev))
8012                 return false;
8013
8014         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8015                 return false;
8016
8017         if (IS_GEN5(dev) &&
8018             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8019                 return false;
8020
8021         return true;
8022 }
8023
8024 static void intel_setup_outputs(struct drm_device *dev)
8025 {
8026         struct drm_i915_private *dev_priv = dev->dev_private;
8027         struct intel_encoder *encoder;
8028         bool dpd_is_edp = false;
8029         bool has_lvds;
8030
8031         has_lvds = intel_lvds_init(dev);
8032         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8033                 /* disable the panel fitter on everything but LVDS */
8034                 I915_WRITE(PFIT_CONTROL, 0);
8035         }
8036
8037         if (HAS_PCH_SPLIT(dev)) {
8038                 dpd_is_edp = intel_dpd_is_edp(dev);
8039
8040                 if (has_edp_a(dev))
8041                         intel_dp_init(dev, DP_A, PORT_A);
8042
8043                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
8044                         intel_dp_init(dev, PCH_DP_D, PORT_D);
8045         }
8046
8047         intel_crt_init(dev);
8048
8049         if (IS_HASWELL(dev)) {
8050                 int found;
8051
8052                 /* Haswell uses DDI functions to detect digital outputs */
8053                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8054                 /* DDI A only supports eDP */
8055                 if (found)
8056                         intel_ddi_init(dev, PORT_A);
8057
8058                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8059                  * register */
8060                 found = I915_READ(SFUSE_STRAP);
8061
8062                 if (found & SFUSE_STRAP_DDIB_DETECTED)
8063                         intel_ddi_init(dev, PORT_B);
8064                 if (found & SFUSE_STRAP_DDIC_DETECTED)
8065                         intel_ddi_init(dev, PORT_C);
8066                 if (found & SFUSE_STRAP_DDID_DETECTED)
8067                         intel_ddi_init(dev, PORT_D);
8068         } else if (HAS_PCH_SPLIT(dev)) {
8069                 int found;
8070
8071                 if (I915_READ(HDMIB) & PORT_DETECTED) {
8072                         /* PCH SDVOB multiplex with HDMIB */
8073                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
8074                         if (!found)
8075                                 intel_hdmi_init(dev, HDMIB, PORT_B);
8076                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
8077                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
8078                 }
8079
8080                 if (I915_READ(HDMIC) & PORT_DETECTED)
8081                         intel_hdmi_init(dev, HDMIC, PORT_C);
8082
8083                 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
8084                         intel_hdmi_init(dev, HDMID, PORT_D);
8085
8086                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
8087                         intel_dp_init(dev, PCH_DP_C, PORT_C);
8088
8089                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
8090                         intel_dp_init(dev, PCH_DP_D, PORT_D);
8091         } else if (IS_VALLEYVIEW(dev)) {
8092                 int found;
8093
8094                 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8095                 if (I915_READ(DP_C) & DP_DETECTED)
8096                         intel_dp_init(dev, DP_C, PORT_C);
8097
8098                 if (I915_READ(SDVOB) & PORT_DETECTED) {
8099                         /* SDVOB multiplex with HDMIB */
8100                         found = intel_sdvo_init(dev, SDVOB, true);
8101                         if (!found)
8102                                 intel_hdmi_init(dev, SDVOB, PORT_B);
8103                         if (!found && (I915_READ(DP_B) & DP_DETECTED))
8104                                 intel_dp_init(dev, DP_B, PORT_B);
8105                 }
8106
8107                 if (I915_READ(SDVOC) & PORT_DETECTED)
8108                         intel_hdmi_init(dev, SDVOC, PORT_C);
8109
8110         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
8111                 bool found = false;
8112
8113                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8114                         DRM_DEBUG_KMS("probing SDVOB\n");
8115                         found = intel_sdvo_init(dev, SDVOB, true);
8116                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8117                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8118                                 intel_hdmi_init(dev, SDVOB, PORT_B);
8119                         }
8120
8121                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8122                                 DRM_DEBUG_KMS("probing DP_B\n");
8123                                 intel_dp_init(dev, DP_B, PORT_B);
8124                         }
8125                 }
8126
8127                 /* Before G4X SDVOC doesn't have its own detect register */
8128
8129                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8130                         DRM_DEBUG_KMS("probing SDVOC\n");
8131                         found = intel_sdvo_init(dev, SDVOC, false);
8132                 }
8133
8134                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
8135
8136                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8137                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8138                                 intel_hdmi_init(dev, SDVOC, PORT_C);
8139                         }
8140                         if (SUPPORTS_INTEGRATED_DP(dev)) {
8141                                 DRM_DEBUG_KMS("probing DP_C\n");
8142                                 intel_dp_init(dev, DP_C, PORT_C);
8143                         }
8144                 }
8145
8146                 if (SUPPORTS_INTEGRATED_DP(dev) &&
8147                     (I915_READ(DP_D) & DP_DETECTED)) {
8148                         DRM_DEBUG_KMS("probing DP_D\n");
8149                         intel_dp_init(dev, DP_D, PORT_D);
8150                 }
8151         } else if (IS_GEN2(dev))
8152                 intel_dvo_init(dev);
8153
8154         if (SUPPORTS_TV(dev))
8155                 intel_tv_init(dev);
8156
8157         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8158                 encoder->base.possible_crtcs = encoder->crtc_mask;
8159                 encoder->base.possible_clones =
8160                         intel_encoder_clones(encoder);
8161         }
8162
8163         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8164                 ironlake_init_pch_refclk(dev);
8165 }
8166
8167 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8168 {
8169         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8170
8171         drm_framebuffer_cleanup(fb);
8172         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8173
8174         kfree(intel_fb);
8175 }
8176
8177 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8178                                                 struct drm_file *file,
8179                                                 unsigned int *handle)
8180 {
8181         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8182         struct drm_i915_gem_object *obj = intel_fb->obj;
8183
8184         return drm_gem_handle_create(file, &obj->base, handle);
8185 }
8186
8187 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8188         .destroy = intel_user_framebuffer_destroy,
8189         .create_handle = intel_user_framebuffer_create_handle,
8190 };
8191
8192 int intel_framebuffer_init(struct drm_device *dev,
8193                            struct intel_framebuffer *intel_fb,
8194                            struct drm_mode_fb_cmd2 *mode_cmd,
8195                            struct drm_i915_gem_object *obj)
8196 {
8197         int ret;
8198
8199         if (obj->tiling_mode == I915_TILING_Y)
8200                 return -EINVAL;
8201
8202         if (mode_cmd->pitches[0] & 63)
8203                 return -EINVAL;
8204
8205         switch (mode_cmd->pixel_format) {
8206         case DRM_FORMAT_RGB332:
8207         case DRM_FORMAT_RGB565:
8208         case DRM_FORMAT_XRGB8888:
8209         case DRM_FORMAT_XBGR8888:
8210         case DRM_FORMAT_ARGB8888:
8211         case DRM_FORMAT_XRGB2101010:
8212         case DRM_FORMAT_ARGB2101010:
8213                 /* RGB formats are common across chipsets */
8214                 break;
8215         case DRM_FORMAT_YUYV:
8216         case DRM_FORMAT_UYVY:
8217         case DRM_FORMAT_YVYU:
8218         case DRM_FORMAT_VYUY:
8219                 break;
8220         default:
8221                 DRM_DEBUG_KMS("unsupported pixel format %u\n",
8222                                 mode_cmd->pixel_format);
8223                 return -EINVAL;
8224         }
8225
8226         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8227         if (ret) {
8228                 DRM_ERROR("framebuffer init failed %d\n", ret);
8229                 return ret;
8230         }
8231
8232         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8233         intel_fb->obj = obj;
8234         return 0;
8235 }
8236
8237 static struct drm_framebuffer *
8238 intel_user_framebuffer_create(struct drm_device *dev,
8239                               struct drm_file *filp,
8240                               struct drm_mode_fb_cmd2 *mode_cmd)
8241 {
8242         struct drm_i915_gem_object *obj;
8243
8244         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8245                                                 mode_cmd->handles[0]));
8246         if (&obj->base == NULL)
8247                 return ERR_PTR(-ENOENT);
8248
8249         return intel_framebuffer_create(dev, mode_cmd, obj);
8250 }
8251
8252 static const struct drm_mode_config_funcs intel_mode_funcs = {
8253         .fb_create = intel_user_framebuffer_create,
8254         .output_poll_changed = intel_fb_output_poll_changed,
8255 };
8256
8257 /* Set up chip specific display functions */
8258 static void intel_init_display(struct drm_device *dev)
8259 {
8260         struct drm_i915_private *dev_priv = dev->dev_private;
8261
8262         /* We always want a DPMS function */
8263         if (IS_HASWELL(dev)) {
8264                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
8265                 dev_priv->display.crtc_enable = haswell_crtc_enable;
8266                 dev_priv->display.crtc_disable = haswell_crtc_disable;
8267                 dev_priv->display.off = haswell_crtc_off;
8268                 dev_priv->display.update_plane = ironlake_update_plane;
8269         } else if (HAS_PCH_SPLIT(dev)) {
8270                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8271                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8272                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
8273                 dev_priv->display.off = ironlake_crtc_off;
8274                 dev_priv->display.update_plane = ironlake_update_plane;
8275         } else {
8276                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8277                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8278                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8279                 dev_priv->display.off = i9xx_crtc_off;
8280                 dev_priv->display.update_plane = i9xx_update_plane;
8281         }
8282
8283         /* Returns the core display clock speed */
8284         if (IS_VALLEYVIEW(dev))
8285                 dev_priv->display.get_display_clock_speed =
8286                         valleyview_get_display_clock_speed;
8287         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8288                 dev_priv->display.get_display_clock_speed =
8289                         i945_get_display_clock_speed;
8290         else if (IS_I915G(dev))
8291                 dev_priv->display.get_display_clock_speed =
8292                         i915_get_display_clock_speed;
8293         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8294                 dev_priv->display.get_display_clock_speed =
8295                         i9xx_misc_get_display_clock_speed;
8296         else if (IS_I915GM(dev))
8297                 dev_priv->display.get_display_clock_speed =
8298                         i915gm_get_display_clock_speed;
8299         else if (IS_I865G(dev))
8300                 dev_priv->display.get_display_clock_speed =
8301                         i865_get_display_clock_speed;
8302         else if (IS_I85X(dev))
8303                 dev_priv->display.get_display_clock_speed =
8304                         i855_get_display_clock_speed;
8305         else /* 852, 830 */
8306                 dev_priv->display.get_display_clock_speed =
8307                         i830_get_display_clock_speed;
8308
8309         if (HAS_PCH_SPLIT(dev)) {
8310                 if (IS_GEN5(dev)) {
8311                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8312                         dev_priv->display.write_eld = ironlake_write_eld;
8313                 } else if (IS_GEN6(dev)) {
8314                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8315                         dev_priv->display.write_eld = ironlake_write_eld;
8316                 } else if (IS_IVYBRIDGE(dev)) {
8317                         /* FIXME: detect B0+ stepping and use auto training */
8318                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8319                         dev_priv->display.write_eld = ironlake_write_eld;
8320                 } else if (IS_HASWELL(dev)) {
8321                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
8322                         dev_priv->display.write_eld = haswell_write_eld;
8323                 } else
8324                         dev_priv->display.update_wm = NULL;
8325         } else if (IS_G4X(dev)) {
8326                 dev_priv->display.write_eld = g4x_write_eld;
8327         }
8328
8329         /* Default just returns -ENODEV to indicate unsupported */
8330         dev_priv->display.queue_flip = intel_default_queue_flip;
8331
8332         switch (INTEL_INFO(dev)->gen) {
8333         case 2:
8334                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8335                 break;
8336
8337         case 3:
8338                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8339                 break;
8340
8341         case 4:
8342         case 5:
8343                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8344                 break;
8345
8346         case 6:
8347                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8348                 break;
8349         case 7:
8350                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8351                 break;
8352         }
8353 }
8354
8355 /*
8356  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8357  * resume, or other times.  This quirk makes sure that's the case for
8358  * affected systems.
8359  */
8360 static void quirk_pipea_force(struct drm_device *dev)
8361 {
8362         struct drm_i915_private *dev_priv = dev->dev_private;
8363
8364         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8365         DRM_INFO("applying pipe a force quirk\n");
8366 }
8367
8368 /*
8369  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8370  */
8371 static void quirk_ssc_force_disable(struct drm_device *dev)
8372 {
8373         struct drm_i915_private *dev_priv = dev->dev_private;
8374         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8375         DRM_INFO("applying lvds SSC disable quirk\n");
8376 }
8377
8378 /*
8379  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8380  * brightness value
8381  */
8382 static void quirk_invert_brightness(struct drm_device *dev)
8383 {
8384         struct drm_i915_private *dev_priv = dev->dev_private;
8385         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
8386         DRM_INFO("applying inverted panel brightness quirk\n");
8387 }
8388
8389 struct intel_quirk {
8390         int device;
8391         int subsystem_vendor;
8392         int subsystem_device;
8393         void (*hook)(struct drm_device *dev);
8394 };
8395
8396 static struct intel_quirk intel_quirks[] = {
8397         /* HP Mini needs pipe A force quirk (LP: #322104) */
8398         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
8399
8400         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8401         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8402
8403         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8404         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8405
8406         /* 830/845 need to leave pipe A & dpll A up */
8407         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8408         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8409
8410         /* Lenovo U160 cannot use SSC on LVDS */
8411         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8412
8413         /* Sony Vaio Y cannot use SSC on LVDS */
8414         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
8415
8416         /* Acer Aspire 5734Z must invert backlight brightness */
8417         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
8418 };
8419
8420 static void intel_init_quirks(struct drm_device *dev)
8421 {
8422         struct pci_dev *d = dev->pdev;
8423         int i;
8424
8425         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8426                 struct intel_quirk *q = &intel_quirks[i];
8427
8428                 if (d->device == q->device &&
8429                     (d->subsystem_vendor == q->subsystem_vendor ||
8430                      q->subsystem_vendor == PCI_ANY_ID) &&
8431                     (d->subsystem_device == q->subsystem_device ||
8432                      q->subsystem_device == PCI_ANY_ID))
8433                         q->hook(dev);
8434         }
8435 }
8436
8437 /* Disable the VGA plane that we never use */
8438 static void i915_disable_vga(struct drm_device *dev)
8439 {
8440         struct drm_i915_private *dev_priv = dev->dev_private;
8441         u8 sr1;
8442         u32 vga_reg;
8443
8444         if (HAS_PCH_SPLIT(dev))
8445                 vga_reg = CPU_VGACNTRL;
8446         else
8447                 vga_reg = VGACNTRL;
8448
8449         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8450         outb(SR01, VGA_SR_INDEX);
8451         sr1 = inb(VGA_SR_DATA);
8452         outb(sr1 | 1<<5, VGA_SR_DATA);
8453         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8454         udelay(300);
8455
8456         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8457         POSTING_READ(vga_reg);
8458 }
8459
8460 void intel_modeset_init_hw(struct drm_device *dev)
8461 {
8462         /* We attempt to init the necessary power wells early in the initialization
8463          * time, so the subsystems that expect power to be enabled can work.
8464          */
8465         intel_init_power_wells(dev);
8466
8467         intel_prepare_ddi(dev);
8468
8469         intel_init_clock_gating(dev);
8470
8471         mutex_lock(&dev->struct_mutex);
8472         intel_enable_gt_powersave(dev);
8473         mutex_unlock(&dev->struct_mutex);
8474 }
8475
8476 void intel_modeset_init(struct drm_device *dev)
8477 {
8478         struct drm_i915_private *dev_priv = dev->dev_private;
8479         int i, ret;
8480
8481         drm_mode_config_init(dev);
8482
8483         dev->mode_config.min_width = 0;
8484         dev->mode_config.min_height = 0;
8485
8486         dev->mode_config.preferred_depth = 24;
8487         dev->mode_config.prefer_shadow = 1;
8488
8489         dev->mode_config.funcs = &intel_mode_funcs;
8490
8491         intel_init_quirks(dev);
8492
8493         intel_init_pm(dev);
8494
8495         intel_init_display(dev);
8496
8497         if (IS_GEN2(dev)) {
8498                 dev->mode_config.max_width = 2048;
8499                 dev->mode_config.max_height = 2048;
8500         } else if (IS_GEN3(dev)) {
8501                 dev->mode_config.max_width = 4096;
8502                 dev->mode_config.max_height = 4096;
8503         } else {
8504                 dev->mode_config.max_width = 8192;
8505                 dev->mode_config.max_height = 8192;
8506         }
8507         dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
8508
8509         DRM_DEBUG_KMS("%d display pipe%s available.\n",
8510                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
8511
8512         for (i = 0; i < dev_priv->num_pipe; i++) {
8513                 intel_crtc_init(dev, i);
8514                 ret = intel_plane_init(dev, i);
8515                 if (ret)
8516                         DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
8517         }
8518
8519         intel_cpu_pll_init(dev);
8520         intel_pch_pll_init(dev);
8521
8522         /* Just disable it once at startup */
8523         i915_disable_vga(dev);
8524         intel_setup_outputs(dev);
8525 }
8526
8527 static void
8528 intel_connector_break_all_links(struct intel_connector *connector)
8529 {
8530         connector->base.dpms = DRM_MODE_DPMS_OFF;
8531         connector->base.encoder = NULL;
8532         connector->encoder->connectors_active = false;
8533         connector->encoder->base.crtc = NULL;
8534 }
8535
8536 static void intel_enable_pipe_a(struct drm_device *dev)
8537 {
8538         struct intel_connector *connector;
8539         struct drm_connector *crt = NULL;
8540         struct intel_load_detect_pipe load_detect_temp;
8541
8542         /* We can't just switch on the pipe A, we need to set things up with a
8543          * proper mode and output configuration. As a gross hack, enable pipe A
8544          * by enabling the load detect pipe once. */
8545         list_for_each_entry(connector,
8546                             &dev->mode_config.connector_list,
8547                             base.head) {
8548                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8549                         crt = &connector->base;
8550                         break;
8551                 }
8552         }
8553
8554         if (!crt)
8555                 return;
8556
8557         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8558                 intel_release_load_detect_pipe(crt, &load_detect_temp);
8559
8560
8561 }
8562
8563 static bool
8564 intel_check_plane_mapping(struct intel_crtc *crtc)
8565 {
8566         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8567         u32 reg, val;
8568
8569         if (dev_priv->num_pipe == 1)
8570                 return true;
8571
8572         reg = DSPCNTR(!crtc->plane);
8573         val = I915_READ(reg);
8574
8575         if ((val & DISPLAY_PLANE_ENABLE) &&
8576             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8577                 return false;
8578
8579         return true;
8580 }
8581
8582 static void intel_sanitize_crtc(struct intel_crtc *crtc)
8583 {
8584         struct drm_device *dev = crtc->base.dev;
8585         struct drm_i915_private *dev_priv = dev->dev_private;
8586         u32 reg;
8587
8588         /* Clear any frame start delays used for debugging left by the BIOS */
8589         reg = PIPECONF(crtc->cpu_transcoder);
8590         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8591
8592         /* We need to sanitize the plane -> pipe mapping first because this will
8593          * disable the crtc (and hence change the state) if it is wrong. Note
8594          * that gen4+ has a fixed plane -> pipe mapping.  */
8595         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
8596                 struct intel_connector *connector;
8597                 bool plane;
8598
8599                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8600                               crtc->base.base.id);
8601
8602                 /* Pipe has the wrong plane attached and the plane is active.
8603                  * Temporarily change the plane mapping and disable everything
8604                  * ...  */
8605                 plane = crtc->plane;
8606                 crtc->plane = !plane;
8607                 dev_priv->display.crtc_disable(&crtc->base);
8608                 crtc->plane = plane;
8609
8610                 /* ... and break all links. */
8611                 list_for_each_entry(connector, &dev->mode_config.connector_list,
8612                                     base.head) {
8613                         if (connector->encoder->base.crtc != &crtc->base)
8614                                 continue;
8615
8616                         intel_connector_break_all_links(connector);
8617                 }
8618
8619                 WARN_ON(crtc->active);
8620                 crtc->base.enabled = false;
8621         }
8622
8623         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8624             crtc->pipe == PIPE_A && !crtc->active) {
8625                 /* BIOS forgot to enable pipe A, this mostly happens after
8626                  * resume. Force-enable the pipe to fix this, the update_dpms
8627                  * call below we restore the pipe to the right state, but leave
8628                  * the required bits on. */
8629                 intel_enable_pipe_a(dev);
8630         }
8631
8632         /* Adjust the state of the output pipe according to whether we
8633          * have active connectors/encoders. */
8634         intel_crtc_update_dpms(&crtc->base);
8635
8636         if (crtc->active != crtc->base.enabled) {
8637                 struct intel_encoder *encoder;
8638
8639                 /* This can happen either due to bugs in the get_hw_state
8640                  * functions or because the pipe is force-enabled due to the
8641                  * pipe A quirk. */
8642                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8643                               crtc->base.base.id,
8644                               crtc->base.enabled ? "enabled" : "disabled",
8645                               crtc->active ? "enabled" : "disabled");
8646
8647                 crtc->base.enabled = crtc->active;
8648
8649                 /* Because we only establish the connector -> encoder ->
8650                  * crtc links if something is active, this means the
8651                  * crtc is now deactivated. Break the links. connector
8652                  * -> encoder links are only establish when things are
8653                  *  actually up, hence no need to break them. */
8654                 WARN_ON(crtc->active);
8655
8656                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
8657                         WARN_ON(encoder->connectors_active);
8658                         encoder->base.crtc = NULL;
8659                 }
8660         }
8661 }
8662
8663 static void intel_sanitize_encoder(struct intel_encoder *encoder)
8664 {
8665         struct intel_connector *connector;
8666         struct drm_device *dev = encoder->base.dev;
8667
8668         /* We need to check both for a crtc link (meaning that the
8669          * encoder is active and trying to read from a pipe) and the
8670          * pipe itself being active. */
8671         bool has_active_crtc = encoder->base.crtc &&
8672                 to_intel_crtc(encoder->base.crtc)->active;
8673
8674         if (encoder->connectors_active && !has_active_crtc) {
8675                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
8676                               encoder->base.base.id,
8677                               drm_get_encoder_name(&encoder->base));
8678
8679                 /* Connector is active, but has no active pipe. This is
8680                  * fallout from our resume register restoring. Disable
8681                  * the encoder manually again. */
8682                 if (encoder->base.crtc) {
8683                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
8684                                       encoder->base.base.id,
8685                                       drm_get_encoder_name(&encoder->base));
8686                         encoder->disable(encoder);
8687                 }
8688
8689                 /* Inconsistent output/port/pipe state happens presumably due to
8690                  * a bug in one of the get_hw_state functions. Or someplace else
8691                  * in our code, like the register restore mess on resume. Clamp
8692                  * things to off as a safer default. */
8693                 list_for_each_entry(connector,
8694                                     &dev->mode_config.connector_list,
8695                                     base.head) {
8696                         if (connector->encoder != encoder)
8697                                 continue;
8698
8699                         intel_connector_break_all_links(connector);
8700                 }
8701         }
8702         /* Enabled encoders without active connectors will be fixed in
8703          * the crtc fixup. */
8704 }
8705
8706 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
8707  * and i915 state tracking structures. */
8708 void intel_modeset_setup_hw_state(struct drm_device *dev)
8709 {
8710         struct drm_i915_private *dev_priv = dev->dev_private;
8711         enum pipe pipe;
8712         u32 tmp;
8713         struct intel_crtc *crtc;
8714         struct intel_encoder *encoder;
8715         struct intel_connector *connector;
8716
8717         if (IS_HASWELL(dev)) {
8718                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8719
8720                 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8721                         switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8722                         case TRANS_DDI_EDP_INPUT_A_ON:
8723                         case TRANS_DDI_EDP_INPUT_A_ONOFF:
8724                                 pipe = PIPE_A;
8725                                 break;
8726                         case TRANS_DDI_EDP_INPUT_B_ONOFF:
8727                                 pipe = PIPE_B;
8728                                 break;
8729                         case TRANS_DDI_EDP_INPUT_C_ONOFF:
8730                                 pipe = PIPE_C;
8731                                 break;
8732                         }
8733
8734                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8735                         crtc->cpu_transcoder = TRANSCODER_EDP;
8736
8737                         DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
8738                                       pipe_name(pipe));
8739                 }
8740         }
8741
8742         for_each_pipe(pipe) {
8743                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8744
8745                 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
8746                 if (tmp & PIPECONF_ENABLE)
8747                         crtc->active = true;
8748                 else
8749                         crtc->active = false;
8750
8751                 crtc->base.enabled = crtc->active;
8752
8753                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
8754                               crtc->base.base.id,
8755                               crtc->active ? "enabled" : "disabled");
8756         }
8757
8758         if (IS_HASWELL(dev))
8759                 intel_ddi_setup_hw_pll_state(dev);
8760
8761         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8762                             base.head) {
8763                 pipe = 0;
8764
8765                 if (encoder->get_hw_state(encoder, &pipe)) {
8766                         encoder->base.crtc =
8767                                 dev_priv->pipe_to_crtc_mapping[pipe];
8768                 } else {
8769                         encoder->base.crtc = NULL;
8770                 }
8771
8772                 encoder->connectors_active = false;
8773                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
8774                               encoder->base.base.id,
8775                               drm_get_encoder_name(&encoder->base),
8776                               encoder->base.crtc ? "enabled" : "disabled",
8777                               pipe);
8778         }
8779
8780         list_for_each_entry(connector, &dev->mode_config.connector_list,
8781                             base.head) {
8782                 if (connector->get_hw_state(connector)) {
8783                         connector->base.dpms = DRM_MODE_DPMS_ON;
8784                         connector->encoder->connectors_active = true;
8785                         connector->base.encoder = &connector->encoder->base;
8786                 } else {
8787                         connector->base.dpms = DRM_MODE_DPMS_OFF;
8788                         connector->base.encoder = NULL;
8789                 }
8790                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
8791                               connector->base.base.id,
8792                               drm_get_connector_name(&connector->base),
8793                               connector->base.encoder ? "enabled" : "disabled");
8794         }
8795
8796         /* HW state is read out, now we need to sanitize this mess. */
8797         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8798                             base.head) {
8799                 intel_sanitize_encoder(encoder);
8800         }
8801
8802         for_each_pipe(pipe) {
8803                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8804                 intel_sanitize_crtc(crtc);
8805         }
8806
8807         intel_modeset_update_staged_output_state(dev);
8808
8809         intel_modeset_check_state(dev);
8810
8811         drm_mode_config_reset(dev);
8812 }
8813
8814 void intel_modeset_gem_init(struct drm_device *dev)
8815 {
8816         intel_modeset_init_hw(dev);
8817
8818         intel_setup_overlay(dev);
8819
8820         intel_modeset_setup_hw_state(dev);
8821 }
8822
8823 void intel_modeset_cleanup(struct drm_device *dev)
8824 {
8825         struct drm_i915_private *dev_priv = dev->dev_private;
8826         struct drm_crtc *crtc;
8827         struct intel_crtc *intel_crtc;
8828
8829         drm_kms_helper_poll_fini(dev);
8830         mutex_lock(&dev->struct_mutex);
8831
8832         intel_unregister_dsm_handler();
8833
8834
8835         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8836                 /* Skip inactive CRTCs */
8837                 if (!crtc->fb)
8838                         continue;
8839
8840                 intel_crtc = to_intel_crtc(crtc);
8841                 intel_increase_pllclock(crtc);
8842         }
8843
8844         intel_disable_fbc(dev);
8845
8846         intel_disable_gt_powersave(dev);
8847
8848         ironlake_teardown_rc6(dev);
8849
8850         if (IS_VALLEYVIEW(dev))
8851                 vlv_init_dpio(dev);
8852
8853         mutex_unlock(&dev->struct_mutex);
8854
8855         /* Disable the irq before mode object teardown, for the irq might
8856          * enqueue unpin/hotplug work. */
8857         drm_irq_uninstall(dev);
8858         cancel_work_sync(&dev_priv->hotplug_work);
8859         cancel_work_sync(&dev_priv->rps.work);
8860
8861         /* flush any delayed tasks or pending work */
8862         flush_scheduled_work();
8863
8864         drm_mode_config_cleanup(dev);
8865 }
8866
8867 /*
8868  * Return which encoder is currently attached for connector.
8869  */
8870 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
8871 {
8872         return &intel_attached_encoder(connector)->base;
8873 }
8874
8875 void intel_connector_attach_encoder(struct intel_connector *connector,
8876                                     struct intel_encoder *encoder)
8877 {
8878         connector->encoder = encoder;
8879         drm_mode_connector_attach_encoder(&connector->base,
8880                                           &encoder->base);
8881 }
8882
8883 /*
8884  * set vga decode state - true == enable VGA decode
8885  */
8886 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
8887 {
8888         struct drm_i915_private *dev_priv = dev->dev_private;
8889         u16 gmch_ctrl;
8890
8891         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
8892         if (state)
8893                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
8894         else
8895                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
8896         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
8897         return 0;
8898 }
8899
8900 #ifdef CONFIG_DEBUG_FS
8901 #include <linux/seq_file.h>
8902
8903 struct intel_display_error_state {
8904         struct intel_cursor_error_state {
8905                 u32 control;
8906                 u32 position;
8907                 u32 base;
8908                 u32 size;
8909         } cursor[I915_MAX_PIPES];
8910
8911         struct intel_pipe_error_state {
8912                 u32 conf;
8913                 u32 source;
8914
8915                 u32 htotal;
8916                 u32 hblank;
8917                 u32 hsync;
8918                 u32 vtotal;
8919                 u32 vblank;
8920                 u32 vsync;
8921         } pipe[I915_MAX_PIPES];
8922
8923         struct intel_plane_error_state {
8924                 u32 control;
8925                 u32 stride;
8926                 u32 size;
8927                 u32 pos;
8928                 u32 addr;
8929                 u32 surface;
8930                 u32 tile_offset;
8931         } plane[I915_MAX_PIPES];
8932 };
8933
8934 struct intel_display_error_state *
8935 intel_display_capture_error_state(struct drm_device *dev)
8936 {
8937         drm_i915_private_t *dev_priv = dev->dev_private;
8938         struct intel_display_error_state *error;
8939         enum transcoder cpu_transcoder;
8940         int i;
8941
8942         error = kmalloc(sizeof(*error), GFP_ATOMIC);
8943         if (error == NULL)
8944                 return NULL;
8945
8946         for_each_pipe(i) {
8947                 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
8948
8949                 error->cursor[i].control = I915_READ(CURCNTR(i));
8950                 error->cursor[i].position = I915_READ(CURPOS(i));
8951                 error->cursor[i].base = I915_READ(CURBASE(i));
8952
8953                 error->plane[i].control = I915_READ(DSPCNTR(i));
8954                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
8955                 error->plane[i].size = I915_READ(DSPSIZE(i));
8956                 error->plane[i].pos = I915_READ(DSPPOS(i));
8957                 error->plane[i].addr = I915_READ(DSPADDR(i));
8958                 if (INTEL_INFO(dev)->gen >= 4) {
8959                         error->plane[i].surface = I915_READ(DSPSURF(i));
8960                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
8961                 }
8962
8963                 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
8964                 error->pipe[i].source = I915_READ(PIPESRC(i));
8965                 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
8966                 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
8967                 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
8968                 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
8969                 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
8970                 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
8971         }
8972
8973         return error;
8974 }
8975
8976 void
8977 intel_display_print_error_state(struct seq_file *m,
8978                                 struct drm_device *dev,
8979                                 struct intel_display_error_state *error)
8980 {
8981         drm_i915_private_t *dev_priv = dev->dev_private;
8982         int i;
8983
8984         seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
8985         for_each_pipe(i) {
8986                 seq_printf(m, "Pipe [%d]:\n", i);
8987                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
8988                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
8989                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
8990                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
8991                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
8992                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
8993                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
8994                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
8995
8996                 seq_printf(m, "Plane [%d]:\n", i);
8997                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
8998                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
8999                 seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
9000                 seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
9001                 seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
9002                 if (INTEL_INFO(dev)->gen >= 4) {
9003                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
9004                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
9005                 }
9006
9007                 seq_printf(m, "Cursor [%d]:\n", i);
9008                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
9009                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
9010                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
9011         }
9012 }
9013 #endif