2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
47 static void intel_increase_pllclock(struct drm_crtc *crtc);
48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
71 #define INTEL_P2_NUM 2
72 typedef struct intel_limit intel_limit_t;
74 intel_range_t dot, vco, n, m, m1, m2, p, p1;
76 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
77 int, int, intel_clock_t *, intel_clock_t *);
81 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
84 intel_pch_rawclk(struct drm_device *dev)
86 struct drm_i915_private *dev_priv = dev->dev_private;
88 WARN_ON(!HAS_PCH_SPLIT(dev));
90 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
94 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
95 int target, int refclk, intel_clock_t *match_clock,
96 intel_clock_t *best_clock);
98 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
99 int target, int refclk, intel_clock_t *match_clock,
100 intel_clock_t *best_clock);
103 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
104 int target, int refclk, intel_clock_t *match_clock,
105 intel_clock_t *best_clock);
107 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
108 int target, int refclk, intel_clock_t *match_clock,
109 intel_clock_t *best_clock);
112 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
113 int target, int refclk, intel_clock_t *match_clock,
114 intel_clock_t *best_clock);
116 static inline u32 /* units of 100MHz */
117 intel_fdi_link_freq(struct drm_device *dev)
120 struct drm_i915_private *dev_priv = dev->dev_private;
121 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
126 static const intel_limit_t intel_limits_i8xx_dvo = {
127 .dot = { .min = 25000, .max = 350000 },
128 .vco = { .min = 930000, .max = 1400000 },
129 .n = { .min = 3, .max = 16 },
130 .m = { .min = 96, .max = 140 },
131 .m1 = { .min = 18, .max = 26 },
132 .m2 = { .min = 6, .max = 16 },
133 .p = { .min = 4, .max = 128 },
134 .p1 = { .min = 2, .max = 33 },
135 .p2 = { .dot_limit = 165000,
136 .p2_slow = 4, .p2_fast = 2 },
137 .find_pll = intel_find_best_PLL,
140 static const intel_limit_t intel_limits_i8xx_lvds = {
141 .dot = { .min = 25000, .max = 350000 },
142 .vco = { .min = 930000, .max = 1400000 },
143 .n = { .min = 3, .max = 16 },
144 .m = { .min = 96, .max = 140 },
145 .m1 = { .min = 18, .max = 26 },
146 .m2 = { .min = 6, .max = 16 },
147 .p = { .min = 4, .max = 128 },
148 .p1 = { .min = 1, .max = 6 },
149 .p2 = { .dot_limit = 165000,
150 .p2_slow = 14, .p2_fast = 7 },
151 .find_pll = intel_find_best_PLL,
154 static const intel_limit_t intel_limits_i9xx_sdvo = {
155 .dot = { .min = 20000, .max = 400000 },
156 .vco = { .min = 1400000, .max = 2800000 },
157 .n = { .min = 1, .max = 6 },
158 .m = { .min = 70, .max = 120 },
159 .m1 = { .min = 10, .max = 22 },
160 .m2 = { .min = 5, .max = 9 },
161 .p = { .min = 5, .max = 80 },
162 .p1 = { .min = 1, .max = 8 },
163 .p2 = { .dot_limit = 200000,
164 .p2_slow = 10, .p2_fast = 5 },
165 .find_pll = intel_find_best_PLL,
168 static const intel_limit_t intel_limits_i9xx_lvds = {
169 .dot = { .min = 20000, .max = 400000 },
170 .vco = { .min = 1400000, .max = 2800000 },
171 .n = { .min = 1, .max = 6 },
172 .m = { .min = 70, .max = 120 },
173 .m1 = { .min = 10, .max = 22 },
174 .m2 = { .min = 5, .max = 9 },
175 .p = { .min = 7, .max = 98 },
176 .p1 = { .min = 1, .max = 8 },
177 .p2 = { .dot_limit = 112000,
178 .p2_slow = 14, .p2_fast = 7 },
179 .find_pll = intel_find_best_PLL,
183 static const intel_limit_t intel_limits_g4x_sdvo = {
184 .dot = { .min = 25000, .max = 270000 },
185 .vco = { .min = 1750000, .max = 3500000},
186 .n = { .min = 1, .max = 4 },
187 .m = { .min = 104, .max = 138 },
188 .m1 = { .min = 17, .max = 23 },
189 .m2 = { .min = 5, .max = 11 },
190 .p = { .min = 10, .max = 30 },
191 .p1 = { .min = 1, .max = 3},
192 .p2 = { .dot_limit = 270000,
196 .find_pll = intel_g4x_find_best_PLL,
199 static const intel_limit_t intel_limits_g4x_hdmi = {
200 .dot = { .min = 22000, .max = 400000 },
201 .vco = { .min = 1750000, .max = 3500000},
202 .n = { .min = 1, .max = 4 },
203 .m = { .min = 104, .max = 138 },
204 .m1 = { .min = 16, .max = 23 },
205 .m2 = { .min = 5, .max = 11 },
206 .p = { .min = 5, .max = 80 },
207 .p1 = { .min = 1, .max = 8},
208 .p2 = { .dot_limit = 165000,
209 .p2_slow = 10, .p2_fast = 5 },
210 .find_pll = intel_g4x_find_best_PLL,
213 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
214 .dot = { .min = 20000, .max = 115000 },
215 .vco = { .min = 1750000, .max = 3500000 },
216 .n = { .min = 1, .max = 3 },
217 .m = { .min = 104, .max = 138 },
218 .m1 = { .min = 17, .max = 23 },
219 .m2 = { .min = 5, .max = 11 },
220 .p = { .min = 28, .max = 112 },
221 .p1 = { .min = 2, .max = 8 },
222 .p2 = { .dot_limit = 0,
223 .p2_slow = 14, .p2_fast = 14
225 .find_pll = intel_g4x_find_best_PLL,
228 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
229 .dot = { .min = 80000, .max = 224000 },
230 .vco = { .min = 1750000, .max = 3500000 },
231 .n = { .min = 1, .max = 3 },
232 .m = { .min = 104, .max = 138 },
233 .m1 = { .min = 17, .max = 23 },
234 .m2 = { .min = 5, .max = 11 },
235 .p = { .min = 14, .max = 42 },
236 .p1 = { .min = 2, .max = 6 },
237 .p2 = { .dot_limit = 0,
238 .p2_slow = 7, .p2_fast = 7
240 .find_pll = intel_g4x_find_best_PLL,
243 static const intel_limit_t intel_limits_g4x_display_port = {
244 .dot = { .min = 161670, .max = 227000 },
245 .vco = { .min = 1750000, .max = 3500000},
246 .n = { .min = 1, .max = 2 },
247 .m = { .min = 97, .max = 108 },
248 .m1 = { .min = 0x10, .max = 0x12 },
249 .m2 = { .min = 0x05, .max = 0x06 },
250 .p = { .min = 10, .max = 20 },
251 .p1 = { .min = 1, .max = 2},
252 .p2 = { .dot_limit = 0,
253 .p2_slow = 10, .p2_fast = 10 },
254 .find_pll = intel_find_pll_g4x_dp,
257 static const intel_limit_t intel_limits_pineview_sdvo = {
258 .dot = { .min = 20000, .max = 400000},
259 .vco = { .min = 1700000, .max = 3500000 },
260 /* Pineview's Ncounter is a ring counter */
261 .n = { .min = 3, .max = 6 },
262 .m = { .min = 2, .max = 256 },
263 /* Pineview only has one combined m divider, which we treat as m2. */
264 .m1 = { .min = 0, .max = 0 },
265 .m2 = { .min = 0, .max = 254 },
266 .p = { .min = 5, .max = 80 },
267 .p1 = { .min = 1, .max = 8 },
268 .p2 = { .dot_limit = 200000,
269 .p2_slow = 10, .p2_fast = 5 },
270 .find_pll = intel_find_best_PLL,
273 static const intel_limit_t intel_limits_pineview_lvds = {
274 .dot = { .min = 20000, .max = 400000 },
275 .vco = { .min = 1700000, .max = 3500000 },
276 .n = { .min = 3, .max = 6 },
277 .m = { .min = 2, .max = 256 },
278 .m1 = { .min = 0, .max = 0 },
279 .m2 = { .min = 0, .max = 254 },
280 .p = { .min = 7, .max = 112 },
281 .p1 = { .min = 1, .max = 8 },
282 .p2 = { .dot_limit = 112000,
283 .p2_slow = 14, .p2_fast = 14 },
284 .find_pll = intel_find_best_PLL,
287 /* Ironlake / Sandybridge
289 * We calculate clock using (register_value + 2) for N/M1/M2, so here
290 * the range value for them is (actual_value - 2).
292 static const intel_limit_t intel_limits_ironlake_dac = {
293 .dot = { .min = 25000, .max = 350000 },
294 .vco = { .min = 1760000, .max = 3510000 },
295 .n = { .min = 1, .max = 5 },
296 .m = { .min = 79, .max = 127 },
297 .m1 = { .min = 12, .max = 22 },
298 .m2 = { .min = 5, .max = 9 },
299 .p = { .min = 5, .max = 80 },
300 .p1 = { .min = 1, .max = 8 },
301 .p2 = { .dot_limit = 225000,
302 .p2_slow = 10, .p2_fast = 5 },
303 .find_pll = intel_g4x_find_best_PLL,
306 static const intel_limit_t intel_limits_ironlake_single_lvds = {
307 .dot = { .min = 25000, .max = 350000 },
308 .vco = { .min = 1760000, .max = 3510000 },
309 .n = { .min = 1, .max = 3 },
310 .m = { .min = 79, .max = 118 },
311 .m1 = { .min = 12, .max = 22 },
312 .m2 = { .min = 5, .max = 9 },
313 .p = { .min = 28, .max = 112 },
314 .p1 = { .min = 2, .max = 8 },
315 .p2 = { .dot_limit = 225000,
316 .p2_slow = 14, .p2_fast = 14 },
317 .find_pll = intel_g4x_find_best_PLL,
320 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
321 .dot = { .min = 25000, .max = 350000 },
322 .vco = { .min = 1760000, .max = 3510000 },
323 .n = { .min = 1, .max = 3 },
324 .m = { .min = 79, .max = 127 },
325 .m1 = { .min = 12, .max = 22 },
326 .m2 = { .min = 5, .max = 9 },
327 .p = { .min = 14, .max = 56 },
328 .p1 = { .min = 2, .max = 8 },
329 .p2 = { .dot_limit = 225000,
330 .p2_slow = 7, .p2_fast = 7 },
331 .find_pll = intel_g4x_find_best_PLL,
334 /* LVDS 100mhz refclk limits. */
335 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
336 .dot = { .min = 25000, .max = 350000 },
337 .vco = { .min = 1760000, .max = 3510000 },
338 .n = { .min = 1, .max = 2 },
339 .m = { .min = 79, .max = 126 },
340 .m1 = { .min = 12, .max = 22 },
341 .m2 = { .min = 5, .max = 9 },
342 .p = { .min = 28, .max = 112 },
343 .p1 = { .min = 2, .max = 8 },
344 .p2 = { .dot_limit = 225000,
345 .p2_slow = 14, .p2_fast = 14 },
346 .find_pll = intel_g4x_find_best_PLL,
349 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
350 .dot = { .min = 25000, .max = 350000 },
351 .vco = { .min = 1760000, .max = 3510000 },
352 .n = { .min = 1, .max = 3 },
353 .m = { .min = 79, .max = 126 },
354 .m1 = { .min = 12, .max = 22 },
355 .m2 = { .min = 5, .max = 9 },
356 .p = { .min = 14, .max = 42 },
357 .p1 = { .min = 2, .max = 6 },
358 .p2 = { .dot_limit = 225000,
359 .p2_slow = 7, .p2_fast = 7 },
360 .find_pll = intel_g4x_find_best_PLL,
363 static const intel_limit_t intel_limits_ironlake_display_port = {
364 .dot = { .min = 25000, .max = 350000 },
365 .vco = { .min = 1760000, .max = 3510000},
366 .n = { .min = 1, .max = 2 },
367 .m = { .min = 81, .max = 90 },
368 .m1 = { .min = 12, .max = 22 },
369 .m2 = { .min = 5, .max = 9 },
370 .p = { .min = 10, .max = 20 },
371 .p1 = { .min = 1, .max = 2},
372 .p2 = { .dot_limit = 0,
373 .p2_slow = 10, .p2_fast = 10 },
374 .find_pll = intel_find_pll_ironlake_dp,
377 static const intel_limit_t intel_limits_vlv_dac = {
378 .dot = { .min = 25000, .max = 270000 },
379 .vco = { .min = 4000000, .max = 6000000 },
380 .n = { .min = 1, .max = 7 },
381 .m = { .min = 22, .max = 450 }, /* guess */
382 .m1 = { .min = 2, .max = 3 },
383 .m2 = { .min = 11, .max = 156 },
384 .p = { .min = 10, .max = 30 },
385 .p1 = { .min = 2, .max = 3 },
386 .p2 = { .dot_limit = 270000,
387 .p2_slow = 2, .p2_fast = 20 },
388 .find_pll = intel_vlv_find_best_pll,
391 static const intel_limit_t intel_limits_vlv_hdmi = {
392 .dot = { .min = 20000, .max = 165000 },
393 .vco = { .min = 4000000, .max = 5994000},
394 .n = { .min = 1, .max = 7 },
395 .m = { .min = 60, .max = 300 }, /* guess */
396 .m1 = { .min = 2, .max = 3 },
397 .m2 = { .min = 11, .max = 156 },
398 .p = { .min = 10, .max = 30 },
399 .p1 = { .min = 2, .max = 3 },
400 .p2 = { .dot_limit = 270000,
401 .p2_slow = 2, .p2_fast = 20 },
402 .find_pll = intel_vlv_find_best_pll,
405 static const intel_limit_t intel_limits_vlv_dp = {
406 .dot = { .min = 25000, .max = 270000 },
407 .vco = { .min = 4000000, .max = 6000000 },
408 .n = { .min = 1, .max = 7 },
409 .m = { .min = 22, .max = 450 },
410 .m1 = { .min = 2, .max = 3 },
411 .m2 = { .min = 11, .max = 156 },
412 .p = { .min = 10, .max = 30 },
413 .p1 = { .min = 2, .max = 3 },
414 .p2 = { .dot_limit = 270000,
415 .p2_slow = 2, .p2_fast = 20 },
416 .find_pll = intel_vlv_find_best_pll,
419 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
424 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
425 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
426 DRM_ERROR("DPIO idle wait timed out\n");
430 I915_WRITE(DPIO_REG, reg);
431 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
433 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
434 DRM_ERROR("DPIO read wait timed out\n");
437 val = I915_READ(DPIO_DATA);
440 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
444 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
449 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
450 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
451 DRM_ERROR("DPIO idle wait timed out\n");
455 I915_WRITE(DPIO_DATA, val);
456 I915_WRITE(DPIO_REG, reg);
457 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
459 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
460 DRM_ERROR("DPIO write wait timed out\n");
463 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
466 static void vlv_init_dpio(struct drm_device *dev)
468 struct drm_i915_private *dev_priv = dev->dev_private;
470 /* Reset the DPIO config */
471 I915_WRITE(DPIO_CTL, 0);
472 POSTING_READ(DPIO_CTL);
473 I915_WRITE(DPIO_CTL, 1);
474 POSTING_READ(DPIO_CTL);
477 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
479 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
483 static const struct dmi_system_id intel_dual_link_lvds[] = {
485 .callback = intel_dual_link_lvds_callback,
486 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
488 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
489 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
492 { } /* terminating entry */
495 static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
500 /* use the module option value if specified */
501 if (i915_lvds_channel_mode > 0)
502 return i915_lvds_channel_mode == 2;
504 if (dmi_check_system(intel_dual_link_lvds))
507 if (dev_priv->lvds_val)
508 val = dev_priv->lvds_val;
510 /* BIOS should set the proper LVDS register value at boot, but
511 * in reality, it doesn't set the value when the lid is closed;
512 * we need to check "the value to be set" in VBT when LVDS
513 * register is uninitialized.
515 val = I915_READ(reg);
516 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
517 val = dev_priv->bios_lvds_val;
518 dev_priv->lvds_val = val;
520 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
523 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
526 struct drm_device *dev = crtc->dev;
527 struct drm_i915_private *dev_priv = dev->dev_private;
528 const intel_limit_t *limit;
530 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
531 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
532 /* LVDS dual channel */
533 if (refclk == 100000)
534 limit = &intel_limits_ironlake_dual_lvds_100m;
536 limit = &intel_limits_ironlake_dual_lvds;
538 if (refclk == 100000)
539 limit = &intel_limits_ironlake_single_lvds_100m;
541 limit = &intel_limits_ironlake_single_lvds;
543 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
545 limit = &intel_limits_ironlake_display_port;
547 limit = &intel_limits_ironlake_dac;
552 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
554 struct drm_device *dev = crtc->dev;
555 struct drm_i915_private *dev_priv = dev->dev_private;
556 const intel_limit_t *limit;
558 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
559 if (is_dual_link_lvds(dev_priv, LVDS))
560 /* LVDS with dual channel */
561 limit = &intel_limits_g4x_dual_channel_lvds;
563 /* LVDS with dual channel */
564 limit = &intel_limits_g4x_single_channel_lvds;
565 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
566 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
567 limit = &intel_limits_g4x_hdmi;
568 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
569 limit = &intel_limits_g4x_sdvo;
570 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
571 limit = &intel_limits_g4x_display_port;
572 } else /* The option is for other outputs */
573 limit = &intel_limits_i9xx_sdvo;
578 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
580 struct drm_device *dev = crtc->dev;
581 const intel_limit_t *limit;
583 if (HAS_PCH_SPLIT(dev))
584 limit = intel_ironlake_limit(crtc, refclk);
585 else if (IS_G4X(dev)) {
586 limit = intel_g4x_limit(crtc);
587 } else if (IS_PINEVIEW(dev)) {
588 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
589 limit = &intel_limits_pineview_lvds;
591 limit = &intel_limits_pineview_sdvo;
592 } else if (IS_VALLEYVIEW(dev)) {
593 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
594 limit = &intel_limits_vlv_dac;
595 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
596 limit = &intel_limits_vlv_hdmi;
598 limit = &intel_limits_vlv_dp;
599 } else if (!IS_GEN2(dev)) {
600 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
601 limit = &intel_limits_i9xx_lvds;
603 limit = &intel_limits_i9xx_sdvo;
605 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
606 limit = &intel_limits_i8xx_lvds;
608 limit = &intel_limits_i8xx_dvo;
613 /* m1 is reserved as 0 in Pineview, n is a ring counter */
614 static void pineview_clock(int refclk, intel_clock_t *clock)
616 clock->m = clock->m2 + 2;
617 clock->p = clock->p1 * clock->p2;
618 clock->vco = refclk * clock->m / clock->n;
619 clock->dot = clock->vco / clock->p;
622 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
624 if (IS_PINEVIEW(dev)) {
625 pineview_clock(refclk, clock);
628 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
629 clock->p = clock->p1 * clock->p2;
630 clock->vco = refclk * clock->m / (clock->n + 2);
631 clock->dot = clock->vco / clock->p;
635 * Returns whether any output on the specified pipe is of the specified type
637 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
639 struct drm_device *dev = crtc->dev;
640 struct intel_encoder *encoder;
642 for_each_encoder_on_crtc(dev, crtc, encoder)
643 if (encoder->type == type)
649 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
651 * Returns whether the given set of divisors are valid for a given refclk with
652 * the given connectors.
655 static bool intel_PLL_is_valid(struct drm_device *dev,
656 const intel_limit_t *limit,
657 const intel_clock_t *clock)
659 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
660 INTELPllInvalid("p1 out of range\n");
661 if (clock->p < limit->p.min || limit->p.max < clock->p)
662 INTELPllInvalid("p out of range\n");
663 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
664 INTELPllInvalid("m2 out of range\n");
665 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
666 INTELPllInvalid("m1 out of range\n");
667 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
668 INTELPllInvalid("m1 <= m2\n");
669 if (clock->m < limit->m.min || limit->m.max < clock->m)
670 INTELPllInvalid("m out of range\n");
671 if (clock->n < limit->n.min || limit->n.max < clock->n)
672 INTELPllInvalid("n out of range\n");
673 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
674 INTELPllInvalid("vco out of range\n");
675 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
676 * connector, etc., rather than just a single range.
678 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
679 INTELPllInvalid("dot out of range\n");
685 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
686 int target, int refclk, intel_clock_t *match_clock,
687 intel_clock_t *best_clock)
690 struct drm_device *dev = crtc->dev;
691 struct drm_i915_private *dev_priv = dev->dev_private;
695 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
696 (I915_READ(LVDS)) != 0) {
698 * For LVDS, if the panel is on, just rely on its current
699 * settings for dual-channel. We haven't figured out how to
700 * reliably set up different single/dual channel state, if we
703 if (is_dual_link_lvds(dev_priv, LVDS))
704 clock.p2 = limit->p2.p2_fast;
706 clock.p2 = limit->p2.p2_slow;
708 if (target < limit->p2.dot_limit)
709 clock.p2 = limit->p2.p2_slow;
711 clock.p2 = limit->p2.p2_fast;
714 memset(best_clock, 0, sizeof(*best_clock));
716 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
718 for (clock.m2 = limit->m2.min;
719 clock.m2 <= limit->m2.max; clock.m2++) {
720 /* m1 is always 0 in Pineview */
721 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
723 for (clock.n = limit->n.min;
724 clock.n <= limit->n.max; clock.n++) {
725 for (clock.p1 = limit->p1.min;
726 clock.p1 <= limit->p1.max; clock.p1++) {
729 intel_clock(dev, refclk, &clock);
730 if (!intel_PLL_is_valid(dev, limit,
734 clock.p != match_clock->p)
737 this_err = abs(clock.dot - target);
738 if (this_err < err) {
747 return (err != target);
751 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
752 int target, int refclk, intel_clock_t *match_clock,
753 intel_clock_t *best_clock)
755 struct drm_device *dev = crtc->dev;
756 struct drm_i915_private *dev_priv = dev->dev_private;
760 /* approximately equals target * 0.00585 */
761 int err_most = (target >> 8) + (target >> 9);
764 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
767 if (HAS_PCH_SPLIT(dev))
771 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
773 clock.p2 = limit->p2.p2_fast;
775 clock.p2 = limit->p2.p2_slow;
777 if (target < limit->p2.dot_limit)
778 clock.p2 = limit->p2.p2_slow;
780 clock.p2 = limit->p2.p2_fast;
783 memset(best_clock, 0, sizeof(*best_clock));
784 max_n = limit->n.max;
785 /* based on hardware requirement, prefer smaller n to precision */
786 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
787 /* based on hardware requirement, prefere larger m1,m2 */
788 for (clock.m1 = limit->m1.max;
789 clock.m1 >= limit->m1.min; clock.m1--) {
790 for (clock.m2 = limit->m2.max;
791 clock.m2 >= limit->m2.min; clock.m2--) {
792 for (clock.p1 = limit->p1.max;
793 clock.p1 >= limit->p1.min; clock.p1--) {
796 intel_clock(dev, refclk, &clock);
797 if (!intel_PLL_is_valid(dev, limit,
801 clock.p != match_clock->p)
804 this_err = abs(clock.dot - target);
805 if (this_err < err_most) {
819 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
820 int target, int refclk, intel_clock_t *match_clock,
821 intel_clock_t *best_clock)
823 struct drm_device *dev = crtc->dev;
826 if (target < 200000) {
839 intel_clock(dev, refclk, &clock);
840 memcpy(best_clock, &clock, sizeof(intel_clock_t));
844 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
846 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
847 int target, int refclk, intel_clock_t *match_clock,
848 intel_clock_t *best_clock)
851 if (target < 200000) {
864 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
865 clock.p = (clock.p1 * clock.p2);
866 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
868 memcpy(best_clock, &clock, sizeof(intel_clock_t));
872 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
873 int target, int refclk, intel_clock_t *match_clock,
874 intel_clock_t *best_clock)
876 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
878 u32 updrate, minupdate, fracbits, p;
879 unsigned long bestppm, ppm, absppm;
883 dotclk = target * 1000;
886 fastclk = dotclk / (2*100);
890 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
891 bestm1 = bestm2 = bestp1 = bestp2 = 0;
893 /* based on hardware requirement, prefer smaller n to precision */
894 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
895 updrate = refclk / n;
896 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
897 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
901 /* based on hardware requirement, prefer bigger m1,m2 values */
902 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
903 m2 = (((2*(fastclk * p * n / m1 )) +
904 refclk) / (2*refclk));
907 if (vco >= limit->vco.min && vco < limit->vco.max) {
908 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
909 absppm = (ppm > 0) ? ppm : (-ppm);
910 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
914 if (absppm < bestppm - 10) {
931 best_clock->n = bestn;
932 best_clock->m1 = bestm1;
933 best_clock->m2 = bestm2;
934 best_clock->p1 = bestp1;
935 best_clock->p2 = bestp2;
940 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
943 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
944 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
946 return intel_crtc->cpu_transcoder;
949 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
951 struct drm_i915_private *dev_priv = dev->dev_private;
952 u32 frame, frame_reg = PIPEFRAME(pipe);
954 frame = I915_READ(frame_reg);
956 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
957 DRM_DEBUG_KMS("vblank wait timed out\n");
961 * intel_wait_for_vblank - wait for vblank on a given pipe
963 * @pipe: pipe to wait for
965 * Wait for vblank to occur on a given pipe. Needed for various bits of
968 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
970 struct drm_i915_private *dev_priv = dev->dev_private;
971 int pipestat_reg = PIPESTAT(pipe);
973 if (INTEL_INFO(dev)->gen >= 5) {
974 ironlake_wait_for_vblank(dev, pipe);
978 /* Clear existing vblank status. Note this will clear any other
979 * sticky status fields as well.
981 * This races with i915_driver_irq_handler() with the result
982 * that either function could miss a vblank event. Here it is not
983 * fatal, as we will either wait upon the next vblank interrupt or
984 * timeout. Generally speaking intel_wait_for_vblank() is only
985 * called during modeset at which time the GPU should be idle and
986 * should *not* be performing page flips and thus not waiting on
988 * Currently, the result of us stealing a vblank from the irq
989 * handler is that a single frame will be skipped during swapbuffers.
991 I915_WRITE(pipestat_reg,
992 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
994 /* Wait for vblank interrupt bit to set */
995 if (wait_for(I915_READ(pipestat_reg) &
996 PIPE_VBLANK_INTERRUPT_STATUS,
998 DRM_DEBUG_KMS("vblank wait timed out\n");
1002 * intel_wait_for_pipe_off - wait for pipe to turn off
1004 * @pipe: pipe to wait for
1006 * After disabling a pipe, we can't wait for vblank in the usual way,
1007 * spinning on the vblank interrupt status bit, since we won't actually
1008 * see an interrupt when the pipe is disabled.
1010 * On Gen4 and above:
1011 * wait for the pipe register state bit to turn off
1014 * wait for the display line value to settle (it usually
1015 * ends up stopping at the start of the next frame).
1018 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1020 struct drm_i915_private *dev_priv = dev->dev_private;
1021 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1024 if (INTEL_INFO(dev)->gen >= 4) {
1025 int reg = PIPECONF(cpu_transcoder);
1027 /* Wait for the Pipe State to go off */
1028 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1030 WARN(1, "pipe_off wait timed out\n");
1032 u32 last_line, line_mask;
1033 int reg = PIPEDSL(pipe);
1034 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1037 line_mask = DSL_LINEMASK_GEN2;
1039 line_mask = DSL_LINEMASK_GEN3;
1041 /* Wait for the display line to settle */
1043 last_line = I915_READ(reg) & line_mask;
1045 } while (((I915_READ(reg) & line_mask) != last_line) &&
1046 time_after(timeout, jiffies));
1047 if (time_after(jiffies, timeout))
1048 WARN(1, "pipe_off wait timed out\n");
1052 static const char *state_string(bool enabled)
1054 return enabled ? "on" : "off";
1057 /* Only for pre-ILK configs */
1058 static void assert_pll(struct drm_i915_private *dev_priv,
1059 enum pipe pipe, bool state)
1066 val = I915_READ(reg);
1067 cur_state = !!(val & DPLL_VCO_ENABLE);
1068 WARN(cur_state != state,
1069 "PLL state assertion failure (expected %s, current %s)\n",
1070 state_string(state), state_string(cur_state));
1072 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1073 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1076 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1077 struct intel_pch_pll *pll,
1078 struct intel_crtc *crtc,
1084 if (HAS_PCH_LPT(dev_priv->dev)) {
1085 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1090 "asserting PCH PLL %s with no PLL\n", state_string(state)))
1093 val = I915_READ(pll->pll_reg);
1094 cur_state = !!(val & DPLL_VCO_ENABLE);
1095 WARN(cur_state != state,
1096 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1097 pll->pll_reg, state_string(state), state_string(cur_state), val);
1099 /* Make sure the selected PLL is correctly attached to the transcoder */
1100 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
1103 pch_dpll = I915_READ(PCH_DPLL_SEL);
1104 cur_state = pll->pll_reg == _PCH_DPLL_B;
1105 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1106 "PLL[%d] not attached to this transcoder %d: %08x\n",
1107 cur_state, crtc->pipe, pch_dpll)) {
1108 cur_state = !!(val >> (4*crtc->pipe + 3));
1109 WARN(cur_state != state,
1110 "PLL[%d] not %s on this transcoder %d: %08x\n",
1111 pll->pll_reg == _PCH_DPLL_B,
1112 state_string(state),
1118 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1119 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1121 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1122 enum pipe pipe, bool state)
1127 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1130 if (IS_HASWELL(dev_priv->dev)) {
1131 /* On Haswell, DDI is used instead of FDI_TX_CTL */
1132 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1133 val = I915_READ(reg);
1134 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1136 reg = FDI_TX_CTL(pipe);
1137 val = I915_READ(reg);
1138 cur_state = !!(val & FDI_TX_ENABLE);
1140 WARN(cur_state != state,
1141 "FDI TX state assertion failure (expected %s, current %s)\n",
1142 state_string(state), state_string(cur_state));
1144 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1145 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1147 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1148 enum pipe pipe, bool state)
1154 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1155 DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1158 reg = FDI_RX_CTL(pipe);
1159 val = I915_READ(reg);
1160 cur_state = !!(val & FDI_RX_ENABLE);
1162 WARN(cur_state != state,
1163 "FDI RX state assertion failure (expected %s, current %s)\n",
1164 state_string(state), state_string(cur_state));
1166 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1167 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1169 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1175 /* ILK FDI PLL is always enabled */
1176 if (dev_priv->info->gen == 5)
1179 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1180 if (IS_HASWELL(dev_priv->dev))
1183 reg = FDI_TX_CTL(pipe);
1184 val = I915_READ(reg);
1185 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1188 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1194 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1195 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1198 reg = FDI_RX_CTL(pipe);
1199 val = I915_READ(reg);
1200 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1203 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1206 int pp_reg, lvds_reg;
1208 enum pipe panel_pipe = PIPE_A;
1211 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1212 pp_reg = PCH_PP_CONTROL;
1213 lvds_reg = PCH_LVDS;
1215 pp_reg = PP_CONTROL;
1219 val = I915_READ(pp_reg);
1220 if (!(val & PANEL_POWER_ON) ||
1221 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1224 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1225 panel_pipe = PIPE_B;
1227 WARN(panel_pipe == pipe && locked,
1228 "panel assertion failure, pipe %c regs locked\n",
1232 void assert_pipe(struct drm_i915_private *dev_priv,
1233 enum pipe pipe, bool state)
1238 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1241 /* if we need the pipe A quirk it must be always on */
1242 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1245 reg = PIPECONF(cpu_transcoder);
1246 val = I915_READ(reg);
1247 cur_state = !!(val & PIPECONF_ENABLE);
1248 WARN(cur_state != state,
1249 "pipe %c assertion failure (expected %s, current %s)\n",
1250 pipe_name(pipe), state_string(state), state_string(cur_state));
1253 static void assert_plane(struct drm_i915_private *dev_priv,
1254 enum plane plane, bool state)
1260 reg = DSPCNTR(plane);
1261 val = I915_READ(reg);
1262 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1263 WARN(cur_state != state,
1264 "plane %c assertion failure (expected %s, current %s)\n",
1265 plane_name(plane), state_string(state), state_string(cur_state));
1268 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1269 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1271 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1278 /* Planes are fixed to pipes on ILK+ */
1279 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1280 reg = DSPCNTR(pipe);
1281 val = I915_READ(reg);
1282 WARN((val & DISPLAY_PLANE_ENABLE),
1283 "plane %c assertion failure, should be disabled but not\n",
1288 /* Need to check both planes against the pipe */
1289 for (i = 0; i < 2; i++) {
1291 val = I915_READ(reg);
1292 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1293 DISPPLANE_SEL_PIPE_SHIFT;
1294 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1295 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1296 plane_name(i), pipe_name(pipe));
1300 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1305 if (HAS_PCH_LPT(dev_priv->dev)) {
1306 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1310 val = I915_READ(PCH_DREF_CONTROL);
1311 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1312 DREF_SUPERSPREAD_SOURCE_MASK));
1313 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1316 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1323 reg = TRANSCONF(pipe);
1324 val = I915_READ(reg);
1325 enabled = !!(val & TRANS_ENABLE);
1327 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1331 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1332 enum pipe pipe, u32 port_sel, u32 val)
1334 if ((val & DP_PORT_EN) == 0)
1337 if (HAS_PCH_CPT(dev_priv->dev)) {
1338 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1339 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1340 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1343 if ((val & DP_PIPE_MASK) != (pipe << 30))
1349 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1350 enum pipe pipe, u32 val)
1352 if ((val & PORT_ENABLE) == 0)
1355 if (HAS_PCH_CPT(dev_priv->dev)) {
1356 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1359 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1365 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1366 enum pipe pipe, u32 val)
1368 if ((val & LVDS_PORT_EN) == 0)
1371 if (HAS_PCH_CPT(dev_priv->dev)) {
1372 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1375 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1381 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1382 enum pipe pipe, u32 val)
1384 if ((val & ADPA_DAC_ENABLE) == 0)
1386 if (HAS_PCH_CPT(dev_priv->dev)) {
1387 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1390 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1396 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1397 enum pipe pipe, int reg, u32 port_sel)
1399 u32 val = I915_READ(reg);
1400 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1401 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1402 reg, pipe_name(pipe));
1404 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1405 && (val & DP_PIPEB_SELECT),
1406 "IBX PCH dp port still using transcoder B\n");
1409 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1410 enum pipe pipe, int reg)
1412 u32 val = I915_READ(reg);
1413 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1414 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1415 reg, pipe_name(pipe));
1417 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1418 && (val & SDVO_PIPE_B_SELECT),
1419 "IBX PCH hdmi port still using transcoder B\n");
1422 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1428 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1429 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1430 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1433 val = I915_READ(reg);
1434 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1435 "PCH VGA enabled on transcoder %c, should be disabled\n",
1439 val = I915_READ(reg);
1440 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1441 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1444 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1445 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1446 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1450 * intel_enable_pll - enable a PLL
1451 * @dev_priv: i915 private structure
1452 * @pipe: pipe PLL to enable
1454 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1455 * make sure the PLL reg is writable first though, since the panel write
1456 * protect mechanism may be enabled.
1458 * Note! This is for pre-ILK only.
1460 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1462 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1467 /* No really, not for ILK+ */
1468 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1470 /* PLL is protected by panel, make sure we can write it */
1471 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1472 assert_panel_unlocked(dev_priv, pipe);
1475 val = I915_READ(reg);
1476 val |= DPLL_VCO_ENABLE;
1478 /* We do this three times for luck */
1479 I915_WRITE(reg, val);
1481 udelay(150); /* wait for warmup */
1482 I915_WRITE(reg, val);
1484 udelay(150); /* wait for warmup */
1485 I915_WRITE(reg, val);
1487 udelay(150); /* wait for warmup */
1491 * intel_disable_pll - disable a PLL
1492 * @dev_priv: i915 private structure
1493 * @pipe: pipe PLL to disable
1495 * Disable the PLL for @pipe, making sure the pipe is off first.
1497 * Note! This is for pre-ILK only.
1499 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1504 /* Don't disable pipe A or pipe A PLLs if needed */
1505 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1508 /* Make sure the pipe isn't still relying on us */
1509 assert_pipe_disabled(dev_priv, pipe);
1512 val = I915_READ(reg);
1513 val &= ~DPLL_VCO_ENABLE;
1514 I915_WRITE(reg, val);
1520 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1522 unsigned long flags;
1524 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1525 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1527 DRM_ERROR("timeout waiting for SBI to become ready\n");
1531 I915_WRITE(SBI_ADDR,
1533 I915_WRITE(SBI_DATA,
1535 I915_WRITE(SBI_CTL_STAT,
1539 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1541 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1546 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1550 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1552 unsigned long flags;
1555 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1556 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1558 DRM_ERROR("timeout waiting for SBI to become ready\n");
1562 I915_WRITE(SBI_ADDR,
1564 I915_WRITE(SBI_CTL_STAT,
1568 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1570 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1574 value = I915_READ(SBI_DATA);
1577 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1582 * ironlake_enable_pch_pll - enable PCH PLL
1583 * @dev_priv: i915 private structure
1584 * @pipe: pipe PLL to enable
1586 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1587 * drives the transcoder clock.
1589 static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
1591 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1592 struct intel_pch_pll *pll;
1596 /* PCH PLLs only available on ILK, SNB and IVB */
1597 BUG_ON(dev_priv->info->gen < 5);
1598 pll = intel_crtc->pch_pll;
1602 if (WARN_ON(pll->refcount == 0))
1605 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1606 pll->pll_reg, pll->active, pll->on,
1607 intel_crtc->base.base.id);
1609 /* PCH refclock must be enabled first */
1610 assert_pch_refclk_enabled(dev_priv);
1612 if (pll->active++ && pll->on) {
1613 assert_pch_pll_enabled(dev_priv, pll, NULL);
1617 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1620 val = I915_READ(reg);
1621 val |= DPLL_VCO_ENABLE;
1622 I915_WRITE(reg, val);
1629 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1631 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1632 struct intel_pch_pll *pll = intel_crtc->pch_pll;
1636 /* PCH only available on ILK+ */
1637 BUG_ON(dev_priv->info->gen < 5);
1641 if (WARN_ON(pll->refcount == 0))
1644 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1645 pll->pll_reg, pll->active, pll->on,
1646 intel_crtc->base.base.id);
1648 if (WARN_ON(pll->active == 0)) {
1649 assert_pch_pll_disabled(dev_priv, pll, NULL);
1653 if (--pll->active) {
1654 assert_pch_pll_enabled(dev_priv, pll, NULL);
1658 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1660 /* Make sure transcoder isn't still depending on us */
1661 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1664 val = I915_READ(reg);
1665 val &= ~DPLL_VCO_ENABLE;
1666 I915_WRITE(reg, val);
1673 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1677 u32 val, pipeconf_val;
1678 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1680 /* PCH only available on ILK+ */
1681 BUG_ON(dev_priv->info->gen < 5);
1683 /* Make sure PCH DPLL is enabled */
1684 assert_pch_pll_enabled(dev_priv,
1685 to_intel_crtc(crtc)->pch_pll,
1686 to_intel_crtc(crtc));
1688 /* FDI must be feeding us bits for PCH ports */
1689 assert_fdi_tx_enabled(dev_priv, pipe);
1690 assert_fdi_rx_enabled(dev_priv, pipe);
1692 reg = TRANSCONF(pipe);
1693 val = I915_READ(reg);
1694 pipeconf_val = I915_READ(PIPECONF(pipe));
1696 if (HAS_PCH_IBX(dev_priv->dev)) {
1698 * make the BPC in transcoder be consistent with
1699 * that in pipeconf reg.
1701 val &= ~PIPE_BPC_MASK;
1702 val |= pipeconf_val & PIPE_BPC_MASK;
1705 val &= ~TRANS_INTERLACE_MASK;
1706 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1707 if (HAS_PCH_IBX(dev_priv->dev) &&
1708 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1709 val |= TRANS_LEGACY_INTERLACED_ILK;
1711 val |= TRANS_INTERLACED;
1713 val |= TRANS_PROGRESSIVE;
1715 I915_WRITE(reg, val | TRANS_ENABLE);
1716 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1717 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1720 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1721 enum transcoder cpu_transcoder)
1723 u32 val, pipeconf_val;
1725 /* PCH only available on ILK+ */
1726 BUG_ON(dev_priv->info->gen < 5);
1728 /* FDI must be feeding us bits for PCH ports */
1729 assert_fdi_tx_enabled(dev_priv, cpu_transcoder);
1730 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1732 /* Workaround: set timing override bit. */
1733 val = I915_READ(_TRANSA_CHICKEN2);
1734 val |= TRANS_AUTOTRAIN_GEN_STALL_DIS;
1735 I915_WRITE(_TRANSA_CHICKEN2, val);
1738 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1740 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1741 PIPECONF_INTERLACED_ILK)
1742 val |= TRANS_INTERLACED;
1744 val |= TRANS_PROGRESSIVE;
1746 I915_WRITE(TRANSCONF(TRANSCODER_A), val);
1747 if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1748 DRM_ERROR("Failed to enable PCH transcoder\n");
1751 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1757 /* FDI relies on the transcoder */
1758 assert_fdi_tx_disabled(dev_priv, pipe);
1759 assert_fdi_rx_disabled(dev_priv, pipe);
1761 /* Ports must be off as well */
1762 assert_pch_ports_disabled(dev_priv, pipe);
1764 reg = TRANSCONF(pipe);
1765 val = I915_READ(reg);
1766 val &= ~TRANS_ENABLE;
1767 I915_WRITE(reg, val);
1768 /* wait for PCH transcoder off, transcoder state */
1769 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1770 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1773 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1774 enum transcoder cpu_transcoder)
1778 /* FDI relies on the transcoder */
1779 assert_fdi_tx_disabled(dev_priv, cpu_transcoder);
1780 assert_fdi_rx_disabled(dev_priv, TRANSCODER_A);
1782 val = I915_READ(_TRANSACONF);
1783 val &= ~TRANS_ENABLE;
1784 I915_WRITE(_TRANSACONF, val);
1785 /* wait for PCH transcoder off, transcoder state */
1786 if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1787 DRM_ERROR("Failed to disable PCH transcoder\n");
1789 /* Workaround: clear timing override bit. */
1790 val = I915_READ(_TRANSA_CHICKEN2);
1791 val &= ~TRANS_AUTOTRAIN_GEN_STALL_DIS;
1792 I915_WRITE(_TRANSA_CHICKEN2, val);
1796 * intel_enable_pipe - enable a pipe, asserting requirements
1797 * @dev_priv: i915 private structure
1798 * @pipe: pipe to enable
1799 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1801 * Enable @pipe, making sure that various hardware specific requirements
1802 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1804 * @pipe should be %PIPE_A or %PIPE_B.
1806 * Will wait until the pipe is actually running (i.e. first vblank) before
1809 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1812 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1818 * A pipe without a PLL won't actually be able to drive bits from
1819 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1822 if (!HAS_PCH_SPLIT(dev_priv->dev))
1823 assert_pll_enabled(dev_priv, pipe);
1826 /* if driving the PCH, we need FDI enabled */
1827 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1828 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1830 /* FIXME: assert CPU port conditions for SNB+ */
1833 reg = PIPECONF(cpu_transcoder);
1834 val = I915_READ(reg);
1835 if (val & PIPECONF_ENABLE)
1838 I915_WRITE(reg, val | PIPECONF_ENABLE);
1839 intel_wait_for_vblank(dev_priv->dev, pipe);
1843 * intel_disable_pipe - disable a pipe, asserting requirements
1844 * @dev_priv: i915 private structure
1845 * @pipe: pipe to disable
1847 * Disable @pipe, making sure that various hardware specific requirements
1848 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1850 * @pipe should be %PIPE_A or %PIPE_B.
1852 * Will wait until the pipe has shut down before returning.
1854 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1857 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1863 * Make sure planes won't keep trying to pump pixels to us,
1864 * or we might hang the display.
1866 assert_planes_disabled(dev_priv, pipe);
1868 /* Don't disable pipe A or pipe A PLLs if needed */
1869 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1872 reg = PIPECONF(cpu_transcoder);
1873 val = I915_READ(reg);
1874 if ((val & PIPECONF_ENABLE) == 0)
1877 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1878 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1882 * Plane regs are double buffered, going from enabled->disabled needs a
1883 * trigger in order to latch. The display address reg provides this.
1885 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1888 if (dev_priv->info->gen >= 4)
1889 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1891 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1895 * intel_enable_plane - enable a display plane on a given pipe
1896 * @dev_priv: i915 private structure
1897 * @plane: plane to enable
1898 * @pipe: pipe being fed
1900 * Enable @plane on @pipe, making sure that @pipe is running first.
1902 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1903 enum plane plane, enum pipe pipe)
1908 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1909 assert_pipe_enabled(dev_priv, pipe);
1911 reg = DSPCNTR(plane);
1912 val = I915_READ(reg);
1913 if (val & DISPLAY_PLANE_ENABLE)
1916 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1917 intel_flush_display_plane(dev_priv, plane);
1918 intel_wait_for_vblank(dev_priv->dev, pipe);
1922 * intel_disable_plane - disable a display plane
1923 * @dev_priv: i915 private structure
1924 * @plane: plane to disable
1925 * @pipe: pipe consuming the data
1927 * Disable @plane; should be an independent operation.
1929 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1930 enum plane plane, enum pipe pipe)
1935 reg = DSPCNTR(plane);
1936 val = I915_READ(reg);
1937 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1940 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1941 intel_flush_display_plane(dev_priv, plane);
1942 intel_wait_for_vblank(dev_priv->dev, pipe);
1946 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1947 struct drm_i915_gem_object *obj,
1948 struct intel_ring_buffer *pipelined)
1950 struct drm_i915_private *dev_priv = dev->dev_private;
1954 switch (obj->tiling_mode) {
1955 case I915_TILING_NONE:
1956 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1957 alignment = 128 * 1024;
1958 else if (INTEL_INFO(dev)->gen >= 4)
1959 alignment = 4 * 1024;
1961 alignment = 64 * 1024;
1964 /* pin() will align the object as required by fence */
1968 /* FIXME: Is this true? */
1969 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1975 dev_priv->mm.interruptible = false;
1976 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1978 goto err_interruptible;
1980 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1981 * fence, whereas 965+ only requires a fence if using
1982 * framebuffer compression. For simplicity, we always install
1983 * a fence as the cost is not that onerous.
1985 ret = i915_gem_object_get_fence(obj);
1989 i915_gem_object_pin_fence(obj);
1991 dev_priv->mm.interruptible = true;
1995 i915_gem_object_unpin(obj);
1997 dev_priv->mm.interruptible = true;
2001 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2003 i915_gem_object_unpin_fence(obj);
2004 i915_gem_object_unpin(obj);
2007 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2008 * is assumed to be a power-of-two. */
2009 unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y,
2013 int tile_rows, tiles;
2017 tiles = *x / (512/bpp);
2020 return tile_rows * pitch * 8 + tiles * 4096;
2023 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2026 struct drm_device *dev = crtc->dev;
2027 struct drm_i915_private *dev_priv = dev->dev_private;
2028 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2029 struct intel_framebuffer *intel_fb;
2030 struct drm_i915_gem_object *obj;
2031 int plane = intel_crtc->plane;
2032 unsigned long linear_offset;
2041 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2045 intel_fb = to_intel_framebuffer(fb);
2046 obj = intel_fb->obj;
2048 reg = DSPCNTR(plane);
2049 dspcntr = I915_READ(reg);
2050 /* Mask out pixel format bits in case we change it */
2051 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2052 switch (fb->pixel_format) {
2054 dspcntr |= DISPPLANE_8BPP;
2056 case DRM_FORMAT_XRGB1555:
2057 case DRM_FORMAT_ARGB1555:
2058 dspcntr |= DISPPLANE_BGRX555;
2060 case DRM_FORMAT_RGB565:
2061 dspcntr |= DISPPLANE_BGRX565;
2063 case DRM_FORMAT_XRGB8888:
2064 case DRM_FORMAT_ARGB8888:
2065 dspcntr |= DISPPLANE_BGRX888;
2067 case DRM_FORMAT_XBGR8888:
2068 case DRM_FORMAT_ABGR8888:
2069 dspcntr |= DISPPLANE_RGBX888;
2071 case DRM_FORMAT_XRGB2101010:
2072 case DRM_FORMAT_ARGB2101010:
2073 dspcntr |= DISPPLANE_BGRX101010;
2075 case DRM_FORMAT_XBGR2101010:
2076 case DRM_FORMAT_ABGR2101010:
2077 dspcntr |= DISPPLANE_RGBX101010;
2080 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
2084 if (INTEL_INFO(dev)->gen >= 4) {
2085 if (obj->tiling_mode != I915_TILING_NONE)
2086 dspcntr |= DISPPLANE_TILED;
2088 dspcntr &= ~DISPPLANE_TILED;
2091 I915_WRITE(reg, dspcntr);
2093 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2095 if (INTEL_INFO(dev)->gen >= 4) {
2096 intel_crtc->dspaddr_offset =
2097 intel_gen4_compute_offset_xtiled(&x, &y,
2098 fb->bits_per_pixel / 8,
2100 linear_offset -= intel_crtc->dspaddr_offset;
2102 intel_crtc->dspaddr_offset = linear_offset;
2105 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2106 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2107 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2108 if (INTEL_INFO(dev)->gen >= 4) {
2109 I915_MODIFY_DISPBASE(DSPSURF(plane),
2110 obj->gtt_offset + intel_crtc->dspaddr_offset);
2111 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2112 I915_WRITE(DSPLINOFF(plane), linear_offset);
2114 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2120 static int ironlake_update_plane(struct drm_crtc *crtc,
2121 struct drm_framebuffer *fb, int x, int y)
2123 struct drm_device *dev = crtc->dev;
2124 struct drm_i915_private *dev_priv = dev->dev_private;
2125 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2126 struct intel_framebuffer *intel_fb;
2127 struct drm_i915_gem_object *obj;
2128 int plane = intel_crtc->plane;
2129 unsigned long linear_offset;
2139 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2143 intel_fb = to_intel_framebuffer(fb);
2144 obj = intel_fb->obj;
2146 reg = DSPCNTR(plane);
2147 dspcntr = I915_READ(reg);
2148 /* Mask out pixel format bits in case we change it */
2149 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2150 switch (fb->pixel_format) {
2152 dspcntr |= DISPPLANE_8BPP;
2154 case DRM_FORMAT_RGB565:
2155 dspcntr |= DISPPLANE_BGRX565;
2157 case DRM_FORMAT_XRGB8888:
2158 case DRM_FORMAT_ARGB8888:
2159 dspcntr |= DISPPLANE_BGRX888;
2161 case DRM_FORMAT_XBGR8888:
2162 case DRM_FORMAT_ABGR8888:
2163 dspcntr |= DISPPLANE_RGBX888;
2165 case DRM_FORMAT_XRGB2101010:
2166 case DRM_FORMAT_ARGB2101010:
2167 dspcntr |= DISPPLANE_BGRX101010;
2169 case DRM_FORMAT_XBGR2101010:
2170 case DRM_FORMAT_ABGR2101010:
2171 dspcntr |= DISPPLANE_RGBX101010;
2174 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
2178 if (obj->tiling_mode != I915_TILING_NONE)
2179 dspcntr |= DISPPLANE_TILED;
2181 dspcntr &= ~DISPPLANE_TILED;
2184 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2186 I915_WRITE(reg, dspcntr);
2188 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2189 intel_crtc->dspaddr_offset =
2190 intel_gen4_compute_offset_xtiled(&x, &y,
2191 fb->bits_per_pixel / 8,
2193 linear_offset -= intel_crtc->dspaddr_offset;
2195 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2196 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2197 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2198 I915_MODIFY_DISPBASE(DSPSURF(plane),
2199 obj->gtt_offset + intel_crtc->dspaddr_offset);
2200 if (IS_HASWELL(dev)) {
2201 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2203 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2204 I915_WRITE(DSPLINOFF(plane), linear_offset);
2211 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2213 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2214 int x, int y, enum mode_set_atomic state)
2216 struct drm_device *dev = crtc->dev;
2217 struct drm_i915_private *dev_priv = dev->dev_private;
2219 if (dev_priv->display.disable_fbc)
2220 dev_priv->display.disable_fbc(dev);
2221 intel_increase_pllclock(crtc);
2223 return dev_priv->display.update_plane(crtc, fb, x, y);
2227 intel_finish_fb(struct drm_framebuffer *old_fb)
2229 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2230 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2231 bool was_interruptible = dev_priv->mm.interruptible;
2234 wait_event(dev_priv->pending_flip_queue,
2235 atomic_read(&dev_priv->mm.wedged) ||
2236 atomic_read(&obj->pending_flip) == 0);
2238 /* Big Hammer, we also need to ensure that any pending
2239 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2240 * current scanout is retired before unpinning the old
2243 * This should only fail upon a hung GPU, in which case we
2244 * can safely continue.
2246 dev_priv->mm.interruptible = false;
2247 ret = i915_gem_object_finish_gpu(obj);
2248 dev_priv->mm.interruptible = was_interruptible;
2253 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2255 struct drm_device *dev = crtc->dev;
2256 struct drm_i915_master_private *master_priv;
2257 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2259 if (!dev->primary->master)
2262 master_priv = dev->primary->master->driver_priv;
2263 if (!master_priv->sarea_priv)
2266 switch (intel_crtc->pipe) {
2268 master_priv->sarea_priv->pipeA_x = x;
2269 master_priv->sarea_priv->pipeA_y = y;
2272 master_priv->sarea_priv->pipeB_x = x;
2273 master_priv->sarea_priv->pipeB_y = y;
2281 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2282 struct drm_framebuffer *fb)
2284 struct drm_device *dev = crtc->dev;
2285 struct drm_i915_private *dev_priv = dev->dev_private;
2286 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2287 struct drm_framebuffer *old_fb;
2292 DRM_ERROR("No FB bound\n");
2296 if(intel_crtc->plane > dev_priv->num_pipe) {
2297 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2299 dev_priv->num_pipe);
2303 mutex_lock(&dev->struct_mutex);
2304 ret = intel_pin_and_fence_fb_obj(dev,
2305 to_intel_framebuffer(fb)->obj,
2308 mutex_unlock(&dev->struct_mutex);
2309 DRM_ERROR("pin & fence failed\n");
2314 intel_finish_fb(crtc->fb);
2316 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2318 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2319 mutex_unlock(&dev->struct_mutex);
2320 DRM_ERROR("failed to update base address\n");
2330 intel_wait_for_vblank(dev, intel_crtc->pipe);
2331 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2334 intel_update_fbc(dev);
2335 mutex_unlock(&dev->struct_mutex);
2337 intel_crtc_update_sarea_pos(crtc, x, y);
2342 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2344 struct drm_device *dev = crtc->dev;
2345 struct drm_i915_private *dev_priv = dev->dev_private;
2348 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2349 dpa_ctl = I915_READ(DP_A);
2350 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2352 if (clock < 200000) {
2354 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2355 /* workaround for 160Mhz:
2356 1) program 0x4600c bits 15:0 = 0x8124
2357 2) program 0x46010 bit 0 = 1
2358 3) program 0x46034 bit 24 = 1
2359 4) program 0x64000 bit 14 = 1
2361 temp = I915_READ(0x4600c);
2363 I915_WRITE(0x4600c, temp | 0x8124);
2365 temp = I915_READ(0x46010);
2366 I915_WRITE(0x46010, temp | 1);
2368 temp = I915_READ(0x46034);
2369 I915_WRITE(0x46034, temp | (1 << 24));
2371 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2373 I915_WRITE(DP_A, dpa_ctl);
2379 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2381 struct drm_device *dev = crtc->dev;
2382 struct drm_i915_private *dev_priv = dev->dev_private;
2383 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2384 int pipe = intel_crtc->pipe;
2387 /* enable normal train */
2388 reg = FDI_TX_CTL(pipe);
2389 temp = I915_READ(reg);
2390 if (IS_IVYBRIDGE(dev)) {
2391 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2392 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2394 temp &= ~FDI_LINK_TRAIN_NONE;
2395 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2397 I915_WRITE(reg, temp);
2399 reg = FDI_RX_CTL(pipe);
2400 temp = I915_READ(reg);
2401 if (HAS_PCH_CPT(dev)) {
2402 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2403 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2405 temp &= ~FDI_LINK_TRAIN_NONE;
2406 temp |= FDI_LINK_TRAIN_NONE;
2408 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2410 /* wait one idle pattern time */
2414 /* IVB wants error correction enabled */
2415 if (IS_IVYBRIDGE(dev))
2416 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2417 FDI_FE_ERRC_ENABLE);
2420 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2422 struct drm_i915_private *dev_priv = dev->dev_private;
2423 u32 flags = I915_READ(SOUTH_CHICKEN1);
2425 flags |= FDI_PHASE_SYNC_OVR(pipe);
2426 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2427 flags |= FDI_PHASE_SYNC_EN(pipe);
2428 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2429 POSTING_READ(SOUTH_CHICKEN1);
2432 static void ivb_modeset_global_resources(struct drm_device *dev)
2434 struct drm_i915_private *dev_priv = dev->dev_private;
2435 struct intel_crtc *pipe_B_crtc =
2436 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2437 struct intel_crtc *pipe_C_crtc =
2438 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2441 /* When everything is off disable fdi C so that we could enable fdi B
2442 * with all lanes. XXX: This misses the case where a pipe is not using
2443 * any pch resources and so doesn't need any fdi lanes. */
2444 if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2445 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2446 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2448 temp = I915_READ(SOUTH_CHICKEN1);
2449 temp &= ~FDI_BC_BIFURCATION_SELECT;
2450 DRM_DEBUG_KMS("disabling fdi C rx\n");
2451 I915_WRITE(SOUTH_CHICKEN1, temp);
2455 /* The FDI link training functions for ILK/Ibexpeak. */
2456 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2458 struct drm_device *dev = crtc->dev;
2459 struct drm_i915_private *dev_priv = dev->dev_private;
2460 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2461 int pipe = intel_crtc->pipe;
2462 int plane = intel_crtc->plane;
2463 u32 reg, temp, tries;
2465 /* FDI needs bits from pipe & plane first */
2466 assert_pipe_enabled(dev_priv, pipe);
2467 assert_plane_enabled(dev_priv, plane);
2469 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2471 reg = FDI_RX_IMR(pipe);
2472 temp = I915_READ(reg);
2473 temp &= ~FDI_RX_SYMBOL_LOCK;
2474 temp &= ~FDI_RX_BIT_LOCK;
2475 I915_WRITE(reg, temp);
2479 /* enable CPU FDI TX and PCH FDI RX */
2480 reg = FDI_TX_CTL(pipe);
2481 temp = I915_READ(reg);
2483 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2484 temp &= ~FDI_LINK_TRAIN_NONE;
2485 temp |= FDI_LINK_TRAIN_PATTERN_1;
2486 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2488 reg = FDI_RX_CTL(pipe);
2489 temp = I915_READ(reg);
2490 temp &= ~FDI_LINK_TRAIN_NONE;
2491 temp |= FDI_LINK_TRAIN_PATTERN_1;
2492 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2497 /* Ironlake workaround, enable clock pointer after FDI enable*/
2498 if (HAS_PCH_IBX(dev)) {
2499 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2500 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2501 FDI_RX_PHASE_SYNC_POINTER_EN);
2504 reg = FDI_RX_IIR(pipe);
2505 for (tries = 0; tries < 5; tries++) {
2506 temp = I915_READ(reg);
2507 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2509 if ((temp & FDI_RX_BIT_LOCK)) {
2510 DRM_DEBUG_KMS("FDI train 1 done.\n");
2511 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2516 DRM_ERROR("FDI train 1 fail!\n");
2519 reg = FDI_TX_CTL(pipe);
2520 temp = I915_READ(reg);
2521 temp &= ~FDI_LINK_TRAIN_NONE;
2522 temp |= FDI_LINK_TRAIN_PATTERN_2;
2523 I915_WRITE(reg, temp);
2525 reg = FDI_RX_CTL(pipe);
2526 temp = I915_READ(reg);
2527 temp &= ~FDI_LINK_TRAIN_NONE;
2528 temp |= FDI_LINK_TRAIN_PATTERN_2;
2529 I915_WRITE(reg, temp);
2534 reg = FDI_RX_IIR(pipe);
2535 for (tries = 0; tries < 5; tries++) {
2536 temp = I915_READ(reg);
2537 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2539 if (temp & FDI_RX_SYMBOL_LOCK) {
2540 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2541 DRM_DEBUG_KMS("FDI train 2 done.\n");
2546 DRM_ERROR("FDI train 2 fail!\n");
2548 DRM_DEBUG_KMS("FDI train done\n");
2552 static const int snb_b_fdi_train_param[] = {
2553 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2554 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2555 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2556 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2559 /* The FDI link training functions for SNB/Cougarpoint. */
2560 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2562 struct drm_device *dev = crtc->dev;
2563 struct drm_i915_private *dev_priv = dev->dev_private;
2564 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2565 int pipe = intel_crtc->pipe;
2566 u32 reg, temp, i, retry;
2568 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2570 reg = FDI_RX_IMR(pipe);
2571 temp = I915_READ(reg);
2572 temp &= ~FDI_RX_SYMBOL_LOCK;
2573 temp &= ~FDI_RX_BIT_LOCK;
2574 I915_WRITE(reg, temp);
2579 /* enable CPU FDI TX and PCH FDI RX */
2580 reg = FDI_TX_CTL(pipe);
2581 temp = I915_READ(reg);
2583 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2584 temp &= ~FDI_LINK_TRAIN_NONE;
2585 temp |= FDI_LINK_TRAIN_PATTERN_1;
2586 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2588 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2589 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2591 I915_WRITE(FDI_RX_MISC(pipe),
2592 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2594 reg = FDI_RX_CTL(pipe);
2595 temp = I915_READ(reg);
2596 if (HAS_PCH_CPT(dev)) {
2597 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2598 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2600 temp &= ~FDI_LINK_TRAIN_NONE;
2601 temp |= FDI_LINK_TRAIN_PATTERN_1;
2603 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2608 if (HAS_PCH_CPT(dev))
2609 cpt_phase_pointer_enable(dev, pipe);
2611 for (i = 0; i < 4; i++) {
2612 reg = FDI_TX_CTL(pipe);
2613 temp = I915_READ(reg);
2614 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2615 temp |= snb_b_fdi_train_param[i];
2616 I915_WRITE(reg, temp);
2621 for (retry = 0; retry < 5; retry++) {
2622 reg = FDI_RX_IIR(pipe);
2623 temp = I915_READ(reg);
2624 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2625 if (temp & FDI_RX_BIT_LOCK) {
2626 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2627 DRM_DEBUG_KMS("FDI train 1 done.\n");
2636 DRM_ERROR("FDI train 1 fail!\n");
2639 reg = FDI_TX_CTL(pipe);
2640 temp = I915_READ(reg);
2641 temp &= ~FDI_LINK_TRAIN_NONE;
2642 temp |= FDI_LINK_TRAIN_PATTERN_2;
2644 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2646 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2648 I915_WRITE(reg, temp);
2650 reg = FDI_RX_CTL(pipe);
2651 temp = I915_READ(reg);
2652 if (HAS_PCH_CPT(dev)) {
2653 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2654 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2656 temp &= ~FDI_LINK_TRAIN_NONE;
2657 temp |= FDI_LINK_TRAIN_PATTERN_2;
2659 I915_WRITE(reg, temp);
2664 for (i = 0; i < 4; i++) {
2665 reg = FDI_TX_CTL(pipe);
2666 temp = I915_READ(reg);
2667 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2668 temp |= snb_b_fdi_train_param[i];
2669 I915_WRITE(reg, temp);
2674 for (retry = 0; retry < 5; retry++) {
2675 reg = FDI_RX_IIR(pipe);
2676 temp = I915_READ(reg);
2677 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2678 if (temp & FDI_RX_SYMBOL_LOCK) {
2679 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2680 DRM_DEBUG_KMS("FDI train 2 done.\n");
2689 DRM_ERROR("FDI train 2 fail!\n");
2691 DRM_DEBUG_KMS("FDI train done.\n");
2694 /* Manual link training for Ivy Bridge A0 parts */
2695 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2697 struct drm_device *dev = crtc->dev;
2698 struct drm_i915_private *dev_priv = dev->dev_private;
2699 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2700 int pipe = intel_crtc->pipe;
2703 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2705 reg = FDI_RX_IMR(pipe);
2706 temp = I915_READ(reg);
2707 temp &= ~FDI_RX_SYMBOL_LOCK;
2708 temp &= ~FDI_RX_BIT_LOCK;
2709 I915_WRITE(reg, temp);
2714 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2715 I915_READ(FDI_RX_IIR(pipe)));
2717 /* enable CPU FDI TX and PCH FDI RX */
2718 reg = FDI_TX_CTL(pipe);
2719 temp = I915_READ(reg);
2721 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2722 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2723 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2724 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2725 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2726 temp |= FDI_COMPOSITE_SYNC;
2727 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2729 I915_WRITE(FDI_RX_MISC(pipe),
2730 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2732 reg = FDI_RX_CTL(pipe);
2733 temp = I915_READ(reg);
2734 temp &= ~FDI_LINK_TRAIN_AUTO;
2735 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2736 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2737 temp |= FDI_COMPOSITE_SYNC;
2738 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2743 if (HAS_PCH_CPT(dev))
2744 cpt_phase_pointer_enable(dev, pipe);
2746 for (i = 0; i < 4; i++) {
2747 reg = FDI_TX_CTL(pipe);
2748 temp = I915_READ(reg);
2749 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2750 temp |= snb_b_fdi_train_param[i];
2751 I915_WRITE(reg, temp);
2756 reg = FDI_RX_IIR(pipe);
2757 temp = I915_READ(reg);
2758 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2760 if (temp & FDI_RX_BIT_LOCK ||
2761 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2762 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2763 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2768 DRM_ERROR("FDI train 1 fail!\n");
2771 reg = FDI_TX_CTL(pipe);
2772 temp = I915_READ(reg);
2773 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2774 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2775 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2776 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2777 I915_WRITE(reg, temp);
2779 reg = FDI_RX_CTL(pipe);
2780 temp = I915_READ(reg);
2781 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2782 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2783 I915_WRITE(reg, temp);
2788 for (i = 0; i < 4; i++) {
2789 reg = FDI_TX_CTL(pipe);
2790 temp = I915_READ(reg);
2791 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2792 temp |= snb_b_fdi_train_param[i];
2793 I915_WRITE(reg, temp);
2798 reg = FDI_RX_IIR(pipe);
2799 temp = I915_READ(reg);
2800 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2802 if (temp & FDI_RX_SYMBOL_LOCK) {
2803 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2804 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2809 DRM_ERROR("FDI train 2 fail!\n");
2811 DRM_DEBUG_KMS("FDI train done.\n");
2814 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2816 struct drm_device *dev = intel_crtc->base.dev;
2817 struct drm_i915_private *dev_priv = dev->dev_private;
2818 int pipe = intel_crtc->pipe;
2822 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2823 reg = FDI_RX_CTL(pipe);
2824 temp = I915_READ(reg);
2825 temp &= ~((0x7 << 19) | (0x7 << 16));
2826 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2827 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2828 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2833 /* Switch from Rawclk to PCDclk */
2834 temp = I915_READ(reg);
2835 I915_WRITE(reg, temp | FDI_PCDCLK);
2840 /* On Haswell, the PLL configuration for ports and pipes is handled
2841 * separately, as part of DDI setup */
2842 if (!IS_HASWELL(dev)) {
2843 /* Enable CPU FDI TX PLL, always on for Ironlake */
2844 reg = FDI_TX_CTL(pipe);
2845 temp = I915_READ(reg);
2846 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2847 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2855 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2857 struct drm_device *dev = intel_crtc->base.dev;
2858 struct drm_i915_private *dev_priv = dev->dev_private;
2859 int pipe = intel_crtc->pipe;
2862 /* Switch from PCDclk to Rawclk */
2863 reg = FDI_RX_CTL(pipe);
2864 temp = I915_READ(reg);
2865 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2867 /* Disable CPU FDI TX PLL */
2868 reg = FDI_TX_CTL(pipe);
2869 temp = I915_READ(reg);
2870 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2875 reg = FDI_RX_CTL(pipe);
2876 temp = I915_READ(reg);
2877 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2879 /* Wait for the clocks to turn off. */
2884 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2886 struct drm_i915_private *dev_priv = dev->dev_private;
2887 u32 flags = I915_READ(SOUTH_CHICKEN1);
2889 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2890 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2891 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2892 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2893 POSTING_READ(SOUTH_CHICKEN1);
2895 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2897 struct drm_device *dev = crtc->dev;
2898 struct drm_i915_private *dev_priv = dev->dev_private;
2899 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2900 int pipe = intel_crtc->pipe;
2903 /* disable CPU FDI tx and PCH FDI rx */
2904 reg = FDI_TX_CTL(pipe);
2905 temp = I915_READ(reg);
2906 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2909 reg = FDI_RX_CTL(pipe);
2910 temp = I915_READ(reg);
2911 temp &= ~(0x7 << 16);
2912 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2913 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2918 /* Ironlake workaround, disable clock pointer after downing FDI */
2919 if (HAS_PCH_IBX(dev)) {
2920 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2921 I915_WRITE(FDI_RX_CHICKEN(pipe),
2922 I915_READ(FDI_RX_CHICKEN(pipe) &
2923 ~FDI_RX_PHASE_SYNC_POINTER_EN));
2924 } else if (HAS_PCH_CPT(dev)) {
2925 cpt_phase_pointer_disable(dev, pipe);
2928 /* still set train pattern 1 */
2929 reg = FDI_TX_CTL(pipe);
2930 temp = I915_READ(reg);
2931 temp &= ~FDI_LINK_TRAIN_NONE;
2932 temp |= FDI_LINK_TRAIN_PATTERN_1;
2933 I915_WRITE(reg, temp);
2935 reg = FDI_RX_CTL(pipe);
2936 temp = I915_READ(reg);
2937 if (HAS_PCH_CPT(dev)) {
2938 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2939 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2941 temp &= ~FDI_LINK_TRAIN_NONE;
2942 temp |= FDI_LINK_TRAIN_PATTERN_1;
2944 /* BPC in FDI rx is consistent with that in PIPECONF */
2945 temp &= ~(0x07 << 16);
2946 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2947 I915_WRITE(reg, temp);
2953 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2955 struct drm_device *dev = crtc->dev;
2956 struct drm_i915_private *dev_priv = dev->dev_private;
2957 unsigned long flags;
2960 if (atomic_read(&dev_priv->mm.wedged))
2963 spin_lock_irqsave(&dev->event_lock, flags);
2964 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2965 spin_unlock_irqrestore(&dev->event_lock, flags);
2970 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2972 struct drm_device *dev = crtc->dev;
2973 struct drm_i915_private *dev_priv = dev->dev_private;
2975 if (crtc->fb == NULL)
2978 wait_event(dev_priv->pending_flip_queue,
2979 !intel_crtc_has_pending_flip(crtc));
2981 mutex_lock(&dev->struct_mutex);
2982 intel_finish_fb(crtc->fb);
2983 mutex_unlock(&dev->struct_mutex);
2986 static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
2988 struct drm_device *dev = crtc->dev;
2989 struct intel_encoder *intel_encoder;
2992 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2993 * must be driven by its own crtc; no sharing is possible.
2995 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2996 switch (intel_encoder->type) {
2997 case INTEL_OUTPUT_EDP:
2998 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
3007 static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
3009 return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
3012 /* Program iCLKIP clock to the desired frequency */
3013 static void lpt_program_iclkip(struct drm_crtc *crtc)
3015 struct drm_device *dev = crtc->dev;
3016 struct drm_i915_private *dev_priv = dev->dev_private;
3017 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3020 /* It is necessary to ungate the pixclk gate prior to programming
3021 * the divisors, and gate it back when it is done.
3023 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3025 /* Disable SSCCTL */
3026 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3027 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
3028 SBI_SSCCTL_DISABLE);
3030 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3031 if (crtc->mode.clock == 20000) {
3036 /* The iCLK virtual clock root frequency is in MHz,
3037 * but the crtc->mode.clock in in KHz. To get the divisors,
3038 * it is necessary to divide one by another, so we
3039 * convert the virtual clock precision to KHz here for higher
3042 u32 iclk_virtual_root_freq = 172800 * 1000;
3043 u32 iclk_pi_range = 64;
3044 u32 desired_divisor, msb_divisor_value, pi_value;
3046 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
3047 msb_divisor_value = desired_divisor / iclk_pi_range;
3048 pi_value = desired_divisor % iclk_pi_range;
3051 divsel = msb_divisor_value - 2;
3052 phaseinc = pi_value;
3055 /* This should not happen with any sane values */
3056 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3057 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3058 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3059 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3061 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3068 /* Program SSCDIVINTPHASE6 */
3069 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
3070 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3071 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3072 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3073 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3074 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3075 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3077 intel_sbi_write(dev_priv,
3078 SBI_SSCDIVINTPHASE6,
3081 /* Program SSCAUXDIV */
3082 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
3083 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3084 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3085 intel_sbi_write(dev_priv,
3090 /* Enable modulator and associated divider */
3091 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
3092 temp &= ~SBI_SSCCTL_DISABLE;
3093 intel_sbi_write(dev_priv,
3097 /* Wait for initialization time */
3100 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3104 * Enable PCH resources required for PCH ports:
3106 * - FDI training & RX/TX
3107 * - update transcoder timings
3108 * - DP transcoding bits
3111 static void ironlake_pch_enable(struct drm_crtc *crtc)
3113 struct drm_device *dev = crtc->dev;
3114 struct drm_i915_private *dev_priv = dev->dev_private;
3115 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3116 int pipe = intel_crtc->pipe;
3119 assert_transcoder_disabled(dev_priv, pipe);
3121 /* Write the TU size bits before fdi link training, so that error
3122 * detection works. */
3123 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3124 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3126 /* For PCH output, training FDI link */
3127 dev_priv->display.fdi_link_train(crtc);
3129 /* XXX: pch pll's can be enabled any time before we enable the PCH
3130 * transcoder, and we actually should do this to not upset any PCH
3131 * transcoder that already use the clock when we share it.
3133 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3134 * unconditionally resets the pll - we need that to have the right LVDS
3135 * enable sequence. */
3136 ironlake_enable_pch_pll(intel_crtc);
3138 if (HAS_PCH_CPT(dev)) {
3141 temp = I915_READ(PCH_DPLL_SEL);
3145 temp |= TRANSA_DPLL_ENABLE;
3146 sel = TRANSA_DPLLB_SEL;
3149 temp |= TRANSB_DPLL_ENABLE;
3150 sel = TRANSB_DPLLB_SEL;
3153 temp |= TRANSC_DPLL_ENABLE;
3154 sel = TRANSC_DPLLB_SEL;
3157 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3161 I915_WRITE(PCH_DPLL_SEL, temp);
3164 /* set transcoder timing, panel must allow it */
3165 assert_panel_unlocked(dev_priv, pipe);
3166 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3167 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3168 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
3170 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3171 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3172 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
3173 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
3175 intel_fdi_normal_train(crtc);
3177 /* For PCH DP, enable TRANS_DP_CTL */
3178 if (HAS_PCH_CPT(dev) &&
3179 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3180 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3181 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
3182 reg = TRANS_DP_CTL(pipe);
3183 temp = I915_READ(reg);
3184 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3185 TRANS_DP_SYNC_MASK |
3187 temp |= (TRANS_DP_OUTPUT_ENABLE |
3188 TRANS_DP_ENH_FRAMING);
3189 temp |= bpc << 9; /* same format but at 11:9 */
3191 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3192 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3193 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3194 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3196 switch (intel_trans_dp_port_sel(crtc)) {
3198 temp |= TRANS_DP_PORT_SEL_B;
3201 temp |= TRANS_DP_PORT_SEL_C;
3204 temp |= TRANS_DP_PORT_SEL_D;
3210 I915_WRITE(reg, temp);
3213 ironlake_enable_pch_transcoder(dev_priv, pipe);
3216 static void lpt_pch_enable(struct drm_crtc *crtc)
3218 struct drm_device *dev = crtc->dev;
3219 struct drm_i915_private *dev_priv = dev->dev_private;
3220 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3221 int pipe = intel_crtc->pipe;
3222 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3224 assert_transcoder_disabled(dev_priv, TRANSCODER_A);
3226 /* Write the TU size bits before fdi link training, so that error
3227 * detection works. */
3228 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3229 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3231 /* For PCH output, training FDI link */
3232 dev_priv->display.fdi_link_train(crtc);
3234 lpt_program_iclkip(crtc);
3236 /* Set transcoder timing. */
3237 I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3238 I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3239 I915_WRITE(_TRANS_HSYNC_A, I915_READ(HSYNC(cpu_transcoder)));
3241 I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3242 I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3243 I915_WRITE(_TRANS_VSYNC_A, I915_READ(VSYNC(cpu_transcoder)));
3244 I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
3246 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3249 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3251 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3256 if (pll->refcount == 0) {
3257 WARN(1, "bad PCH PLL refcount\n");
3262 intel_crtc->pch_pll = NULL;
3265 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3267 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3268 struct intel_pch_pll *pll;
3271 pll = intel_crtc->pch_pll;
3273 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3274 intel_crtc->base.base.id, pll->pll_reg);
3278 if (HAS_PCH_IBX(dev_priv->dev)) {
3279 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3280 i = intel_crtc->pipe;
3281 pll = &dev_priv->pch_plls[i];
3283 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3284 intel_crtc->base.base.id, pll->pll_reg);
3289 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3290 pll = &dev_priv->pch_plls[i];
3292 /* Only want to check enabled timings first */
3293 if (pll->refcount == 0)
3296 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3297 fp == I915_READ(pll->fp0_reg)) {
3298 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3299 intel_crtc->base.base.id,
3300 pll->pll_reg, pll->refcount, pll->active);
3306 /* Ok no matching timings, maybe there's a free one? */
3307 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3308 pll = &dev_priv->pch_plls[i];
3309 if (pll->refcount == 0) {
3310 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3311 intel_crtc->base.base.id, pll->pll_reg);
3319 intel_crtc->pch_pll = pll;
3321 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3322 prepare: /* separate function? */
3323 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3325 /* Wait for the clocks to stabilize before rewriting the regs */
3326 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3327 POSTING_READ(pll->pll_reg);
3330 I915_WRITE(pll->fp0_reg, fp);
3331 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3336 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3338 struct drm_i915_private *dev_priv = dev->dev_private;
3339 int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3342 temp = I915_READ(dslreg);
3344 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3345 /* Without this, mode sets may fail silently on FDI */
3346 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3348 I915_WRITE(tc2reg, 0);
3349 if (wait_for(I915_READ(dslreg) != temp, 5))
3350 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3354 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3356 struct drm_device *dev = crtc->dev;
3357 struct drm_i915_private *dev_priv = dev->dev_private;
3358 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3359 struct intel_encoder *encoder;
3360 int pipe = intel_crtc->pipe;
3361 int plane = intel_crtc->plane;
3365 WARN_ON(!crtc->enabled);
3367 if (intel_crtc->active)
3370 intel_crtc->active = true;
3371 intel_update_watermarks(dev);
3373 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3374 temp = I915_READ(PCH_LVDS);
3375 if ((temp & LVDS_PORT_EN) == 0)
3376 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3379 is_pch_port = ironlake_crtc_driving_pch(crtc);
3382 /* Note: FDI PLL enabling _must_ be done before we enable the
3383 * cpu pipes, hence this is separate from all the other fdi/pch
3385 ironlake_fdi_pll_enable(intel_crtc);
3387 assert_fdi_tx_disabled(dev_priv, pipe);
3388 assert_fdi_rx_disabled(dev_priv, pipe);
3391 for_each_encoder_on_crtc(dev, crtc, encoder)
3392 if (encoder->pre_enable)
3393 encoder->pre_enable(encoder);
3395 /* Enable panel fitting for LVDS */
3396 if (dev_priv->pch_pf_size &&
3397 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3398 /* Force use of hard-coded filter coefficients
3399 * as some pre-programmed values are broken,
3402 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3403 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3404 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3408 * On ILK+ LUT must be loaded before the pipe is running but with
3411 intel_crtc_load_lut(crtc);
3413 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3414 intel_enable_plane(dev_priv, plane, pipe);
3417 ironlake_pch_enable(crtc);
3419 mutex_lock(&dev->struct_mutex);
3420 intel_update_fbc(dev);
3421 mutex_unlock(&dev->struct_mutex);
3423 intel_crtc_update_cursor(crtc, true);
3425 for_each_encoder_on_crtc(dev, crtc, encoder)
3426 encoder->enable(encoder);
3428 if (HAS_PCH_CPT(dev))
3429 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3432 * There seems to be a race in PCH platform hw (at least on some
3433 * outputs) where an enabled pipe still completes any pageflip right
3434 * away (as if the pipe is off) instead of waiting for vblank. As soon
3435 * as the first vblank happend, everything works as expected. Hence just
3436 * wait for one vblank before returning to avoid strange things
3439 intel_wait_for_vblank(dev, intel_crtc->pipe);
3442 static void haswell_crtc_enable(struct drm_crtc *crtc)
3444 struct drm_device *dev = crtc->dev;
3445 struct drm_i915_private *dev_priv = dev->dev_private;
3446 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3447 struct intel_encoder *encoder;
3448 int pipe = intel_crtc->pipe;
3449 int plane = intel_crtc->plane;
3452 WARN_ON(!crtc->enabled);
3454 if (intel_crtc->active)
3457 intel_crtc->active = true;
3458 intel_update_watermarks(dev);
3460 is_pch_port = haswell_crtc_driving_pch(crtc);
3463 ironlake_fdi_pll_enable(intel_crtc);
3465 for_each_encoder_on_crtc(dev, crtc, encoder)
3466 if (encoder->pre_enable)
3467 encoder->pre_enable(encoder);
3469 intel_ddi_enable_pipe_clock(intel_crtc);
3471 /* Enable panel fitting for eDP */
3472 if (dev_priv->pch_pf_size && HAS_eDP) {
3473 /* Force use of hard-coded filter coefficients
3474 * as some pre-programmed values are broken,
3477 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3478 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3479 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3483 * On ILK+ LUT must be loaded before the pipe is running but with
3486 intel_crtc_load_lut(crtc);
3488 intel_ddi_set_pipe_settings(crtc);
3489 intel_ddi_enable_pipe_func(crtc);
3491 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3492 intel_enable_plane(dev_priv, plane, pipe);
3495 lpt_pch_enable(crtc);
3497 mutex_lock(&dev->struct_mutex);
3498 intel_update_fbc(dev);
3499 mutex_unlock(&dev->struct_mutex);
3501 intel_crtc_update_cursor(crtc, true);
3503 for_each_encoder_on_crtc(dev, crtc, encoder)
3504 encoder->enable(encoder);
3507 * There seems to be a race in PCH platform hw (at least on some
3508 * outputs) where an enabled pipe still completes any pageflip right
3509 * away (as if the pipe is off) instead of waiting for vblank. As soon
3510 * as the first vblank happend, everything works as expected. Hence just
3511 * wait for one vblank before returning to avoid strange things
3514 intel_wait_for_vblank(dev, intel_crtc->pipe);
3517 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3519 struct drm_device *dev = crtc->dev;
3520 struct drm_i915_private *dev_priv = dev->dev_private;
3521 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3522 struct intel_encoder *encoder;
3523 int pipe = intel_crtc->pipe;
3524 int plane = intel_crtc->plane;
3528 if (!intel_crtc->active)
3531 for_each_encoder_on_crtc(dev, crtc, encoder)
3532 encoder->disable(encoder);
3534 intel_crtc_wait_for_pending_flips(crtc);
3535 drm_vblank_off(dev, pipe);
3536 intel_crtc_update_cursor(crtc, false);
3538 intel_disable_plane(dev_priv, plane, pipe);
3540 if (dev_priv->cfb_plane == plane)
3541 intel_disable_fbc(dev);
3543 intel_disable_pipe(dev_priv, pipe);
3546 I915_WRITE(PF_CTL(pipe), 0);
3547 I915_WRITE(PF_WIN_SZ(pipe), 0);
3549 for_each_encoder_on_crtc(dev, crtc, encoder)
3550 if (encoder->post_disable)
3551 encoder->post_disable(encoder);
3553 ironlake_fdi_disable(crtc);
3555 ironlake_disable_pch_transcoder(dev_priv, pipe);
3557 if (HAS_PCH_CPT(dev)) {
3558 /* disable TRANS_DP_CTL */
3559 reg = TRANS_DP_CTL(pipe);
3560 temp = I915_READ(reg);
3561 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3562 temp |= TRANS_DP_PORT_SEL_NONE;
3563 I915_WRITE(reg, temp);
3565 /* disable DPLL_SEL */
3566 temp = I915_READ(PCH_DPLL_SEL);
3569 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3572 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3575 /* C shares PLL A or B */
3576 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3581 I915_WRITE(PCH_DPLL_SEL, temp);
3584 /* disable PCH DPLL */
3585 intel_disable_pch_pll(intel_crtc);
3587 ironlake_fdi_pll_disable(intel_crtc);
3589 intel_crtc->active = false;
3590 intel_update_watermarks(dev);
3592 mutex_lock(&dev->struct_mutex);
3593 intel_update_fbc(dev);
3594 mutex_unlock(&dev->struct_mutex);
3597 static void haswell_crtc_disable(struct drm_crtc *crtc)
3599 struct drm_device *dev = crtc->dev;
3600 struct drm_i915_private *dev_priv = dev->dev_private;
3601 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3602 struct intel_encoder *encoder;
3603 int pipe = intel_crtc->pipe;
3604 int plane = intel_crtc->plane;
3605 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3608 if (!intel_crtc->active)
3611 is_pch_port = haswell_crtc_driving_pch(crtc);
3613 for_each_encoder_on_crtc(dev, crtc, encoder)
3614 encoder->disable(encoder);
3616 intel_crtc_wait_for_pending_flips(crtc);
3617 drm_vblank_off(dev, pipe);
3618 intel_crtc_update_cursor(crtc, false);
3620 intel_disable_plane(dev_priv, plane, pipe);
3622 if (dev_priv->cfb_plane == plane)
3623 intel_disable_fbc(dev);
3625 intel_disable_pipe(dev_priv, pipe);
3627 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3630 I915_WRITE(PF_CTL(pipe), 0);
3631 I915_WRITE(PF_WIN_SZ(pipe), 0);
3633 intel_ddi_disable_pipe_clock(intel_crtc);
3635 for_each_encoder_on_crtc(dev, crtc, encoder)
3636 if (encoder->post_disable)
3637 encoder->post_disable(encoder);
3640 ironlake_fdi_disable(crtc);
3641 lpt_disable_pch_transcoder(dev_priv, cpu_transcoder);
3642 ironlake_fdi_pll_disable(intel_crtc);
3645 intel_crtc->active = false;
3646 intel_update_watermarks(dev);
3648 mutex_lock(&dev->struct_mutex);
3649 intel_update_fbc(dev);
3650 mutex_unlock(&dev->struct_mutex);
3653 static void ironlake_crtc_off(struct drm_crtc *crtc)
3655 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3656 intel_put_pch_pll(intel_crtc);
3659 static void haswell_crtc_off(struct drm_crtc *crtc)
3661 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3663 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3664 * start using it. */
3665 intel_crtc->cpu_transcoder = intel_crtc->pipe;
3667 intel_ddi_put_crtc_pll(crtc);
3670 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3672 if (!enable && intel_crtc->overlay) {
3673 struct drm_device *dev = intel_crtc->base.dev;
3674 struct drm_i915_private *dev_priv = dev->dev_private;
3676 mutex_lock(&dev->struct_mutex);
3677 dev_priv->mm.interruptible = false;
3678 (void) intel_overlay_switch_off(intel_crtc->overlay);
3679 dev_priv->mm.interruptible = true;
3680 mutex_unlock(&dev->struct_mutex);
3683 /* Let userspace switch the overlay on again. In most cases userspace
3684 * has to recompute where to put it anyway.
3688 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3690 struct drm_device *dev = crtc->dev;
3691 struct drm_i915_private *dev_priv = dev->dev_private;
3692 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3693 struct intel_encoder *encoder;
3694 int pipe = intel_crtc->pipe;
3695 int plane = intel_crtc->plane;
3697 WARN_ON(!crtc->enabled);
3699 if (intel_crtc->active)
3702 intel_crtc->active = true;
3703 intel_update_watermarks(dev);
3705 intel_enable_pll(dev_priv, pipe);
3706 intel_enable_pipe(dev_priv, pipe, false);
3707 intel_enable_plane(dev_priv, plane, pipe);
3709 intel_crtc_load_lut(crtc);
3710 intel_update_fbc(dev);
3712 /* Give the overlay scaler a chance to enable if it's on this pipe */
3713 intel_crtc_dpms_overlay(intel_crtc, true);
3714 intel_crtc_update_cursor(crtc, true);
3716 for_each_encoder_on_crtc(dev, crtc, encoder)
3717 encoder->enable(encoder);
3720 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3722 struct drm_device *dev = crtc->dev;
3723 struct drm_i915_private *dev_priv = dev->dev_private;
3724 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3725 struct intel_encoder *encoder;
3726 int pipe = intel_crtc->pipe;
3727 int plane = intel_crtc->plane;
3730 if (!intel_crtc->active)
3733 for_each_encoder_on_crtc(dev, crtc, encoder)
3734 encoder->disable(encoder);
3736 /* Give the overlay scaler a chance to disable if it's on this pipe */
3737 intel_crtc_wait_for_pending_flips(crtc);
3738 drm_vblank_off(dev, pipe);
3739 intel_crtc_dpms_overlay(intel_crtc, false);
3740 intel_crtc_update_cursor(crtc, false);
3742 if (dev_priv->cfb_plane == plane)
3743 intel_disable_fbc(dev);
3745 intel_disable_plane(dev_priv, plane, pipe);
3746 intel_disable_pipe(dev_priv, pipe);
3747 intel_disable_pll(dev_priv, pipe);
3749 intel_crtc->active = false;
3750 intel_update_fbc(dev);
3751 intel_update_watermarks(dev);
3754 static void i9xx_crtc_off(struct drm_crtc *crtc)
3758 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3761 struct drm_device *dev = crtc->dev;
3762 struct drm_i915_master_private *master_priv;
3763 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3764 int pipe = intel_crtc->pipe;
3766 if (!dev->primary->master)
3769 master_priv = dev->primary->master->driver_priv;
3770 if (!master_priv->sarea_priv)
3775 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3776 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3779 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3780 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3783 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3789 * Sets the power management mode of the pipe and plane.
3791 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3793 struct drm_device *dev = crtc->dev;
3794 struct drm_i915_private *dev_priv = dev->dev_private;
3795 struct intel_encoder *intel_encoder;
3796 bool enable = false;
3798 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3799 enable |= intel_encoder->connectors_active;
3802 dev_priv->display.crtc_enable(crtc);
3804 dev_priv->display.crtc_disable(crtc);
3806 intel_crtc_update_sarea(crtc, enable);
3809 static void intel_crtc_noop(struct drm_crtc *crtc)
3813 static void intel_crtc_disable(struct drm_crtc *crtc)
3815 struct drm_device *dev = crtc->dev;
3816 struct drm_connector *connector;
3817 struct drm_i915_private *dev_priv = dev->dev_private;
3819 /* crtc should still be enabled when we disable it. */
3820 WARN_ON(!crtc->enabled);
3822 dev_priv->display.crtc_disable(crtc);
3823 intel_crtc_update_sarea(crtc, false);
3824 dev_priv->display.off(crtc);
3826 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3827 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3830 mutex_lock(&dev->struct_mutex);
3831 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3832 mutex_unlock(&dev->struct_mutex);
3836 /* Update computed state. */
3837 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3838 if (!connector->encoder || !connector->encoder->crtc)
3841 if (connector->encoder->crtc != crtc)
3844 connector->dpms = DRM_MODE_DPMS_OFF;
3845 to_intel_encoder(connector->encoder)->connectors_active = false;
3849 void intel_modeset_disable(struct drm_device *dev)
3851 struct drm_crtc *crtc;
3853 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3855 intel_crtc_disable(crtc);
3859 void intel_encoder_noop(struct drm_encoder *encoder)
3863 void intel_encoder_destroy(struct drm_encoder *encoder)
3865 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3867 drm_encoder_cleanup(encoder);
3868 kfree(intel_encoder);
3871 /* Simple dpms helper for encodres with just one connector, no cloning and only
3872 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3873 * state of the entire output pipe. */
3874 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3876 if (mode == DRM_MODE_DPMS_ON) {
3877 encoder->connectors_active = true;
3879 intel_crtc_update_dpms(encoder->base.crtc);
3881 encoder->connectors_active = false;
3883 intel_crtc_update_dpms(encoder->base.crtc);
3887 /* Cross check the actual hw state with our own modeset state tracking (and it's
3888 * internal consistency). */
3889 static void intel_connector_check_state(struct intel_connector *connector)
3891 if (connector->get_hw_state(connector)) {
3892 struct intel_encoder *encoder = connector->encoder;
3893 struct drm_crtc *crtc;
3894 bool encoder_enabled;
3897 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3898 connector->base.base.id,
3899 drm_get_connector_name(&connector->base));
3901 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3902 "wrong connector dpms state\n");
3903 WARN(connector->base.encoder != &encoder->base,
3904 "active connector not linked to encoder\n");
3905 WARN(!encoder->connectors_active,
3906 "encoder->connectors_active not set\n");
3908 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3909 WARN(!encoder_enabled, "encoder not enabled\n");
3910 if (WARN_ON(!encoder->base.crtc))
3913 crtc = encoder->base.crtc;
3915 WARN(!crtc->enabled, "crtc not enabled\n");
3916 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3917 WARN(pipe != to_intel_crtc(crtc)->pipe,
3918 "encoder active on the wrong pipe\n");
3922 /* Even simpler default implementation, if there's really no special case to
3924 void intel_connector_dpms(struct drm_connector *connector, int mode)
3926 struct intel_encoder *encoder = intel_attached_encoder(connector);
3928 /* All the simple cases only support two dpms states. */
3929 if (mode != DRM_MODE_DPMS_ON)
3930 mode = DRM_MODE_DPMS_OFF;
3932 if (mode == connector->dpms)
3935 connector->dpms = mode;
3937 /* Only need to change hw state when actually enabled */
3938 if (encoder->base.crtc)
3939 intel_encoder_dpms(encoder, mode);
3941 WARN_ON(encoder->connectors_active != false);
3943 intel_modeset_check_state(connector->dev);
3946 /* Simple connector->get_hw_state implementation for encoders that support only
3947 * one connector and no cloning and hence the encoder state determines the state
3948 * of the connector. */
3949 bool intel_connector_get_hw_state(struct intel_connector *connector)
3952 struct intel_encoder *encoder = connector->encoder;
3954 return encoder->get_hw_state(encoder, &pipe);
3957 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3958 const struct drm_display_mode *mode,
3959 struct drm_display_mode *adjusted_mode)
3961 struct drm_device *dev = crtc->dev;
3963 if (HAS_PCH_SPLIT(dev)) {
3964 /* FDI link clock is fixed at 2.7G */
3965 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3969 /* All interlaced capable intel hw wants timings in frames. Note though
3970 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3971 * timings, so we need to be careful not to clobber these.*/
3972 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3973 drm_mode_set_crtcinfo(adjusted_mode, 0);
3975 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3976 * with a hsync front porch of 0.
3978 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3979 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3985 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3987 return 400000; /* FIXME */
3990 static int i945_get_display_clock_speed(struct drm_device *dev)
3995 static int i915_get_display_clock_speed(struct drm_device *dev)
4000 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4005 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4009 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4011 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4014 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4015 case GC_DISPLAY_CLOCK_333_MHZ:
4018 case GC_DISPLAY_CLOCK_190_200_MHZ:
4024 static int i865_get_display_clock_speed(struct drm_device *dev)
4029 static int i855_get_display_clock_speed(struct drm_device *dev)
4032 /* Assume that the hardware is in the high speed state. This
4033 * should be the default.
4035 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4036 case GC_CLOCK_133_200:
4037 case GC_CLOCK_100_200:
4039 case GC_CLOCK_166_250:
4041 case GC_CLOCK_100_133:
4045 /* Shouldn't happen */
4049 static int i830_get_display_clock_speed(struct drm_device *dev)
4063 fdi_reduce_ratio(u32 *num, u32 *den)
4065 while (*num > 0xffffff || *den > 0xffffff) {
4072 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
4073 int link_clock, struct fdi_m_n *m_n)
4075 m_n->tu = 64; /* default size */
4077 /* BUG_ON(pixel_clock > INT_MAX / 36); */
4078 m_n->gmch_m = bits_per_pixel * pixel_clock;
4079 m_n->gmch_n = link_clock * nlanes * 8;
4080 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
4082 m_n->link_m = pixel_clock;
4083 m_n->link_n = link_clock;
4084 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
4087 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4089 if (i915_panel_use_ssc >= 0)
4090 return i915_panel_use_ssc != 0;
4091 return dev_priv->lvds_use_ssc
4092 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4096 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4097 * @crtc: CRTC structure
4098 * @mode: requested mode
4100 * A pipe may be connected to one or more outputs. Based on the depth of the
4101 * attached framebuffer, choose a good color depth to use on the pipe.
4103 * If possible, match the pipe depth to the fb depth. In some cases, this
4104 * isn't ideal, because the connected output supports a lesser or restricted
4105 * set of depths. Resolve that here:
4106 * LVDS typically supports only 6bpc, so clamp down in that case
4107 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4108 * Displays may support a restricted set as well, check EDID and clamp as
4110 * DP may want to dither down to 6bpc to fit larger modes
4113 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4114 * true if they don't match).
4116 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4117 struct drm_framebuffer *fb,
4118 unsigned int *pipe_bpp,
4119 struct drm_display_mode *mode)
4121 struct drm_device *dev = crtc->dev;
4122 struct drm_i915_private *dev_priv = dev->dev_private;
4123 struct drm_connector *connector;
4124 struct intel_encoder *intel_encoder;
4125 unsigned int display_bpc = UINT_MAX, bpc;
4127 /* Walk the encoders & connectors on this crtc, get min bpc */
4128 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4130 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4131 unsigned int lvds_bpc;
4133 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4139 if (lvds_bpc < display_bpc) {
4140 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4141 display_bpc = lvds_bpc;
4146 /* Not one of the known troublemakers, check the EDID */
4147 list_for_each_entry(connector, &dev->mode_config.connector_list,
4149 if (connector->encoder != &intel_encoder->base)
4152 /* Don't use an invalid EDID bpc value */
4153 if (connector->display_info.bpc &&
4154 connector->display_info.bpc < display_bpc) {
4155 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4156 display_bpc = connector->display_info.bpc;
4161 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4162 * through, clamp it down. (Note: >12bpc will be caught below.)
4164 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4165 if (display_bpc > 8 && display_bpc < 12) {
4166 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
4169 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
4175 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4176 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4181 * We could just drive the pipe at the highest bpc all the time and
4182 * enable dithering as needed, but that costs bandwidth. So choose
4183 * the minimum value that expresses the full color range of the fb but
4184 * also stays within the max display bpc discovered above.
4187 switch (fb->depth) {
4189 bpc = 8; /* since we go through a colormap */
4193 bpc = 6; /* min is 18bpp */
4205 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4206 bpc = min((unsigned int)8, display_bpc);
4210 display_bpc = min(display_bpc, bpc);
4212 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4215 *pipe_bpp = display_bpc * 3;
4217 return display_bpc != bpc;
4220 static int vlv_get_refclk(struct drm_crtc *crtc)
4222 struct drm_device *dev = crtc->dev;
4223 struct drm_i915_private *dev_priv = dev->dev_private;
4224 int refclk = 27000; /* for DP & HDMI */
4226 return 100000; /* only one validated so far */
4228 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4230 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4231 if (intel_panel_use_ssc(dev_priv))
4235 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4242 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4244 struct drm_device *dev = crtc->dev;
4245 struct drm_i915_private *dev_priv = dev->dev_private;
4248 if (IS_VALLEYVIEW(dev)) {
4249 refclk = vlv_get_refclk(crtc);
4250 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4251 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4252 refclk = dev_priv->lvds_ssc_freq * 1000;
4253 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4255 } else if (!IS_GEN2(dev)) {
4264 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4265 intel_clock_t *clock)
4267 /* SDVO TV has fixed PLL values depend on its clock range,
4268 this mirrors vbios setting. */
4269 if (adjusted_mode->clock >= 100000
4270 && adjusted_mode->clock < 140500) {
4276 } else if (adjusted_mode->clock >= 140500
4277 && adjusted_mode->clock <= 200000) {
4286 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4287 intel_clock_t *clock,
4288 intel_clock_t *reduced_clock)
4290 struct drm_device *dev = crtc->dev;
4291 struct drm_i915_private *dev_priv = dev->dev_private;
4292 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4293 int pipe = intel_crtc->pipe;
4296 if (IS_PINEVIEW(dev)) {
4297 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4299 fp2 = (1 << reduced_clock->n) << 16 |
4300 reduced_clock->m1 << 8 | reduced_clock->m2;
4302 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4304 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4308 I915_WRITE(FP0(pipe), fp);
4310 intel_crtc->lowfreq_avail = false;
4311 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4312 reduced_clock && i915_powersave) {
4313 I915_WRITE(FP1(pipe), fp2);
4314 intel_crtc->lowfreq_avail = true;
4316 I915_WRITE(FP1(pipe), fp);
4320 static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
4321 struct drm_display_mode *adjusted_mode)
4323 struct drm_device *dev = crtc->dev;
4324 struct drm_i915_private *dev_priv = dev->dev_private;
4325 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4326 int pipe = intel_crtc->pipe;
4329 temp = I915_READ(LVDS);
4330 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4332 temp |= LVDS_PIPEB_SELECT;
4334 temp &= ~LVDS_PIPEB_SELECT;
4336 /* set the corresponsding LVDS_BORDER bit */
4337 temp |= dev_priv->lvds_border_bits;
4338 /* Set the B0-B3 data pairs corresponding to whether we're going to
4339 * set the DPLLs for dual-channel mode or not.
4342 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4344 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4346 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4347 * appropriately here, but we need to look more thoroughly into how
4348 * panels behave in the two modes.
4350 /* set the dithering flag on LVDS as needed */
4351 if (INTEL_INFO(dev)->gen >= 4) {
4352 if (dev_priv->lvds_dither)
4353 temp |= LVDS_ENABLE_DITHER;
4355 temp &= ~LVDS_ENABLE_DITHER;
4357 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4358 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4359 temp |= LVDS_HSYNC_POLARITY;
4360 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4361 temp |= LVDS_VSYNC_POLARITY;
4362 I915_WRITE(LVDS, temp);
4365 static void vlv_update_pll(struct drm_crtc *crtc,
4366 struct drm_display_mode *mode,
4367 struct drm_display_mode *adjusted_mode,
4368 intel_clock_t *clock, intel_clock_t *reduced_clock,
4371 struct drm_device *dev = crtc->dev;
4372 struct drm_i915_private *dev_priv = dev->dev_private;
4373 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4374 int pipe = intel_crtc->pipe;
4375 u32 dpll, mdiv, pdiv;
4376 u32 bestn, bestm1, bestm2, bestp1, bestp2;
4380 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4381 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4383 dpll = DPLL_VGA_MODE_DIS;
4384 dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4385 dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4386 dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4388 I915_WRITE(DPLL(pipe), dpll);
4389 POSTING_READ(DPLL(pipe));
4398 * In Valleyview PLL and program lane counter registers are exposed
4399 * through DPIO interface
4401 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4402 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4403 mdiv |= ((bestn << DPIO_N_SHIFT));
4404 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4405 mdiv |= (1 << DPIO_K_SHIFT);
4406 mdiv |= DPIO_ENABLE_CALIBRATION;
4407 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4409 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4411 pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
4412 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4413 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4414 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4415 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4417 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
4419 dpll |= DPLL_VCO_ENABLE;
4420 I915_WRITE(DPLL(pipe), dpll);
4421 POSTING_READ(DPLL(pipe));
4422 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4423 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4425 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4427 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4428 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4430 I915_WRITE(DPLL(pipe), dpll);
4432 /* Wait for the clocks to stabilize. */
4433 POSTING_READ(DPLL(pipe));
4438 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4440 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4444 I915_WRITE(DPLL_MD(pipe), temp);
4445 POSTING_READ(DPLL_MD(pipe));
4447 /* Now program lane control registers */
4448 if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4449 || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4454 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4456 if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4461 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4465 static void i9xx_update_pll(struct drm_crtc *crtc,
4466 struct drm_display_mode *mode,
4467 struct drm_display_mode *adjusted_mode,
4468 intel_clock_t *clock, intel_clock_t *reduced_clock,
4471 struct drm_device *dev = crtc->dev;
4472 struct drm_i915_private *dev_priv = dev->dev_private;
4473 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4474 int pipe = intel_crtc->pipe;
4478 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4480 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4481 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4483 dpll = DPLL_VGA_MODE_DIS;
4485 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4486 dpll |= DPLLB_MODE_LVDS;
4488 dpll |= DPLLB_MODE_DAC_SERIAL;
4490 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4491 if (pixel_multiplier > 1) {
4492 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4493 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4495 dpll |= DPLL_DVO_HIGH_SPEED;
4497 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4498 dpll |= DPLL_DVO_HIGH_SPEED;
4500 /* compute bitmask from p1 value */
4501 if (IS_PINEVIEW(dev))
4502 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4504 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4505 if (IS_G4X(dev) && reduced_clock)
4506 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4508 switch (clock->p2) {
4510 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4513 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4516 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4519 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4522 if (INTEL_INFO(dev)->gen >= 4)
4523 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4525 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4526 dpll |= PLL_REF_INPUT_TVCLKINBC;
4527 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4528 /* XXX: just matching BIOS for now */
4529 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4531 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4532 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4533 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4535 dpll |= PLL_REF_INPUT_DREFCLK;
4537 dpll |= DPLL_VCO_ENABLE;
4538 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4539 POSTING_READ(DPLL(pipe));
4542 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4543 * This is an exception to the general rule that mode_set doesn't turn
4546 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4547 intel_update_lvds(crtc, clock, adjusted_mode);
4549 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4550 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4552 I915_WRITE(DPLL(pipe), dpll);
4554 /* Wait for the clocks to stabilize. */
4555 POSTING_READ(DPLL(pipe));
4558 if (INTEL_INFO(dev)->gen >= 4) {
4561 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4563 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4567 I915_WRITE(DPLL_MD(pipe), temp);
4569 /* The pixel multiplier can only be updated once the
4570 * DPLL is enabled and the clocks are stable.
4572 * So write it again.
4574 I915_WRITE(DPLL(pipe), dpll);
4578 static void i8xx_update_pll(struct drm_crtc *crtc,
4579 struct drm_display_mode *adjusted_mode,
4580 intel_clock_t *clock, intel_clock_t *reduced_clock,
4583 struct drm_device *dev = crtc->dev;
4584 struct drm_i915_private *dev_priv = dev->dev_private;
4585 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4586 int pipe = intel_crtc->pipe;
4589 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4591 dpll = DPLL_VGA_MODE_DIS;
4593 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4594 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4597 dpll |= PLL_P1_DIVIDE_BY_TWO;
4599 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4601 dpll |= PLL_P2_DIVIDE_BY_4;
4604 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4605 /* XXX: just matching BIOS for now */
4606 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4608 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4609 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4610 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4612 dpll |= PLL_REF_INPUT_DREFCLK;
4614 dpll |= DPLL_VCO_ENABLE;
4615 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4616 POSTING_READ(DPLL(pipe));
4619 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4620 * This is an exception to the general rule that mode_set doesn't turn
4623 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4624 intel_update_lvds(crtc, clock, adjusted_mode);
4626 I915_WRITE(DPLL(pipe), dpll);
4628 /* Wait for the clocks to stabilize. */
4629 POSTING_READ(DPLL(pipe));
4632 /* The pixel multiplier can only be updated once the
4633 * DPLL is enabled and the clocks are stable.
4635 * So write it again.
4637 I915_WRITE(DPLL(pipe), dpll);
4640 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4641 struct drm_display_mode *mode,
4642 struct drm_display_mode *adjusted_mode)
4644 struct drm_device *dev = intel_crtc->base.dev;
4645 struct drm_i915_private *dev_priv = dev->dev_private;
4646 enum pipe pipe = intel_crtc->pipe;
4647 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
4648 uint32_t vsyncshift;
4650 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4651 /* the chip adds 2 halflines automatically */
4652 adjusted_mode->crtc_vtotal -= 1;
4653 adjusted_mode->crtc_vblank_end -= 1;
4654 vsyncshift = adjusted_mode->crtc_hsync_start
4655 - adjusted_mode->crtc_htotal / 2;
4660 if (INTEL_INFO(dev)->gen > 3)
4661 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4663 I915_WRITE(HTOTAL(cpu_transcoder),
4664 (adjusted_mode->crtc_hdisplay - 1) |
4665 ((adjusted_mode->crtc_htotal - 1) << 16));
4666 I915_WRITE(HBLANK(cpu_transcoder),
4667 (adjusted_mode->crtc_hblank_start - 1) |
4668 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4669 I915_WRITE(HSYNC(cpu_transcoder),
4670 (adjusted_mode->crtc_hsync_start - 1) |
4671 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4673 I915_WRITE(VTOTAL(cpu_transcoder),
4674 (adjusted_mode->crtc_vdisplay - 1) |
4675 ((adjusted_mode->crtc_vtotal - 1) << 16));
4676 I915_WRITE(VBLANK(cpu_transcoder),
4677 (adjusted_mode->crtc_vblank_start - 1) |
4678 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4679 I915_WRITE(VSYNC(cpu_transcoder),
4680 (adjusted_mode->crtc_vsync_start - 1) |
4681 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4683 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4684 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4685 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4687 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4688 (pipe == PIPE_B || pipe == PIPE_C))
4689 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4691 /* pipesrc controls the size that is scaled from, which should
4692 * always be the user's requested size.
4694 I915_WRITE(PIPESRC(pipe),
4695 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4698 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4699 struct drm_display_mode *mode,
4700 struct drm_display_mode *adjusted_mode,
4702 struct drm_framebuffer *fb)
4704 struct drm_device *dev = crtc->dev;
4705 struct drm_i915_private *dev_priv = dev->dev_private;
4706 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4707 int pipe = intel_crtc->pipe;
4708 int plane = intel_crtc->plane;
4709 int refclk, num_connectors = 0;
4710 intel_clock_t clock, reduced_clock;
4711 u32 dspcntr, pipeconf;
4712 bool ok, has_reduced_clock = false, is_sdvo = false;
4713 bool is_lvds = false, is_tv = false, is_dp = false;
4714 struct intel_encoder *encoder;
4715 const intel_limit_t *limit;
4718 for_each_encoder_on_crtc(dev, crtc, encoder) {
4719 switch (encoder->type) {
4720 case INTEL_OUTPUT_LVDS:
4723 case INTEL_OUTPUT_SDVO:
4724 case INTEL_OUTPUT_HDMI:
4726 if (encoder->needs_tv_clock)
4729 case INTEL_OUTPUT_TVOUT:
4732 case INTEL_OUTPUT_DISPLAYPORT:
4740 refclk = i9xx_get_refclk(crtc, num_connectors);
4743 * Returns a set of divisors for the desired target clock with the given
4744 * refclk, or FALSE. The returned values represent the clock equation:
4745 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4747 limit = intel_limit(crtc, refclk);
4748 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4751 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4755 /* Ensure that the cursor is valid for the new mode before changing... */
4756 intel_crtc_update_cursor(crtc, true);
4758 if (is_lvds && dev_priv->lvds_downclock_avail) {
4760 * Ensure we match the reduced clock's P to the target clock.
4761 * If the clocks don't match, we can't switch the display clock
4762 * by using the FP0/FP1. In such case we will disable the LVDS
4763 * downclock feature.
4765 has_reduced_clock = limit->find_pll(limit, crtc,
4766 dev_priv->lvds_downclock,
4772 if (is_sdvo && is_tv)
4773 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4776 i8xx_update_pll(crtc, adjusted_mode, &clock,
4777 has_reduced_clock ? &reduced_clock : NULL,
4779 else if (IS_VALLEYVIEW(dev))
4780 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4781 has_reduced_clock ? &reduced_clock : NULL,
4784 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4785 has_reduced_clock ? &reduced_clock : NULL,
4788 /* setup pipeconf */
4789 pipeconf = I915_READ(PIPECONF(pipe));
4791 /* Set up the display plane register */
4792 dspcntr = DISPPLANE_GAMMA_ENABLE;
4795 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4797 dspcntr |= DISPPLANE_SEL_PIPE_B;
4799 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4800 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4803 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4807 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4808 pipeconf |= PIPECONF_DOUBLE_WIDE;
4810 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4813 /* default to 8bpc */
4814 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4816 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4817 pipeconf |= PIPECONF_BPP_6 |
4818 PIPECONF_DITHER_EN |
4819 PIPECONF_DITHER_TYPE_SP;
4823 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4824 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4825 pipeconf |= PIPECONF_BPP_6 |
4827 I965_PIPECONF_ACTIVE;
4831 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4832 drm_mode_debug_printmodeline(mode);
4834 if (HAS_PIPE_CXSR(dev)) {
4835 if (intel_crtc->lowfreq_avail) {
4836 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4837 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4839 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4840 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4844 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4845 if (!IS_GEN2(dev) &&
4846 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4847 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4849 pipeconf |= PIPECONF_PROGRESSIVE;
4851 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
4853 /* pipesrc and dspsize control the size that is scaled from,
4854 * which should always be the user's requested size.
4856 I915_WRITE(DSPSIZE(plane),
4857 ((mode->vdisplay - 1) << 16) |
4858 (mode->hdisplay - 1));
4859 I915_WRITE(DSPPOS(plane), 0);
4861 I915_WRITE(PIPECONF(pipe), pipeconf);
4862 POSTING_READ(PIPECONF(pipe));
4863 intel_enable_pipe(dev_priv, pipe, false);
4865 intel_wait_for_vblank(dev, pipe);
4867 I915_WRITE(DSPCNTR(plane), dspcntr);
4868 POSTING_READ(DSPCNTR(plane));
4870 ret = intel_pipe_set_base(crtc, x, y, fb);
4872 intel_update_watermarks(dev);
4878 * Initialize reference clocks when the driver loads
4880 void ironlake_init_pch_refclk(struct drm_device *dev)
4882 struct drm_i915_private *dev_priv = dev->dev_private;
4883 struct drm_mode_config *mode_config = &dev->mode_config;
4884 struct intel_encoder *encoder;
4886 bool has_lvds = false;
4887 bool has_cpu_edp = false;
4888 bool has_pch_edp = false;
4889 bool has_panel = false;
4890 bool has_ck505 = false;
4891 bool can_ssc = false;
4893 /* We need to take the global config into account */
4894 list_for_each_entry(encoder, &mode_config->encoder_list,
4896 switch (encoder->type) {
4897 case INTEL_OUTPUT_LVDS:
4901 case INTEL_OUTPUT_EDP:
4903 if (intel_encoder_is_pch_edp(&encoder->base))
4911 if (HAS_PCH_IBX(dev)) {
4912 has_ck505 = dev_priv->display_clock_mode;
4913 can_ssc = has_ck505;
4919 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4920 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4923 /* Ironlake: try to setup display ref clock before DPLL
4924 * enabling. This is only under driver's control after
4925 * PCH B stepping, previous chipset stepping should be
4926 * ignoring this setting.
4928 temp = I915_READ(PCH_DREF_CONTROL);
4929 /* Always enable nonspread source */
4930 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4933 temp |= DREF_NONSPREAD_CK505_ENABLE;
4935 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4938 temp &= ~DREF_SSC_SOURCE_MASK;
4939 temp |= DREF_SSC_SOURCE_ENABLE;
4941 /* SSC must be turned on before enabling the CPU output */
4942 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4943 DRM_DEBUG_KMS("Using SSC on panel\n");
4944 temp |= DREF_SSC1_ENABLE;
4946 temp &= ~DREF_SSC1_ENABLE;
4948 /* Get SSC going before enabling the outputs */
4949 I915_WRITE(PCH_DREF_CONTROL, temp);
4950 POSTING_READ(PCH_DREF_CONTROL);
4953 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4955 /* Enable CPU source on CPU attached eDP */
4957 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4958 DRM_DEBUG_KMS("Using SSC on eDP\n");
4959 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4962 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4964 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4966 I915_WRITE(PCH_DREF_CONTROL, temp);
4967 POSTING_READ(PCH_DREF_CONTROL);
4970 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4972 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4974 /* Turn off CPU output */
4975 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4977 I915_WRITE(PCH_DREF_CONTROL, temp);
4978 POSTING_READ(PCH_DREF_CONTROL);
4981 /* Turn off the SSC source */
4982 temp &= ~DREF_SSC_SOURCE_MASK;
4983 temp |= DREF_SSC_SOURCE_DISABLE;
4986 temp &= ~ DREF_SSC1_ENABLE;
4988 I915_WRITE(PCH_DREF_CONTROL, temp);
4989 POSTING_READ(PCH_DREF_CONTROL);
4994 static int ironlake_get_refclk(struct drm_crtc *crtc)
4996 struct drm_device *dev = crtc->dev;
4997 struct drm_i915_private *dev_priv = dev->dev_private;
4998 struct intel_encoder *encoder;
4999 struct intel_encoder *edp_encoder = NULL;
5000 int num_connectors = 0;
5001 bool is_lvds = false;
5003 for_each_encoder_on_crtc(dev, crtc, encoder) {
5004 switch (encoder->type) {
5005 case INTEL_OUTPUT_LVDS:
5008 case INTEL_OUTPUT_EDP:
5009 edp_encoder = encoder;
5015 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5016 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5017 dev_priv->lvds_ssc_freq);
5018 return dev_priv->lvds_ssc_freq * 1000;
5024 static void ironlake_set_pipeconf(struct drm_crtc *crtc,
5025 struct drm_display_mode *adjusted_mode,
5028 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5029 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5030 int pipe = intel_crtc->pipe;
5033 val = I915_READ(PIPECONF(pipe));
5035 val &= ~PIPE_BPC_MASK;
5036 switch (intel_crtc->bpp) {
5050 /* Case prevented by intel_choose_pipe_bpp_dither. */
5054 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5056 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5058 val &= ~PIPECONF_INTERLACE_MASK;
5059 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5060 val |= PIPECONF_INTERLACED_ILK;
5062 val |= PIPECONF_PROGRESSIVE;
5064 I915_WRITE(PIPECONF(pipe), val);
5065 POSTING_READ(PIPECONF(pipe));
5068 static void haswell_set_pipeconf(struct drm_crtc *crtc,
5069 struct drm_display_mode *adjusted_mode,
5072 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5073 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5074 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5077 val = I915_READ(PIPECONF(cpu_transcoder));
5079 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5081 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5083 val &= ~PIPECONF_INTERLACE_MASK_HSW;
5084 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5085 val |= PIPECONF_INTERLACED_ILK;
5087 val |= PIPECONF_PROGRESSIVE;
5089 I915_WRITE(PIPECONF(cpu_transcoder), val);
5090 POSTING_READ(PIPECONF(cpu_transcoder));
5093 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5094 struct drm_display_mode *adjusted_mode,
5095 intel_clock_t *clock,
5096 bool *has_reduced_clock,
5097 intel_clock_t *reduced_clock)
5099 struct drm_device *dev = crtc->dev;
5100 struct drm_i915_private *dev_priv = dev->dev_private;
5101 struct intel_encoder *intel_encoder;
5103 const intel_limit_t *limit;
5104 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
5106 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5107 switch (intel_encoder->type) {
5108 case INTEL_OUTPUT_LVDS:
5111 case INTEL_OUTPUT_SDVO:
5112 case INTEL_OUTPUT_HDMI:
5114 if (intel_encoder->needs_tv_clock)
5117 case INTEL_OUTPUT_TVOUT:
5123 refclk = ironlake_get_refclk(crtc);
5126 * Returns a set of divisors for the desired target clock with the given
5127 * refclk, or FALSE. The returned values represent the clock equation:
5128 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5130 limit = intel_limit(crtc, refclk);
5131 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5136 if (is_lvds && dev_priv->lvds_downclock_avail) {
5138 * Ensure we match the reduced clock's P to the target clock.
5139 * If the clocks don't match, we can't switch the display clock
5140 * by using the FP0/FP1. In such case we will disable the LVDS
5141 * downclock feature.
5143 *has_reduced_clock = limit->find_pll(limit, crtc,
5144 dev_priv->lvds_downclock,
5150 if (is_sdvo && is_tv)
5151 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5156 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5158 struct drm_i915_private *dev_priv = dev->dev_private;
5161 temp = I915_READ(SOUTH_CHICKEN1);
5162 if (temp & FDI_BC_BIFURCATION_SELECT)
5165 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5166 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5168 temp |= FDI_BC_BIFURCATION_SELECT;
5169 DRM_DEBUG_KMS("enabling fdi C rx\n");
5170 I915_WRITE(SOUTH_CHICKEN1, temp);
5171 POSTING_READ(SOUTH_CHICKEN1);
5174 static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5176 struct drm_device *dev = intel_crtc->base.dev;
5177 struct drm_i915_private *dev_priv = dev->dev_private;
5178 struct intel_crtc *pipe_B_crtc =
5179 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5181 DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5182 intel_crtc->pipe, intel_crtc->fdi_lanes);
5183 if (intel_crtc->fdi_lanes > 4) {
5184 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5185 intel_crtc->pipe, intel_crtc->fdi_lanes);
5186 /* Clamp lanes to avoid programming the hw with bogus values. */
5187 intel_crtc->fdi_lanes = 4;
5192 if (dev_priv->num_pipe == 2)
5195 switch (intel_crtc->pipe) {
5199 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5200 intel_crtc->fdi_lanes > 2) {
5201 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5202 intel_crtc->pipe, intel_crtc->fdi_lanes);
5203 /* Clamp lanes to avoid programming the hw with bogus values. */
5204 intel_crtc->fdi_lanes = 2;
5209 if (intel_crtc->fdi_lanes > 2)
5210 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5212 cpt_enable_fdi_bc_bifurcation(dev);
5216 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5217 if (intel_crtc->fdi_lanes > 2) {
5218 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5219 intel_crtc->pipe, intel_crtc->fdi_lanes);
5220 /* Clamp lanes to avoid programming the hw with bogus values. */
5221 intel_crtc->fdi_lanes = 2;
5226 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5230 cpt_enable_fdi_bc_bifurcation(dev);
5238 static void ironlake_set_m_n(struct drm_crtc *crtc,
5239 struct drm_display_mode *mode,
5240 struct drm_display_mode *adjusted_mode)
5242 struct drm_device *dev = crtc->dev;
5243 struct drm_i915_private *dev_priv = dev->dev_private;
5244 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5245 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5246 struct intel_encoder *intel_encoder, *edp_encoder = NULL;
5247 struct fdi_m_n m_n = {0};
5248 int target_clock, pixel_multiplier, lane, link_bw;
5249 bool is_dp = false, is_cpu_edp = false;
5251 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5252 switch (intel_encoder->type) {
5253 case INTEL_OUTPUT_DISPLAYPORT:
5256 case INTEL_OUTPUT_EDP:
5258 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5260 edp_encoder = intel_encoder;
5266 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5268 /* CPU eDP doesn't require FDI link, so just set DP M/N
5269 according to current link config */
5271 intel_edp_link_config(edp_encoder, &lane, &link_bw);
5273 /* FDI is a binary signal running at ~2.7GHz, encoding
5274 * each output octet as 10 bits. The actual frequency
5275 * is stored as a divider into a 100MHz clock, and the
5276 * mode pixel clock is stored in units of 1KHz.
5277 * Hence the bw of each lane in terms of the mode signal
5280 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5283 /* [e]DP over FDI requires target mode clock instead of link clock. */
5285 target_clock = intel_edp_target_clock(edp_encoder, mode);
5287 target_clock = mode->clock;
5289 target_clock = adjusted_mode->clock;
5293 * Account for spread spectrum to avoid
5294 * oversubscribing the link. Max center spread
5295 * is 2.5%; use 5% for safety's sake.
5297 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5298 lane = bps / (link_bw * 8) + 1;
5301 intel_crtc->fdi_lanes = lane;
5303 if (pixel_multiplier > 1)
5304 link_bw *= pixel_multiplier;
5305 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5308 I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
5309 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
5310 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
5311 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
5314 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5315 struct drm_display_mode *adjusted_mode,
5316 intel_clock_t *clock, u32 fp)
5318 struct drm_crtc *crtc = &intel_crtc->base;
5319 struct drm_device *dev = crtc->dev;
5320 struct drm_i915_private *dev_priv = dev->dev_private;
5321 struct intel_encoder *intel_encoder;
5323 int factor, pixel_multiplier, num_connectors = 0;
5324 bool is_lvds = false, is_sdvo = false, is_tv = false;
5325 bool is_dp = false, is_cpu_edp = false;
5327 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5328 switch (intel_encoder->type) {
5329 case INTEL_OUTPUT_LVDS:
5332 case INTEL_OUTPUT_SDVO:
5333 case INTEL_OUTPUT_HDMI:
5335 if (intel_encoder->needs_tv_clock)
5338 case INTEL_OUTPUT_TVOUT:
5341 case INTEL_OUTPUT_DISPLAYPORT:
5344 case INTEL_OUTPUT_EDP:
5346 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5354 /* Enable autotuning of the PLL clock (if permissible) */
5357 if ((intel_panel_use_ssc(dev_priv) &&
5358 dev_priv->lvds_ssc_freq == 100) ||
5359 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5361 } else if (is_sdvo && is_tv)
5364 if (clock->m < factor * clock->n)
5370 dpll |= DPLLB_MODE_LVDS;
5372 dpll |= DPLLB_MODE_DAC_SERIAL;
5374 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5375 if (pixel_multiplier > 1) {
5376 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5378 dpll |= DPLL_DVO_HIGH_SPEED;
5380 if (is_dp && !is_cpu_edp)
5381 dpll |= DPLL_DVO_HIGH_SPEED;
5383 /* compute bitmask from p1 value */
5384 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5386 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5388 switch (clock->p2) {
5390 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5393 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5396 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5399 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5403 if (is_sdvo && is_tv)
5404 dpll |= PLL_REF_INPUT_TVCLKINBC;
5406 /* XXX: just matching BIOS for now */
5407 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5409 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5410 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5412 dpll |= PLL_REF_INPUT_DREFCLK;
5417 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5418 struct drm_display_mode *mode,
5419 struct drm_display_mode *adjusted_mode,
5421 struct drm_framebuffer *fb)
5423 struct drm_device *dev = crtc->dev;
5424 struct drm_i915_private *dev_priv = dev->dev_private;
5425 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5426 int pipe = intel_crtc->pipe;
5427 int plane = intel_crtc->plane;
5428 int num_connectors = 0;
5429 intel_clock_t clock, reduced_clock;
5430 u32 dpll, fp = 0, fp2 = 0;
5431 bool ok, has_reduced_clock = false;
5432 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5433 struct intel_encoder *encoder;
5436 bool dither, fdi_config_ok;
5438 for_each_encoder_on_crtc(dev, crtc, encoder) {
5439 switch (encoder->type) {
5440 case INTEL_OUTPUT_LVDS:
5443 case INTEL_OUTPUT_DISPLAYPORT:
5446 case INTEL_OUTPUT_EDP:
5448 if (!intel_encoder_is_pch_edp(&encoder->base))
5456 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5457 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5459 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5460 &has_reduced_clock, &reduced_clock);
5462 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5466 /* Ensure that the cursor is valid for the new mode before changing... */
5467 intel_crtc_update_cursor(crtc, true);
5469 /* determine panel color depth */
5470 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5472 if (is_lvds && dev_priv->lvds_dither)
5475 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5476 if (has_reduced_clock)
5477 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5480 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
5482 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5483 drm_mode_debug_printmodeline(mode);
5485 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5487 struct intel_pch_pll *pll;
5489 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5491 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5496 intel_put_pch_pll(intel_crtc);
5498 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5499 * This is an exception to the general rule that mode_set doesn't turn
5503 temp = I915_READ(PCH_LVDS);
5504 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5505 if (HAS_PCH_CPT(dev)) {
5506 temp &= ~PORT_TRANS_SEL_MASK;
5507 temp |= PORT_TRANS_SEL_CPT(pipe);
5510 temp |= LVDS_PIPEB_SELECT;
5512 temp &= ~LVDS_PIPEB_SELECT;
5515 /* set the corresponsding LVDS_BORDER bit */
5516 temp |= dev_priv->lvds_border_bits;
5517 /* Set the B0-B3 data pairs corresponding to whether we're going to
5518 * set the DPLLs for dual-channel mode or not.
5521 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5523 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5525 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5526 * appropriately here, but we need to look more thoroughly into how
5527 * panels behave in the two modes.
5529 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5530 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5531 temp |= LVDS_HSYNC_POLARITY;
5532 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5533 temp |= LVDS_VSYNC_POLARITY;
5534 I915_WRITE(PCH_LVDS, temp);
5537 if (is_dp && !is_cpu_edp) {
5538 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5540 /* For non-DP output, clear any trans DP clock recovery setting.*/
5541 I915_WRITE(TRANSDATA_M1(pipe), 0);
5542 I915_WRITE(TRANSDATA_N1(pipe), 0);
5543 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5544 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5547 if (intel_crtc->pch_pll) {
5548 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5550 /* Wait for the clocks to stabilize. */
5551 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5554 /* The pixel multiplier can only be updated once the
5555 * DPLL is enabled and the clocks are stable.
5557 * So write it again.
5559 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5562 intel_crtc->lowfreq_avail = false;
5563 if (intel_crtc->pch_pll) {
5564 if (is_lvds && has_reduced_clock && i915_powersave) {
5565 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5566 intel_crtc->lowfreq_avail = true;
5568 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5572 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5574 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5575 * ironlake_check_fdi_lanes. */
5576 ironlake_set_m_n(crtc, mode, adjusted_mode);
5578 fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
5581 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5583 ironlake_set_pipeconf(crtc, adjusted_mode, dither);
5585 intel_wait_for_vblank(dev, pipe);
5587 /* Set up the display plane register */
5588 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5589 POSTING_READ(DSPCNTR(plane));
5591 ret = intel_pipe_set_base(crtc, x, y, fb);
5593 intel_update_watermarks(dev);
5595 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5597 return fdi_config_ok ? ret : -EINVAL;
5600 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5601 struct drm_display_mode *mode,
5602 struct drm_display_mode *adjusted_mode,
5604 struct drm_framebuffer *fb)
5606 struct drm_device *dev = crtc->dev;
5607 struct drm_i915_private *dev_priv = dev->dev_private;
5608 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5609 int pipe = intel_crtc->pipe;
5610 int plane = intel_crtc->plane;
5611 int num_connectors = 0;
5612 intel_clock_t clock, reduced_clock;
5613 u32 dpll = 0, fp = 0, fp2 = 0;
5614 bool ok, has_reduced_clock = false;
5615 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5616 struct intel_encoder *encoder;
5621 for_each_encoder_on_crtc(dev, crtc, encoder) {
5622 switch (encoder->type) {
5623 case INTEL_OUTPUT_LVDS:
5626 case INTEL_OUTPUT_DISPLAYPORT:
5629 case INTEL_OUTPUT_EDP:
5631 if (!intel_encoder_is_pch_edp(&encoder->base))
5640 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5642 intel_crtc->cpu_transcoder = pipe;
5644 /* We are not sure yet this won't happen. */
5645 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5646 INTEL_PCH_TYPE(dev));
5648 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5649 num_connectors, pipe_name(pipe));
5651 WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
5652 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5654 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5656 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5659 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5660 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5664 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5669 /* Ensure that the cursor is valid for the new mode before changing... */
5670 intel_crtc_update_cursor(crtc, true);
5672 /* determine panel color depth */
5673 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5675 if (is_lvds && dev_priv->lvds_dither)
5678 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5679 drm_mode_debug_printmodeline(mode);
5681 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5682 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5683 if (has_reduced_clock)
5684 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5687 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock,
5690 /* CPU eDP is the only output that doesn't need a PCH PLL of its
5691 * own on pre-Haswell/LPT generation */
5693 struct intel_pch_pll *pll;
5695 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5697 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5702 intel_put_pch_pll(intel_crtc);
5704 /* The LVDS pin pair needs to be on before the DPLLs are
5705 * enabled. This is an exception to the general rule that
5706 * mode_set doesn't turn things on.
5709 temp = I915_READ(PCH_LVDS);
5710 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5711 if (HAS_PCH_CPT(dev)) {
5712 temp &= ~PORT_TRANS_SEL_MASK;
5713 temp |= PORT_TRANS_SEL_CPT(pipe);
5716 temp |= LVDS_PIPEB_SELECT;
5718 temp &= ~LVDS_PIPEB_SELECT;
5721 /* set the corresponsding LVDS_BORDER bit */
5722 temp |= dev_priv->lvds_border_bits;
5723 /* Set the B0-B3 data pairs corresponding to whether
5724 * we're going to set the DPLLs for dual-channel mode or
5728 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5730 temp &= ~(LVDS_B0B3_POWER_UP |
5731 LVDS_CLKB_POWER_UP);
5733 /* It would be nice to set 24 vs 18-bit mode
5734 * (LVDS_A3_POWER_UP) appropriately here, but we need to
5735 * look more thoroughly into how panels behave in the
5738 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5739 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5740 temp |= LVDS_HSYNC_POLARITY;
5741 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5742 temp |= LVDS_VSYNC_POLARITY;
5743 I915_WRITE(PCH_LVDS, temp);
5747 if (is_dp && !is_cpu_edp) {
5748 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5750 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5751 /* For non-DP output, clear any trans DP clock recovery
5753 I915_WRITE(TRANSDATA_M1(pipe), 0);
5754 I915_WRITE(TRANSDATA_N1(pipe), 0);
5755 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5756 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5760 intel_crtc->lowfreq_avail = false;
5761 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5762 if (intel_crtc->pch_pll) {
5763 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5765 /* Wait for the clocks to stabilize. */
5766 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5769 /* The pixel multiplier can only be updated once the
5770 * DPLL is enabled and the clocks are stable.
5772 * So write it again.
5774 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5777 if (intel_crtc->pch_pll) {
5778 if (is_lvds && has_reduced_clock && i915_powersave) {
5779 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5780 intel_crtc->lowfreq_avail = true;
5782 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5787 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5789 if (!is_dp || is_cpu_edp)
5790 ironlake_set_m_n(crtc, mode, adjusted_mode);
5792 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5794 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5796 haswell_set_pipeconf(crtc, adjusted_mode, dither);
5798 /* Set up the display plane register */
5799 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5800 POSTING_READ(DSPCNTR(plane));
5802 ret = intel_pipe_set_base(crtc, x, y, fb);
5804 intel_update_watermarks(dev);
5806 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5811 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5812 struct drm_display_mode *mode,
5813 struct drm_display_mode *adjusted_mode,
5815 struct drm_framebuffer *fb)
5817 struct drm_device *dev = crtc->dev;
5818 struct drm_i915_private *dev_priv = dev->dev_private;
5819 struct drm_encoder_helper_funcs *encoder_funcs;
5820 struct intel_encoder *encoder;
5821 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5822 int pipe = intel_crtc->pipe;
5825 drm_vblank_pre_modeset(dev, pipe);
5827 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5829 drm_vblank_post_modeset(dev, pipe);
5834 for_each_encoder_on_crtc(dev, crtc, encoder) {
5835 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5836 encoder->base.base.id,
5837 drm_get_encoder_name(&encoder->base),
5838 mode->base.id, mode->name);
5839 encoder_funcs = encoder->base.helper_private;
5840 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5846 static bool intel_eld_uptodate(struct drm_connector *connector,
5847 int reg_eldv, uint32_t bits_eldv,
5848 int reg_elda, uint32_t bits_elda,
5851 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5852 uint8_t *eld = connector->eld;
5855 i = I915_READ(reg_eldv);
5864 i = I915_READ(reg_elda);
5866 I915_WRITE(reg_elda, i);
5868 for (i = 0; i < eld[2]; i++)
5869 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5875 static void g4x_write_eld(struct drm_connector *connector,
5876 struct drm_crtc *crtc)
5878 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5879 uint8_t *eld = connector->eld;
5884 i = I915_READ(G4X_AUD_VID_DID);
5886 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5887 eldv = G4X_ELDV_DEVCL_DEVBLC;
5889 eldv = G4X_ELDV_DEVCTG;
5891 if (intel_eld_uptodate(connector,
5892 G4X_AUD_CNTL_ST, eldv,
5893 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5894 G4X_HDMIW_HDMIEDID))
5897 i = I915_READ(G4X_AUD_CNTL_ST);
5898 i &= ~(eldv | G4X_ELD_ADDR);
5899 len = (i >> 9) & 0x1f; /* ELD buffer size */
5900 I915_WRITE(G4X_AUD_CNTL_ST, i);
5905 len = min_t(uint8_t, eld[2], len);
5906 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5907 for (i = 0; i < len; i++)
5908 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5910 i = I915_READ(G4X_AUD_CNTL_ST);
5912 I915_WRITE(G4X_AUD_CNTL_ST, i);
5915 static void haswell_write_eld(struct drm_connector *connector,
5916 struct drm_crtc *crtc)
5918 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5919 uint8_t *eld = connector->eld;
5920 struct drm_device *dev = crtc->dev;
5924 int pipe = to_intel_crtc(crtc)->pipe;
5927 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5928 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5929 int aud_config = HSW_AUD_CFG(pipe);
5930 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5933 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5935 /* Audio output enable */
5936 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5937 tmp = I915_READ(aud_cntrl_st2);
5938 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5939 I915_WRITE(aud_cntrl_st2, tmp);
5941 /* Wait for 1 vertical blank */
5942 intel_wait_for_vblank(dev, pipe);
5944 /* Set ELD valid state */
5945 tmp = I915_READ(aud_cntrl_st2);
5946 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5947 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5948 I915_WRITE(aud_cntrl_st2, tmp);
5949 tmp = I915_READ(aud_cntrl_st2);
5950 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5952 /* Enable HDMI mode */
5953 tmp = I915_READ(aud_config);
5954 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5955 /* clear N_programing_enable and N_value_index */
5956 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5957 I915_WRITE(aud_config, tmp);
5959 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5961 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5963 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5964 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5965 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5966 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5968 I915_WRITE(aud_config, 0);
5970 if (intel_eld_uptodate(connector,
5971 aud_cntrl_st2, eldv,
5972 aud_cntl_st, IBX_ELD_ADDRESS,
5976 i = I915_READ(aud_cntrl_st2);
5978 I915_WRITE(aud_cntrl_st2, i);
5983 i = I915_READ(aud_cntl_st);
5984 i &= ~IBX_ELD_ADDRESS;
5985 I915_WRITE(aud_cntl_st, i);
5986 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
5987 DRM_DEBUG_DRIVER("port num:%d\n", i);
5989 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5990 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5991 for (i = 0; i < len; i++)
5992 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5994 i = I915_READ(aud_cntrl_st2);
5996 I915_WRITE(aud_cntrl_st2, i);
6000 static void ironlake_write_eld(struct drm_connector *connector,
6001 struct drm_crtc *crtc)
6003 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6004 uint8_t *eld = connector->eld;
6012 int pipe = to_intel_crtc(crtc)->pipe;
6014 if (HAS_PCH_IBX(connector->dev)) {
6015 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6016 aud_config = IBX_AUD_CFG(pipe);
6017 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6018 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6020 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6021 aud_config = CPT_AUD_CFG(pipe);
6022 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6023 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6026 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6028 i = I915_READ(aud_cntl_st);
6029 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6031 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6032 /* operate blindly on all ports */
6033 eldv = IBX_ELD_VALIDB;
6034 eldv |= IBX_ELD_VALIDB << 4;
6035 eldv |= IBX_ELD_VALIDB << 8;
6037 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
6038 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6041 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6042 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6043 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6044 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6046 I915_WRITE(aud_config, 0);
6048 if (intel_eld_uptodate(connector,
6049 aud_cntrl_st2, eldv,
6050 aud_cntl_st, IBX_ELD_ADDRESS,
6054 i = I915_READ(aud_cntrl_st2);
6056 I915_WRITE(aud_cntrl_st2, i);
6061 i = I915_READ(aud_cntl_st);
6062 i &= ~IBX_ELD_ADDRESS;
6063 I915_WRITE(aud_cntl_st, i);
6065 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6066 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6067 for (i = 0; i < len; i++)
6068 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6070 i = I915_READ(aud_cntrl_st2);
6072 I915_WRITE(aud_cntrl_st2, i);
6075 void intel_write_eld(struct drm_encoder *encoder,
6076 struct drm_display_mode *mode)
6078 struct drm_crtc *crtc = encoder->crtc;
6079 struct drm_connector *connector;
6080 struct drm_device *dev = encoder->dev;
6081 struct drm_i915_private *dev_priv = dev->dev_private;
6083 connector = drm_select_eld(encoder, mode);
6087 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6089 drm_get_connector_name(connector),
6090 connector->encoder->base.id,
6091 drm_get_encoder_name(connector->encoder));
6093 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6095 if (dev_priv->display.write_eld)
6096 dev_priv->display.write_eld(connector, crtc);
6099 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6100 void intel_crtc_load_lut(struct drm_crtc *crtc)
6102 struct drm_device *dev = crtc->dev;
6103 struct drm_i915_private *dev_priv = dev->dev_private;
6104 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6105 int palreg = PALETTE(intel_crtc->pipe);
6108 /* The clocks have to be on to load the palette. */
6109 if (!crtc->enabled || !intel_crtc->active)
6112 /* use legacy palette for Ironlake */
6113 if (HAS_PCH_SPLIT(dev))
6114 palreg = LGC_PALETTE(intel_crtc->pipe);
6116 for (i = 0; i < 256; i++) {
6117 I915_WRITE(palreg + 4 * i,
6118 (intel_crtc->lut_r[i] << 16) |
6119 (intel_crtc->lut_g[i] << 8) |
6120 intel_crtc->lut_b[i]);
6124 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6126 struct drm_device *dev = crtc->dev;
6127 struct drm_i915_private *dev_priv = dev->dev_private;
6128 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6129 bool visible = base != 0;
6132 if (intel_crtc->cursor_visible == visible)
6135 cntl = I915_READ(_CURACNTR);
6137 /* On these chipsets we can only modify the base whilst
6138 * the cursor is disabled.
6140 I915_WRITE(_CURABASE, base);
6142 cntl &= ~(CURSOR_FORMAT_MASK);
6143 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6144 cntl |= CURSOR_ENABLE |
6145 CURSOR_GAMMA_ENABLE |
6148 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6149 I915_WRITE(_CURACNTR, cntl);
6151 intel_crtc->cursor_visible = visible;
6154 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6156 struct drm_device *dev = crtc->dev;
6157 struct drm_i915_private *dev_priv = dev->dev_private;
6158 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6159 int pipe = intel_crtc->pipe;
6160 bool visible = base != 0;
6162 if (intel_crtc->cursor_visible != visible) {
6163 uint32_t cntl = I915_READ(CURCNTR(pipe));
6165 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6166 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6167 cntl |= pipe << 28; /* Connect to correct pipe */
6169 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6170 cntl |= CURSOR_MODE_DISABLE;
6172 I915_WRITE(CURCNTR(pipe), cntl);
6174 intel_crtc->cursor_visible = visible;
6176 /* and commit changes on next vblank */
6177 I915_WRITE(CURBASE(pipe), base);
6180 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6182 struct drm_device *dev = crtc->dev;
6183 struct drm_i915_private *dev_priv = dev->dev_private;
6184 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6185 int pipe = intel_crtc->pipe;
6186 bool visible = base != 0;
6188 if (intel_crtc->cursor_visible != visible) {
6189 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6191 cntl &= ~CURSOR_MODE;
6192 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6194 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6195 cntl |= CURSOR_MODE_DISABLE;
6197 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6199 intel_crtc->cursor_visible = visible;
6201 /* and commit changes on next vblank */
6202 I915_WRITE(CURBASE_IVB(pipe), base);
6205 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6206 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6209 struct drm_device *dev = crtc->dev;
6210 struct drm_i915_private *dev_priv = dev->dev_private;
6211 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6212 int pipe = intel_crtc->pipe;
6213 int x = intel_crtc->cursor_x;
6214 int y = intel_crtc->cursor_y;
6220 if (on && crtc->enabled && crtc->fb) {
6221 base = intel_crtc->cursor_addr;
6222 if (x > (int) crtc->fb->width)
6225 if (y > (int) crtc->fb->height)
6231 if (x + intel_crtc->cursor_width < 0)
6234 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6237 pos |= x << CURSOR_X_SHIFT;
6240 if (y + intel_crtc->cursor_height < 0)
6243 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6246 pos |= y << CURSOR_Y_SHIFT;
6248 visible = base != 0;
6249 if (!visible && !intel_crtc->cursor_visible)
6252 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6253 I915_WRITE(CURPOS_IVB(pipe), pos);
6254 ivb_update_cursor(crtc, base);
6256 I915_WRITE(CURPOS(pipe), pos);
6257 if (IS_845G(dev) || IS_I865G(dev))
6258 i845_update_cursor(crtc, base);
6260 i9xx_update_cursor(crtc, base);
6264 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6265 struct drm_file *file,
6267 uint32_t width, uint32_t height)
6269 struct drm_device *dev = crtc->dev;
6270 struct drm_i915_private *dev_priv = dev->dev_private;
6271 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6272 struct drm_i915_gem_object *obj;
6276 /* if we want to turn off the cursor ignore width and height */
6278 DRM_DEBUG_KMS("cursor off\n");
6281 mutex_lock(&dev->struct_mutex);
6285 /* Currently we only support 64x64 cursors */
6286 if (width != 64 || height != 64) {
6287 DRM_ERROR("we currently only support 64x64 cursors\n");
6291 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6292 if (&obj->base == NULL)
6295 if (obj->base.size < width * height * 4) {
6296 DRM_ERROR("buffer is to small\n");
6301 /* we only need to pin inside GTT if cursor is non-phy */
6302 mutex_lock(&dev->struct_mutex);
6303 if (!dev_priv->info->cursor_needs_physical) {
6304 if (obj->tiling_mode) {
6305 DRM_ERROR("cursor cannot be tiled\n");
6310 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
6312 DRM_ERROR("failed to move cursor bo into the GTT\n");
6316 ret = i915_gem_object_put_fence(obj);
6318 DRM_ERROR("failed to release fence for cursor");
6322 addr = obj->gtt_offset;
6324 int align = IS_I830(dev) ? 16 * 1024 : 256;
6325 ret = i915_gem_attach_phys_object(dev, obj,
6326 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6329 DRM_ERROR("failed to attach phys object\n");
6332 addr = obj->phys_obj->handle->busaddr;
6336 I915_WRITE(CURSIZE, (height << 12) | width);
6339 if (intel_crtc->cursor_bo) {
6340 if (dev_priv->info->cursor_needs_physical) {
6341 if (intel_crtc->cursor_bo != obj)
6342 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6344 i915_gem_object_unpin(intel_crtc->cursor_bo);
6345 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6348 mutex_unlock(&dev->struct_mutex);
6350 intel_crtc->cursor_addr = addr;
6351 intel_crtc->cursor_bo = obj;
6352 intel_crtc->cursor_width = width;
6353 intel_crtc->cursor_height = height;
6355 intel_crtc_update_cursor(crtc, true);
6359 i915_gem_object_unpin(obj);
6361 mutex_unlock(&dev->struct_mutex);
6363 drm_gem_object_unreference_unlocked(&obj->base);
6367 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6369 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6371 intel_crtc->cursor_x = x;
6372 intel_crtc->cursor_y = y;
6374 intel_crtc_update_cursor(crtc, true);
6379 /** Sets the color ramps on behalf of RandR */
6380 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6381 u16 blue, int regno)
6383 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6385 intel_crtc->lut_r[regno] = red >> 8;
6386 intel_crtc->lut_g[regno] = green >> 8;
6387 intel_crtc->lut_b[regno] = blue >> 8;
6390 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6391 u16 *blue, int regno)
6393 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6395 *red = intel_crtc->lut_r[regno] << 8;
6396 *green = intel_crtc->lut_g[regno] << 8;
6397 *blue = intel_crtc->lut_b[regno] << 8;
6400 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6401 u16 *blue, uint32_t start, uint32_t size)
6403 int end = (start + size > 256) ? 256 : start + size, i;
6404 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6406 for (i = start; i < end; i++) {
6407 intel_crtc->lut_r[i] = red[i] >> 8;
6408 intel_crtc->lut_g[i] = green[i] >> 8;
6409 intel_crtc->lut_b[i] = blue[i] >> 8;
6412 intel_crtc_load_lut(crtc);
6416 * Get a pipe with a simple mode set on it for doing load-based monitor
6419 * It will be up to the load-detect code to adjust the pipe as appropriate for
6420 * its requirements. The pipe will be connected to no other encoders.
6422 * Currently this code will only succeed if there is a pipe with no encoders
6423 * configured for it. In the future, it could choose to temporarily disable
6424 * some outputs to free up a pipe for its use.
6426 * \return crtc, or NULL if no pipes are available.
6429 /* VESA 640x480x72Hz mode to set on the pipe */
6430 static struct drm_display_mode load_detect_mode = {
6431 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6432 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6435 static struct drm_framebuffer *
6436 intel_framebuffer_create(struct drm_device *dev,
6437 struct drm_mode_fb_cmd2 *mode_cmd,
6438 struct drm_i915_gem_object *obj)
6440 struct intel_framebuffer *intel_fb;
6443 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6445 drm_gem_object_unreference_unlocked(&obj->base);
6446 return ERR_PTR(-ENOMEM);
6449 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6451 drm_gem_object_unreference_unlocked(&obj->base);
6453 return ERR_PTR(ret);
6456 return &intel_fb->base;
6460 intel_framebuffer_pitch_for_width(int width, int bpp)
6462 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6463 return ALIGN(pitch, 64);
6467 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6469 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6470 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6473 static struct drm_framebuffer *
6474 intel_framebuffer_create_for_mode(struct drm_device *dev,
6475 struct drm_display_mode *mode,
6478 struct drm_i915_gem_object *obj;
6479 struct drm_mode_fb_cmd2 mode_cmd;
6481 obj = i915_gem_alloc_object(dev,
6482 intel_framebuffer_size_for_mode(mode, bpp));
6484 return ERR_PTR(-ENOMEM);
6486 mode_cmd.width = mode->hdisplay;
6487 mode_cmd.height = mode->vdisplay;
6488 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6490 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6492 return intel_framebuffer_create(dev, &mode_cmd, obj);
6495 static struct drm_framebuffer *
6496 mode_fits_in_fbdev(struct drm_device *dev,
6497 struct drm_display_mode *mode)
6499 struct drm_i915_private *dev_priv = dev->dev_private;
6500 struct drm_i915_gem_object *obj;
6501 struct drm_framebuffer *fb;
6503 if (dev_priv->fbdev == NULL)
6506 obj = dev_priv->fbdev->ifb.obj;
6510 fb = &dev_priv->fbdev->ifb.base;
6511 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6512 fb->bits_per_pixel))
6515 if (obj->base.size < mode->vdisplay * fb->pitches[0])
6521 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6522 struct drm_display_mode *mode,
6523 struct intel_load_detect_pipe *old)
6525 struct intel_crtc *intel_crtc;
6526 struct intel_encoder *intel_encoder =
6527 intel_attached_encoder(connector);
6528 struct drm_crtc *possible_crtc;
6529 struct drm_encoder *encoder = &intel_encoder->base;
6530 struct drm_crtc *crtc = NULL;
6531 struct drm_device *dev = encoder->dev;
6532 struct drm_framebuffer *fb;
6535 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6536 connector->base.id, drm_get_connector_name(connector),
6537 encoder->base.id, drm_get_encoder_name(encoder));
6540 * Algorithm gets a little messy:
6542 * - if the connector already has an assigned crtc, use it (but make
6543 * sure it's on first)
6545 * - try to find the first unused crtc that can drive this connector,
6546 * and use that if we find one
6549 /* See if we already have a CRTC for this connector */
6550 if (encoder->crtc) {
6551 crtc = encoder->crtc;
6553 old->dpms_mode = connector->dpms;
6554 old->load_detect_temp = false;
6556 /* Make sure the crtc and connector are running */
6557 if (connector->dpms != DRM_MODE_DPMS_ON)
6558 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6563 /* Find an unused one (if possible) */
6564 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6566 if (!(encoder->possible_crtcs & (1 << i)))
6568 if (!possible_crtc->enabled) {
6569 crtc = possible_crtc;
6575 * If we didn't find an unused CRTC, don't use any.
6578 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6582 intel_encoder->new_crtc = to_intel_crtc(crtc);
6583 to_intel_connector(connector)->new_encoder = intel_encoder;
6585 intel_crtc = to_intel_crtc(crtc);
6586 old->dpms_mode = connector->dpms;
6587 old->load_detect_temp = true;
6588 old->release_fb = NULL;
6591 mode = &load_detect_mode;
6593 /* We need a framebuffer large enough to accommodate all accesses
6594 * that the plane may generate whilst we perform load detection.
6595 * We can not rely on the fbcon either being present (we get called
6596 * during its initialisation to detect all boot displays, or it may
6597 * not even exist) or that it is large enough to satisfy the
6600 fb = mode_fits_in_fbdev(dev, mode);
6602 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6603 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6604 old->release_fb = fb;
6606 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6608 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6612 if (!intel_set_mode(crtc, mode, 0, 0, fb)) {
6613 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6614 if (old->release_fb)
6615 old->release_fb->funcs->destroy(old->release_fb);
6619 /* let the connector get through one full cycle before testing */
6620 intel_wait_for_vblank(dev, intel_crtc->pipe);
6624 connector->encoder = NULL;
6625 encoder->crtc = NULL;
6629 void intel_release_load_detect_pipe(struct drm_connector *connector,
6630 struct intel_load_detect_pipe *old)
6632 struct intel_encoder *intel_encoder =
6633 intel_attached_encoder(connector);
6634 struct drm_encoder *encoder = &intel_encoder->base;
6636 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6637 connector->base.id, drm_get_connector_name(connector),
6638 encoder->base.id, drm_get_encoder_name(encoder));
6640 if (old->load_detect_temp) {
6641 struct drm_crtc *crtc = encoder->crtc;
6643 to_intel_connector(connector)->new_encoder = NULL;
6644 intel_encoder->new_crtc = NULL;
6645 intel_set_mode(crtc, NULL, 0, 0, NULL);
6647 if (old->release_fb)
6648 old->release_fb->funcs->destroy(old->release_fb);
6653 /* Switch crtc and encoder back off if necessary */
6654 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6655 connector->funcs->dpms(connector, old->dpms_mode);
6658 /* Returns the clock of the currently programmed mode of the given pipe. */
6659 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6661 struct drm_i915_private *dev_priv = dev->dev_private;
6662 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6663 int pipe = intel_crtc->pipe;
6664 u32 dpll = I915_READ(DPLL(pipe));
6666 intel_clock_t clock;
6668 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6669 fp = I915_READ(FP0(pipe));
6671 fp = I915_READ(FP1(pipe));
6673 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6674 if (IS_PINEVIEW(dev)) {
6675 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6676 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6678 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6679 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6682 if (!IS_GEN2(dev)) {
6683 if (IS_PINEVIEW(dev))
6684 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6685 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6687 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6688 DPLL_FPA01_P1_POST_DIV_SHIFT);
6690 switch (dpll & DPLL_MODE_MASK) {
6691 case DPLLB_MODE_DAC_SERIAL:
6692 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6695 case DPLLB_MODE_LVDS:
6696 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6700 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6701 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6705 /* XXX: Handle the 100Mhz refclk */
6706 intel_clock(dev, 96000, &clock);
6708 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6711 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6712 DPLL_FPA01_P1_POST_DIV_SHIFT);
6715 if ((dpll & PLL_REF_INPUT_MASK) ==
6716 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6717 /* XXX: might not be 66MHz */
6718 intel_clock(dev, 66000, &clock);
6720 intel_clock(dev, 48000, &clock);
6722 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6725 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6726 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6728 if (dpll & PLL_P2_DIVIDE_BY_4)
6733 intel_clock(dev, 48000, &clock);
6737 /* XXX: It would be nice to validate the clocks, but we can't reuse
6738 * i830PllIsValid() because it relies on the xf86_config connector
6739 * configuration being accurate, which it isn't necessarily.
6745 /** Returns the currently programmed mode of the given pipe. */
6746 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6747 struct drm_crtc *crtc)
6749 struct drm_i915_private *dev_priv = dev->dev_private;
6750 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6751 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
6752 struct drm_display_mode *mode;
6753 int htot = I915_READ(HTOTAL(cpu_transcoder));
6754 int hsync = I915_READ(HSYNC(cpu_transcoder));
6755 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6756 int vsync = I915_READ(VSYNC(cpu_transcoder));
6758 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6762 mode->clock = intel_crtc_clock_get(dev, crtc);
6763 mode->hdisplay = (htot & 0xffff) + 1;
6764 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6765 mode->hsync_start = (hsync & 0xffff) + 1;
6766 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6767 mode->vdisplay = (vtot & 0xffff) + 1;
6768 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6769 mode->vsync_start = (vsync & 0xffff) + 1;
6770 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6772 drm_mode_set_name(mode);
6777 static void intel_increase_pllclock(struct drm_crtc *crtc)
6779 struct drm_device *dev = crtc->dev;
6780 drm_i915_private_t *dev_priv = dev->dev_private;
6781 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6782 int pipe = intel_crtc->pipe;
6783 int dpll_reg = DPLL(pipe);
6786 if (HAS_PCH_SPLIT(dev))
6789 if (!dev_priv->lvds_downclock_avail)
6792 dpll = I915_READ(dpll_reg);
6793 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6794 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6796 assert_panel_unlocked(dev_priv, pipe);
6798 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6799 I915_WRITE(dpll_reg, dpll);
6800 intel_wait_for_vblank(dev, pipe);
6802 dpll = I915_READ(dpll_reg);
6803 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6804 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6808 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6810 struct drm_device *dev = crtc->dev;
6811 drm_i915_private_t *dev_priv = dev->dev_private;
6812 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6814 if (HAS_PCH_SPLIT(dev))
6817 if (!dev_priv->lvds_downclock_avail)
6821 * Since this is called by a timer, we should never get here in
6824 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6825 int pipe = intel_crtc->pipe;
6826 int dpll_reg = DPLL(pipe);
6829 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6831 assert_panel_unlocked(dev_priv, pipe);
6833 dpll = I915_READ(dpll_reg);
6834 dpll |= DISPLAY_RATE_SELECT_FPA1;
6835 I915_WRITE(dpll_reg, dpll);
6836 intel_wait_for_vblank(dev, pipe);
6837 dpll = I915_READ(dpll_reg);
6838 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6839 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6844 void intel_mark_busy(struct drm_device *dev)
6846 i915_update_gfx_val(dev->dev_private);
6849 void intel_mark_idle(struct drm_device *dev)
6853 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6855 struct drm_device *dev = obj->base.dev;
6856 struct drm_crtc *crtc;
6858 if (!i915_powersave)
6861 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6865 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6866 intel_increase_pllclock(crtc);
6870 void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
6872 struct drm_device *dev = obj->base.dev;
6873 struct drm_crtc *crtc;
6875 if (!i915_powersave)
6878 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6882 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6883 intel_decrease_pllclock(crtc);
6887 static void intel_crtc_destroy(struct drm_crtc *crtc)
6889 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6890 struct drm_device *dev = crtc->dev;
6891 struct intel_unpin_work *work;
6892 unsigned long flags;
6894 spin_lock_irqsave(&dev->event_lock, flags);
6895 work = intel_crtc->unpin_work;
6896 intel_crtc->unpin_work = NULL;
6897 spin_unlock_irqrestore(&dev->event_lock, flags);
6900 cancel_work_sync(&work->work);
6904 drm_crtc_cleanup(crtc);
6909 static void intel_unpin_work_fn(struct work_struct *__work)
6911 struct intel_unpin_work *work =
6912 container_of(__work, struct intel_unpin_work, work);
6914 mutex_lock(&work->dev->struct_mutex);
6915 intel_unpin_fb_obj(work->old_fb_obj);
6916 drm_gem_object_unreference(&work->pending_flip_obj->base);
6917 drm_gem_object_unreference(&work->old_fb_obj->base);
6919 intel_update_fbc(work->dev);
6920 mutex_unlock(&work->dev->struct_mutex);
6924 static void do_intel_finish_page_flip(struct drm_device *dev,
6925 struct drm_crtc *crtc)
6927 drm_i915_private_t *dev_priv = dev->dev_private;
6928 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6929 struct intel_unpin_work *work;
6930 struct drm_i915_gem_object *obj;
6931 struct drm_pending_vblank_event *e;
6932 struct timeval tvbl;
6933 unsigned long flags;
6935 /* Ignore early vblank irqs */
6936 if (intel_crtc == NULL)
6939 spin_lock_irqsave(&dev->event_lock, flags);
6940 work = intel_crtc->unpin_work;
6941 if (work == NULL || !work->pending) {
6942 spin_unlock_irqrestore(&dev->event_lock, flags);
6946 intel_crtc->unpin_work = NULL;
6950 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
6952 e->event.tv_sec = tvbl.tv_sec;
6953 e->event.tv_usec = tvbl.tv_usec;
6955 list_add_tail(&e->base.link,
6956 &e->base.file_priv->event_list);
6957 wake_up_interruptible(&e->base.file_priv->event_wait);
6960 drm_vblank_put(dev, intel_crtc->pipe);
6962 spin_unlock_irqrestore(&dev->event_lock, flags);
6964 obj = work->old_fb_obj;
6966 atomic_clear_mask(1 << intel_crtc->plane,
6967 &obj->pending_flip.counter);
6969 wake_up(&dev_priv->pending_flip_queue);
6970 schedule_work(&work->work);
6972 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6975 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6977 drm_i915_private_t *dev_priv = dev->dev_private;
6978 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6980 do_intel_finish_page_flip(dev, crtc);
6983 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6985 drm_i915_private_t *dev_priv = dev->dev_private;
6986 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6988 do_intel_finish_page_flip(dev, crtc);
6991 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6993 drm_i915_private_t *dev_priv = dev->dev_private;
6994 struct intel_crtc *intel_crtc =
6995 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6996 unsigned long flags;
6998 spin_lock_irqsave(&dev->event_lock, flags);
6999 if (intel_crtc->unpin_work) {
7000 if ((++intel_crtc->unpin_work->pending) > 1)
7001 DRM_ERROR("Prepared flip multiple times\n");
7003 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
7005 spin_unlock_irqrestore(&dev->event_lock, flags);
7008 static int intel_gen2_queue_flip(struct drm_device *dev,
7009 struct drm_crtc *crtc,
7010 struct drm_framebuffer *fb,
7011 struct drm_i915_gem_object *obj)
7013 struct drm_i915_private *dev_priv = dev->dev_private;
7014 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7016 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7019 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7023 ret = intel_ring_begin(ring, 6);
7027 /* Can't queue multiple flips, so wait for the previous
7028 * one to finish before executing the next.
7030 if (intel_crtc->plane)
7031 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7033 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7034 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7035 intel_ring_emit(ring, MI_NOOP);
7036 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7037 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7038 intel_ring_emit(ring, fb->pitches[0]);
7039 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7040 intel_ring_emit(ring, 0); /* aux display base address, unused */
7041 intel_ring_advance(ring);
7045 intel_unpin_fb_obj(obj);
7050 static int intel_gen3_queue_flip(struct drm_device *dev,
7051 struct drm_crtc *crtc,
7052 struct drm_framebuffer *fb,
7053 struct drm_i915_gem_object *obj)
7055 struct drm_i915_private *dev_priv = dev->dev_private;
7056 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7058 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7061 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7065 ret = intel_ring_begin(ring, 6);
7069 if (intel_crtc->plane)
7070 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7072 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7073 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7074 intel_ring_emit(ring, MI_NOOP);
7075 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7076 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7077 intel_ring_emit(ring, fb->pitches[0]);
7078 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7079 intel_ring_emit(ring, MI_NOOP);
7081 intel_ring_advance(ring);
7085 intel_unpin_fb_obj(obj);
7090 static int intel_gen4_queue_flip(struct drm_device *dev,
7091 struct drm_crtc *crtc,
7092 struct drm_framebuffer *fb,
7093 struct drm_i915_gem_object *obj)
7095 struct drm_i915_private *dev_priv = dev->dev_private;
7096 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7097 uint32_t pf, pipesrc;
7098 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7101 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7105 ret = intel_ring_begin(ring, 4);
7109 /* i965+ uses the linear or tiled offsets from the
7110 * Display Registers (which do not change across a page-flip)
7111 * so we need only reprogram the base address.
7113 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7114 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7115 intel_ring_emit(ring, fb->pitches[0]);
7116 intel_ring_emit(ring,
7117 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7120 /* XXX Enabling the panel-fitter across page-flip is so far
7121 * untested on non-native modes, so ignore it for now.
7122 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7125 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7126 intel_ring_emit(ring, pf | pipesrc);
7127 intel_ring_advance(ring);
7131 intel_unpin_fb_obj(obj);
7136 static int intel_gen6_queue_flip(struct drm_device *dev,
7137 struct drm_crtc *crtc,
7138 struct drm_framebuffer *fb,
7139 struct drm_i915_gem_object *obj)
7141 struct drm_i915_private *dev_priv = dev->dev_private;
7142 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7143 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7144 uint32_t pf, pipesrc;
7147 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7151 ret = intel_ring_begin(ring, 4);
7155 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7156 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7157 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7158 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7160 /* Contrary to the suggestions in the documentation,
7161 * "Enable Panel Fitter" does not seem to be required when page
7162 * flipping with a non-native mode, and worse causes a normal
7164 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7167 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7168 intel_ring_emit(ring, pf | pipesrc);
7169 intel_ring_advance(ring);
7173 intel_unpin_fb_obj(obj);
7179 * On gen7 we currently use the blit ring because (in early silicon at least)
7180 * the render ring doesn't give us interrpts for page flip completion, which
7181 * means clients will hang after the first flip is queued. Fortunately the
7182 * blit ring generates interrupts properly, so use it instead.
7184 static int intel_gen7_queue_flip(struct drm_device *dev,
7185 struct drm_crtc *crtc,
7186 struct drm_framebuffer *fb,
7187 struct drm_i915_gem_object *obj)
7189 struct drm_i915_private *dev_priv = dev->dev_private;
7190 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7191 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7192 uint32_t plane_bit = 0;
7195 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7199 switch(intel_crtc->plane) {
7201 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7204 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7207 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7210 WARN_ONCE(1, "unknown plane in flip command\n");
7215 ret = intel_ring_begin(ring, 4);
7219 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7220 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7221 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7222 intel_ring_emit(ring, (MI_NOOP));
7223 intel_ring_advance(ring);
7227 intel_unpin_fb_obj(obj);
7232 static int intel_default_queue_flip(struct drm_device *dev,
7233 struct drm_crtc *crtc,
7234 struct drm_framebuffer *fb,
7235 struct drm_i915_gem_object *obj)
7240 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7241 struct drm_framebuffer *fb,
7242 struct drm_pending_vblank_event *event)
7244 struct drm_device *dev = crtc->dev;
7245 struct drm_i915_private *dev_priv = dev->dev_private;
7246 struct intel_framebuffer *intel_fb;
7247 struct drm_i915_gem_object *obj;
7248 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7249 struct intel_unpin_work *work;
7250 unsigned long flags;
7253 /* Can't change pixel format via MI display flips. */
7254 if (fb->pixel_format != crtc->fb->pixel_format)
7258 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7259 * Note that pitch changes could also affect these register.
7261 if (INTEL_INFO(dev)->gen > 3 &&
7262 (fb->offsets[0] != crtc->fb->offsets[0] ||
7263 fb->pitches[0] != crtc->fb->pitches[0]))
7266 work = kzalloc(sizeof *work, GFP_KERNEL);
7270 work->event = event;
7271 work->dev = crtc->dev;
7272 intel_fb = to_intel_framebuffer(crtc->fb);
7273 work->old_fb_obj = intel_fb->obj;
7274 INIT_WORK(&work->work, intel_unpin_work_fn);
7276 ret = drm_vblank_get(dev, intel_crtc->pipe);
7280 /* We borrow the event spin lock for protecting unpin_work */
7281 spin_lock_irqsave(&dev->event_lock, flags);
7282 if (intel_crtc->unpin_work) {
7283 spin_unlock_irqrestore(&dev->event_lock, flags);
7285 drm_vblank_put(dev, intel_crtc->pipe);
7287 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7290 intel_crtc->unpin_work = work;
7291 spin_unlock_irqrestore(&dev->event_lock, flags);
7293 intel_fb = to_intel_framebuffer(fb);
7294 obj = intel_fb->obj;
7296 ret = i915_mutex_lock_interruptible(dev);
7300 /* Reference the objects for the scheduled work. */
7301 drm_gem_object_reference(&work->old_fb_obj->base);
7302 drm_gem_object_reference(&obj->base);
7306 work->pending_flip_obj = obj;
7308 work->enable_stall_check = true;
7310 /* Block clients from rendering to the new back buffer until
7311 * the flip occurs and the object is no longer visible.
7313 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7315 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7317 goto cleanup_pending;
7319 intel_disable_fbc(dev);
7320 intel_mark_fb_busy(obj);
7321 mutex_unlock(&dev->struct_mutex);
7323 trace_i915_flip_request(intel_crtc->plane, obj);
7328 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7329 drm_gem_object_unreference(&work->old_fb_obj->base);
7330 drm_gem_object_unreference(&obj->base);
7331 mutex_unlock(&dev->struct_mutex);
7334 spin_lock_irqsave(&dev->event_lock, flags);
7335 intel_crtc->unpin_work = NULL;
7336 spin_unlock_irqrestore(&dev->event_lock, flags);
7338 drm_vblank_put(dev, intel_crtc->pipe);
7345 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7346 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7347 .load_lut = intel_crtc_load_lut,
7348 .disable = intel_crtc_noop,
7351 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
7353 struct intel_encoder *other_encoder;
7354 struct drm_crtc *crtc = &encoder->new_crtc->base;
7359 list_for_each_entry(other_encoder,
7360 &crtc->dev->mode_config.encoder_list,
7363 if (&other_encoder->new_crtc->base != crtc ||
7364 encoder == other_encoder)
7373 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7374 struct drm_crtc *crtc)
7376 struct drm_device *dev;
7377 struct drm_crtc *tmp;
7380 WARN(!crtc, "checking null crtc?\n");
7384 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7390 if (encoder->possible_crtcs & crtc_mask)
7396 * intel_modeset_update_staged_output_state
7398 * Updates the staged output configuration state, e.g. after we've read out the
7401 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7403 struct intel_encoder *encoder;
7404 struct intel_connector *connector;
7406 list_for_each_entry(connector, &dev->mode_config.connector_list,
7408 connector->new_encoder =
7409 to_intel_encoder(connector->base.encoder);
7412 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7415 to_intel_crtc(encoder->base.crtc);
7420 * intel_modeset_commit_output_state
7422 * This function copies the stage display pipe configuration to the real one.
7424 static void intel_modeset_commit_output_state(struct drm_device *dev)
7426 struct intel_encoder *encoder;
7427 struct intel_connector *connector;
7429 list_for_each_entry(connector, &dev->mode_config.connector_list,
7431 connector->base.encoder = &connector->new_encoder->base;
7434 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7436 encoder->base.crtc = &encoder->new_crtc->base;
7440 static struct drm_display_mode *
7441 intel_modeset_adjusted_mode(struct drm_crtc *crtc,
7442 struct drm_display_mode *mode)
7444 struct drm_device *dev = crtc->dev;
7445 struct drm_display_mode *adjusted_mode;
7446 struct drm_encoder_helper_funcs *encoder_funcs;
7447 struct intel_encoder *encoder;
7449 adjusted_mode = drm_mode_duplicate(dev, mode);
7451 return ERR_PTR(-ENOMEM);
7453 /* Pass our mode to the connectors and the CRTC to give them a chance to
7454 * adjust it according to limitations or connector properties, and also
7455 * a chance to reject the mode entirely.
7457 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7460 if (&encoder->new_crtc->base != crtc)
7462 encoder_funcs = encoder->base.helper_private;
7463 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
7465 DRM_DEBUG_KMS("Encoder fixup failed\n");
7470 if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
7471 DRM_DEBUG_KMS("CRTC fixup failed\n");
7474 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7476 return adjusted_mode;
7478 drm_mode_destroy(dev, adjusted_mode);
7479 return ERR_PTR(-EINVAL);
7482 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7483 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7485 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7486 unsigned *prepare_pipes, unsigned *disable_pipes)
7488 struct intel_crtc *intel_crtc;
7489 struct drm_device *dev = crtc->dev;
7490 struct intel_encoder *encoder;
7491 struct intel_connector *connector;
7492 struct drm_crtc *tmp_crtc;
7494 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7496 /* Check which crtcs have changed outputs connected to them, these need
7497 * to be part of the prepare_pipes mask. We don't (yet) support global
7498 * modeset across multiple crtcs, so modeset_pipes will only have one
7499 * bit set at most. */
7500 list_for_each_entry(connector, &dev->mode_config.connector_list,
7502 if (connector->base.encoder == &connector->new_encoder->base)
7505 if (connector->base.encoder) {
7506 tmp_crtc = connector->base.encoder->crtc;
7508 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7511 if (connector->new_encoder)
7513 1 << connector->new_encoder->new_crtc->pipe;
7516 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7518 if (encoder->base.crtc == &encoder->new_crtc->base)
7521 if (encoder->base.crtc) {
7522 tmp_crtc = encoder->base.crtc;
7524 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7527 if (encoder->new_crtc)
7528 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7531 /* Check for any pipes that will be fully disabled ... */
7532 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7536 /* Don't try to disable disabled crtcs. */
7537 if (!intel_crtc->base.enabled)
7540 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7542 if (encoder->new_crtc == intel_crtc)
7547 *disable_pipes |= 1 << intel_crtc->pipe;
7551 /* set_mode is also used to update properties on life display pipes. */
7552 intel_crtc = to_intel_crtc(crtc);
7554 *prepare_pipes |= 1 << intel_crtc->pipe;
7556 /* We only support modeset on one single crtc, hence we need to do that
7557 * only for the passed in crtc iff we change anything else than just
7560 * This is actually not true, to be fully compatible with the old crtc
7561 * helper we automatically disable _any_ output (i.e. doesn't need to be
7562 * connected to the crtc we're modesetting on) if it's disconnected.
7563 * Which is a rather nutty api (since changed the output configuration
7564 * without userspace's explicit request can lead to confusion), but
7565 * alas. Hence we currently need to modeset on all pipes we prepare. */
7567 *modeset_pipes = *prepare_pipes;
7569 /* ... and mask these out. */
7570 *modeset_pipes &= ~(*disable_pipes);
7571 *prepare_pipes &= ~(*disable_pipes);
7574 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7576 struct drm_encoder *encoder;
7577 struct drm_device *dev = crtc->dev;
7579 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7580 if (encoder->crtc == crtc)
7587 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7589 struct intel_encoder *intel_encoder;
7590 struct intel_crtc *intel_crtc;
7591 struct drm_connector *connector;
7593 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7595 if (!intel_encoder->base.crtc)
7598 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7600 if (prepare_pipes & (1 << intel_crtc->pipe))
7601 intel_encoder->connectors_active = false;
7604 intel_modeset_commit_output_state(dev);
7606 /* Update computed state. */
7607 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7609 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7612 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7613 if (!connector->encoder || !connector->encoder->crtc)
7616 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7618 if (prepare_pipes & (1 << intel_crtc->pipe)) {
7619 struct drm_property *dpms_property =
7620 dev->mode_config.dpms_property;
7622 connector->dpms = DRM_MODE_DPMS_ON;
7623 drm_connector_property_set_value(connector,
7627 intel_encoder = to_intel_encoder(connector->encoder);
7628 intel_encoder->connectors_active = true;
7634 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7635 list_for_each_entry((intel_crtc), \
7636 &(dev)->mode_config.crtc_list, \
7638 if (mask & (1 <<(intel_crtc)->pipe)) \
7641 intel_modeset_check_state(struct drm_device *dev)
7643 struct intel_crtc *crtc;
7644 struct intel_encoder *encoder;
7645 struct intel_connector *connector;
7647 list_for_each_entry(connector, &dev->mode_config.connector_list,
7649 /* This also checks the encoder/connector hw state with the
7650 * ->get_hw_state callbacks. */
7651 intel_connector_check_state(connector);
7653 WARN(&connector->new_encoder->base != connector->base.encoder,
7654 "connector's staged encoder doesn't match current encoder\n");
7657 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7659 bool enabled = false;
7660 bool active = false;
7661 enum pipe pipe, tracked_pipe;
7663 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7664 encoder->base.base.id,
7665 drm_get_encoder_name(&encoder->base));
7667 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7668 "encoder's stage crtc doesn't match current crtc\n");
7669 WARN(encoder->connectors_active && !encoder->base.crtc,
7670 "encoder's active_connectors set, but no crtc\n");
7672 list_for_each_entry(connector, &dev->mode_config.connector_list,
7674 if (connector->base.encoder != &encoder->base)
7677 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7680 WARN(!!encoder->base.crtc != enabled,
7681 "encoder's enabled state mismatch "
7682 "(expected %i, found %i)\n",
7683 !!encoder->base.crtc, enabled);
7684 WARN(active && !encoder->base.crtc,
7685 "active encoder with no crtc\n");
7687 WARN(encoder->connectors_active != active,
7688 "encoder's computed active state doesn't match tracked active state "
7689 "(expected %i, found %i)\n", active, encoder->connectors_active);
7691 active = encoder->get_hw_state(encoder, &pipe);
7692 WARN(active != encoder->connectors_active,
7693 "encoder's hw state doesn't match sw tracking "
7694 "(expected %i, found %i)\n",
7695 encoder->connectors_active, active);
7697 if (!encoder->base.crtc)
7700 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7701 WARN(active && pipe != tracked_pipe,
7702 "active encoder's pipe doesn't match"
7703 "(expected %i, found %i)\n",
7704 tracked_pipe, pipe);
7708 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7710 bool enabled = false;
7711 bool active = false;
7713 DRM_DEBUG_KMS("[CRTC:%d]\n",
7714 crtc->base.base.id);
7716 WARN(crtc->active && !crtc->base.enabled,
7717 "active crtc, but not enabled in sw tracking\n");
7719 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7721 if (encoder->base.crtc != &crtc->base)
7724 if (encoder->connectors_active)
7727 WARN(active != crtc->active,
7728 "crtc's computed active state doesn't match tracked active state "
7729 "(expected %i, found %i)\n", active, crtc->active);
7730 WARN(enabled != crtc->base.enabled,
7731 "crtc's computed enabled state doesn't match tracked enabled state "
7732 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7734 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7738 bool intel_set_mode(struct drm_crtc *crtc,
7739 struct drm_display_mode *mode,
7740 int x, int y, struct drm_framebuffer *fb)
7742 struct drm_device *dev = crtc->dev;
7743 drm_i915_private_t *dev_priv = dev->dev_private;
7744 struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
7745 struct intel_crtc *intel_crtc;
7746 unsigned disable_pipes, prepare_pipes, modeset_pipes;
7749 intel_modeset_affected_pipes(crtc, &modeset_pipes,
7750 &prepare_pipes, &disable_pipes);
7752 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7753 modeset_pipes, prepare_pipes, disable_pipes);
7755 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7756 intel_crtc_disable(&intel_crtc->base);
7758 saved_hwmode = crtc->hwmode;
7759 saved_mode = crtc->mode;
7761 /* Hack: Because we don't (yet) support global modeset on multiple
7762 * crtcs, we don't keep track of the new mode for more than one crtc.
7763 * Hence simply check whether any bit is set in modeset_pipes in all the
7764 * pieces of code that are not yet converted to deal with mutliple crtcs
7765 * changing their mode at the same time. */
7766 adjusted_mode = NULL;
7767 if (modeset_pipes) {
7768 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7769 if (IS_ERR(adjusted_mode)) {
7774 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7775 if (intel_crtc->base.enabled)
7776 dev_priv->display.crtc_disable(&intel_crtc->base);
7779 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7780 * to set it here already despite that we pass it down the callchain.
7785 /* Only after disabling all output pipelines that will be changed can we
7786 * update the the output configuration. */
7787 intel_modeset_update_state(dev, prepare_pipes);
7789 if (dev_priv->display.modeset_global_resources)
7790 dev_priv->display.modeset_global_resources(dev);
7792 /* Set up the DPLL and any encoders state that needs to adjust or depend
7795 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7796 ret = !intel_crtc_mode_set(&intel_crtc->base,
7797 mode, adjusted_mode,
7803 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7804 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7805 dev_priv->display.crtc_enable(&intel_crtc->base);
7807 if (modeset_pipes) {
7808 /* Store real post-adjustment hardware mode. */
7809 crtc->hwmode = *adjusted_mode;
7811 /* Calculate and store various constants which
7812 * are later needed by vblank and swap-completion
7813 * timestamping. They are derived from true hwmode.
7815 drm_calc_timestamping_constants(crtc);
7818 /* FIXME: add subpixel order */
7820 drm_mode_destroy(dev, adjusted_mode);
7821 if (!ret && crtc->enabled) {
7822 crtc->hwmode = saved_hwmode;
7823 crtc->mode = saved_mode;
7825 intel_modeset_check_state(dev);
7831 #undef for_each_intel_crtc_masked
7833 static void intel_set_config_free(struct intel_set_config *config)
7838 kfree(config->save_connector_encoders);
7839 kfree(config->save_encoder_crtcs);
7843 static int intel_set_config_save_state(struct drm_device *dev,
7844 struct intel_set_config *config)
7846 struct drm_encoder *encoder;
7847 struct drm_connector *connector;
7850 config->save_encoder_crtcs =
7851 kcalloc(dev->mode_config.num_encoder,
7852 sizeof(struct drm_crtc *), GFP_KERNEL);
7853 if (!config->save_encoder_crtcs)
7856 config->save_connector_encoders =
7857 kcalloc(dev->mode_config.num_connector,
7858 sizeof(struct drm_encoder *), GFP_KERNEL);
7859 if (!config->save_connector_encoders)
7862 /* Copy data. Note that driver private data is not affected.
7863 * Should anything bad happen only the expected state is
7864 * restored, not the drivers personal bookkeeping.
7867 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
7868 config->save_encoder_crtcs[count++] = encoder->crtc;
7872 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7873 config->save_connector_encoders[count++] = connector->encoder;
7879 static void intel_set_config_restore_state(struct drm_device *dev,
7880 struct intel_set_config *config)
7882 struct intel_encoder *encoder;
7883 struct intel_connector *connector;
7887 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7889 to_intel_crtc(config->save_encoder_crtcs[count++]);
7893 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7894 connector->new_encoder =
7895 to_intel_encoder(config->save_connector_encoders[count++]);
7900 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7901 struct intel_set_config *config)
7904 /* We should be able to check here if the fb has the same properties
7905 * and then just flip_or_move it */
7906 if (set->crtc->fb != set->fb) {
7907 /* If we have no fb then treat it as a full mode set */
7908 if (set->crtc->fb == NULL) {
7909 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7910 config->mode_changed = true;
7911 } else if (set->fb == NULL) {
7912 config->mode_changed = true;
7913 } else if (set->fb->depth != set->crtc->fb->depth) {
7914 config->mode_changed = true;
7915 } else if (set->fb->bits_per_pixel !=
7916 set->crtc->fb->bits_per_pixel) {
7917 config->mode_changed = true;
7919 config->fb_changed = true;
7922 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
7923 config->fb_changed = true;
7925 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7926 DRM_DEBUG_KMS("modes are different, full mode set\n");
7927 drm_mode_debug_printmodeline(&set->crtc->mode);
7928 drm_mode_debug_printmodeline(set->mode);
7929 config->mode_changed = true;
7934 intel_modeset_stage_output_state(struct drm_device *dev,
7935 struct drm_mode_set *set,
7936 struct intel_set_config *config)
7938 struct drm_crtc *new_crtc;
7939 struct intel_connector *connector;
7940 struct intel_encoder *encoder;
7943 /* The upper layers ensure that we either disabl a crtc or have a list
7944 * of connectors. For paranoia, double-check this. */
7945 WARN_ON(!set->fb && (set->num_connectors != 0));
7946 WARN_ON(set->fb && (set->num_connectors == 0));
7949 list_for_each_entry(connector, &dev->mode_config.connector_list,
7951 /* Otherwise traverse passed in connector list and get encoders
7953 for (ro = 0; ro < set->num_connectors; ro++) {
7954 if (set->connectors[ro] == &connector->base) {
7955 connector->new_encoder = connector->encoder;
7960 /* If we disable the crtc, disable all its connectors. Also, if
7961 * the connector is on the changing crtc but not on the new
7962 * connector list, disable it. */
7963 if ((!set->fb || ro == set->num_connectors) &&
7964 connector->base.encoder &&
7965 connector->base.encoder->crtc == set->crtc) {
7966 connector->new_encoder = NULL;
7968 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7969 connector->base.base.id,
7970 drm_get_connector_name(&connector->base));
7974 if (&connector->new_encoder->base != connector->base.encoder) {
7975 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
7976 config->mode_changed = true;
7979 /* Disable all disconnected encoders. */
7980 if (connector->base.status == connector_status_disconnected)
7981 connector->new_encoder = NULL;
7983 /* connector->new_encoder is now updated for all connectors. */
7985 /* Update crtc of enabled connectors. */
7987 list_for_each_entry(connector, &dev->mode_config.connector_list,
7989 if (!connector->new_encoder)
7992 new_crtc = connector->new_encoder->base.crtc;
7994 for (ro = 0; ro < set->num_connectors; ro++) {
7995 if (set->connectors[ro] == &connector->base)
7996 new_crtc = set->crtc;
7999 /* Make sure the new CRTC will work with the encoder */
8000 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8004 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8006 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8007 connector->base.base.id,
8008 drm_get_connector_name(&connector->base),
8012 /* Check for any encoders that needs to be disabled. */
8013 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8015 list_for_each_entry(connector,
8016 &dev->mode_config.connector_list,
8018 if (connector->new_encoder == encoder) {
8019 WARN_ON(!connector->new_encoder->new_crtc);
8024 encoder->new_crtc = NULL;
8026 /* Only now check for crtc changes so we don't miss encoders
8027 * that will be disabled. */
8028 if (&encoder->new_crtc->base != encoder->base.crtc) {
8029 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8030 config->mode_changed = true;
8033 /* Now we've also updated encoder->new_crtc for all encoders. */
8038 static int intel_crtc_set_config(struct drm_mode_set *set)
8040 struct drm_device *dev;
8041 struct drm_mode_set save_set;
8042 struct intel_set_config *config;
8047 BUG_ON(!set->crtc->helper_private);
8052 /* The fb helper likes to play gross jokes with ->mode_set_config.
8053 * Unfortunately the crtc helper doesn't do much at all for this case,
8054 * so we have to cope with this madness until the fb helper is fixed up. */
8055 if (set->fb && set->num_connectors == 0)
8059 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8060 set->crtc->base.id, set->fb->base.id,
8061 (int)set->num_connectors, set->x, set->y);
8063 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
8066 dev = set->crtc->dev;
8069 config = kzalloc(sizeof(*config), GFP_KERNEL);
8073 ret = intel_set_config_save_state(dev, config);
8077 save_set.crtc = set->crtc;
8078 save_set.mode = &set->crtc->mode;
8079 save_set.x = set->crtc->x;
8080 save_set.y = set->crtc->y;
8081 save_set.fb = set->crtc->fb;
8083 /* Compute whether we need a full modeset, only an fb base update or no
8084 * change at all. In the future we might also check whether only the
8085 * mode changed, e.g. for LVDS where we only change the panel fitter in
8087 intel_set_config_compute_mode_changes(set, config);
8089 ret = intel_modeset_stage_output_state(dev, set, config);
8093 if (config->mode_changed) {
8095 DRM_DEBUG_KMS("attempting to set mode from"
8097 drm_mode_debug_printmodeline(set->mode);
8100 if (!intel_set_mode(set->crtc, set->mode,
8101 set->x, set->y, set->fb)) {
8102 DRM_ERROR("failed to set mode on [CRTC:%d]\n",
8103 set->crtc->base.id);
8107 } else if (config->fb_changed) {
8108 ret = intel_pipe_set_base(set->crtc,
8109 set->x, set->y, set->fb);
8112 intel_set_config_free(config);
8117 intel_set_config_restore_state(dev, config);
8119 /* Try to restore the config */
8120 if (config->mode_changed &&
8121 !intel_set_mode(save_set.crtc, save_set.mode,
8122 save_set.x, save_set.y, save_set.fb))
8123 DRM_ERROR("failed to restore config after modeset failure\n");
8126 intel_set_config_free(config);
8130 static const struct drm_crtc_funcs intel_crtc_funcs = {
8131 .cursor_set = intel_crtc_cursor_set,
8132 .cursor_move = intel_crtc_cursor_move,
8133 .gamma_set = intel_crtc_gamma_set,
8134 .set_config = intel_crtc_set_config,
8135 .destroy = intel_crtc_destroy,
8136 .page_flip = intel_crtc_page_flip,
8139 static void intel_cpu_pll_init(struct drm_device *dev)
8141 if (IS_HASWELL(dev))
8142 intel_ddi_pll_init(dev);
8145 static void intel_pch_pll_init(struct drm_device *dev)
8147 drm_i915_private_t *dev_priv = dev->dev_private;
8150 if (dev_priv->num_pch_pll == 0) {
8151 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8155 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8156 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8157 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8158 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8162 static void intel_crtc_init(struct drm_device *dev, int pipe)
8164 drm_i915_private_t *dev_priv = dev->dev_private;
8165 struct intel_crtc *intel_crtc;
8168 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8169 if (intel_crtc == NULL)
8172 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8174 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
8175 for (i = 0; i < 256; i++) {
8176 intel_crtc->lut_r[i] = i;
8177 intel_crtc->lut_g[i] = i;
8178 intel_crtc->lut_b[i] = i;
8181 /* Swap pipes & planes for FBC on pre-965 */
8182 intel_crtc->pipe = pipe;
8183 intel_crtc->plane = pipe;
8184 intel_crtc->cpu_transcoder = pipe;
8185 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
8186 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8187 intel_crtc->plane = !pipe;
8190 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8191 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8192 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8193 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8195 intel_crtc->bpp = 24; /* default for pre-Ironlake */
8197 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8200 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
8201 struct drm_file *file)
8203 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
8204 struct drm_mode_object *drmmode_obj;
8205 struct intel_crtc *crtc;
8207 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8210 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8211 DRM_MODE_OBJECT_CRTC);
8214 DRM_ERROR("no such CRTC id\n");
8218 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8219 pipe_from_crtc_id->pipe = crtc->pipe;
8224 static int intel_encoder_clones(struct intel_encoder *encoder)
8226 struct drm_device *dev = encoder->base.dev;
8227 struct intel_encoder *source_encoder;
8231 list_for_each_entry(source_encoder,
8232 &dev->mode_config.encoder_list, base.head) {
8234 if (encoder == source_encoder)
8235 index_mask |= (1 << entry);
8237 /* Intel hw has only one MUX where enocoders could be cloned. */
8238 if (encoder->cloneable && source_encoder->cloneable)
8239 index_mask |= (1 << entry);
8247 static bool has_edp_a(struct drm_device *dev)
8249 struct drm_i915_private *dev_priv = dev->dev_private;
8251 if (!IS_MOBILE(dev))
8254 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8258 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8264 static void intel_setup_outputs(struct drm_device *dev)
8266 struct drm_i915_private *dev_priv = dev->dev_private;
8267 struct intel_encoder *encoder;
8268 bool dpd_is_edp = false;
8271 has_lvds = intel_lvds_init(dev);
8272 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8273 /* disable the panel fitter on everything but LVDS */
8274 I915_WRITE(PFIT_CONTROL, 0);
8277 if (HAS_PCH_SPLIT(dev)) {
8278 dpd_is_edp = intel_dpd_is_edp(dev);
8281 intel_dp_init(dev, DP_A, PORT_A);
8283 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
8284 intel_dp_init(dev, PCH_DP_D, PORT_D);
8287 intel_crt_init(dev);
8289 if (IS_HASWELL(dev)) {
8292 /* Haswell uses DDI functions to detect digital outputs */
8293 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8294 /* DDI A only supports eDP */
8296 intel_ddi_init(dev, PORT_A);
8298 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8300 found = I915_READ(SFUSE_STRAP);
8302 if (found & SFUSE_STRAP_DDIB_DETECTED)
8303 intel_ddi_init(dev, PORT_B);
8304 if (found & SFUSE_STRAP_DDIC_DETECTED)
8305 intel_ddi_init(dev, PORT_C);
8306 if (found & SFUSE_STRAP_DDID_DETECTED)
8307 intel_ddi_init(dev, PORT_D);
8308 } else if (HAS_PCH_SPLIT(dev)) {
8311 if (I915_READ(HDMIB) & PORT_DETECTED) {
8312 /* PCH SDVOB multiplex with HDMIB */
8313 found = intel_sdvo_init(dev, PCH_SDVOB, true);
8315 intel_hdmi_init(dev, HDMIB, PORT_B);
8316 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
8317 intel_dp_init(dev, PCH_DP_B, PORT_B);
8320 if (I915_READ(HDMIC) & PORT_DETECTED)
8321 intel_hdmi_init(dev, HDMIC, PORT_C);
8323 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
8324 intel_hdmi_init(dev, HDMID, PORT_D);
8326 if (I915_READ(PCH_DP_C) & DP_DETECTED)
8327 intel_dp_init(dev, PCH_DP_C, PORT_C);
8329 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
8330 intel_dp_init(dev, PCH_DP_D, PORT_D);
8331 } else if (IS_VALLEYVIEW(dev)) {
8334 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8335 if (I915_READ(DP_C) & DP_DETECTED)
8336 intel_dp_init(dev, DP_C, PORT_C);
8338 if (I915_READ(SDVOB) & PORT_DETECTED) {
8339 /* SDVOB multiplex with HDMIB */
8340 found = intel_sdvo_init(dev, SDVOB, true);
8342 intel_hdmi_init(dev, SDVOB, PORT_B);
8343 if (!found && (I915_READ(DP_B) & DP_DETECTED))
8344 intel_dp_init(dev, DP_B, PORT_B);
8347 if (I915_READ(SDVOC) & PORT_DETECTED)
8348 intel_hdmi_init(dev, SDVOC, PORT_C);
8350 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
8353 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8354 DRM_DEBUG_KMS("probing SDVOB\n");
8355 found = intel_sdvo_init(dev, SDVOB, true);
8356 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8357 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8358 intel_hdmi_init(dev, SDVOB, PORT_B);
8361 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8362 DRM_DEBUG_KMS("probing DP_B\n");
8363 intel_dp_init(dev, DP_B, PORT_B);
8367 /* Before G4X SDVOC doesn't have its own detect register */
8369 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8370 DRM_DEBUG_KMS("probing SDVOC\n");
8371 found = intel_sdvo_init(dev, SDVOC, false);
8374 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
8376 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8377 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8378 intel_hdmi_init(dev, SDVOC, PORT_C);
8380 if (SUPPORTS_INTEGRATED_DP(dev)) {
8381 DRM_DEBUG_KMS("probing DP_C\n");
8382 intel_dp_init(dev, DP_C, PORT_C);
8386 if (SUPPORTS_INTEGRATED_DP(dev) &&
8387 (I915_READ(DP_D) & DP_DETECTED)) {
8388 DRM_DEBUG_KMS("probing DP_D\n");
8389 intel_dp_init(dev, DP_D, PORT_D);
8391 } else if (IS_GEN2(dev))
8392 intel_dvo_init(dev);
8394 if (SUPPORTS_TV(dev))
8397 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8398 encoder->base.possible_crtcs = encoder->crtc_mask;
8399 encoder->base.possible_clones =
8400 intel_encoder_clones(encoder);
8403 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8404 ironlake_init_pch_refclk(dev);
8407 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8409 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8411 drm_framebuffer_cleanup(fb);
8412 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8417 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8418 struct drm_file *file,
8419 unsigned int *handle)
8421 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8422 struct drm_i915_gem_object *obj = intel_fb->obj;
8424 return drm_gem_handle_create(file, &obj->base, handle);
8427 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8428 .destroy = intel_user_framebuffer_destroy,
8429 .create_handle = intel_user_framebuffer_create_handle,
8432 int intel_framebuffer_init(struct drm_device *dev,
8433 struct intel_framebuffer *intel_fb,
8434 struct drm_mode_fb_cmd2 *mode_cmd,
8435 struct drm_i915_gem_object *obj)
8439 if (obj->tiling_mode == I915_TILING_Y)
8442 if (mode_cmd->pitches[0] & 63)
8445 /* FIXME <= Gen4 stride limits are bit unclear */
8446 if (mode_cmd->pitches[0] > 32768)
8449 if (obj->tiling_mode != I915_TILING_NONE &&
8450 mode_cmd->pitches[0] != obj->stride)
8453 /* Reject formats not supported by any plane early. */
8454 switch (mode_cmd->pixel_format) {
8456 case DRM_FORMAT_RGB565:
8457 case DRM_FORMAT_XRGB8888:
8458 case DRM_FORMAT_ARGB8888:
8460 case DRM_FORMAT_XRGB1555:
8461 case DRM_FORMAT_ARGB1555:
8462 if (INTEL_INFO(dev)->gen > 3)
8465 case DRM_FORMAT_XBGR8888:
8466 case DRM_FORMAT_ABGR8888:
8467 case DRM_FORMAT_XRGB2101010:
8468 case DRM_FORMAT_ARGB2101010:
8469 case DRM_FORMAT_XBGR2101010:
8470 case DRM_FORMAT_ABGR2101010:
8471 if (INTEL_INFO(dev)->gen < 4)
8474 case DRM_FORMAT_YUYV:
8475 case DRM_FORMAT_UYVY:
8476 case DRM_FORMAT_YVYU:
8477 case DRM_FORMAT_VYUY:
8478 if (INTEL_INFO(dev)->gen < 6)
8482 DRM_DEBUG_KMS("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
8486 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8487 if (mode_cmd->offsets[0] != 0)
8490 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8492 DRM_ERROR("framebuffer init failed %d\n", ret);
8496 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8497 intel_fb->obj = obj;
8501 static struct drm_framebuffer *
8502 intel_user_framebuffer_create(struct drm_device *dev,
8503 struct drm_file *filp,
8504 struct drm_mode_fb_cmd2 *mode_cmd)
8506 struct drm_i915_gem_object *obj;
8508 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8509 mode_cmd->handles[0]));
8510 if (&obj->base == NULL)
8511 return ERR_PTR(-ENOENT);
8513 return intel_framebuffer_create(dev, mode_cmd, obj);
8516 static const struct drm_mode_config_funcs intel_mode_funcs = {
8517 .fb_create = intel_user_framebuffer_create,
8518 .output_poll_changed = intel_fb_output_poll_changed,
8521 /* Set up chip specific display functions */
8522 static void intel_init_display(struct drm_device *dev)
8524 struct drm_i915_private *dev_priv = dev->dev_private;
8526 /* We always want a DPMS function */
8527 if (IS_HASWELL(dev)) {
8528 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
8529 dev_priv->display.crtc_enable = haswell_crtc_enable;
8530 dev_priv->display.crtc_disable = haswell_crtc_disable;
8531 dev_priv->display.off = haswell_crtc_off;
8532 dev_priv->display.update_plane = ironlake_update_plane;
8533 } else if (HAS_PCH_SPLIT(dev)) {
8534 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8535 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8536 dev_priv->display.crtc_disable = ironlake_crtc_disable;
8537 dev_priv->display.off = ironlake_crtc_off;
8538 dev_priv->display.update_plane = ironlake_update_plane;
8540 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8541 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8542 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8543 dev_priv->display.off = i9xx_crtc_off;
8544 dev_priv->display.update_plane = i9xx_update_plane;
8547 /* Returns the core display clock speed */
8548 if (IS_VALLEYVIEW(dev))
8549 dev_priv->display.get_display_clock_speed =
8550 valleyview_get_display_clock_speed;
8551 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8552 dev_priv->display.get_display_clock_speed =
8553 i945_get_display_clock_speed;
8554 else if (IS_I915G(dev))
8555 dev_priv->display.get_display_clock_speed =
8556 i915_get_display_clock_speed;
8557 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8558 dev_priv->display.get_display_clock_speed =
8559 i9xx_misc_get_display_clock_speed;
8560 else if (IS_I915GM(dev))
8561 dev_priv->display.get_display_clock_speed =
8562 i915gm_get_display_clock_speed;
8563 else if (IS_I865G(dev))
8564 dev_priv->display.get_display_clock_speed =
8565 i865_get_display_clock_speed;
8566 else if (IS_I85X(dev))
8567 dev_priv->display.get_display_clock_speed =
8568 i855_get_display_clock_speed;
8570 dev_priv->display.get_display_clock_speed =
8571 i830_get_display_clock_speed;
8573 if (HAS_PCH_SPLIT(dev)) {
8575 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8576 dev_priv->display.write_eld = ironlake_write_eld;
8577 } else if (IS_GEN6(dev)) {
8578 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8579 dev_priv->display.write_eld = ironlake_write_eld;
8580 } else if (IS_IVYBRIDGE(dev)) {
8581 /* FIXME: detect B0+ stepping and use auto training */
8582 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8583 dev_priv->display.write_eld = ironlake_write_eld;
8584 dev_priv->display.modeset_global_resources =
8585 ivb_modeset_global_resources;
8586 } else if (IS_HASWELL(dev)) {
8587 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
8588 dev_priv->display.write_eld = haswell_write_eld;
8590 dev_priv->display.update_wm = NULL;
8591 } else if (IS_G4X(dev)) {
8592 dev_priv->display.write_eld = g4x_write_eld;
8595 /* Default just returns -ENODEV to indicate unsupported */
8596 dev_priv->display.queue_flip = intel_default_queue_flip;
8598 switch (INTEL_INFO(dev)->gen) {
8600 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8604 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8609 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8613 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8616 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8622 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8623 * resume, or other times. This quirk makes sure that's the case for
8626 static void quirk_pipea_force(struct drm_device *dev)
8628 struct drm_i915_private *dev_priv = dev->dev_private;
8630 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8631 DRM_INFO("applying pipe a force quirk\n");
8635 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8637 static void quirk_ssc_force_disable(struct drm_device *dev)
8639 struct drm_i915_private *dev_priv = dev->dev_private;
8640 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8641 DRM_INFO("applying lvds SSC disable quirk\n");
8645 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8648 static void quirk_invert_brightness(struct drm_device *dev)
8650 struct drm_i915_private *dev_priv = dev->dev_private;
8651 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
8652 DRM_INFO("applying inverted panel brightness quirk\n");
8655 struct intel_quirk {
8657 int subsystem_vendor;
8658 int subsystem_device;
8659 void (*hook)(struct drm_device *dev);
8662 static struct intel_quirk intel_quirks[] = {
8663 /* HP Mini needs pipe A force quirk (LP: #322104) */
8664 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
8666 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8667 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8669 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8670 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8672 /* 830/845 need to leave pipe A & dpll A up */
8673 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8674 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8676 /* Lenovo U160 cannot use SSC on LVDS */
8677 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8679 /* Sony Vaio Y cannot use SSC on LVDS */
8680 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
8682 /* Acer Aspire 5734Z must invert backlight brightness */
8683 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
8686 static void intel_init_quirks(struct drm_device *dev)
8688 struct pci_dev *d = dev->pdev;
8691 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8692 struct intel_quirk *q = &intel_quirks[i];
8694 if (d->device == q->device &&
8695 (d->subsystem_vendor == q->subsystem_vendor ||
8696 q->subsystem_vendor == PCI_ANY_ID) &&
8697 (d->subsystem_device == q->subsystem_device ||
8698 q->subsystem_device == PCI_ANY_ID))
8703 /* Disable the VGA plane that we never use */
8704 static void i915_disable_vga(struct drm_device *dev)
8706 struct drm_i915_private *dev_priv = dev->dev_private;
8710 if (HAS_PCH_SPLIT(dev))
8711 vga_reg = CPU_VGACNTRL;
8715 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8716 outb(SR01, VGA_SR_INDEX);
8717 sr1 = inb(VGA_SR_DATA);
8718 outb(sr1 | 1<<5, VGA_SR_DATA);
8719 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8722 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8723 POSTING_READ(vga_reg);
8726 void intel_modeset_init_hw(struct drm_device *dev)
8728 /* We attempt to init the necessary power wells early in the initialization
8729 * time, so the subsystems that expect power to be enabled can work.
8731 intel_init_power_wells(dev);
8733 intel_prepare_ddi(dev);
8735 intel_init_clock_gating(dev);
8737 mutex_lock(&dev->struct_mutex);
8738 intel_enable_gt_powersave(dev);
8739 mutex_unlock(&dev->struct_mutex);
8742 void intel_modeset_init(struct drm_device *dev)
8744 struct drm_i915_private *dev_priv = dev->dev_private;
8747 drm_mode_config_init(dev);
8749 dev->mode_config.min_width = 0;
8750 dev->mode_config.min_height = 0;
8752 dev->mode_config.preferred_depth = 24;
8753 dev->mode_config.prefer_shadow = 1;
8755 dev->mode_config.funcs = &intel_mode_funcs;
8757 intel_init_quirks(dev);
8761 intel_init_display(dev);
8764 dev->mode_config.max_width = 2048;
8765 dev->mode_config.max_height = 2048;
8766 } else if (IS_GEN3(dev)) {
8767 dev->mode_config.max_width = 4096;
8768 dev->mode_config.max_height = 4096;
8770 dev->mode_config.max_width = 8192;
8771 dev->mode_config.max_height = 8192;
8773 dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
8775 DRM_DEBUG_KMS("%d display pipe%s available.\n",
8776 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
8778 for (i = 0; i < dev_priv->num_pipe; i++) {
8779 intel_crtc_init(dev, i);
8780 ret = intel_plane_init(dev, i);
8782 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
8785 intel_cpu_pll_init(dev);
8786 intel_pch_pll_init(dev);
8788 /* Just disable it once at startup */
8789 i915_disable_vga(dev);
8790 intel_setup_outputs(dev);
8794 intel_connector_break_all_links(struct intel_connector *connector)
8796 connector->base.dpms = DRM_MODE_DPMS_OFF;
8797 connector->base.encoder = NULL;
8798 connector->encoder->connectors_active = false;
8799 connector->encoder->base.crtc = NULL;
8802 static void intel_enable_pipe_a(struct drm_device *dev)
8804 struct intel_connector *connector;
8805 struct drm_connector *crt = NULL;
8806 struct intel_load_detect_pipe load_detect_temp;
8808 /* We can't just switch on the pipe A, we need to set things up with a
8809 * proper mode and output configuration. As a gross hack, enable pipe A
8810 * by enabling the load detect pipe once. */
8811 list_for_each_entry(connector,
8812 &dev->mode_config.connector_list,
8814 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8815 crt = &connector->base;
8823 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8824 intel_release_load_detect_pipe(crt, &load_detect_temp);
8830 intel_check_plane_mapping(struct intel_crtc *crtc)
8832 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8835 if (dev_priv->num_pipe == 1)
8838 reg = DSPCNTR(!crtc->plane);
8839 val = I915_READ(reg);
8841 if ((val & DISPLAY_PLANE_ENABLE) &&
8842 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8848 static void intel_sanitize_crtc(struct intel_crtc *crtc)
8850 struct drm_device *dev = crtc->base.dev;
8851 struct drm_i915_private *dev_priv = dev->dev_private;
8854 /* Clear any frame start delays used for debugging left by the BIOS */
8855 reg = PIPECONF(crtc->cpu_transcoder);
8856 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8858 /* We need to sanitize the plane -> pipe mapping first because this will
8859 * disable the crtc (and hence change the state) if it is wrong. Note
8860 * that gen4+ has a fixed plane -> pipe mapping. */
8861 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
8862 struct intel_connector *connector;
8865 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8866 crtc->base.base.id);
8868 /* Pipe has the wrong plane attached and the plane is active.
8869 * Temporarily change the plane mapping and disable everything
8871 plane = crtc->plane;
8872 crtc->plane = !plane;
8873 dev_priv->display.crtc_disable(&crtc->base);
8874 crtc->plane = plane;
8876 /* ... and break all links. */
8877 list_for_each_entry(connector, &dev->mode_config.connector_list,
8879 if (connector->encoder->base.crtc != &crtc->base)
8882 intel_connector_break_all_links(connector);
8885 WARN_ON(crtc->active);
8886 crtc->base.enabled = false;
8889 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8890 crtc->pipe == PIPE_A && !crtc->active) {
8891 /* BIOS forgot to enable pipe A, this mostly happens after
8892 * resume. Force-enable the pipe to fix this, the update_dpms
8893 * call below we restore the pipe to the right state, but leave
8894 * the required bits on. */
8895 intel_enable_pipe_a(dev);
8898 /* Adjust the state of the output pipe according to whether we
8899 * have active connectors/encoders. */
8900 intel_crtc_update_dpms(&crtc->base);
8902 if (crtc->active != crtc->base.enabled) {
8903 struct intel_encoder *encoder;
8905 /* This can happen either due to bugs in the get_hw_state
8906 * functions or because the pipe is force-enabled due to the
8908 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8910 crtc->base.enabled ? "enabled" : "disabled",
8911 crtc->active ? "enabled" : "disabled");
8913 crtc->base.enabled = crtc->active;
8915 /* Because we only establish the connector -> encoder ->
8916 * crtc links if something is active, this means the
8917 * crtc is now deactivated. Break the links. connector
8918 * -> encoder links are only establish when things are
8919 * actually up, hence no need to break them. */
8920 WARN_ON(crtc->active);
8922 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
8923 WARN_ON(encoder->connectors_active);
8924 encoder->base.crtc = NULL;
8929 static void intel_sanitize_encoder(struct intel_encoder *encoder)
8931 struct intel_connector *connector;
8932 struct drm_device *dev = encoder->base.dev;
8934 /* We need to check both for a crtc link (meaning that the
8935 * encoder is active and trying to read from a pipe) and the
8936 * pipe itself being active. */
8937 bool has_active_crtc = encoder->base.crtc &&
8938 to_intel_crtc(encoder->base.crtc)->active;
8940 if (encoder->connectors_active && !has_active_crtc) {
8941 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
8942 encoder->base.base.id,
8943 drm_get_encoder_name(&encoder->base));
8945 /* Connector is active, but has no active pipe. This is
8946 * fallout from our resume register restoring. Disable
8947 * the encoder manually again. */
8948 if (encoder->base.crtc) {
8949 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
8950 encoder->base.base.id,
8951 drm_get_encoder_name(&encoder->base));
8952 encoder->disable(encoder);
8955 /* Inconsistent output/port/pipe state happens presumably due to
8956 * a bug in one of the get_hw_state functions. Or someplace else
8957 * in our code, like the register restore mess on resume. Clamp
8958 * things to off as a safer default. */
8959 list_for_each_entry(connector,
8960 &dev->mode_config.connector_list,
8962 if (connector->encoder != encoder)
8965 intel_connector_break_all_links(connector);
8968 /* Enabled encoders without active connectors will be fixed in
8969 * the crtc fixup. */
8972 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
8973 * and i915 state tracking structures. */
8974 void intel_modeset_setup_hw_state(struct drm_device *dev)
8976 struct drm_i915_private *dev_priv = dev->dev_private;
8979 struct intel_crtc *crtc;
8980 struct intel_encoder *encoder;
8981 struct intel_connector *connector;
8983 if (IS_HASWELL(dev)) {
8984 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8986 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8987 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8988 case TRANS_DDI_EDP_INPUT_A_ON:
8989 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8992 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8995 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9000 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9001 crtc->cpu_transcoder = TRANSCODER_EDP;
9003 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9008 for_each_pipe(pipe) {
9009 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9011 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
9012 if (tmp & PIPECONF_ENABLE)
9013 crtc->active = true;
9015 crtc->active = false;
9017 crtc->base.enabled = crtc->active;
9019 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9021 crtc->active ? "enabled" : "disabled");
9024 if (IS_HASWELL(dev))
9025 intel_ddi_setup_hw_pll_state(dev);
9027 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9031 if (encoder->get_hw_state(encoder, &pipe)) {
9032 encoder->base.crtc =
9033 dev_priv->pipe_to_crtc_mapping[pipe];
9035 encoder->base.crtc = NULL;
9038 encoder->connectors_active = false;
9039 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9040 encoder->base.base.id,
9041 drm_get_encoder_name(&encoder->base),
9042 encoder->base.crtc ? "enabled" : "disabled",
9046 list_for_each_entry(connector, &dev->mode_config.connector_list,
9048 if (connector->get_hw_state(connector)) {
9049 connector->base.dpms = DRM_MODE_DPMS_ON;
9050 connector->encoder->connectors_active = true;
9051 connector->base.encoder = &connector->encoder->base;
9053 connector->base.dpms = DRM_MODE_DPMS_OFF;
9054 connector->base.encoder = NULL;
9056 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9057 connector->base.base.id,
9058 drm_get_connector_name(&connector->base),
9059 connector->base.encoder ? "enabled" : "disabled");
9062 /* HW state is read out, now we need to sanitize this mess. */
9063 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9065 intel_sanitize_encoder(encoder);
9068 for_each_pipe(pipe) {
9069 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9070 intel_sanitize_crtc(crtc);
9073 intel_modeset_update_staged_output_state(dev);
9075 intel_modeset_check_state(dev);
9077 drm_mode_config_reset(dev);
9080 void intel_modeset_gem_init(struct drm_device *dev)
9082 intel_modeset_init_hw(dev);
9084 intel_setup_overlay(dev);
9086 intel_modeset_setup_hw_state(dev);
9089 void intel_modeset_cleanup(struct drm_device *dev)
9091 struct drm_i915_private *dev_priv = dev->dev_private;
9092 struct drm_crtc *crtc;
9093 struct intel_crtc *intel_crtc;
9095 drm_kms_helper_poll_fini(dev);
9096 mutex_lock(&dev->struct_mutex);
9098 intel_unregister_dsm_handler();
9101 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9102 /* Skip inactive CRTCs */
9106 intel_crtc = to_intel_crtc(crtc);
9107 intel_increase_pllclock(crtc);
9110 intel_disable_fbc(dev);
9112 intel_disable_gt_powersave(dev);
9114 ironlake_teardown_rc6(dev);
9116 if (IS_VALLEYVIEW(dev))
9119 mutex_unlock(&dev->struct_mutex);
9121 /* Disable the irq before mode object teardown, for the irq might
9122 * enqueue unpin/hotplug work. */
9123 drm_irq_uninstall(dev);
9124 cancel_work_sync(&dev_priv->hotplug_work);
9125 cancel_work_sync(&dev_priv->rps.work);
9127 /* flush any delayed tasks or pending work */
9128 flush_scheduled_work();
9130 drm_mode_config_cleanup(dev);
9134 * Return which encoder is currently attached for connector.
9136 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9138 return &intel_attached_encoder(connector)->base;
9141 void intel_connector_attach_encoder(struct intel_connector *connector,
9142 struct intel_encoder *encoder)
9144 connector->encoder = encoder;
9145 drm_mode_connector_attach_encoder(&connector->base,
9150 * set vga decode state - true == enable VGA decode
9152 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9154 struct drm_i915_private *dev_priv = dev->dev_private;
9157 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9159 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9161 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9162 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9166 #ifdef CONFIG_DEBUG_FS
9167 #include <linux/seq_file.h>
9169 struct intel_display_error_state {
9170 struct intel_cursor_error_state {
9175 } cursor[I915_MAX_PIPES];
9177 struct intel_pipe_error_state {
9187 } pipe[I915_MAX_PIPES];
9189 struct intel_plane_error_state {
9197 } plane[I915_MAX_PIPES];
9200 struct intel_display_error_state *
9201 intel_display_capture_error_state(struct drm_device *dev)
9203 drm_i915_private_t *dev_priv = dev->dev_private;
9204 struct intel_display_error_state *error;
9205 enum transcoder cpu_transcoder;
9208 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9213 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9215 error->cursor[i].control = I915_READ(CURCNTR(i));
9216 error->cursor[i].position = I915_READ(CURPOS(i));
9217 error->cursor[i].base = I915_READ(CURBASE(i));
9219 error->plane[i].control = I915_READ(DSPCNTR(i));
9220 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9221 error->plane[i].size = I915_READ(DSPSIZE(i));
9222 error->plane[i].pos = I915_READ(DSPPOS(i));
9223 error->plane[i].addr = I915_READ(DSPADDR(i));
9224 if (INTEL_INFO(dev)->gen >= 4) {
9225 error->plane[i].surface = I915_READ(DSPSURF(i));
9226 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9229 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
9230 error->pipe[i].source = I915_READ(PIPESRC(i));
9231 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9232 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9233 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9234 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9235 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9236 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
9243 intel_display_print_error_state(struct seq_file *m,
9244 struct drm_device *dev,
9245 struct intel_display_error_state *error)
9247 drm_i915_private_t *dev_priv = dev->dev_private;
9250 seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
9252 seq_printf(m, "Pipe [%d]:\n", i);
9253 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9254 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9255 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9256 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9257 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9258 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9259 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9260 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9262 seq_printf(m, "Plane [%d]:\n", i);
9263 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9264 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9265 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
9266 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9267 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9268 if (INTEL_INFO(dev)->gen >= 4) {
9269 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9270 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9273 seq_printf(m, "Cursor [%d]:\n", i);
9274 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9275 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9276 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);