Pileus Git - ~andy/linux/blob - drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  45
  46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  47 static void intel_increase_pllclock(struct drm_crtc *crtc);
  48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  49
  50 typedef struct {
  51         /* given values */
  52         int n;
  53         int m1, m2;
  54         int p1, p2;
  55         /* derived values */
  56         int     dot;
  57         int     vco;
  58         int     m;
  59         int     p;
  60 } intel_clock_t;
  61
  62 typedef struct {
  63         int     min, max;
  64 } intel_range_t;
  65
  66 typedef struct {
  67         int     dot_limit;
  68         int     p2_slow, p2_fast;
  69 } intel_p2_t;
  70
  71 #define INTEL_P2_NUM                  2
  72 typedef struct intel_limit intel_limit_t;
  73 struct intel_limit {
  74         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  75         intel_p2_t          p2;
  76         bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  77                         int, int, intel_clock_t *, intel_clock_t *);
  78 };
  79
  80 /* FDI */
  81 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  82
  83 int
  84 intel_pch_rawclk(struct drm_device *dev)
  85 {
  86         struct drm_i915_private *dev_priv = dev->dev_private;
  87
  88         WARN_ON(!HAS_PCH_SPLIT(dev));
  89
  90         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  91 }
  92
  93 static bool
  94 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  95                     int target, int refclk, intel_clock_t *match_clock,
  96                     intel_clock_t *best_clock);
  97 static bool
  98 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  99                         int target, int refclk, intel_clock_t *match_clock,
 100                         intel_clock_t *best_clock);
 101
 102 static bool
 103 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 104                       int target, int refclk, intel_clock_t *match_clock,
 105                       intel_clock_t *best_clock);
 106 static bool
 107 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 108                            int target, int refclk, intel_clock_t *match_clock,
 109                            intel_clock_t *best_clock);
 110
 111 static bool
 112 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 113                         int target, int refclk, intel_clock_t *match_clock,
 114                         intel_clock_t *best_clock);
 115
 116 static inline u32 /* units of 100MHz */
 117 intel_fdi_link_freq(struct drm_device *dev)
 118 {
 119         if (IS_GEN5(dev)) {
 120                 struct drm_i915_private *dev_priv = dev->dev_private;
 121                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 122         } else
 123                 return 27;
 124 }
 125
 126 static const intel_limit_t intel_limits_i8xx_dvo = {
 127         .dot = { .min = 25000, .max = 350000 },
 128         .vco = { .min = 930000, .max = 1400000 },
 129         .n = { .min = 3, .max = 16 },
 130         .m = { .min = 96, .max = 140 },
 131         .m1 = { .min = 18, .max = 26 },
 132         .m2 = { .min = 6, .max = 16 },
 133         .p = { .min = 4, .max = 128 },
 134         .p1 = { .min = 2, .max = 33 },
 135         .p2 = { .dot_limit = 165000,
 136                 .p2_slow = 4, .p2_fast = 2 },
 137         .find_pll = intel_find_best_PLL,
 138 };
 139
 140 static const intel_limit_t intel_limits_i8xx_lvds = {
 141         .dot = { .min = 25000, .max = 350000 },
 142         .vco = { .min = 930000, .max = 1400000 },
 143         .n = { .min = 3, .max = 16 },
 144         .m = { .min = 96, .max = 140 },
 145         .m1 = { .min = 18, .max = 26 },
 146         .m2 = { .min = 6, .max = 16 },
 147         .p = { .min = 4, .max = 128 },
 148         .p1 = { .min = 1, .max = 6 },
 149         .p2 = { .dot_limit = 165000,
 150                 .p2_slow = 14, .p2_fast = 7 },
 151         .find_pll = intel_find_best_PLL,
 152 };
 153
 154 static const intel_limit_t intel_limits_i9xx_sdvo = {
 155         .dot = { .min = 20000, .max = 400000 },
 156         .vco = { .min = 1400000, .max = 2800000 },
 157         .n = { .min = 1, .max = 6 },
 158         .m = { .min = 70, .max = 120 },
 159         .m1 = { .min = 10, .max = 22 },
 160         .m2 = { .min = 5, .max = 9 },
 161         .p = { .min = 5, .max = 80 },
 162         .p1 = { .min = 1, .max = 8 },
 163         .p2 = { .dot_limit = 200000,
 164                 .p2_slow = 10, .p2_fast = 5 },
 165         .find_pll = intel_find_best_PLL,
 166 };
 167
 168 static const intel_limit_t intel_limits_i9xx_lvds = {
 169         .dot = { .min = 20000, .max = 400000 },
 170         .vco = { .min = 1400000, .max = 2800000 },
 171         .n = { .min = 1, .max = 6 },
 172         .m = { .min = 70, .max = 120 },
 173         .m1 = { .min = 10, .max = 22 },
 174         .m2 = { .min = 5, .max = 9 },
 175         .p = { .min = 7, .max = 98 },
 176         .p1 = { .min = 1, .max = 8 },
 177         .p2 = { .dot_limit = 112000,
 178                 .p2_slow = 14, .p2_fast = 7 },
 179         .find_pll = intel_find_best_PLL,
 180 };
 181
 182
 183 static const intel_limit_t intel_limits_g4x_sdvo = {
 184         .dot = { .min = 25000, .max = 270000 },
 185         .vco = { .min = 1750000, .max = 3500000},
 186         .n = { .min = 1, .max = 4 },
 187         .m = { .min = 104, .max = 138 },
 188         .m1 = { .min = 17, .max = 23 },
 189         .m2 = { .min = 5, .max = 11 },
 190         .p = { .min = 10, .max = 30 },
 191         .p1 = { .min = 1, .max = 3},
 192         .p2 = { .dot_limit = 270000,
 193                 .p2_slow = 10,
 194                 .p2_fast = 10
 195         },
 196         .find_pll = intel_g4x_find_best_PLL,
 197 };
 198
 199 static const intel_limit_t intel_limits_g4x_hdmi = {
 200         .dot = { .min = 22000, .max = 400000 },
 201         .vco = { .min = 1750000, .max = 3500000},
 202         .n = { .min = 1, .max = 4 },
 203         .m = { .min = 104, .max = 138 },
 204         .m1 = { .min = 16, .max = 23 },
 205         .m2 = { .min = 5, .max = 11 },
 206         .p = { .min = 5, .max = 80 },
 207         .p1 = { .min = 1, .max = 8},
 208         .p2 = { .dot_limit = 165000,
 209                 .p2_slow = 10, .p2_fast = 5 },
 210         .find_pll = intel_g4x_find_best_PLL,
 211 };
 212
 213 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 214         .dot = { .min = 20000, .max = 115000 },
 215         .vco = { .min = 1750000, .max = 3500000 },
 216         .n = { .min = 1, .max = 3 },
 217         .m = { .min = 104, .max = 138 },
 218         .m1 = { .min = 17, .max = 23 },
 219         .m2 = { .min = 5, .max = 11 },
 220         .p = { .min = 28, .max = 112 },
 221         .p1 = { .min = 2, .max = 8 },
 222         .p2 = { .dot_limit = 0,
 223                 .p2_slow = 14, .p2_fast = 14
 224         },
 225         .find_pll = intel_g4x_find_best_PLL,
 226 };
 227
 228 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 229         .dot = { .min = 80000, .max = 224000 },
 230         .vco = { .min = 1750000, .max = 3500000 },
 231         .n = { .min = 1, .max = 3 },
 232         .m = { .min = 104, .max = 138 },
 233         .m1 = { .min = 17, .max = 23 },
 234         .m2 = { .min = 5, .max = 11 },
 235         .p = { .min = 14, .max = 42 },
 236         .p1 = { .min = 2, .max = 6 },
 237         .p2 = { .dot_limit = 0,
 238                 .p2_slow = 7, .p2_fast = 7
 239         },
 240         .find_pll = intel_g4x_find_best_PLL,
 241 };
 242
 243 static const intel_limit_t intel_limits_g4x_display_port = {
 244         .dot = { .min = 161670, .max = 227000 },
 245         .vco = { .min = 1750000, .max = 3500000},
 246         .n = { .min = 1, .max = 2 },
 247         .m = { .min = 97, .max = 108 },
 248         .m1 = { .min = 0x10, .max = 0x12 },
 249         .m2 = { .min = 0x05, .max = 0x06 },
 250         .p = { .min = 10, .max = 20 },
 251         .p1 = { .min = 1, .max = 2},
 252         .p2 = { .dot_limit = 0,
 253                 .p2_slow = 10, .p2_fast = 10 },
 254         .find_pll = intel_find_pll_g4x_dp,
 255 };
 256
 257 static const intel_limit_t intel_limits_pineview_sdvo = {
 258         .dot = { .min = 20000, .max = 400000},
 259         .vco = { .min = 1700000, .max = 3500000 },
 260         /* Pineview's Ncounter is a ring counter */
 261         .n = { .min = 3, .max = 6 },
 262         .m = { .min = 2, .max = 256 },
 263         /* Pineview only has one combined m divider, which we treat as m2. */
 264         .m1 = { .min = 0, .max = 0 },
 265         .m2 = { .min = 0, .max = 254 },
 266         .p = { .min = 5, .max = 80 },
 267         .p1 = { .min = 1, .max = 8 },
 268         .p2 = { .dot_limit = 200000,
 269                 .p2_slow = 10, .p2_fast = 5 },
 270         .find_pll = intel_find_best_PLL,
 271 };
 272
 273 static const intel_limit_t intel_limits_pineview_lvds = {
 274         .dot = { .min = 20000, .max = 400000 },
 275         .vco = { .min = 1700000, .max = 3500000 },
 276         .n = { .min = 3, .max = 6 },
 277         .m = { .min = 2, .max = 256 },
 278         .m1 = { .min = 0, .max = 0 },
 279         .m2 = { .min = 0, .max = 254 },
 280         .p = { .min = 7, .max = 112 },
 281         .p1 = { .min = 1, .max = 8 },
 282         .p2 = { .dot_limit = 112000,
 283                 .p2_slow = 14, .p2_fast = 14 },
 284         .find_pll = intel_find_best_PLL,
 285 };
 286
 287 /* Ironlake / Sandybridge
 288  *
 289  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 290  * the range value for them is (actual_value - 2).
 291  */
 292 static const intel_limit_t intel_limits_ironlake_dac = {
 293         .dot = { .min = 25000, .max = 350000 },
 294         .vco = { .min = 1760000, .max = 3510000 },
 295         .n = { .min = 1, .max = 5 },
 296         .m = { .min = 79, .max = 127 },
 297         .m1 = { .min = 12, .max = 22 },
 298         .m2 = { .min = 5, .max = 9 },
 299         .p = { .min = 5, .max = 80 },
 300         .p1 = { .min = 1, .max = 8 },
 301         .p2 = { .dot_limit = 225000,
 302                 .p2_slow = 10, .p2_fast = 5 },
 303         .find_pll = intel_g4x_find_best_PLL,
 304 };
 305
 306 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 307         .dot = { .min = 25000, .max = 350000 },
 308         .vco = { .min = 1760000, .max = 3510000 },
 309         .n = { .min = 1, .max = 3 },
 310         .m = { .min = 79, .max = 118 },
 311         .m1 = { .min = 12, .max = 22 },
 312         .m2 = { .min = 5, .max = 9 },
 313         .p = { .min = 28, .max = 112 },
 314         .p1 = { .min = 2, .max = 8 },
 315         .p2 = { .dot_limit = 225000,
 316                 .p2_slow = 14, .p2_fast = 14 },
 317         .find_pll = intel_g4x_find_best_PLL,
 318 };
 319
 320 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 321         .dot = { .min = 25000, .max = 350000 },
 322         .vco = { .min = 1760000, .max = 3510000 },
 323         .n = { .min = 1, .max = 3 },
 324         .m = { .min = 79, .max = 127 },
 325         .m1 = { .min = 12, .max = 22 },
 326         .m2 = { .min = 5, .max = 9 },
 327         .p = { .min = 14, .max = 56 },
 328         .p1 = { .min = 2, .max = 8 },
 329         .p2 = { .dot_limit = 225000,
 330                 .p2_slow = 7, .p2_fast = 7 },
 331         .find_pll = intel_g4x_find_best_PLL,
 332 };
 333
 334 /* LVDS 100mhz refclk limits. */
 335 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 336         .dot = { .min = 25000, .max = 350000 },
 337         .vco = { .min = 1760000, .max = 3510000 },
 338         .n = { .min = 1, .max = 2 },
 339         .m = { .min = 79, .max = 126 },
 340         .m1 = { .min = 12, .max = 22 },
 341         .m2 = { .min = 5, .max = 9 },
 342         .p = { .min = 28, .max = 112 },
 343         .p1 = { .min = 2, .max = 8 },
 344         .p2 = { .dot_limit = 225000,
 345                 .p2_slow = 14, .p2_fast = 14 },
 346         .find_pll = intel_g4x_find_best_PLL,
 347 };
 348
 349 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 350         .dot = { .min = 25000, .max = 350000 },
 351         .vco = { .min = 1760000, .max = 3510000 },
 352         .n = { .min = 1, .max = 3 },
 353         .m = { .min = 79, .max = 126 },
 354         .m1 = { .min = 12, .max = 22 },
 355         .m2 = { .min = 5, .max = 9 },
 356         .p = { .min = 14, .max = 42 },
 357         .p1 = { .min = 2, .max = 6 },
 358         .p2 = { .dot_limit = 225000,
 359                 .p2_slow = 7, .p2_fast = 7 },
 360         .find_pll = intel_g4x_find_best_PLL,
 361 };
 362
 363 static const intel_limit_t intel_limits_ironlake_display_port = {
 364         .dot = { .min = 25000, .max = 350000 },
 365         .vco = { .min = 1760000, .max = 3510000},
 366         .n = { .min = 1, .max = 2 },
 367         .m = { .min = 81, .max = 90 },
 368         .m1 = { .min = 12, .max = 22 },
 369         .m2 = { .min = 5, .max = 9 },
 370         .p = { .min = 10, .max = 20 },
 371         .p1 = { .min = 1, .max = 2},
 372         .p2 = { .dot_limit = 0,
 373                 .p2_slow = 10, .p2_fast = 10 },
 374         .find_pll = intel_find_pll_ironlake_dp,
 375 };
 376
 377 static const intel_limit_t intel_limits_vlv_dac = {
 378         .dot = { .min = 25000, .max = 270000 },
 379         .vco = { .min = 4000000, .max = 6000000 },
 380         .n = { .min = 1, .max = 7 },
 381         .m = { .min = 22, .max = 450 }, /* guess */
 382         .m1 = { .min = 2, .max = 3 },
 383         .m2 = { .min = 11, .max = 156 },
 384         .p = { .min = 10, .max = 30 },
 385         .p1 = { .min = 2, .max = 3 },
 386         .p2 = { .dot_limit = 270000,
 387                 .p2_slow = 2, .p2_fast = 20 },
 388         .find_pll = intel_vlv_find_best_pll,
 389 };
 390
 391 static const intel_limit_t intel_limits_vlv_hdmi = {
 392         .dot = { .min = 20000, .max = 165000 },
 393         .vco = { .min = 4000000, .max = 5994000},
 394         .n = { .min = 1, .max = 7 },
 395         .m = { .min = 60, .max = 300 }, /* guess */
 396         .m1 = { .min = 2, .max = 3 },
 397         .m2 = { .min = 11, .max = 156 },
 398         .p = { .min = 10, .max = 30 },
 399         .p1 = { .min = 2, .max = 3 },
 400         .p2 = { .dot_limit = 270000,
 401                 .p2_slow = 2, .p2_fast = 20 },
 402         .find_pll = intel_vlv_find_best_pll,
 403 };
 404
 405 static const intel_limit_t intel_limits_vlv_dp = {
 406         .dot = { .min = 25000, .max = 270000 },
 407         .vco = { .min = 4000000, .max = 6000000 },
 408         .n = { .min = 1, .max = 7 },
 409         .m = { .min = 22, .max = 450 },
 410         .m1 = { .min = 2, .max = 3 },
 411         .m2 = { .min = 11, .max = 156 },
 412         .p = { .min = 10, .max = 30 },
 413         .p1 = { .min = 2, .max = 3 },
 414         .p2 = { .dot_limit = 270000,
 415                 .p2_slow = 2, .p2_fast = 20 },
 416         .find_pll = intel_vlv_find_best_pll,
 417 };
 418
 419 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
 420 {
 421         unsigned long flags;
 422         u32 val = 0;
 423
 424         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
 425         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 426                 DRM_ERROR("DPIO idle wait timed out\n");
 427                 goto out_unlock;
 428         }
 429
 430         I915_WRITE(DPIO_REG, reg);
 431         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
 432                    DPIO_BYTE);
 433         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 434                 DRM_ERROR("DPIO read wait timed out\n");
 435                 goto out_unlock;
 436         }
 437         val = I915_READ(DPIO_DATA);
 438
 439 out_unlock:
 440         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
 441         return val;
 442 }
 443
 444 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
 445                              u32 val)
 446 {
 447         unsigned long flags;
 448
 449         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
 450         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 451                 DRM_ERROR("DPIO idle wait timed out\n");
 452                 goto out_unlock;
 453         }
 454
 455         I915_WRITE(DPIO_DATA, val);
 456         I915_WRITE(DPIO_REG, reg);
 457         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
 458                    DPIO_BYTE);
 459         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
 460                 DRM_ERROR("DPIO write wait timed out\n");
 461
 462 out_unlock:
 463        spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
 464 }
 465
 466 static void vlv_init_dpio(struct drm_device *dev)
 467 {
 468         struct drm_i915_private *dev_priv = dev->dev_private;
 469
 470         /* Reset the DPIO config */
 471         I915_WRITE(DPIO_CTL, 0);
 472         POSTING_READ(DPIO_CTL);
 473         I915_WRITE(DPIO_CTL, 1);
 474         POSTING_READ(DPIO_CTL);
 475 }
 476
 477 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
 478 {
 479         DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
 480         return 1;
 481 }
 482
 483 static const struct dmi_system_id intel_dual_link_lvds[] = {
 484         {
 485                 .callback = intel_dual_link_lvds_callback,
 486                 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
 487                 .matches = {
 488                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 489                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
 490                 },
 491         },
 492         { }     /* terminating entry */
 493 };
 494
 495 static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
 496                               unsigned int reg)
 497 {
 498         unsigned int val;
 499
 500         /* use the module option value if specified */
 501         if (i915_lvds_channel_mode > 0)
 502                 return i915_lvds_channel_mode == 2;
 503
 504         if (dmi_check_system(intel_dual_link_lvds))
 505                 return true;
 506
 507         if (dev_priv->lvds_val)
 508                 val = dev_priv->lvds_val;
 509         else {
 510                 /* BIOS should set the proper LVDS register value at boot, but
 511                  * in reality, it doesn't set the value when the lid is closed;
 512                  * we need to check "the value to be set" in VBT when LVDS
 513                  * register is uninitialized.
 514                  */
 515                 val = I915_READ(reg);
 516                 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
 517                         val = dev_priv->bios_lvds_val;
 518                 dev_priv->lvds_val = val;
 519         }
 520         return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
 521 }
 522
 523 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 524                                                 int refclk)
 525 {
 526         struct drm_device *dev = crtc->dev;
 527         struct drm_i915_private *dev_priv = dev->dev_private;
 528         const intel_limit_t *limit;
 529
 530         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 531                 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
 532                         /* LVDS dual channel */
 533                         if (refclk == 100000)
 534                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 535                         else
 536                                 limit = &intel_limits_ironlake_dual_lvds;
 537                 } else {
 538                         if (refclk == 100000)
 539                                 limit = &intel_limits_ironlake_single_lvds_100m;
 540                         else
 541                                 limit = &intel_limits_ironlake_single_lvds;
 542                 }
 543         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 544                         HAS_eDP)
 545                 limit = &intel_limits_ironlake_display_port;
 546         else
 547                 limit = &intel_limits_ironlake_dac;
 548
 549         return limit;
 550 }
 551
 552 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 553 {
 554         struct drm_device *dev = crtc->dev;
 555         struct drm_i915_private *dev_priv = dev->dev_private;
 556         const intel_limit_t *limit;
 557
 558         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 559                 if (is_dual_link_lvds(dev_priv, LVDS))
 560                         /* LVDS with dual channel */
 561                         limit = &intel_limits_g4x_dual_channel_lvds;
 562                 else
 563                         /* LVDS with dual channel */
 564                         limit = &intel_limits_g4x_single_channel_lvds;
 565         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 566                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 567                 limit = &intel_limits_g4x_hdmi;
 568         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 569                 limit = &intel_limits_g4x_sdvo;
 570         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 571                 limit = &intel_limits_g4x_display_port;
 572         } else /* The option is for other outputs */
 573                 limit = &intel_limits_i9xx_sdvo;
 574
 575         return limit;
 576 }
 577
 578 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 579 {
 580         struct drm_device *dev = crtc->dev;
 581         const intel_limit_t *limit;
 582
 583         if (HAS_PCH_SPLIT(dev))
 584                 limit = intel_ironlake_limit(crtc, refclk);
 585         else if (IS_G4X(dev)) {
 586                 limit = intel_g4x_limit(crtc);
 587         } else if (IS_PINEVIEW(dev)) {
 588                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 589                         limit = &intel_limits_pineview_lvds;
 590                 else
 591                         limit = &intel_limits_pineview_sdvo;
 592         } else if (IS_VALLEYVIEW(dev)) {
 593                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
 594                         limit = &intel_limits_vlv_dac;
 595                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
 596                         limit = &intel_limits_vlv_hdmi;
 597                 else
 598                         limit = &intel_limits_vlv_dp;
 599         } else if (!IS_GEN2(dev)) {
 600                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 601                         limit = &intel_limits_i9xx_lvds;
 602                 else
 603                         limit = &intel_limits_i9xx_sdvo;
 604         } else {
 605                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 606                         limit = &intel_limits_i8xx_lvds;
 607                 else
 608                         limit = &intel_limits_i8xx_dvo;
 609         }
 610         return limit;
 611 }
 612
 613 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 614 static void pineview_clock(int refclk, intel_clock_t *clock)
 615 {
 616         clock->m = clock->m2 + 2;
 617         clock->p = clock->p1 * clock->p2;
 618         clock->vco = refclk * clock->m / clock->n;
 619         clock->dot = clock->vco / clock->p;
 620 }
 621
 622 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 623 {
 624         if (IS_PINEVIEW(dev)) {
 625                 pineview_clock(refclk, clock);
 626                 return;
 627         }
 628         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 629         clock->p = clock->p1 * clock->p2;
 630         clock->vco = refclk * clock->m / (clock->n + 2);
 631         clock->dot = clock->vco / clock->p;
 632 }
 633
 634 /**
 635  * Returns whether any output on the specified pipe is of the specified type
 636  */
 637 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 638 {
 639         struct drm_device *dev = crtc->dev;
 640         struct intel_encoder *encoder;
 641
 642         for_each_encoder_on_crtc(dev, crtc, encoder)
 643                 if (encoder->type == type)
 644                         return true;
 645
 646         return false;
 647 }
 648
 649 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 650 /**
 651  * Returns whether the given set of divisors are valid for a given refclk with
 652  * the given connectors.
 653  */
 654
 655 static bool intel_PLL_is_valid(struct drm_device *dev,
 656                                const intel_limit_t *limit,
 657                                const intel_clock_t *clock)
 658 {
 659         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 660                 INTELPllInvalid("p1 out of range\n");
 661         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 662                 INTELPllInvalid("p out of range\n");
 663         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 664                 INTELPllInvalid("m2 out of range\n");
 665         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 666                 INTELPllInvalid("m1 out of range\n");
 667         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 668                 INTELPllInvalid("m1 <= m2\n");
 669         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 670                 INTELPllInvalid("m out of range\n");
 671         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 672                 INTELPllInvalid("n out of range\n");
 673         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 674                 INTELPllInvalid("vco out of range\n");
 675         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 676          * connector, etc., rather than just a single range.
 677          */
 678         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 679                 INTELPllInvalid("dot out of range\n");
 680
 681         return true;
 682 }
 683
 684 static bool
 685 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 686                     int target, int refclk, intel_clock_t *match_clock,
 687                     intel_clock_t *best_clock)
 688
 689 {
 690         struct drm_device *dev = crtc->dev;
 691         struct drm_i915_private *dev_priv = dev->dev_private;
 692         intel_clock_t clock;
 693         int err = target;
 694
 695         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 696             (I915_READ(LVDS)) != 0) {
 697                 /*
 698                  * For LVDS, if the panel is on, just rely on its current
 699                  * settings for dual-channel.  We haven't figured out how to
 700                  * reliably set up different single/dual channel state, if we
 701                  * even can.
 702                  */
 703                 if (is_dual_link_lvds(dev_priv, LVDS))
 704                         clock.p2 = limit->p2.p2_fast;
 705                 else
 706                         clock.p2 = limit->p2.p2_slow;
 707         } else {
 708                 if (target < limit->p2.dot_limit)
 709                         clock.p2 = limit->p2.p2_slow;
 710                 else
 711                         clock.p2 = limit->p2.p2_fast;
 712         }
 713
 714         memset(best_clock, 0, sizeof(*best_clock));
 715
 716         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 717              clock.m1++) {
 718                 for (clock.m2 = limit->m2.min;
 719                      clock.m2 <= limit->m2.max; clock.m2++) {
 720                         /* m1 is always 0 in Pineview */
 721                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 722                                 break;
 723                         for (clock.n = limit->n.min;
 724                              clock.n <= limit->n.max; clock.n++) {
 725                                 for (clock.p1 = limit->p1.min;
 726                                         clock.p1 <= limit->p1.max; clock.p1++) {
 727                                         int this_err;
 728
 729                                         intel_clock(dev, refclk, &clock);
 730                                         if (!intel_PLL_is_valid(dev, limit,
 731                                                                 &clock))
 732                                                 continue;
 733                                         if (match_clock &&
 734                                             clock.p != match_clock->p)
 735                                                 continue;
 736
 737                                         this_err = abs(clock.dot - target);
 738                                         if (this_err < err) {
 739                                                 *best_clock = clock;
 740                                                 err = this_err;
 741                                         }
 742                                 }
 743                         }
 744                 }
 745         }
 746
 747         return (err != target);
 748 }
 749
 750 static bool
 751 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 752                         int target, int refclk, intel_clock_t *match_clock,
 753                         intel_clock_t *best_clock)
 754 {
 755         struct drm_device *dev = crtc->dev;
 756         struct drm_i915_private *dev_priv = dev->dev_private;
 757         intel_clock_t clock;
 758         int max_n;
 759         bool found;
 760         /* approximately equals target * 0.00585 */
 761         int err_most = (target >> 8) + (target >> 9);
 762         found = false;
 763
 764         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 765                 int lvds_reg;
 766
 767                 if (HAS_PCH_SPLIT(dev))
 768                         lvds_reg = PCH_LVDS;
 769                 else
 770                         lvds_reg = LVDS;
 771                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 772                     LVDS_CLKB_POWER_UP)
 773                         clock.p2 = limit->p2.p2_fast;
 774                 else
 775                         clock.p2 = limit->p2.p2_slow;
 776         } else {
 777                 if (target < limit->p2.dot_limit)
 778                         clock.p2 = limit->p2.p2_slow;
 779                 else
 780                         clock.p2 = limit->p2.p2_fast;
 781         }
 782
 783         memset(best_clock, 0, sizeof(*best_clock));
 784         max_n = limit->n.max;
 785         /* based on hardware requirement, prefer smaller n to precision */
 786         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 787                 /* based on hardware requirement, prefere larger m1,m2 */
 788                 for (clock.m1 = limit->m1.max;
 789                      clock.m1 >= limit->m1.min; clock.m1--) {
 790                         for (clock.m2 = limit->m2.max;
 791                              clock.m2 >= limit->m2.min; clock.m2--) {
 792                                 for (clock.p1 = limit->p1.max;
 793                                      clock.p1 >= limit->p1.min; clock.p1--) {
 794                                         int this_err;
 795
 796                                         intel_clock(dev, refclk, &clock);
 797                                         if (!intel_PLL_is_valid(dev, limit,
 798                                                                 &clock))
 799                                                 continue;
 800                                         if (match_clock &&
 801                                             clock.p != match_clock->p)
 802                                                 continue;
 803
 804                                         this_err = abs(clock.dot - target);
 805                                         if (this_err < err_most) {
 806                                                 *best_clock = clock;
 807                                                 err_most = this_err;
 808                                                 max_n = clock.n;
 809                                                 found = true;
 810                                         }
 811                                 }
 812                         }
 813                 }
 814         }
 815         return found;
 816 }
 817
 818 static bool
 819 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 820                            int target, int refclk, intel_clock_t *match_clock,
 821                            intel_clock_t *best_clock)
 822 {
 823         struct drm_device *dev = crtc->dev;
 824         intel_clock_t clock;
 825
 826         if (target < 200000) {
 827                 clock.n = 1;
 828                 clock.p1 = 2;
 829                 clock.p2 = 10;
 830                 clock.m1 = 12;
 831                 clock.m2 = 9;
 832         } else {
 833                 clock.n = 2;
 834                 clock.p1 = 1;
 835                 clock.p2 = 10;
 836                 clock.m1 = 14;
 837                 clock.m2 = 8;
 838         }
 839         intel_clock(dev, refclk, &clock);
 840         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 841         return true;
 842 }
 843
 844 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 845 static bool
 846 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 847                       int target, int refclk, intel_clock_t *match_clock,
 848                       intel_clock_t *best_clock)
 849 {
 850         intel_clock_t clock;
 851         if (target < 200000) {
 852                 clock.p1 = 2;
 853                 clock.p2 = 10;
 854                 clock.n = 2;
 855                 clock.m1 = 23;
 856                 clock.m2 = 8;
 857         } else {
 858                 clock.p1 = 1;
 859                 clock.p2 = 10;
 860                 clock.n = 1;
 861                 clock.m1 = 14;
 862                 clock.m2 = 2;
 863         }
 864         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 865         clock.p = (clock.p1 * clock.p2);
 866         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 867         clock.vco = 0;
 868         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 869         return true;
 870 }
 871 static bool
 872 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 873                         int target, int refclk, intel_clock_t *match_clock,
 874                         intel_clock_t *best_clock)
 875 {
 876         u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
 877         u32 m, n, fastclk;
 878         u32 updrate, minupdate, fracbits, p;
 879         unsigned long bestppm, ppm, absppm;
 880         int dotclk, flag;
 881
 882         flag = 0;
 883         dotclk = target * 1000;
 884         bestppm = 1000000;
 885         ppm = absppm = 0;
 886         fastclk = dotclk / (2*100);
 887         updrate = 0;
 888         minupdate = 19200;
 889         fracbits = 1;
 890         n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
 891         bestm1 = bestm2 = bestp1 = bestp2 = 0;
 892
 893         /* based on hardware requirement, prefer smaller n to precision */
 894         for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
 895                 updrate = refclk / n;
 896                 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
 897                         for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
 898                                 if (p2 > 10)
 899                                         p2 = p2 - 1;
 900                                 p = p1 * p2;
 901                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 902                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
 903                                         m2 = (((2*(fastclk * p * n / m1 )) +
 904                                                refclk) / (2*refclk));
 905                                         m = m1 * m2;
 906                                         vco = updrate * m;
 907                                         if (vco >= limit->vco.min && vco < limit->vco.max) {
 908                                                 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
 909                                                 absppm = (ppm > 0) ? ppm : (-ppm);
 910                                                 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
 911                                                         bestppm = 0;
 912                                                         flag = 1;
 913                                                 }
 914                                                 if (absppm < bestppm - 10) {
 915                                                         bestppm = absppm;
 916                                                         flag = 1;
 917                                                 }
 918                                                 if (flag) {
 919                                                         bestn = n;
 920                                                         bestm1 = m1;
 921                                                         bestm2 = m2;
 922                                                         bestp1 = p1;
 923                                                         bestp2 = p2;
 924                                                         flag = 0;
 925                                                 }
 926                                         }
 927                                 }
 928                         }
 929                 }
 930         }
 931         best_clock->n = bestn;
 932         best_clock->m1 = bestm1;
 933         best_clock->m2 = bestm2;
 934         best_clock->p1 = bestp1;
 935         best_clock->p2 = bestp2;
 936
 937         return true;
 938 }
 939
 940 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 941                                              enum pipe pipe)
 942 {
 943         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 944         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 945
 946         return intel_crtc->cpu_transcoder;
 947 }
 948
 949 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 950 {
 951         struct drm_i915_private *dev_priv = dev->dev_private;
 952         u32 frame, frame_reg = PIPEFRAME(pipe);
 953
 954         frame = I915_READ(frame_reg);
 955
 956         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 957                 DRM_DEBUG_KMS("vblank wait timed out\n");
 958 }
 959
 960 /**
 961  * intel_wait_for_vblank - wait for vblank on a given pipe
 962  * @dev: drm device
 963  * @pipe: pipe to wait for
 964  *
 965  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 966  * mode setting code.
 967  */
 968 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 969 {
 970         struct drm_i915_private *dev_priv = dev->dev_private;
 971         int pipestat_reg = PIPESTAT(pipe);
 972
 973         if (INTEL_INFO(dev)->gen >= 5) {
 974                 ironlake_wait_for_vblank(dev, pipe);
 975                 return;
 976         }
 977
 978         /* Clear existing vblank status. Note this will clear any other
 979          * sticky status fields as well.
 980          *
 981          * This races with i915_driver_irq_handler() with the result
 982          * that either function could miss a vblank event.  Here it is not
 983          * fatal, as we will either wait upon the next vblank interrupt or
 984          * timeout.  Generally speaking intel_wait_for_vblank() is only
 985          * called during modeset at which time the GPU should be idle and
 986          * should *not* be performing page flips and thus not waiting on
 987          * vblanks...
 988          * Currently, the result of us stealing a vblank from the irq
 989          * handler is that a single frame will be skipped during swapbuffers.
 990          */
 991         I915_WRITE(pipestat_reg,
 992                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 993
 994         /* Wait for vblank interrupt bit to set */
 995         if (wait_for(I915_READ(pipestat_reg) &
 996                      PIPE_VBLANK_INTERRUPT_STATUS,
 997                      50))
 998                 DRM_DEBUG_KMS("vblank wait timed out\n");
 999 }
1000
1001 /*
1002  * intel_wait_for_pipe_off - wait for pipe to turn off
1003  * @dev: drm device
1004  * @pipe: pipe to wait for
1005  *
1006  * After disabling a pipe, we can't wait for vblank in the usual way,
1007  * spinning on the vblank interrupt status bit, since we won't actually
1008  * see an interrupt when the pipe is disabled.
1009  *
1010  * On Gen4 and above:
1011  *   wait for the pipe register state bit to turn off
1012  *
1013  * Otherwise:
1014  *   wait for the display line value to settle (it usually
1015  *   ends up stopping at the start of the next frame).
1016  *
1017  */
1018 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1019 {
1020         struct drm_i915_private *dev_priv = dev->dev_private;
1021         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1022                                                                       pipe);
1023
1024         if (INTEL_INFO(dev)->gen >= 4) {
1025                 int reg = PIPECONF(cpu_transcoder);
1026
1027                 /* Wait for the Pipe State to go off */
1028                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1029                              100))
1030                         WARN(1, "pipe_off wait timed out\n");
1031         } else {
1032                 u32 last_line, line_mask;
1033                 int reg = PIPEDSL(pipe);
1034                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1035
1036                 if (IS_GEN2(dev))
1037                         line_mask = DSL_LINEMASK_GEN2;
1038                 else
1039                         line_mask = DSL_LINEMASK_GEN3;
1040
1041                 /* Wait for the display line to settle */
1042                 do {
1043                         last_line = I915_READ(reg) & line_mask;
1044                         mdelay(5);
1045                 } while (((I915_READ(reg) & line_mask) != last_line) &&
1046                          time_after(timeout, jiffies));
1047                 if (time_after(jiffies, timeout))
1048                         WARN(1, "pipe_off wait timed out\n");
1049         }
1050 }
1051
1052 static const char *state_string(bool enabled)
1053 {
1054         return enabled ? "on" : "off";
1055 }
1056
1057 /* Only for pre-ILK configs */
1058 static void assert_pll(struct drm_i915_private *dev_priv,
1059                        enum pipe pipe, bool state)
1060 {
1061         int reg;
1062         u32 val;
1063         bool cur_state;
1064
1065         reg = DPLL(pipe);
1066         val = I915_READ(reg);
1067         cur_state = !!(val & DPLL_VCO_ENABLE);
1068         WARN(cur_state != state,
1069              "PLL state assertion failure (expected %s, current %s)\n",
1070              state_string(state), state_string(cur_state));
1071 }
1072 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1073 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1074
1075 /* For ILK+ */
1076 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1077                            struct intel_pch_pll *pll,
1078                            struct intel_crtc *crtc,
1079                            bool state)
1080 {
1081         u32 val;
1082         bool cur_state;
1083
1084         if (HAS_PCH_LPT(dev_priv->dev)) {
1085                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1086                 return;
1087         }
1088
1089         if (WARN (!pll,
1090                   "asserting PCH PLL %s with no PLL\n", state_string(state)))
1091                 return;
1092
1093         val = I915_READ(pll->pll_reg);
1094         cur_state = !!(val & DPLL_VCO_ENABLE);
1095         WARN(cur_state != state,
1096              "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1097              pll->pll_reg, state_string(state), state_string(cur_state), val);
1098
1099         /* Make sure the selected PLL is correctly attached to the transcoder */
1100         if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
1101                 u32 pch_dpll;
1102
1103                 pch_dpll = I915_READ(PCH_DPLL_SEL);
1104                 cur_state = pll->pll_reg == _PCH_DPLL_B;
1105                 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1106                           "PLL[%d] not attached to this transcoder %d: %08x\n",
1107                           cur_state, crtc->pipe, pch_dpll)) {
1108                         cur_state = !!(val >> (4*crtc->pipe + 3));
1109                         WARN(cur_state != state,
1110                              "PLL[%d] not %s on this transcoder %d: %08x\n",
1111                              pll->pll_reg == _PCH_DPLL_B,
1112                              state_string(state),
1113                              crtc->pipe,
1114                              val);
1115                 }
1116         }
1117 }
1118 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1119 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1120
1121 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1122                           enum pipe pipe, bool state)
1123 {
1124         int reg;
1125         u32 val;
1126         bool cur_state;
1127         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1128                                                                       pipe);
1129
1130         if (IS_HASWELL(dev_priv->dev)) {
1131                 /* On Haswell, DDI is used instead of FDI_TX_CTL */
1132                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1133                 val = I915_READ(reg);
1134                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1135         } else {
1136                 reg = FDI_TX_CTL(pipe);
1137                 val = I915_READ(reg);
1138                 cur_state = !!(val & FDI_TX_ENABLE);
1139         }
1140         WARN(cur_state != state,
1141              "FDI TX state assertion failure (expected %s, current %s)\n",
1142              state_string(state), state_string(cur_state));
1143 }
1144 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1145 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1146
1147 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1148                           enum pipe pipe, bool state)
1149 {
1150         int reg;
1151         u32 val;
1152         bool cur_state;
1153
1154         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1155                         DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1156                         return;
1157         } else {
1158                 reg = FDI_RX_CTL(pipe);
1159                 val = I915_READ(reg);
1160                 cur_state = !!(val & FDI_RX_ENABLE);
1161         }
1162         WARN(cur_state != state,
1163              "FDI RX state assertion failure (expected %s, current %s)\n",
1164              state_string(state), state_string(cur_state));
1165 }
1166 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1167 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1168
1169 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1170                                       enum pipe pipe)
1171 {
1172         int reg;
1173         u32 val;
1174
1175         /* ILK FDI PLL is always enabled */
1176         if (dev_priv->info->gen == 5)
1177                 return;
1178
1179         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1180         if (IS_HASWELL(dev_priv->dev))
1181                 return;
1182
1183         reg = FDI_TX_CTL(pipe);
1184         val = I915_READ(reg);
1185         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1186 }
1187
1188 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1189                                       enum pipe pipe)
1190 {
1191         int reg;
1192         u32 val;
1193
1194         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1195                 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1196                 return;
1197         }
1198         reg = FDI_RX_CTL(pipe);
1199         val = I915_READ(reg);
1200         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1201 }
1202
1203 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1204                                   enum pipe pipe)
1205 {
1206         int pp_reg, lvds_reg;
1207         u32 val;
1208         enum pipe panel_pipe = PIPE_A;
1209         bool locked = true;
1210
1211         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1212                 pp_reg = PCH_PP_CONTROL;
1213                 lvds_reg = PCH_LVDS;
1214         } else {
1215                 pp_reg = PP_CONTROL;
1216                 lvds_reg = LVDS;
1217         }
1218
1219         val = I915_READ(pp_reg);
1220         if (!(val & PANEL_POWER_ON) ||
1221             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1222                 locked = false;
1223
1224         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1225                 panel_pipe = PIPE_B;
1226
1227         WARN(panel_pipe == pipe && locked,
1228              "panel assertion failure, pipe %c regs locked\n",
1229              pipe_name(pipe));
1230 }
1231
1232 void assert_pipe(struct drm_i915_private *dev_priv,
1233                  enum pipe pipe, bool state)
1234 {
1235         int reg;
1236         u32 val;
1237         bool cur_state;
1238         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1239                                                                       pipe);
1240
1241         /* if we need the pipe A quirk it must be always on */
1242         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1243                 state = true;
1244
1245         reg = PIPECONF(cpu_transcoder);
1246         val = I915_READ(reg);
1247         cur_state = !!(val & PIPECONF_ENABLE);
1248         WARN(cur_state != state,
1249              "pipe %c assertion failure (expected %s, current %s)\n",
1250              pipe_name(pipe), state_string(state), state_string(cur_state));
1251 }
1252
1253 static void assert_plane(struct drm_i915_private *dev_priv,
1254                          enum plane plane, bool state)
1255 {
1256         int reg;
1257         u32 val;
1258         bool cur_state;
1259
1260         reg = DSPCNTR(plane);
1261         val = I915_READ(reg);
1262         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1263         WARN(cur_state != state,
1264              "plane %c assertion failure (expected %s, current %s)\n",
1265              plane_name(plane), state_string(state), state_string(cur_state));
1266 }
1267
1268 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1269 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1270
1271 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1272                                    enum pipe pipe)
1273 {
1274         int reg, i;
1275         u32 val;
1276         int cur_pipe;
1277
1278         /* Planes are fixed to pipes on ILK+ */
1279         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1280                 reg = DSPCNTR(pipe);
1281                 val = I915_READ(reg);
1282                 WARN((val & DISPLAY_PLANE_ENABLE),
1283                      "plane %c assertion failure, should be disabled but not\n",
1284                      plane_name(pipe));
1285                 return;
1286         }
1287
1288         /* Need to check both planes against the pipe */
1289         for (i = 0; i < 2; i++) {
1290                 reg = DSPCNTR(i);
1291                 val = I915_READ(reg);
1292                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1293                         DISPPLANE_SEL_PIPE_SHIFT;
1294                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1295                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1296                      plane_name(i), pipe_name(pipe));
1297         }
1298 }
1299
1300 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1301 {
1302         u32 val;
1303         bool enabled;
1304
1305         if (HAS_PCH_LPT(dev_priv->dev)) {
1306                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1307                 return;
1308         }
1309
1310         val = I915_READ(PCH_DREF_CONTROL);
1311         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1312                             DREF_SUPERSPREAD_SOURCE_MASK));
1313         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1314 }
1315
1316 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1317                                        enum pipe pipe)
1318 {
1319         int reg;
1320         u32 val;
1321         bool enabled;
1322
1323         reg = TRANSCONF(pipe);
1324         val = I915_READ(reg);
1325         enabled = !!(val & TRANS_ENABLE);
1326         WARN(enabled,
1327              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1328              pipe_name(pipe));
1329 }
1330
1331 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1332                             enum pipe pipe, u32 port_sel, u32 val)
1333 {
1334         if ((val & DP_PORT_EN) == 0)
1335                 return false;
1336
1337         if (HAS_PCH_CPT(dev_priv->dev)) {
1338                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1339                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1340                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1341                         return false;
1342         } else {
1343                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1344                         return false;
1345         }
1346         return true;
1347 }
1348
1349 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1350                               enum pipe pipe, u32 val)
1351 {
1352         if ((val & PORT_ENABLE) == 0)
1353                 return false;
1354
1355         if (HAS_PCH_CPT(dev_priv->dev)) {
1356                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1357                         return false;
1358         } else {
1359                 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1360                         return false;
1361         }
1362         return true;
1363 }
1364
1365 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1366                               enum pipe pipe, u32 val)
1367 {
1368         if ((val & LVDS_PORT_EN) == 0)
1369                 return false;
1370
1371         if (HAS_PCH_CPT(dev_priv->dev)) {
1372                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1373                         return false;
1374         } else {
1375                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1376                         return false;
1377         }
1378         return true;
1379 }
1380
1381 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1382                               enum pipe pipe, u32 val)
1383 {
1384         if ((val & ADPA_DAC_ENABLE) == 0)
1385                 return false;
1386         if (HAS_PCH_CPT(dev_priv->dev)) {
1387                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1388                         return false;
1389         } else {
1390                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1391                         return false;
1392         }
1393         return true;
1394 }
1395
1396 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1397                                    enum pipe pipe, int reg, u32 port_sel)
1398 {
1399         u32 val = I915_READ(reg);
1400         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1401              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1402              reg, pipe_name(pipe));
1403
1404         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1405              && (val & DP_PIPEB_SELECT),
1406              "IBX PCH dp port still using transcoder B\n");
1407 }
1408
1409 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1410                                      enum pipe pipe, int reg)
1411 {
1412         u32 val = I915_READ(reg);
1413         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1414              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1415              reg, pipe_name(pipe));
1416
1417         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1418              && (val & SDVO_PIPE_B_SELECT),
1419              "IBX PCH hdmi port still using transcoder B\n");
1420 }
1421
1422 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1423                                       enum pipe pipe)
1424 {
1425         int reg;
1426         u32 val;
1427
1428         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1429         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1430         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1431
1432         reg = PCH_ADPA;
1433         val = I915_READ(reg);
1434         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1435              "PCH VGA enabled on transcoder %c, should be disabled\n",
1436              pipe_name(pipe));
1437
1438         reg = PCH_LVDS;
1439         val = I915_READ(reg);
1440         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1441              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1442              pipe_name(pipe));
1443
1444         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1445         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1446         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1447 }
1448
1449 /**
1450  * intel_enable_pll - enable a PLL
1451  * @dev_priv: i915 private structure
1452  * @pipe: pipe PLL to enable
1453  *
1454  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1455  * make sure the PLL reg is writable first though, since the panel write
1456  * protect mechanism may be enabled.
1457  *
1458  * Note!  This is for pre-ILK only.
1459  *
1460  * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1461  */
1462 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1463 {
1464         int reg;
1465         u32 val;
1466
1467         /* No really, not for ILK+ */
1468         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1469
1470         /* PLL is protected by panel, make sure we can write it */
1471         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1472                 assert_panel_unlocked(dev_priv, pipe);
1473
1474         reg = DPLL(pipe);
1475         val = I915_READ(reg);
1476         val |= DPLL_VCO_ENABLE;
1477
1478         /* We do this three times for luck */
1479         I915_WRITE(reg, val);
1480         POSTING_READ(reg);
1481         udelay(150); /* wait for warmup */
1482         I915_WRITE(reg, val);
1483         POSTING_READ(reg);
1484         udelay(150); /* wait for warmup */
1485         I915_WRITE(reg, val);
1486         POSTING_READ(reg);
1487         udelay(150); /* wait for warmup */
1488 }
1489
1490 /**
1491  * intel_disable_pll - disable a PLL
1492  * @dev_priv: i915 private structure
1493  * @pipe: pipe PLL to disable
1494  *
1495  * Disable the PLL for @pipe, making sure the pipe is off first.
1496  *
1497  * Note!  This is for pre-ILK only.
1498  */
1499 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1500 {
1501         int reg;
1502         u32 val;
1503
1504         /* Don't disable pipe A or pipe A PLLs if needed */
1505         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1506                 return;
1507
1508         /* Make sure the pipe isn't still relying on us */
1509         assert_pipe_disabled(dev_priv, pipe);
1510
1511         reg = DPLL(pipe);
1512         val = I915_READ(reg);
1513         val &= ~DPLL_VCO_ENABLE;
1514         I915_WRITE(reg, val);
1515         POSTING_READ(reg);
1516 }
1517
1518 /* SBI access */
1519 static void
1520 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1521 {
1522         unsigned long flags;
1523
1524         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1525         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1526                                 100)) {
1527                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1528                 goto out_unlock;
1529         }
1530
1531         I915_WRITE(SBI_ADDR,
1532                         (reg << 16));
1533         I915_WRITE(SBI_DATA,
1534                         value);
1535         I915_WRITE(SBI_CTL_STAT,
1536                         SBI_BUSY |
1537                         SBI_CTL_OP_CRWR);
1538
1539         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1540                                 100)) {
1541                 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1542                 goto out_unlock;
1543         }
1544
1545 out_unlock:
1546         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1547 }
1548
1549 static u32
1550 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1551 {
1552         unsigned long flags;
1553         u32 value = 0;
1554
1555         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1556         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1557                                 100)) {
1558                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1559                 goto out_unlock;
1560         }
1561
1562         I915_WRITE(SBI_ADDR,
1563                         (reg << 16));
1564         I915_WRITE(SBI_CTL_STAT,
1565                         SBI_BUSY |
1566                         SBI_CTL_OP_CRRD);
1567
1568         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1569                                 100)) {
1570                 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1571                 goto out_unlock;
1572         }
1573
1574         value = I915_READ(SBI_DATA);
1575
1576 out_unlock:
1577         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1578         return value;
1579 }
1580
1581 /**
1582  * intel_enable_pch_pll - enable PCH PLL
1583  * @dev_priv: i915 private structure
1584  * @pipe: pipe PLL to enable
1585  *
1586  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1587  * drives the transcoder clock.
1588  */
1589 static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
1590 {
1591         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1592         struct intel_pch_pll *pll;
1593         int reg;
1594         u32 val;
1595
1596         /* PCH PLLs only available on ILK, SNB and IVB */
1597         BUG_ON(dev_priv->info->gen < 5);
1598         pll = intel_crtc->pch_pll;
1599         if (pll == NULL)
1600                 return;
1601
1602         if (WARN_ON(pll->refcount == 0))
1603                 return;
1604
1605         DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1606                       pll->pll_reg, pll->active, pll->on,
1607                       intel_crtc->base.base.id);
1608
1609         /* PCH refclock must be enabled first */
1610         assert_pch_refclk_enabled(dev_priv);
1611
1612         if (pll->active++ && pll->on) {
1613                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1614                 return;
1615         }
1616
1617         DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1618
1619         reg = pll->pll_reg;
1620         val = I915_READ(reg);
1621         val |= DPLL_VCO_ENABLE;
1622         I915_WRITE(reg, val);
1623         POSTING_READ(reg);
1624         udelay(200);
1625
1626         pll->on = true;
1627 }
1628
1629 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1630 {
1631         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1632         struct intel_pch_pll *pll = intel_crtc->pch_pll;
1633         int reg;
1634         u32 val;
1635
1636         /* PCH only available on ILK+ */
1637         BUG_ON(dev_priv->info->gen < 5);
1638         if (pll == NULL)
1639                return;
1640
1641         if (WARN_ON(pll->refcount == 0))
1642                 return;
1643
1644         DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1645                       pll->pll_reg, pll->active, pll->on,
1646                       intel_crtc->base.base.id);
1647
1648         if (WARN_ON(pll->active == 0)) {
1649                 assert_pch_pll_disabled(dev_priv, pll, NULL);
1650                 return;
1651         }
1652
1653         if (--pll->active) {
1654                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1655                 return;
1656         }
1657
1658         DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1659
1660         /* Make sure transcoder isn't still depending on us */
1661         assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1662
1663         reg = pll->pll_reg;
1664         val = I915_READ(reg);
1665         val &= ~DPLL_VCO_ENABLE;
1666         I915_WRITE(reg, val);
1667         POSTING_READ(reg);
1668         udelay(200);
1669
1670         pll->on = false;
1671 }
1672
1673 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1674                                     enum pipe pipe)
1675 {
1676         int reg;
1677         u32 val, pipeconf_val;
1678         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1679
1680         /* PCH only available on ILK+ */
1681         BUG_ON(dev_priv->info->gen < 5);
1682
1683         /* Make sure PCH DPLL is enabled */
1684         assert_pch_pll_enabled(dev_priv,
1685                                to_intel_crtc(crtc)->pch_pll,
1686                                to_intel_crtc(crtc));
1687
1688         /* FDI must be feeding us bits for PCH ports */
1689         assert_fdi_tx_enabled(dev_priv, pipe);
1690         assert_fdi_rx_enabled(dev_priv, pipe);
1691
1692         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1693                 DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
1694                 return;
1695         }
1696         reg = TRANSCONF(pipe);
1697         val = I915_READ(reg);
1698         pipeconf_val = I915_READ(PIPECONF(pipe));
1699
1700         if (HAS_PCH_IBX(dev_priv->dev)) {
1701                 /*
1702                  * make the BPC in transcoder be consistent with
1703                  * that in pipeconf reg.
1704                  */
1705                 val &= ~PIPE_BPC_MASK;
1706                 val |= pipeconf_val & PIPE_BPC_MASK;
1707         }
1708
1709         val &= ~TRANS_INTERLACE_MASK;
1710         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1711                 if (HAS_PCH_IBX(dev_priv->dev) &&
1712                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1713                         val |= TRANS_LEGACY_INTERLACED_ILK;
1714                 else
1715                         val |= TRANS_INTERLACED;
1716         else
1717                 val |= TRANS_PROGRESSIVE;
1718
1719         I915_WRITE(reg, val | TRANS_ENABLE);
1720         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1721                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1722 }
1723
1724 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1725                                      enum pipe pipe)
1726 {
1727         int reg;
1728         u32 val;
1729
1730         /* FDI relies on the transcoder */
1731         assert_fdi_tx_disabled(dev_priv, pipe);
1732         assert_fdi_rx_disabled(dev_priv, pipe);
1733
1734         /* Ports must be off as well */
1735         assert_pch_ports_disabled(dev_priv, pipe);
1736
1737         reg = TRANSCONF(pipe);
1738         val = I915_READ(reg);
1739         val &= ~TRANS_ENABLE;
1740         I915_WRITE(reg, val);
1741         /* wait for PCH transcoder off, transcoder state */
1742         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1743                 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1744 }
1745
1746 /**
1747  * intel_enable_pipe - enable a pipe, asserting requirements
1748  * @dev_priv: i915 private structure
1749  * @pipe: pipe to enable
1750  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1751  *
1752  * Enable @pipe, making sure that various hardware specific requirements
1753  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1754  *
1755  * @pipe should be %PIPE_A or %PIPE_B.
1756  *
1757  * Will wait until the pipe is actually running (i.e. first vblank) before
1758  * returning.
1759  */
1760 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1761                               bool pch_port)
1762 {
1763         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1764                                                                       pipe);
1765         int reg;
1766         u32 val;
1767
1768         /*
1769          * A pipe without a PLL won't actually be able to drive bits from
1770          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1771          * need the check.
1772          */
1773         if (!HAS_PCH_SPLIT(dev_priv->dev))
1774                 assert_pll_enabled(dev_priv, pipe);
1775         else {
1776                 if (pch_port) {
1777                         /* if driving the PCH, we need FDI enabled */
1778                         assert_fdi_rx_pll_enabled(dev_priv, pipe);
1779                         assert_fdi_tx_pll_enabled(dev_priv, pipe);
1780                 }
1781                 /* FIXME: assert CPU port conditions for SNB+ */
1782         }
1783
1784         reg = PIPECONF(cpu_transcoder);
1785         val = I915_READ(reg);
1786         if (val & PIPECONF_ENABLE)
1787                 return;
1788
1789         I915_WRITE(reg, val | PIPECONF_ENABLE);
1790         intel_wait_for_vblank(dev_priv->dev, pipe);
1791 }
1792
1793 /**
1794  * intel_disable_pipe - disable a pipe, asserting requirements
1795  * @dev_priv: i915 private structure
1796  * @pipe: pipe to disable
1797  *
1798  * Disable @pipe, making sure that various hardware specific requirements
1799  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1800  *
1801  * @pipe should be %PIPE_A or %PIPE_B.
1802  *
1803  * Will wait until the pipe has shut down before returning.
1804  */
1805 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1806                                enum pipe pipe)
1807 {
1808         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1809                                                                       pipe);
1810         int reg;
1811         u32 val;
1812
1813         /*
1814          * Make sure planes won't keep trying to pump pixels to us,
1815          * or we might hang the display.
1816          */
1817         assert_planes_disabled(dev_priv, pipe);
1818
1819         /* Don't disable pipe A or pipe A PLLs if needed */
1820         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1821                 return;
1822
1823         reg = PIPECONF(cpu_transcoder);
1824         val = I915_READ(reg);
1825         if ((val & PIPECONF_ENABLE) == 0)
1826                 return;
1827
1828         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1829         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1830 }
1831
1832 /*
1833  * Plane regs are double buffered, going from enabled->disabled needs a
1834  * trigger in order to latch.  The display address reg provides this.
1835  */
1836 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1837                                       enum plane plane)
1838 {
1839         I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1840         I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1841 }
1842
1843 /**
1844  * intel_enable_plane - enable a display plane on a given pipe
1845  * @dev_priv: i915 private structure
1846  * @plane: plane to enable
1847  * @pipe: pipe being fed
1848  *
1849  * Enable @plane on @pipe, making sure that @pipe is running first.
1850  */
1851 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1852                                enum plane plane, enum pipe pipe)
1853 {
1854         int reg;
1855         u32 val;
1856
1857         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1858         assert_pipe_enabled(dev_priv, pipe);
1859
1860         reg = DSPCNTR(plane);
1861         val = I915_READ(reg);
1862         if (val & DISPLAY_PLANE_ENABLE)
1863                 return;
1864
1865         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1866         intel_flush_display_plane(dev_priv, plane);
1867         intel_wait_for_vblank(dev_priv->dev, pipe);
1868 }
1869
1870 /**
1871  * intel_disable_plane - disable a display plane
1872  * @dev_priv: i915 private structure
1873  * @plane: plane to disable
1874  * @pipe: pipe consuming the data
1875  *
1876  * Disable @plane; should be an independent operation.
1877  */
1878 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1879                                 enum plane plane, enum pipe pipe)
1880 {
1881         int reg;
1882         u32 val;
1883
1884         reg = DSPCNTR(plane);
1885         val = I915_READ(reg);
1886         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1887                 return;
1888
1889         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1890         intel_flush_display_plane(dev_priv, plane);
1891         intel_wait_for_vblank(dev_priv->dev, pipe);
1892 }
1893
1894 int
1895 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1896                            struct drm_i915_gem_object *obj,
1897                            struct intel_ring_buffer *pipelined)
1898 {
1899         struct drm_i915_private *dev_priv = dev->dev_private;
1900         u32 alignment;
1901         int ret;
1902
1903         switch (obj->tiling_mode) {
1904         case I915_TILING_NONE:
1905                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1906                         alignment = 128 * 1024;
1907                 else if (INTEL_INFO(dev)->gen >= 4)
1908                         alignment = 4 * 1024;
1909                 else
1910                         alignment = 64 * 1024;
1911                 break;
1912         case I915_TILING_X:
1913                 /* pin() will align the object as required by fence */
1914                 alignment = 0;
1915                 break;
1916         case I915_TILING_Y:
1917                 /* FIXME: Is this true? */
1918                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1919                 return -EINVAL;
1920         default:
1921                 BUG();
1922         }
1923
1924         dev_priv->mm.interruptible = false;
1925         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1926         if (ret)
1927                 goto err_interruptible;
1928
1929         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1930          * fence, whereas 965+ only requires a fence if using
1931          * framebuffer compression.  For simplicity, we always install
1932          * a fence as the cost is not that onerous.
1933          */
1934         ret = i915_gem_object_get_fence(obj);
1935         if (ret)
1936                 goto err_unpin;
1937
1938         i915_gem_object_pin_fence(obj);
1939
1940         dev_priv->mm.interruptible = true;
1941         return 0;
1942
1943 err_unpin:
1944         i915_gem_object_unpin(obj);
1945 err_interruptible:
1946         dev_priv->mm.interruptible = true;
1947         return ret;
1948 }
1949
1950 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1951 {
1952         i915_gem_object_unpin_fence(obj);
1953         i915_gem_object_unpin(obj);
1954 }
1955
1956 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1957  * is assumed to be a power-of-two. */
1958 static unsigned long gen4_compute_dspaddr_offset_xtiled(int *x, int *y,
1959                                                         unsigned int bpp,
1960                                                         unsigned int pitch)
1961 {
1962         int tile_rows, tiles;
1963
1964         tile_rows = *y / 8;
1965         *y %= 8;
1966         tiles = *x / (512/bpp);
1967         *x %= 512/bpp;
1968
1969         return tile_rows * pitch * 8 + tiles * 4096;
1970 }
1971
1972 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1973                              int x, int y)
1974 {
1975         struct drm_device *dev = crtc->dev;
1976         struct drm_i915_private *dev_priv = dev->dev_private;
1977         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1978         struct intel_framebuffer *intel_fb;
1979         struct drm_i915_gem_object *obj;
1980         int plane = intel_crtc->plane;
1981         unsigned long linear_offset;
1982         u32 dspcntr;
1983         u32 reg;
1984
1985         switch (plane) {
1986         case 0:
1987         case 1:
1988                 break;
1989         default:
1990                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1991                 return -EINVAL;
1992         }
1993
1994         intel_fb = to_intel_framebuffer(fb);
1995         obj = intel_fb->obj;
1996
1997         reg = DSPCNTR(plane);
1998         dspcntr = I915_READ(reg);
1999         /* Mask out pixel format bits in case we change it */
2000         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2001         switch (fb->bits_per_pixel) {
2002         case 8:
2003                 dspcntr |= DISPPLANE_8BPP;
2004                 break;
2005         case 16:
2006                 if (fb->depth == 15)
2007                         dspcntr |= DISPPLANE_15_16BPP;
2008                 else
2009                         dspcntr |= DISPPLANE_16BPP;
2010                 break;
2011         case 24:
2012         case 32:
2013                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2014                 break;
2015         default:
2016                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2017                 return -EINVAL;
2018         }
2019         if (INTEL_INFO(dev)->gen >= 4) {
2020                 if (obj->tiling_mode != I915_TILING_NONE)
2021                         dspcntr |= DISPPLANE_TILED;
2022                 else
2023                         dspcntr &= ~DISPPLANE_TILED;
2024         }
2025
2026         I915_WRITE(reg, dspcntr);
2027
2028         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2029
2030         if (INTEL_INFO(dev)->gen >= 4) {
2031                 intel_crtc->dspaddr_offset =
2032                         gen4_compute_dspaddr_offset_xtiled(&x, &y,
2033                                                            fb->bits_per_pixel / 8,
2034                                                            fb->pitches[0]);
2035                 linear_offset -= intel_crtc->dspaddr_offset;
2036         } else {
2037                 intel_crtc->dspaddr_offset = linear_offset;
2038         }
2039
2040         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2041                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2042         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2043         if (INTEL_INFO(dev)->gen >= 4) {
2044                 I915_MODIFY_DISPBASE(DSPSURF(plane),
2045                                      obj->gtt_offset + intel_crtc->dspaddr_offset);
2046                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2047                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2048         } else
2049                 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2050         POSTING_READ(reg);
2051
2052         return 0;
2053 }
2054
2055 static int ironlake_update_plane(struct drm_crtc *crtc,
2056                                  struct drm_framebuffer *fb, int x, int y)
2057 {
2058         struct drm_device *dev = crtc->dev;
2059         struct drm_i915_private *dev_priv = dev->dev_private;
2060         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2061         struct intel_framebuffer *intel_fb;
2062         struct drm_i915_gem_object *obj;
2063         int plane = intel_crtc->plane;
2064         unsigned long linear_offset;
2065         u32 dspcntr;
2066         u32 reg;
2067
2068         switch (plane) {
2069         case 0:
2070         case 1:
2071         case 2:
2072                 break;
2073         default:
2074                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2075                 return -EINVAL;
2076         }
2077
2078         intel_fb = to_intel_framebuffer(fb);
2079         obj = intel_fb->obj;
2080
2081         reg = DSPCNTR(plane);
2082         dspcntr = I915_READ(reg);
2083         /* Mask out pixel format bits in case we change it */
2084         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2085         switch (fb->bits_per_pixel) {
2086         case 8:
2087                 dspcntr |= DISPPLANE_8BPP;
2088                 break;
2089         case 16:
2090                 if (fb->depth != 16)
2091                         return -EINVAL;
2092
2093                 dspcntr |= DISPPLANE_16BPP;
2094                 break;
2095         case 24:
2096         case 32:
2097                 if (fb->depth == 24)
2098                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2099                 else if (fb->depth == 30)
2100                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2101                 else
2102                         return -EINVAL;
2103                 break;
2104         default:
2105                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2106                 return -EINVAL;
2107         }
2108
2109         if (obj->tiling_mode != I915_TILING_NONE)
2110                 dspcntr |= DISPPLANE_TILED;
2111         else
2112                 dspcntr &= ~DISPPLANE_TILED;
2113
2114         /* must disable */
2115         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2116
2117         I915_WRITE(reg, dspcntr);
2118
2119         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2120         intel_crtc->dspaddr_offset =
2121                 gen4_compute_dspaddr_offset_xtiled(&x, &y,
2122                                                    fb->bits_per_pixel / 8,
2123                                                    fb->pitches[0]);
2124         linear_offset -= intel_crtc->dspaddr_offset;
2125
2126         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2127                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2128         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2129         I915_MODIFY_DISPBASE(DSPSURF(plane),
2130                              obj->gtt_offset + intel_crtc->dspaddr_offset);
2131         I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2132         I915_WRITE(DSPLINOFF(plane), linear_offset);
2133         POSTING_READ(reg);
2134
2135         return 0;
2136 }
2137
2138 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2139 static int
2140 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2141                            int x, int y, enum mode_set_atomic state)
2142 {
2143         struct drm_device *dev = crtc->dev;
2144         struct drm_i915_private *dev_priv = dev->dev_private;
2145
2146         if (dev_priv->display.disable_fbc)
2147                 dev_priv->display.disable_fbc(dev);
2148         intel_increase_pllclock(crtc);
2149
2150         return dev_priv->display.update_plane(crtc, fb, x, y);
2151 }
2152
2153 static int
2154 intel_finish_fb(struct drm_framebuffer *old_fb)
2155 {
2156         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2157         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2158         bool was_interruptible = dev_priv->mm.interruptible;
2159         int ret;
2160
2161         wait_event(dev_priv->pending_flip_queue,
2162                    atomic_read(&dev_priv->mm.wedged) ||
2163                    atomic_read(&obj->pending_flip) == 0);
2164
2165         /* Big Hammer, we also need to ensure that any pending
2166          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2167          * current scanout is retired before unpinning the old
2168          * framebuffer.
2169          *
2170          * This should only fail upon a hung GPU, in which case we
2171          * can safely continue.
2172          */
2173         dev_priv->mm.interruptible = false;
2174         ret = i915_gem_object_finish_gpu(obj);
2175         dev_priv->mm.interruptible = was_interruptible;
2176
2177         return ret;
2178 }
2179
2180 static int
2181 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2182                     struct drm_framebuffer *fb)
2183 {
2184         struct drm_device *dev = crtc->dev;
2185         struct drm_i915_private *dev_priv = dev->dev_private;
2186         struct drm_i915_master_private *master_priv;
2187         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2188         struct drm_framebuffer *old_fb;
2189         int ret;
2190
2191         /* no fb bound */
2192         if (!fb) {
2193                 DRM_ERROR("No FB bound\n");
2194                 return 0;
2195         }
2196
2197         if(intel_crtc->plane > dev_priv->num_pipe) {
2198                 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2199                                 intel_crtc->plane,
2200                                 dev_priv->num_pipe);
2201                 return -EINVAL;
2202         }
2203
2204         mutex_lock(&dev->struct_mutex);
2205         ret = intel_pin_and_fence_fb_obj(dev,
2206                                          to_intel_framebuffer(fb)->obj,
2207                                          NULL);
2208         if (ret != 0) {
2209                 mutex_unlock(&dev->struct_mutex);
2210                 DRM_ERROR("pin & fence failed\n");
2211                 return ret;
2212         }
2213
2214         if (crtc->fb)
2215                 intel_finish_fb(crtc->fb);
2216
2217         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2218         if (ret) {
2219                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2220                 mutex_unlock(&dev->struct_mutex);
2221                 DRM_ERROR("failed to update base address\n");
2222                 return ret;
2223         }
2224
2225         old_fb = crtc->fb;
2226         crtc->fb = fb;
2227         crtc->x = x;
2228         crtc->y = y;
2229
2230         if (old_fb) {
2231                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2232                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2233         }
2234
2235         intel_update_fbc(dev);
2236         mutex_unlock(&dev->struct_mutex);
2237
2238         if (!dev->primary->master)
2239                 return 0;
2240
2241         master_priv = dev->primary->master->driver_priv;
2242         if (!master_priv->sarea_priv)
2243                 return 0;
2244
2245         if (intel_crtc->pipe) {
2246                 master_priv->sarea_priv->pipeB_x = x;
2247                 master_priv->sarea_priv->pipeB_y = y;
2248         } else {
2249                 master_priv->sarea_priv->pipeA_x = x;
2250                 master_priv->sarea_priv->pipeA_y = y;
2251         }
2252
2253         return 0;
2254 }
2255
2256 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2257 {
2258         struct drm_device *dev = crtc->dev;
2259         struct drm_i915_private *dev_priv = dev->dev_private;
2260         u32 dpa_ctl;
2261
2262         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2263         dpa_ctl = I915_READ(DP_A);
2264         dpa_ctl &= ~DP_PLL_FREQ_MASK;
2265
2266         if (clock < 200000) {
2267                 u32 temp;
2268                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2269                 /* workaround for 160Mhz:
2270                    1) program 0x4600c bits 15:0 = 0x8124
2271                    2) program 0x46010 bit 0 = 1
2272                    3) program 0x46034 bit 24 = 1
2273                    4) program 0x64000 bit 14 = 1
2274                    */
2275                 temp = I915_READ(0x4600c);
2276                 temp &= 0xffff0000;
2277                 I915_WRITE(0x4600c, temp | 0x8124);
2278
2279                 temp = I915_READ(0x46010);
2280                 I915_WRITE(0x46010, temp | 1);
2281
2282                 temp = I915_READ(0x46034);
2283                 I915_WRITE(0x46034, temp | (1 << 24));
2284         } else {
2285                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2286         }
2287         I915_WRITE(DP_A, dpa_ctl);
2288
2289         POSTING_READ(DP_A);
2290         udelay(500);
2291 }
2292
2293 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2294 {
2295         struct drm_device *dev = crtc->dev;
2296         struct drm_i915_private *dev_priv = dev->dev_private;
2297         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2298         int pipe = intel_crtc->pipe;
2299         u32 reg, temp;
2300
2301         /* enable normal train */
2302         reg = FDI_TX_CTL(pipe);
2303         temp = I915_READ(reg);
2304         if (IS_IVYBRIDGE(dev)) {
2305                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2306                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2307         } else {
2308                 temp &= ~FDI_LINK_TRAIN_NONE;
2309                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2310         }
2311         I915_WRITE(reg, temp);
2312
2313         reg = FDI_RX_CTL(pipe);
2314         temp = I915_READ(reg);
2315         if (HAS_PCH_CPT(dev)) {
2316                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2317                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2318         } else {
2319                 temp &= ~FDI_LINK_TRAIN_NONE;
2320                 temp |= FDI_LINK_TRAIN_NONE;
2321         }
2322         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2323
2324         /* wait one idle pattern time */
2325         POSTING_READ(reg);
2326         udelay(1000);
2327
2328         /* IVB wants error correction enabled */
2329         if (IS_IVYBRIDGE(dev))
2330                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2331                            FDI_FE_ERRC_ENABLE);
2332 }
2333
2334 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2335 {
2336         struct drm_i915_private *dev_priv = dev->dev_private;
2337         u32 flags = I915_READ(SOUTH_CHICKEN1);
2338
2339         flags |= FDI_PHASE_SYNC_OVR(pipe);
2340         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2341         flags |= FDI_PHASE_SYNC_EN(pipe);
2342         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2343         POSTING_READ(SOUTH_CHICKEN1);
2344 }
2345
2346 /* The FDI link training functions for ILK/Ibexpeak. */
2347 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2348 {
2349         struct drm_device *dev = crtc->dev;
2350         struct drm_i915_private *dev_priv = dev->dev_private;
2351         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2352         int pipe = intel_crtc->pipe;
2353         int plane = intel_crtc->plane;
2354         u32 reg, temp, tries;
2355
2356         /* FDI needs bits from pipe & plane first */
2357         assert_pipe_enabled(dev_priv, pipe);
2358         assert_plane_enabled(dev_priv, plane);
2359
2360         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2361            for train result */
2362         reg = FDI_RX_IMR(pipe);
2363         temp = I915_READ(reg);
2364         temp &= ~FDI_RX_SYMBOL_LOCK;
2365         temp &= ~FDI_RX_BIT_LOCK;
2366         I915_WRITE(reg, temp);
2367         I915_READ(reg);
2368         udelay(150);
2369
2370         /* enable CPU FDI TX and PCH FDI RX */
2371         reg = FDI_TX_CTL(pipe);
2372         temp = I915_READ(reg);
2373         temp &= ~(7 << 19);
2374         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2375         temp &= ~FDI_LINK_TRAIN_NONE;
2376         temp |= FDI_LINK_TRAIN_PATTERN_1;
2377         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2378
2379         reg = FDI_RX_CTL(pipe);
2380         temp = I915_READ(reg);
2381         temp &= ~FDI_LINK_TRAIN_NONE;
2382         temp |= FDI_LINK_TRAIN_PATTERN_1;
2383         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2384
2385         POSTING_READ(reg);
2386         udelay(150);
2387
2388         /* Ironlake workaround, enable clock pointer after FDI enable*/
2389         if (HAS_PCH_IBX(dev)) {
2390                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2391                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2392                            FDI_RX_PHASE_SYNC_POINTER_EN);
2393         }
2394
2395         reg = FDI_RX_IIR(pipe);
2396         for (tries = 0; tries < 5; tries++) {
2397                 temp = I915_READ(reg);
2398                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2399
2400                 if ((temp & FDI_RX_BIT_LOCK)) {
2401                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2402                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2403                         break;
2404                 }
2405         }
2406         if (tries == 5)
2407                 DRM_ERROR("FDI train 1 fail!\n");
2408
2409         /* Train 2 */
2410         reg = FDI_TX_CTL(pipe);
2411         temp = I915_READ(reg);
2412         temp &= ~FDI_LINK_TRAIN_NONE;
2413         temp |= FDI_LINK_TRAIN_PATTERN_2;
2414         I915_WRITE(reg, temp);
2415
2416         reg = FDI_RX_CTL(pipe);
2417         temp = I915_READ(reg);
2418         temp &= ~FDI_LINK_TRAIN_NONE;
2419         temp |= FDI_LINK_TRAIN_PATTERN_2;
2420         I915_WRITE(reg, temp);
2421
2422         POSTING_READ(reg);
2423         udelay(150);
2424
2425         reg = FDI_RX_IIR(pipe);
2426         for (tries = 0; tries < 5; tries++) {
2427                 temp = I915_READ(reg);
2428                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2429
2430                 if (temp & FDI_RX_SYMBOL_LOCK) {
2431                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2432                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2433                         break;
2434                 }
2435         }
2436         if (tries == 5)
2437                 DRM_ERROR("FDI train 2 fail!\n");
2438
2439         DRM_DEBUG_KMS("FDI train done\n");
2440
2441 }
2442
2443 static const int snb_b_fdi_train_param[] = {
2444         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2445         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2446         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2447         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2448 };
2449
2450 /* The FDI link training functions for SNB/Cougarpoint. */
2451 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2452 {
2453         struct drm_device *dev = crtc->dev;
2454         struct drm_i915_private *dev_priv = dev->dev_private;
2455         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2456         int pipe = intel_crtc->pipe;
2457         u32 reg, temp, i, retry;
2458
2459         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2460            for train result */
2461         reg = FDI_RX_IMR(pipe);
2462         temp = I915_READ(reg);
2463         temp &= ~FDI_RX_SYMBOL_LOCK;
2464         temp &= ~FDI_RX_BIT_LOCK;
2465         I915_WRITE(reg, temp);
2466
2467         POSTING_READ(reg);
2468         udelay(150);
2469
2470         /* enable CPU FDI TX and PCH FDI RX */
2471         reg = FDI_TX_CTL(pipe);
2472         temp = I915_READ(reg);
2473         temp &= ~(7 << 19);
2474         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2475         temp &= ~FDI_LINK_TRAIN_NONE;
2476         temp |= FDI_LINK_TRAIN_PATTERN_1;
2477         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2478         /* SNB-B */
2479         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2480         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2481
2482         I915_WRITE(FDI_RX_MISC(pipe),
2483                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2484
2485         reg = FDI_RX_CTL(pipe);
2486         temp = I915_READ(reg);
2487         if (HAS_PCH_CPT(dev)) {
2488                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2489                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2490         } else {
2491                 temp &= ~FDI_LINK_TRAIN_NONE;
2492                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2493         }
2494         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2495
2496         POSTING_READ(reg);
2497         udelay(150);
2498
2499         if (HAS_PCH_CPT(dev))
2500                 cpt_phase_pointer_enable(dev, pipe);
2501
2502         for (i = 0; i < 4; i++) {
2503                 reg = FDI_TX_CTL(pipe);
2504                 temp = I915_READ(reg);
2505                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2506                 temp |= snb_b_fdi_train_param[i];
2507                 I915_WRITE(reg, temp);
2508
2509                 POSTING_READ(reg);
2510                 udelay(500);
2511
2512                 for (retry = 0; retry < 5; retry++) {
2513                         reg = FDI_RX_IIR(pipe);
2514                         temp = I915_READ(reg);
2515                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2516                         if (temp & FDI_RX_BIT_LOCK) {
2517                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2518                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2519                                 break;
2520                         }
2521                         udelay(50);
2522                 }
2523                 if (retry < 5)
2524                         break;
2525         }
2526         if (i == 4)
2527                 DRM_ERROR("FDI train 1 fail!\n");
2528
2529         /* Train 2 */
2530         reg = FDI_TX_CTL(pipe);
2531         temp = I915_READ(reg);
2532         temp &= ~FDI_LINK_TRAIN_NONE;
2533         temp |= FDI_LINK_TRAIN_PATTERN_2;
2534         if (IS_GEN6(dev)) {
2535                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2536                 /* SNB-B */
2537                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2538         }
2539         I915_WRITE(reg, temp);
2540
2541         reg = FDI_RX_CTL(pipe);
2542         temp = I915_READ(reg);
2543         if (HAS_PCH_CPT(dev)) {
2544                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2545                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2546         } else {
2547                 temp &= ~FDI_LINK_TRAIN_NONE;
2548                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2549         }
2550         I915_WRITE(reg, temp);
2551
2552         POSTING_READ(reg);
2553         udelay(150);
2554
2555         for (i = 0; i < 4; i++) {
2556                 reg = FDI_TX_CTL(pipe);
2557                 temp = I915_READ(reg);
2558                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2559                 temp |= snb_b_fdi_train_param[i];
2560                 I915_WRITE(reg, temp);
2561
2562                 POSTING_READ(reg);
2563                 udelay(500);
2564
2565                 for (retry = 0; retry < 5; retry++) {
2566                         reg = FDI_RX_IIR(pipe);
2567                         temp = I915_READ(reg);
2568                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2569                         if (temp & FDI_RX_SYMBOL_LOCK) {
2570                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2571                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2572                                 break;
2573                         }
2574                         udelay(50);
2575                 }
2576                 if (retry < 5)
2577                         break;
2578         }
2579         if (i == 4)
2580                 DRM_ERROR("FDI train 2 fail!\n");
2581
2582         DRM_DEBUG_KMS("FDI train done.\n");
2583 }
2584
2585 /* Manual link training for Ivy Bridge A0 parts */
2586 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2587 {
2588         struct drm_device *dev = crtc->dev;
2589         struct drm_i915_private *dev_priv = dev->dev_private;
2590         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2591         int pipe = intel_crtc->pipe;
2592         u32 reg, temp, i;
2593
2594         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2595            for train result */
2596         reg = FDI_RX_IMR(pipe);
2597         temp = I915_READ(reg);
2598         temp &= ~FDI_RX_SYMBOL_LOCK;
2599         temp &= ~FDI_RX_BIT_LOCK;
2600         I915_WRITE(reg, temp);
2601
2602         POSTING_READ(reg);
2603         udelay(150);
2604
2605         /* enable CPU FDI TX and PCH FDI RX */
2606         reg = FDI_TX_CTL(pipe);
2607         temp = I915_READ(reg);
2608         temp &= ~(7 << 19);
2609         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2610         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2611         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2612         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2613         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2614         temp |= FDI_COMPOSITE_SYNC;
2615         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2616
2617         I915_WRITE(FDI_RX_MISC(pipe),
2618                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2619
2620         reg = FDI_RX_CTL(pipe);
2621         temp = I915_READ(reg);
2622         temp &= ~FDI_LINK_TRAIN_AUTO;
2623         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2624         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2625         temp |= FDI_COMPOSITE_SYNC;
2626         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2627
2628         POSTING_READ(reg);
2629         udelay(150);
2630
2631         if (HAS_PCH_CPT(dev))
2632                 cpt_phase_pointer_enable(dev, pipe);
2633
2634         for (i = 0; i < 4; i++) {
2635                 reg = FDI_TX_CTL(pipe);
2636                 temp = I915_READ(reg);
2637                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2638                 temp |= snb_b_fdi_train_param[i];
2639                 I915_WRITE(reg, temp);
2640
2641                 POSTING_READ(reg);
2642                 udelay(500);
2643
2644                 reg = FDI_RX_IIR(pipe);
2645                 temp = I915_READ(reg);
2646                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2647
2648                 if (temp & FDI_RX_BIT_LOCK ||
2649                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2650                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2651                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2652                         break;
2653                 }
2654         }
2655         if (i == 4)
2656                 DRM_ERROR("FDI train 1 fail!\n");
2657
2658         /* Train 2 */
2659         reg = FDI_TX_CTL(pipe);
2660         temp = I915_READ(reg);
2661         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2662         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2663         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2664         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2665         I915_WRITE(reg, temp);
2666
2667         reg = FDI_RX_CTL(pipe);
2668         temp = I915_READ(reg);
2669         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2670         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2671         I915_WRITE(reg, temp);
2672
2673         POSTING_READ(reg);
2674         udelay(150);
2675
2676         for (i = 0; i < 4; i++) {
2677                 reg = FDI_TX_CTL(pipe);
2678                 temp = I915_READ(reg);
2679                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2680                 temp |= snb_b_fdi_train_param[i];
2681                 I915_WRITE(reg, temp);
2682
2683                 POSTING_READ(reg);
2684                 udelay(500);
2685
2686                 reg = FDI_RX_IIR(pipe);
2687                 temp = I915_READ(reg);
2688                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2689
2690                 if (temp & FDI_RX_SYMBOL_LOCK) {
2691                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2692                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2693                         break;
2694                 }
2695         }
2696         if (i == 4)
2697                 DRM_ERROR("FDI train 2 fail!\n");
2698
2699         DRM_DEBUG_KMS("FDI train done.\n");
2700 }
2701
2702 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2703 {
2704         struct drm_device *dev = intel_crtc->base.dev;
2705         struct drm_i915_private *dev_priv = dev->dev_private;
2706         int pipe = intel_crtc->pipe;
2707         u32 reg, temp;
2708
2709
2710         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2711         reg = FDI_RX_CTL(pipe);
2712         temp = I915_READ(reg);
2713         temp &= ~((0x7 << 19) | (0x7 << 16));
2714         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2715         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2716         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2717
2718         POSTING_READ(reg);
2719         udelay(200);
2720
2721         /* Switch from Rawclk to PCDclk */
2722         temp = I915_READ(reg);
2723         I915_WRITE(reg, temp | FDI_PCDCLK);
2724
2725         POSTING_READ(reg);
2726         udelay(200);
2727
2728         /* On Haswell, the PLL configuration for ports and pipes is handled
2729          * separately, as part of DDI setup */
2730         if (!IS_HASWELL(dev)) {
2731                 /* Enable CPU FDI TX PLL, always on for Ironlake */
2732                 reg = FDI_TX_CTL(pipe);
2733                 temp = I915_READ(reg);
2734                 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2735                         I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2736
2737                         POSTING_READ(reg);
2738                         udelay(100);
2739                 }
2740         }
2741 }
2742
2743 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2744 {
2745         struct drm_device *dev = intel_crtc->base.dev;
2746         struct drm_i915_private *dev_priv = dev->dev_private;
2747         int pipe = intel_crtc->pipe;
2748         u32 reg, temp;
2749
2750         /* Switch from PCDclk to Rawclk */
2751         reg = FDI_RX_CTL(pipe);
2752         temp = I915_READ(reg);
2753         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2754
2755         /* Disable CPU FDI TX PLL */
2756         reg = FDI_TX_CTL(pipe);
2757         temp = I915_READ(reg);
2758         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2759
2760         POSTING_READ(reg);
2761         udelay(100);
2762
2763         reg = FDI_RX_CTL(pipe);
2764         temp = I915_READ(reg);
2765         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2766
2767         /* Wait for the clocks to turn off. */
2768         POSTING_READ(reg);
2769         udelay(100);
2770 }
2771
2772 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2773 {
2774         struct drm_i915_private *dev_priv = dev->dev_private;
2775         u32 flags = I915_READ(SOUTH_CHICKEN1);
2776
2777         flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2778         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2779         flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2780         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2781         POSTING_READ(SOUTH_CHICKEN1);
2782 }
2783 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2784 {
2785         struct drm_device *dev = crtc->dev;
2786         struct drm_i915_private *dev_priv = dev->dev_private;
2787         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2788         int pipe = intel_crtc->pipe;
2789         u32 reg, temp;
2790
2791         /* disable CPU FDI tx and PCH FDI rx */
2792         reg = FDI_TX_CTL(pipe);
2793         temp = I915_READ(reg);
2794         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2795         POSTING_READ(reg);
2796
2797         reg = FDI_RX_CTL(pipe);
2798         temp = I915_READ(reg);
2799         temp &= ~(0x7 << 16);
2800         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2801         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2802
2803         POSTING_READ(reg);
2804         udelay(100);
2805
2806         /* Ironlake workaround, disable clock pointer after downing FDI */
2807         if (HAS_PCH_IBX(dev)) {
2808                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2809                 I915_WRITE(FDI_RX_CHICKEN(pipe),
2810                            I915_READ(FDI_RX_CHICKEN(pipe) &
2811                                      ~FDI_RX_PHASE_SYNC_POINTER_EN));
2812         } else if (HAS_PCH_CPT(dev)) {
2813                 cpt_phase_pointer_disable(dev, pipe);
2814         }
2815
2816         /* still set train pattern 1 */
2817         reg = FDI_TX_CTL(pipe);
2818         temp = I915_READ(reg);
2819         temp &= ~FDI_LINK_TRAIN_NONE;
2820         temp |= FDI_LINK_TRAIN_PATTERN_1;
2821         I915_WRITE(reg, temp);
2822
2823         reg = FDI_RX_CTL(pipe);
2824         temp = I915_READ(reg);
2825         if (HAS_PCH_CPT(dev)) {
2826                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2827                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2828         } else {
2829                 temp &= ~FDI_LINK_TRAIN_NONE;
2830                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2831         }
2832         /* BPC in FDI rx is consistent with that in PIPECONF */
2833         temp &= ~(0x07 << 16);
2834         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2835         I915_WRITE(reg, temp);
2836
2837         POSTING_READ(reg);
2838         udelay(100);
2839 }
2840
2841 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2842 {
2843         struct drm_device *dev = crtc->dev;
2844         struct drm_i915_private *dev_priv = dev->dev_private;
2845         unsigned long flags;
2846         bool pending;
2847
2848         if (atomic_read(&dev_priv->mm.wedged))
2849                 return false;
2850
2851         spin_lock_irqsave(&dev->event_lock, flags);
2852         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2853         spin_unlock_irqrestore(&dev->event_lock, flags);
2854
2855         return pending;
2856 }
2857
2858 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2859 {
2860         struct drm_device *dev = crtc->dev;
2861         struct drm_i915_private *dev_priv = dev->dev_private;
2862
2863         if (crtc->fb == NULL)
2864                 return;
2865
2866         wait_event(dev_priv->pending_flip_queue,
2867                    !intel_crtc_has_pending_flip(crtc));
2868
2869         mutex_lock(&dev->struct_mutex);
2870         intel_finish_fb(crtc->fb);
2871         mutex_unlock(&dev->struct_mutex);
2872 }
2873
2874 static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
2875 {
2876         struct drm_device *dev = crtc->dev;
2877         struct intel_encoder *intel_encoder;
2878
2879         /*
2880          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2881          * must be driven by its own crtc; no sharing is possible.
2882          */
2883         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2884                 switch (intel_encoder->type) {
2885                 case INTEL_OUTPUT_EDP:
2886                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
2887                                 return false;
2888                         continue;
2889                 }
2890         }
2891
2892         return true;
2893 }
2894
2895 static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
2896 {
2897         return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
2898 }
2899
2900 /* Program iCLKIP clock to the desired frequency */
2901 static void lpt_program_iclkip(struct drm_crtc *crtc)
2902 {
2903         struct drm_device *dev = crtc->dev;
2904         struct drm_i915_private *dev_priv = dev->dev_private;
2905         u32 divsel, phaseinc, auxdiv, phasedir = 0;
2906         u32 temp;
2907
2908         /* It is necessary to ungate the pixclk gate prior to programming
2909          * the divisors, and gate it back when it is done.
2910          */
2911         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2912
2913         /* Disable SSCCTL */
2914         intel_sbi_write(dev_priv, SBI_SSCCTL6,
2915                                 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
2916                                         SBI_SSCCTL_DISABLE);
2917
2918         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2919         if (crtc->mode.clock == 20000) {
2920                 auxdiv = 1;
2921                 divsel = 0x41;
2922                 phaseinc = 0x20;
2923         } else {
2924                 /* The iCLK virtual clock root frequency is in MHz,
2925                  * but the crtc->mode.clock in in KHz. To get the divisors,
2926                  * it is necessary to divide one by another, so we
2927                  * convert the virtual clock precision to KHz here for higher
2928                  * precision.
2929                  */
2930                 u32 iclk_virtual_root_freq = 172800 * 1000;
2931                 u32 iclk_pi_range = 64;
2932                 u32 desired_divisor, msb_divisor_value, pi_value;
2933
2934                 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2935                 msb_divisor_value = desired_divisor / iclk_pi_range;
2936                 pi_value = desired_divisor % iclk_pi_range;
2937
2938                 auxdiv = 0;
2939                 divsel = msb_divisor_value - 2;
2940                 phaseinc = pi_value;
2941         }
2942
2943         /* This should not happen with any sane values */
2944         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2945                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2946         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2947                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2948
2949         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2950                         crtc->mode.clock,
2951                         auxdiv,
2952                         divsel,
2953                         phasedir,
2954                         phaseinc);
2955
2956         /* Program SSCDIVINTPHASE6 */
2957         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
2958         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2959         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2960         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2961         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2962         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2963         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2964
2965         intel_sbi_write(dev_priv,
2966                         SBI_SSCDIVINTPHASE6,
2967                         temp);
2968
2969         /* Program SSCAUXDIV */
2970         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
2971         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2972         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2973         intel_sbi_write(dev_priv,
2974                         SBI_SSCAUXDIV6,
2975                         temp);
2976
2977
2978         /* Enable modulator and associated divider */
2979         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
2980         temp &= ~SBI_SSCCTL_DISABLE;
2981         intel_sbi_write(dev_priv,
2982                         SBI_SSCCTL6,
2983                         temp);
2984
2985         /* Wait for initialization time */
2986         udelay(24);
2987
2988         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2989 }
2990
2991 /*
2992  * Enable PCH resources required for PCH ports:
2993  *   - PCH PLLs
2994  *   - FDI training & RX/TX
2995  *   - update transcoder timings
2996  *   - DP transcoding bits
2997  *   - transcoder
2998  */
2999 static void ironlake_pch_enable(struct drm_crtc *crtc)
3000 {
3001         struct drm_device *dev = crtc->dev;
3002         struct drm_i915_private *dev_priv = dev->dev_private;
3003         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3004         int pipe = intel_crtc->pipe;
3005         u32 reg, temp;
3006
3007         assert_transcoder_disabled(dev_priv, pipe);
3008
3009         /* Write the TU size bits before fdi link training, so that error
3010          * detection works. */
3011         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3012                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3013
3014         /* For PCH output, training FDI link */
3015         dev_priv->display.fdi_link_train(crtc);
3016
3017         intel_enable_pch_pll(intel_crtc);
3018
3019         if (HAS_PCH_LPT(dev)) {
3020                 DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
3021                 lpt_program_iclkip(crtc);
3022         } else if (HAS_PCH_CPT(dev)) {
3023                 u32 sel;
3024
3025                 temp = I915_READ(PCH_DPLL_SEL);
3026                 switch (pipe) {
3027                 default:
3028                 case 0:
3029                         temp |= TRANSA_DPLL_ENABLE;
3030                         sel = TRANSA_DPLLB_SEL;
3031                         break;
3032                 case 1:
3033                         temp |= TRANSB_DPLL_ENABLE;
3034                         sel = TRANSB_DPLLB_SEL;
3035                         break;
3036                 case 2:
3037                         temp |= TRANSC_DPLL_ENABLE;
3038                         sel = TRANSC_DPLLB_SEL;
3039                         break;
3040                 }
3041                 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3042                         temp |= sel;
3043                 else
3044                         temp &= ~sel;
3045                 I915_WRITE(PCH_DPLL_SEL, temp);
3046         }
3047
3048         /* set transcoder timing, panel must allow it */
3049         assert_panel_unlocked(dev_priv, pipe);
3050         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3051         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3052         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
3053
3054         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3055         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3056         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
3057         I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));
3058
3059         if (!IS_HASWELL(dev))
3060                 intel_fdi_normal_train(crtc);
3061
3062         /* For PCH DP, enable TRANS_DP_CTL */
3063         if (HAS_PCH_CPT(dev) &&
3064             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3065              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3066                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
3067                 reg = TRANS_DP_CTL(pipe);
3068                 temp = I915_READ(reg);
3069                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3070                           TRANS_DP_SYNC_MASK |
3071                           TRANS_DP_BPC_MASK);
3072                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3073                          TRANS_DP_ENH_FRAMING);
3074                 temp |= bpc << 9; /* same format but at 11:9 */
3075
3076                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3077                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3078                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3079                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3080
3081                 switch (intel_trans_dp_port_sel(crtc)) {
3082                 case PCH_DP_B:
3083                         temp |= TRANS_DP_PORT_SEL_B;
3084                         break;
3085                 case PCH_DP_C:
3086                         temp |= TRANS_DP_PORT_SEL_C;
3087                         break;
3088                 case PCH_DP_D:
3089                         temp |= TRANS_DP_PORT_SEL_D;
3090                         break;
3091                 default:
3092                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
3093                         temp |= TRANS_DP_PORT_SEL_B;
3094                         break;
3095                 }
3096
3097                 I915_WRITE(reg, temp);
3098         }
3099
3100         intel_enable_transcoder(dev_priv, pipe);
3101 }
3102
3103 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3104 {
3105         struct intel_pch_pll *pll = intel_crtc->pch_pll;
3106
3107         if (pll == NULL)
3108                 return;
3109
3110         if (pll->refcount == 0) {
3111                 WARN(1, "bad PCH PLL refcount\n");
3112                 return;
3113         }
3114
3115         --pll->refcount;
3116         intel_crtc->pch_pll = NULL;
3117 }
3118
3119 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3120 {
3121         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3122         struct intel_pch_pll *pll;
3123         int i;
3124
3125         pll = intel_crtc->pch_pll;
3126         if (pll) {
3127                 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3128                               intel_crtc->base.base.id, pll->pll_reg);
3129                 goto prepare;
3130         }
3131
3132         if (HAS_PCH_IBX(dev_priv->dev)) {
3133                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3134                 i = intel_crtc->pipe;
3135                 pll = &dev_priv->pch_plls[i];
3136
3137                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3138                               intel_crtc->base.base.id, pll->pll_reg);
3139
3140                 goto found;
3141         }
3142
3143         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3144                 pll = &dev_priv->pch_plls[i];
3145
3146                 /* Only want to check enabled timings first */
3147                 if (pll->refcount == 0)
3148                         continue;
3149
3150                 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3151                     fp == I915_READ(pll->fp0_reg)) {
3152                         DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3153                                       intel_crtc->base.base.id,
3154                                       pll->pll_reg, pll->refcount, pll->active);
3155
3156                         goto found;
3157                 }
3158         }
3159
3160         /* Ok no matching timings, maybe there's a free one? */
3161         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3162                 pll = &dev_priv->pch_plls[i];
3163                 if (pll->refcount == 0) {
3164                         DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3165                                       intel_crtc->base.base.id, pll->pll_reg);
3166                         goto found;
3167                 }
3168         }
3169
3170         return NULL;
3171
3172 found:
3173         intel_crtc->pch_pll = pll;
3174         pll->refcount++;
3175         DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3176 prepare: /* separate function? */
3177         DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3178
3179         /* Wait for the clocks to stabilize before rewriting the regs */
3180         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3181         POSTING_READ(pll->pll_reg);
3182         udelay(150);
3183
3184         I915_WRITE(pll->fp0_reg, fp);
3185         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3186         pll->on = false;
3187         return pll;
3188 }
3189
3190 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3191 {
3192         struct drm_i915_private *dev_priv = dev->dev_private;
3193         int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3194         u32 temp;
3195
3196         temp = I915_READ(dslreg);
3197         udelay(500);
3198         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3199                 /* Without this, mode sets may fail silently on FDI */
3200                 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3201                 udelay(250);
3202                 I915_WRITE(tc2reg, 0);
3203                 if (wait_for(I915_READ(dslreg) != temp, 5))
3204                         DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3205         }
3206 }
3207
3208 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3209 {
3210         struct drm_device *dev = crtc->dev;
3211         struct drm_i915_private *dev_priv = dev->dev_private;
3212         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3213         struct intel_encoder *encoder;
3214         int pipe = intel_crtc->pipe;
3215         int plane = intel_crtc->plane;
3216         u32 temp;
3217         bool is_pch_port;
3218
3219         WARN_ON(!crtc->enabled);
3220
3221         if (intel_crtc->active)
3222                 return;
3223
3224         intel_crtc->active = true;
3225         intel_update_watermarks(dev);
3226
3227         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3228                 temp = I915_READ(PCH_LVDS);
3229                 if ((temp & LVDS_PORT_EN) == 0)
3230                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3231         }
3232
3233         is_pch_port = ironlake_crtc_driving_pch(crtc);
3234
3235         if (is_pch_port) {
3236                 /* Note: FDI PLL enabling _must_ be done before we enable the
3237                  * cpu pipes, hence this is separate from all the other fdi/pch
3238                  * enabling. */
3239                 ironlake_fdi_pll_enable(intel_crtc);
3240         } else {
3241                 assert_fdi_tx_disabled(dev_priv, pipe);
3242                 assert_fdi_rx_disabled(dev_priv, pipe);
3243         }
3244
3245         for_each_encoder_on_crtc(dev, crtc, encoder)
3246                 if (encoder->pre_enable)
3247                         encoder->pre_enable(encoder);
3248
3249         /* Enable panel fitting for LVDS */
3250         if (dev_priv->pch_pf_size &&
3251             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3252                 /* Force use of hard-coded filter coefficients
3253                  * as some pre-programmed values are broken,
3254                  * e.g. x201.
3255                  */
3256                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3257                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3258                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3259         }
3260
3261         /*
3262          * On ILK+ LUT must be loaded before the pipe is running but with
3263          * clocks enabled
3264          */
3265         intel_crtc_load_lut(crtc);
3266
3267         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3268         intel_enable_plane(dev_priv, plane, pipe);
3269
3270         if (is_pch_port)
3271                 ironlake_pch_enable(crtc);
3272
3273         mutex_lock(&dev->struct_mutex);
3274         intel_update_fbc(dev);
3275         mutex_unlock(&dev->struct_mutex);
3276
3277         intel_crtc_update_cursor(crtc, true);
3278
3279         for_each_encoder_on_crtc(dev, crtc, encoder)
3280                 encoder->enable(encoder);
3281
3282         if (HAS_PCH_CPT(dev))
3283                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3284
3285         /*
3286          * There seems to be a race in PCH platform hw (at least on some
3287          * outputs) where an enabled pipe still completes any pageflip right
3288          * away (as if the pipe is off) instead of waiting for vblank. As soon
3289          * as the first vblank happend, everything works as expected. Hence just
3290          * wait for one vblank before returning to avoid strange things
3291          * happening.
3292          */
3293         intel_wait_for_vblank(dev, intel_crtc->pipe);
3294 }
3295
3296 static void haswell_crtc_enable(struct drm_crtc *crtc)
3297 {
3298         struct drm_device *dev = crtc->dev;
3299         struct drm_i915_private *dev_priv = dev->dev_private;
3300         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3301         struct intel_encoder *encoder;
3302         int pipe = intel_crtc->pipe;
3303         int plane = intel_crtc->plane;
3304         bool is_pch_port;
3305
3306         WARN_ON(!crtc->enabled);
3307
3308         if (intel_crtc->active)
3309                 return;
3310
3311         intel_crtc->active = true;
3312         intel_update_watermarks(dev);
3313
3314         is_pch_port = haswell_crtc_driving_pch(crtc);
3315
3316         if (is_pch_port)
3317                 ironlake_fdi_pll_enable(intel_crtc);
3318
3319         for_each_encoder_on_crtc(dev, crtc, encoder)
3320                 if (encoder->pre_enable)
3321                         encoder->pre_enable(encoder);
3322
3323         intel_ddi_enable_pipe_clock(intel_crtc);
3324
3325         /* Enable panel fitting for eDP */
3326         if (dev_priv->pch_pf_size && HAS_eDP) {
3327                 /* Force use of hard-coded filter coefficients
3328                  * as some pre-programmed values are broken,
3329                  * e.g. x201.
3330                  */
3331                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3332                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3333                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3334         }
3335
3336         /*
3337          * On ILK+ LUT must be loaded before the pipe is running but with
3338          * clocks enabled
3339          */
3340         intel_crtc_load_lut(crtc);
3341
3342         intel_ddi_set_pipe_settings(crtc);
3343         intel_ddi_enable_pipe_func(crtc);
3344
3345         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3346         intel_enable_plane(dev_priv, plane, pipe);
3347
3348         if (is_pch_port)
3349                 ironlake_pch_enable(crtc);
3350
3351         mutex_lock(&dev->struct_mutex);
3352         intel_update_fbc(dev);
3353         mutex_unlock(&dev->struct_mutex);
3354
3355         intel_crtc_update_cursor(crtc, true);
3356
3357         for_each_encoder_on_crtc(dev, crtc, encoder)
3358                 encoder->enable(encoder);
3359
3360         /*
3361          * There seems to be a race in PCH platform hw (at least on some
3362          * outputs) where an enabled pipe still completes any pageflip right
3363          * away (as if the pipe is off) instead of waiting for vblank. As soon
3364          * as the first vblank happend, everything works as expected. Hence just
3365          * wait for one vblank before returning to avoid strange things
3366          * happening.
3367          */
3368         intel_wait_for_vblank(dev, intel_crtc->pipe);
3369 }
3370
3371 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3372 {
3373         struct drm_device *dev = crtc->dev;
3374         struct drm_i915_private *dev_priv = dev->dev_private;
3375         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3376         struct intel_encoder *encoder;
3377         int pipe = intel_crtc->pipe;
3378         int plane = intel_crtc->plane;
3379         u32 reg, temp;
3380
3381
3382         if (!intel_crtc->active)
3383                 return;
3384
3385         for_each_encoder_on_crtc(dev, crtc, encoder)
3386                 encoder->disable(encoder);
3387
3388         intel_crtc_wait_for_pending_flips(crtc);
3389         drm_vblank_off(dev, pipe);
3390         intel_crtc_update_cursor(crtc, false);
3391
3392         intel_disable_plane(dev_priv, plane, pipe);
3393
3394         if (dev_priv->cfb_plane == plane)
3395                 intel_disable_fbc(dev);
3396
3397         intel_disable_pipe(dev_priv, pipe);
3398
3399         /* Disable PF */
3400         I915_WRITE(PF_CTL(pipe), 0);
3401         I915_WRITE(PF_WIN_SZ(pipe), 0);
3402
3403         for_each_encoder_on_crtc(dev, crtc, encoder)
3404                 if (encoder->post_disable)
3405                         encoder->post_disable(encoder);
3406
3407         ironlake_fdi_disable(crtc);
3408
3409         intel_disable_transcoder(dev_priv, pipe);
3410
3411         if (HAS_PCH_CPT(dev)) {
3412                 /* disable TRANS_DP_CTL */
3413                 reg = TRANS_DP_CTL(pipe);
3414                 temp = I915_READ(reg);
3415                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3416                 temp |= TRANS_DP_PORT_SEL_NONE;
3417                 I915_WRITE(reg, temp);
3418
3419                 /* disable DPLL_SEL */
3420                 temp = I915_READ(PCH_DPLL_SEL);
3421                 switch (pipe) {
3422                 case 0:
3423                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3424                         break;
3425                 case 1:
3426                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3427                         break;
3428                 case 2:
3429                         /* C shares PLL A or B */
3430                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3431                         break;
3432                 default:
3433                         BUG(); /* wtf */
3434                 }
3435                 I915_WRITE(PCH_DPLL_SEL, temp);
3436         }
3437
3438         /* disable PCH DPLL */
3439         intel_disable_pch_pll(intel_crtc);
3440
3441         ironlake_fdi_pll_disable(intel_crtc);
3442
3443         intel_crtc->active = false;
3444         intel_update_watermarks(dev);
3445
3446         mutex_lock(&dev->struct_mutex);
3447         intel_update_fbc(dev);
3448         mutex_unlock(&dev->struct_mutex);
3449 }
3450
3451 static void haswell_crtc_disable(struct drm_crtc *crtc)
3452 {
3453         struct drm_device *dev = crtc->dev;
3454         struct drm_i915_private *dev_priv = dev->dev_private;
3455         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3456         struct intel_encoder *encoder;
3457         int pipe = intel_crtc->pipe;
3458         int plane = intel_crtc->plane;
3459         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3460         bool is_pch_port;
3461
3462         if (!intel_crtc->active)
3463                 return;
3464
3465         is_pch_port = haswell_crtc_driving_pch(crtc);
3466
3467         for_each_encoder_on_crtc(dev, crtc, encoder)
3468                 encoder->disable(encoder);
3469
3470         intel_crtc_wait_for_pending_flips(crtc);
3471         drm_vblank_off(dev, pipe);
3472         intel_crtc_update_cursor(crtc, false);
3473
3474         intel_disable_plane(dev_priv, plane, pipe);
3475
3476         if (dev_priv->cfb_plane == plane)
3477                 intel_disable_fbc(dev);
3478
3479         intel_disable_pipe(dev_priv, pipe);
3480
3481         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3482
3483         /* Disable PF */
3484         I915_WRITE(PF_CTL(pipe), 0);
3485         I915_WRITE(PF_WIN_SZ(pipe), 0);
3486
3487         intel_ddi_disable_pipe_clock(intel_crtc);
3488
3489         for_each_encoder_on_crtc(dev, crtc, encoder)
3490                 if (encoder->post_disable)
3491                         encoder->post_disable(encoder);
3492
3493         if (is_pch_port) {
3494                 ironlake_fdi_disable(crtc);
3495                 intel_disable_transcoder(dev_priv, pipe);
3496                 intel_disable_pch_pll(intel_crtc);
3497                 ironlake_fdi_pll_disable(intel_crtc);
3498         }
3499
3500         intel_crtc->active = false;
3501         intel_update_watermarks(dev);
3502
3503         mutex_lock(&dev->struct_mutex);
3504         intel_update_fbc(dev);
3505         mutex_unlock(&dev->struct_mutex);
3506 }
3507
3508 static void ironlake_crtc_off(struct drm_crtc *crtc)
3509 {
3510         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3511         intel_put_pch_pll(intel_crtc);
3512 }
3513
3514 static void haswell_crtc_off(struct drm_crtc *crtc)
3515 {
3516         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3517
3518         /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3519          * start using it. */
3520         intel_crtc->cpu_transcoder = intel_crtc->pipe;
3521
3522         intel_ddi_put_crtc_pll(crtc);
3523 }
3524
3525 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3526 {
3527         if (!enable && intel_crtc->overlay) {
3528                 struct drm_device *dev = intel_crtc->base.dev;
3529                 struct drm_i915_private *dev_priv = dev->dev_private;
3530
3531                 mutex_lock(&dev->struct_mutex);
3532                 dev_priv->mm.interruptible = false;
3533                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3534                 dev_priv->mm.interruptible = true;
3535                 mutex_unlock(&dev->struct_mutex);
3536         }
3537
3538         /* Let userspace switch the overlay on again. In most cases userspace
3539          * has to recompute where to put it anyway.
3540          */
3541 }
3542
3543 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3544 {
3545         struct drm_device *dev = crtc->dev;
3546         struct drm_i915_private *dev_priv = dev->dev_private;
3547         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3548         struct intel_encoder *encoder;
3549         int pipe = intel_crtc->pipe;
3550         int plane = intel_crtc->plane;
3551
3552         WARN_ON(!crtc->enabled);
3553
3554         if (intel_crtc->active)
3555                 return;
3556
3557         intel_crtc->active = true;
3558         intel_update_watermarks(dev);
3559
3560         intel_enable_pll(dev_priv, pipe);
3561         intel_enable_pipe(dev_priv, pipe, false);
3562         intel_enable_plane(dev_priv, plane, pipe);
3563
3564         intel_crtc_load_lut(crtc);
3565         intel_update_fbc(dev);
3566
3567         /* Give the overlay scaler a chance to enable if it's on this pipe */
3568         intel_crtc_dpms_overlay(intel_crtc, true);
3569         intel_crtc_update_cursor(crtc, true);
3570
3571         for_each_encoder_on_crtc(dev, crtc, encoder)
3572                 encoder->enable(encoder);
3573 }
3574
3575 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3576 {
3577         struct drm_device *dev = crtc->dev;
3578         struct drm_i915_private *dev_priv = dev->dev_private;
3579         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3580         struct intel_encoder *encoder;
3581         int pipe = intel_crtc->pipe;
3582         int plane = intel_crtc->plane;
3583
3584
3585         if (!intel_crtc->active)
3586                 return;
3587
3588         for_each_encoder_on_crtc(dev, crtc, encoder)
3589                 encoder->disable(encoder);
3590
3591         /* Give the overlay scaler a chance to disable if it's on this pipe */
3592         intel_crtc_wait_for_pending_flips(crtc);
3593         drm_vblank_off(dev, pipe);
3594         intel_crtc_dpms_overlay(intel_crtc, false);
3595         intel_crtc_update_cursor(crtc, false);
3596
3597         if (dev_priv->cfb_plane == plane)
3598                 intel_disable_fbc(dev);
3599
3600         intel_disable_plane(dev_priv, plane, pipe);
3601         intel_disable_pipe(dev_priv, pipe);
3602         intel_disable_pll(dev_priv, pipe);
3603
3604         intel_crtc->active = false;
3605         intel_update_fbc(dev);
3606         intel_update_watermarks(dev);
3607 }
3608
3609 static void i9xx_crtc_off(struct drm_crtc *crtc)
3610 {
3611 }
3612
3613 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3614                                     bool enabled)
3615 {
3616         struct drm_device *dev = crtc->dev;
3617         struct drm_i915_master_private *master_priv;
3618         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3619         int pipe = intel_crtc->pipe;
3620
3621         if (!dev->primary->master)
3622                 return;
3623
3624         master_priv = dev->primary->master->driver_priv;
3625         if (!master_priv->sarea_priv)
3626                 return;
3627
3628         switch (pipe) {
3629         case 0:
3630                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3631                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3632                 break;
3633         case 1:
3634                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3635                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3636                 break;
3637         default:
3638                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3639                 break;
3640         }
3641 }
3642
3643 /**
3644  * Sets the power management mode of the pipe and plane.
3645  */
3646 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3647 {
3648         struct drm_device *dev = crtc->dev;
3649         struct drm_i915_private *dev_priv = dev->dev_private;
3650         struct intel_encoder *intel_encoder;
3651         bool enable = false;
3652
3653         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3654                 enable |= intel_encoder->connectors_active;
3655
3656         if (enable)
3657                 dev_priv->display.crtc_enable(crtc);
3658         else
3659                 dev_priv->display.crtc_disable(crtc);
3660
3661         intel_crtc_update_sarea(crtc, enable);
3662 }
3663
3664 static void intel_crtc_noop(struct drm_crtc *crtc)
3665 {
3666 }
3667
3668 static void intel_crtc_disable(struct drm_crtc *crtc)
3669 {
3670         struct drm_device *dev = crtc->dev;
3671         struct drm_connector *connector;
3672         struct drm_i915_private *dev_priv = dev->dev_private;
3673
3674         /* crtc should still be enabled when we disable it. */
3675         WARN_ON(!crtc->enabled);
3676
3677         dev_priv->display.crtc_disable(crtc);
3678         intel_crtc_update_sarea(crtc, false);
3679         dev_priv->display.off(crtc);
3680
3681         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3682         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3683
3684         if (crtc->fb) {
3685                 mutex_lock(&dev->struct_mutex);
3686                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3687                 mutex_unlock(&dev->struct_mutex);
3688                 crtc->fb = NULL;
3689         }
3690
3691         /* Update computed state. */
3692         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3693                 if (!connector->encoder || !connector->encoder->crtc)
3694                         continue;
3695
3696                 if (connector->encoder->crtc != crtc)
3697                         continue;
3698
3699                 connector->dpms = DRM_MODE_DPMS_OFF;
3700                 to_intel_encoder(connector->encoder)->connectors_active = false;
3701         }
3702 }
3703
3704 void intel_modeset_disable(struct drm_device *dev)
3705 {
3706         struct drm_crtc *crtc;
3707
3708         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3709                 if (crtc->enabled)
3710                         intel_crtc_disable(crtc);
3711         }
3712 }
3713
3714 void intel_encoder_noop(struct drm_encoder *encoder)
3715 {
3716 }
3717
3718 void intel_encoder_destroy(struct drm_encoder *encoder)
3719 {
3720         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3721
3722         drm_encoder_cleanup(encoder);
3723         kfree(intel_encoder);
3724 }
3725
3726 /* Simple dpms helper for encodres with just one connector, no cloning and only
3727  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3728  * state of the entire output pipe. */
3729 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3730 {
3731         if (mode == DRM_MODE_DPMS_ON) {
3732                 encoder->connectors_active = true;
3733
3734                 intel_crtc_update_dpms(encoder->base.crtc);
3735         } else {
3736                 encoder->connectors_active = false;
3737
3738                 intel_crtc_update_dpms(encoder->base.crtc);
3739         }
3740 }
3741
3742 /* Cross check the actual hw state with our own modeset state tracking (and it's
3743  * internal consistency). */
3744 static void intel_connector_check_state(struct intel_connector *connector)
3745 {
3746         if (connector->get_hw_state(connector)) {
3747                 struct intel_encoder *encoder = connector->encoder;
3748                 struct drm_crtc *crtc;
3749                 bool encoder_enabled;
3750                 enum pipe pipe;
3751
3752                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3753                               connector->base.base.id,
3754                               drm_get_connector_name(&connector->base));
3755
3756                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3757                      "wrong connector dpms state\n");
3758                 WARN(connector->base.encoder != &encoder->base,
3759                      "active connector not linked to encoder\n");
3760                 WARN(!encoder->connectors_active,
3761                      "encoder->connectors_active not set\n");
3762
3763                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3764                 WARN(!encoder_enabled, "encoder not enabled\n");
3765                 if (WARN_ON(!encoder->base.crtc))
3766                         return;
3767
3768                 crtc = encoder->base.crtc;
3769
3770                 WARN(!crtc->enabled, "crtc not enabled\n");
3771                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3772                 WARN(pipe != to_intel_crtc(crtc)->pipe,
3773                      "encoder active on the wrong pipe\n");
3774         }
3775 }
3776
3777 /* Even simpler default implementation, if there's really no special case to
3778  * consider. */
3779 void intel_connector_dpms(struct drm_connector *connector, int mode)
3780 {
3781         struct intel_encoder *encoder = intel_attached_encoder(connector);
3782
3783         /* All the simple cases only support two dpms states. */
3784         if (mode != DRM_MODE_DPMS_ON)
3785                 mode = DRM_MODE_DPMS_OFF;
3786
3787         if (mode == connector->dpms)
3788                 return;
3789
3790         connector->dpms = mode;
3791
3792         /* Only need to change hw state when actually enabled */
3793         if (encoder->base.crtc)
3794                 intel_encoder_dpms(encoder, mode);
3795         else
3796                 WARN_ON(encoder->connectors_active != false);
3797
3798         intel_modeset_check_state(connector->dev);
3799 }
3800
3801 /* Simple connector->get_hw_state implementation for encoders that support only
3802  * one connector and no cloning and hence the encoder state determines the state
3803  * of the connector. */
3804 bool intel_connector_get_hw_state(struct intel_connector *connector)
3805 {
3806         enum pipe pipe = 0;
3807         struct intel_encoder *encoder = connector->encoder;
3808
3809         return encoder->get_hw_state(encoder, &pipe);
3810 }
3811
3812 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3813                                   const struct drm_display_mode *mode,
3814                                   struct drm_display_mode *adjusted_mode)
3815 {
3816         struct drm_device *dev = crtc->dev;
3817
3818         if (HAS_PCH_SPLIT(dev)) {
3819                 /* FDI link clock is fixed at 2.7G */
3820                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3821                         return false;
3822         }
3823
3824         /* All interlaced capable intel hw wants timings in frames. Note though
3825          * that intel_lvds_mode_fixup does some funny tricks with the crtc
3826          * timings, so we need to be careful not to clobber these.*/
3827         if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3828                 drm_mode_set_crtcinfo(adjusted_mode, 0);
3829
3830         /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3831          * with a hsync front porch of 0.
3832          */
3833         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3834                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3835                 return false;
3836
3837         return true;
3838 }
3839
3840 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3841 {
3842         return 400000; /* FIXME */
3843 }
3844
3845 static int i945_get_display_clock_speed(struct drm_device *dev)
3846 {
3847         return 400000;
3848 }
3849
3850 static int i915_get_display_clock_speed(struct drm_device *dev)
3851 {
3852         return 333000;
3853 }
3854
3855 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3856 {
3857         return 200000;
3858 }
3859
3860 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3861 {
3862         u16 gcfgc = 0;
3863
3864         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3865
3866         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3867                 return 133000;
3868         else {
3869                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3870                 case GC_DISPLAY_CLOCK_333_MHZ:
3871                         return 333000;
3872                 default:
3873                 case GC_DISPLAY_CLOCK_190_200_MHZ:
3874                         return 190000;
3875                 }
3876         }
3877 }
3878
3879 static int i865_get_display_clock_speed(struct drm_device *dev)
3880 {
3881         return 266000;
3882 }
3883
3884 static int i855_get_display_clock_speed(struct drm_device *dev)
3885 {
3886         u16 hpllcc = 0;
3887         /* Assume that the hardware is in the high speed state.  This
3888          * should be the default.
3889          */
3890         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3891         case GC_CLOCK_133_200:
3892         case GC_CLOCK_100_200:
3893                 return 200000;
3894         case GC_CLOCK_166_250:
3895                 return 250000;
3896         case GC_CLOCK_100_133:
3897                 return 133000;
3898         }
3899
3900         /* Shouldn't happen */
3901         return 0;
3902 }
3903
3904 static int i830_get_display_clock_speed(struct drm_device *dev)
3905 {
3906         return 133000;
3907 }
3908
3909 struct fdi_m_n {
3910         u32        tu;
3911         u32        gmch_m;
3912         u32        gmch_n;
3913         u32        link_m;
3914         u32        link_n;
3915 };
3916
3917 static void
3918 fdi_reduce_ratio(u32 *num, u32 *den)
3919 {
3920         while (*num > 0xffffff || *den > 0xffffff) {
3921                 *num >>= 1;
3922                 *den >>= 1;
3923         }
3924 }
3925
3926 static void
3927 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3928                      int link_clock, struct fdi_m_n *m_n)
3929 {
3930         m_n->tu = 64; /* default size */
3931
3932         /* BUG_ON(pixel_clock > INT_MAX / 36); */
3933         m_n->gmch_m = bits_per_pixel * pixel_clock;
3934         m_n->gmch_n = link_clock * nlanes * 8;
3935         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3936
3937         m_n->link_m = pixel_clock;
3938         m_n->link_n = link_clock;
3939         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3940 }
3941
3942 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3943 {
3944         if (i915_panel_use_ssc >= 0)
3945                 return i915_panel_use_ssc != 0;
3946         return dev_priv->lvds_use_ssc
3947                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
3948 }
3949
3950 /**
3951  * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3952  * @crtc: CRTC structure
3953  * @mode: requested mode
3954  *
3955  * A pipe may be connected to one or more outputs.  Based on the depth of the
3956  * attached framebuffer, choose a good color depth to use on the pipe.
3957  *
3958  * If possible, match the pipe depth to the fb depth.  In some cases, this
3959  * isn't ideal, because the connected output supports a lesser or restricted
3960  * set of depths.  Resolve that here:
3961  *    LVDS typically supports only 6bpc, so clamp down in that case
3962  *    HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
3963  *    Displays may support a restricted set as well, check EDID and clamp as
3964  *      appropriate.
3965  *    DP may want to dither down to 6bpc to fit larger modes
3966  *
3967  * RETURNS:
3968  * Dithering requirement (i.e. false if display bpc and pipe bpc match,
3969  * true if they don't match).
3970  */
3971 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
3972                                          struct drm_framebuffer *fb,
3973                                          unsigned int *pipe_bpp,
3974                                          struct drm_display_mode *mode)
3975 {
3976         struct drm_device *dev = crtc->dev;
3977         struct drm_i915_private *dev_priv = dev->dev_private;
3978         struct drm_connector *connector;
3979         struct intel_encoder *intel_encoder;
3980         unsigned int display_bpc = UINT_MAX, bpc;
3981
3982         /* Walk the encoders & connectors on this crtc, get min bpc */
3983         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3984
3985                 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
3986                         unsigned int lvds_bpc;
3987
3988                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
3989                             LVDS_A3_POWER_UP)
3990                                 lvds_bpc = 8;
3991                         else
3992                                 lvds_bpc = 6;
3993
3994                         if (lvds_bpc < display_bpc) {
3995                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
3996                                 display_bpc = lvds_bpc;
3997                         }
3998                         continue;
3999                 }
4000
4001                 /* Not one of the known troublemakers, check the EDID */
4002                 list_for_each_entry(connector, &dev->mode_config.connector_list,
4003                                     head) {
4004                         if (connector->encoder != &intel_encoder->base)
4005                                 continue;
4006
4007                         /* Don't use an invalid EDID bpc value */
4008                         if (connector->display_info.bpc &&
4009                             connector->display_info.bpc < display_bpc) {
4010                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4011                                 display_bpc = connector->display_info.bpc;
4012                         }
4013                 }
4014
4015                 /*
4016                  * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4017                  * through, clamp it down.  (Note: >12bpc will be caught below.)
4018                  */
4019                 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4020                         if (display_bpc > 8 && display_bpc < 12) {
4021                                 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
4022                                 display_bpc = 12;
4023                         } else {
4024                                 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
4025                                 display_bpc = 8;
4026                         }
4027                 }
4028         }
4029
4030         if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4031                 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4032                 display_bpc = 6;
4033         }
4034
4035         /*
4036          * We could just drive the pipe at the highest bpc all the time and
4037          * enable dithering as needed, but that costs bandwidth.  So choose
4038          * the minimum value that expresses the full color range of the fb but
4039          * also stays within the max display bpc discovered above.
4040          */
4041
4042         switch (fb->depth) {
4043         case 8:
4044                 bpc = 8; /* since we go through a colormap */
4045                 break;
4046         case 15:
4047         case 16:
4048                 bpc = 6; /* min is 18bpp */
4049                 break;
4050         case 24:
4051                 bpc = 8;
4052                 break;
4053         case 30:
4054                 bpc = 10;
4055                 break;
4056         case 48:
4057                 bpc = 12;
4058                 break;
4059         default:
4060                 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4061                 bpc = min((unsigned int)8, display_bpc);
4062                 break;
4063         }
4064
4065         display_bpc = min(display_bpc, bpc);
4066
4067         DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4068                       bpc, display_bpc);
4069
4070         *pipe_bpp = display_bpc * 3;
4071
4072         return display_bpc != bpc;
4073 }
4074
4075 static int vlv_get_refclk(struct drm_crtc *crtc)
4076 {
4077         struct drm_device *dev = crtc->dev;
4078         struct drm_i915_private *dev_priv = dev->dev_private;
4079         int refclk = 27000; /* for DP & HDMI */
4080
4081         return 100000; /* only one validated so far */
4082
4083         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4084                 refclk = 96000;
4085         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4086                 if (intel_panel_use_ssc(dev_priv))
4087                         refclk = 100000;
4088                 else
4089                         refclk = 96000;
4090         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4091                 refclk = 100000;
4092         }
4093
4094         return refclk;
4095 }
4096
4097 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4098 {
4099         struct drm_device *dev = crtc->dev;
4100         struct drm_i915_private *dev_priv = dev->dev_private;
4101         int refclk;
4102
4103         if (IS_VALLEYVIEW(dev)) {
4104                 refclk = vlv_get_refclk(crtc);
4105         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4106             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4107                 refclk = dev_priv->lvds_ssc_freq * 1000;
4108                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4109                               refclk / 1000);
4110         } else if (!IS_GEN2(dev)) {
4111                 refclk = 96000;
4112         } else {
4113                 refclk = 48000;
4114         }
4115
4116         return refclk;
4117 }
4118
4119 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4120                                       intel_clock_t *clock)
4121 {
4122         /* SDVO TV has fixed PLL values depend on its clock range,
4123            this mirrors vbios setting. */
4124         if (adjusted_mode->clock >= 100000
4125             && adjusted_mode->clock < 140500) {
4126                 clock->p1 = 2;
4127                 clock->p2 = 10;
4128                 clock->n = 3;
4129                 clock->m1 = 16;
4130                 clock->m2 = 8;
4131         } else if (adjusted_mode->clock >= 140500
4132                    && adjusted_mode->clock <= 200000) {
4133                 clock->p1 = 1;
4134                 clock->p2 = 10;
4135                 clock->n = 6;
4136                 clock->m1 = 12;
4137                 clock->m2 = 8;
4138         }
4139 }
4140
4141 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4142                                      intel_clock_t *clock,
4143                                      intel_clock_t *reduced_clock)
4144 {
4145         struct drm_device *dev = crtc->dev;
4146         struct drm_i915_private *dev_priv = dev->dev_private;
4147         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4148         int pipe = intel_crtc->pipe;
4149         u32 fp, fp2 = 0;
4150
4151         if (IS_PINEVIEW(dev)) {
4152                 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4153                 if (reduced_clock)
4154                         fp2 = (1 << reduced_clock->n) << 16 |
4155                                 reduced_clock->m1 << 8 | reduced_clock->m2;
4156         } else {
4157                 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4158                 if (reduced_clock)
4159                         fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4160                                 reduced_clock->m2;
4161         }
4162
4163         I915_WRITE(FP0(pipe), fp);
4164
4165         intel_crtc->lowfreq_avail = false;
4166         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4167             reduced_clock && i915_powersave) {
4168                 I915_WRITE(FP1(pipe), fp2);
4169                 intel_crtc->lowfreq_avail = true;
4170         } else {
4171                 I915_WRITE(FP1(pipe), fp);
4172         }
4173 }
4174
4175 static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
4176                               struct drm_display_mode *adjusted_mode)
4177 {
4178         struct drm_device *dev = crtc->dev;
4179         struct drm_i915_private *dev_priv = dev->dev_private;
4180         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4181         int pipe = intel_crtc->pipe;
4182         u32 temp;
4183
4184         temp = I915_READ(LVDS);
4185         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4186         if (pipe == 1) {
4187                 temp |= LVDS_PIPEB_SELECT;
4188         } else {
4189                 temp &= ~LVDS_PIPEB_SELECT;
4190         }
4191         /* set the corresponsding LVDS_BORDER bit */
4192         temp |= dev_priv->lvds_border_bits;
4193         /* Set the B0-B3 data pairs corresponding to whether we're going to
4194          * set the DPLLs for dual-channel mode or not.
4195          */
4196         if (clock->p2 == 7)
4197                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4198         else
4199                 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4200
4201         /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4202          * appropriately here, but we need to look more thoroughly into how
4203          * panels behave in the two modes.
4204          */
4205         /* set the dithering flag on LVDS as needed */
4206         if (INTEL_INFO(dev)->gen >= 4) {
4207                 if (dev_priv->lvds_dither)
4208                         temp |= LVDS_ENABLE_DITHER;
4209                 else
4210                         temp &= ~LVDS_ENABLE_DITHER;
4211         }
4212         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4213         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4214                 temp |= LVDS_HSYNC_POLARITY;
4215         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4216                 temp |= LVDS_VSYNC_POLARITY;
4217         I915_WRITE(LVDS, temp);
4218 }
4219
4220 static void vlv_update_pll(struct drm_crtc *crtc,
4221                            struct drm_display_mode *mode,
4222                            struct drm_display_mode *adjusted_mode,
4223                            intel_clock_t *clock, intel_clock_t *reduced_clock,
4224                            int num_connectors)
4225 {
4226         struct drm_device *dev = crtc->dev;
4227         struct drm_i915_private *dev_priv = dev->dev_private;
4228         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4229         int pipe = intel_crtc->pipe;
4230         u32 dpll, mdiv, pdiv;
4231         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4232         bool is_sdvo;
4233         u32 temp;
4234
4235         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4236                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4237
4238         dpll = DPLL_VGA_MODE_DIS;
4239         dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4240         dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4241         dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4242
4243         I915_WRITE(DPLL(pipe), dpll);
4244         POSTING_READ(DPLL(pipe));
4245
4246         bestn = clock->n;
4247         bestm1 = clock->m1;
4248         bestm2 = clock->m2;
4249         bestp1 = clock->p1;
4250         bestp2 = clock->p2;
4251
4252         /*
4253          * In Valleyview PLL and program lane counter registers are exposed
4254          * through DPIO interface
4255          */
4256         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4257         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4258         mdiv |= ((bestn << DPIO_N_SHIFT));
4259         mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4260         mdiv |= (1 << DPIO_K_SHIFT);
4261         mdiv |= DPIO_ENABLE_CALIBRATION;
4262         intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4263
4264         intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4265
4266         pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
4267                 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4268                 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4269                 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4270         intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4271
4272         intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
4273
4274         dpll |= DPLL_VCO_ENABLE;
4275         I915_WRITE(DPLL(pipe), dpll);
4276         POSTING_READ(DPLL(pipe));
4277         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4278                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4279
4280         intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4281
4282         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4283                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4284
4285         I915_WRITE(DPLL(pipe), dpll);
4286
4287         /* Wait for the clocks to stabilize. */
4288         POSTING_READ(DPLL(pipe));
4289         udelay(150);
4290
4291         temp = 0;
4292         if (is_sdvo) {
4293                 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4294                 if (temp > 1)
4295                         temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4296                 else
4297                         temp = 0;
4298         }
4299         I915_WRITE(DPLL_MD(pipe), temp);
4300         POSTING_READ(DPLL_MD(pipe));
4301
4302         /* Now program lane control registers */
4303         if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4304                         || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4305         {
4306                 temp = 0x1000C4;
4307                 if(pipe == 1)
4308                         temp |= (1 << 21);
4309                 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4310         }
4311         if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4312         {
4313                 temp = 0x1000C4;
4314                 if(pipe == 1)
4315                         temp |= (1 << 21);
4316                 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4317         }
4318 }
4319
4320 static void i9xx_update_pll(struct drm_crtc *crtc,
4321                             struct drm_display_mode *mode,
4322                             struct drm_display_mode *adjusted_mode,
4323                             intel_clock_t *clock, intel_clock_t *reduced_clock,
4324                             int num_connectors)
4325 {
4326         struct drm_device *dev = crtc->dev;
4327         struct drm_i915_private *dev_priv = dev->dev_private;
4328         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4329         int pipe = intel_crtc->pipe;
4330         u32 dpll;
4331         bool is_sdvo;
4332
4333         i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4334
4335         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4336                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4337
4338         dpll = DPLL_VGA_MODE_DIS;
4339
4340         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4341                 dpll |= DPLLB_MODE_LVDS;
4342         else
4343                 dpll |= DPLLB_MODE_DAC_SERIAL;
4344         if (is_sdvo) {
4345                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4346                 if (pixel_multiplier > 1) {
4347                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4348                                 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4349                 }
4350                 dpll |= DPLL_DVO_HIGH_SPEED;
4351         }
4352         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4353                 dpll |= DPLL_DVO_HIGH_SPEED;
4354
4355         /* compute bitmask from p1 value */
4356         if (IS_PINEVIEW(dev))
4357                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4358         else {
4359                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4360                 if (IS_G4X(dev) && reduced_clock)
4361                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4362         }
4363         switch (clock->p2) {
4364         case 5:
4365                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4366                 break;
4367         case 7:
4368                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4369                 break;
4370         case 10:
4371                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4372                 break;
4373         case 14:
4374                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4375                 break;
4376         }
4377         if (INTEL_INFO(dev)->gen >= 4)
4378                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4379
4380         if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4381                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4382         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4383                 /* XXX: just matching BIOS for now */
4384                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4385                 dpll |= 3;
4386         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4387                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4388                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4389         else
4390                 dpll |= PLL_REF_INPUT_DREFCLK;
4391
4392         dpll |= DPLL_VCO_ENABLE;
4393         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4394         POSTING_READ(DPLL(pipe));
4395         udelay(150);
4396
4397         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4398          * This is an exception to the general rule that mode_set doesn't turn
4399          * things on.
4400          */
4401         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4402                 intel_update_lvds(crtc, clock, adjusted_mode);
4403
4404         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4405                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4406
4407         I915_WRITE(DPLL(pipe), dpll);
4408
4409         /* Wait for the clocks to stabilize. */
4410         POSTING_READ(DPLL(pipe));
4411         udelay(150);
4412
4413         if (INTEL_INFO(dev)->gen >= 4) {
4414                 u32 temp = 0;
4415                 if (is_sdvo) {
4416                         temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4417                         if (temp > 1)
4418                                 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4419                         else
4420                                 temp = 0;
4421                 }
4422                 I915_WRITE(DPLL_MD(pipe), temp);
4423         } else {
4424                 /* The pixel multiplier can only be updated once the
4425                  * DPLL is enabled and the clocks are stable.
4426                  *
4427                  * So write it again.
4428                  */
4429                 I915_WRITE(DPLL(pipe), dpll);
4430         }
4431 }
4432
4433 static void i8xx_update_pll(struct drm_crtc *crtc,
4434                             struct drm_display_mode *adjusted_mode,
4435                             intel_clock_t *clock, intel_clock_t *reduced_clock,
4436                             int num_connectors)
4437 {
4438         struct drm_device *dev = crtc->dev;
4439         struct drm_i915_private *dev_priv = dev->dev_private;
4440         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4441         int pipe = intel_crtc->pipe;
4442         u32 dpll;
4443
4444         i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4445
4446         dpll = DPLL_VGA_MODE_DIS;
4447
4448         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4449                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4450         } else {
4451                 if (clock->p1 == 2)
4452                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4453                 else
4454                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4455                 if (clock->p2 == 4)
4456                         dpll |= PLL_P2_DIVIDE_BY_4;
4457         }
4458
4459         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4460                 /* XXX: just matching BIOS for now */
4461                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4462                 dpll |= 3;
4463         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4464                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4465                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4466         else
4467                 dpll |= PLL_REF_INPUT_DREFCLK;
4468
4469         dpll |= DPLL_VCO_ENABLE;
4470         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4471         POSTING_READ(DPLL(pipe));
4472         udelay(150);
4473
4474         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4475          * This is an exception to the general rule that mode_set doesn't turn
4476          * things on.
4477          */
4478         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4479                 intel_update_lvds(crtc, clock, adjusted_mode);
4480
4481         I915_WRITE(DPLL(pipe), dpll);
4482
4483         /* Wait for the clocks to stabilize. */
4484         POSTING_READ(DPLL(pipe));
4485         udelay(150);
4486
4487         /* The pixel multiplier can only be updated once the
4488          * DPLL is enabled and the clocks are stable.
4489          *
4490          * So write it again.
4491          */
4492         I915_WRITE(DPLL(pipe), dpll);
4493 }
4494
4495 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4496                                    struct drm_display_mode *mode,
4497                                    struct drm_display_mode *adjusted_mode)
4498 {
4499         struct drm_device *dev = intel_crtc->base.dev;
4500         struct drm_i915_private *dev_priv = dev->dev_private;
4501         enum pipe pipe = intel_crtc->pipe;
4502         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
4503         uint32_t vsyncshift;
4504
4505         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4506                 /* the chip adds 2 halflines automatically */
4507                 adjusted_mode->crtc_vtotal -= 1;
4508                 adjusted_mode->crtc_vblank_end -= 1;
4509                 vsyncshift = adjusted_mode->crtc_hsync_start
4510                              - adjusted_mode->crtc_htotal / 2;
4511         } else {
4512                 vsyncshift = 0;
4513         }
4514
4515         if (INTEL_INFO(dev)->gen > 3)
4516                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4517
4518         I915_WRITE(HTOTAL(cpu_transcoder),
4519                    (adjusted_mode->crtc_hdisplay - 1) |
4520                    ((adjusted_mode->crtc_htotal - 1) << 16));
4521         I915_WRITE(HBLANK(cpu_transcoder),
4522                    (adjusted_mode->crtc_hblank_start - 1) |
4523                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4524         I915_WRITE(HSYNC(cpu_transcoder),
4525                    (adjusted_mode->crtc_hsync_start - 1) |
4526                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4527
4528         I915_WRITE(VTOTAL(cpu_transcoder),
4529                    (adjusted_mode->crtc_vdisplay - 1) |
4530                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4531         I915_WRITE(VBLANK(cpu_transcoder),
4532                    (adjusted_mode->crtc_vblank_start - 1) |
4533                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4534         I915_WRITE(VSYNC(cpu_transcoder),
4535                    (adjusted_mode->crtc_vsync_start - 1) |
4536                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4537
4538         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4539          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4540          * documented on the DDI_FUNC_CTL register description, EDP Input Select
4541          * bits. */
4542         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4543             (pipe == PIPE_B || pipe == PIPE_C))
4544                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4545
4546         /* pipesrc controls the size that is scaled from, which should
4547          * always be the user's requested size.
4548          */
4549         I915_WRITE(PIPESRC(pipe),
4550                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4551 }
4552
4553 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4554                               struct drm_display_mode *mode,
4555                               struct drm_display_mode *adjusted_mode,
4556                               int x, int y,
4557                               struct drm_framebuffer *fb)
4558 {
4559         struct drm_device *dev = crtc->dev;
4560         struct drm_i915_private *dev_priv = dev->dev_private;
4561         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4562         int pipe = intel_crtc->pipe;
4563         int plane = intel_crtc->plane;
4564         int refclk, num_connectors = 0;
4565         intel_clock_t clock, reduced_clock;
4566         u32 dspcntr, pipeconf;
4567         bool ok, has_reduced_clock = false, is_sdvo = false;
4568         bool is_lvds = false, is_tv = false, is_dp = false;
4569         struct intel_encoder *encoder;
4570         const intel_limit_t *limit;
4571         int ret;
4572
4573         for_each_encoder_on_crtc(dev, crtc, encoder) {
4574                 switch (encoder->type) {
4575                 case INTEL_OUTPUT_LVDS:
4576                         is_lvds = true;
4577                         break;
4578                 case INTEL_OUTPUT_SDVO:
4579                 case INTEL_OUTPUT_HDMI:
4580                         is_sdvo = true;
4581                         if (encoder->needs_tv_clock)
4582                                 is_tv = true;
4583                         break;
4584                 case INTEL_OUTPUT_TVOUT:
4585                         is_tv = true;
4586                         break;
4587                 case INTEL_OUTPUT_DISPLAYPORT:
4588                         is_dp = true;
4589                         break;
4590                 }
4591
4592                 num_connectors++;
4593         }
4594
4595         refclk = i9xx_get_refclk(crtc, num_connectors);
4596
4597         /*
4598          * Returns a set of divisors for the desired target clock with the given
4599          * refclk, or FALSE.  The returned values represent the clock equation:
4600          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4601          */
4602         limit = intel_limit(crtc, refclk);
4603         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4604                              &clock);
4605         if (!ok) {
4606                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4607                 return -EINVAL;
4608         }
4609
4610         /* Ensure that the cursor is valid for the new mode before changing... */
4611         intel_crtc_update_cursor(crtc, true);
4612
4613         if (is_lvds && dev_priv->lvds_downclock_avail) {
4614                 /*
4615                  * Ensure we match the reduced clock's P to the target clock.
4616                  * If the clocks don't match, we can't switch the display clock
4617                  * by using the FP0/FP1. In such case we will disable the LVDS
4618                  * downclock feature.
4619                 */
4620                 has_reduced_clock = limit->find_pll(limit, crtc,
4621                                                     dev_priv->lvds_downclock,
4622                                                     refclk,
4623                                                     &clock,
4624                                                     &reduced_clock);
4625         }
4626
4627         if (is_sdvo && is_tv)
4628                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4629
4630         if (IS_GEN2(dev))
4631                 i8xx_update_pll(crtc, adjusted_mode, &clock,
4632                                 has_reduced_clock ? &reduced_clock : NULL,
4633                                 num_connectors);
4634         else if (IS_VALLEYVIEW(dev))
4635                 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4636                                 has_reduced_clock ? &reduced_clock : NULL,
4637                                 num_connectors);
4638         else
4639                 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4640                                 has_reduced_clock ? &reduced_clock : NULL,
4641                                 num_connectors);
4642
4643         /* setup pipeconf */
4644         pipeconf = I915_READ(PIPECONF(pipe));
4645
4646         /* Set up the display plane register */
4647         dspcntr = DISPPLANE_GAMMA_ENABLE;
4648
4649         if (pipe == 0)
4650                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4651         else
4652                 dspcntr |= DISPPLANE_SEL_PIPE_B;
4653
4654         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4655                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4656                  * core speed.
4657                  *
4658                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4659                  * pipe == 0 check?
4660                  */
4661                 if (mode->clock >
4662                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4663                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4664                 else
4665                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4666         }
4667
4668         /* default to 8bpc */
4669         pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4670         if (is_dp) {
4671                 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4672                         pipeconf |= PIPECONF_BPP_6 |
4673                                     PIPECONF_DITHER_EN |
4674                                     PIPECONF_DITHER_TYPE_SP;
4675                 }
4676         }
4677
4678         if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4679                 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4680                         pipeconf |= PIPECONF_BPP_6 |
4681                                         PIPECONF_ENABLE |
4682                                         I965_PIPECONF_ACTIVE;
4683                 }
4684         }
4685
4686         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4687         drm_mode_debug_printmodeline(mode);
4688
4689         if (HAS_PIPE_CXSR(dev)) {
4690                 if (intel_crtc->lowfreq_avail) {
4691                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4692                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4693                 } else {
4694                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4695                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4696                 }
4697         }
4698
4699         pipeconf &= ~PIPECONF_INTERLACE_MASK;
4700         if (!IS_GEN2(dev) &&
4701             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4702                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4703         else
4704                 pipeconf |= PIPECONF_PROGRESSIVE;
4705
4706         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
4707
4708         /* pipesrc and dspsize control the size that is scaled from,
4709          * which should always be the user's requested size.
4710          */
4711         I915_WRITE(DSPSIZE(plane),
4712                    ((mode->vdisplay - 1) << 16) |
4713                    (mode->hdisplay - 1));
4714         I915_WRITE(DSPPOS(plane), 0);
4715
4716         I915_WRITE(PIPECONF(pipe), pipeconf);
4717         POSTING_READ(PIPECONF(pipe));
4718         intel_enable_pipe(dev_priv, pipe, false);
4719
4720         intel_wait_for_vblank(dev, pipe);
4721
4722         I915_WRITE(DSPCNTR(plane), dspcntr);
4723         POSTING_READ(DSPCNTR(plane));
4724
4725         ret = intel_pipe_set_base(crtc, x, y, fb);
4726
4727         intel_update_watermarks(dev);
4728
4729         return ret;
4730 }
4731
4732 /*
4733  * Initialize reference clocks when the driver loads
4734  */
4735 void ironlake_init_pch_refclk(struct drm_device *dev)
4736 {
4737         struct drm_i915_private *dev_priv = dev->dev_private;
4738         struct drm_mode_config *mode_config = &dev->mode_config;
4739         struct intel_encoder *encoder;
4740         u32 temp;
4741         bool has_lvds = false;
4742         bool has_cpu_edp = false;
4743         bool has_pch_edp = false;
4744         bool has_panel = false;
4745         bool has_ck505 = false;
4746         bool can_ssc = false;
4747
4748         /* We need to take the global config into account */
4749         list_for_each_entry(encoder, &mode_config->encoder_list,
4750                             base.head) {
4751                 switch (encoder->type) {
4752                 case INTEL_OUTPUT_LVDS:
4753                         has_panel = true;
4754                         has_lvds = true;
4755                         break;
4756                 case INTEL_OUTPUT_EDP:
4757                         has_panel = true;
4758                         if (intel_encoder_is_pch_edp(&encoder->base))
4759                                 has_pch_edp = true;
4760                         else
4761                                 has_cpu_edp = true;
4762                         break;
4763                 }
4764         }
4765
4766         if (HAS_PCH_IBX(dev)) {
4767                 has_ck505 = dev_priv->display_clock_mode;
4768                 can_ssc = has_ck505;
4769         } else {
4770                 has_ck505 = false;
4771                 can_ssc = true;
4772         }
4773
4774         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4775                       has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4776                       has_ck505);
4777
4778         /* Ironlake: try to setup display ref clock before DPLL
4779          * enabling. This is only under driver's control after
4780          * PCH B stepping, previous chipset stepping should be
4781          * ignoring this setting.
4782          */
4783         temp = I915_READ(PCH_DREF_CONTROL);
4784         /* Always enable nonspread source */
4785         temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4786
4787         if (has_ck505)
4788                 temp |= DREF_NONSPREAD_CK505_ENABLE;
4789         else
4790                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4791
4792         if (has_panel) {
4793                 temp &= ~DREF_SSC_SOURCE_MASK;
4794                 temp |= DREF_SSC_SOURCE_ENABLE;
4795
4796                 /* SSC must be turned on before enabling the CPU output  */
4797                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4798                         DRM_DEBUG_KMS("Using SSC on panel\n");
4799                         temp |= DREF_SSC1_ENABLE;
4800                 } else
4801                         temp &= ~DREF_SSC1_ENABLE;
4802
4803                 /* Get SSC going before enabling the outputs */
4804                 I915_WRITE(PCH_DREF_CONTROL, temp);
4805                 POSTING_READ(PCH_DREF_CONTROL);
4806                 udelay(200);
4807
4808                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4809
4810                 /* Enable CPU source on CPU attached eDP */
4811                 if (has_cpu_edp) {
4812                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4813                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
4814                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4815                         }
4816                         else
4817                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4818                 } else
4819                         temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4820
4821                 I915_WRITE(PCH_DREF_CONTROL, temp);
4822                 POSTING_READ(PCH_DREF_CONTROL);
4823                 udelay(200);
4824         } else {
4825                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4826
4827                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4828
4829                 /* Turn off CPU output */
4830                 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4831
4832                 I915_WRITE(PCH_DREF_CONTROL, temp);
4833                 POSTING_READ(PCH_DREF_CONTROL);
4834                 udelay(200);
4835
4836                 /* Turn off the SSC source */
4837                 temp &= ~DREF_SSC_SOURCE_MASK;
4838                 temp |= DREF_SSC_SOURCE_DISABLE;
4839
4840                 /* Turn off SSC1 */
4841                 temp &= ~ DREF_SSC1_ENABLE;
4842
4843                 I915_WRITE(PCH_DREF_CONTROL, temp);
4844                 POSTING_READ(PCH_DREF_CONTROL);
4845                 udelay(200);
4846         }
4847 }
4848
4849 static int ironlake_get_refclk(struct drm_crtc *crtc)
4850 {
4851         struct drm_device *dev = crtc->dev;
4852         struct drm_i915_private *dev_priv = dev->dev_private;
4853         struct intel_encoder *encoder;
4854         struct intel_encoder *edp_encoder = NULL;
4855         int num_connectors = 0;
4856         bool is_lvds = false;
4857
4858         for_each_encoder_on_crtc(dev, crtc, encoder) {
4859                 switch (encoder->type) {
4860                 case INTEL_OUTPUT_LVDS:
4861                         is_lvds = true;
4862                         break;
4863                 case INTEL_OUTPUT_EDP:
4864                         edp_encoder = encoder;
4865                         break;
4866                 }
4867                 num_connectors++;
4868         }
4869
4870         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4871                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4872                               dev_priv->lvds_ssc_freq);
4873                 return dev_priv->lvds_ssc_freq * 1000;
4874         }
4875
4876         return 120000;
4877 }
4878
4879 static void ironlake_set_pipeconf(struct drm_crtc *crtc,
4880                                   struct drm_display_mode *adjusted_mode,
4881                                   bool dither)
4882 {
4883         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4884         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4885         int pipe = intel_crtc->pipe;
4886         uint32_t val;
4887
4888         val = I915_READ(PIPECONF(pipe));
4889
4890         val &= ~PIPE_BPC_MASK;
4891         switch (intel_crtc->bpp) {
4892         case 18:
4893                 val |= PIPE_6BPC;
4894                 break;
4895         case 24:
4896                 val |= PIPE_8BPC;
4897                 break;
4898         case 30:
4899                 val |= PIPE_10BPC;
4900                 break;
4901         case 36:
4902                 val |= PIPE_12BPC;
4903                 break;
4904         default:
4905                 /* Case prevented by intel_choose_pipe_bpp_dither. */
4906                 BUG();
4907         }
4908
4909         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4910         if (dither)
4911                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
4912
4913         val &= ~PIPECONF_INTERLACE_MASK;
4914         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4915                 val |= PIPECONF_INTERLACED_ILK;
4916         else
4917                 val |= PIPECONF_PROGRESSIVE;
4918
4919         I915_WRITE(PIPECONF(pipe), val);
4920         POSTING_READ(PIPECONF(pipe));
4921 }
4922
4923 static void haswell_set_pipeconf(struct drm_crtc *crtc,
4924                                  struct drm_display_mode *adjusted_mode,
4925                                  bool dither)
4926 {
4927         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4928         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4929         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
4930         uint32_t val;
4931
4932         val = I915_READ(PIPECONF(cpu_transcoder));
4933
4934         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4935         if (dither)
4936                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
4937
4938         val &= ~PIPECONF_INTERLACE_MASK_HSW;
4939         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4940                 val |= PIPECONF_INTERLACED_ILK;
4941         else
4942                 val |= PIPECONF_PROGRESSIVE;
4943
4944         I915_WRITE(PIPECONF(cpu_transcoder), val);
4945         POSTING_READ(PIPECONF(cpu_transcoder));
4946 }
4947
4948 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
4949                                     struct drm_display_mode *adjusted_mode,
4950                                     intel_clock_t *clock,
4951                                     bool *has_reduced_clock,
4952                                     intel_clock_t *reduced_clock)
4953 {
4954         struct drm_device *dev = crtc->dev;
4955         struct drm_i915_private *dev_priv = dev->dev_private;
4956         struct intel_encoder *intel_encoder;
4957         int refclk;
4958         const intel_limit_t *limit;
4959         bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
4960
4961         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4962                 switch (intel_encoder->type) {
4963                 case INTEL_OUTPUT_LVDS:
4964                         is_lvds = true;
4965                         break;
4966                 case INTEL_OUTPUT_SDVO:
4967                 case INTEL_OUTPUT_HDMI:
4968                         is_sdvo = true;
4969                         if (intel_encoder->needs_tv_clock)
4970                                 is_tv = true;
4971                         break;
4972                 case INTEL_OUTPUT_TVOUT:
4973                         is_tv = true;
4974                         break;
4975                 }
4976         }
4977
4978         refclk = ironlake_get_refclk(crtc);
4979
4980         /*
4981          * Returns a set of divisors for the desired target clock with the given
4982          * refclk, or FALSE.  The returned values represent the clock equation:
4983          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4984          */
4985         limit = intel_limit(crtc, refclk);
4986         ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4987                               clock);
4988         if (!ret)
4989                 return false;
4990
4991         if (is_lvds && dev_priv->lvds_downclock_avail) {
4992                 /*
4993                  * Ensure we match the reduced clock's P to the target clock.
4994                  * If the clocks don't match, we can't switch the display clock
4995                  * by using the FP0/FP1. In such case we will disable the LVDS
4996                  * downclock feature.
4997                 */
4998                 *has_reduced_clock = limit->find_pll(limit, crtc,
4999                                                      dev_priv->lvds_downclock,
5000                                                      refclk,
5001                                                      clock,
5002                                                      reduced_clock);
5003         }
5004
5005         if (is_sdvo && is_tv)
5006                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5007
5008         return true;
5009 }
5010
5011 static void ironlake_set_m_n(struct drm_crtc *crtc,
5012                              struct drm_display_mode *mode,
5013                              struct drm_display_mode *adjusted_mode)
5014 {
5015         struct drm_device *dev = crtc->dev;
5016         struct drm_i915_private *dev_priv = dev->dev_private;
5017         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5018         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5019         struct intel_encoder *intel_encoder, *edp_encoder = NULL;
5020         struct fdi_m_n m_n = {0};
5021         int target_clock, pixel_multiplier, lane, link_bw;
5022         bool is_dp = false, is_cpu_edp = false;
5023
5024         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5025                 switch (intel_encoder->type) {
5026                 case INTEL_OUTPUT_DISPLAYPORT:
5027                         is_dp = true;
5028                         break;
5029                 case INTEL_OUTPUT_EDP:
5030                         is_dp = true;
5031                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5032                                 is_cpu_edp = true;
5033                         edp_encoder = intel_encoder;
5034                         break;
5035                 }
5036         }
5037
5038         /* FDI link */
5039         pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5040         lane = 0;
5041         /* CPU eDP doesn't require FDI link, so just set DP M/N
5042            according to current link config */
5043         if (is_cpu_edp) {
5044                 intel_edp_link_config(edp_encoder, &lane, &link_bw);
5045         } else {
5046                 /* FDI is a binary signal running at ~2.7GHz, encoding
5047                  * each output octet as 10 bits. The actual frequency
5048                  * is stored as a divider into a 100MHz clock, and the
5049                  * mode pixel clock is stored in units of 1KHz.
5050                  * Hence the bw of each lane in terms of the mode signal
5051                  * is:
5052                  */
5053                 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5054         }
5055
5056         /* [e]DP over FDI requires target mode clock instead of link clock. */
5057         if (edp_encoder)
5058                 target_clock = intel_edp_target_clock(edp_encoder, mode);
5059         else if (is_dp)
5060                 target_clock = mode->clock;
5061         else
5062                 target_clock = adjusted_mode->clock;
5063
5064         if (!lane) {
5065                 /*
5066                  * Account for spread spectrum to avoid
5067                  * oversubscribing the link. Max center spread
5068                  * is 2.5%; use 5% for safety's sake.
5069                  */
5070                 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5071                 lane = bps / (link_bw * 8) + 1;
5072         }
5073
5074         intel_crtc->fdi_lanes = lane;
5075
5076         if (pixel_multiplier > 1)
5077                 link_bw *= pixel_multiplier;
5078         ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5079                              &m_n);
5080
5081         I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
5082         I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
5083         I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
5084         I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
5085 }
5086
5087 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5088                                       struct drm_display_mode *adjusted_mode,
5089                                       intel_clock_t *clock, u32 fp)
5090 {
5091         struct drm_crtc *crtc = &intel_crtc->base;
5092         struct drm_device *dev = crtc->dev;
5093         struct drm_i915_private *dev_priv = dev->dev_private;
5094         struct intel_encoder *intel_encoder;
5095         uint32_t dpll;
5096         int factor, pixel_multiplier, num_connectors = 0;
5097         bool is_lvds = false, is_sdvo = false, is_tv = false;
5098         bool is_dp = false, is_cpu_edp = false;
5099
5100         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5101                 switch (intel_encoder->type) {
5102                 case INTEL_OUTPUT_LVDS:
5103                         is_lvds = true;
5104                         break;
5105                 case INTEL_OUTPUT_SDVO:
5106                 case INTEL_OUTPUT_HDMI:
5107                         is_sdvo = true;
5108                         if (intel_encoder->needs_tv_clock)
5109                                 is_tv = true;
5110                         break;
5111                 case INTEL_OUTPUT_TVOUT:
5112                         is_tv = true;
5113                         break;
5114                 case INTEL_OUTPUT_DISPLAYPORT:
5115                         is_dp = true;
5116                         break;
5117                 case INTEL_OUTPUT_EDP:
5118                         is_dp = true;
5119                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5120                                 is_cpu_edp = true;
5121                         break;
5122                 }
5123
5124                 num_connectors++;
5125         }
5126
5127         /* Enable autotuning of the PLL clock (if permissible) */
5128         factor = 21;
5129         if (is_lvds) {
5130                 if ((intel_panel_use_ssc(dev_priv) &&
5131                      dev_priv->lvds_ssc_freq == 100) ||
5132                     (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5133                         factor = 25;
5134         } else if (is_sdvo && is_tv)
5135                 factor = 20;
5136
5137         if (clock->m < factor * clock->n)
5138                 fp |= FP_CB_TUNE;
5139
5140         dpll = 0;
5141
5142         if (is_lvds)
5143                 dpll |= DPLLB_MODE_LVDS;
5144         else
5145                 dpll |= DPLLB_MODE_DAC_SERIAL;
5146         if (is_sdvo) {
5147                 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5148                 if (pixel_multiplier > 1) {
5149                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5150                 }
5151                 dpll |= DPLL_DVO_HIGH_SPEED;
5152         }
5153         if (is_dp && !is_cpu_edp)
5154                 dpll |= DPLL_DVO_HIGH_SPEED;
5155
5156         /* compute bitmask from p1 value */
5157         dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5158         /* also FPA1 */
5159         dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5160
5161         switch (clock->p2) {
5162         case 5:
5163                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5164                 break;
5165         case 7:
5166                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5167                 break;
5168         case 10:
5169                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5170                 break;
5171         case 14:
5172                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5173                 break;
5174         }
5175
5176         if (is_sdvo && is_tv)
5177                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5178         else if (is_tv)
5179                 /* XXX: just matching BIOS for now */
5180                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5181                 dpll |= 3;
5182         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5183                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5184         else
5185                 dpll |= PLL_REF_INPUT_DREFCLK;
5186
5187         return dpll;
5188 }
5189
5190 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5191                                   struct drm_display_mode *mode,
5192                                   struct drm_display_mode *adjusted_mode,
5193                                   int x, int y,
5194                                   struct drm_framebuffer *fb)
5195 {
5196         struct drm_device *dev = crtc->dev;
5197         struct drm_i915_private *dev_priv = dev->dev_private;
5198         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5199         int pipe = intel_crtc->pipe;
5200         int plane = intel_crtc->plane;
5201         int num_connectors = 0;
5202         intel_clock_t clock, reduced_clock;
5203         u32 dpll, fp = 0, fp2 = 0;
5204         bool ok, has_reduced_clock = false;
5205         bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5206         struct intel_encoder *encoder;
5207         u32 temp;
5208         int ret;
5209         bool dither;
5210
5211         for_each_encoder_on_crtc(dev, crtc, encoder) {
5212                 switch (encoder->type) {
5213                 case INTEL_OUTPUT_LVDS:
5214                         is_lvds = true;
5215                         break;
5216                 case INTEL_OUTPUT_DISPLAYPORT:
5217                         is_dp = true;
5218                         break;
5219                 case INTEL_OUTPUT_EDP:
5220                         is_dp = true;
5221                         if (!intel_encoder_is_pch_edp(&encoder->base))
5222                                 is_cpu_edp = true;
5223                         break;
5224                 }
5225
5226                 num_connectors++;
5227         }
5228
5229         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5230              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5231
5232         ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5233                                      &has_reduced_clock, &reduced_clock);
5234         if (!ok) {
5235                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5236                 return -EINVAL;
5237         }
5238
5239         /* Ensure that the cursor is valid for the new mode before changing... */
5240         intel_crtc_update_cursor(crtc, true);
5241
5242         /* determine panel color depth */
5243         dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5244                                               adjusted_mode);
5245         if (is_lvds && dev_priv->lvds_dither)
5246                 dither = true;
5247
5248         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5249         if (has_reduced_clock)
5250                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5251                         reduced_clock.m2;
5252
5253         dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
5254
5255         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5256         drm_mode_debug_printmodeline(mode);
5257
5258         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5259         if (!is_cpu_edp) {
5260                 struct intel_pch_pll *pll;
5261
5262                 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5263                 if (pll == NULL) {
5264                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5265                                          pipe);
5266                         return -EINVAL;
5267                 }
5268         } else
5269                 intel_put_pch_pll(intel_crtc);
5270
5271         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5272          * This is an exception to the general rule that mode_set doesn't turn
5273          * things on.
5274          */
5275         if (is_lvds) {
5276                 temp = I915_READ(PCH_LVDS);
5277                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5278                 if (HAS_PCH_CPT(dev)) {
5279                         temp &= ~PORT_TRANS_SEL_MASK;
5280                         temp |= PORT_TRANS_SEL_CPT(pipe);
5281                 } else {
5282                         if (pipe == 1)
5283                                 temp |= LVDS_PIPEB_SELECT;
5284                         else
5285                                 temp &= ~LVDS_PIPEB_SELECT;
5286                 }
5287
5288                 /* set the corresponsding LVDS_BORDER bit */
5289                 temp |= dev_priv->lvds_border_bits;
5290                 /* Set the B0-B3 data pairs corresponding to whether we're going to
5291                  * set the DPLLs for dual-channel mode or not.
5292                  */
5293                 if (clock.p2 == 7)
5294                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5295                 else
5296                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5297
5298                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5299                  * appropriately here, but we need to look more thoroughly into how
5300                  * panels behave in the two modes.
5301                  */
5302                 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5303                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5304                         temp |= LVDS_HSYNC_POLARITY;
5305                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5306                         temp |= LVDS_VSYNC_POLARITY;
5307                 I915_WRITE(PCH_LVDS, temp);
5308         }
5309
5310         if (is_dp && !is_cpu_edp) {
5311                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5312         } else {
5313                 /* For non-DP output, clear any trans DP clock recovery setting.*/
5314                 I915_WRITE(TRANSDATA_M1(pipe), 0);
5315                 I915_WRITE(TRANSDATA_N1(pipe), 0);
5316                 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5317                 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5318         }
5319
5320         if (intel_crtc->pch_pll) {
5321                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5322
5323                 /* Wait for the clocks to stabilize. */
5324                 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5325                 udelay(150);
5326
5327                 /* The pixel multiplier can only be updated once the
5328                  * DPLL is enabled and the clocks are stable.
5329                  *
5330                  * So write it again.
5331                  */
5332                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5333         }
5334
5335         intel_crtc->lowfreq_avail = false;
5336         if (intel_crtc->pch_pll) {
5337                 if (is_lvds && has_reduced_clock && i915_powersave) {
5338                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5339                         intel_crtc->lowfreq_avail = true;
5340                 } else {
5341                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5342                 }
5343         }
5344
5345         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5346
5347         ironlake_set_m_n(crtc, mode, adjusted_mode);
5348
5349         if (is_cpu_edp)
5350                 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5351
5352         ironlake_set_pipeconf(crtc, adjusted_mode, dither);
5353
5354         intel_wait_for_vblank(dev, pipe);
5355
5356         /* Set up the display plane register */
5357         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5358         POSTING_READ(DSPCNTR(plane));
5359
5360         ret = intel_pipe_set_base(crtc, x, y, fb);
5361
5362         intel_update_watermarks(dev);
5363
5364         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5365
5366         return ret;
5367 }
5368
5369 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5370                                  struct drm_display_mode *mode,
5371                                  struct drm_display_mode *adjusted_mode,
5372                                  int x, int y,
5373                                  struct drm_framebuffer *fb)
5374 {
5375         struct drm_device *dev = crtc->dev;
5376         struct drm_i915_private *dev_priv = dev->dev_private;
5377         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5378         int pipe = intel_crtc->pipe;
5379         int plane = intel_crtc->plane;
5380         int num_connectors = 0;
5381         intel_clock_t clock, reduced_clock;
5382         u32 dpll = 0, fp = 0, fp2 = 0;
5383         bool ok, has_reduced_clock = false;
5384         bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5385         struct intel_encoder *encoder;
5386         u32 temp;
5387         int ret;
5388         bool dither;
5389
5390         for_each_encoder_on_crtc(dev, crtc, encoder) {
5391                 switch (encoder->type) {
5392                 case INTEL_OUTPUT_LVDS:
5393                         is_lvds = true;
5394                         break;
5395                 case INTEL_OUTPUT_DISPLAYPORT:
5396                         is_dp = true;
5397                         break;
5398                 case INTEL_OUTPUT_EDP:
5399                         is_dp = true;
5400                         if (!intel_encoder_is_pch_edp(&encoder->base))
5401                                 is_cpu_edp = true;
5402                         break;
5403                 }
5404
5405                 num_connectors++;
5406         }
5407
5408         if (is_cpu_edp)
5409                 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5410         else
5411                 intel_crtc->cpu_transcoder = pipe;
5412
5413         /* We are not sure yet this won't happen. */
5414         WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5415              INTEL_PCH_TYPE(dev));
5416
5417         WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5418              num_connectors, pipe_name(pipe));
5419
5420         WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
5421                 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5422
5423         WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5424
5425         if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5426                 return -EINVAL;
5427
5428         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5429                 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5430                                              &has_reduced_clock,
5431                                              &reduced_clock);
5432                 if (!ok) {
5433                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
5434                         return -EINVAL;
5435                 }
5436         }
5437
5438         /* Ensure that the cursor is valid for the new mode before changing... */
5439         intel_crtc_update_cursor(crtc, true);
5440
5441         /* determine panel color depth */
5442         dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5443                                               adjusted_mode);
5444         if (is_lvds && dev_priv->lvds_dither)
5445                 dither = true;
5446
5447         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5448         drm_mode_debug_printmodeline(mode);
5449
5450         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5451                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5452                 if (has_reduced_clock)
5453                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5454                               reduced_clock.m2;
5455
5456                 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock,
5457                                              fp);
5458
5459                 /* CPU eDP is the only output that doesn't need a PCH PLL of its
5460                  * own on pre-Haswell/LPT generation */
5461                 if (!is_cpu_edp) {
5462                         struct intel_pch_pll *pll;
5463
5464                         pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5465                         if (pll == NULL) {
5466                                 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5467                                                  pipe);
5468                                 return -EINVAL;
5469                         }
5470                 } else
5471                         intel_put_pch_pll(intel_crtc);
5472
5473                 /* The LVDS pin pair needs to be on before the DPLLs are
5474                  * enabled.  This is an exception to the general rule that
5475                  * mode_set doesn't turn things on.
5476                  */
5477                 if (is_lvds) {
5478                         temp = I915_READ(PCH_LVDS);
5479                         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5480                         if (HAS_PCH_CPT(dev)) {
5481                                 temp &= ~PORT_TRANS_SEL_MASK;
5482                                 temp |= PORT_TRANS_SEL_CPT(pipe);
5483                         } else {
5484                                 if (pipe == 1)
5485                                         temp |= LVDS_PIPEB_SELECT;
5486                                 else
5487                                         temp &= ~LVDS_PIPEB_SELECT;
5488                         }
5489
5490                         /* set the corresponsding LVDS_BORDER bit */
5491                         temp |= dev_priv->lvds_border_bits;
5492                         /* Set the B0-B3 data pairs corresponding to whether
5493                          * we're going to set the DPLLs for dual-channel mode or
5494                          * not.
5495                          */
5496                         if (clock.p2 == 7)
5497                                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5498                         else
5499                                 temp &= ~(LVDS_B0B3_POWER_UP |
5500                                           LVDS_CLKB_POWER_UP);
5501
5502                         /* It would be nice to set 24 vs 18-bit mode
5503                          * (LVDS_A3_POWER_UP) appropriately here, but we need to
5504                          * look more thoroughly into how panels behave in the
5505                          * two modes.
5506                          */
5507                         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5508                         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5509                                 temp |= LVDS_HSYNC_POLARITY;
5510                         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5511                                 temp |= LVDS_VSYNC_POLARITY;
5512                         I915_WRITE(PCH_LVDS, temp);
5513                 }
5514         }
5515
5516         if (is_dp && !is_cpu_edp) {
5517                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5518         } else {
5519                 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5520                         /* For non-DP output, clear any trans DP clock recovery
5521                          * setting.*/
5522                         I915_WRITE(TRANSDATA_M1(pipe), 0);
5523                         I915_WRITE(TRANSDATA_N1(pipe), 0);
5524                         I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5525                         I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5526                 }
5527         }
5528
5529         intel_crtc->lowfreq_avail = false;
5530         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5531                 if (intel_crtc->pch_pll) {
5532                         I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5533
5534                         /* Wait for the clocks to stabilize. */
5535                         POSTING_READ(intel_crtc->pch_pll->pll_reg);
5536                         udelay(150);
5537
5538                         /* The pixel multiplier can only be updated once the
5539                          * DPLL is enabled and the clocks are stable.
5540                          *
5541                          * So write it again.
5542                          */
5543                         I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5544                 }
5545
5546                 if (intel_crtc->pch_pll) {
5547                         if (is_lvds && has_reduced_clock && i915_powersave) {
5548                                 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5549                                 intel_crtc->lowfreq_avail = true;
5550                         } else {
5551                                 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5552                         }
5553                 }
5554         }
5555
5556         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5557
5558         if (!is_dp || is_cpu_edp)
5559                 ironlake_set_m_n(crtc, mode, adjusted_mode);
5560
5561         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5562                 if (is_cpu_edp)
5563                         ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5564
5565         haswell_set_pipeconf(crtc, adjusted_mode, dither);
5566
5567         /* Set up the display plane register */
5568         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5569         POSTING_READ(DSPCNTR(plane));
5570
5571         ret = intel_pipe_set_base(crtc, x, y, fb);
5572
5573         intel_update_watermarks(dev);
5574
5575         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5576
5577         return ret;
5578 }
5579
5580 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5581                                struct drm_display_mode *mode,
5582                                struct drm_display_mode *adjusted_mode,
5583                                int x, int y,
5584                                struct drm_framebuffer *fb)
5585 {
5586         struct drm_device *dev = crtc->dev;
5587         struct drm_i915_private *dev_priv = dev->dev_private;
5588         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5589         int pipe = intel_crtc->pipe;
5590         int ret;
5591
5592         drm_vblank_pre_modeset(dev, pipe);
5593
5594         ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5595                                               x, y, fb);
5596         drm_vblank_post_modeset(dev, pipe);
5597
5598         return ret;
5599 }
5600
5601 static bool intel_eld_uptodate(struct drm_connector *connector,
5602                                int reg_eldv, uint32_t bits_eldv,
5603                                int reg_elda, uint32_t bits_elda,
5604                                int reg_edid)
5605 {
5606         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5607         uint8_t *eld = connector->eld;
5608         uint32_t i;
5609
5610         i = I915_READ(reg_eldv);
5611         i &= bits_eldv;
5612
5613         if (!eld[0])
5614                 return !i;
5615
5616         if (!i)
5617                 return false;
5618
5619         i = I915_READ(reg_elda);
5620         i &= ~bits_elda;
5621         I915_WRITE(reg_elda, i);
5622
5623         for (i = 0; i < eld[2]; i++)
5624                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5625                         return false;
5626
5627         return true;
5628 }
5629
5630 static void g4x_write_eld(struct drm_connector *connector,
5631                           struct drm_crtc *crtc)
5632 {
5633         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5634         uint8_t *eld = connector->eld;
5635         uint32_t eldv;
5636         uint32_t len;
5637         uint32_t i;
5638
5639         i = I915_READ(G4X_AUD_VID_DID);
5640
5641         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5642                 eldv = G4X_ELDV_DEVCL_DEVBLC;
5643         else
5644                 eldv = G4X_ELDV_DEVCTG;
5645
5646         if (intel_eld_uptodate(connector,
5647                                G4X_AUD_CNTL_ST, eldv,
5648                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5649                                G4X_HDMIW_HDMIEDID))
5650                 return;
5651
5652         i = I915_READ(G4X_AUD_CNTL_ST);
5653         i &= ~(eldv | G4X_ELD_ADDR);
5654         len = (i >> 9) & 0x1f;          /* ELD buffer size */
5655         I915_WRITE(G4X_AUD_CNTL_ST, i);
5656
5657         if (!eld[0])
5658                 return;
5659
5660         len = min_t(uint8_t, eld[2], len);
5661         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5662         for (i = 0; i < len; i++)
5663                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5664
5665         i = I915_READ(G4X_AUD_CNTL_ST);
5666         i |= eldv;
5667         I915_WRITE(G4X_AUD_CNTL_ST, i);
5668 }
5669
5670 static void haswell_write_eld(struct drm_connector *connector,
5671                                      struct drm_crtc *crtc)
5672 {
5673         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5674         uint8_t *eld = connector->eld;
5675         struct drm_device *dev = crtc->dev;
5676         uint32_t eldv;
5677         uint32_t i;
5678         int len;
5679         int pipe = to_intel_crtc(crtc)->pipe;
5680         int tmp;
5681
5682         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5683         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5684         int aud_config = HSW_AUD_CFG(pipe);
5685         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5686
5687
5688         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5689
5690         /* Audio output enable */
5691         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5692         tmp = I915_READ(aud_cntrl_st2);
5693         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5694         I915_WRITE(aud_cntrl_st2, tmp);
5695
5696         /* Wait for 1 vertical blank */
5697         intel_wait_for_vblank(dev, pipe);
5698
5699         /* Set ELD valid state */
5700         tmp = I915_READ(aud_cntrl_st2);
5701         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5702         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5703         I915_WRITE(aud_cntrl_st2, tmp);
5704         tmp = I915_READ(aud_cntrl_st2);
5705         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5706
5707         /* Enable HDMI mode */
5708         tmp = I915_READ(aud_config);
5709         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5710         /* clear N_programing_enable and N_value_index */
5711         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5712         I915_WRITE(aud_config, tmp);
5713
5714         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5715
5716         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5717
5718         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5719                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5720                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
5721                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5722         } else
5723                 I915_WRITE(aud_config, 0);
5724
5725         if (intel_eld_uptodate(connector,
5726                                aud_cntrl_st2, eldv,
5727                                aud_cntl_st, IBX_ELD_ADDRESS,
5728                                hdmiw_hdmiedid))
5729                 return;
5730
5731         i = I915_READ(aud_cntrl_st2);
5732         i &= ~eldv;
5733         I915_WRITE(aud_cntrl_st2, i);
5734
5735         if (!eld[0])
5736                 return;
5737
5738         i = I915_READ(aud_cntl_st);
5739         i &= ~IBX_ELD_ADDRESS;
5740         I915_WRITE(aud_cntl_st, i);
5741         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
5742         DRM_DEBUG_DRIVER("port num:%d\n", i);
5743
5744         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
5745         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5746         for (i = 0; i < len; i++)
5747                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5748
5749         i = I915_READ(aud_cntrl_st2);
5750         i |= eldv;
5751         I915_WRITE(aud_cntrl_st2, i);
5752
5753 }
5754
5755 static void ironlake_write_eld(struct drm_connector *connector,
5756                                      struct drm_crtc *crtc)
5757 {
5758         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5759         uint8_t *eld = connector->eld;
5760         uint32_t eldv;
5761         uint32_t i;
5762         int len;
5763         int hdmiw_hdmiedid;
5764         int aud_config;
5765         int aud_cntl_st;
5766         int aud_cntrl_st2;
5767         int pipe = to_intel_crtc(crtc)->pipe;
5768
5769         if (HAS_PCH_IBX(connector->dev)) {
5770                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
5771                 aud_config = IBX_AUD_CFG(pipe);
5772                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
5773                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
5774         } else {
5775                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
5776                 aud_config = CPT_AUD_CFG(pipe);
5777                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
5778                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
5779         }
5780
5781         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5782
5783         i = I915_READ(aud_cntl_st);
5784         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
5785         if (!i) {
5786                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5787                 /* operate blindly on all ports */
5788                 eldv = IBX_ELD_VALIDB;
5789                 eldv |= IBX_ELD_VALIDB << 4;
5790                 eldv |= IBX_ELD_VALIDB << 8;
5791         } else {
5792                 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
5793                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
5794         }
5795
5796         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5797                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5798                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
5799                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5800         } else
5801                 I915_WRITE(aud_config, 0);
5802
5803         if (intel_eld_uptodate(connector,
5804                                aud_cntrl_st2, eldv,
5805                                aud_cntl_st, IBX_ELD_ADDRESS,
5806                                hdmiw_hdmiedid))
5807                 return;
5808
5809         i = I915_READ(aud_cntrl_st2);
5810         i &= ~eldv;
5811         I915_WRITE(aud_cntrl_st2, i);
5812
5813         if (!eld[0])
5814                 return;
5815
5816         i = I915_READ(aud_cntl_st);
5817         i &= ~IBX_ELD_ADDRESS;
5818         I915_WRITE(aud_cntl_st, i);
5819
5820         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
5821         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5822         for (i = 0; i < len; i++)
5823                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5824
5825         i = I915_READ(aud_cntrl_st2);
5826         i |= eldv;
5827         I915_WRITE(aud_cntrl_st2, i);
5828 }
5829
5830 void intel_write_eld(struct drm_encoder *encoder,
5831                      struct drm_display_mode *mode)
5832 {
5833         struct drm_crtc *crtc = encoder->crtc;
5834         struct drm_connector *connector;
5835         struct drm_device *dev = encoder->dev;
5836         struct drm_i915_private *dev_priv = dev->dev_private;
5837
5838         connector = drm_select_eld(encoder, mode);
5839         if (!connector)
5840                 return;
5841
5842         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5843                          connector->base.id,
5844                          drm_get_connector_name(connector),
5845                          connector->encoder->base.id,
5846                          drm_get_encoder_name(connector->encoder));
5847
5848         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
5849
5850         if (dev_priv->display.write_eld)
5851                 dev_priv->display.write_eld(connector, crtc);
5852 }
5853
5854 /** Loads the palette/gamma unit for the CRTC with the prepared values */
5855 void intel_crtc_load_lut(struct drm_crtc *crtc)
5856 {
5857         struct drm_device *dev = crtc->dev;
5858         struct drm_i915_private *dev_priv = dev->dev_private;
5859         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5860         int palreg = PALETTE(intel_crtc->pipe);
5861         int i;
5862
5863         /* The clocks have to be on to load the palette. */
5864         if (!crtc->enabled || !intel_crtc->active)
5865                 return;
5866
5867         /* use legacy palette for Ironlake */
5868         if (HAS_PCH_SPLIT(dev))
5869                 palreg = LGC_PALETTE(intel_crtc->pipe);
5870
5871         for (i = 0; i < 256; i++) {
5872                 I915_WRITE(palreg + 4 * i,
5873                            (intel_crtc->lut_r[i] << 16) |
5874                            (intel_crtc->lut_g[i] << 8) |
5875                            intel_crtc->lut_b[i]);
5876         }
5877 }
5878
5879 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5880 {
5881         struct drm_device *dev = crtc->dev;
5882         struct drm_i915_private *dev_priv = dev->dev_private;
5883         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5884         bool visible = base != 0;
5885         u32 cntl;
5886
5887         if (intel_crtc->cursor_visible == visible)
5888                 return;
5889
5890         cntl = I915_READ(_CURACNTR);
5891         if (visible) {
5892                 /* On these chipsets we can only modify the base whilst
5893                  * the cursor is disabled.
5894                  */
5895                 I915_WRITE(_CURABASE, base);
5896
5897                 cntl &= ~(CURSOR_FORMAT_MASK);
5898                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5899                 cntl |= CURSOR_ENABLE |
5900                         CURSOR_GAMMA_ENABLE |
5901                         CURSOR_FORMAT_ARGB;
5902         } else
5903                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
5904         I915_WRITE(_CURACNTR, cntl);
5905
5906         intel_crtc->cursor_visible = visible;
5907 }
5908
5909 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5910 {
5911         struct drm_device *dev = crtc->dev;
5912         struct drm_i915_private *dev_priv = dev->dev_private;
5913         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5914         int pipe = intel_crtc->pipe;
5915         bool visible = base != 0;
5916
5917         if (intel_crtc->cursor_visible != visible) {
5918                 uint32_t cntl = I915_READ(CURCNTR(pipe));
5919                 if (base) {
5920                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5921                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5922                         cntl |= pipe << 28; /* Connect to correct pipe */
5923                 } else {
5924                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5925                         cntl |= CURSOR_MODE_DISABLE;
5926                 }
5927                 I915_WRITE(CURCNTR(pipe), cntl);
5928
5929                 intel_crtc->cursor_visible = visible;
5930         }
5931         /* and commit changes on next vblank */
5932         I915_WRITE(CURBASE(pipe), base);
5933 }
5934
5935 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
5936 {
5937         struct drm_device *dev = crtc->dev;
5938         struct drm_i915_private *dev_priv = dev->dev_private;
5939         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5940         int pipe = intel_crtc->pipe;
5941         bool visible = base != 0;
5942
5943         if (intel_crtc->cursor_visible != visible) {
5944                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
5945                 if (base) {
5946                         cntl &= ~CURSOR_MODE;
5947                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5948                 } else {
5949                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5950                         cntl |= CURSOR_MODE_DISABLE;
5951                 }
5952                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
5953
5954                 intel_crtc->cursor_visible = visible;
5955         }
5956         /* and commit changes on next vblank */
5957         I915_WRITE(CURBASE_IVB(pipe), base);
5958 }
5959
5960 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
5961 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5962                                      bool on)
5963 {
5964         struct drm_device *dev = crtc->dev;
5965         struct drm_i915_private *dev_priv = dev->dev_private;
5966         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5967         int pipe = intel_crtc->pipe;
5968         int x = intel_crtc->cursor_x;
5969         int y = intel_crtc->cursor_y;
5970         u32 base, pos;
5971         bool visible;
5972
5973         pos = 0;
5974
5975         if (on && crtc->enabled && crtc->fb) {
5976                 base = intel_crtc->cursor_addr;
5977                 if (x > (int) crtc->fb->width)
5978                         base = 0;
5979
5980                 if (y > (int) crtc->fb->height)
5981                         base = 0;
5982         } else
5983                 base = 0;
5984
5985         if (x < 0) {
5986                 if (x + intel_crtc->cursor_width < 0)
5987                         base = 0;
5988
5989                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5990                 x = -x;
5991         }
5992         pos |= x << CURSOR_X_SHIFT;
5993
5994         if (y < 0) {
5995                 if (y + intel_crtc->cursor_height < 0)
5996                         base = 0;
5997
5998                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5999                 y = -y;
6000         }
6001         pos |= y << CURSOR_Y_SHIFT;
6002
6003         visible = base != 0;
6004         if (!visible && !intel_crtc->cursor_visible)
6005                 return;
6006
6007         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6008                 I915_WRITE(CURPOS_IVB(pipe), pos);
6009                 ivb_update_cursor(crtc, base);
6010         } else {
6011                 I915_WRITE(CURPOS(pipe), pos);
6012                 if (IS_845G(dev) || IS_I865G(dev))
6013                         i845_update_cursor(crtc, base);
6014                 else
6015                         i9xx_update_cursor(crtc, base);
6016         }
6017 }
6018
6019 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6020                                  struct drm_file *file,
6021                                  uint32_t handle,
6022                                  uint32_t width, uint32_t height)
6023 {
6024         struct drm_device *dev = crtc->dev;
6025         struct drm_i915_private *dev_priv = dev->dev_private;
6026         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6027         struct drm_i915_gem_object *obj;
6028         uint32_t addr;
6029         int ret;
6030
6031         /* if we want to turn off the cursor ignore width and height */
6032         if (!handle) {
6033                 DRM_DEBUG_KMS("cursor off\n");
6034                 addr = 0;
6035                 obj = NULL;
6036                 mutex_lock(&dev->struct_mutex);
6037                 goto finish;
6038         }
6039
6040         /* Currently we only support 64x64 cursors */
6041         if (width != 64 || height != 64) {
6042                 DRM_ERROR("we currently only support 64x64 cursors\n");
6043                 return -EINVAL;
6044         }
6045
6046         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6047         if (&obj->base == NULL)
6048                 return -ENOENT;
6049
6050         if (obj->base.size < width * height * 4) {
6051                 DRM_ERROR("buffer is to small\n");
6052                 ret = -ENOMEM;
6053                 goto fail;
6054         }
6055
6056         /* we only need to pin inside GTT if cursor is non-phy */
6057         mutex_lock(&dev->struct_mutex);
6058         if (!dev_priv->info->cursor_needs_physical) {
6059                 if (obj->tiling_mode) {
6060                         DRM_ERROR("cursor cannot be tiled\n");
6061                         ret = -EINVAL;
6062                         goto fail_locked;
6063                 }
6064
6065                 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
6066                 if (ret) {
6067                         DRM_ERROR("failed to move cursor bo into the GTT\n");
6068                         goto fail_locked;
6069                 }
6070
6071                 ret = i915_gem_object_put_fence(obj);
6072                 if (ret) {
6073                         DRM_ERROR("failed to release fence for cursor");
6074                         goto fail_unpin;
6075                 }
6076
6077                 addr = obj->gtt_offset;
6078         } else {
6079                 int align = IS_I830(dev) ? 16 * 1024 : 256;
6080                 ret = i915_gem_attach_phys_object(dev, obj,
6081                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6082                                                   align);
6083                 if (ret) {
6084                         DRM_ERROR("failed to attach phys object\n");
6085                         goto fail_locked;
6086                 }
6087                 addr = obj->phys_obj->handle->busaddr;
6088         }
6089
6090         if (IS_GEN2(dev))
6091                 I915_WRITE(CURSIZE, (height << 12) | width);
6092
6093  finish:
6094         if (intel_crtc->cursor_bo) {
6095                 if (dev_priv->info->cursor_needs_physical) {
6096                         if (intel_crtc->cursor_bo != obj)
6097                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6098                 } else
6099                         i915_gem_object_unpin(intel_crtc->cursor_bo);
6100                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6101         }
6102
6103         mutex_unlock(&dev->struct_mutex);
6104
6105         intel_crtc->cursor_addr = addr;
6106         intel_crtc->cursor_bo = obj;
6107         intel_crtc->cursor_width = width;
6108         intel_crtc->cursor_height = height;
6109
6110         intel_crtc_update_cursor(crtc, true);
6111
6112         return 0;
6113 fail_unpin:
6114         i915_gem_object_unpin(obj);
6115 fail_locked:
6116         mutex_unlock(&dev->struct_mutex);
6117 fail:
6118         drm_gem_object_unreference_unlocked(&obj->base);
6119         return ret;
6120 }
6121
6122 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6123 {
6124         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6125
6126         intel_crtc->cursor_x = x;
6127         intel_crtc->cursor_y = y;
6128
6129         intel_crtc_update_cursor(crtc, true);
6130
6131         return 0;
6132 }
6133
6134 /** Sets the color ramps on behalf of RandR */
6135 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6136                                  u16 blue, int regno)
6137 {
6138         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6139
6140         intel_crtc->lut_r[regno] = red >> 8;
6141         intel_crtc->lut_g[regno] = green >> 8;
6142         intel_crtc->lut_b[regno] = blue >> 8;
6143 }
6144
6145 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6146                              u16 *blue, int regno)
6147 {
6148         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6149
6150         *red = intel_crtc->lut_r[regno] << 8;
6151         *green = intel_crtc->lut_g[regno] << 8;
6152         *blue = intel_crtc->lut_b[regno] << 8;
6153 }
6154
6155 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6156                                  u16 *blue, uint32_t start, uint32_t size)
6157 {
6158         int end = (start + size > 256) ? 256 : start + size, i;
6159         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6160
6161         for (i = start; i < end; i++) {
6162                 intel_crtc->lut_r[i] = red[i] >> 8;
6163                 intel_crtc->lut_g[i] = green[i] >> 8;
6164                 intel_crtc->lut_b[i] = blue[i] >> 8;
6165         }
6166
6167         intel_crtc_load_lut(crtc);
6168 }
6169
6170 /**
6171  * Get a pipe with a simple mode set on it for doing load-based monitor
6172  * detection.
6173  *
6174  * It will be up to the load-detect code to adjust the pipe as appropriate for
6175  * its requirements.  The pipe will be connected to no other encoders.
6176  *
6177  * Currently this code will only succeed if there is a pipe with no encoders
6178  * configured for it.  In the future, it could choose to temporarily disable
6179  * some outputs to free up a pipe for its use.
6180  *
6181  * \return crtc, or NULL if no pipes are available.
6182  */
6183
6184 /* VESA 640x480x72Hz mode to set on the pipe */
6185 static struct drm_display_mode load_detect_mode = {
6186         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6187                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6188 };
6189
6190 static struct drm_framebuffer *
6191 intel_framebuffer_create(struct drm_device *dev,
6192                          struct drm_mode_fb_cmd2 *mode_cmd,
6193                          struct drm_i915_gem_object *obj)
6194 {
6195         struct intel_framebuffer *intel_fb;
6196         int ret;
6197
6198         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6199         if (!intel_fb) {
6200                 drm_gem_object_unreference_unlocked(&obj->base);
6201                 return ERR_PTR(-ENOMEM);
6202         }
6203
6204         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6205         if (ret) {
6206                 drm_gem_object_unreference_unlocked(&obj->base);
6207                 kfree(intel_fb);
6208                 return ERR_PTR(ret);
6209         }
6210
6211         return &intel_fb->base;
6212 }
6213
6214 static u32
6215 intel_framebuffer_pitch_for_width(int width, int bpp)
6216 {
6217         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6218         return ALIGN(pitch, 64);
6219 }
6220
6221 static u32
6222 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6223 {
6224         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6225         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6226 }
6227
6228 static struct drm_framebuffer *
6229 intel_framebuffer_create_for_mode(struct drm_device *dev,
6230                                   struct drm_display_mode *mode,
6231                                   int depth, int bpp)
6232 {
6233         struct drm_i915_gem_object *obj;
6234         struct drm_mode_fb_cmd2 mode_cmd;
6235
6236         obj = i915_gem_alloc_object(dev,
6237                                     intel_framebuffer_size_for_mode(mode, bpp));
6238         if (obj == NULL)
6239                 return ERR_PTR(-ENOMEM);
6240
6241         mode_cmd.width = mode->hdisplay;
6242         mode_cmd.height = mode->vdisplay;
6243         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6244                                                                 bpp);
6245         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6246
6247         return intel_framebuffer_create(dev, &mode_cmd, obj);
6248 }
6249
6250 static struct drm_framebuffer *
6251 mode_fits_in_fbdev(struct drm_device *dev,
6252                    struct drm_display_mode *mode)
6253 {
6254         struct drm_i915_private *dev_priv = dev->dev_private;
6255         struct drm_i915_gem_object *obj;
6256         struct drm_framebuffer *fb;
6257
6258         if (dev_priv->fbdev == NULL)
6259                 return NULL;
6260
6261         obj = dev_priv->fbdev->ifb.obj;
6262         if (obj == NULL)
6263                 return NULL;
6264
6265         fb = &dev_priv->fbdev->ifb.base;
6266         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6267                                                                fb->bits_per_pixel))
6268                 return NULL;
6269
6270         if (obj->base.size < mode->vdisplay * fb->pitches[0])
6271                 return NULL;
6272
6273         return fb;
6274 }
6275
6276 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6277                                 struct drm_display_mode *mode,
6278                                 struct intel_load_detect_pipe *old)
6279 {
6280         struct intel_crtc *intel_crtc;
6281         struct intel_encoder *intel_encoder =
6282                 intel_attached_encoder(connector);
6283         struct drm_crtc *possible_crtc;
6284         struct drm_encoder *encoder = &intel_encoder->base;
6285         struct drm_crtc *crtc = NULL;
6286         struct drm_device *dev = encoder->dev;
6287         struct drm_framebuffer *fb;
6288         int i = -1;
6289
6290         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6291                       connector->base.id, drm_get_connector_name(connector),
6292                       encoder->base.id, drm_get_encoder_name(encoder));
6293
6294         /*
6295          * Algorithm gets a little messy:
6296          *
6297          *   - if the connector already has an assigned crtc, use it (but make
6298          *     sure it's on first)
6299          *
6300          *   - try to find the first unused crtc that can drive this connector,
6301          *     and use that if we find one
6302          */
6303
6304         /* See if we already have a CRTC for this connector */
6305         if (encoder->crtc) {
6306                 crtc = encoder->crtc;
6307
6308                 old->dpms_mode = connector->dpms;
6309                 old->load_detect_temp = false;
6310
6311                 /* Make sure the crtc and connector are running */
6312                 if (connector->dpms != DRM_MODE_DPMS_ON)
6313                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6314
6315                 return true;
6316         }
6317
6318         /* Find an unused one (if possible) */
6319         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6320                 i++;
6321                 if (!(encoder->possible_crtcs & (1 << i)))
6322                         continue;
6323                 if (!possible_crtc->enabled) {
6324                         crtc = possible_crtc;
6325                         break;
6326                 }
6327         }
6328
6329         /*
6330          * If we didn't find an unused CRTC, don't use any.
6331          */
6332         if (!crtc) {
6333                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6334                 return false;
6335         }
6336
6337         intel_encoder->new_crtc = to_intel_crtc(crtc);
6338         to_intel_connector(connector)->new_encoder = intel_encoder;
6339
6340         intel_crtc = to_intel_crtc(crtc);
6341         old->dpms_mode = connector->dpms;
6342         old->load_detect_temp = true;
6343         old->release_fb = NULL;
6344
6345         if (!mode)
6346                 mode = &load_detect_mode;
6347
6348         /* We need a framebuffer large enough to accommodate all accesses
6349          * that the plane may generate whilst we perform load detection.
6350          * We can not rely on the fbcon either being present (we get called
6351          * during its initialisation to detect all boot displays, or it may
6352          * not even exist) or that it is large enough to satisfy the
6353          * requested mode.
6354          */
6355         fb = mode_fits_in_fbdev(dev, mode);
6356         if (fb == NULL) {
6357                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6358                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6359                 old->release_fb = fb;
6360         } else
6361                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6362         if (IS_ERR(fb)) {
6363                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6364                 goto fail;
6365         }
6366
6367         if (!intel_set_mode(crtc, mode, 0, 0, fb)) {
6368                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6369                 if (old->release_fb)
6370                         old->release_fb->funcs->destroy(old->release_fb);
6371                 goto fail;
6372         }
6373
6374         /* let the connector get through one full cycle before testing */
6375         intel_wait_for_vblank(dev, intel_crtc->pipe);
6376
6377         return true;
6378 fail:
6379         connector->encoder = NULL;
6380         encoder->crtc = NULL;
6381         return false;
6382 }
6383
6384 void intel_release_load_detect_pipe(struct drm_connector *connector,
6385                                     struct intel_load_detect_pipe *old)
6386 {
6387         struct intel_encoder *intel_encoder =
6388                 intel_attached_encoder(connector);
6389         struct drm_encoder *encoder = &intel_encoder->base;
6390
6391         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6392                       connector->base.id, drm_get_connector_name(connector),
6393                       encoder->base.id, drm_get_encoder_name(encoder));
6394
6395         if (old->load_detect_temp) {
6396                 struct drm_crtc *crtc = encoder->crtc;
6397
6398                 to_intel_connector(connector)->new_encoder = NULL;
6399                 intel_encoder->new_crtc = NULL;
6400                 intel_set_mode(crtc, NULL, 0, 0, NULL);
6401
6402                 if (old->release_fb)
6403                         old->release_fb->funcs->destroy(old->release_fb);
6404
6405                 return;
6406         }
6407
6408         /* Switch crtc and encoder back off if necessary */
6409         if (old->dpms_mode != DRM_MODE_DPMS_ON)
6410                 connector->funcs->dpms(connector, old->dpms_mode);
6411 }
6412
6413 /* Returns the clock of the currently programmed mode of the given pipe. */
6414 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6415 {
6416         struct drm_i915_private *dev_priv = dev->dev_private;
6417         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6418         int pipe = intel_crtc->pipe;
6419         u32 dpll = I915_READ(DPLL(pipe));
6420         u32 fp;
6421         intel_clock_t clock;
6422
6423         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6424                 fp = I915_READ(FP0(pipe));
6425         else
6426                 fp = I915_READ(FP1(pipe));
6427
6428         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6429         if (IS_PINEVIEW(dev)) {
6430                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6431                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6432         } else {
6433                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6434                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6435         }
6436
6437         if (!IS_GEN2(dev)) {
6438                 if (IS_PINEVIEW(dev))
6439                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6440                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6441                 else
6442                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6443                                DPLL_FPA01_P1_POST_DIV_SHIFT);
6444
6445                 switch (dpll & DPLL_MODE_MASK) {
6446                 case DPLLB_MODE_DAC_SERIAL:
6447                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6448                                 5 : 10;
6449                         break;
6450                 case DPLLB_MODE_LVDS:
6451                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6452                                 7 : 14;
6453                         break;
6454                 default:
6455                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6456                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
6457                         return 0;
6458                 }
6459
6460                 /* XXX: Handle the 100Mhz refclk */
6461                 intel_clock(dev, 96000, &clock);
6462         } else {
6463                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6464
6465                 if (is_lvds) {
6466                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6467                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
6468                         clock.p2 = 14;
6469
6470                         if ((dpll & PLL_REF_INPUT_MASK) ==
6471                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6472                                 /* XXX: might not be 66MHz */
6473                                 intel_clock(dev, 66000, &clock);
6474                         } else
6475                                 intel_clock(dev, 48000, &clock);
6476                 } else {
6477                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
6478                                 clock.p1 = 2;
6479                         else {
6480                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6481                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6482                         }
6483                         if (dpll & PLL_P2_DIVIDE_BY_4)
6484                                 clock.p2 = 4;
6485                         else
6486                                 clock.p2 = 2;
6487
6488                         intel_clock(dev, 48000, &clock);
6489                 }
6490         }
6491
6492         /* XXX: It would be nice to validate the clocks, but we can't reuse
6493          * i830PllIsValid() because it relies on the xf86_config connector
6494          * configuration being accurate, which it isn't necessarily.
6495          */
6496
6497         return clock.dot;
6498 }
6499
6500 /** Returns the currently programmed mode of the given pipe. */
6501 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6502                                              struct drm_crtc *crtc)
6503 {
6504         struct drm_i915_private *dev_priv = dev->dev_private;
6505         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6506         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
6507         struct drm_display_mode *mode;
6508         int htot = I915_READ(HTOTAL(cpu_transcoder));
6509         int hsync = I915_READ(HSYNC(cpu_transcoder));
6510         int vtot = I915_READ(VTOTAL(cpu_transcoder));
6511         int vsync = I915_READ(VSYNC(cpu_transcoder));
6512
6513         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6514         if (!mode)
6515                 return NULL;
6516
6517         mode->clock = intel_crtc_clock_get(dev, crtc);
6518         mode->hdisplay = (htot & 0xffff) + 1;
6519         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6520         mode->hsync_start = (hsync & 0xffff) + 1;
6521         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6522         mode->vdisplay = (vtot & 0xffff) + 1;
6523         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6524         mode->vsync_start = (vsync & 0xffff) + 1;
6525         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6526
6527         drm_mode_set_name(mode);
6528
6529         return mode;
6530 }
6531
6532 static void intel_increase_pllclock(struct drm_crtc *crtc)
6533 {
6534         struct drm_device *dev = crtc->dev;
6535         drm_i915_private_t *dev_priv = dev->dev_private;
6536         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6537         int pipe = intel_crtc->pipe;
6538         int dpll_reg = DPLL(pipe);
6539         int dpll;
6540
6541         if (HAS_PCH_SPLIT(dev))
6542                 return;
6543
6544         if (!dev_priv->lvds_downclock_avail)
6545                 return;
6546
6547         dpll = I915_READ(dpll_reg);
6548         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6549                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6550
6551                 assert_panel_unlocked(dev_priv, pipe);
6552
6553                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6554                 I915_WRITE(dpll_reg, dpll);
6555                 intel_wait_for_vblank(dev, pipe);
6556
6557                 dpll = I915_READ(dpll_reg);
6558                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6559                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6560         }
6561 }
6562
6563 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6564 {
6565         struct drm_device *dev = crtc->dev;
6566         drm_i915_private_t *dev_priv = dev->dev_private;
6567         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6568
6569         if (HAS_PCH_SPLIT(dev))
6570                 return;
6571
6572         if (!dev_priv->lvds_downclock_avail)
6573                 return;
6574
6575         /*
6576          * Since this is called by a timer, we should never get here in
6577          * the manual case.
6578          */
6579         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6580                 int pipe = intel_crtc->pipe;
6581                 int dpll_reg = DPLL(pipe);
6582                 int dpll;
6583
6584                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6585
6586                 assert_panel_unlocked(dev_priv, pipe);
6587
6588                 dpll = I915_READ(dpll_reg);
6589                 dpll |= DISPLAY_RATE_SELECT_FPA1;
6590                 I915_WRITE(dpll_reg, dpll);
6591                 intel_wait_for_vblank(dev, pipe);
6592                 dpll = I915_READ(dpll_reg);
6593                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6594                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6595         }
6596
6597 }
6598
6599 void intel_mark_busy(struct drm_device *dev)
6600 {
6601         i915_update_gfx_val(dev->dev_private);
6602 }
6603
6604 void intel_mark_idle(struct drm_device *dev)
6605 {
6606 }
6607
6608 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6609 {
6610         struct drm_device *dev = obj->base.dev;
6611         struct drm_crtc *crtc;
6612
6613         if (!i915_powersave)
6614                 return;
6615
6616         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6617                 if (!crtc->fb)
6618                         continue;
6619
6620                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6621                         intel_increase_pllclock(crtc);
6622         }
6623 }
6624
6625 void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
6626 {
6627         struct drm_device *dev = obj->base.dev;
6628         struct drm_crtc *crtc;
6629
6630         if (!i915_powersave)
6631                 return;
6632
6633         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6634                 if (!crtc->fb)
6635                         continue;
6636
6637                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6638                         intel_decrease_pllclock(crtc);
6639         }
6640 }
6641
6642 static void intel_crtc_destroy(struct drm_crtc *crtc)
6643 {
6644         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6645         struct drm_device *dev = crtc->dev;
6646         struct intel_unpin_work *work;
6647         unsigned long flags;
6648
6649         spin_lock_irqsave(&dev->event_lock, flags);
6650         work = intel_crtc->unpin_work;
6651         intel_crtc->unpin_work = NULL;
6652         spin_unlock_irqrestore(&dev->event_lock, flags);
6653
6654         if (work) {
6655                 cancel_work_sync(&work->work);
6656                 kfree(work);
6657         }
6658
6659         drm_crtc_cleanup(crtc);
6660
6661         kfree(intel_crtc);
6662 }
6663
6664 static void intel_unpin_work_fn(struct work_struct *__work)
6665 {
6666         struct intel_unpin_work *work =
6667                 container_of(__work, struct intel_unpin_work, work);
6668
6669         mutex_lock(&work->dev->struct_mutex);
6670         intel_unpin_fb_obj(work->old_fb_obj);
6671         drm_gem_object_unreference(&work->pending_flip_obj->base);
6672         drm_gem_object_unreference(&work->old_fb_obj->base);
6673
6674         intel_update_fbc(work->dev);
6675         mutex_unlock(&work->dev->struct_mutex);
6676         kfree(work);
6677 }
6678
6679 static void do_intel_finish_page_flip(struct drm_device *dev,
6680                                       struct drm_crtc *crtc)
6681 {
6682         drm_i915_private_t *dev_priv = dev->dev_private;
6683         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6684         struct intel_unpin_work *work;
6685         struct drm_i915_gem_object *obj;
6686         struct drm_pending_vblank_event *e;
6687         struct timeval tvbl;
6688         unsigned long flags;
6689
6690         /* Ignore early vblank irqs */
6691         if (intel_crtc == NULL)
6692                 return;
6693
6694         spin_lock_irqsave(&dev->event_lock, flags);
6695         work = intel_crtc->unpin_work;
6696         if (work == NULL || !work->pending) {
6697                 spin_unlock_irqrestore(&dev->event_lock, flags);
6698                 return;
6699         }
6700
6701         intel_crtc->unpin_work = NULL;
6702
6703         if (work->event) {
6704                 e = work->event;
6705                 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
6706
6707                 e->event.tv_sec = tvbl.tv_sec;
6708                 e->event.tv_usec = tvbl.tv_usec;
6709
6710                 list_add_tail(&e->base.link,
6711                               &e->base.file_priv->event_list);
6712                 wake_up_interruptible(&e->base.file_priv->event_wait);
6713         }
6714
6715         drm_vblank_put(dev, intel_crtc->pipe);
6716
6717         spin_unlock_irqrestore(&dev->event_lock, flags);
6718
6719         obj = work->old_fb_obj;
6720
6721         atomic_clear_mask(1 << intel_crtc->plane,
6722                           &obj->pending_flip.counter);
6723
6724         wake_up(&dev_priv->pending_flip_queue);
6725         schedule_work(&work->work);
6726
6727         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6728 }
6729
6730 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6731 {
6732         drm_i915_private_t *dev_priv = dev->dev_private;
6733         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6734
6735         do_intel_finish_page_flip(dev, crtc);
6736 }
6737
6738 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6739 {
6740         drm_i915_private_t *dev_priv = dev->dev_private;
6741         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6742
6743         do_intel_finish_page_flip(dev, crtc);
6744 }
6745
6746 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6747 {
6748         drm_i915_private_t *dev_priv = dev->dev_private;
6749         struct intel_crtc *intel_crtc =
6750                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6751         unsigned long flags;
6752
6753         spin_lock_irqsave(&dev->event_lock, flags);
6754         if (intel_crtc->unpin_work) {
6755                 if ((++intel_crtc->unpin_work->pending) > 1)
6756                         DRM_ERROR("Prepared flip multiple times\n");
6757         } else {
6758                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6759         }
6760         spin_unlock_irqrestore(&dev->event_lock, flags);
6761 }
6762
6763 static int intel_gen2_queue_flip(struct drm_device *dev,
6764                                  struct drm_crtc *crtc,
6765                                  struct drm_framebuffer *fb,
6766                                  struct drm_i915_gem_object *obj)
6767 {
6768         struct drm_i915_private *dev_priv = dev->dev_private;
6769         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6770         u32 flip_mask;
6771         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6772         int ret;
6773
6774         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6775         if (ret)
6776                 goto err;
6777
6778         ret = intel_ring_begin(ring, 6);
6779         if (ret)
6780                 goto err_unpin;
6781
6782         /* Can't queue multiple flips, so wait for the previous
6783          * one to finish before executing the next.
6784          */
6785         if (intel_crtc->plane)
6786                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6787         else
6788                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6789         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6790         intel_ring_emit(ring, MI_NOOP);
6791         intel_ring_emit(ring, MI_DISPLAY_FLIP |
6792                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6793         intel_ring_emit(ring, fb->pitches[0]);
6794         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6795         intel_ring_emit(ring, 0); /* aux display base address, unused */
6796         intel_ring_advance(ring);
6797         return 0;
6798
6799 err_unpin:
6800         intel_unpin_fb_obj(obj);
6801 err:
6802         return ret;
6803 }
6804
6805 static int intel_gen3_queue_flip(struct drm_device *dev,
6806                                  struct drm_crtc *crtc,
6807                                  struct drm_framebuffer *fb,
6808                                  struct drm_i915_gem_object *obj)
6809 {
6810         struct drm_i915_private *dev_priv = dev->dev_private;
6811         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6812         u32 flip_mask;
6813         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6814         int ret;
6815
6816         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6817         if (ret)
6818                 goto err;
6819
6820         ret = intel_ring_begin(ring, 6);
6821         if (ret)
6822                 goto err_unpin;
6823
6824         if (intel_crtc->plane)
6825                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6826         else
6827                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6828         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6829         intel_ring_emit(ring, MI_NOOP);
6830         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
6831                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6832         intel_ring_emit(ring, fb->pitches[0]);
6833         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6834         intel_ring_emit(ring, MI_NOOP);
6835
6836         intel_ring_advance(ring);
6837         return 0;
6838
6839 err_unpin:
6840         intel_unpin_fb_obj(obj);
6841 err:
6842         return ret;
6843 }
6844
6845 static int intel_gen4_queue_flip(struct drm_device *dev,
6846                                  struct drm_crtc *crtc,
6847                                  struct drm_framebuffer *fb,
6848                                  struct drm_i915_gem_object *obj)
6849 {
6850         struct drm_i915_private *dev_priv = dev->dev_private;
6851         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6852         uint32_t pf, pipesrc;
6853         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6854         int ret;
6855
6856         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6857         if (ret)
6858                 goto err;
6859
6860         ret = intel_ring_begin(ring, 4);
6861         if (ret)
6862                 goto err_unpin;
6863
6864         /* i965+ uses the linear or tiled offsets from the
6865          * Display Registers (which do not change across a page-flip)
6866          * so we need only reprogram the base address.
6867          */
6868         intel_ring_emit(ring, MI_DISPLAY_FLIP |
6869                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6870         intel_ring_emit(ring, fb->pitches[0]);
6871         intel_ring_emit(ring,
6872                         (obj->gtt_offset + intel_crtc->dspaddr_offset) |
6873                         obj->tiling_mode);
6874
6875         /* XXX Enabling the panel-fitter across page-flip is so far
6876          * untested on non-native modes, so ignore it for now.
6877          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6878          */
6879         pf = 0;
6880         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6881         intel_ring_emit(ring, pf | pipesrc);
6882         intel_ring_advance(ring);
6883         return 0;
6884
6885 err_unpin:
6886         intel_unpin_fb_obj(obj);
6887 err:
6888         return ret;
6889 }
6890
6891 static int intel_gen6_queue_flip(struct drm_device *dev,
6892                                  struct drm_crtc *crtc,
6893                                  struct drm_framebuffer *fb,
6894                                  struct drm_i915_gem_object *obj)
6895 {
6896         struct drm_i915_private *dev_priv = dev->dev_private;
6897         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6898         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6899         uint32_t pf, pipesrc;
6900         int ret;
6901
6902         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6903         if (ret)
6904                 goto err;
6905
6906         ret = intel_ring_begin(ring, 4);
6907         if (ret)
6908                 goto err_unpin;
6909
6910         intel_ring_emit(ring, MI_DISPLAY_FLIP |
6911                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6912         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
6913         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6914
6915         /* Contrary to the suggestions in the documentation,
6916          * "Enable Panel Fitter" does not seem to be required when page
6917          * flipping with a non-native mode, and worse causes a normal
6918          * modeset to fail.
6919          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6920          */
6921         pf = 0;
6922         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6923         intel_ring_emit(ring, pf | pipesrc);
6924         intel_ring_advance(ring);
6925         return 0;
6926
6927 err_unpin:
6928         intel_unpin_fb_obj(obj);
6929 err:
6930         return ret;
6931 }
6932
6933 /*
6934  * On gen7 we currently use the blit ring because (in early silicon at least)
6935  * the render ring doesn't give us interrpts for page flip completion, which
6936  * means clients will hang after the first flip is queued.  Fortunately the
6937  * blit ring generates interrupts properly, so use it instead.
6938  */
6939 static int intel_gen7_queue_flip(struct drm_device *dev,
6940                                  struct drm_crtc *crtc,
6941                                  struct drm_framebuffer *fb,
6942                                  struct drm_i915_gem_object *obj)
6943 {
6944         struct drm_i915_private *dev_priv = dev->dev_private;
6945         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6946         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
6947         uint32_t plane_bit = 0;
6948         int ret;
6949
6950         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6951         if (ret)
6952                 goto err;
6953
6954         switch(intel_crtc->plane) {
6955         case PLANE_A:
6956                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
6957                 break;
6958         case PLANE_B:
6959                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
6960                 break;
6961         case PLANE_C:
6962                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
6963                 break;
6964         default:
6965                 WARN_ONCE(1, "unknown plane in flip command\n");
6966                 ret = -ENODEV;
6967                 goto err_unpin;
6968         }
6969
6970         ret = intel_ring_begin(ring, 4);
6971         if (ret)
6972                 goto err_unpin;
6973
6974         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
6975         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
6976         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6977         intel_ring_emit(ring, (MI_NOOP));
6978         intel_ring_advance(ring);
6979         return 0;
6980
6981 err_unpin:
6982         intel_unpin_fb_obj(obj);
6983 err:
6984         return ret;
6985 }
6986
6987 static int intel_default_queue_flip(struct drm_device *dev,
6988                                     struct drm_crtc *crtc,
6989                                     struct drm_framebuffer *fb,
6990                                     struct drm_i915_gem_object *obj)
6991 {
6992         return -ENODEV;
6993 }
6994
6995 static int intel_crtc_page_flip(struct drm_crtc *crtc,
6996                                 struct drm_framebuffer *fb,
6997                                 struct drm_pending_vblank_event *event)
6998 {
6999         struct drm_device *dev = crtc->dev;
7000         struct drm_i915_private *dev_priv = dev->dev_private;
7001         struct intel_framebuffer *intel_fb;
7002         struct drm_i915_gem_object *obj;
7003         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7004         struct intel_unpin_work *work;
7005         unsigned long flags;
7006         int ret;
7007
7008         /* Can't change pixel format via MI display flips. */
7009         if (fb->pixel_format != crtc->fb->pixel_format)
7010                 return -EINVAL;
7011
7012         /*
7013          * TILEOFF/LINOFF registers can't be changed via MI display flips.
7014          * Note that pitch changes could also affect these register.
7015          */
7016         if (INTEL_INFO(dev)->gen > 3 &&
7017             (fb->offsets[0] != crtc->fb->offsets[0] ||
7018              fb->pitches[0] != crtc->fb->pitches[0]))
7019                 return -EINVAL;
7020
7021         work = kzalloc(sizeof *work, GFP_KERNEL);
7022         if (work == NULL)
7023                 return -ENOMEM;
7024
7025         work->event = event;
7026         work->dev = crtc->dev;
7027         intel_fb = to_intel_framebuffer(crtc->fb);
7028         work->old_fb_obj = intel_fb->obj;
7029         INIT_WORK(&work->work, intel_unpin_work_fn);
7030
7031         ret = drm_vblank_get(dev, intel_crtc->pipe);
7032         if (ret)
7033                 goto free_work;
7034
7035         /* We borrow the event spin lock for protecting unpin_work */
7036         spin_lock_irqsave(&dev->event_lock, flags);
7037         if (intel_crtc->unpin_work) {
7038                 spin_unlock_irqrestore(&dev->event_lock, flags);
7039                 kfree(work);
7040                 drm_vblank_put(dev, intel_crtc->pipe);
7041
7042                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7043                 return -EBUSY;
7044         }
7045         intel_crtc->unpin_work = work;
7046         spin_unlock_irqrestore(&dev->event_lock, flags);
7047
7048         intel_fb = to_intel_framebuffer(fb);
7049         obj = intel_fb->obj;
7050
7051         ret = i915_mutex_lock_interruptible(dev);
7052         if (ret)
7053                 goto cleanup;
7054
7055         /* Reference the objects for the scheduled work. */
7056         drm_gem_object_reference(&work->old_fb_obj->base);
7057         drm_gem_object_reference(&obj->base);
7058
7059         crtc->fb = fb;
7060
7061         work->pending_flip_obj = obj;
7062
7063         work->enable_stall_check = true;
7064
7065         /* Block clients from rendering to the new back buffer until
7066          * the flip occurs and the object is no longer visible.
7067          */
7068         atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7069
7070         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7071         if (ret)
7072                 goto cleanup_pending;
7073
7074         intel_disable_fbc(dev);
7075         intel_mark_fb_busy(obj);
7076         mutex_unlock(&dev->struct_mutex);
7077
7078         trace_i915_flip_request(intel_crtc->plane, obj);
7079
7080         return 0;
7081
7082 cleanup_pending:
7083         atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7084         drm_gem_object_unreference(&work->old_fb_obj->base);
7085         drm_gem_object_unreference(&obj->base);
7086         mutex_unlock(&dev->struct_mutex);
7087
7088 cleanup:
7089         spin_lock_irqsave(&dev->event_lock, flags);
7090         intel_crtc->unpin_work = NULL;
7091         spin_unlock_irqrestore(&dev->event_lock, flags);
7092
7093         drm_vblank_put(dev, intel_crtc->pipe);
7094 free_work:
7095         kfree(work);
7096
7097         return ret;
7098 }
7099
7100 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7101         .mode_set_base_atomic = intel_pipe_set_base_atomic,
7102         .load_lut = intel_crtc_load_lut,
7103         .disable = intel_crtc_noop,
7104 };
7105
7106 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
7107 {
7108         struct intel_encoder *other_encoder;
7109         struct drm_crtc *crtc = &encoder->new_crtc->base;
7110
7111         if (WARN_ON(!crtc))
7112                 return false;
7113
7114         list_for_each_entry(other_encoder,
7115                             &crtc->dev->mode_config.encoder_list,
7116                             base.head) {
7117
7118                 if (&other_encoder->new_crtc->base != crtc ||
7119                     encoder == other_encoder)
7120                         continue;
7121                 else
7122                         return true;
7123         }
7124
7125         return false;
7126 }
7127
7128 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7129                                   struct drm_crtc *crtc)
7130 {
7131         struct drm_device *dev;
7132         struct drm_crtc *tmp;
7133         int crtc_mask = 1;
7134
7135         WARN(!crtc, "checking null crtc?\n");
7136
7137         dev = crtc->dev;
7138
7139         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7140                 if (tmp == crtc)
7141                         break;
7142                 crtc_mask <<= 1;
7143         }
7144
7145         if (encoder->possible_crtcs & crtc_mask)
7146                 return true;
7147         return false;
7148 }
7149
7150 /**
7151  * intel_modeset_update_staged_output_state
7152  *
7153  * Updates the staged output configuration state, e.g. after we've read out the
7154  * current hw state.
7155  */
7156 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7157 {
7158         struct intel_encoder *encoder;
7159         struct intel_connector *connector;
7160
7161         list_for_each_entry(connector, &dev->mode_config.connector_list,
7162                             base.head) {
7163                 connector->new_encoder =
7164                         to_intel_encoder(connector->base.encoder);
7165         }
7166
7167         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7168                             base.head) {
7169                 encoder->new_crtc =
7170                         to_intel_crtc(encoder->base.crtc);
7171         }
7172 }
7173
7174 /**
7175  * intel_modeset_commit_output_state
7176  *
7177  * This function copies the stage display pipe configuration to the real one.
7178  */
7179 static void intel_modeset_commit_output_state(struct drm_device *dev)
7180 {
7181         struct intel_encoder *encoder;
7182         struct intel_connector *connector;
7183
7184         list_for_each_entry(connector, &dev->mode_config.connector_list,
7185                             base.head) {
7186                 connector->base.encoder = &connector->new_encoder->base;
7187         }
7188
7189         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7190                             base.head) {
7191                 encoder->base.crtc = &encoder->new_crtc->base;
7192         }
7193 }
7194
7195 static struct drm_display_mode *
7196 intel_modeset_adjusted_mode(struct drm_crtc *crtc,
7197                             struct drm_display_mode *mode)
7198 {
7199         struct drm_device *dev = crtc->dev;
7200         struct drm_display_mode *adjusted_mode;
7201         struct drm_encoder_helper_funcs *encoder_funcs;
7202         struct intel_encoder *encoder;
7203
7204         adjusted_mode = drm_mode_duplicate(dev, mode);
7205         if (!adjusted_mode)
7206                 return ERR_PTR(-ENOMEM);
7207
7208         /* Pass our mode to the connectors and the CRTC to give them a chance to
7209          * adjust it according to limitations or connector properties, and also
7210          * a chance to reject the mode entirely.
7211          */
7212         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7213                             base.head) {
7214
7215                 if (&encoder->new_crtc->base != crtc)
7216                         continue;
7217                 encoder_funcs = encoder->base.helper_private;
7218                 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
7219                                                 adjusted_mode))) {
7220                         DRM_DEBUG_KMS("Encoder fixup failed\n");
7221                         goto fail;
7222                 }
7223         }
7224
7225         if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
7226                 DRM_DEBUG_KMS("CRTC fixup failed\n");
7227                 goto fail;
7228         }
7229         DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7230
7231         return adjusted_mode;
7232 fail:
7233         drm_mode_destroy(dev, adjusted_mode);
7234         return ERR_PTR(-EINVAL);
7235 }
7236
7237 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7238  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7239 static void
7240 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7241                              unsigned *prepare_pipes, unsigned *disable_pipes)
7242 {
7243         struct intel_crtc *intel_crtc;
7244         struct drm_device *dev = crtc->dev;
7245         struct intel_encoder *encoder;
7246         struct intel_connector *connector;
7247         struct drm_crtc *tmp_crtc;
7248
7249         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7250
7251         /* Check which crtcs have changed outputs connected to them, these need
7252          * to be part of the prepare_pipes mask. We don't (yet) support global
7253          * modeset across multiple crtcs, so modeset_pipes will only have one
7254          * bit set at most. */
7255         list_for_each_entry(connector, &dev->mode_config.connector_list,
7256                             base.head) {
7257                 if (connector->base.encoder == &connector->new_encoder->base)
7258                         continue;
7259
7260                 if (connector->base.encoder) {
7261                         tmp_crtc = connector->base.encoder->crtc;
7262
7263                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7264                 }
7265
7266                 if (connector->new_encoder)
7267                         *prepare_pipes |=
7268                                 1 << connector->new_encoder->new_crtc->pipe;
7269         }
7270
7271         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7272                             base.head) {
7273                 if (encoder->base.crtc == &encoder->new_crtc->base)
7274                         continue;
7275
7276                 if (encoder->base.crtc) {
7277                         tmp_crtc = encoder->base.crtc;
7278
7279                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7280                 }
7281
7282                 if (encoder->new_crtc)
7283                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7284         }
7285
7286         /* Check for any pipes that will be fully disabled ... */
7287         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7288                             base.head) {
7289                 bool used = false;
7290
7291                 /* Don't try to disable disabled crtcs. */
7292                 if (!intel_crtc->base.enabled)
7293                         continue;
7294
7295                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7296                                     base.head) {
7297                         if (encoder->new_crtc == intel_crtc)
7298                                 used = true;
7299                 }
7300
7301                 if (!used)
7302                         *disable_pipes |= 1 << intel_crtc->pipe;
7303         }
7304
7305
7306         /* set_mode is also used to update properties on life display pipes. */
7307         intel_crtc = to_intel_crtc(crtc);
7308         if (crtc->enabled)
7309                 *prepare_pipes |= 1 << intel_crtc->pipe;
7310
7311         /* We only support modeset on one single crtc, hence we need to do that
7312          * only for the passed in crtc iff we change anything else than just
7313          * disable crtcs.
7314          *
7315          * This is actually not true, to be fully compatible with the old crtc
7316          * helper we automatically disable _any_ output (i.e. doesn't need to be
7317          * connected to the crtc we're modesetting on) if it's disconnected.
7318          * Which is a rather nutty api (since changed the output configuration
7319          * without userspace's explicit request can lead to confusion), but
7320          * alas. Hence we currently need to modeset on all pipes we prepare. */
7321         if (*prepare_pipes)
7322                 *modeset_pipes = *prepare_pipes;
7323
7324         /* ... and mask these out. */
7325         *modeset_pipes &= ~(*disable_pipes);
7326         *prepare_pipes &= ~(*disable_pipes);
7327 }
7328
7329 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7330 {
7331         struct drm_encoder *encoder;
7332         struct drm_device *dev = crtc->dev;
7333
7334         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7335                 if (encoder->crtc == crtc)
7336                         return true;
7337
7338         return false;
7339 }
7340
7341 static void
7342 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7343 {
7344         struct intel_encoder *intel_encoder;
7345         struct intel_crtc *intel_crtc;
7346         struct drm_connector *connector;
7347
7348         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7349                             base.head) {
7350                 if (!intel_encoder->base.crtc)
7351                         continue;
7352
7353                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7354
7355                 if (prepare_pipes & (1 << intel_crtc->pipe))
7356                         intel_encoder->connectors_active = false;
7357         }
7358
7359         intel_modeset_commit_output_state(dev);
7360
7361         /* Update computed state. */
7362         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7363                             base.head) {
7364                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7365         }
7366
7367         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7368                 if (!connector->encoder || !connector->encoder->crtc)
7369                         continue;
7370
7371                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7372
7373                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
7374                         struct drm_property *dpms_property =
7375                                 dev->mode_config.dpms_property;
7376
7377                         connector->dpms = DRM_MODE_DPMS_ON;
7378                         drm_connector_property_set_value(connector,
7379                                                          dpms_property,
7380                                                          DRM_MODE_DPMS_ON);
7381
7382                         intel_encoder = to_intel_encoder(connector->encoder);
7383                         intel_encoder->connectors_active = true;
7384                 }
7385         }
7386
7387 }
7388
7389 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7390         list_for_each_entry((intel_crtc), \
7391                             &(dev)->mode_config.crtc_list, \
7392                             base.head) \
7393                 if (mask & (1 <<(intel_crtc)->pipe)) \
7394
7395 void
7396 intel_modeset_check_state(struct drm_device *dev)
7397 {
7398         struct intel_crtc *crtc;
7399         struct intel_encoder *encoder;
7400         struct intel_connector *connector;
7401
7402         list_for_each_entry(connector, &dev->mode_config.connector_list,
7403                             base.head) {
7404                 /* This also checks the encoder/connector hw state with the
7405                  * ->get_hw_state callbacks. */
7406                 intel_connector_check_state(connector);
7407
7408                 WARN(&connector->new_encoder->base != connector->base.encoder,
7409                      "connector's staged encoder doesn't match current encoder\n");
7410         }
7411
7412         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7413                             base.head) {
7414                 bool enabled = false;
7415                 bool active = false;
7416                 enum pipe pipe, tracked_pipe;
7417
7418                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7419                               encoder->base.base.id,
7420                               drm_get_encoder_name(&encoder->base));
7421
7422                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7423                      "encoder's stage crtc doesn't match current crtc\n");
7424                 WARN(encoder->connectors_active && !encoder->base.crtc,
7425                      "encoder's active_connectors set, but no crtc\n");
7426
7427                 list_for_each_entry(connector, &dev->mode_config.connector_list,
7428                                     base.head) {
7429                         if (connector->base.encoder != &encoder->base)
7430                                 continue;
7431                         enabled = true;
7432                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7433                                 active = true;
7434                 }
7435                 WARN(!!encoder->base.crtc != enabled,
7436                      "encoder's enabled state mismatch "
7437                      "(expected %i, found %i)\n",
7438                      !!encoder->base.crtc, enabled);
7439                 WARN(active && !encoder->base.crtc,
7440                      "active encoder with no crtc\n");
7441
7442                 WARN(encoder->connectors_active != active,
7443                      "encoder's computed active state doesn't match tracked active state "
7444                      "(expected %i, found %i)\n", active, encoder->connectors_active);
7445
7446                 active = encoder->get_hw_state(encoder, &pipe);
7447                 WARN(active != encoder->connectors_active,
7448                      "encoder's hw state doesn't match sw tracking "
7449                      "(expected %i, found %i)\n",
7450                      encoder->connectors_active, active);
7451
7452                 if (!encoder->base.crtc)
7453                         continue;
7454
7455                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7456                 WARN(active && pipe != tracked_pipe,
7457                      "active encoder's pipe doesn't match"
7458                      "(expected %i, found %i)\n",
7459                      tracked_pipe, pipe);
7460
7461         }
7462
7463         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7464                             base.head) {
7465                 bool enabled = false;
7466                 bool active = false;
7467
7468                 DRM_DEBUG_KMS("[CRTC:%d]\n",
7469                               crtc->base.base.id);
7470
7471                 WARN(crtc->active && !crtc->base.enabled,
7472                      "active crtc, but not enabled in sw tracking\n");
7473
7474                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7475                                     base.head) {
7476                         if (encoder->base.crtc != &crtc->base)
7477                                 continue;
7478                         enabled = true;
7479                         if (encoder->connectors_active)
7480                                 active = true;
7481                 }
7482                 WARN(active != crtc->active,
7483                      "crtc's computed active state doesn't match tracked active state "
7484                      "(expected %i, found %i)\n", active, crtc->active);
7485                 WARN(enabled != crtc->base.enabled,
7486                      "crtc's computed enabled state doesn't match tracked enabled state "
7487                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7488
7489                 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7490         }
7491 }
7492
7493 bool intel_set_mode(struct drm_crtc *crtc,
7494                     struct drm_display_mode *mode,
7495                     int x, int y, struct drm_framebuffer *fb)
7496 {
7497         struct drm_device *dev = crtc->dev;
7498         drm_i915_private_t *dev_priv = dev->dev_private;
7499         struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
7500         struct drm_encoder_helper_funcs *encoder_funcs;
7501         struct drm_encoder *encoder;
7502         struct intel_crtc *intel_crtc;
7503         unsigned disable_pipes, prepare_pipes, modeset_pipes;
7504         bool ret = true;
7505
7506         intel_modeset_affected_pipes(crtc, &modeset_pipes,
7507                                      &prepare_pipes, &disable_pipes);
7508
7509         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7510                       modeset_pipes, prepare_pipes, disable_pipes);
7511
7512         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7513                 intel_crtc_disable(&intel_crtc->base);
7514
7515         saved_hwmode = crtc->hwmode;
7516         saved_mode = crtc->mode;
7517
7518         /* Hack: Because we don't (yet) support global modeset on multiple
7519          * crtcs, we don't keep track of the new mode for more than one crtc.
7520          * Hence simply check whether any bit is set in modeset_pipes in all the
7521          * pieces of code that are not yet converted to deal with mutliple crtcs
7522          * changing their mode at the same time. */
7523         adjusted_mode = NULL;
7524         if (modeset_pipes) {
7525                 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7526                 if (IS_ERR(adjusted_mode)) {
7527                         return false;
7528                 }
7529         }
7530
7531         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7532                 if (intel_crtc->base.enabled)
7533                         dev_priv->display.crtc_disable(&intel_crtc->base);
7534         }
7535
7536         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7537          * to set it here already despite that we pass it down the callchain.
7538          */
7539         if (modeset_pipes)
7540                 crtc->mode = *mode;
7541
7542         /* Only after disabling all output pipelines that will be changed can we
7543          * update the the output configuration. */
7544         intel_modeset_update_state(dev, prepare_pipes);
7545
7546         /* Set up the DPLL and any encoders state that needs to adjust or depend
7547          * on the DPLL.
7548          */
7549         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7550                 ret = !intel_crtc_mode_set(&intel_crtc->base,
7551                                            mode, adjusted_mode,
7552                                            x, y, fb);
7553                 if (!ret)
7554                     goto done;
7555
7556                 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
7557
7558                         if (encoder->crtc != &intel_crtc->base)
7559                                 continue;
7560
7561                         DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
7562                                 encoder->base.id, drm_get_encoder_name(encoder),
7563                                 mode->base.id, mode->name);
7564                         encoder_funcs = encoder->helper_private;
7565                         encoder_funcs->mode_set(encoder, mode, adjusted_mode);
7566                 }
7567         }
7568
7569         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7570         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7571                 dev_priv->display.crtc_enable(&intel_crtc->base);
7572
7573         if (modeset_pipes) {
7574                 /* Store real post-adjustment hardware mode. */
7575                 crtc->hwmode = *adjusted_mode;
7576
7577                 /* Calculate and store various constants which
7578                  * are later needed by vblank and swap-completion
7579                  * timestamping. They are derived from true hwmode.
7580                  */
7581                 drm_calc_timestamping_constants(crtc);
7582         }
7583
7584         /* FIXME: add subpixel order */
7585 done:
7586         drm_mode_destroy(dev, adjusted_mode);
7587         if (!ret && crtc->enabled) {
7588                 crtc->hwmode = saved_hwmode;
7589                 crtc->mode = saved_mode;
7590         } else {
7591                 intel_modeset_check_state(dev);
7592         }
7593
7594         return ret;
7595 }
7596
7597 #undef for_each_intel_crtc_masked
7598
7599 static void intel_set_config_free(struct intel_set_config *config)
7600 {
7601         if (!config)
7602                 return;
7603
7604         kfree(config->save_connector_encoders);
7605         kfree(config->save_encoder_crtcs);
7606         kfree(config);
7607 }
7608
7609 static int intel_set_config_save_state(struct drm_device *dev,
7610                                        struct intel_set_config *config)
7611 {
7612         struct drm_encoder *encoder;
7613         struct drm_connector *connector;
7614         int count;
7615
7616         config->save_encoder_crtcs =
7617                 kcalloc(dev->mode_config.num_encoder,
7618                         sizeof(struct drm_crtc *), GFP_KERNEL);
7619         if (!config->save_encoder_crtcs)
7620                 return -ENOMEM;
7621
7622         config->save_connector_encoders =
7623                 kcalloc(dev->mode_config.num_connector,
7624                         sizeof(struct drm_encoder *), GFP_KERNEL);
7625         if (!config->save_connector_encoders)
7626                 return -ENOMEM;
7627
7628         /* Copy data. Note that driver private data is not affected.
7629          * Should anything bad happen only the expected state is
7630          * restored, not the drivers personal bookkeeping.
7631          */
7632         count = 0;
7633         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
7634                 config->save_encoder_crtcs[count++] = encoder->crtc;
7635         }
7636
7637         count = 0;
7638         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7639                 config->save_connector_encoders[count++] = connector->encoder;
7640         }
7641
7642         return 0;
7643 }
7644
7645 static void intel_set_config_restore_state(struct drm_device *dev,
7646                                            struct intel_set_config *config)
7647 {
7648         struct intel_encoder *encoder;
7649         struct intel_connector *connector;
7650         int count;
7651
7652         count = 0;
7653         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7654                 encoder->new_crtc =
7655                         to_intel_crtc(config->save_encoder_crtcs[count++]);
7656         }
7657
7658         count = 0;
7659         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7660                 connector->new_encoder =
7661                         to_intel_encoder(config->save_connector_encoders[count++]);
7662         }
7663 }
7664
7665 static void
7666 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7667                                       struct intel_set_config *config)
7668 {
7669
7670         /* We should be able to check here if the fb has the same properties
7671          * and then just flip_or_move it */
7672         if (set->crtc->fb != set->fb) {
7673                 /* If we have no fb then treat it as a full mode set */
7674                 if (set->crtc->fb == NULL) {
7675                         DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7676                         config->mode_changed = true;
7677                 } else if (set->fb == NULL) {
7678                         config->mode_changed = true;
7679                 } else if (set->fb->depth != set->crtc->fb->depth) {
7680                         config->mode_changed = true;
7681                 } else if (set->fb->bits_per_pixel !=
7682                            set->crtc->fb->bits_per_pixel) {
7683                         config->mode_changed = true;
7684                 } else
7685                         config->fb_changed = true;
7686         }
7687
7688         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
7689                 config->fb_changed = true;
7690
7691         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7692                 DRM_DEBUG_KMS("modes are different, full mode set\n");
7693                 drm_mode_debug_printmodeline(&set->crtc->mode);
7694                 drm_mode_debug_printmodeline(set->mode);
7695                 config->mode_changed = true;
7696         }
7697 }
7698
7699 static int
7700 intel_modeset_stage_output_state(struct drm_device *dev,
7701                                  struct drm_mode_set *set,
7702                                  struct intel_set_config *config)
7703 {
7704         struct drm_crtc *new_crtc;
7705         struct intel_connector *connector;
7706         struct intel_encoder *encoder;
7707         int count, ro;
7708
7709         /* The upper layers ensure that we either disabl a crtc or have a list
7710          * of connectors. For paranoia, double-check this. */
7711         WARN_ON(!set->fb && (set->num_connectors != 0));
7712         WARN_ON(set->fb && (set->num_connectors == 0));
7713
7714         count = 0;
7715         list_for_each_entry(connector, &dev->mode_config.connector_list,
7716                             base.head) {
7717                 /* Otherwise traverse passed in connector list and get encoders
7718                  * for them. */
7719                 for (ro = 0; ro < set->num_connectors; ro++) {
7720                         if (set->connectors[ro] == &connector->base) {
7721                                 connector->new_encoder = connector->encoder;
7722                                 break;
7723                         }
7724                 }
7725
7726                 /* If we disable the crtc, disable all its connectors. Also, if
7727                  * the connector is on the changing crtc but not on the new
7728                  * connector list, disable it. */
7729                 if ((!set->fb || ro == set->num_connectors) &&
7730                     connector->base.encoder &&
7731                     connector->base.encoder->crtc == set->crtc) {
7732                         connector->new_encoder = NULL;
7733
7734                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7735                                 connector->base.base.id,
7736                                 drm_get_connector_name(&connector->base));
7737                 }
7738
7739
7740                 if (&connector->new_encoder->base != connector->base.encoder) {
7741                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
7742                         config->mode_changed = true;
7743                 }
7744
7745                 /* Disable all disconnected encoders. */
7746                 if (connector->base.status == connector_status_disconnected)
7747                         connector->new_encoder = NULL;
7748         }
7749         /* connector->new_encoder is now updated for all connectors. */
7750
7751         /* Update crtc of enabled connectors. */
7752         count = 0;
7753         list_for_each_entry(connector, &dev->mode_config.connector_list,
7754                             base.head) {
7755                 if (!connector->new_encoder)
7756                         continue;
7757
7758                 new_crtc = connector->new_encoder->base.crtc;
7759
7760                 for (ro = 0; ro < set->num_connectors; ro++) {
7761                         if (set->connectors[ro] == &connector->base)
7762                                 new_crtc = set->crtc;
7763                 }
7764
7765                 /* Make sure the new CRTC will work with the encoder */
7766                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
7767                                            new_crtc)) {
7768                         return -EINVAL;
7769                 }
7770                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
7771
7772                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
7773                         connector->base.base.id,
7774                         drm_get_connector_name(&connector->base),
7775                         new_crtc->base.id);
7776         }
7777
7778         /* Check for any encoders that needs to be disabled. */
7779         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7780                             base.head) {
7781                 list_for_each_entry(connector,
7782                                     &dev->mode_config.connector_list,
7783                                     base.head) {
7784                         if (connector->new_encoder == encoder) {
7785                                 WARN_ON(!connector->new_encoder->new_crtc);
7786
7787                                 goto next_encoder;
7788                         }
7789                 }
7790                 encoder->new_crtc = NULL;
7791 next_encoder:
7792                 /* Only now check for crtc changes so we don't miss encoders
7793                  * that will be disabled. */
7794                 if (&encoder->new_crtc->base != encoder->base.crtc) {
7795                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
7796                         config->mode_changed = true;
7797                 }
7798         }
7799         /* Now we've also updated encoder->new_crtc for all encoders. */
7800
7801         return 0;
7802 }
7803
7804 static int intel_crtc_set_config(struct drm_mode_set *set)
7805 {
7806         struct drm_device *dev;
7807         struct drm_mode_set save_set;
7808         struct intel_set_config *config;
7809         int ret;
7810
7811         BUG_ON(!set);
7812         BUG_ON(!set->crtc);
7813         BUG_ON(!set->crtc->helper_private);
7814
7815         if (!set->mode)
7816                 set->fb = NULL;
7817
7818         /* The fb helper likes to play gross jokes with ->mode_set_config.
7819          * Unfortunately the crtc helper doesn't do much at all for this case,
7820          * so we have to cope with this madness until the fb helper is fixed up. */
7821         if (set->fb && set->num_connectors == 0)
7822                 return 0;
7823
7824         if (set->fb) {
7825                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
7826                                 set->crtc->base.id, set->fb->base.id,
7827                                 (int)set->num_connectors, set->x, set->y);
7828         } else {
7829                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
7830         }
7831
7832         dev = set->crtc->dev;
7833
7834         ret = -ENOMEM;
7835         config = kzalloc(sizeof(*config), GFP_KERNEL);
7836         if (!config)
7837                 goto out_config;
7838
7839         ret = intel_set_config_save_state(dev, config);
7840         if (ret)
7841                 goto out_config;
7842
7843         save_set.crtc = set->crtc;
7844         save_set.mode = &set->crtc->mode;
7845         save_set.x = set->crtc->x;
7846         save_set.y = set->crtc->y;
7847         save_set.fb = set->crtc->fb;
7848
7849         /* Compute whether we need a full modeset, only an fb base update or no
7850          * change at all. In the future we might also check whether only the
7851          * mode changed, e.g. for LVDS where we only change the panel fitter in
7852          * such cases. */
7853         intel_set_config_compute_mode_changes(set, config);
7854
7855         ret = intel_modeset_stage_output_state(dev, set, config);
7856         if (ret)
7857                 goto fail;
7858
7859         if (config->mode_changed) {
7860                 if (set->mode) {
7861                         DRM_DEBUG_KMS("attempting to set mode from"
7862                                         " userspace\n");
7863                         drm_mode_debug_printmodeline(set->mode);
7864                 }
7865
7866                 if (!intel_set_mode(set->crtc, set->mode,
7867                                     set->x, set->y, set->fb)) {
7868                         DRM_ERROR("failed to set mode on [CRTC:%d]\n",
7869                                   set->crtc->base.id);
7870                         ret = -EINVAL;
7871                         goto fail;
7872                 }
7873         } else if (config->fb_changed) {
7874                 ret = intel_pipe_set_base(set->crtc,
7875                                           set->x, set->y, set->fb);
7876         }
7877
7878         intel_set_config_free(config);
7879
7880         return 0;
7881
7882 fail:
7883         intel_set_config_restore_state(dev, config);
7884
7885         /* Try to restore the config */
7886         if (config->mode_changed &&
7887             !intel_set_mode(save_set.crtc, save_set.mode,
7888                             save_set.x, save_set.y, save_set.fb))
7889                 DRM_ERROR("failed to restore config after modeset failure\n");
7890
7891 out_config:
7892         intel_set_config_free(config);
7893         return ret;
7894 }
7895
7896 static const struct drm_crtc_funcs intel_crtc_funcs = {
7897         .cursor_set = intel_crtc_cursor_set,
7898         .cursor_move = intel_crtc_cursor_move,
7899         .gamma_set = intel_crtc_gamma_set,
7900         .set_config = intel_crtc_set_config,
7901         .destroy = intel_crtc_destroy,
7902         .page_flip = intel_crtc_page_flip,
7903 };
7904
7905 static void intel_cpu_pll_init(struct drm_device *dev)
7906 {
7907         if (IS_HASWELL(dev))
7908                 intel_ddi_pll_init(dev);
7909 }
7910
7911 static void intel_pch_pll_init(struct drm_device *dev)
7912 {
7913         drm_i915_private_t *dev_priv = dev->dev_private;
7914         int i;
7915
7916         if (dev_priv->num_pch_pll == 0) {
7917                 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
7918                 return;
7919         }
7920
7921         for (i = 0; i < dev_priv->num_pch_pll; i++) {
7922                 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
7923                 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
7924                 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
7925         }
7926 }
7927
7928 static void intel_crtc_init(struct drm_device *dev, int pipe)
7929 {
7930         drm_i915_private_t *dev_priv = dev->dev_private;
7931         struct intel_crtc *intel_crtc;
7932         int i;
7933
7934         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7935         if (intel_crtc == NULL)
7936                 return;
7937
7938         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7939
7940         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
7941         for (i = 0; i < 256; i++) {
7942                 intel_crtc->lut_r[i] = i;
7943                 intel_crtc->lut_g[i] = i;
7944                 intel_crtc->lut_b[i] = i;
7945         }
7946
7947         /* Swap pipes & planes for FBC on pre-965 */
7948         intel_crtc->pipe = pipe;
7949         intel_crtc->plane = pipe;
7950         intel_crtc->cpu_transcoder = pipe;
7951         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
7952                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
7953                 intel_crtc->plane = !pipe;
7954         }
7955
7956         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7957                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7958         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7959         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7960
7961         intel_crtc->bpp = 24; /* default for pre-Ironlake */
7962
7963         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
7964 }
7965
7966 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
7967                                 struct drm_file *file)
7968 {
7969         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7970         struct drm_mode_object *drmmode_obj;
7971         struct intel_crtc *crtc;
7972
7973         if (!drm_core_check_feature(dev, DRIVER_MODESET))
7974                 return -ENODEV;
7975
7976         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7977                         DRM_MODE_OBJECT_CRTC);
7978
7979         if (!drmmode_obj) {
7980                 DRM_ERROR("no such CRTC id\n");
7981                 return -EINVAL;
7982         }
7983
7984         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7985         pipe_from_crtc_id->pipe = crtc->pipe;
7986
7987         return 0;
7988 }
7989
7990 static int intel_encoder_clones(struct intel_encoder *encoder)
7991 {
7992         struct drm_device *dev = encoder->base.dev;
7993         struct intel_encoder *source_encoder;
7994         int index_mask = 0;
7995         int entry = 0;
7996
7997         list_for_each_entry(source_encoder,
7998                             &dev->mode_config.encoder_list, base.head) {
7999
8000                 if (encoder == source_encoder)
8001                         index_mask |= (1 << entry);
8002
8003                 /* Intel hw has only one MUX where enocoders could be cloned. */
8004                 if (encoder->cloneable && source_encoder->cloneable)
8005                         index_mask |= (1 << entry);
8006
8007                 entry++;
8008         }
8009
8010         return index_mask;
8011 }
8012
8013 static bool has_edp_a(struct drm_device *dev)
8014 {
8015         struct drm_i915_private *dev_priv = dev->dev_private;
8016
8017         if (!IS_MOBILE(dev))
8018                 return false;
8019
8020         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8021                 return false;
8022
8023         if (IS_GEN5(dev) &&
8024             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8025                 return false;
8026
8027         return true;
8028 }
8029
8030 static void intel_setup_outputs(struct drm_device *dev)
8031 {
8032         struct drm_i915_private *dev_priv = dev->dev_private;
8033         struct intel_encoder *encoder;
8034         bool dpd_is_edp = false;
8035         bool has_lvds;
8036
8037         has_lvds = intel_lvds_init(dev);
8038         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8039                 /* disable the panel fitter on everything but LVDS */
8040                 I915_WRITE(PFIT_CONTROL, 0);
8041         }
8042
8043         if (HAS_PCH_SPLIT(dev)) {
8044                 dpd_is_edp = intel_dpd_is_edp(dev);
8045
8046                 if (has_edp_a(dev))
8047                         intel_dp_init(dev, DP_A, PORT_A);
8048
8049                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
8050                         intel_dp_init(dev, PCH_DP_D, PORT_D);
8051         }
8052
8053         intel_crt_init(dev);
8054
8055         if (IS_HASWELL(dev)) {
8056                 int found;
8057
8058                 /* Haswell uses DDI functions to detect digital outputs */
8059                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8060                 /* DDI A only supports eDP */
8061                 if (found)
8062                         intel_ddi_init(dev, PORT_A);
8063
8064                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8065                  * register */
8066                 found = I915_READ(SFUSE_STRAP);
8067
8068                 if (found & SFUSE_STRAP_DDIB_DETECTED)
8069                         intel_ddi_init(dev, PORT_B);
8070                 if (found & SFUSE_STRAP_DDIC_DETECTED)
8071                         intel_ddi_init(dev, PORT_C);
8072                 if (found & SFUSE_STRAP_DDID_DETECTED)
8073                         intel_ddi_init(dev, PORT_D);
8074         } else if (HAS_PCH_SPLIT(dev)) {
8075                 int found;
8076
8077                 if (I915_READ(HDMIB) & PORT_DETECTED) {
8078                         /* PCH SDVOB multiplex with HDMIB */
8079                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
8080                         if (!found)
8081                                 intel_hdmi_init(dev, HDMIB, PORT_B);
8082                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
8083                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
8084                 }
8085
8086                 if (I915_READ(HDMIC) & PORT_DETECTED)
8087                         intel_hdmi_init(dev, HDMIC, PORT_C);
8088
8089                 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
8090                         intel_hdmi_init(dev, HDMID, PORT_D);
8091
8092                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
8093                         intel_dp_init(dev, PCH_DP_C, PORT_C);
8094
8095                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
8096                         intel_dp_init(dev, PCH_DP_D, PORT_D);
8097         } else if (IS_VALLEYVIEW(dev)) {
8098                 int found;
8099
8100                 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8101                 if (I915_READ(DP_C) & DP_DETECTED)
8102                         intel_dp_init(dev, DP_C, PORT_C);
8103
8104                 if (I915_READ(SDVOB) & PORT_DETECTED) {
8105                         /* SDVOB multiplex with HDMIB */
8106                         found = intel_sdvo_init(dev, SDVOB, true);
8107                         if (!found)
8108                                 intel_hdmi_init(dev, SDVOB, PORT_B);
8109                         if (!found && (I915_READ(DP_B) & DP_DETECTED))
8110                                 intel_dp_init(dev, DP_B, PORT_B);
8111                 }
8112
8113                 if (I915_READ(SDVOC) & PORT_DETECTED)
8114                         intel_hdmi_init(dev, SDVOC, PORT_C);
8115
8116         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
8117                 bool found = false;
8118
8119                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8120                         DRM_DEBUG_KMS("probing SDVOB\n");
8121                         found = intel_sdvo_init(dev, SDVOB, true);
8122                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8123                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8124                                 intel_hdmi_init(dev, SDVOB, PORT_B);
8125                         }
8126
8127                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8128                                 DRM_DEBUG_KMS("probing DP_B\n");
8129                                 intel_dp_init(dev, DP_B, PORT_B);
8130                         }
8131                 }
8132
8133                 /* Before G4X SDVOC doesn't have its own detect register */
8134
8135                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8136                         DRM_DEBUG_KMS("probing SDVOC\n");
8137                         found = intel_sdvo_init(dev, SDVOC, false);
8138                 }
8139
8140                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
8141
8142                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8143                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8144                                 intel_hdmi_init(dev, SDVOC, PORT_C);
8145                         }
8146                         if (SUPPORTS_INTEGRATED_DP(dev)) {
8147                                 DRM_DEBUG_KMS("probing DP_C\n");
8148                                 intel_dp_init(dev, DP_C, PORT_C);
8149                         }
8150                 }
8151
8152                 if (SUPPORTS_INTEGRATED_DP(dev) &&
8153                     (I915_READ(DP_D) & DP_DETECTED)) {
8154                         DRM_DEBUG_KMS("probing DP_D\n");
8155                         intel_dp_init(dev, DP_D, PORT_D);
8156                 }
8157         } else if (IS_GEN2(dev))
8158                 intel_dvo_init(dev);
8159
8160         if (SUPPORTS_TV(dev))
8161                 intel_tv_init(dev);
8162
8163         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8164                 encoder->base.possible_crtcs = encoder->crtc_mask;
8165                 encoder->base.possible_clones =
8166                         intel_encoder_clones(encoder);
8167         }
8168
8169         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8170                 ironlake_init_pch_refclk(dev);
8171 }
8172
8173 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8174 {
8175         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8176
8177         drm_framebuffer_cleanup(fb);
8178         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8179
8180         kfree(intel_fb);
8181 }
8182
8183 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8184                                                 struct drm_file *file,
8185                                                 unsigned int *handle)
8186 {
8187         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8188         struct drm_i915_gem_object *obj = intel_fb->obj;
8189
8190         return drm_gem_handle_create(file, &obj->base, handle);
8191 }
8192
8193 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8194         .destroy = intel_user_framebuffer_destroy,
8195         .create_handle = intel_user_framebuffer_create_handle,
8196 };
8197
8198 int intel_framebuffer_init(struct drm_device *dev,
8199                            struct intel_framebuffer *intel_fb,
8200                            struct drm_mode_fb_cmd2 *mode_cmd,
8201                            struct drm_i915_gem_object *obj)
8202 {
8203         int ret;
8204
8205         if (obj->tiling_mode == I915_TILING_Y)
8206                 return -EINVAL;
8207
8208         if (mode_cmd->pitches[0] & 63)
8209                 return -EINVAL;
8210
8211         switch (mode_cmd->pixel_format) {
8212         case DRM_FORMAT_RGB332:
8213         case DRM_FORMAT_RGB565:
8214         case DRM_FORMAT_XRGB8888:
8215         case DRM_FORMAT_XBGR8888:
8216         case DRM_FORMAT_ARGB8888:
8217         case DRM_FORMAT_XRGB2101010:
8218         case DRM_FORMAT_ARGB2101010:
8219                 /* RGB formats are common across chipsets */
8220                 break;
8221         case DRM_FORMAT_YUYV:
8222         case DRM_FORMAT_UYVY:
8223         case DRM_FORMAT_YVYU:
8224         case DRM_FORMAT_VYUY:
8225                 break;
8226         default:
8227                 DRM_DEBUG_KMS("unsupported pixel format %u\n",
8228                                 mode_cmd->pixel_format);
8229                 return -EINVAL;
8230         }
8231
8232         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8233         if (ret) {
8234                 DRM_ERROR("framebuffer init failed %d\n", ret);
8235                 return ret;
8236         }
8237
8238         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8239         intel_fb->obj = obj;
8240         return 0;
8241 }
8242
8243 static struct drm_framebuffer *
8244 intel_user_framebuffer_create(struct drm_device *dev,
8245                               struct drm_file *filp,
8246                               struct drm_mode_fb_cmd2 *mode_cmd)
8247 {
8248         struct drm_i915_gem_object *obj;
8249
8250         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8251                                                 mode_cmd->handles[0]));
8252         if (&obj->base == NULL)
8253                 return ERR_PTR(-ENOENT);
8254
8255         return intel_framebuffer_create(dev, mode_cmd, obj);
8256 }
8257
8258 static const struct drm_mode_config_funcs intel_mode_funcs = {
8259         .fb_create = intel_user_framebuffer_create,
8260         .output_poll_changed = intel_fb_output_poll_changed,
8261 };
8262
8263 /* Set up chip specific display functions */
8264 static void intel_init_display(struct drm_device *dev)
8265 {
8266         struct drm_i915_private *dev_priv = dev->dev_private;
8267
8268         /* We always want a DPMS function */
8269         if (IS_HASWELL(dev)) {
8270                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
8271                 dev_priv->display.crtc_enable = haswell_crtc_enable;
8272                 dev_priv->display.crtc_disable = haswell_crtc_disable;
8273                 dev_priv->display.off = haswell_crtc_off;
8274                 dev_priv->display.update_plane = ironlake_update_plane;
8275         } else if (HAS_PCH_SPLIT(dev)) {
8276                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8277                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8278                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
8279                 dev_priv->display.off = ironlake_crtc_off;
8280                 dev_priv->display.update_plane = ironlake_update_plane;
8281         } else {
8282                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8283                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8284                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8285                 dev_priv->display.off = i9xx_crtc_off;
8286                 dev_priv->display.update_plane = i9xx_update_plane;
8287         }
8288
8289         /* Returns the core display clock speed */
8290         if (IS_VALLEYVIEW(dev))
8291                 dev_priv->display.get_display_clock_speed =
8292                         valleyview_get_display_clock_speed;
8293         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8294                 dev_priv->display.get_display_clock_speed =
8295                         i945_get_display_clock_speed;
8296         else if (IS_I915G(dev))
8297                 dev_priv->display.get_display_clock_speed =
8298                         i915_get_display_clock_speed;
8299         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8300                 dev_priv->display.get_display_clock_speed =
8301                         i9xx_misc_get_display_clock_speed;
8302         else if (IS_I915GM(dev))
8303                 dev_priv->display.get_display_clock_speed =
8304                         i915gm_get_display_clock_speed;
8305         else if (IS_I865G(dev))
8306                 dev_priv->display.get_display_clock_speed =
8307                         i865_get_display_clock_speed;
8308         else if (IS_I85X(dev))
8309                 dev_priv->display.get_display_clock_speed =
8310                         i855_get_display_clock_speed;
8311         else /* 852, 830 */
8312                 dev_priv->display.get_display_clock_speed =
8313                         i830_get_display_clock_speed;
8314
8315         if (HAS_PCH_SPLIT(dev)) {
8316                 if (IS_GEN5(dev)) {
8317                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8318                         dev_priv->display.write_eld = ironlake_write_eld;
8319                 } else if (IS_GEN6(dev)) {
8320                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8321                         dev_priv->display.write_eld = ironlake_write_eld;
8322                 } else if (IS_IVYBRIDGE(dev)) {
8323                         /* FIXME: detect B0+ stepping and use auto training */
8324                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8325                         dev_priv->display.write_eld = ironlake_write_eld;
8326                 } else if (IS_HASWELL(dev)) {
8327                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
8328                         dev_priv->display.write_eld = haswell_write_eld;
8329                 } else
8330                         dev_priv->display.update_wm = NULL;
8331         } else if (IS_G4X(dev)) {
8332                 dev_priv->display.write_eld = g4x_write_eld;
8333         }
8334
8335         /* Default just returns -ENODEV to indicate unsupported */
8336         dev_priv->display.queue_flip = intel_default_queue_flip;
8337
8338         switch (INTEL_INFO(dev)->gen) {
8339         case 2:
8340                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8341                 break;
8342
8343         case 3:
8344                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8345                 break;
8346
8347         case 4:
8348         case 5:
8349                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8350                 break;
8351
8352         case 6:
8353                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8354                 break;
8355         case 7:
8356                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8357                 break;
8358         }
8359 }
8360
8361 /*
8362  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8363  * resume, or other times.  This quirk makes sure that's the case for
8364  * affected systems.
8365  */
8366 static void quirk_pipea_force(struct drm_device *dev)
8367 {
8368         struct drm_i915_private *dev_priv = dev->dev_private;
8369
8370         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8371         DRM_INFO("applying pipe a force quirk\n");
8372 }
8373
8374 /*
8375  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8376  */
8377 static void quirk_ssc_force_disable(struct drm_device *dev)
8378 {
8379         struct drm_i915_private *dev_priv = dev->dev_private;
8380         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8381         DRM_INFO("applying lvds SSC disable quirk\n");
8382 }
8383
8384 /*
8385  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8386  * brightness value
8387  */
8388 static void quirk_invert_brightness(struct drm_device *dev)
8389 {
8390         struct drm_i915_private *dev_priv = dev->dev_private;
8391         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
8392         DRM_INFO("applying inverted panel brightness quirk\n");
8393 }
8394
8395 struct intel_quirk {
8396         int device;
8397         int subsystem_vendor;
8398         int subsystem_device;
8399         void (*hook)(struct drm_device *dev);
8400 };
8401
8402 static struct intel_quirk intel_quirks[] = {
8403         /* HP Mini needs pipe A force quirk (LP: #322104) */
8404         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
8405
8406         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8407         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8408
8409         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8410         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8411
8412         /* 830/845 need to leave pipe A & dpll A up */
8413         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8414         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8415
8416         /* Lenovo U160 cannot use SSC on LVDS */
8417         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8418
8419         /* Sony Vaio Y cannot use SSC on LVDS */
8420         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
8421
8422         /* Acer Aspire 5734Z must invert backlight brightness */
8423         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
8424 };
8425
8426 static void intel_init_quirks(struct drm_device *dev)
8427 {
8428         struct pci_dev *d = dev->pdev;
8429         int i;
8430
8431         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8432                 struct intel_quirk *q = &intel_quirks[i];
8433
8434                 if (d->device == q->device &&
8435                     (d->subsystem_vendor == q->subsystem_vendor ||
8436                      q->subsystem_vendor == PCI_ANY_ID) &&
8437                     (d->subsystem_device == q->subsystem_device ||
8438                      q->subsystem_device == PCI_ANY_ID))
8439                         q->hook(dev);
8440         }
8441 }
8442
8443 /* Disable the VGA plane that we never use */
8444 static void i915_disable_vga(struct drm_device *dev)
8445 {
8446         struct drm_i915_private *dev_priv = dev->dev_private;
8447         u8 sr1;
8448         u32 vga_reg;
8449
8450         if (HAS_PCH_SPLIT(dev))
8451                 vga_reg = CPU_VGACNTRL;
8452         else
8453                 vga_reg = VGACNTRL;
8454
8455         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8456         outb(SR01, VGA_SR_INDEX);
8457         sr1 = inb(VGA_SR_DATA);
8458         outb(sr1 | 1<<5, VGA_SR_DATA);
8459         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8460         udelay(300);
8461
8462         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8463         POSTING_READ(vga_reg);
8464 }
8465
8466 void intel_modeset_init_hw(struct drm_device *dev)
8467 {
8468         /* We attempt to init the necessary power wells early in the initialization
8469          * time, so the subsystems that expect power to be enabled can work.
8470          */
8471         intel_init_power_wells(dev);
8472
8473         intel_prepare_ddi(dev);
8474
8475         intel_init_clock_gating(dev);
8476
8477         mutex_lock(&dev->struct_mutex);
8478         intel_enable_gt_powersave(dev);
8479         mutex_unlock(&dev->struct_mutex);
8480 }
8481
8482 void intel_modeset_init(struct drm_device *dev)
8483 {
8484         struct drm_i915_private *dev_priv = dev->dev_private;
8485         int i, ret;
8486
8487         drm_mode_config_init(dev);
8488
8489         dev->mode_config.min_width = 0;
8490         dev->mode_config.min_height = 0;
8491
8492         dev->mode_config.preferred_depth = 24;
8493         dev->mode_config.prefer_shadow = 1;
8494
8495         dev->mode_config.funcs = &intel_mode_funcs;
8496
8497         intel_init_quirks(dev);
8498
8499         intel_init_pm(dev);
8500
8501         intel_init_display(dev);
8502
8503         if (IS_GEN2(dev)) {
8504                 dev->mode_config.max_width = 2048;
8505                 dev->mode_config.max_height = 2048;
8506         } else if (IS_GEN3(dev)) {
8507                 dev->mode_config.max_width = 4096;
8508                 dev->mode_config.max_height = 4096;
8509         } else {
8510                 dev->mode_config.max_width = 8192;
8511                 dev->mode_config.max_height = 8192;
8512         }
8513         dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
8514
8515         DRM_DEBUG_KMS("%d display pipe%s available.\n",
8516                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
8517
8518         for (i = 0; i < dev_priv->num_pipe; i++) {
8519                 intel_crtc_init(dev, i);
8520                 ret = intel_plane_init(dev, i);
8521                 if (ret)
8522                         DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
8523         }
8524
8525         intel_cpu_pll_init(dev);
8526         intel_pch_pll_init(dev);
8527
8528         /* Just disable it once at startup */
8529         i915_disable_vga(dev);
8530         intel_setup_outputs(dev);
8531 }
8532
8533 static void
8534 intel_connector_break_all_links(struct intel_connector *connector)
8535 {
8536         connector->base.dpms = DRM_MODE_DPMS_OFF;
8537         connector->base.encoder = NULL;
8538         connector->encoder->connectors_active = false;
8539         connector->encoder->base.crtc = NULL;
8540 }
8541
8542 static void intel_enable_pipe_a(struct drm_device *dev)
8543 {
8544         struct intel_connector *connector;
8545         struct drm_connector *crt = NULL;
8546         struct intel_load_detect_pipe load_detect_temp;
8547
8548         /* We can't just switch on the pipe A, we need to set things up with a
8549          * proper mode and output configuration. As a gross hack, enable pipe A
8550          * by enabling the load detect pipe once. */
8551         list_for_each_entry(connector,
8552                             &dev->mode_config.connector_list,
8553                             base.head) {
8554                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8555                         crt = &connector->base;
8556                         break;
8557                 }
8558         }
8559
8560         if (!crt)
8561                 return;
8562
8563         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8564                 intel_release_load_detect_pipe(crt, &load_detect_temp);
8565
8566
8567 }
8568
8569 static bool
8570 intel_check_plane_mapping(struct intel_crtc *crtc)
8571 {
8572         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8573         u32 reg, val;
8574
8575         if (dev_priv->num_pipe == 1)
8576                 return true;
8577
8578         reg = DSPCNTR(!crtc->plane);
8579         val = I915_READ(reg);
8580
8581         if ((val & DISPLAY_PLANE_ENABLE) &&
8582             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8583                 return false;
8584
8585         return true;
8586 }
8587
8588 static void intel_sanitize_crtc(struct intel_crtc *crtc)
8589 {
8590         struct drm_device *dev = crtc->base.dev;
8591         struct drm_i915_private *dev_priv = dev->dev_private;
8592         u32 reg;
8593
8594         /* Clear any frame start delays used for debugging left by the BIOS */
8595         reg = PIPECONF(crtc->cpu_transcoder);
8596         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8597
8598         /* We need to sanitize the plane -> pipe mapping first because this will
8599          * disable the crtc (and hence change the state) if it is wrong. Note
8600          * that gen4+ has a fixed plane -> pipe mapping.  */
8601         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
8602                 struct intel_connector *connector;
8603                 bool plane;
8604
8605                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8606                               crtc->base.base.id);
8607
8608                 /* Pipe has the wrong plane attached and the plane is active.
8609                  * Temporarily change the plane mapping and disable everything
8610                  * ...  */
8611                 plane = crtc->plane;
8612                 crtc->plane = !plane;
8613                 dev_priv->display.crtc_disable(&crtc->base);
8614                 crtc->plane = plane;
8615
8616                 /* ... and break all links. */
8617                 list_for_each_entry(connector, &dev->mode_config.connector_list,
8618                                     base.head) {
8619                         if (connector->encoder->base.crtc != &crtc->base)
8620                                 continue;
8621
8622                         intel_connector_break_all_links(connector);
8623                 }
8624
8625                 WARN_ON(crtc->active);
8626                 crtc->base.enabled = false;
8627         }
8628
8629         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8630             crtc->pipe == PIPE_A && !crtc->active) {
8631                 /* BIOS forgot to enable pipe A, this mostly happens after
8632                  * resume. Force-enable the pipe to fix this, the update_dpms
8633                  * call below we restore the pipe to the right state, but leave
8634                  * the required bits on. */
8635                 intel_enable_pipe_a(dev);
8636         }
8637
8638         /* Adjust the state of the output pipe according to whether we
8639          * have active connectors/encoders. */
8640         intel_crtc_update_dpms(&crtc->base);
8641
8642         if (crtc->active != crtc->base.enabled) {
8643                 struct intel_encoder *encoder;
8644
8645                 /* This can happen either due to bugs in the get_hw_state
8646                  * functions or because the pipe is force-enabled due to the
8647                  * pipe A quirk. */
8648                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8649                               crtc->base.base.id,
8650                               crtc->base.enabled ? "enabled" : "disabled",
8651                               crtc->active ? "enabled" : "disabled");
8652
8653                 crtc->base.enabled = crtc->active;
8654
8655                 /* Because we only establish the connector -> encoder ->
8656                  * crtc links if something is active, this means the
8657                  * crtc is now deactivated. Break the links. connector
8658                  * -> encoder links are only establish when things are
8659                  *  actually up, hence no need to break them. */
8660                 WARN_ON(crtc->active);
8661
8662                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
8663                         WARN_ON(encoder->connectors_active);
8664                         encoder->base.crtc = NULL;
8665                 }
8666         }
8667 }
8668
8669 static void intel_sanitize_encoder(struct intel_encoder *encoder)
8670 {
8671         struct intel_connector *connector;
8672         struct drm_device *dev = encoder->base.dev;
8673
8674         /* We need to check both for a crtc link (meaning that the
8675          * encoder is active and trying to read from a pipe) and the
8676          * pipe itself being active. */
8677         bool has_active_crtc = encoder->base.crtc &&
8678                 to_intel_crtc(encoder->base.crtc)->active;
8679
8680         if (encoder->connectors_active && !has_active_crtc) {
8681                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
8682                               encoder->base.base.id,
8683                               drm_get_encoder_name(&encoder->base));
8684
8685                 /* Connector is active, but has no active pipe. This is
8686                  * fallout from our resume register restoring. Disable
8687                  * the encoder manually again. */
8688                 if (encoder->base.crtc) {
8689                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
8690                                       encoder->base.base.id,
8691                                       drm_get_encoder_name(&encoder->base));
8692                         encoder->disable(encoder);
8693                 }
8694
8695                 /* Inconsistent output/port/pipe state happens presumably due to
8696                  * a bug in one of the get_hw_state functions. Or someplace else
8697                  * in our code, like the register restore mess on resume. Clamp
8698                  * things to off as a safer default. */
8699                 list_for_each_entry(connector,
8700                                     &dev->mode_config.connector_list,
8701                                     base.head) {
8702                         if (connector->encoder != encoder)
8703                                 continue;
8704
8705                         intel_connector_break_all_links(connector);
8706                 }
8707         }
8708         /* Enabled encoders without active connectors will be fixed in
8709          * the crtc fixup. */
8710 }
8711
8712 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
8713  * and i915 state tracking structures. */
8714 void intel_modeset_setup_hw_state(struct drm_device *dev)
8715 {
8716         struct drm_i915_private *dev_priv = dev->dev_private;
8717         enum pipe pipe;
8718         u32 tmp;
8719         struct intel_crtc *crtc;
8720         struct intel_encoder *encoder;
8721         struct intel_connector *connector;
8722
8723         if (IS_HASWELL(dev)) {
8724                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8725
8726                 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8727                         switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8728                         case TRANS_DDI_EDP_INPUT_A_ON:
8729                         case TRANS_DDI_EDP_INPUT_A_ONOFF:
8730                                 pipe = PIPE_A;
8731                                 break;
8732                         case TRANS_DDI_EDP_INPUT_B_ONOFF:
8733                                 pipe = PIPE_B;
8734                                 break;
8735                         case TRANS_DDI_EDP_INPUT_C_ONOFF:
8736                                 pipe = PIPE_C;
8737                                 break;
8738                         }
8739
8740                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8741                         crtc->cpu_transcoder = TRANSCODER_EDP;
8742
8743                         DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
8744                                       pipe_name(pipe));
8745                 }
8746         }
8747
8748         for_each_pipe(pipe) {
8749                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8750
8751                 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
8752                 if (tmp & PIPECONF_ENABLE)
8753                         crtc->active = true;
8754                 else
8755                         crtc->active = false;
8756
8757                 crtc->base.enabled = crtc->active;
8758
8759                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
8760                               crtc->base.base.id,
8761                               crtc->active ? "enabled" : "disabled");
8762         }
8763
8764         if (IS_HASWELL(dev))
8765                 intel_ddi_setup_hw_pll_state(dev);
8766
8767         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8768                             base.head) {
8769                 pipe = 0;
8770
8771                 if (encoder->get_hw_state(encoder, &pipe)) {
8772                         encoder->base.crtc =
8773                                 dev_priv->pipe_to_crtc_mapping[pipe];
8774                 } else {
8775                         encoder->base.crtc = NULL;
8776                 }
8777
8778                 encoder->connectors_active = false;
8779                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
8780                               encoder->base.base.id,
8781                               drm_get_encoder_name(&encoder->base),
8782                               encoder->base.crtc ? "enabled" : "disabled",
8783                               pipe);
8784         }
8785
8786         list_for_each_entry(connector, &dev->mode_config.connector_list,
8787                             base.head) {
8788                 if (connector->get_hw_state(connector)) {
8789                         connector->base.dpms = DRM_MODE_DPMS_ON;
8790                         connector->encoder->connectors_active = true;
8791                         connector->base.encoder = &connector->encoder->base;
8792                 } else {
8793                         connector->base.dpms = DRM_MODE_DPMS_OFF;
8794                         connector->base.encoder = NULL;
8795                 }
8796                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
8797                               connector->base.base.id,
8798                               drm_get_connector_name(&connector->base),
8799                               connector->base.encoder ? "enabled" : "disabled");
8800         }
8801
8802         /* HW state is read out, now we need to sanitize this mess. */
8803         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8804                             base.head) {
8805                 intel_sanitize_encoder(encoder);
8806         }
8807
8808         for_each_pipe(pipe) {
8809                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8810                 intel_sanitize_crtc(crtc);
8811         }
8812
8813         intel_modeset_update_staged_output_state(dev);
8814
8815         intel_modeset_check_state(dev);
8816
8817         drm_mode_config_reset(dev);
8818 }
8819
8820 void intel_modeset_gem_init(struct drm_device *dev)
8821 {
8822         intel_modeset_init_hw(dev);
8823
8824         intel_setup_overlay(dev);
8825
8826         intel_modeset_setup_hw_state(dev);
8827 }
8828
8829 void intel_modeset_cleanup(struct drm_device *dev)
8830 {
8831         struct drm_i915_private *dev_priv = dev->dev_private;
8832         struct drm_crtc *crtc;
8833         struct intel_crtc *intel_crtc;
8834
8835         drm_kms_helper_poll_fini(dev);
8836         mutex_lock(&dev->struct_mutex);
8837
8838         intel_unregister_dsm_handler();
8839
8840
8841         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8842                 /* Skip inactive CRTCs */
8843                 if (!crtc->fb)
8844                         continue;
8845
8846                 intel_crtc = to_intel_crtc(crtc);
8847                 intel_increase_pllclock(crtc);
8848         }
8849
8850         intel_disable_fbc(dev);
8851
8852         intel_disable_gt_powersave(dev);
8853
8854         ironlake_teardown_rc6(dev);
8855
8856         if (IS_VALLEYVIEW(dev))
8857                 vlv_init_dpio(dev);
8858
8859         mutex_unlock(&dev->struct_mutex);
8860
8861         /* Disable the irq before mode object teardown, for the irq might
8862          * enqueue unpin/hotplug work. */
8863         drm_irq_uninstall(dev);
8864         cancel_work_sync(&dev_priv->hotplug_work);
8865         cancel_work_sync(&dev_priv->rps.work);
8866
8867         /* flush any delayed tasks or pending work */
8868         flush_scheduled_work();
8869
8870         drm_mode_config_cleanup(dev);
8871 }
8872
8873 /*
8874  * Return which encoder is currently attached for connector.
8875  */
8876 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
8877 {
8878         return &intel_attached_encoder(connector)->base;
8879 }
8880
8881 void intel_connector_attach_encoder(struct intel_connector *connector,
8882                                     struct intel_encoder *encoder)
8883 {
8884         connector->encoder = encoder;
8885         drm_mode_connector_attach_encoder(&connector->base,
8886                                           &encoder->base);
8887 }
8888
8889 /*
8890  * set vga decode state - true == enable VGA decode
8891  */
8892 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
8893 {
8894         struct drm_i915_private *dev_priv = dev->dev_private;
8895         u16 gmch_ctrl;
8896
8897         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
8898         if (state)
8899                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
8900         else
8901                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
8902         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
8903         return 0;
8904 }
8905
8906 #ifdef CONFIG_DEBUG_FS
8907 #include <linux/seq_file.h>
8908
8909 struct intel_display_error_state {
8910         struct intel_cursor_error_state {
8911                 u32 control;
8912                 u32 position;
8913                 u32 base;
8914                 u32 size;
8915         } cursor[I915_MAX_PIPES];
8916
8917         struct intel_pipe_error_state {
8918                 u32 conf;
8919                 u32 source;
8920
8921                 u32 htotal;
8922                 u32 hblank;
8923                 u32 hsync;
8924                 u32 vtotal;
8925                 u32 vblank;
8926                 u32 vsync;
8927         } pipe[I915_MAX_PIPES];
8928
8929         struct intel_plane_error_state {
8930                 u32 control;
8931                 u32 stride;
8932                 u32 size;
8933                 u32 pos;
8934                 u32 addr;
8935                 u32 surface;
8936                 u32 tile_offset;
8937         } plane[I915_MAX_PIPES];
8938 };
8939
8940 struct intel_display_error_state *
8941 intel_display_capture_error_state(struct drm_device *dev)
8942 {
8943         drm_i915_private_t *dev_priv = dev->dev_private;
8944         struct intel_display_error_state *error;
8945         enum transcoder cpu_transcoder;
8946         int i;
8947
8948         error = kmalloc(sizeof(*error), GFP_ATOMIC);
8949         if (error == NULL)
8950                 return NULL;
8951
8952         for_each_pipe(i) {
8953                 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
8954
8955                 error->cursor[i].control = I915_READ(CURCNTR(i));
8956                 error->cursor[i].position = I915_READ(CURPOS(i));
8957                 error->cursor[i].base = I915_READ(CURBASE(i));
8958
8959                 error->plane[i].control = I915_READ(DSPCNTR(i));
8960                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
8961                 error->plane[i].size = I915_READ(DSPSIZE(i));
8962                 error->plane[i].pos = I915_READ(DSPPOS(i));
8963                 error->plane[i].addr = I915_READ(DSPADDR(i));
8964                 if (INTEL_INFO(dev)->gen >= 4) {
8965                         error->plane[i].surface = I915_READ(DSPSURF(i));
8966                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
8967                 }
8968
8969                 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
8970                 error->pipe[i].source = I915_READ(PIPESRC(i));
8971                 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
8972                 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
8973                 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
8974                 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
8975                 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
8976                 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
8977         }
8978
8979         return error;
8980 }
8981
8982 void
8983 intel_display_print_error_state(struct seq_file *m,
8984                                 struct drm_device *dev,
8985                                 struct intel_display_error_state *error)
8986 {
8987         drm_i915_private_t *dev_priv = dev->dev_private;
8988         int i;
8989
8990         seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
8991         for_each_pipe(i) {
8992                 seq_printf(m, "Pipe [%d]:\n", i);
8993                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
8994                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
8995                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
8996                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
8997                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
8998                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
8999                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
9000                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
9001
9002                 seq_printf(m, "Plane [%d]:\n", i);
9003                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
9004                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
9005                 seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
9006                 seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
9007                 seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
9008                 if (INTEL_INFO(dev)->gen >= 4) {
9009                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
9010                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
9011                 }
9012
9013                 seq_printf(m, "Cursor [%d]:\n", i);
9014                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
9015                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
9016                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
9017         }
9018 }
9019 #endif