Pileus Git - ~andy/linux/blob - drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  45
  46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  47 static void intel_increase_pllclock(struct drm_crtc *crtc);
  48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  49
  50 typedef struct {
  51         /* given values */
  52         int n;
  53         int m1, m2;
  54         int p1, p2;
  55         /* derived values */
  56         int     dot;
  57         int     vco;
  58         int     m;
  59         int     p;
  60 } intel_clock_t;
  61
  62 typedef struct {
  63         int     min, max;
  64 } intel_range_t;
  65
  66 typedef struct {
  67         int     dot_limit;
  68         int     p2_slow, p2_fast;
  69 } intel_p2_t;
  70
  71 #define INTEL_P2_NUM                  2
  72 typedef struct intel_limit intel_limit_t;
  73 struct intel_limit {
  74         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  75         intel_p2_t          p2;
  76         bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  77                         int, int, intel_clock_t *, intel_clock_t *);
  78 };
  79
  80 /* FDI */
  81 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  82
  83 int
  84 intel_pch_rawclk(struct drm_device *dev)
  85 {
  86         struct drm_i915_private *dev_priv = dev->dev_private;
  87
  88         WARN_ON(!HAS_PCH_SPLIT(dev));
  89
  90         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  91 }
  92
  93 static bool
  94 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  95                     int target, int refclk, intel_clock_t *match_clock,
  96                     intel_clock_t *best_clock);
  97 static bool
  98 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  99                         int target, int refclk, intel_clock_t *match_clock,
 100                         intel_clock_t *best_clock);
 101
 102 static bool
 103 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 104                       int target, int refclk, intel_clock_t *match_clock,
 105                       intel_clock_t *best_clock);
 106 static bool
 107 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 108                            int target, int refclk, intel_clock_t *match_clock,
 109                            intel_clock_t *best_clock);
 110
 111 static bool
 112 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 113                         int target, int refclk, intel_clock_t *match_clock,
 114                         intel_clock_t *best_clock);
 115
 116 static inline u32 /* units of 100MHz */
 117 intel_fdi_link_freq(struct drm_device *dev)
 118 {
 119         if (IS_GEN5(dev)) {
 120                 struct drm_i915_private *dev_priv = dev->dev_private;
 121                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 122         } else
 123                 return 27;
 124 }
 125
 126 static const intel_limit_t intel_limits_i8xx_dvo = {
 127         .dot = { .min = 25000, .max = 350000 },
 128         .vco = { .min = 930000, .max = 1400000 },
 129         .n = { .min = 3, .max = 16 },
 130         .m = { .min = 96, .max = 140 },
 131         .m1 = { .min = 18, .max = 26 },
 132         .m2 = { .min = 6, .max = 16 },
 133         .p = { .min = 4, .max = 128 },
 134         .p1 = { .min = 2, .max = 33 },
 135         .p2 = { .dot_limit = 165000,
 136                 .p2_slow = 4, .p2_fast = 2 },
 137         .find_pll = intel_find_best_PLL,
 138 };
 139
 140 static const intel_limit_t intel_limits_i8xx_lvds = {
 141         .dot = { .min = 25000, .max = 350000 },
 142         .vco = { .min = 930000, .max = 1400000 },
 143         .n = { .min = 3, .max = 16 },
 144         .m = { .min = 96, .max = 140 },
 145         .m1 = { .min = 18, .max = 26 },
 146         .m2 = { .min = 6, .max = 16 },
 147         .p = { .min = 4, .max = 128 },
 148         .p1 = { .min = 1, .max = 6 },
 149         .p2 = { .dot_limit = 165000,
 150                 .p2_slow = 14, .p2_fast = 7 },
 151         .find_pll = intel_find_best_PLL,
 152 };
 153
 154 static const intel_limit_t intel_limits_i9xx_sdvo = {
 155         .dot = { .min = 20000, .max = 400000 },
 156         .vco = { .min = 1400000, .max = 2800000 },
 157         .n = { .min = 1, .max = 6 },
 158         .m = { .min = 70, .max = 120 },
 159         .m1 = { .min = 10, .max = 22 },
 160         .m2 = { .min = 5, .max = 9 },
 161         .p = { .min = 5, .max = 80 },
 162         .p1 = { .min = 1, .max = 8 },
 163         .p2 = { .dot_limit = 200000,
 164                 .p2_slow = 10, .p2_fast = 5 },
 165         .find_pll = intel_find_best_PLL,
 166 };
 167
 168 static const intel_limit_t intel_limits_i9xx_lvds = {
 169         .dot = { .min = 20000, .max = 400000 },
 170         .vco = { .min = 1400000, .max = 2800000 },
 171         .n = { .min = 1, .max = 6 },
 172         .m = { .min = 70, .max = 120 },
 173         .m1 = { .min = 10, .max = 22 },
 174         .m2 = { .min = 5, .max = 9 },
 175         .p = { .min = 7, .max = 98 },
 176         .p1 = { .min = 1, .max = 8 },
 177         .p2 = { .dot_limit = 112000,
 178                 .p2_slow = 14, .p2_fast = 7 },
 179         .find_pll = intel_find_best_PLL,
 180 };
 181
 182
 183 static const intel_limit_t intel_limits_g4x_sdvo = {
 184         .dot = { .min = 25000, .max = 270000 },
 185         .vco = { .min = 1750000, .max = 3500000},
 186         .n = { .min = 1, .max = 4 },
 187         .m = { .min = 104, .max = 138 },
 188         .m1 = { .min = 17, .max = 23 },
 189         .m2 = { .min = 5, .max = 11 },
 190         .p = { .min = 10, .max = 30 },
 191         .p1 = { .min = 1, .max = 3},
 192         .p2 = { .dot_limit = 270000,
 193                 .p2_slow = 10,
 194                 .p2_fast = 10
 195         },
 196         .find_pll = intel_g4x_find_best_PLL,
 197 };
 198
 199 static const intel_limit_t intel_limits_g4x_hdmi = {
 200         .dot = { .min = 22000, .max = 400000 },
 201         .vco = { .min = 1750000, .max = 3500000},
 202         .n = { .min = 1, .max = 4 },
 203         .m = { .min = 104, .max = 138 },
 204         .m1 = { .min = 16, .max = 23 },
 205         .m2 = { .min = 5, .max = 11 },
 206         .p = { .min = 5, .max = 80 },
 207         .p1 = { .min = 1, .max = 8},
 208         .p2 = { .dot_limit = 165000,
 209                 .p2_slow = 10, .p2_fast = 5 },
 210         .find_pll = intel_g4x_find_best_PLL,
 211 };
 212
 213 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 214         .dot = { .min = 20000, .max = 115000 },
 215         .vco = { .min = 1750000, .max = 3500000 },
 216         .n = { .min = 1, .max = 3 },
 217         .m = { .min = 104, .max = 138 },
 218         .m1 = { .min = 17, .max = 23 },
 219         .m2 = { .min = 5, .max = 11 },
 220         .p = { .min = 28, .max = 112 },
 221         .p1 = { .min = 2, .max = 8 },
 222         .p2 = { .dot_limit = 0,
 223                 .p2_slow = 14, .p2_fast = 14
 224         },
 225         .find_pll = intel_g4x_find_best_PLL,
 226 };
 227
 228 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 229         .dot = { .min = 80000, .max = 224000 },
 230         .vco = { .min = 1750000, .max = 3500000 },
 231         .n = { .min = 1, .max = 3 },
 232         .m = { .min = 104, .max = 138 },
 233         .m1 = { .min = 17, .max = 23 },
 234         .m2 = { .min = 5, .max = 11 },
 235         .p = { .min = 14, .max = 42 },
 236         .p1 = { .min = 2, .max = 6 },
 237         .p2 = { .dot_limit = 0,
 238                 .p2_slow = 7, .p2_fast = 7
 239         },
 240         .find_pll = intel_g4x_find_best_PLL,
 241 };
 242
 243 static const intel_limit_t intel_limits_g4x_display_port = {
 244         .dot = { .min = 161670, .max = 227000 },
 245         .vco = { .min = 1750000, .max = 3500000},
 246         .n = { .min = 1, .max = 2 },
 247         .m = { .min = 97, .max = 108 },
 248         .m1 = { .min = 0x10, .max = 0x12 },
 249         .m2 = { .min = 0x05, .max = 0x06 },
 250         .p = { .min = 10, .max = 20 },
 251         .p1 = { .min = 1, .max = 2},
 252         .p2 = { .dot_limit = 0,
 253                 .p2_slow = 10, .p2_fast = 10 },
 254         .find_pll = intel_find_pll_g4x_dp,
 255 };
 256
 257 static const intel_limit_t intel_limits_pineview_sdvo = {
 258         .dot = { .min = 20000, .max = 400000},
 259         .vco = { .min = 1700000, .max = 3500000 },
 260         /* Pineview's Ncounter is a ring counter */
 261         .n = { .min = 3, .max = 6 },
 262         .m = { .min = 2, .max = 256 },
 263         /* Pineview only has one combined m divider, which we treat as m2. */
 264         .m1 = { .min = 0, .max = 0 },
 265         .m2 = { .min = 0, .max = 254 },
 266         .p = { .min = 5, .max = 80 },
 267         .p1 = { .min = 1, .max = 8 },
 268         .p2 = { .dot_limit = 200000,
 269                 .p2_slow = 10, .p2_fast = 5 },
 270         .find_pll = intel_find_best_PLL,
 271 };
 272
 273 static const intel_limit_t intel_limits_pineview_lvds = {
 274         .dot = { .min = 20000, .max = 400000 },
 275         .vco = { .min = 1700000, .max = 3500000 },
 276         .n = { .min = 3, .max = 6 },
 277         .m = { .min = 2, .max = 256 },
 278         .m1 = { .min = 0, .max = 0 },
 279         .m2 = { .min = 0, .max = 254 },
 280         .p = { .min = 7, .max = 112 },
 281         .p1 = { .min = 1, .max = 8 },
 282         .p2 = { .dot_limit = 112000,
 283                 .p2_slow = 14, .p2_fast = 14 },
 284         .find_pll = intel_find_best_PLL,
 285 };
 286
 287 /* Ironlake / Sandybridge
 288  *
 289  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 290  * the range value for them is (actual_value - 2).
 291  */
 292 static const intel_limit_t intel_limits_ironlake_dac = {
 293         .dot = { .min = 25000, .max = 350000 },
 294         .vco = { .min = 1760000, .max = 3510000 },
 295         .n = { .min = 1, .max = 5 },
 296         .m = { .min = 79, .max = 127 },
 297         .m1 = { .min = 12, .max = 22 },
 298         .m2 = { .min = 5, .max = 9 },
 299         .p = { .min = 5, .max = 80 },
 300         .p1 = { .min = 1, .max = 8 },
 301         .p2 = { .dot_limit = 225000,
 302                 .p2_slow = 10, .p2_fast = 5 },
 303         .find_pll = intel_g4x_find_best_PLL,
 304 };
 305
 306 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 307         .dot = { .min = 25000, .max = 350000 },
 308         .vco = { .min = 1760000, .max = 3510000 },
 309         .n = { .min = 1, .max = 3 },
 310         .m = { .min = 79, .max = 118 },
 311         .m1 = { .min = 12, .max = 22 },
 312         .m2 = { .min = 5, .max = 9 },
 313         .p = { .min = 28, .max = 112 },
 314         .p1 = { .min = 2, .max = 8 },
 315         .p2 = { .dot_limit = 225000,
 316                 .p2_slow = 14, .p2_fast = 14 },
 317         .find_pll = intel_g4x_find_best_PLL,
 318 };
 319
 320 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 321         .dot = { .min = 25000, .max = 350000 },
 322         .vco = { .min = 1760000, .max = 3510000 },
 323         .n = { .min = 1, .max = 3 },
 324         .m = { .min = 79, .max = 127 },
 325         .m1 = { .min = 12, .max = 22 },
 326         .m2 = { .min = 5, .max = 9 },
 327         .p = { .min = 14, .max = 56 },
 328         .p1 = { .min = 2, .max = 8 },
 329         .p2 = { .dot_limit = 225000,
 330                 .p2_slow = 7, .p2_fast = 7 },
 331         .find_pll = intel_g4x_find_best_PLL,
 332 };
 333
 334 /* LVDS 100mhz refclk limits. */
 335 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 336         .dot = { .min = 25000, .max = 350000 },
 337         .vco = { .min = 1760000, .max = 3510000 },
 338         .n = { .min = 1, .max = 2 },
 339         .m = { .min = 79, .max = 126 },
 340         .m1 = { .min = 12, .max = 22 },
 341         .m2 = { .min = 5, .max = 9 },
 342         .p = { .min = 28, .max = 112 },
 343         .p1 = { .min = 2, .max = 8 },
 344         .p2 = { .dot_limit = 225000,
 345                 .p2_slow = 14, .p2_fast = 14 },
 346         .find_pll = intel_g4x_find_best_PLL,
 347 };
 348
 349 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 350         .dot = { .min = 25000, .max = 350000 },
 351         .vco = { .min = 1760000, .max = 3510000 },
 352         .n = { .min = 1, .max = 3 },
 353         .m = { .min = 79, .max = 126 },
 354         .m1 = { .min = 12, .max = 22 },
 355         .m2 = { .min = 5, .max = 9 },
 356         .p = { .min = 14, .max = 42 },
 357         .p1 = { .min = 2, .max = 6 },
 358         .p2 = { .dot_limit = 225000,
 359                 .p2_slow = 7, .p2_fast = 7 },
 360         .find_pll = intel_g4x_find_best_PLL,
 361 };
 362
 363 static const intel_limit_t intel_limits_ironlake_display_port = {
 364         .dot = { .min = 25000, .max = 350000 },
 365         .vco = { .min = 1760000, .max = 3510000},
 366         .n = { .min = 1, .max = 2 },
 367         .m = { .min = 81, .max = 90 },
 368         .m1 = { .min = 12, .max = 22 },
 369         .m2 = { .min = 5, .max = 9 },
 370         .p = { .min = 10, .max = 20 },
 371         .p1 = { .min = 1, .max = 2},
 372         .p2 = { .dot_limit = 0,
 373                 .p2_slow = 10, .p2_fast = 10 },
 374         .find_pll = intel_find_pll_ironlake_dp,
 375 };
 376
 377 static const intel_limit_t intel_limits_vlv_dac = {
 378         .dot = { .min = 25000, .max = 270000 },
 379         .vco = { .min = 4000000, .max = 6000000 },
 380         .n = { .min = 1, .max = 7 },
 381         .m = { .min = 22, .max = 450 }, /* guess */
 382         .m1 = { .min = 2, .max = 3 },
 383         .m2 = { .min = 11, .max = 156 },
 384         .p = { .min = 10, .max = 30 },
 385         .p1 = { .min = 2, .max = 3 },
 386         .p2 = { .dot_limit = 270000,
 387                 .p2_slow = 2, .p2_fast = 20 },
 388         .find_pll = intel_vlv_find_best_pll,
 389 };
 390
 391 static const intel_limit_t intel_limits_vlv_hdmi = {
 392         .dot = { .min = 20000, .max = 165000 },
 393         .vco = { .min = 4000000, .max = 5994000},
 394         .n = { .min = 1, .max = 7 },
 395         .m = { .min = 60, .max = 300 }, /* guess */
 396         .m1 = { .min = 2, .max = 3 },
 397         .m2 = { .min = 11, .max = 156 },
 398         .p = { .min = 10, .max = 30 },
 399         .p1 = { .min = 2, .max = 3 },
 400         .p2 = { .dot_limit = 270000,
 401                 .p2_slow = 2, .p2_fast = 20 },
 402         .find_pll = intel_vlv_find_best_pll,
 403 };
 404
 405 static const intel_limit_t intel_limits_vlv_dp = {
 406         .dot = { .min = 25000, .max = 270000 },
 407         .vco = { .min = 4000000, .max = 6000000 },
 408         .n = { .min = 1, .max = 7 },
 409         .m = { .min = 22, .max = 450 },
 410         .m1 = { .min = 2, .max = 3 },
 411         .m2 = { .min = 11, .max = 156 },
 412         .p = { .min = 10, .max = 30 },
 413         .p1 = { .min = 2, .max = 3 },
 414         .p2 = { .dot_limit = 270000,
 415                 .p2_slow = 2, .p2_fast = 20 },
 416         .find_pll = intel_vlv_find_best_pll,
 417 };
 418
 419 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
 420 {
 421         unsigned long flags;
 422         u32 val = 0;
 423
 424         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
 425         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 426                 DRM_ERROR("DPIO idle wait timed out\n");
 427                 goto out_unlock;
 428         }
 429
 430         I915_WRITE(DPIO_REG, reg);
 431         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
 432                    DPIO_BYTE);
 433         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 434                 DRM_ERROR("DPIO read wait timed out\n");
 435                 goto out_unlock;
 436         }
 437         val = I915_READ(DPIO_DATA);
 438
 439 out_unlock:
 440         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
 441         return val;
 442 }
 443
 444 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
 445                              u32 val)
 446 {
 447         unsigned long flags;
 448
 449         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
 450         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 451                 DRM_ERROR("DPIO idle wait timed out\n");
 452                 goto out_unlock;
 453         }
 454
 455         I915_WRITE(DPIO_DATA, val);
 456         I915_WRITE(DPIO_REG, reg);
 457         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
 458                    DPIO_BYTE);
 459         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
 460                 DRM_ERROR("DPIO write wait timed out\n");
 461
 462 out_unlock:
 463        spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
 464 }
 465
 466 static void vlv_init_dpio(struct drm_device *dev)
 467 {
 468         struct drm_i915_private *dev_priv = dev->dev_private;
 469
 470         /* Reset the DPIO config */
 471         I915_WRITE(DPIO_CTL, 0);
 472         POSTING_READ(DPIO_CTL);
 473         I915_WRITE(DPIO_CTL, 1);
 474         POSTING_READ(DPIO_CTL);
 475 }
 476
 477 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
 478 {
 479         DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
 480         return 1;
 481 }
 482
 483 static const struct dmi_system_id intel_dual_link_lvds[] = {
 484         {
 485                 .callback = intel_dual_link_lvds_callback,
 486                 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
 487                 .matches = {
 488                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 489                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
 490                 },
 491         },
 492         { }     /* terminating entry */
 493 };
 494
 495 static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
 496                               unsigned int reg)
 497 {
 498         unsigned int val;
 499
 500         /* use the module option value if specified */
 501         if (i915_lvds_channel_mode > 0)
 502                 return i915_lvds_channel_mode == 2;
 503
 504         if (dmi_check_system(intel_dual_link_lvds))
 505                 return true;
 506
 507         if (dev_priv->lvds_val)
 508                 val = dev_priv->lvds_val;
 509         else {
 510                 /* BIOS should set the proper LVDS register value at boot, but
 511                  * in reality, it doesn't set the value when the lid is closed;
 512                  * we need to check "the value to be set" in VBT when LVDS
 513                  * register is uninitialized.
 514                  */
 515                 val = I915_READ(reg);
 516                 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
 517                         val = dev_priv->bios_lvds_val;
 518                 dev_priv->lvds_val = val;
 519         }
 520         return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
 521 }
 522
 523 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 524                                                 int refclk)
 525 {
 526         struct drm_device *dev = crtc->dev;
 527         struct drm_i915_private *dev_priv = dev->dev_private;
 528         const intel_limit_t *limit;
 529
 530         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 531                 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
 532                         /* LVDS dual channel */
 533                         if (refclk == 100000)
 534                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 535                         else
 536                                 limit = &intel_limits_ironlake_dual_lvds;
 537                 } else {
 538                         if (refclk == 100000)
 539                                 limit = &intel_limits_ironlake_single_lvds_100m;
 540                         else
 541                                 limit = &intel_limits_ironlake_single_lvds;
 542                 }
 543         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 544                         HAS_eDP)
 545                 limit = &intel_limits_ironlake_display_port;
 546         else
 547                 limit = &intel_limits_ironlake_dac;
 548
 549         return limit;
 550 }
 551
 552 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 553 {
 554         struct drm_device *dev = crtc->dev;
 555         struct drm_i915_private *dev_priv = dev->dev_private;
 556         const intel_limit_t *limit;
 557
 558         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 559                 if (is_dual_link_lvds(dev_priv, LVDS))
 560                         /* LVDS with dual channel */
 561                         limit = &intel_limits_g4x_dual_channel_lvds;
 562                 else
 563                         /* LVDS with dual channel */
 564                         limit = &intel_limits_g4x_single_channel_lvds;
 565         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 566                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 567                 limit = &intel_limits_g4x_hdmi;
 568         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 569                 limit = &intel_limits_g4x_sdvo;
 570         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 571                 limit = &intel_limits_g4x_display_port;
 572         } else /* The option is for other outputs */
 573                 limit = &intel_limits_i9xx_sdvo;
 574
 575         return limit;
 576 }
 577
 578 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 579 {
 580         struct drm_device *dev = crtc->dev;
 581         const intel_limit_t *limit;
 582
 583         if (HAS_PCH_SPLIT(dev))
 584                 limit = intel_ironlake_limit(crtc, refclk);
 585         else if (IS_G4X(dev)) {
 586                 limit = intel_g4x_limit(crtc);
 587         } else if (IS_PINEVIEW(dev)) {
 588                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 589                         limit = &intel_limits_pineview_lvds;
 590                 else
 591                         limit = &intel_limits_pineview_sdvo;
 592         } else if (IS_VALLEYVIEW(dev)) {
 593                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
 594                         limit = &intel_limits_vlv_dac;
 595                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
 596                         limit = &intel_limits_vlv_hdmi;
 597                 else
 598                         limit = &intel_limits_vlv_dp;
 599         } else if (!IS_GEN2(dev)) {
 600                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 601                         limit = &intel_limits_i9xx_lvds;
 602                 else
 603                         limit = &intel_limits_i9xx_sdvo;
 604         } else {
 605                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 606                         limit = &intel_limits_i8xx_lvds;
 607                 else
 608                         limit = &intel_limits_i8xx_dvo;
 609         }
 610         return limit;
 611 }
 612
 613 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 614 static void pineview_clock(int refclk, intel_clock_t *clock)
 615 {
 616         clock->m = clock->m2 + 2;
 617         clock->p = clock->p1 * clock->p2;
 618         clock->vco = refclk * clock->m / clock->n;
 619         clock->dot = clock->vco / clock->p;
 620 }
 621
 622 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 623 {
 624         if (IS_PINEVIEW(dev)) {
 625                 pineview_clock(refclk, clock);
 626                 return;
 627         }
 628         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 629         clock->p = clock->p1 * clock->p2;
 630         clock->vco = refclk * clock->m / (clock->n + 2);
 631         clock->dot = clock->vco / clock->p;
 632 }
 633
 634 /**
 635  * Returns whether any output on the specified pipe is of the specified type
 636  */
 637 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 638 {
 639         struct drm_device *dev = crtc->dev;
 640         struct intel_encoder *encoder;
 641
 642         for_each_encoder_on_crtc(dev, crtc, encoder)
 643                 if (encoder->type == type)
 644                         return true;
 645
 646         return false;
 647 }
 648
 649 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 650 /**
 651  * Returns whether the given set of divisors are valid for a given refclk with
 652  * the given connectors.
 653  */
 654
 655 static bool intel_PLL_is_valid(struct drm_device *dev,
 656                                const intel_limit_t *limit,
 657                                const intel_clock_t *clock)
 658 {
 659         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 660                 INTELPllInvalid("p1 out of range\n");
 661         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 662                 INTELPllInvalid("p out of range\n");
 663         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 664                 INTELPllInvalid("m2 out of range\n");
 665         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 666                 INTELPllInvalid("m1 out of range\n");
 667         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 668                 INTELPllInvalid("m1 <= m2\n");
 669         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 670                 INTELPllInvalid("m out of range\n");
 671         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 672                 INTELPllInvalid("n out of range\n");
 673         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 674                 INTELPllInvalid("vco out of range\n");
 675         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 676          * connector, etc., rather than just a single range.
 677          */
 678         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 679                 INTELPllInvalid("dot out of range\n");
 680
 681         return true;
 682 }
 683
 684 static bool
 685 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 686                     int target, int refclk, intel_clock_t *match_clock,
 687                     intel_clock_t *best_clock)
 688
 689 {
 690         struct drm_device *dev = crtc->dev;
 691         struct drm_i915_private *dev_priv = dev->dev_private;
 692         intel_clock_t clock;
 693         int err = target;
 694
 695         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 696             (I915_READ(LVDS)) != 0) {
 697                 /*
 698                  * For LVDS, if the panel is on, just rely on its current
 699                  * settings for dual-channel.  We haven't figured out how to
 700                  * reliably set up different single/dual channel state, if we
 701                  * even can.
 702                  */
 703                 if (is_dual_link_lvds(dev_priv, LVDS))
 704                         clock.p2 = limit->p2.p2_fast;
 705                 else
 706                         clock.p2 = limit->p2.p2_slow;
 707         } else {
 708                 if (target < limit->p2.dot_limit)
 709                         clock.p2 = limit->p2.p2_slow;
 710                 else
 711                         clock.p2 = limit->p2.p2_fast;
 712         }
 713
 714         memset(best_clock, 0, sizeof(*best_clock));
 715
 716         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 717              clock.m1++) {
 718                 for (clock.m2 = limit->m2.min;
 719                      clock.m2 <= limit->m2.max; clock.m2++) {
 720                         /* m1 is always 0 in Pineview */
 721                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 722                                 break;
 723                         for (clock.n = limit->n.min;
 724                              clock.n <= limit->n.max; clock.n++) {
 725                                 for (clock.p1 = limit->p1.min;
 726                                         clock.p1 <= limit->p1.max; clock.p1++) {
 727                                         int this_err;
 728
 729                                         intel_clock(dev, refclk, &clock);
 730                                         if (!intel_PLL_is_valid(dev, limit,
 731                                                                 &clock))
 732                                                 continue;
 733                                         if (match_clock &&
 734                                             clock.p != match_clock->p)
 735                                                 continue;
 736
 737                                         this_err = abs(clock.dot - target);
 738                                         if (this_err < err) {
 739                                                 *best_clock = clock;
 740                                                 err = this_err;
 741                                         }
 742                                 }
 743                         }
 744                 }
 745         }
 746
 747         return (err != target);
 748 }
 749
 750 static bool
 751 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 752                         int target, int refclk, intel_clock_t *match_clock,
 753                         intel_clock_t *best_clock)
 754 {
 755         struct drm_device *dev = crtc->dev;
 756         struct drm_i915_private *dev_priv = dev->dev_private;
 757         intel_clock_t clock;
 758         int max_n;
 759         bool found;
 760         /* approximately equals target * 0.00585 */
 761         int err_most = (target >> 8) + (target >> 9);
 762         found = false;
 763
 764         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 765                 int lvds_reg;
 766
 767                 if (HAS_PCH_SPLIT(dev))
 768                         lvds_reg = PCH_LVDS;
 769                 else
 770                         lvds_reg = LVDS;
 771                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 772                     LVDS_CLKB_POWER_UP)
 773                         clock.p2 = limit->p2.p2_fast;
 774                 else
 775                         clock.p2 = limit->p2.p2_slow;
 776         } else {
 777                 if (target < limit->p2.dot_limit)
 778                         clock.p2 = limit->p2.p2_slow;
 779                 else
 780                         clock.p2 = limit->p2.p2_fast;
 781         }
 782
 783         memset(best_clock, 0, sizeof(*best_clock));
 784         max_n = limit->n.max;
 785         /* based on hardware requirement, prefer smaller n to precision */
 786         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 787                 /* based on hardware requirement, prefere larger m1,m2 */
 788                 for (clock.m1 = limit->m1.max;
 789                      clock.m1 >= limit->m1.min; clock.m1--) {
 790                         for (clock.m2 = limit->m2.max;
 791                              clock.m2 >= limit->m2.min; clock.m2--) {
 792                                 for (clock.p1 = limit->p1.max;
 793                                      clock.p1 >= limit->p1.min; clock.p1--) {
 794                                         int this_err;
 795
 796                                         intel_clock(dev, refclk, &clock);
 797                                         if (!intel_PLL_is_valid(dev, limit,
 798                                                                 &clock))
 799                                                 continue;
 800                                         if (match_clock &&
 801                                             clock.p != match_clock->p)
 802                                                 continue;
 803
 804                                         this_err = abs(clock.dot - target);
 805                                         if (this_err < err_most) {
 806                                                 *best_clock = clock;
 807                                                 err_most = this_err;
 808                                                 max_n = clock.n;
 809                                                 found = true;
 810                                         }
 811                                 }
 812                         }
 813                 }
 814         }
 815         return found;
 816 }
 817
 818 static bool
 819 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 820                            int target, int refclk, intel_clock_t *match_clock,
 821                            intel_clock_t *best_clock)
 822 {
 823         struct drm_device *dev = crtc->dev;
 824         intel_clock_t clock;
 825
 826         if (target < 200000) {
 827                 clock.n = 1;
 828                 clock.p1 = 2;
 829                 clock.p2 = 10;
 830                 clock.m1 = 12;
 831                 clock.m2 = 9;
 832         } else {
 833                 clock.n = 2;
 834                 clock.p1 = 1;
 835                 clock.p2 = 10;
 836                 clock.m1 = 14;
 837                 clock.m2 = 8;
 838         }
 839         intel_clock(dev, refclk, &clock);
 840         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 841         return true;
 842 }
 843
 844 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 845 static bool
 846 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 847                       int target, int refclk, intel_clock_t *match_clock,
 848                       intel_clock_t *best_clock)
 849 {
 850         intel_clock_t clock;
 851         if (target < 200000) {
 852                 clock.p1 = 2;
 853                 clock.p2 = 10;
 854                 clock.n = 2;
 855                 clock.m1 = 23;
 856                 clock.m2 = 8;
 857         } else {
 858                 clock.p1 = 1;
 859                 clock.p2 = 10;
 860                 clock.n = 1;
 861                 clock.m1 = 14;
 862                 clock.m2 = 2;
 863         }
 864         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 865         clock.p = (clock.p1 * clock.p2);
 866         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 867         clock.vco = 0;
 868         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 869         return true;
 870 }
 871 static bool
 872 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 873                         int target, int refclk, intel_clock_t *match_clock,
 874                         intel_clock_t *best_clock)
 875 {
 876         u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
 877         u32 m, n, fastclk;
 878         u32 updrate, minupdate, fracbits, p;
 879         unsigned long bestppm, ppm, absppm;
 880         int dotclk, flag;
 881
 882         flag = 0;
 883         dotclk = target * 1000;
 884         bestppm = 1000000;
 885         ppm = absppm = 0;
 886         fastclk = dotclk / (2*100);
 887         updrate = 0;
 888         minupdate = 19200;
 889         fracbits = 1;
 890         n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
 891         bestm1 = bestm2 = bestp1 = bestp2 = 0;
 892
 893         /* based on hardware requirement, prefer smaller n to precision */
 894         for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
 895                 updrate = refclk / n;
 896                 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
 897                         for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
 898                                 if (p2 > 10)
 899                                         p2 = p2 - 1;
 900                                 p = p1 * p2;
 901                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 902                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
 903                                         m2 = (((2*(fastclk * p * n / m1 )) +
 904                                                refclk) / (2*refclk));
 905                                         m = m1 * m2;
 906                                         vco = updrate * m;
 907                                         if (vco >= limit->vco.min && vco < limit->vco.max) {
 908                                                 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
 909                                                 absppm = (ppm > 0) ? ppm : (-ppm);
 910                                                 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
 911                                                         bestppm = 0;
 912                                                         flag = 1;
 913                                                 }
 914                                                 if (absppm < bestppm - 10) {
 915                                                         bestppm = absppm;
 916                                                         flag = 1;
 917                                                 }
 918                                                 if (flag) {
 919                                                         bestn = n;
 920                                                         bestm1 = m1;
 921                                                         bestm2 = m2;
 922                                                         bestp1 = p1;
 923                                                         bestp2 = p2;
 924                                                         flag = 0;
 925                                                 }
 926                                         }
 927                                 }
 928                         }
 929                 }
 930         }
 931         best_clock->n = bestn;
 932         best_clock->m1 = bestm1;
 933         best_clock->m2 = bestm2;
 934         best_clock->p1 = bestp1;
 935         best_clock->p2 = bestp2;
 936
 937         return true;
 938 }
 939
 940 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 941 {
 942         struct drm_i915_private *dev_priv = dev->dev_private;
 943         u32 frame, frame_reg = PIPEFRAME(pipe);
 944
 945         frame = I915_READ(frame_reg);
 946
 947         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 948                 DRM_DEBUG_KMS("vblank wait timed out\n");
 949 }
 950
 951 /**
 952  * intel_wait_for_vblank - wait for vblank on a given pipe
 953  * @dev: drm device
 954  * @pipe: pipe to wait for
 955  *
 956  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 957  * mode setting code.
 958  */
 959 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 960 {
 961         struct drm_i915_private *dev_priv = dev->dev_private;
 962         int pipestat_reg = PIPESTAT(pipe);
 963
 964         if (INTEL_INFO(dev)->gen >= 5) {
 965                 ironlake_wait_for_vblank(dev, pipe);
 966                 return;
 967         }
 968
 969         /* Clear existing vblank status. Note this will clear any other
 970          * sticky status fields as well.
 971          *
 972          * This races with i915_driver_irq_handler() with the result
 973          * that either function could miss a vblank event.  Here it is not
 974          * fatal, as we will either wait upon the next vblank interrupt or
 975          * timeout.  Generally speaking intel_wait_for_vblank() is only
 976          * called during modeset at which time the GPU should be idle and
 977          * should *not* be performing page flips and thus not waiting on
 978          * vblanks...
 979          * Currently, the result of us stealing a vblank from the irq
 980          * handler is that a single frame will be skipped during swapbuffers.
 981          */
 982         I915_WRITE(pipestat_reg,
 983                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 984
 985         /* Wait for vblank interrupt bit to set */
 986         if (wait_for(I915_READ(pipestat_reg) &
 987                      PIPE_VBLANK_INTERRUPT_STATUS,
 988                      50))
 989                 DRM_DEBUG_KMS("vblank wait timed out\n");
 990 }
 991
 992 /*
 993  * intel_wait_for_pipe_off - wait for pipe to turn off
 994  * @dev: drm device
 995  * @pipe: pipe to wait for
 996  *
 997  * After disabling a pipe, we can't wait for vblank in the usual way,
 998  * spinning on the vblank interrupt status bit, since we won't actually
 999  * see an interrupt when the pipe is disabled.
1000  *
1001  * On Gen4 and above:
1002  *   wait for the pipe register state bit to turn off
1003  *
1004  * Otherwise:
1005  *   wait for the display line value to settle (it usually
1006  *   ends up stopping at the start of the next frame).
1007  *
1008  */
1009 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1010 {
1011         struct drm_i915_private *dev_priv = dev->dev_private;
1012
1013         if (INTEL_INFO(dev)->gen >= 4) {
1014                 int reg = PIPECONF(pipe);
1015
1016                 /* Wait for the Pipe State to go off */
1017                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1018                              100))
1019                         WARN(1, "pipe_off wait timed out\n");
1020         } else {
1021                 u32 last_line, line_mask;
1022                 int reg = PIPEDSL(pipe);
1023                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1024
1025                 if (IS_GEN2(dev))
1026                         line_mask = DSL_LINEMASK_GEN2;
1027                 else
1028                         line_mask = DSL_LINEMASK_GEN3;
1029
1030                 /* Wait for the display line to settle */
1031                 do {
1032                         last_line = I915_READ(reg) & line_mask;
1033                         mdelay(5);
1034                 } while (((I915_READ(reg) & line_mask) != last_line) &&
1035                          time_after(timeout, jiffies));
1036                 if (time_after(jiffies, timeout))
1037                         WARN(1, "pipe_off wait timed out\n");
1038         }
1039 }
1040
1041 static const char *state_string(bool enabled)
1042 {
1043         return enabled ? "on" : "off";
1044 }
1045
1046 /* Only for pre-ILK configs */
1047 static void assert_pll(struct drm_i915_private *dev_priv,
1048                        enum pipe pipe, bool state)
1049 {
1050         int reg;
1051         u32 val;
1052         bool cur_state;
1053
1054         reg = DPLL(pipe);
1055         val = I915_READ(reg);
1056         cur_state = !!(val & DPLL_VCO_ENABLE);
1057         WARN(cur_state != state,
1058              "PLL state assertion failure (expected %s, current %s)\n",
1059              state_string(state), state_string(cur_state));
1060 }
1061 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1062 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1063
1064 /* For ILK+ */
1065 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1066                            struct intel_pch_pll *pll,
1067                            struct intel_crtc *crtc,
1068                            bool state)
1069 {
1070         u32 val;
1071         bool cur_state;
1072
1073         if (HAS_PCH_LPT(dev_priv->dev)) {
1074                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1075                 return;
1076         }
1077
1078         if (WARN (!pll,
1079                   "asserting PCH PLL %s with no PLL\n", state_string(state)))
1080                 return;
1081
1082         val = I915_READ(pll->pll_reg);
1083         cur_state = !!(val & DPLL_VCO_ENABLE);
1084         WARN(cur_state != state,
1085              "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1086              pll->pll_reg, state_string(state), state_string(cur_state), val);
1087
1088         /* Make sure the selected PLL is correctly attached to the transcoder */
1089         if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
1090                 u32 pch_dpll;
1091
1092                 pch_dpll = I915_READ(PCH_DPLL_SEL);
1093                 cur_state = pll->pll_reg == _PCH_DPLL_B;
1094                 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1095                           "PLL[%d] not attached to this transcoder %d: %08x\n",
1096                           cur_state, crtc->pipe, pch_dpll)) {
1097                         cur_state = !!(val >> (4*crtc->pipe + 3));
1098                         WARN(cur_state != state,
1099                              "PLL[%d] not %s on this transcoder %d: %08x\n",
1100                              pll->pll_reg == _PCH_DPLL_B,
1101                              state_string(state),
1102                              crtc->pipe,
1103                              val);
1104                 }
1105         }
1106 }
1107 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1108 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1109
1110 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1111                           enum pipe pipe, bool state)
1112 {
1113         int reg;
1114         u32 val;
1115         bool cur_state;
1116
1117         if (IS_HASWELL(dev_priv->dev)) {
1118                 /* On Haswell, DDI is used instead of FDI_TX_CTL */
1119                 reg = DDI_FUNC_CTL(pipe);
1120                 val = I915_READ(reg);
1121                 cur_state = !!(val & PIPE_DDI_FUNC_ENABLE);
1122         } else {
1123                 reg = FDI_TX_CTL(pipe);
1124                 val = I915_READ(reg);
1125                 cur_state = !!(val & FDI_TX_ENABLE);
1126         }
1127         WARN(cur_state != state,
1128              "FDI TX state assertion failure (expected %s, current %s)\n",
1129              state_string(state), state_string(cur_state));
1130 }
1131 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1132 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1133
1134 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1135                           enum pipe pipe, bool state)
1136 {
1137         int reg;
1138         u32 val;
1139         bool cur_state;
1140
1141         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1142                         DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1143                         return;
1144         } else {
1145                 reg = FDI_RX_CTL(pipe);
1146                 val = I915_READ(reg);
1147                 cur_state = !!(val & FDI_RX_ENABLE);
1148         }
1149         WARN(cur_state != state,
1150              "FDI RX state assertion failure (expected %s, current %s)\n",
1151              state_string(state), state_string(cur_state));
1152 }
1153 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1154 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1155
1156 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1157                                       enum pipe pipe)
1158 {
1159         int reg;
1160         u32 val;
1161
1162         /* ILK FDI PLL is always enabled */
1163         if (dev_priv->info->gen == 5)
1164                 return;
1165
1166         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1167         if (IS_HASWELL(dev_priv->dev))
1168                 return;
1169
1170         reg = FDI_TX_CTL(pipe);
1171         val = I915_READ(reg);
1172         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1173 }
1174
1175 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1176                                       enum pipe pipe)
1177 {
1178         int reg;
1179         u32 val;
1180
1181         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1182                 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1183                 return;
1184         }
1185         reg = FDI_RX_CTL(pipe);
1186         val = I915_READ(reg);
1187         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1188 }
1189
1190 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1191                                   enum pipe pipe)
1192 {
1193         int pp_reg, lvds_reg;
1194         u32 val;
1195         enum pipe panel_pipe = PIPE_A;
1196         bool locked = true;
1197
1198         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1199                 pp_reg = PCH_PP_CONTROL;
1200                 lvds_reg = PCH_LVDS;
1201         } else {
1202                 pp_reg = PP_CONTROL;
1203                 lvds_reg = LVDS;
1204         }
1205
1206         val = I915_READ(pp_reg);
1207         if (!(val & PANEL_POWER_ON) ||
1208             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1209                 locked = false;
1210
1211         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1212                 panel_pipe = PIPE_B;
1213
1214         WARN(panel_pipe == pipe && locked,
1215              "panel assertion failure, pipe %c regs locked\n",
1216              pipe_name(pipe));
1217 }
1218
1219 void assert_pipe(struct drm_i915_private *dev_priv,
1220                  enum pipe pipe, bool state)
1221 {
1222         int reg;
1223         u32 val;
1224         bool cur_state;
1225
1226         /* if we need the pipe A quirk it must be always on */
1227         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1228                 state = true;
1229
1230         reg = PIPECONF(pipe);
1231         val = I915_READ(reg);
1232         cur_state = !!(val & PIPECONF_ENABLE);
1233         WARN(cur_state != state,
1234              "pipe %c assertion failure (expected %s, current %s)\n",
1235              pipe_name(pipe), state_string(state), state_string(cur_state));
1236 }
1237
1238 static void assert_plane(struct drm_i915_private *dev_priv,
1239                          enum plane plane, bool state)
1240 {
1241         int reg;
1242         u32 val;
1243         bool cur_state;
1244
1245         reg = DSPCNTR(plane);
1246         val = I915_READ(reg);
1247         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1248         WARN(cur_state != state,
1249              "plane %c assertion failure (expected %s, current %s)\n",
1250              plane_name(plane), state_string(state), state_string(cur_state));
1251 }
1252
1253 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1254 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1255
1256 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1257                                    enum pipe pipe)
1258 {
1259         int reg, i;
1260         u32 val;
1261         int cur_pipe;
1262
1263         /* Planes are fixed to pipes on ILK+ */
1264         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1265                 reg = DSPCNTR(pipe);
1266                 val = I915_READ(reg);
1267                 WARN((val & DISPLAY_PLANE_ENABLE),
1268                      "plane %c assertion failure, should be disabled but not\n",
1269                      plane_name(pipe));
1270                 return;
1271         }
1272
1273         /* Need to check both planes against the pipe */
1274         for (i = 0; i < 2; i++) {
1275                 reg = DSPCNTR(i);
1276                 val = I915_READ(reg);
1277                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1278                         DISPPLANE_SEL_PIPE_SHIFT;
1279                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1280                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1281                      plane_name(i), pipe_name(pipe));
1282         }
1283 }
1284
1285 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1286 {
1287         u32 val;
1288         bool enabled;
1289
1290         if (HAS_PCH_LPT(dev_priv->dev)) {
1291                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1292                 return;
1293         }
1294
1295         val = I915_READ(PCH_DREF_CONTROL);
1296         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1297                             DREF_SUPERSPREAD_SOURCE_MASK));
1298         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1299 }
1300
1301 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1302                                        enum pipe pipe)
1303 {
1304         int reg;
1305         u32 val;
1306         bool enabled;
1307
1308         reg = TRANSCONF(pipe);
1309         val = I915_READ(reg);
1310         enabled = !!(val & TRANS_ENABLE);
1311         WARN(enabled,
1312              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1313              pipe_name(pipe));
1314 }
1315
1316 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1317                             enum pipe pipe, u32 port_sel, u32 val)
1318 {
1319         if ((val & DP_PORT_EN) == 0)
1320                 return false;
1321
1322         if (HAS_PCH_CPT(dev_priv->dev)) {
1323                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1324                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1325                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1326                         return false;
1327         } else {
1328                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1329                         return false;
1330         }
1331         return true;
1332 }
1333
1334 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1335                               enum pipe pipe, u32 val)
1336 {
1337         if ((val & PORT_ENABLE) == 0)
1338                 return false;
1339
1340         if (HAS_PCH_CPT(dev_priv->dev)) {
1341                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1342                         return false;
1343         } else {
1344                 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1345                         return false;
1346         }
1347         return true;
1348 }
1349
1350 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1351                               enum pipe pipe, u32 val)
1352 {
1353         if ((val & LVDS_PORT_EN) == 0)
1354                 return false;
1355
1356         if (HAS_PCH_CPT(dev_priv->dev)) {
1357                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1358                         return false;
1359         } else {
1360                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1361                         return false;
1362         }
1363         return true;
1364 }
1365
1366 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1367                               enum pipe pipe, u32 val)
1368 {
1369         if ((val & ADPA_DAC_ENABLE) == 0)
1370                 return false;
1371         if (HAS_PCH_CPT(dev_priv->dev)) {
1372                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1373                         return false;
1374         } else {
1375                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1376                         return false;
1377         }
1378         return true;
1379 }
1380
1381 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1382                                    enum pipe pipe, int reg, u32 port_sel)
1383 {
1384         u32 val = I915_READ(reg);
1385         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1386              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1387              reg, pipe_name(pipe));
1388
1389         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1390              && (val & DP_PIPEB_SELECT),
1391              "IBX PCH dp port still using transcoder B\n");
1392 }
1393
1394 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1395                                      enum pipe pipe, int reg)
1396 {
1397         u32 val = I915_READ(reg);
1398         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1399              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1400              reg, pipe_name(pipe));
1401
1402         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1403              && (val & SDVO_PIPE_B_SELECT),
1404              "IBX PCH hdmi port still using transcoder B\n");
1405 }
1406
1407 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1408                                       enum pipe pipe)
1409 {
1410         int reg;
1411         u32 val;
1412
1413         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1414         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1415         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1416
1417         reg = PCH_ADPA;
1418         val = I915_READ(reg);
1419         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1420              "PCH VGA enabled on transcoder %c, should be disabled\n",
1421              pipe_name(pipe));
1422
1423         reg = PCH_LVDS;
1424         val = I915_READ(reg);
1425         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1426              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1427              pipe_name(pipe));
1428
1429         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1430         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1431         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1432 }
1433
1434 /**
1435  * intel_enable_pll - enable a PLL
1436  * @dev_priv: i915 private structure
1437  * @pipe: pipe PLL to enable
1438  *
1439  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1440  * make sure the PLL reg is writable first though, since the panel write
1441  * protect mechanism may be enabled.
1442  *
1443  * Note!  This is for pre-ILK only.
1444  *
1445  * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1446  */
1447 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1448 {
1449         int reg;
1450         u32 val;
1451
1452         /* No really, not for ILK+ */
1453         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1454
1455         /* PLL is protected by panel, make sure we can write it */
1456         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1457                 assert_panel_unlocked(dev_priv, pipe);
1458
1459         reg = DPLL(pipe);
1460         val = I915_READ(reg);
1461         val |= DPLL_VCO_ENABLE;
1462
1463         /* We do this three times for luck */
1464         I915_WRITE(reg, val);
1465         POSTING_READ(reg);
1466         udelay(150); /* wait for warmup */
1467         I915_WRITE(reg, val);
1468         POSTING_READ(reg);
1469         udelay(150); /* wait for warmup */
1470         I915_WRITE(reg, val);
1471         POSTING_READ(reg);
1472         udelay(150); /* wait for warmup */
1473 }
1474
1475 /**
1476  * intel_disable_pll - disable a PLL
1477  * @dev_priv: i915 private structure
1478  * @pipe: pipe PLL to disable
1479  *
1480  * Disable the PLL for @pipe, making sure the pipe is off first.
1481  *
1482  * Note!  This is for pre-ILK only.
1483  */
1484 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1485 {
1486         int reg;
1487         u32 val;
1488
1489         /* Don't disable pipe A or pipe A PLLs if needed */
1490         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1491                 return;
1492
1493         /* Make sure the pipe isn't still relying on us */
1494         assert_pipe_disabled(dev_priv, pipe);
1495
1496         reg = DPLL(pipe);
1497         val = I915_READ(reg);
1498         val &= ~DPLL_VCO_ENABLE;
1499         I915_WRITE(reg, val);
1500         POSTING_READ(reg);
1501 }
1502
1503 /* SBI access */
1504 static void
1505 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1506 {
1507         unsigned long flags;
1508
1509         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1510         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1511                                 100)) {
1512                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1513                 goto out_unlock;
1514         }
1515
1516         I915_WRITE(SBI_ADDR,
1517                         (reg << 16));
1518         I915_WRITE(SBI_DATA,
1519                         value);
1520         I915_WRITE(SBI_CTL_STAT,
1521                         SBI_BUSY |
1522                         SBI_CTL_OP_CRWR);
1523
1524         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1525                                 100)) {
1526                 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1527                 goto out_unlock;
1528         }
1529
1530 out_unlock:
1531         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1532 }
1533
1534 static u32
1535 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1536 {
1537         unsigned long flags;
1538         u32 value = 0;
1539
1540         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1541         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1542                                 100)) {
1543                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1544                 goto out_unlock;
1545         }
1546
1547         I915_WRITE(SBI_ADDR,
1548                         (reg << 16));
1549         I915_WRITE(SBI_CTL_STAT,
1550                         SBI_BUSY |
1551                         SBI_CTL_OP_CRRD);
1552
1553         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1554                                 100)) {
1555                 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1556                 goto out_unlock;
1557         }
1558
1559         value = I915_READ(SBI_DATA);
1560
1561 out_unlock:
1562         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1563         return value;
1564 }
1565
1566 /**
1567  * intel_enable_pch_pll - enable PCH PLL
1568  * @dev_priv: i915 private structure
1569  * @pipe: pipe PLL to enable
1570  *
1571  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1572  * drives the transcoder clock.
1573  */
1574 static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
1575 {
1576         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1577         struct intel_pch_pll *pll;
1578         int reg;
1579         u32 val;
1580
1581         /* PCH PLLs only available on ILK, SNB and IVB */
1582         BUG_ON(dev_priv->info->gen < 5);
1583         pll = intel_crtc->pch_pll;
1584         if (pll == NULL)
1585                 return;
1586
1587         if (WARN_ON(pll->refcount == 0))
1588                 return;
1589
1590         DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1591                       pll->pll_reg, pll->active, pll->on,
1592                       intel_crtc->base.base.id);
1593
1594         /* PCH refclock must be enabled first */
1595         assert_pch_refclk_enabled(dev_priv);
1596
1597         if (pll->active++ && pll->on) {
1598                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1599                 return;
1600         }
1601
1602         DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1603
1604         reg = pll->pll_reg;
1605         val = I915_READ(reg);
1606         val |= DPLL_VCO_ENABLE;
1607         I915_WRITE(reg, val);
1608         POSTING_READ(reg);
1609         udelay(200);
1610
1611         pll->on = true;
1612 }
1613
1614 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1615 {
1616         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1617         struct intel_pch_pll *pll = intel_crtc->pch_pll;
1618         int reg;
1619         u32 val;
1620
1621         /* PCH only available on ILK+ */
1622         BUG_ON(dev_priv->info->gen < 5);
1623         if (pll == NULL)
1624                return;
1625
1626         if (WARN_ON(pll->refcount == 0))
1627                 return;
1628
1629         DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1630                       pll->pll_reg, pll->active, pll->on,
1631                       intel_crtc->base.base.id);
1632
1633         if (WARN_ON(pll->active == 0)) {
1634                 assert_pch_pll_disabled(dev_priv, pll, NULL);
1635                 return;
1636         }
1637
1638         if (--pll->active) {
1639                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1640                 return;
1641         }
1642
1643         DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1644
1645         /* Make sure transcoder isn't still depending on us */
1646         assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1647
1648         reg = pll->pll_reg;
1649         val = I915_READ(reg);
1650         val &= ~DPLL_VCO_ENABLE;
1651         I915_WRITE(reg, val);
1652         POSTING_READ(reg);
1653         udelay(200);
1654
1655         pll->on = false;
1656 }
1657
1658 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1659                                     enum pipe pipe)
1660 {
1661         int reg;
1662         u32 val, pipeconf_val;
1663         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1664
1665         /* PCH only available on ILK+ */
1666         BUG_ON(dev_priv->info->gen < 5);
1667
1668         /* Make sure PCH DPLL is enabled */
1669         assert_pch_pll_enabled(dev_priv,
1670                                to_intel_crtc(crtc)->pch_pll,
1671                                to_intel_crtc(crtc));
1672
1673         /* FDI must be feeding us bits for PCH ports */
1674         assert_fdi_tx_enabled(dev_priv, pipe);
1675         assert_fdi_rx_enabled(dev_priv, pipe);
1676
1677         if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1678                 DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
1679                 return;
1680         }
1681         reg = TRANSCONF(pipe);
1682         val = I915_READ(reg);
1683         pipeconf_val = I915_READ(PIPECONF(pipe));
1684
1685         if (HAS_PCH_IBX(dev_priv->dev)) {
1686                 /*
1687                  * make the BPC in transcoder be consistent with
1688                  * that in pipeconf reg.
1689                  */
1690                 val &= ~PIPE_BPC_MASK;
1691                 val |= pipeconf_val & PIPE_BPC_MASK;
1692         }
1693
1694         val &= ~TRANS_INTERLACE_MASK;
1695         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1696                 if (HAS_PCH_IBX(dev_priv->dev) &&
1697                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1698                         val |= TRANS_LEGACY_INTERLACED_ILK;
1699                 else
1700                         val |= TRANS_INTERLACED;
1701         else
1702                 val |= TRANS_PROGRESSIVE;
1703
1704         I915_WRITE(reg, val | TRANS_ENABLE);
1705         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1706                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1707 }
1708
1709 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1710                                      enum pipe pipe)
1711 {
1712         int reg;
1713         u32 val;
1714
1715         /* FDI relies on the transcoder */
1716         assert_fdi_tx_disabled(dev_priv, pipe);
1717         assert_fdi_rx_disabled(dev_priv, pipe);
1718
1719         /* Ports must be off as well */
1720         assert_pch_ports_disabled(dev_priv, pipe);
1721
1722         reg = TRANSCONF(pipe);
1723         val = I915_READ(reg);
1724         val &= ~TRANS_ENABLE;
1725         I915_WRITE(reg, val);
1726         /* wait for PCH transcoder off, transcoder state */
1727         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1728                 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1729 }
1730
1731 /**
1732  * intel_enable_pipe - enable a pipe, asserting requirements
1733  * @dev_priv: i915 private structure
1734  * @pipe: pipe to enable
1735  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1736  *
1737  * Enable @pipe, making sure that various hardware specific requirements
1738  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1739  *
1740  * @pipe should be %PIPE_A or %PIPE_B.
1741  *
1742  * Will wait until the pipe is actually running (i.e. first vblank) before
1743  * returning.
1744  */
1745 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1746                               bool pch_port)
1747 {
1748         int reg;
1749         u32 val;
1750
1751         /*
1752          * A pipe without a PLL won't actually be able to drive bits from
1753          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1754          * need the check.
1755          */
1756         if (!HAS_PCH_SPLIT(dev_priv->dev))
1757                 assert_pll_enabled(dev_priv, pipe);
1758         else {
1759                 if (pch_port) {
1760                         /* if driving the PCH, we need FDI enabled */
1761                         assert_fdi_rx_pll_enabled(dev_priv, pipe);
1762                         assert_fdi_tx_pll_enabled(dev_priv, pipe);
1763                 }
1764                 /* FIXME: assert CPU port conditions for SNB+ */
1765         }
1766
1767         reg = PIPECONF(pipe);
1768         val = I915_READ(reg);
1769         if (val & PIPECONF_ENABLE)
1770                 return;
1771
1772         I915_WRITE(reg, val | PIPECONF_ENABLE);
1773         intel_wait_for_vblank(dev_priv->dev, pipe);
1774 }
1775
1776 /**
1777  * intel_disable_pipe - disable a pipe, asserting requirements
1778  * @dev_priv: i915 private structure
1779  * @pipe: pipe to disable
1780  *
1781  * Disable @pipe, making sure that various hardware specific requirements
1782  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1783  *
1784  * @pipe should be %PIPE_A or %PIPE_B.
1785  *
1786  * Will wait until the pipe has shut down before returning.
1787  */
1788 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1789                                enum pipe pipe)
1790 {
1791         int reg;
1792         u32 val;
1793
1794         /*
1795          * Make sure planes won't keep trying to pump pixels to us,
1796          * or we might hang the display.
1797          */
1798         assert_planes_disabled(dev_priv, pipe);
1799
1800         /* Don't disable pipe A or pipe A PLLs if needed */
1801         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1802                 return;
1803
1804         reg = PIPECONF(pipe);
1805         val = I915_READ(reg);
1806         if ((val & PIPECONF_ENABLE) == 0)
1807                 return;
1808
1809         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1810         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1811 }
1812
1813 /*
1814  * Plane regs are double buffered, going from enabled->disabled needs a
1815  * trigger in order to latch.  The display address reg provides this.
1816  */
1817 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1818                                       enum plane plane)
1819 {
1820         I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1821         I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1822 }
1823
1824 /**
1825  * intel_enable_plane - enable a display plane on a given pipe
1826  * @dev_priv: i915 private structure
1827  * @plane: plane to enable
1828  * @pipe: pipe being fed
1829  *
1830  * Enable @plane on @pipe, making sure that @pipe is running first.
1831  */
1832 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1833                                enum plane plane, enum pipe pipe)
1834 {
1835         int reg;
1836         u32 val;
1837
1838         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1839         assert_pipe_enabled(dev_priv, pipe);
1840
1841         reg = DSPCNTR(plane);
1842         val = I915_READ(reg);
1843         if (val & DISPLAY_PLANE_ENABLE)
1844                 return;
1845
1846         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1847         intel_flush_display_plane(dev_priv, plane);
1848         intel_wait_for_vblank(dev_priv->dev, pipe);
1849 }
1850
1851 /**
1852  * intel_disable_plane - disable a display plane
1853  * @dev_priv: i915 private structure
1854  * @plane: plane to disable
1855  * @pipe: pipe consuming the data
1856  *
1857  * Disable @plane; should be an independent operation.
1858  */
1859 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1860                                 enum plane plane, enum pipe pipe)
1861 {
1862         int reg;
1863         u32 val;
1864
1865         reg = DSPCNTR(plane);
1866         val = I915_READ(reg);
1867         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1868                 return;
1869
1870         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1871         intel_flush_display_plane(dev_priv, plane);
1872         intel_wait_for_vblank(dev_priv->dev, pipe);
1873 }
1874
1875 int
1876 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1877                            struct drm_i915_gem_object *obj,
1878                            struct intel_ring_buffer *pipelined)
1879 {
1880         struct drm_i915_private *dev_priv = dev->dev_private;
1881         u32 alignment;
1882         int ret;
1883
1884         switch (obj->tiling_mode) {
1885         case I915_TILING_NONE:
1886                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1887                         alignment = 128 * 1024;
1888                 else if (INTEL_INFO(dev)->gen >= 4)
1889                         alignment = 4 * 1024;
1890                 else
1891                         alignment = 64 * 1024;
1892                 break;
1893         case I915_TILING_X:
1894                 /* pin() will align the object as required by fence */
1895                 alignment = 0;
1896                 break;
1897         case I915_TILING_Y:
1898                 /* FIXME: Is this true? */
1899                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1900                 return -EINVAL;
1901         default:
1902                 BUG();
1903         }
1904
1905         dev_priv->mm.interruptible = false;
1906         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1907         if (ret)
1908                 goto err_interruptible;
1909
1910         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1911          * fence, whereas 965+ only requires a fence if using
1912          * framebuffer compression.  For simplicity, we always install
1913          * a fence as the cost is not that onerous.
1914          */
1915         ret = i915_gem_object_get_fence(obj);
1916         if (ret)
1917                 goto err_unpin;
1918
1919         i915_gem_object_pin_fence(obj);
1920
1921         dev_priv->mm.interruptible = true;
1922         return 0;
1923
1924 err_unpin:
1925         i915_gem_object_unpin(obj);
1926 err_interruptible:
1927         dev_priv->mm.interruptible = true;
1928         return ret;
1929 }
1930
1931 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1932 {
1933         i915_gem_object_unpin_fence(obj);
1934         i915_gem_object_unpin(obj);
1935 }
1936
1937 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1938  * is assumed to be a power-of-two. */
1939 static unsigned long gen4_compute_dspaddr_offset_xtiled(int *x, int *y,
1940                                                         unsigned int bpp,
1941                                                         unsigned int pitch)
1942 {
1943         int tile_rows, tiles;
1944
1945         tile_rows = *y / 8;
1946         *y %= 8;
1947         tiles = *x / (512/bpp);
1948         *x %= 512/bpp;
1949
1950         return tile_rows * pitch * 8 + tiles * 4096;
1951 }
1952
1953 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1954                              int x, int y)
1955 {
1956         struct drm_device *dev = crtc->dev;
1957         struct drm_i915_private *dev_priv = dev->dev_private;
1958         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1959         struct intel_framebuffer *intel_fb;
1960         struct drm_i915_gem_object *obj;
1961         int plane = intel_crtc->plane;
1962         unsigned long linear_offset;
1963         u32 dspcntr;
1964         u32 reg;
1965
1966         switch (plane) {
1967         case 0:
1968         case 1:
1969                 break;
1970         default:
1971                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1972                 return -EINVAL;
1973         }
1974
1975         intel_fb = to_intel_framebuffer(fb);
1976         obj = intel_fb->obj;
1977
1978         reg = DSPCNTR(plane);
1979         dspcntr = I915_READ(reg);
1980         /* Mask out pixel format bits in case we change it */
1981         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1982         switch (fb->bits_per_pixel) {
1983         case 8:
1984                 dspcntr |= DISPPLANE_8BPP;
1985                 break;
1986         case 16:
1987                 if (fb->depth == 15)
1988                         dspcntr |= DISPPLANE_15_16BPP;
1989                 else
1990                         dspcntr |= DISPPLANE_16BPP;
1991                 break;
1992         case 24:
1993         case 32:
1994                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1995                 break;
1996         default:
1997                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
1998                 return -EINVAL;
1999         }
2000         if (INTEL_INFO(dev)->gen >= 4) {
2001                 if (obj->tiling_mode != I915_TILING_NONE)
2002                         dspcntr |= DISPPLANE_TILED;
2003                 else
2004                         dspcntr &= ~DISPPLANE_TILED;
2005         }
2006
2007         I915_WRITE(reg, dspcntr);
2008
2009         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2010
2011         if (INTEL_INFO(dev)->gen >= 4) {
2012                 intel_crtc->dspaddr_offset =
2013                         gen4_compute_dspaddr_offset_xtiled(&x, &y,
2014                                                            fb->bits_per_pixel / 8,
2015                                                            fb->pitches[0]);
2016                 linear_offset -= intel_crtc->dspaddr_offset;
2017         } else {
2018                 intel_crtc->dspaddr_offset = linear_offset;
2019         }
2020
2021         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2022                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2023         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2024         if (INTEL_INFO(dev)->gen >= 4) {
2025                 I915_MODIFY_DISPBASE(DSPSURF(plane),
2026                                      obj->gtt_offset + intel_crtc->dspaddr_offset);
2027                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2028                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2029         } else
2030                 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2031         POSTING_READ(reg);
2032
2033         return 0;
2034 }
2035
2036 static int ironlake_update_plane(struct drm_crtc *crtc,
2037                                  struct drm_framebuffer *fb, int x, int y)
2038 {
2039         struct drm_device *dev = crtc->dev;
2040         struct drm_i915_private *dev_priv = dev->dev_private;
2041         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2042         struct intel_framebuffer *intel_fb;
2043         struct drm_i915_gem_object *obj;
2044         int plane = intel_crtc->plane;
2045         unsigned long linear_offset;
2046         u32 dspcntr;
2047         u32 reg;
2048
2049         switch (plane) {
2050         case 0:
2051         case 1:
2052         case 2:
2053                 break;
2054         default:
2055                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2056                 return -EINVAL;
2057         }
2058
2059         intel_fb = to_intel_framebuffer(fb);
2060         obj = intel_fb->obj;
2061
2062         reg = DSPCNTR(plane);
2063         dspcntr = I915_READ(reg);
2064         /* Mask out pixel format bits in case we change it */
2065         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2066         switch (fb->bits_per_pixel) {
2067         case 8:
2068                 dspcntr |= DISPPLANE_8BPP;
2069                 break;
2070         case 16:
2071                 if (fb->depth != 16)
2072                         return -EINVAL;
2073
2074                 dspcntr |= DISPPLANE_16BPP;
2075                 break;
2076         case 24:
2077         case 32:
2078                 if (fb->depth == 24)
2079                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2080                 else if (fb->depth == 30)
2081                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2082                 else
2083                         return -EINVAL;
2084                 break;
2085         default:
2086                 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2087                 return -EINVAL;
2088         }
2089
2090         if (obj->tiling_mode != I915_TILING_NONE)
2091                 dspcntr |= DISPPLANE_TILED;
2092         else
2093                 dspcntr &= ~DISPPLANE_TILED;
2094
2095         /* must disable */
2096         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2097
2098         I915_WRITE(reg, dspcntr);
2099
2100         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2101         intel_crtc->dspaddr_offset =
2102                 gen4_compute_dspaddr_offset_xtiled(&x, &y,
2103                                                    fb->bits_per_pixel / 8,
2104                                                    fb->pitches[0]);
2105         linear_offset -= intel_crtc->dspaddr_offset;
2106
2107         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2108                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2109         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2110         I915_MODIFY_DISPBASE(DSPSURF(plane),
2111                              obj->gtt_offset + intel_crtc->dspaddr_offset);
2112         I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2113         I915_WRITE(DSPLINOFF(plane), linear_offset);
2114         POSTING_READ(reg);
2115
2116         return 0;
2117 }
2118
2119 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2120 static int
2121 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2122                            int x, int y, enum mode_set_atomic state)
2123 {
2124         struct drm_device *dev = crtc->dev;
2125         struct drm_i915_private *dev_priv = dev->dev_private;
2126
2127         if (dev_priv->display.disable_fbc)
2128                 dev_priv->display.disable_fbc(dev);
2129         intel_increase_pllclock(crtc);
2130
2131         return dev_priv->display.update_plane(crtc, fb, x, y);
2132 }
2133
2134 static int
2135 intel_finish_fb(struct drm_framebuffer *old_fb)
2136 {
2137         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2138         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2139         bool was_interruptible = dev_priv->mm.interruptible;
2140         int ret;
2141
2142         wait_event(dev_priv->pending_flip_queue,
2143                    atomic_read(&dev_priv->mm.wedged) ||
2144                    atomic_read(&obj->pending_flip) == 0);
2145
2146         /* Big Hammer, we also need to ensure that any pending
2147          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2148          * current scanout is retired before unpinning the old
2149          * framebuffer.
2150          *
2151          * This should only fail upon a hung GPU, in which case we
2152          * can safely continue.
2153          */
2154         dev_priv->mm.interruptible = false;
2155         ret = i915_gem_object_finish_gpu(obj);
2156         dev_priv->mm.interruptible = was_interruptible;
2157
2158         return ret;
2159 }
2160
2161 static int
2162 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2163                     struct drm_framebuffer *fb)
2164 {
2165         struct drm_device *dev = crtc->dev;
2166         struct drm_i915_private *dev_priv = dev->dev_private;
2167         struct drm_i915_master_private *master_priv;
2168         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2169         struct drm_framebuffer *old_fb;
2170         int ret;
2171
2172         /* no fb bound */
2173         if (!fb) {
2174                 DRM_ERROR("No FB bound\n");
2175                 return 0;
2176         }
2177
2178         if(intel_crtc->plane > dev_priv->num_pipe) {
2179                 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2180                                 intel_crtc->plane,
2181                                 dev_priv->num_pipe);
2182                 return -EINVAL;
2183         }
2184
2185         mutex_lock(&dev->struct_mutex);
2186         ret = intel_pin_and_fence_fb_obj(dev,
2187                                          to_intel_framebuffer(fb)->obj,
2188                                          NULL);
2189         if (ret != 0) {
2190                 mutex_unlock(&dev->struct_mutex);
2191                 DRM_ERROR("pin & fence failed\n");
2192                 return ret;
2193         }
2194
2195         if (crtc->fb)
2196                 intel_finish_fb(crtc->fb);
2197
2198         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2199         if (ret) {
2200                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2201                 mutex_unlock(&dev->struct_mutex);
2202                 DRM_ERROR("failed to update base address\n");
2203                 return ret;
2204         }
2205
2206         old_fb = crtc->fb;
2207         crtc->fb = fb;
2208         crtc->x = x;
2209         crtc->y = y;
2210
2211         if (old_fb) {
2212                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2213                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2214         }
2215
2216         intel_update_fbc(dev);
2217         mutex_unlock(&dev->struct_mutex);
2218
2219         if (!dev->primary->master)
2220                 return 0;
2221
2222         master_priv = dev->primary->master->driver_priv;
2223         if (!master_priv->sarea_priv)
2224                 return 0;
2225
2226         if (intel_crtc->pipe) {
2227                 master_priv->sarea_priv->pipeB_x = x;
2228                 master_priv->sarea_priv->pipeB_y = y;
2229         } else {
2230                 master_priv->sarea_priv->pipeA_x = x;
2231                 master_priv->sarea_priv->pipeA_y = y;
2232         }
2233
2234         return 0;
2235 }
2236
2237 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2238 {
2239         struct drm_device *dev = crtc->dev;
2240         struct drm_i915_private *dev_priv = dev->dev_private;
2241         u32 dpa_ctl;
2242
2243         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2244         dpa_ctl = I915_READ(DP_A);
2245         dpa_ctl &= ~DP_PLL_FREQ_MASK;
2246
2247         if (clock < 200000) {
2248                 u32 temp;
2249                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2250                 /* workaround for 160Mhz:
2251                    1) program 0x4600c bits 15:0 = 0x8124
2252                    2) program 0x46010 bit 0 = 1
2253                    3) program 0x46034 bit 24 = 1
2254                    4) program 0x64000 bit 14 = 1
2255                    */
2256                 temp = I915_READ(0x4600c);
2257                 temp &= 0xffff0000;
2258                 I915_WRITE(0x4600c, temp | 0x8124);
2259
2260                 temp = I915_READ(0x46010);
2261                 I915_WRITE(0x46010, temp | 1);
2262
2263                 temp = I915_READ(0x46034);
2264                 I915_WRITE(0x46034, temp | (1 << 24));
2265         } else {
2266                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2267         }
2268         I915_WRITE(DP_A, dpa_ctl);
2269
2270         POSTING_READ(DP_A);
2271         udelay(500);
2272 }
2273
2274 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2275 {
2276         struct drm_device *dev = crtc->dev;
2277         struct drm_i915_private *dev_priv = dev->dev_private;
2278         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2279         int pipe = intel_crtc->pipe;
2280         u32 reg, temp;
2281
2282         /* enable normal train */
2283         reg = FDI_TX_CTL(pipe);
2284         temp = I915_READ(reg);
2285         if (IS_IVYBRIDGE(dev)) {
2286                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2287                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2288         } else {
2289                 temp &= ~FDI_LINK_TRAIN_NONE;
2290                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2291         }
2292         I915_WRITE(reg, temp);
2293
2294         reg = FDI_RX_CTL(pipe);
2295         temp = I915_READ(reg);
2296         if (HAS_PCH_CPT(dev)) {
2297                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2298                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2299         } else {
2300                 temp &= ~FDI_LINK_TRAIN_NONE;
2301                 temp |= FDI_LINK_TRAIN_NONE;
2302         }
2303         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2304
2305         /* wait one idle pattern time */
2306         POSTING_READ(reg);
2307         udelay(1000);
2308
2309         /* IVB wants error correction enabled */
2310         if (IS_IVYBRIDGE(dev))
2311                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2312                            FDI_FE_ERRC_ENABLE);
2313 }
2314
2315 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2316 {
2317         struct drm_i915_private *dev_priv = dev->dev_private;
2318         u32 flags = I915_READ(SOUTH_CHICKEN1);
2319
2320         flags |= FDI_PHASE_SYNC_OVR(pipe);
2321         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2322         flags |= FDI_PHASE_SYNC_EN(pipe);
2323         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2324         POSTING_READ(SOUTH_CHICKEN1);
2325 }
2326
2327 /* The FDI link training functions for ILK/Ibexpeak. */
2328 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2329 {
2330         struct drm_device *dev = crtc->dev;
2331         struct drm_i915_private *dev_priv = dev->dev_private;
2332         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2333         int pipe = intel_crtc->pipe;
2334         int plane = intel_crtc->plane;
2335         u32 reg, temp, tries;
2336
2337         /* FDI needs bits from pipe & plane first */
2338         assert_pipe_enabled(dev_priv, pipe);
2339         assert_plane_enabled(dev_priv, plane);
2340
2341         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2342            for train result */
2343         reg = FDI_RX_IMR(pipe);
2344         temp = I915_READ(reg);
2345         temp &= ~FDI_RX_SYMBOL_LOCK;
2346         temp &= ~FDI_RX_BIT_LOCK;
2347         I915_WRITE(reg, temp);
2348         I915_READ(reg);
2349         udelay(150);
2350
2351         /* enable CPU FDI TX and PCH FDI RX */
2352         reg = FDI_TX_CTL(pipe);
2353         temp = I915_READ(reg);
2354         temp &= ~(7 << 19);
2355         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2356         temp &= ~FDI_LINK_TRAIN_NONE;
2357         temp |= FDI_LINK_TRAIN_PATTERN_1;
2358         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2359
2360         reg = FDI_RX_CTL(pipe);
2361         temp = I915_READ(reg);
2362         temp &= ~FDI_LINK_TRAIN_NONE;
2363         temp |= FDI_LINK_TRAIN_PATTERN_1;
2364         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2365
2366         POSTING_READ(reg);
2367         udelay(150);
2368
2369         /* Ironlake workaround, enable clock pointer after FDI enable*/
2370         if (HAS_PCH_IBX(dev)) {
2371                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2372                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2373                            FDI_RX_PHASE_SYNC_POINTER_EN);
2374         }
2375
2376         reg = FDI_RX_IIR(pipe);
2377         for (tries = 0; tries < 5; tries++) {
2378                 temp = I915_READ(reg);
2379                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2380
2381                 if ((temp & FDI_RX_BIT_LOCK)) {
2382                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2383                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2384                         break;
2385                 }
2386         }
2387         if (tries == 5)
2388                 DRM_ERROR("FDI train 1 fail!\n");
2389
2390         /* Train 2 */
2391         reg = FDI_TX_CTL(pipe);
2392         temp = I915_READ(reg);
2393         temp &= ~FDI_LINK_TRAIN_NONE;
2394         temp |= FDI_LINK_TRAIN_PATTERN_2;
2395         I915_WRITE(reg, temp);
2396
2397         reg = FDI_RX_CTL(pipe);
2398         temp = I915_READ(reg);
2399         temp &= ~FDI_LINK_TRAIN_NONE;
2400         temp |= FDI_LINK_TRAIN_PATTERN_2;
2401         I915_WRITE(reg, temp);
2402
2403         POSTING_READ(reg);
2404         udelay(150);
2405
2406         reg = FDI_RX_IIR(pipe);
2407         for (tries = 0; tries < 5; tries++) {
2408                 temp = I915_READ(reg);
2409                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2410
2411                 if (temp & FDI_RX_SYMBOL_LOCK) {
2412                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2413                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2414                         break;
2415                 }
2416         }
2417         if (tries == 5)
2418                 DRM_ERROR("FDI train 2 fail!\n");
2419
2420         DRM_DEBUG_KMS("FDI train done\n");
2421
2422 }
2423
2424 static const int snb_b_fdi_train_param[] = {
2425         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2426         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2427         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2428         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2429 };
2430
2431 /* The FDI link training functions for SNB/Cougarpoint. */
2432 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2433 {
2434         struct drm_device *dev = crtc->dev;
2435         struct drm_i915_private *dev_priv = dev->dev_private;
2436         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2437         int pipe = intel_crtc->pipe;
2438         u32 reg, temp, i, retry;
2439
2440         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2441            for train result */
2442         reg = FDI_RX_IMR(pipe);
2443         temp = I915_READ(reg);
2444         temp &= ~FDI_RX_SYMBOL_LOCK;
2445         temp &= ~FDI_RX_BIT_LOCK;
2446         I915_WRITE(reg, temp);
2447
2448         POSTING_READ(reg);
2449         udelay(150);
2450
2451         /* enable CPU FDI TX and PCH FDI RX */
2452         reg = FDI_TX_CTL(pipe);
2453         temp = I915_READ(reg);
2454         temp &= ~(7 << 19);
2455         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2456         temp &= ~FDI_LINK_TRAIN_NONE;
2457         temp |= FDI_LINK_TRAIN_PATTERN_1;
2458         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2459         /* SNB-B */
2460         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2461         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2462
2463         reg = FDI_RX_CTL(pipe);
2464         temp = I915_READ(reg);
2465         if (HAS_PCH_CPT(dev)) {
2466                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2467                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2468         } else {
2469                 temp &= ~FDI_LINK_TRAIN_NONE;
2470                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2471         }
2472         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2473
2474         POSTING_READ(reg);
2475         udelay(150);
2476
2477         if (HAS_PCH_CPT(dev))
2478                 cpt_phase_pointer_enable(dev, pipe);
2479
2480         for (i = 0; i < 4; i++) {
2481                 reg = FDI_TX_CTL(pipe);
2482                 temp = I915_READ(reg);
2483                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2484                 temp |= snb_b_fdi_train_param[i];
2485                 I915_WRITE(reg, temp);
2486
2487                 POSTING_READ(reg);
2488                 udelay(500);
2489
2490                 for (retry = 0; retry < 5; retry++) {
2491                         reg = FDI_RX_IIR(pipe);
2492                         temp = I915_READ(reg);
2493                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2494                         if (temp & FDI_RX_BIT_LOCK) {
2495                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2496                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2497                                 break;
2498                         }
2499                         udelay(50);
2500                 }
2501                 if (retry < 5)
2502                         break;
2503         }
2504         if (i == 4)
2505                 DRM_ERROR("FDI train 1 fail!\n");
2506
2507         /* Train 2 */
2508         reg = FDI_TX_CTL(pipe);
2509         temp = I915_READ(reg);
2510         temp &= ~FDI_LINK_TRAIN_NONE;
2511         temp |= FDI_LINK_TRAIN_PATTERN_2;
2512         if (IS_GEN6(dev)) {
2513                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2514                 /* SNB-B */
2515                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2516         }
2517         I915_WRITE(reg, temp);
2518
2519         reg = FDI_RX_CTL(pipe);
2520         temp = I915_READ(reg);
2521         if (HAS_PCH_CPT(dev)) {
2522                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2523                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2524         } else {
2525                 temp &= ~FDI_LINK_TRAIN_NONE;
2526                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2527         }
2528         I915_WRITE(reg, temp);
2529
2530         POSTING_READ(reg);
2531         udelay(150);
2532
2533         for (i = 0; i < 4; i++) {
2534                 reg = FDI_TX_CTL(pipe);
2535                 temp = I915_READ(reg);
2536                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2537                 temp |= snb_b_fdi_train_param[i];
2538                 I915_WRITE(reg, temp);
2539
2540                 POSTING_READ(reg);
2541                 udelay(500);
2542
2543                 for (retry = 0; retry < 5; retry++) {
2544                         reg = FDI_RX_IIR(pipe);
2545                         temp = I915_READ(reg);
2546                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2547                         if (temp & FDI_RX_SYMBOL_LOCK) {
2548                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2549                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2550                                 break;
2551                         }
2552                         udelay(50);
2553                 }
2554                 if (retry < 5)
2555                         break;
2556         }
2557         if (i == 4)
2558                 DRM_ERROR("FDI train 2 fail!\n");
2559
2560         DRM_DEBUG_KMS("FDI train done.\n");
2561 }
2562
2563 /* Manual link training for Ivy Bridge A0 parts */
2564 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2565 {
2566         struct drm_device *dev = crtc->dev;
2567         struct drm_i915_private *dev_priv = dev->dev_private;
2568         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2569         int pipe = intel_crtc->pipe;
2570         u32 reg, temp, i;
2571
2572         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2573            for train result */
2574         reg = FDI_RX_IMR(pipe);
2575         temp = I915_READ(reg);
2576         temp &= ~FDI_RX_SYMBOL_LOCK;
2577         temp &= ~FDI_RX_BIT_LOCK;
2578         I915_WRITE(reg, temp);
2579
2580         POSTING_READ(reg);
2581         udelay(150);
2582
2583         /* enable CPU FDI TX and PCH FDI RX */
2584         reg = FDI_TX_CTL(pipe);
2585         temp = I915_READ(reg);
2586         temp &= ~(7 << 19);
2587         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2588         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2589         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2590         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2591         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2592         temp |= FDI_COMPOSITE_SYNC;
2593         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2594
2595         reg = FDI_RX_CTL(pipe);
2596         temp = I915_READ(reg);
2597         temp &= ~FDI_LINK_TRAIN_AUTO;
2598         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2599         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2600         temp |= FDI_COMPOSITE_SYNC;
2601         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2602
2603         POSTING_READ(reg);
2604         udelay(150);
2605
2606         if (HAS_PCH_CPT(dev))
2607                 cpt_phase_pointer_enable(dev, pipe);
2608
2609         for (i = 0; i < 4; i++) {
2610                 reg = FDI_TX_CTL(pipe);
2611                 temp = I915_READ(reg);
2612                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2613                 temp |= snb_b_fdi_train_param[i];
2614                 I915_WRITE(reg, temp);
2615
2616                 POSTING_READ(reg);
2617                 udelay(500);
2618
2619                 reg = FDI_RX_IIR(pipe);
2620                 temp = I915_READ(reg);
2621                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2622
2623                 if (temp & FDI_RX_BIT_LOCK ||
2624                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2625                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2626                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2627                         break;
2628                 }
2629         }
2630         if (i == 4)
2631                 DRM_ERROR("FDI train 1 fail!\n");
2632
2633         /* Train 2 */
2634         reg = FDI_TX_CTL(pipe);
2635         temp = I915_READ(reg);
2636         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2637         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2638         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2639         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2640         I915_WRITE(reg, temp);
2641
2642         reg = FDI_RX_CTL(pipe);
2643         temp = I915_READ(reg);
2644         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2645         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2646         I915_WRITE(reg, temp);
2647
2648         POSTING_READ(reg);
2649         udelay(150);
2650
2651         for (i = 0; i < 4; i++) {
2652                 reg = FDI_TX_CTL(pipe);
2653                 temp = I915_READ(reg);
2654                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2655                 temp |= snb_b_fdi_train_param[i];
2656                 I915_WRITE(reg, temp);
2657
2658                 POSTING_READ(reg);
2659                 udelay(500);
2660
2661                 reg = FDI_RX_IIR(pipe);
2662                 temp = I915_READ(reg);
2663                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2664
2665                 if (temp & FDI_RX_SYMBOL_LOCK) {
2666                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2667                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2668                         break;
2669                 }
2670         }
2671         if (i == 4)
2672                 DRM_ERROR("FDI train 2 fail!\n");
2673
2674         DRM_DEBUG_KMS("FDI train done.\n");
2675 }
2676
2677 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2678 {
2679         struct drm_device *dev = intel_crtc->base.dev;
2680         struct drm_i915_private *dev_priv = dev->dev_private;
2681         int pipe = intel_crtc->pipe;
2682         u32 reg, temp;
2683
2684         /* Write the TU size bits so error detection works */
2685         I915_WRITE(FDI_RX_TUSIZE1(pipe),
2686                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2687
2688         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2689         reg = FDI_RX_CTL(pipe);
2690         temp = I915_READ(reg);
2691         temp &= ~((0x7 << 19) | (0x7 << 16));
2692         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2693         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2694         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2695
2696         POSTING_READ(reg);
2697         udelay(200);
2698
2699         /* Switch from Rawclk to PCDclk */
2700         temp = I915_READ(reg);
2701         I915_WRITE(reg, temp | FDI_PCDCLK);
2702
2703         POSTING_READ(reg);
2704         udelay(200);
2705
2706         /* On Haswell, the PLL configuration for ports and pipes is handled
2707          * separately, as part of DDI setup */
2708         if (!IS_HASWELL(dev)) {
2709                 /* Enable CPU FDI TX PLL, always on for Ironlake */
2710                 reg = FDI_TX_CTL(pipe);
2711                 temp = I915_READ(reg);
2712                 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2713                         I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2714
2715                         POSTING_READ(reg);
2716                         udelay(100);
2717                 }
2718         }
2719 }
2720
2721 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2722 {
2723         struct drm_device *dev = intel_crtc->base.dev;
2724         struct drm_i915_private *dev_priv = dev->dev_private;
2725         int pipe = intel_crtc->pipe;
2726         u32 reg, temp;
2727
2728         /* Switch from PCDclk to Rawclk */
2729         reg = FDI_RX_CTL(pipe);
2730         temp = I915_READ(reg);
2731         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2732
2733         /* Disable CPU FDI TX PLL */
2734         reg = FDI_TX_CTL(pipe);
2735         temp = I915_READ(reg);
2736         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2737
2738         POSTING_READ(reg);
2739         udelay(100);
2740
2741         reg = FDI_RX_CTL(pipe);
2742         temp = I915_READ(reg);
2743         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2744
2745         /* Wait for the clocks to turn off. */
2746         POSTING_READ(reg);
2747         udelay(100);
2748 }
2749
2750 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2751 {
2752         struct drm_i915_private *dev_priv = dev->dev_private;
2753         u32 flags = I915_READ(SOUTH_CHICKEN1);
2754
2755         flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2756         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2757         flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2758         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2759         POSTING_READ(SOUTH_CHICKEN1);
2760 }
2761 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2762 {
2763         struct drm_device *dev = crtc->dev;
2764         struct drm_i915_private *dev_priv = dev->dev_private;
2765         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2766         int pipe = intel_crtc->pipe;
2767         u32 reg, temp;
2768
2769         /* disable CPU FDI tx and PCH FDI rx */
2770         reg = FDI_TX_CTL(pipe);
2771         temp = I915_READ(reg);
2772         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2773         POSTING_READ(reg);
2774
2775         reg = FDI_RX_CTL(pipe);
2776         temp = I915_READ(reg);
2777         temp &= ~(0x7 << 16);
2778         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2779         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2780
2781         POSTING_READ(reg);
2782         udelay(100);
2783
2784         /* Ironlake workaround, disable clock pointer after downing FDI */
2785         if (HAS_PCH_IBX(dev)) {
2786                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2787                 I915_WRITE(FDI_RX_CHICKEN(pipe),
2788                            I915_READ(FDI_RX_CHICKEN(pipe) &
2789                                      ~FDI_RX_PHASE_SYNC_POINTER_EN));
2790         } else if (HAS_PCH_CPT(dev)) {
2791                 cpt_phase_pointer_disable(dev, pipe);
2792         }
2793
2794         /* still set train pattern 1 */
2795         reg = FDI_TX_CTL(pipe);
2796         temp = I915_READ(reg);
2797         temp &= ~FDI_LINK_TRAIN_NONE;
2798         temp |= FDI_LINK_TRAIN_PATTERN_1;
2799         I915_WRITE(reg, temp);
2800
2801         reg = FDI_RX_CTL(pipe);
2802         temp = I915_READ(reg);
2803         if (HAS_PCH_CPT(dev)) {
2804                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2805                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2806         } else {
2807                 temp &= ~FDI_LINK_TRAIN_NONE;
2808                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2809         }
2810         /* BPC in FDI rx is consistent with that in PIPECONF */
2811         temp &= ~(0x07 << 16);
2812         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2813         I915_WRITE(reg, temp);
2814
2815         POSTING_READ(reg);
2816         udelay(100);
2817 }
2818
2819 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2820 {
2821         struct drm_device *dev = crtc->dev;
2822         struct drm_i915_private *dev_priv = dev->dev_private;
2823         unsigned long flags;
2824         bool pending;
2825
2826         if (atomic_read(&dev_priv->mm.wedged))
2827                 return false;
2828
2829         spin_lock_irqsave(&dev->event_lock, flags);
2830         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2831         spin_unlock_irqrestore(&dev->event_lock, flags);
2832
2833         return pending;
2834 }
2835
2836 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2837 {
2838         struct drm_device *dev = crtc->dev;
2839         struct drm_i915_private *dev_priv = dev->dev_private;
2840
2841         if (crtc->fb == NULL)
2842                 return;
2843
2844         wait_event(dev_priv->pending_flip_queue,
2845                    !intel_crtc_has_pending_flip(crtc));
2846
2847         mutex_lock(&dev->struct_mutex);
2848         intel_finish_fb(crtc->fb);
2849         mutex_unlock(&dev->struct_mutex);
2850 }
2851
2852 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2853 {
2854         struct drm_device *dev = crtc->dev;
2855         struct intel_encoder *intel_encoder;
2856
2857         /*
2858          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2859          * must be driven by its own crtc; no sharing is possible.
2860          */
2861         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2862
2863                 /* On Haswell, LPT PCH handles the VGA connection via FDI, and Haswell
2864                  * CPU handles all others */
2865                 if (IS_HASWELL(dev)) {
2866                         /* It is still unclear how this will work on PPT, so throw up a warning */
2867                         WARN_ON(!HAS_PCH_LPT(dev));
2868
2869                         if (intel_encoder->type == INTEL_OUTPUT_ANALOG) {
2870                                 DRM_DEBUG_KMS("Haswell detected DAC encoder, assuming is PCH\n");
2871                                 return true;
2872                         } else {
2873                                 DRM_DEBUG_KMS("Haswell detected encoder %d, assuming is CPU\n",
2874                                               intel_encoder->type);
2875                                 return false;
2876                         }
2877                 }
2878
2879                 switch (intel_encoder->type) {
2880                 case INTEL_OUTPUT_EDP:
2881                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
2882                                 return false;
2883                         continue;
2884                 }
2885         }
2886
2887         return true;
2888 }
2889
2890 /* Program iCLKIP clock to the desired frequency */
2891 static void lpt_program_iclkip(struct drm_crtc *crtc)
2892 {
2893         struct drm_device *dev = crtc->dev;
2894         struct drm_i915_private *dev_priv = dev->dev_private;
2895         u32 divsel, phaseinc, auxdiv, phasedir = 0;
2896         u32 temp;
2897
2898         /* It is necessary to ungate the pixclk gate prior to programming
2899          * the divisors, and gate it back when it is done.
2900          */
2901         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2902
2903         /* Disable SSCCTL */
2904         intel_sbi_write(dev_priv, SBI_SSCCTL6,
2905                                 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
2906                                         SBI_SSCCTL_DISABLE);
2907
2908         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2909         if (crtc->mode.clock == 20000) {
2910                 auxdiv = 1;
2911                 divsel = 0x41;
2912                 phaseinc = 0x20;
2913         } else {
2914                 /* The iCLK virtual clock root frequency is in MHz,
2915                  * but the crtc->mode.clock in in KHz. To get the divisors,
2916                  * it is necessary to divide one by another, so we
2917                  * convert the virtual clock precision to KHz here for higher
2918                  * precision.
2919                  */
2920                 u32 iclk_virtual_root_freq = 172800 * 1000;
2921                 u32 iclk_pi_range = 64;
2922                 u32 desired_divisor, msb_divisor_value, pi_value;
2923
2924                 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2925                 msb_divisor_value = desired_divisor / iclk_pi_range;
2926                 pi_value = desired_divisor % iclk_pi_range;
2927
2928                 auxdiv = 0;
2929                 divsel = msb_divisor_value - 2;
2930                 phaseinc = pi_value;
2931         }
2932
2933         /* This should not happen with any sane values */
2934         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2935                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2936         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2937                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2938
2939         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2940                         crtc->mode.clock,
2941                         auxdiv,
2942                         divsel,
2943                         phasedir,
2944                         phaseinc);
2945
2946         /* Program SSCDIVINTPHASE6 */
2947         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
2948         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2949         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2950         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2951         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2952         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2953         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2954
2955         intel_sbi_write(dev_priv,
2956                         SBI_SSCDIVINTPHASE6,
2957                         temp);
2958
2959         /* Program SSCAUXDIV */
2960         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
2961         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2962         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2963         intel_sbi_write(dev_priv,
2964                         SBI_SSCAUXDIV6,
2965                         temp);
2966
2967
2968         /* Enable modulator and associated divider */
2969         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
2970         temp &= ~SBI_SSCCTL_DISABLE;
2971         intel_sbi_write(dev_priv,
2972                         SBI_SSCCTL6,
2973                         temp);
2974
2975         /* Wait for initialization time */
2976         udelay(24);
2977
2978         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2979 }
2980
2981 /*
2982  * Enable PCH resources required for PCH ports:
2983  *   - PCH PLLs
2984  *   - FDI training & RX/TX
2985  *   - update transcoder timings
2986  *   - DP transcoding bits
2987  *   - transcoder
2988  */
2989 static void ironlake_pch_enable(struct drm_crtc *crtc)
2990 {
2991         struct drm_device *dev = crtc->dev;
2992         struct drm_i915_private *dev_priv = dev->dev_private;
2993         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2994         int pipe = intel_crtc->pipe;
2995         u32 reg, temp;
2996
2997         assert_transcoder_disabled(dev_priv, pipe);
2998
2999         /* For PCH output, training FDI link */
3000         dev_priv->display.fdi_link_train(crtc);
3001
3002         intel_enable_pch_pll(intel_crtc);
3003
3004         if (HAS_PCH_LPT(dev)) {
3005                 DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
3006                 lpt_program_iclkip(crtc);
3007         } else if (HAS_PCH_CPT(dev)) {
3008                 u32 sel;
3009
3010                 temp = I915_READ(PCH_DPLL_SEL);
3011                 switch (pipe) {
3012                 default:
3013                 case 0:
3014                         temp |= TRANSA_DPLL_ENABLE;
3015                         sel = TRANSA_DPLLB_SEL;
3016                         break;
3017                 case 1:
3018                         temp |= TRANSB_DPLL_ENABLE;
3019                         sel = TRANSB_DPLLB_SEL;
3020                         break;
3021                 case 2:
3022                         temp |= TRANSC_DPLL_ENABLE;
3023                         sel = TRANSC_DPLLB_SEL;
3024                         break;
3025                 }
3026                 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3027                         temp |= sel;
3028                 else
3029                         temp &= ~sel;
3030                 I915_WRITE(PCH_DPLL_SEL, temp);
3031         }
3032
3033         /* set transcoder timing, panel must allow it */
3034         assert_panel_unlocked(dev_priv, pipe);
3035         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3036         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3037         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
3038
3039         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3040         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3041         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
3042         I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));
3043
3044         if (!IS_HASWELL(dev))
3045                 intel_fdi_normal_train(crtc);
3046
3047         /* For PCH DP, enable TRANS_DP_CTL */
3048         if (HAS_PCH_CPT(dev) &&
3049             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3050              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3051                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
3052                 reg = TRANS_DP_CTL(pipe);
3053                 temp = I915_READ(reg);
3054                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3055                           TRANS_DP_SYNC_MASK |
3056                           TRANS_DP_BPC_MASK);
3057                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3058                          TRANS_DP_ENH_FRAMING);
3059                 temp |= bpc << 9; /* same format but at 11:9 */
3060
3061                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3062                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3063                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3064                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3065
3066                 switch (intel_trans_dp_port_sel(crtc)) {
3067                 case PCH_DP_B:
3068                         temp |= TRANS_DP_PORT_SEL_B;
3069                         break;
3070                 case PCH_DP_C:
3071                         temp |= TRANS_DP_PORT_SEL_C;
3072                         break;
3073                 case PCH_DP_D:
3074                         temp |= TRANS_DP_PORT_SEL_D;
3075                         break;
3076                 default:
3077                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
3078                         temp |= TRANS_DP_PORT_SEL_B;
3079                         break;
3080                 }
3081
3082                 I915_WRITE(reg, temp);
3083         }
3084
3085         intel_enable_transcoder(dev_priv, pipe);
3086 }
3087
3088 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3089 {
3090         struct intel_pch_pll *pll = intel_crtc->pch_pll;
3091
3092         if (pll == NULL)
3093                 return;
3094
3095         if (pll->refcount == 0) {
3096                 WARN(1, "bad PCH PLL refcount\n");
3097                 return;
3098         }
3099
3100         --pll->refcount;
3101         intel_crtc->pch_pll = NULL;
3102 }
3103
3104 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3105 {
3106         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3107         struct intel_pch_pll *pll;
3108         int i;
3109
3110         pll = intel_crtc->pch_pll;
3111         if (pll) {
3112                 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3113                               intel_crtc->base.base.id, pll->pll_reg);
3114                 goto prepare;
3115         }
3116
3117         if (HAS_PCH_IBX(dev_priv->dev)) {
3118                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3119                 i = intel_crtc->pipe;
3120                 pll = &dev_priv->pch_plls[i];
3121
3122                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3123                               intel_crtc->base.base.id, pll->pll_reg);
3124
3125                 goto found;
3126         }
3127
3128         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3129                 pll = &dev_priv->pch_plls[i];
3130
3131                 /* Only want to check enabled timings first */
3132                 if (pll->refcount == 0)
3133                         continue;
3134
3135                 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3136                     fp == I915_READ(pll->fp0_reg)) {
3137                         DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3138                                       intel_crtc->base.base.id,
3139                                       pll->pll_reg, pll->refcount, pll->active);
3140
3141                         goto found;
3142                 }
3143         }
3144
3145         /* Ok no matching timings, maybe there's a free one? */
3146         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3147                 pll = &dev_priv->pch_plls[i];
3148                 if (pll->refcount == 0) {
3149                         DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3150                                       intel_crtc->base.base.id, pll->pll_reg);
3151                         goto found;
3152                 }
3153         }
3154
3155         return NULL;
3156
3157 found:
3158         intel_crtc->pch_pll = pll;
3159         pll->refcount++;
3160         DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3161 prepare: /* separate function? */
3162         DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3163
3164         /* Wait for the clocks to stabilize before rewriting the regs */
3165         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3166         POSTING_READ(pll->pll_reg);
3167         udelay(150);
3168
3169         I915_WRITE(pll->fp0_reg, fp);
3170         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3171         pll->on = false;
3172         return pll;
3173 }
3174
3175 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3176 {
3177         struct drm_i915_private *dev_priv = dev->dev_private;
3178         int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3179         u32 temp;
3180
3181         temp = I915_READ(dslreg);
3182         udelay(500);
3183         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3184                 /* Without this, mode sets may fail silently on FDI */
3185                 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3186                 udelay(250);
3187                 I915_WRITE(tc2reg, 0);
3188                 if (wait_for(I915_READ(dslreg) != temp, 5))
3189                         DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3190         }
3191 }
3192
3193 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3194 {
3195         struct drm_device *dev = crtc->dev;
3196         struct drm_i915_private *dev_priv = dev->dev_private;
3197         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3198         struct intel_encoder *encoder;
3199         int pipe = intel_crtc->pipe;
3200         int plane = intel_crtc->plane;
3201         u32 temp;
3202         bool is_pch_port;
3203
3204         WARN_ON(!crtc->enabled);
3205
3206         if (intel_crtc->active)
3207                 return;
3208
3209         intel_crtc->active = true;
3210         intel_update_watermarks(dev);
3211
3212         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3213                 temp = I915_READ(PCH_LVDS);
3214                 if ((temp & LVDS_PORT_EN) == 0)
3215                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3216         }
3217
3218         is_pch_port = intel_crtc_driving_pch(crtc);
3219
3220         if (is_pch_port) {
3221                 ironlake_fdi_pll_enable(intel_crtc);
3222         } else {
3223                 assert_fdi_tx_disabled(dev_priv, pipe);
3224                 assert_fdi_rx_disabled(dev_priv, pipe);
3225         }
3226
3227         for_each_encoder_on_crtc(dev, crtc, encoder)
3228                 if (encoder->pre_enable)
3229                         encoder->pre_enable(encoder);
3230
3231         if (IS_HASWELL(dev))
3232                 intel_ddi_enable_pipe_clock(intel_crtc);
3233
3234         /* Enable panel fitting for LVDS */
3235         if (dev_priv->pch_pf_size &&
3236             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3237                 /* Force use of hard-coded filter coefficients
3238                  * as some pre-programmed values are broken,
3239                  * e.g. x201.
3240                  */
3241                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3242                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3243                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3244         }
3245
3246         /*
3247          * On ILK+ LUT must be loaded before the pipe is running but with
3248          * clocks enabled
3249          */
3250         intel_crtc_load_lut(crtc);
3251
3252         if (IS_HASWELL(dev)) {
3253                 intel_ddi_set_pipe_settings(crtc);
3254                 intel_ddi_enable_pipe_func(crtc);
3255         }
3256
3257         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3258         intel_enable_plane(dev_priv, plane, pipe);
3259
3260         if (is_pch_port)
3261                 ironlake_pch_enable(crtc);
3262
3263         mutex_lock(&dev->struct_mutex);
3264         intel_update_fbc(dev);
3265         mutex_unlock(&dev->struct_mutex);
3266
3267         intel_crtc_update_cursor(crtc, true);
3268
3269         for_each_encoder_on_crtc(dev, crtc, encoder)
3270                 encoder->enable(encoder);
3271
3272         if (HAS_PCH_CPT(dev))
3273                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3274
3275         /*
3276          * There seems to be a race in PCH platform hw (at least on some
3277          * outputs) where an enabled pipe still completes any pageflip right
3278          * away (as if the pipe is off) instead of waiting for vblank. As soon
3279          * as the first vblank happend, everything works as expected. Hence just
3280          * wait for one vblank before returning to avoid strange things
3281          * happening.
3282          */
3283         intel_wait_for_vblank(dev, intel_crtc->pipe);
3284 }
3285
3286 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3287 {
3288         struct drm_device *dev = crtc->dev;
3289         struct drm_i915_private *dev_priv = dev->dev_private;
3290         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3291         struct intel_encoder *encoder;
3292         int pipe = intel_crtc->pipe;
3293         int plane = intel_crtc->plane;
3294         u32 reg, temp;
3295
3296
3297         if (!intel_crtc->active)
3298                 return;
3299
3300         for_each_encoder_on_crtc(dev, crtc, encoder)
3301                 encoder->disable(encoder);
3302
3303         intel_crtc_wait_for_pending_flips(crtc);
3304         drm_vblank_off(dev, pipe);
3305         intel_crtc_update_cursor(crtc, false);
3306
3307         intel_disable_plane(dev_priv, plane, pipe);
3308
3309         if (dev_priv->cfb_plane == plane)
3310                 intel_disable_fbc(dev);
3311
3312         intel_disable_pipe(dev_priv, pipe);
3313
3314         if (IS_HASWELL(dev))
3315                 intel_ddi_disable_pipe_func(dev_priv, pipe);
3316
3317         /* Disable PF */
3318         I915_WRITE(PF_CTL(pipe), 0);
3319         I915_WRITE(PF_WIN_SZ(pipe), 0);
3320
3321         if (IS_HASWELL(dev))
3322                 intel_ddi_disable_pipe_clock(intel_crtc);
3323
3324         for_each_encoder_on_crtc(dev, crtc, encoder)
3325                 if (encoder->post_disable)
3326                         encoder->post_disable(encoder);
3327
3328         ironlake_fdi_disable(crtc);
3329
3330         intel_disable_transcoder(dev_priv, pipe);
3331
3332         if (HAS_PCH_CPT(dev)) {
3333                 /* disable TRANS_DP_CTL */
3334                 reg = TRANS_DP_CTL(pipe);
3335                 temp = I915_READ(reg);
3336                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3337                 temp |= TRANS_DP_PORT_SEL_NONE;
3338                 I915_WRITE(reg, temp);
3339
3340                 /* disable DPLL_SEL */
3341                 temp = I915_READ(PCH_DPLL_SEL);
3342                 switch (pipe) {
3343                 case 0:
3344                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3345                         break;
3346                 case 1:
3347                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3348                         break;
3349                 case 2:
3350                         /* C shares PLL A or B */
3351                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3352                         break;
3353                 default:
3354                         BUG(); /* wtf */
3355                 }
3356                 I915_WRITE(PCH_DPLL_SEL, temp);
3357         }
3358
3359         /* disable PCH DPLL */
3360         intel_disable_pch_pll(intel_crtc);
3361
3362         ironlake_fdi_pll_disable(intel_crtc);
3363
3364         intel_crtc->active = false;
3365         intel_update_watermarks(dev);
3366
3367         mutex_lock(&dev->struct_mutex);
3368         intel_update_fbc(dev);
3369         mutex_unlock(&dev->struct_mutex);
3370 }
3371
3372 static void ironlake_crtc_off(struct drm_crtc *crtc)
3373 {
3374         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3375         intel_put_pch_pll(intel_crtc);
3376 }
3377
3378 static void haswell_crtc_off(struct drm_crtc *crtc)
3379 {
3380         intel_ddi_put_crtc_pll(crtc);
3381 }
3382
3383 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3384 {
3385         if (!enable && intel_crtc->overlay) {
3386                 struct drm_device *dev = intel_crtc->base.dev;
3387                 struct drm_i915_private *dev_priv = dev->dev_private;
3388
3389                 mutex_lock(&dev->struct_mutex);
3390                 dev_priv->mm.interruptible = false;
3391                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3392                 dev_priv->mm.interruptible = true;
3393                 mutex_unlock(&dev->struct_mutex);
3394         }
3395
3396         /* Let userspace switch the overlay on again. In most cases userspace
3397          * has to recompute where to put it anyway.
3398          */
3399 }
3400
3401 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3402 {
3403         struct drm_device *dev = crtc->dev;
3404         struct drm_i915_private *dev_priv = dev->dev_private;
3405         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3406         struct intel_encoder *encoder;
3407         int pipe = intel_crtc->pipe;
3408         int plane = intel_crtc->plane;
3409
3410         WARN_ON(!crtc->enabled);
3411
3412         if (intel_crtc->active)
3413                 return;
3414
3415         intel_crtc->active = true;
3416         intel_update_watermarks(dev);
3417
3418         intel_enable_pll(dev_priv, pipe);
3419         intel_enable_pipe(dev_priv, pipe, false);
3420         intel_enable_plane(dev_priv, plane, pipe);
3421
3422         intel_crtc_load_lut(crtc);
3423         intel_update_fbc(dev);
3424
3425         /* Give the overlay scaler a chance to enable if it's on this pipe */
3426         intel_crtc_dpms_overlay(intel_crtc, true);
3427         intel_crtc_update_cursor(crtc, true);
3428
3429         for_each_encoder_on_crtc(dev, crtc, encoder)
3430                 encoder->enable(encoder);
3431 }
3432
3433 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3434 {
3435         struct drm_device *dev = crtc->dev;
3436         struct drm_i915_private *dev_priv = dev->dev_private;
3437         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3438         struct intel_encoder *encoder;
3439         int pipe = intel_crtc->pipe;
3440         int plane = intel_crtc->plane;
3441
3442
3443         if (!intel_crtc->active)
3444                 return;
3445
3446         for_each_encoder_on_crtc(dev, crtc, encoder)
3447                 encoder->disable(encoder);
3448
3449         /* Give the overlay scaler a chance to disable if it's on this pipe */
3450         intel_crtc_wait_for_pending_flips(crtc);
3451         drm_vblank_off(dev, pipe);
3452         intel_crtc_dpms_overlay(intel_crtc, false);
3453         intel_crtc_update_cursor(crtc, false);
3454
3455         if (dev_priv->cfb_plane == plane)
3456                 intel_disable_fbc(dev);
3457
3458         intel_disable_plane(dev_priv, plane, pipe);
3459         intel_disable_pipe(dev_priv, pipe);
3460         intel_disable_pll(dev_priv, pipe);
3461
3462         intel_crtc->active = false;
3463         intel_update_fbc(dev);
3464         intel_update_watermarks(dev);
3465 }
3466
3467 static void i9xx_crtc_off(struct drm_crtc *crtc)
3468 {
3469 }
3470
3471 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3472                                     bool enabled)
3473 {
3474         struct drm_device *dev = crtc->dev;
3475         struct drm_i915_master_private *master_priv;
3476         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3477         int pipe = intel_crtc->pipe;
3478
3479         if (!dev->primary->master)
3480                 return;
3481
3482         master_priv = dev->primary->master->driver_priv;
3483         if (!master_priv->sarea_priv)
3484                 return;
3485
3486         switch (pipe) {
3487         case 0:
3488                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3489                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3490                 break;
3491         case 1:
3492                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3493                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3494                 break;
3495         default:
3496                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3497                 break;
3498         }
3499 }
3500
3501 /**
3502  * Sets the power management mode of the pipe and plane.
3503  */
3504 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3505 {
3506         struct drm_device *dev = crtc->dev;
3507         struct drm_i915_private *dev_priv = dev->dev_private;
3508         struct intel_encoder *intel_encoder;
3509         bool enable = false;
3510
3511         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3512                 enable |= intel_encoder->connectors_active;
3513
3514         if (enable)
3515                 dev_priv->display.crtc_enable(crtc);
3516         else
3517                 dev_priv->display.crtc_disable(crtc);
3518
3519         intel_crtc_update_sarea(crtc, enable);
3520 }
3521
3522 static void intel_crtc_noop(struct drm_crtc *crtc)
3523 {
3524 }
3525
3526 static void intel_crtc_disable(struct drm_crtc *crtc)
3527 {
3528         struct drm_device *dev = crtc->dev;
3529         struct drm_connector *connector;
3530         struct drm_i915_private *dev_priv = dev->dev_private;
3531
3532         /* crtc should still be enabled when we disable it. */
3533         WARN_ON(!crtc->enabled);
3534
3535         dev_priv->display.crtc_disable(crtc);
3536         intel_crtc_update_sarea(crtc, false);
3537         dev_priv->display.off(crtc);
3538
3539         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3540         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3541
3542         if (crtc->fb) {
3543                 mutex_lock(&dev->struct_mutex);
3544                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3545                 mutex_unlock(&dev->struct_mutex);
3546                 crtc->fb = NULL;
3547         }
3548
3549         /* Update computed state. */
3550         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3551                 if (!connector->encoder || !connector->encoder->crtc)
3552                         continue;
3553
3554                 if (connector->encoder->crtc != crtc)
3555                         continue;
3556
3557                 connector->dpms = DRM_MODE_DPMS_OFF;
3558                 to_intel_encoder(connector->encoder)->connectors_active = false;
3559         }
3560 }
3561
3562 void intel_modeset_disable(struct drm_device *dev)
3563 {
3564         struct drm_crtc *crtc;
3565
3566         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3567                 if (crtc->enabled)
3568                         intel_crtc_disable(crtc);
3569         }
3570 }
3571
3572 void intel_encoder_noop(struct drm_encoder *encoder)
3573 {
3574 }
3575
3576 void intel_encoder_destroy(struct drm_encoder *encoder)
3577 {
3578         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3579
3580         drm_encoder_cleanup(encoder);
3581         kfree(intel_encoder);
3582 }
3583
3584 /* Simple dpms helper for encodres with just one connector, no cloning and only
3585  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3586  * state of the entire output pipe. */
3587 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3588 {
3589         if (mode == DRM_MODE_DPMS_ON) {
3590                 encoder->connectors_active = true;
3591
3592                 intel_crtc_update_dpms(encoder->base.crtc);
3593         } else {
3594                 encoder->connectors_active = false;
3595
3596                 intel_crtc_update_dpms(encoder->base.crtc);
3597         }
3598 }
3599
3600 /* Cross check the actual hw state with our own modeset state tracking (and it's
3601  * internal consistency). */
3602 static void intel_connector_check_state(struct intel_connector *connector)
3603 {
3604         if (connector->get_hw_state(connector)) {
3605                 struct intel_encoder *encoder = connector->encoder;
3606                 struct drm_crtc *crtc;
3607                 bool encoder_enabled;
3608                 enum pipe pipe;
3609
3610                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3611                               connector->base.base.id,
3612                               drm_get_connector_name(&connector->base));
3613
3614                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3615                      "wrong connector dpms state\n");
3616                 WARN(connector->base.encoder != &encoder->base,
3617                      "active connector not linked to encoder\n");
3618                 WARN(!encoder->connectors_active,
3619                      "encoder->connectors_active not set\n");
3620
3621                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3622                 WARN(!encoder_enabled, "encoder not enabled\n");
3623                 if (WARN_ON(!encoder->base.crtc))
3624                         return;
3625
3626                 crtc = encoder->base.crtc;
3627
3628                 WARN(!crtc->enabled, "crtc not enabled\n");
3629                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3630                 WARN(pipe != to_intel_crtc(crtc)->pipe,
3631                      "encoder active on the wrong pipe\n");
3632         }
3633 }
3634
3635 /* Even simpler default implementation, if there's really no special case to
3636  * consider. */
3637 void intel_connector_dpms(struct drm_connector *connector, int mode)
3638 {
3639         struct intel_encoder *encoder = intel_attached_encoder(connector);
3640
3641         /* All the simple cases only support two dpms states. */
3642         if (mode != DRM_MODE_DPMS_ON)
3643                 mode = DRM_MODE_DPMS_OFF;
3644
3645         if (mode == connector->dpms)
3646                 return;
3647
3648         connector->dpms = mode;
3649
3650         /* Only need to change hw state when actually enabled */
3651         if (encoder->base.crtc)
3652                 intel_encoder_dpms(encoder, mode);
3653         else
3654                 WARN_ON(encoder->connectors_active != false);
3655
3656         intel_modeset_check_state(connector->dev);
3657 }
3658
3659 /* Simple connector->get_hw_state implementation for encoders that support only
3660  * one connector and no cloning and hence the encoder state determines the state
3661  * of the connector. */
3662 bool intel_connector_get_hw_state(struct intel_connector *connector)
3663 {
3664         enum pipe pipe = 0;
3665         struct intel_encoder *encoder = connector->encoder;
3666
3667         return encoder->get_hw_state(encoder, &pipe);
3668 }
3669
3670 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3671                                   const struct drm_display_mode *mode,
3672                                   struct drm_display_mode *adjusted_mode)
3673 {
3674         struct drm_device *dev = crtc->dev;
3675
3676         if (HAS_PCH_SPLIT(dev)) {
3677                 /* FDI link clock is fixed at 2.7G */
3678                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3679                         return false;
3680         }
3681
3682         /* All interlaced capable intel hw wants timings in frames. Note though
3683          * that intel_lvds_mode_fixup does some funny tricks with the crtc
3684          * timings, so we need to be careful not to clobber these.*/
3685         if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3686                 drm_mode_set_crtcinfo(adjusted_mode, 0);
3687
3688         /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3689          * with a hsync front porch of 0.
3690          */
3691         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3692                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3693                 return false;
3694
3695         return true;
3696 }
3697
3698 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3699 {
3700         return 400000; /* FIXME */
3701 }
3702
3703 static int i945_get_display_clock_speed(struct drm_device *dev)
3704 {
3705         return 400000;
3706 }
3707
3708 static int i915_get_display_clock_speed(struct drm_device *dev)
3709 {
3710         return 333000;
3711 }
3712
3713 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3714 {
3715         return 200000;
3716 }
3717
3718 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3719 {
3720         u16 gcfgc = 0;
3721
3722         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3723
3724         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3725                 return 133000;
3726         else {
3727                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3728                 case GC_DISPLAY_CLOCK_333_MHZ:
3729                         return 333000;
3730                 default:
3731                 case GC_DISPLAY_CLOCK_190_200_MHZ:
3732                         return 190000;
3733                 }
3734         }
3735 }
3736
3737 static int i865_get_display_clock_speed(struct drm_device *dev)
3738 {
3739         return 266000;
3740 }
3741
3742 static int i855_get_display_clock_speed(struct drm_device *dev)
3743 {
3744         u16 hpllcc = 0;
3745         /* Assume that the hardware is in the high speed state.  This
3746          * should be the default.
3747          */
3748         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3749         case GC_CLOCK_133_200:
3750         case GC_CLOCK_100_200:
3751                 return 200000;
3752         case GC_CLOCK_166_250:
3753                 return 250000;
3754         case GC_CLOCK_100_133:
3755                 return 133000;
3756         }
3757
3758         /* Shouldn't happen */
3759         return 0;
3760 }
3761
3762 static int i830_get_display_clock_speed(struct drm_device *dev)
3763 {
3764         return 133000;
3765 }
3766
3767 struct fdi_m_n {
3768         u32        tu;
3769         u32        gmch_m;
3770         u32        gmch_n;
3771         u32        link_m;
3772         u32        link_n;
3773 };
3774
3775 static void
3776 fdi_reduce_ratio(u32 *num, u32 *den)
3777 {
3778         while (*num > 0xffffff || *den > 0xffffff) {
3779                 *num >>= 1;
3780                 *den >>= 1;
3781         }
3782 }
3783
3784 static void
3785 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3786                      int link_clock, struct fdi_m_n *m_n)
3787 {
3788         m_n->tu = 64; /* default size */
3789
3790         /* BUG_ON(pixel_clock > INT_MAX / 36); */
3791         m_n->gmch_m = bits_per_pixel * pixel_clock;
3792         m_n->gmch_n = link_clock * nlanes * 8;
3793         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3794
3795         m_n->link_m = pixel_clock;
3796         m_n->link_n = link_clock;
3797         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3798 }
3799
3800 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3801 {
3802         if (i915_panel_use_ssc >= 0)
3803                 return i915_panel_use_ssc != 0;
3804         return dev_priv->lvds_use_ssc
3805                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
3806 }
3807
3808 /**
3809  * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3810  * @crtc: CRTC structure
3811  * @mode: requested mode
3812  *
3813  * A pipe may be connected to one or more outputs.  Based on the depth of the
3814  * attached framebuffer, choose a good color depth to use on the pipe.
3815  *
3816  * If possible, match the pipe depth to the fb depth.  In some cases, this
3817  * isn't ideal, because the connected output supports a lesser or restricted
3818  * set of depths.  Resolve that here:
3819  *    LVDS typically supports only 6bpc, so clamp down in that case
3820  *    HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
3821  *    Displays may support a restricted set as well, check EDID and clamp as
3822  *      appropriate.
3823  *    DP may want to dither down to 6bpc to fit larger modes
3824  *
3825  * RETURNS:
3826  * Dithering requirement (i.e. false if display bpc and pipe bpc match,
3827  * true if they don't match).
3828  */
3829 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
3830                                          struct drm_framebuffer *fb,
3831                                          unsigned int *pipe_bpp,
3832                                          struct drm_display_mode *mode)
3833 {
3834         struct drm_device *dev = crtc->dev;
3835         struct drm_i915_private *dev_priv = dev->dev_private;
3836         struct drm_connector *connector;
3837         struct intel_encoder *intel_encoder;
3838         unsigned int display_bpc = UINT_MAX, bpc;
3839
3840         /* Walk the encoders & connectors on this crtc, get min bpc */
3841         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3842
3843                 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
3844                         unsigned int lvds_bpc;
3845
3846                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
3847                             LVDS_A3_POWER_UP)
3848                                 lvds_bpc = 8;
3849                         else
3850                                 lvds_bpc = 6;
3851
3852                         if (lvds_bpc < display_bpc) {
3853                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
3854                                 display_bpc = lvds_bpc;
3855                         }
3856                         continue;
3857                 }
3858
3859                 /* Not one of the known troublemakers, check the EDID */
3860                 list_for_each_entry(connector, &dev->mode_config.connector_list,
3861                                     head) {
3862                         if (connector->encoder != &intel_encoder->base)
3863                                 continue;
3864
3865                         /* Don't use an invalid EDID bpc value */
3866                         if (connector->display_info.bpc &&
3867                             connector->display_info.bpc < display_bpc) {
3868                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
3869                                 display_bpc = connector->display_info.bpc;
3870                         }
3871                 }
3872
3873                 /*
3874                  * HDMI is either 12 or 8, so if the display lets 10bpc sneak
3875                  * through, clamp it down.  (Note: >12bpc will be caught below.)
3876                  */
3877                 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
3878                         if (display_bpc > 8 && display_bpc < 12) {
3879                                 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
3880                                 display_bpc = 12;
3881                         } else {
3882                                 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
3883                                 display_bpc = 8;
3884                         }
3885                 }
3886         }
3887
3888         if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3889                 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
3890                 display_bpc = 6;
3891         }
3892
3893         /*
3894          * We could just drive the pipe at the highest bpc all the time and
3895          * enable dithering as needed, but that costs bandwidth.  So choose
3896          * the minimum value that expresses the full color range of the fb but
3897          * also stays within the max display bpc discovered above.
3898          */
3899
3900         switch (fb->depth) {
3901         case 8:
3902                 bpc = 8; /* since we go through a colormap */
3903                 break;
3904         case 15:
3905         case 16:
3906                 bpc = 6; /* min is 18bpp */
3907                 break;
3908         case 24:
3909                 bpc = 8;
3910                 break;
3911         case 30:
3912                 bpc = 10;
3913                 break;
3914         case 48:
3915                 bpc = 12;
3916                 break;
3917         default:
3918                 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
3919                 bpc = min((unsigned int)8, display_bpc);
3920                 break;
3921         }
3922
3923         display_bpc = min(display_bpc, bpc);
3924
3925         DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
3926                       bpc, display_bpc);
3927
3928         *pipe_bpp = display_bpc * 3;
3929
3930         return display_bpc != bpc;
3931 }
3932
3933 static int vlv_get_refclk(struct drm_crtc *crtc)
3934 {
3935         struct drm_device *dev = crtc->dev;
3936         struct drm_i915_private *dev_priv = dev->dev_private;
3937         int refclk = 27000; /* for DP & HDMI */
3938
3939         return 100000; /* only one validated so far */
3940
3941         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
3942                 refclk = 96000;
3943         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3944                 if (intel_panel_use_ssc(dev_priv))
3945                         refclk = 100000;
3946                 else
3947                         refclk = 96000;
3948         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
3949                 refclk = 100000;
3950         }
3951
3952         return refclk;
3953 }
3954
3955 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
3956 {
3957         struct drm_device *dev = crtc->dev;
3958         struct drm_i915_private *dev_priv = dev->dev_private;
3959         int refclk;
3960
3961         if (IS_VALLEYVIEW(dev)) {
3962                 refclk = vlv_get_refclk(crtc);
3963         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3964             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
3965                 refclk = dev_priv->lvds_ssc_freq * 1000;
3966                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3967                               refclk / 1000);
3968         } else if (!IS_GEN2(dev)) {
3969                 refclk = 96000;
3970         } else {
3971                 refclk = 48000;
3972         }
3973
3974         return refclk;
3975 }
3976
3977 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
3978                                       intel_clock_t *clock)
3979 {
3980         /* SDVO TV has fixed PLL values depend on its clock range,
3981            this mirrors vbios setting. */
3982         if (adjusted_mode->clock >= 100000
3983             && adjusted_mode->clock < 140500) {
3984                 clock->p1 = 2;
3985                 clock->p2 = 10;
3986                 clock->n = 3;
3987                 clock->m1 = 16;
3988                 clock->m2 = 8;
3989         } else if (adjusted_mode->clock >= 140500
3990                    && adjusted_mode->clock <= 200000) {
3991                 clock->p1 = 1;
3992                 clock->p2 = 10;
3993                 clock->n = 6;
3994                 clock->m1 = 12;
3995                 clock->m2 = 8;
3996         }
3997 }
3998
3999 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4000                                      intel_clock_t *clock,
4001                                      intel_clock_t *reduced_clock)
4002 {
4003         struct drm_device *dev = crtc->dev;
4004         struct drm_i915_private *dev_priv = dev->dev_private;
4005         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4006         int pipe = intel_crtc->pipe;
4007         u32 fp, fp2 = 0;
4008
4009         if (IS_PINEVIEW(dev)) {
4010                 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4011                 if (reduced_clock)
4012                         fp2 = (1 << reduced_clock->n) << 16 |
4013                                 reduced_clock->m1 << 8 | reduced_clock->m2;
4014         } else {
4015                 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4016                 if (reduced_clock)
4017                         fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4018                                 reduced_clock->m2;
4019         }
4020
4021         I915_WRITE(FP0(pipe), fp);
4022
4023         intel_crtc->lowfreq_avail = false;
4024         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4025             reduced_clock && i915_powersave) {
4026                 I915_WRITE(FP1(pipe), fp2);
4027                 intel_crtc->lowfreq_avail = true;
4028         } else {
4029                 I915_WRITE(FP1(pipe), fp);
4030         }
4031 }
4032
4033 static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
4034                               struct drm_display_mode *adjusted_mode)
4035 {
4036         struct drm_device *dev = crtc->dev;
4037         struct drm_i915_private *dev_priv = dev->dev_private;
4038         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4039         int pipe = intel_crtc->pipe;
4040         u32 temp;
4041
4042         temp = I915_READ(LVDS);
4043         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4044         if (pipe == 1) {
4045                 temp |= LVDS_PIPEB_SELECT;
4046         } else {
4047                 temp &= ~LVDS_PIPEB_SELECT;
4048         }
4049         /* set the corresponsding LVDS_BORDER bit */
4050         temp |= dev_priv->lvds_border_bits;
4051         /* Set the B0-B3 data pairs corresponding to whether we're going to
4052          * set the DPLLs for dual-channel mode or not.
4053          */
4054         if (clock->p2 == 7)
4055                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4056         else
4057                 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4058
4059         /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4060          * appropriately here, but we need to look more thoroughly into how
4061          * panels behave in the two modes.
4062          */
4063         /* set the dithering flag on LVDS as needed */
4064         if (INTEL_INFO(dev)->gen >= 4) {
4065                 if (dev_priv->lvds_dither)
4066                         temp |= LVDS_ENABLE_DITHER;
4067                 else
4068                         temp &= ~LVDS_ENABLE_DITHER;
4069         }
4070         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4071         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4072                 temp |= LVDS_HSYNC_POLARITY;
4073         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4074                 temp |= LVDS_VSYNC_POLARITY;
4075         I915_WRITE(LVDS, temp);
4076 }
4077
4078 static void vlv_update_pll(struct drm_crtc *crtc,
4079                            struct drm_display_mode *mode,
4080                            struct drm_display_mode *adjusted_mode,
4081                            intel_clock_t *clock, intel_clock_t *reduced_clock,
4082                            int num_connectors)
4083 {
4084         struct drm_device *dev = crtc->dev;
4085         struct drm_i915_private *dev_priv = dev->dev_private;
4086         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4087         int pipe = intel_crtc->pipe;
4088         u32 dpll, mdiv, pdiv;
4089         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4090         bool is_sdvo;
4091         u32 temp;
4092
4093         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4094                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4095
4096         dpll = DPLL_VGA_MODE_DIS;
4097         dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4098         dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4099         dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4100
4101         I915_WRITE(DPLL(pipe), dpll);
4102         POSTING_READ(DPLL(pipe));
4103
4104         bestn = clock->n;
4105         bestm1 = clock->m1;
4106         bestm2 = clock->m2;
4107         bestp1 = clock->p1;
4108         bestp2 = clock->p2;
4109
4110         /*
4111          * In Valleyview PLL and program lane counter registers are exposed
4112          * through DPIO interface
4113          */
4114         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4115         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4116         mdiv |= ((bestn << DPIO_N_SHIFT));
4117         mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4118         mdiv |= (1 << DPIO_K_SHIFT);
4119         mdiv |= DPIO_ENABLE_CALIBRATION;
4120         intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4121
4122         intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4123
4124         pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
4125                 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4126                 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4127                 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4128         intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4129
4130         intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
4131
4132         dpll |= DPLL_VCO_ENABLE;
4133         I915_WRITE(DPLL(pipe), dpll);
4134         POSTING_READ(DPLL(pipe));
4135         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4136                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4137
4138         intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4139
4140         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4141                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4142
4143         I915_WRITE(DPLL(pipe), dpll);
4144
4145         /* Wait for the clocks to stabilize. */
4146         POSTING_READ(DPLL(pipe));
4147         udelay(150);
4148
4149         temp = 0;
4150         if (is_sdvo) {
4151                 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4152                 if (temp > 1)
4153                         temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4154                 else
4155                         temp = 0;
4156         }
4157         I915_WRITE(DPLL_MD(pipe), temp);
4158         POSTING_READ(DPLL_MD(pipe));
4159
4160         /* Now program lane control registers */
4161         if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4162                         || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4163         {
4164                 temp = 0x1000C4;
4165                 if(pipe == 1)
4166                         temp |= (1 << 21);
4167                 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4168         }
4169         if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4170         {
4171                 temp = 0x1000C4;
4172                 if(pipe == 1)
4173                         temp |= (1 << 21);
4174                 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4175         }
4176 }
4177
4178 static void i9xx_update_pll(struct drm_crtc *crtc,
4179                             struct drm_display_mode *mode,
4180                             struct drm_display_mode *adjusted_mode,
4181                             intel_clock_t *clock, intel_clock_t *reduced_clock,
4182                             int num_connectors)
4183 {
4184         struct drm_device *dev = crtc->dev;
4185         struct drm_i915_private *dev_priv = dev->dev_private;
4186         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4187         int pipe = intel_crtc->pipe;
4188         u32 dpll;
4189         bool is_sdvo;
4190
4191         i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4192
4193         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4194                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4195
4196         dpll = DPLL_VGA_MODE_DIS;
4197
4198         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4199                 dpll |= DPLLB_MODE_LVDS;
4200         else
4201                 dpll |= DPLLB_MODE_DAC_SERIAL;
4202         if (is_sdvo) {
4203                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4204                 if (pixel_multiplier > 1) {
4205                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4206                                 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4207                 }
4208                 dpll |= DPLL_DVO_HIGH_SPEED;
4209         }
4210         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4211                 dpll |= DPLL_DVO_HIGH_SPEED;
4212
4213         /* compute bitmask from p1 value */
4214         if (IS_PINEVIEW(dev))
4215                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4216         else {
4217                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4218                 if (IS_G4X(dev) && reduced_clock)
4219                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4220         }
4221         switch (clock->p2) {
4222         case 5:
4223                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4224                 break;
4225         case 7:
4226                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4227                 break;
4228         case 10:
4229                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4230                 break;
4231         case 14:
4232                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4233                 break;
4234         }
4235         if (INTEL_INFO(dev)->gen >= 4)
4236                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4237
4238         if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4239                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4240         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4241                 /* XXX: just matching BIOS for now */
4242                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4243                 dpll |= 3;
4244         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4245                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4246                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4247         else
4248                 dpll |= PLL_REF_INPUT_DREFCLK;
4249
4250         dpll |= DPLL_VCO_ENABLE;
4251         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4252         POSTING_READ(DPLL(pipe));
4253         udelay(150);
4254
4255         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4256          * This is an exception to the general rule that mode_set doesn't turn
4257          * things on.
4258          */
4259         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4260                 intel_update_lvds(crtc, clock, adjusted_mode);
4261
4262         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4263                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4264
4265         I915_WRITE(DPLL(pipe), dpll);
4266
4267         /* Wait for the clocks to stabilize. */
4268         POSTING_READ(DPLL(pipe));
4269         udelay(150);
4270
4271         if (INTEL_INFO(dev)->gen >= 4) {
4272                 u32 temp = 0;
4273                 if (is_sdvo) {
4274                         temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4275                         if (temp > 1)
4276                                 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4277                         else
4278                                 temp = 0;
4279                 }
4280                 I915_WRITE(DPLL_MD(pipe), temp);
4281         } else {
4282                 /* The pixel multiplier can only be updated once the
4283                  * DPLL is enabled and the clocks are stable.
4284                  *
4285                  * So write it again.
4286                  */
4287                 I915_WRITE(DPLL(pipe), dpll);
4288         }
4289 }
4290
4291 static void i8xx_update_pll(struct drm_crtc *crtc,
4292                             struct drm_display_mode *adjusted_mode,
4293                             intel_clock_t *clock, intel_clock_t *reduced_clock,
4294                             int num_connectors)
4295 {
4296         struct drm_device *dev = crtc->dev;
4297         struct drm_i915_private *dev_priv = dev->dev_private;
4298         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4299         int pipe = intel_crtc->pipe;
4300         u32 dpll;
4301
4302         i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4303
4304         dpll = DPLL_VGA_MODE_DIS;
4305
4306         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4307                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4308         } else {
4309                 if (clock->p1 == 2)
4310                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4311                 else
4312                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4313                 if (clock->p2 == 4)
4314                         dpll |= PLL_P2_DIVIDE_BY_4;
4315         }
4316
4317         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4318                 /* XXX: just matching BIOS for now */
4319                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4320                 dpll |= 3;
4321         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4322                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4323                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4324         else
4325                 dpll |= PLL_REF_INPUT_DREFCLK;
4326
4327         dpll |= DPLL_VCO_ENABLE;
4328         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4329         POSTING_READ(DPLL(pipe));
4330         udelay(150);
4331
4332         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4333          * This is an exception to the general rule that mode_set doesn't turn
4334          * things on.
4335          */
4336         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4337                 intel_update_lvds(crtc, clock, adjusted_mode);
4338
4339         I915_WRITE(DPLL(pipe), dpll);
4340
4341         /* Wait for the clocks to stabilize. */
4342         POSTING_READ(DPLL(pipe));
4343         udelay(150);
4344
4345         /* The pixel multiplier can only be updated once the
4346          * DPLL is enabled and the clocks are stable.
4347          *
4348          * So write it again.
4349          */
4350         I915_WRITE(DPLL(pipe), dpll);
4351 }
4352
4353 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4354                                    struct drm_display_mode *mode,
4355                                    struct drm_display_mode *adjusted_mode)
4356 {
4357         struct drm_device *dev = intel_crtc->base.dev;
4358         struct drm_i915_private *dev_priv = dev->dev_private;
4359         enum pipe pipe = intel_crtc->pipe;
4360         uint32_t vsyncshift;
4361
4362         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4363                 /* the chip adds 2 halflines automatically */
4364                 adjusted_mode->crtc_vtotal -= 1;
4365                 adjusted_mode->crtc_vblank_end -= 1;
4366                 vsyncshift = adjusted_mode->crtc_hsync_start
4367                              - adjusted_mode->crtc_htotal / 2;
4368         } else {
4369                 vsyncshift = 0;
4370         }
4371
4372         if (INTEL_INFO(dev)->gen > 3)
4373                 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
4374
4375         I915_WRITE(HTOTAL(pipe),
4376                    (adjusted_mode->crtc_hdisplay - 1) |
4377                    ((adjusted_mode->crtc_htotal - 1) << 16));
4378         I915_WRITE(HBLANK(pipe),
4379                    (adjusted_mode->crtc_hblank_start - 1) |
4380                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4381         I915_WRITE(HSYNC(pipe),
4382                    (adjusted_mode->crtc_hsync_start - 1) |
4383                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4384
4385         I915_WRITE(VTOTAL(pipe),
4386                    (adjusted_mode->crtc_vdisplay - 1) |
4387                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4388         I915_WRITE(VBLANK(pipe),
4389                    (adjusted_mode->crtc_vblank_start - 1) |
4390                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4391         I915_WRITE(VSYNC(pipe),
4392                    (adjusted_mode->crtc_vsync_start - 1) |
4393                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4394
4395         /* pipesrc controls the size that is scaled from, which should
4396          * always be the user's requested size.
4397          */
4398         I915_WRITE(PIPESRC(pipe),
4399                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4400 }
4401
4402 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4403                               struct drm_display_mode *mode,
4404                               struct drm_display_mode *adjusted_mode,
4405                               int x, int y,
4406                               struct drm_framebuffer *fb)
4407 {
4408         struct drm_device *dev = crtc->dev;
4409         struct drm_i915_private *dev_priv = dev->dev_private;
4410         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4411         int pipe = intel_crtc->pipe;
4412         int plane = intel_crtc->plane;
4413         int refclk, num_connectors = 0;
4414         intel_clock_t clock, reduced_clock;
4415         u32 dspcntr, pipeconf;
4416         bool ok, has_reduced_clock = false, is_sdvo = false;
4417         bool is_lvds = false, is_tv = false, is_dp = false;
4418         struct intel_encoder *encoder;
4419         const intel_limit_t *limit;
4420         int ret;
4421
4422         for_each_encoder_on_crtc(dev, crtc, encoder) {
4423                 switch (encoder->type) {
4424                 case INTEL_OUTPUT_LVDS:
4425                         is_lvds = true;
4426                         break;
4427                 case INTEL_OUTPUT_SDVO:
4428                 case INTEL_OUTPUT_HDMI:
4429                         is_sdvo = true;
4430                         if (encoder->needs_tv_clock)
4431                                 is_tv = true;
4432                         break;
4433                 case INTEL_OUTPUT_TVOUT:
4434                         is_tv = true;
4435                         break;
4436                 case INTEL_OUTPUT_DISPLAYPORT:
4437                         is_dp = true;
4438                         break;
4439                 }
4440
4441                 num_connectors++;
4442         }
4443
4444         refclk = i9xx_get_refclk(crtc, num_connectors);
4445
4446         /*
4447          * Returns a set of divisors for the desired target clock with the given
4448          * refclk, or FALSE.  The returned values represent the clock equation:
4449          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4450          */
4451         limit = intel_limit(crtc, refclk);
4452         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4453                              &clock);
4454         if (!ok) {
4455                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4456                 return -EINVAL;
4457         }
4458
4459         /* Ensure that the cursor is valid for the new mode before changing... */
4460         intel_crtc_update_cursor(crtc, true);
4461
4462         if (is_lvds && dev_priv->lvds_downclock_avail) {
4463                 /*
4464                  * Ensure we match the reduced clock's P to the target clock.
4465                  * If the clocks don't match, we can't switch the display clock
4466                  * by using the FP0/FP1. In such case we will disable the LVDS
4467                  * downclock feature.
4468                 */
4469                 has_reduced_clock = limit->find_pll(limit, crtc,
4470                                                     dev_priv->lvds_downclock,
4471                                                     refclk,
4472                                                     &clock,
4473                                                     &reduced_clock);
4474         }
4475
4476         if (is_sdvo && is_tv)
4477                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4478
4479         if (IS_GEN2(dev))
4480                 i8xx_update_pll(crtc, adjusted_mode, &clock,
4481                                 has_reduced_clock ? &reduced_clock : NULL,
4482                                 num_connectors);
4483         else if (IS_VALLEYVIEW(dev))
4484                 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4485                                 has_reduced_clock ? &reduced_clock : NULL,
4486                                 num_connectors);
4487         else
4488                 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4489                                 has_reduced_clock ? &reduced_clock : NULL,
4490                                 num_connectors);
4491
4492         /* setup pipeconf */
4493         pipeconf = I915_READ(PIPECONF(pipe));
4494
4495         /* Set up the display plane register */
4496         dspcntr = DISPPLANE_GAMMA_ENABLE;
4497
4498         if (pipe == 0)
4499                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4500         else
4501                 dspcntr |= DISPPLANE_SEL_PIPE_B;
4502
4503         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4504                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4505                  * core speed.
4506                  *
4507                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4508                  * pipe == 0 check?
4509                  */
4510                 if (mode->clock >
4511                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4512                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4513                 else
4514                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4515         }
4516
4517         /* default to 8bpc */
4518         pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4519         if (is_dp) {
4520                 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4521                         pipeconf |= PIPECONF_BPP_6 |
4522                                     PIPECONF_DITHER_EN |
4523                                     PIPECONF_DITHER_TYPE_SP;
4524                 }
4525         }
4526
4527         if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4528                 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4529                         pipeconf |= PIPECONF_BPP_6 |
4530                                         PIPECONF_ENABLE |
4531                                         I965_PIPECONF_ACTIVE;
4532                 }
4533         }
4534
4535         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4536         drm_mode_debug_printmodeline(mode);
4537
4538         if (HAS_PIPE_CXSR(dev)) {
4539                 if (intel_crtc->lowfreq_avail) {
4540                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4541                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4542                 } else {
4543                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4544                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4545                 }
4546         }
4547
4548         pipeconf &= ~PIPECONF_INTERLACE_MASK;
4549         if (!IS_GEN2(dev) &&
4550             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4551                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4552         else
4553                 pipeconf |= PIPECONF_PROGRESSIVE;
4554
4555         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
4556
4557         /* pipesrc and dspsize control the size that is scaled from,
4558          * which should always be the user's requested size.
4559          */
4560         I915_WRITE(DSPSIZE(plane),
4561                    ((mode->vdisplay - 1) << 16) |
4562                    (mode->hdisplay - 1));
4563         I915_WRITE(DSPPOS(plane), 0);
4564
4565         I915_WRITE(PIPECONF(pipe), pipeconf);
4566         POSTING_READ(PIPECONF(pipe));
4567         intel_enable_pipe(dev_priv, pipe, false);
4568
4569         intel_wait_for_vblank(dev, pipe);
4570
4571         I915_WRITE(DSPCNTR(plane), dspcntr);
4572         POSTING_READ(DSPCNTR(plane));
4573
4574         ret = intel_pipe_set_base(crtc, x, y, fb);
4575
4576         intel_update_watermarks(dev);
4577
4578         return ret;
4579 }
4580
4581 /*
4582  * Initialize reference clocks when the driver loads
4583  */
4584 void ironlake_init_pch_refclk(struct drm_device *dev)
4585 {
4586         struct drm_i915_private *dev_priv = dev->dev_private;
4587         struct drm_mode_config *mode_config = &dev->mode_config;
4588         struct intel_encoder *encoder;
4589         u32 temp;
4590         bool has_lvds = false;
4591         bool has_cpu_edp = false;
4592         bool has_pch_edp = false;
4593         bool has_panel = false;
4594         bool has_ck505 = false;
4595         bool can_ssc = false;
4596
4597         /* We need to take the global config into account */
4598         list_for_each_entry(encoder, &mode_config->encoder_list,
4599                             base.head) {
4600                 switch (encoder->type) {
4601                 case INTEL_OUTPUT_LVDS:
4602                         has_panel = true;
4603                         has_lvds = true;
4604                         break;
4605                 case INTEL_OUTPUT_EDP:
4606                         has_panel = true;
4607                         if (intel_encoder_is_pch_edp(&encoder->base))
4608                                 has_pch_edp = true;
4609                         else
4610                                 has_cpu_edp = true;
4611                         break;
4612                 }
4613         }
4614
4615         if (HAS_PCH_IBX(dev)) {
4616                 has_ck505 = dev_priv->display_clock_mode;
4617                 can_ssc = has_ck505;
4618         } else {
4619                 has_ck505 = false;
4620                 can_ssc = true;
4621         }
4622
4623         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4624                       has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4625                       has_ck505);
4626
4627         /* Ironlake: try to setup display ref clock before DPLL
4628          * enabling. This is only under driver's control after
4629          * PCH B stepping, previous chipset stepping should be
4630          * ignoring this setting.
4631          */
4632         temp = I915_READ(PCH_DREF_CONTROL);
4633         /* Always enable nonspread source */
4634         temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4635
4636         if (has_ck505)
4637                 temp |= DREF_NONSPREAD_CK505_ENABLE;
4638         else
4639                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4640
4641         if (has_panel) {
4642                 temp &= ~DREF_SSC_SOURCE_MASK;
4643                 temp |= DREF_SSC_SOURCE_ENABLE;
4644
4645                 /* SSC must be turned on before enabling the CPU output  */
4646                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4647                         DRM_DEBUG_KMS("Using SSC on panel\n");
4648                         temp |= DREF_SSC1_ENABLE;
4649                 } else
4650                         temp &= ~DREF_SSC1_ENABLE;
4651
4652                 /* Get SSC going before enabling the outputs */
4653                 I915_WRITE(PCH_DREF_CONTROL, temp);
4654                 POSTING_READ(PCH_DREF_CONTROL);
4655                 udelay(200);
4656
4657                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4658
4659                 /* Enable CPU source on CPU attached eDP */
4660                 if (has_cpu_edp) {
4661                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4662                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
4663                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4664                         }
4665                         else
4666                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4667                 } else
4668                         temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4669
4670                 I915_WRITE(PCH_DREF_CONTROL, temp);
4671                 POSTING_READ(PCH_DREF_CONTROL);
4672                 udelay(200);
4673         } else {
4674                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4675
4676                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4677
4678                 /* Turn off CPU output */
4679                 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4680
4681                 I915_WRITE(PCH_DREF_CONTROL, temp);
4682                 POSTING_READ(PCH_DREF_CONTROL);
4683                 udelay(200);
4684
4685                 /* Turn off the SSC source */
4686                 temp &= ~DREF_SSC_SOURCE_MASK;
4687                 temp |= DREF_SSC_SOURCE_DISABLE;
4688
4689                 /* Turn off SSC1 */
4690                 temp &= ~ DREF_SSC1_ENABLE;
4691
4692                 I915_WRITE(PCH_DREF_CONTROL, temp);
4693                 POSTING_READ(PCH_DREF_CONTROL);
4694                 udelay(200);
4695         }
4696 }
4697
4698 static int ironlake_get_refclk(struct drm_crtc *crtc)
4699 {
4700         struct drm_device *dev = crtc->dev;
4701         struct drm_i915_private *dev_priv = dev->dev_private;
4702         struct intel_encoder *encoder;
4703         struct intel_encoder *edp_encoder = NULL;
4704         int num_connectors = 0;
4705         bool is_lvds = false;
4706
4707         for_each_encoder_on_crtc(dev, crtc, encoder) {
4708                 switch (encoder->type) {
4709                 case INTEL_OUTPUT_LVDS:
4710                         is_lvds = true;
4711                         break;
4712                 case INTEL_OUTPUT_EDP:
4713                         edp_encoder = encoder;
4714                         break;
4715                 }
4716                 num_connectors++;
4717         }
4718
4719         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4720                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4721                               dev_priv->lvds_ssc_freq);
4722                 return dev_priv->lvds_ssc_freq * 1000;
4723         }
4724
4725         return 120000;
4726 }
4727
4728 static void ironlake_set_pipeconf(struct drm_crtc *crtc,
4729                                   struct drm_display_mode *adjusted_mode,
4730                                   bool dither)
4731 {
4732         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4733         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4734         int pipe = intel_crtc->pipe;
4735         uint32_t val;
4736
4737         val = I915_READ(PIPECONF(pipe));
4738
4739         val &= ~PIPE_BPC_MASK;
4740         switch (intel_crtc->bpp) {
4741         case 18:
4742                 val |= PIPE_6BPC;
4743                 break;
4744         case 24:
4745                 val |= PIPE_8BPC;
4746                 break;
4747         case 30:
4748                 val |= PIPE_10BPC;
4749                 break;
4750         case 36:
4751                 val |= PIPE_12BPC;
4752                 break;
4753         default:
4754                 /* Case prevented by intel_choose_pipe_bpp_dither. */
4755                 BUG();
4756         }
4757
4758         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4759         if (dither)
4760                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
4761
4762         val &= ~PIPECONF_INTERLACE_MASK;
4763         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4764                 val |= PIPECONF_INTERLACED_ILK;
4765         else
4766                 val |= PIPECONF_PROGRESSIVE;
4767
4768         I915_WRITE(PIPECONF(pipe), val);
4769         POSTING_READ(PIPECONF(pipe));
4770 }
4771
4772 static void haswell_set_pipeconf(struct drm_crtc *crtc,
4773                                  struct drm_display_mode *adjusted_mode,
4774                                  bool dither)
4775 {
4776         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4777         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4778         int pipe = intel_crtc->pipe;
4779         uint32_t val;
4780
4781         val = I915_READ(PIPECONF(pipe));
4782
4783         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4784         if (dither)
4785                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
4786
4787         val &= ~PIPECONF_INTERLACE_MASK_HSW;
4788         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4789                 val |= PIPECONF_INTERLACED_ILK;
4790         else
4791                 val |= PIPECONF_PROGRESSIVE;
4792
4793         I915_WRITE(PIPECONF(pipe), val);
4794         POSTING_READ(PIPECONF(pipe));
4795 }
4796
4797 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
4798                                     struct drm_display_mode *adjusted_mode,
4799                                     intel_clock_t *clock,
4800                                     bool *has_reduced_clock,
4801                                     intel_clock_t *reduced_clock)
4802 {
4803         struct drm_device *dev = crtc->dev;
4804         struct drm_i915_private *dev_priv = dev->dev_private;
4805         struct intel_encoder *intel_encoder;
4806         int refclk;
4807         const intel_limit_t *limit;
4808         bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
4809
4810         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4811                 switch (intel_encoder->type) {
4812                 case INTEL_OUTPUT_LVDS:
4813                         is_lvds = true;
4814                         break;
4815                 case INTEL_OUTPUT_SDVO:
4816                 case INTEL_OUTPUT_HDMI:
4817                         is_sdvo = true;
4818                         if (intel_encoder->needs_tv_clock)
4819                                 is_tv = true;
4820                         break;
4821                 case INTEL_OUTPUT_TVOUT:
4822                         is_tv = true;
4823                         break;
4824                 }
4825         }
4826
4827         refclk = ironlake_get_refclk(crtc);
4828
4829         /*
4830          * Returns a set of divisors for the desired target clock with the given
4831          * refclk, or FALSE.  The returned values represent the clock equation:
4832          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4833          */
4834         limit = intel_limit(crtc, refclk);
4835         ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4836                               clock);
4837         if (!ret)
4838                 return false;
4839
4840         if (is_lvds && dev_priv->lvds_downclock_avail) {
4841                 /*
4842                  * Ensure we match the reduced clock's P to the target clock.
4843                  * If the clocks don't match, we can't switch the display clock
4844                  * by using the FP0/FP1. In such case we will disable the LVDS
4845                  * downclock feature.
4846                 */
4847                 *has_reduced_clock = limit->find_pll(limit, crtc,
4848                                                      dev_priv->lvds_downclock,
4849                                                      refclk,
4850                                                      clock,
4851                                                      reduced_clock);
4852         }
4853
4854         if (is_sdvo && is_tv)
4855                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
4856
4857         return true;
4858 }
4859
4860 static void ironlake_set_m_n(struct drm_crtc *crtc,
4861                              struct drm_display_mode *mode,
4862                              struct drm_display_mode *adjusted_mode)
4863 {
4864         struct drm_device *dev = crtc->dev;
4865         struct drm_i915_private *dev_priv = dev->dev_private;
4866         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4867         enum pipe pipe = intel_crtc->pipe;
4868         struct intel_encoder *intel_encoder, *edp_encoder = NULL;
4869         struct fdi_m_n m_n = {0};
4870         int target_clock, pixel_multiplier, lane, link_bw;
4871         bool is_dp = false, is_cpu_edp = false;
4872
4873         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4874                 switch (intel_encoder->type) {
4875                 case INTEL_OUTPUT_DISPLAYPORT:
4876                         is_dp = true;
4877                         break;
4878                 case INTEL_OUTPUT_EDP:
4879                         is_dp = true;
4880                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
4881                                 is_cpu_edp = true;
4882                         edp_encoder = intel_encoder;
4883                         break;
4884                 }
4885         }
4886
4887         /* FDI link */
4888         pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4889         lane = 0;
4890         /* CPU eDP doesn't require FDI link, so just set DP M/N
4891            according to current link config */
4892         if (is_cpu_edp) {
4893                 intel_edp_link_config(edp_encoder, &lane, &link_bw);
4894         } else {
4895                 /* FDI is a binary signal running at ~2.7GHz, encoding
4896                  * each output octet as 10 bits. The actual frequency
4897                  * is stored as a divider into a 100MHz clock, and the
4898                  * mode pixel clock is stored in units of 1KHz.
4899                  * Hence the bw of each lane in terms of the mode signal
4900                  * is:
4901                  */
4902                 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4903         }
4904
4905         /* [e]DP over FDI requires target mode clock instead of link clock. */
4906         if (edp_encoder)
4907                 target_clock = intel_edp_target_clock(edp_encoder, mode);
4908         else if (is_dp)
4909                 target_clock = mode->clock;
4910         else
4911                 target_clock = adjusted_mode->clock;
4912
4913         if (!lane) {
4914                 /*
4915                  * Account for spread spectrum to avoid
4916                  * oversubscribing the link. Max center spread
4917                  * is 2.5%; use 5% for safety's sake.
4918                  */
4919                 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
4920                 lane = bps / (link_bw * 8) + 1;
4921         }
4922
4923         intel_crtc->fdi_lanes = lane;
4924
4925         if (pixel_multiplier > 1)
4926                 link_bw *= pixel_multiplier;
4927         ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
4928                              &m_n);
4929
4930         I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4931         I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4932         I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
4933         I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
4934 }
4935
4936 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
4937                                       struct drm_display_mode *adjusted_mode,
4938                                       intel_clock_t *clock, u32 fp)
4939 {
4940         struct drm_crtc *crtc = &intel_crtc->base;
4941         struct drm_device *dev = crtc->dev;
4942         struct drm_i915_private *dev_priv = dev->dev_private;
4943         struct intel_encoder *intel_encoder;
4944         uint32_t dpll;
4945         int factor, pixel_multiplier, num_connectors = 0;
4946         bool is_lvds = false, is_sdvo = false, is_tv = false;
4947         bool is_dp = false, is_cpu_edp = false;
4948
4949         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4950                 switch (intel_encoder->type) {
4951                 case INTEL_OUTPUT_LVDS:
4952                         is_lvds = true;
4953                         break;
4954                 case INTEL_OUTPUT_SDVO:
4955                 case INTEL_OUTPUT_HDMI:
4956                         is_sdvo = true;
4957                         if (intel_encoder->needs_tv_clock)
4958                                 is_tv = true;
4959                         break;
4960                 case INTEL_OUTPUT_TVOUT:
4961                         is_tv = true;
4962                         break;
4963                 case INTEL_OUTPUT_DISPLAYPORT:
4964                         is_dp = true;
4965                         break;
4966                 case INTEL_OUTPUT_EDP:
4967                         is_dp = true;
4968                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
4969                                 is_cpu_edp = true;
4970                         break;
4971                 }
4972
4973                 num_connectors++;
4974         }
4975
4976         /* Enable autotuning of the PLL clock (if permissible) */
4977         factor = 21;
4978         if (is_lvds) {
4979                 if ((intel_panel_use_ssc(dev_priv) &&
4980                      dev_priv->lvds_ssc_freq == 100) ||
4981                     (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4982                         factor = 25;
4983         } else if (is_sdvo && is_tv)
4984                 factor = 20;
4985
4986         if (clock->m < factor * clock->n)
4987                 fp |= FP_CB_TUNE;
4988
4989         dpll = 0;
4990
4991         if (is_lvds)
4992                 dpll |= DPLLB_MODE_LVDS;
4993         else
4994                 dpll |= DPLLB_MODE_DAC_SERIAL;
4995         if (is_sdvo) {
4996                 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4997                 if (pixel_multiplier > 1) {
4998                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
4999                 }
5000                 dpll |= DPLL_DVO_HIGH_SPEED;
5001         }
5002         if (is_dp && !is_cpu_edp)
5003                 dpll |= DPLL_DVO_HIGH_SPEED;
5004
5005         /* compute bitmask from p1 value */
5006         dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5007         /* also FPA1 */
5008         dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5009
5010         switch (clock->p2) {
5011         case 5:
5012                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5013                 break;
5014         case 7:
5015                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5016                 break;
5017         case 10:
5018                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5019                 break;
5020         case 14:
5021                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5022                 break;
5023         }
5024
5025         if (is_sdvo && is_tv)
5026                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5027         else if (is_tv)
5028                 /* XXX: just matching BIOS for now */
5029                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5030                 dpll |= 3;
5031         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5032                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5033         else
5034                 dpll |= PLL_REF_INPUT_DREFCLK;
5035
5036         return dpll;
5037 }
5038
5039 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5040                                   struct drm_display_mode *mode,
5041                                   struct drm_display_mode *adjusted_mode,
5042                                   int x, int y,
5043                                   struct drm_framebuffer *fb)
5044 {
5045         struct drm_device *dev = crtc->dev;
5046         struct drm_i915_private *dev_priv = dev->dev_private;
5047         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5048         int pipe = intel_crtc->pipe;
5049         int plane = intel_crtc->plane;
5050         int num_connectors = 0;
5051         intel_clock_t clock, reduced_clock;
5052         u32 dpll, fp = 0, fp2 = 0;
5053         bool ok, has_reduced_clock = false;
5054         bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5055         struct intel_encoder *encoder;
5056         u32 temp;
5057         int ret;
5058         bool dither;
5059
5060         for_each_encoder_on_crtc(dev, crtc, encoder) {
5061                 switch (encoder->type) {
5062                 case INTEL_OUTPUT_LVDS:
5063                         is_lvds = true;
5064                         break;
5065                 case INTEL_OUTPUT_DISPLAYPORT:
5066                         is_dp = true;
5067                         break;
5068                 case INTEL_OUTPUT_EDP:
5069                         is_dp = true;
5070                         if (!intel_encoder_is_pch_edp(&encoder->base))
5071                                 is_cpu_edp = true;
5072                         break;
5073                 }
5074
5075                 num_connectors++;
5076         }
5077
5078         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5079              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5080
5081         ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5082                                      &has_reduced_clock, &reduced_clock);
5083         if (!ok) {
5084                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5085                 return -EINVAL;
5086         }
5087
5088         /* Ensure that the cursor is valid for the new mode before changing... */
5089         intel_crtc_update_cursor(crtc, true);
5090
5091         /* determine panel color depth */
5092         dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp, mode);
5093         if (is_lvds && dev_priv->lvds_dither)
5094                 dither = true;
5095
5096         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5097         if (has_reduced_clock)
5098                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5099                         reduced_clock.m2;
5100
5101         dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
5102
5103         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5104         drm_mode_debug_printmodeline(mode);
5105
5106         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5107         if (!is_cpu_edp) {
5108                 struct intel_pch_pll *pll;
5109
5110                 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5111                 if (pll == NULL) {
5112                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5113                                          pipe);
5114                         return -EINVAL;
5115                 }
5116         } else
5117                 intel_put_pch_pll(intel_crtc);
5118
5119         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5120          * This is an exception to the general rule that mode_set doesn't turn
5121          * things on.
5122          */
5123         if (is_lvds) {
5124                 temp = I915_READ(PCH_LVDS);
5125                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5126                 if (HAS_PCH_CPT(dev)) {
5127                         temp &= ~PORT_TRANS_SEL_MASK;
5128                         temp |= PORT_TRANS_SEL_CPT(pipe);
5129                 } else {
5130                         if (pipe == 1)
5131                                 temp |= LVDS_PIPEB_SELECT;
5132                         else
5133                                 temp &= ~LVDS_PIPEB_SELECT;
5134                 }
5135
5136                 /* set the corresponsding LVDS_BORDER bit */
5137                 temp |= dev_priv->lvds_border_bits;
5138                 /* Set the B0-B3 data pairs corresponding to whether we're going to
5139                  * set the DPLLs for dual-channel mode or not.
5140                  */
5141                 if (clock.p2 == 7)
5142                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5143                 else
5144                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5145
5146                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5147                  * appropriately here, but we need to look more thoroughly into how
5148                  * panels behave in the two modes.
5149                  */
5150                 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5151                 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5152                         temp |= LVDS_HSYNC_POLARITY;
5153                 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5154                         temp |= LVDS_VSYNC_POLARITY;
5155                 I915_WRITE(PCH_LVDS, temp);
5156         }
5157
5158         if (is_dp && !is_cpu_edp) {
5159                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5160         } else {
5161                 /* For non-DP output, clear any trans DP clock recovery setting.*/
5162                 I915_WRITE(TRANSDATA_M1(pipe), 0);
5163                 I915_WRITE(TRANSDATA_N1(pipe), 0);
5164                 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5165                 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5166         }
5167
5168         if (intel_crtc->pch_pll) {
5169                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5170
5171                 /* Wait for the clocks to stabilize. */
5172                 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5173                 udelay(150);
5174
5175                 /* The pixel multiplier can only be updated once the
5176                  * DPLL is enabled and the clocks are stable.
5177                  *
5178                  * So write it again.
5179                  */
5180                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5181         }
5182
5183         intel_crtc->lowfreq_avail = false;
5184         if (intel_crtc->pch_pll) {
5185                 if (is_lvds && has_reduced_clock && i915_powersave) {
5186                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5187                         intel_crtc->lowfreq_avail = true;
5188                 } else {
5189                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5190                 }
5191         }
5192
5193         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5194
5195         ironlake_set_m_n(crtc, mode, adjusted_mode);
5196
5197         if (is_cpu_edp)
5198                 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5199
5200         ironlake_set_pipeconf(crtc, adjusted_mode, dither);
5201
5202         intel_wait_for_vblank(dev, pipe);
5203
5204         /* Set up the display plane register */
5205         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5206         POSTING_READ(DSPCNTR(plane));
5207
5208         ret = intel_pipe_set_base(crtc, x, y, fb);
5209
5210         intel_update_watermarks(dev);
5211
5212         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5213
5214         return ret;
5215 }
5216
5217 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5218                                  struct drm_display_mode *mode,
5219                                  struct drm_display_mode *adjusted_mode,
5220                                  int x, int y,
5221                                  struct drm_framebuffer *fb)
5222 {
5223         struct drm_device *dev = crtc->dev;
5224         struct drm_i915_private *dev_priv = dev->dev_private;
5225         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5226         int pipe = intel_crtc->pipe;
5227         int plane = intel_crtc->plane;
5228         int num_connectors = 0;
5229         intel_clock_t clock, reduced_clock;
5230         u32 dpll = 0, fp = 0, fp2 = 0;
5231         bool ok, has_reduced_clock = false;
5232         bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5233         struct intel_encoder *encoder;
5234         u32 temp;
5235         int ret;
5236         bool dither;
5237
5238         for_each_encoder_on_crtc(dev, crtc, encoder) {
5239                 switch (encoder->type) {
5240                 case INTEL_OUTPUT_LVDS:
5241                         is_lvds = true;
5242                         break;
5243                 case INTEL_OUTPUT_DISPLAYPORT:
5244                         is_dp = true;
5245                         break;
5246                 case INTEL_OUTPUT_EDP:
5247                         is_dp = true;
5248                         if (!intel_encoder_is_pch_edp(&encoder->base))
5249                                 is_cpu_edp = true;
5250                         break;
5251                 }
5252
5253                 num_connectors++;
5254         }
5255
5256         /* We are not sure yet this won't happen. */
5257         WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5258              INTEL_PCH_TYPE(dev));
5259
5260         WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5261              num_connectors, pipe_name(pipe));
5262
5263         WARN_ON(I915_READ(PIPECONF(pipe)) &
5264                 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5265
5266         WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5267
5268         if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5269                 return -EINVAL;
5270
5271         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5272                 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5273                                              &has_reduced_clock,
5274                                              &reduced_clock);
5275                 if (!ok) {
5276                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
5277                         return -EINVAL;
5278                 }
5279         }
5280
5281         /* Ensure that the cursor is valid for the new mode before changing... */
5282         intel_crtc_update_cursor(crtc, true);
5283
5284         /* determine panel color depth */
5285         dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp, mode);
5286         if (is_lvds && dev_priv->lvds_dither)
5287                 dither = true;
5288
5289         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5290         drm_mode_debug_printmodeline(mode);
5291
5292         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5293                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5294                 if (has_reduced_clock)
5295                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5296                               reduced_clock.m2;
5297
5298                 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock,
5299                                              fp);
5300
5301                 /* CPU eDP is the only output that doesn't need a PCH PLL of its
5302                  * own on pre-Haswell/LPT generation */
5303                 if (!is_cpu_edp) {
5304                         struct intel_pch_pll *pll;
5305
5306                         pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5307                         if (pll == NULL) {
5308                                 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5309                                                  pipe);
5310                                 return -EINVAL;
5311                         }
5312                 } else
5313                         intel_put_pch_pll(intel_crtc);
5314
5315                 /* The LVDS pin pair needs to be on before the DPLLs are
5316                  * enabled.  This is an exception to the general rule that
5317                  * mode_set doesn't turn things on.
5318                  */
5319                 if (is_lvds) {
5320                         temp = I915_READ(PCH_LVDS);
5321                         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5322                         if (HAS_PCH_CPT(dev)) {
5323                                 temp &= ~PORT_TRANS_SEL_MASK;
5324                                 temp |= PORT_TRANS_SEL_CPT(pipe);
5325                         } else {
5326                                 if (pipe == 1)
5327                                         temp |= LVDS_PIPEB_SELECT;
5328                                 else
5329                                         temp &= ~LVDS_PIPEB_SELECT;
5330                         }
5331
5332                         /* set the corresponsding LVDS_BORDER bit */
5333                         temp |= dev_priv->lvds_border_bits;
5334                         /* Set the B0-B3 data pairs corresponding to whether
5335                          * we're going to set the DPLLs for dual-channel mode or
5336                          * not.
5337                          */
5338                         if (clock.p2 == 7)
5339                                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5340                         else
5341                                 temp &= ~(LVDS_B0B3_POWER_UP |
5342                                           LVDS_CLKB_POWER_UP);
5343
5344                         /* It would be nice to set 24 vs 18-bit mode
5345                          * (LVDS_A3_POWER_UP) appropriately here, but we need to
5346                          * look more thoroughly into how panels behave in the
5347                          * two modes.
5348                          */
5349                         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5350                         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5351                                 temp |= LVDS_HSYNC_POLARITY;
5352                         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5353                                 temp |= LVDS_VSYNC_POLARITY;
5354                         I915_WRITE(PCH_LVDS, temp);
5355                 }
5356         }
5357
5358         if (is_dp && !is_cpu_edp) {
5359                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5360         } else {
5361                 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5362                         /* For non-DP output, clear any trans DP clock recovery
5363                          * setting.*/
5364                         I915_WRITE(TRANSDATA_M1(pipe), 0);
5365                         I915_WRITE(TRANSDATA_N1(pipe), 0);
5366                         I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5367                         I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5368                 }
5369         }
5370
5371         intel_crtc->lowfreq_avail = false;
5372         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5373                 if (intel_crtc->pch_pll) {
5374                         I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5375
5376                         /* Wait for the clocks to stabilize. */
5377                         POSTING_READ(intel_crtc->pch_pll->pll_reg);
5378                         udelay(150);
5379
5380                         /* The pixel multiplier can only be updated once the
5381                          * DPLL is enabled and the clocks are stable.
5382                          *
5383                          * So write it again.
5384                          */
5385                         I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5386                 }
5387
5388                 if (intel_crtc->pch_pll) {
5389                         if (is_lvds && has_reduced_clock && i915_powersave) {
5390                                 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5391                                 intel_crtc->lowfreq_avail = true;
5392                         } else {
5393                                 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5394                         }
5395                 }
5396         }
5397
5398         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5399
5400         if (!is_dp || is_cpu_edp)
5401                 ironlake_set_m_n(crtc, mode, adjusted_mode);
5402
5403         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5404                 if (is_cpu_edp)
5405                         ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5406
5407         haswell_set_pipeconf(crtc, adjusted_mode, dither);
5408
5409         /* Set up the display plane register */
5410         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5411         POSTING_READ(DSPCNTR(plane));
5412
5413         ret = intel_pipe_set_base(crtc, x, y, fb);
5414
5415         intel_update_watermarks(dev);
5416
5417         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5418
5419         return ret;
5420 }
5421
5422 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5423                                struct drm_display_mode *mode,
5424                                struct drm_display_mode *adjusted_mode,
5425                                int x, int y,
5426                                struct drm_framebuffer *fb)
5427 {
5428         struct drm_device *dev = crtc->dev;
5429         struct drm_i915_private *dev_priv = dev->dev_private;
5430         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5431         int pipe = intel_crtc->pipe;
5432         int ret;
5433
5434         drm_vblank_pre_modeset(dev, pipe);
5435
5436         ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5437                                               x, y, fb);
5438         drm_vblank_post_modeset(dev, pipe);
5439
5440         return ret;
5441 }
5442
5443 static bool intel_eld_uptodate(struct drm_connector *connector,
5444                                int reg_eldv, uint32_t bits_eldv,
5445                                int reg_elda, uint32_t bits_elda,
5446                                int reg_edid)
5447 {
5448         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5449         uint8_t *eld = connector->eld;
5450         uint32_t i;
5451
5452         i = I915_READ(reg_eldv);
5453         i &= bits_eldv;
5454
5455         if (!eld[0])
5456                 return !i;
5457
5458         if (!i)
5459                 return false;
5460
5461         i = I915_READ(reg_elda);
5462         i &= ~bits_elda;
5463         I915_WRITE(reg_elda, i);
5464
5465         for (i = 0; i < eld[2]; i++)
5466                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5467                         return false;
5468
5469         return true;
5470 }
5471
5472 static void g4x_write_eld(struct drm_connector *connector,
5473                           struct drm_crtc *crtc)
5474 {
5475         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5476         uint8_t *eld = connector->eld;
5477         uint32_t eldv;
5478         uint32_t len;
5479         uint32_t i;
5480
5481         i = I915_READ(G4X_AUD_VID_DID);
5482
5483         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5484                 eldv = G4X_ELDV_DEVCL_DEVBLC;
5485         else
5486                 eldv = G4X_ELDV_DEVCTG;
5487
5488         if (intel_eld_uptodate(connector,
5489                                G4X_AUD_CNTL_ST, eldv,
5490                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5491                                G4X_HDMIW_HDMIEDID))
5492                 return;
5493
5494         i = I915_READ(G4X_AUD_CNTL_ST);
5495         i &= ~(eldv | G4X_ELD_ADDR);
5496         len = (i >> 9) & 0x1f;          /* ELD buffer size */
5497         I915_WRITE(G4X_AUD_CNTL_ST, i);
5498
5499         if (!eld[0])
5500                 return;
5501
5502         len = min_t(uint8_t, eld[2], len);
5503         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5504         for (i = 0; i < len; i++)
5505                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5506
5507         i = I915_READ(G4X_AUD_CNTL_ST);
5508         i |= eldv;
5509         I915_WRITE(G4X_AUD_CNTL_ST, i);
5510 }
5511
5512 static void haswell_write_eld(struct drm_connector *connector,
5513                                      struct drm_crtc *crtc)
5514 {
5515         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5516         uint8_t *eld = connector->eld;
5517         struct drm_device *dev = crtc->dev;
5518         uint32_t eldv;
5519         uint32_t i;
5520         int len;
5521         int pipe = to_intel_crtc(crtc)->pipe;
5522         int tmp;
5523
5524         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5525         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5526         int aud_config = HSW_AUD_CFG(pipe);
5527         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5528
5529
5530         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5531
5532         /* Audio output enable */
5533         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5534         tmp = I915_READ(aud_cntrl_st2);
5535         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5536         I915_WRITE(aud_cntrl_st2, tmp);
5537
5538         /* Wait for 1 vertical blank */
5539         intel_wait_for_vblank(dev, pipe);
5540
5541         /* Set ELD valid state */
5542         tmp = I915_READ(aud_cntrl_st2);
5543         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5544         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5545         I915_WRITE(aud_cntrl_st2, tmp);
5546         tmp = I915_READ(aud_cntrl_st2);
5547         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5548
5549         /* Enable HDMI mode */
5550         tmp = I915_READ(aud_config);
5551         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5552         /* clear N_programing_enable and N_value_index */
5553         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5554         I915_WRITE(aud_config, tmp);
5555
5556         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5557
5558         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5559
5560         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5561                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5562                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
5563                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5564         } else
5565                 I915_WRITE(aud_config, 0);
5566
5567         if (intel_eld_uptodate(connector,
5568                                aud_cntrl_st2, eldv,
5569                                aud_cntl_st, IBX_ELD_ADDRESS,
5570                                hdmiw_hdmiedid))
5571                 return;
5572
5573         i = I915_READ(aud_cntrl_st2);
5574         i &= ~eldv;
5575         I915_WRITE(aud_cntrl_st2, i);
5576
5577         if (!eld[0])
5578                 return;
5579
5580         i = I915_READ(aud_cntl_st);
5581         i &= ~IBX_ELD_ADDRESS;
5582         I915_WRITE(aud_cntl_st, i);
5583         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
5584         DRM_DEBUG_DRIVER("port num:%d\n", i);
5585
5586         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
5587         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5588         for (i = 0; i < len; i++)
5589                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5590
5591         i = I915_READ(aud_cntrl_st2);
5592         i |= eldv;
5593         I915_WRITE(aud_cntrl_st2, i);
5594
5595 }
5596
5597 static void ironlake_write_eld(struct drm_connector *connector,
5598                                      struct drm_crtc *crtc)
5599 {
5600         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5601         uint8_t *eld = connector->eld;
5602         uint32_t eldv;
5603         uint32_t i;
5604         int len;
5605         int hdmiw_hdmiedid;
5606         int aud_config;
5607         int aud_cntl_st;
5608         int aud_cntrl_st2;
5609         int pipe = to_intel_crtc(crtc)->pipe;
5610
5611         if (HAS_PCH_IBX(connector->dev)) {
5612                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
5613                 aud_config = IBX_AUD_CFG(pipe);
5614                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
5615                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
5616         } else {
5617                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
5618                 aud_config = CPT_AUD_CFG(pipe);
5619                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
5620                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
5621         }
5622
5623         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5624
5625         i = I915_READ(aud_cntl_st);
5626         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
5627         if (!i) {
5628                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5629                 /* operate blindly on all ports */
5630                 eldv = IBX_ELD_VALIDB;
5631                 eldv |= IBX_ELD_VALIDB << 4;
5632                 eldv |= IBX_ELD_VALIDB << 8;
5633         } else {
5634                 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
5635                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
5636         }
5637
5638         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5639                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5640                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
5641                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5642         } else
5643                 I915_WRITE(aud_config, 0);
5644
5645         if (intel_eld_uptodate(connector,
5646                                aud_cntrl_st2, eldv,
5647                                aud_cntl_st, IBX_ELD_ADDRESS,
5648                                hdmiw_hdmiedid))
5649                 return;
5650
5651         i = I915_READ(aud_cntrl_st2);
5652         i &= ~eldv;
5653         I915_WRITE(aud_cntrl_st2, i);
5654
5655         if (!eld[0])
5656                 return;
5657
5658         i = I915_READ(aud_cntl_st);
5659         i &= ~IBX_ELD_ADDRESS;
5660         I915_WRITE(aud_cntl_st, i);
5661
5662         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
5663         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5664         for (i = 0; i < len; i++)
5665                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5666
5667         i = I915_READ(aud_cntrl_st2);
5668         i |= eldv;
5669         I915_WRITE(aud_cntrl_st2, i);
5670 }
5671
5672 void intel_write_eld(struct drm_encoder *encoder,
5673                      struct drm_display_mode *mode)
5674 {
5675         struct drm_crtc *crtc = encoder->crtc;
5676         struct drm_connector *connector;
5677         struct drm_device *dev = encoder->dev;
5678         struct drm_i915_private *dev_priv = dev->dev_private;
5679
5680         connector = drm_select_eld(encoder, mode);
5681         if (!connector)
5682                 return;
5683
5684         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5685                          connector->base.id,
5686                          drm_get_connector_name(connector),
5687                          connector->encoder->base.id,
5688                          drm_get_encoder_name(connector->encoder));
5689
5690         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
5691
5692         if (dev_priv->display.write_eld)
5693                 dev_priv->display.write_eld(connector, crtc);
5694 }
5695
5696 /** Loads the palette/gamma unit for the CRTC with the prepared values */
5697 void intel_crtc_load_lut(struct drm_crtc *crtc)
5698 {
5699         struct drm_device *dev = crtc->dev;
5700         struct drm_i915_private *dev_priv = dev->dev_private;
5701         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5702         int palreg = PALETTE(intel_crtc->pipe);
5703         int i;
5704
5705         /* The clocks have to be on to load the palette. */
5706         if (!crtc->enabled || !intel_crtc->active)
5707                 return;
5708
5709         /* use legacy palette for Ironlake */
5710         if (HAS_PCH_SPLIT(dev))
5711                 palreg = LGC_PALETTE(intel_crtc->pipe);
5712
5713         for (i = 0; i < 256; i++) {
5714                 I915_WRITE(palreg + 4 * i,
5715                            (intel_crtc->lut_r[i] << 16) |
5716                            (intel_crtc->lut_g[i] << 8) |
5717                            intel_crtc->lut_b[i]);
5718         }
5719 }
5720
5721 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5722 {
5723         struct drm_device *dev = crtc->dev;
5724         struct drm_i915_private *dev_priv = dev->dev_private;
5725         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5726         bool visible = base != 0;
5727         u32 cntl;
5728
5729         if (intel_crtc->cursor_visible == visible)
5730                 return;
5731
5732         cntl = I915_READ(_CURACNTR);
5733         if (visible) {
5734                 /* On these chipsets we can only modify the base whilst
5735                  * the cursor is disabled.
5736                  */
5737                 I915_WRITE(_CURABASE, base);
5738
5739                 cntl &= ~(CURSOR_FORMAT_MASK);
5740                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5741                 cntl |= CURSOR_ENABLE |
5742                         CURSOR_GAMMA_ENABLE |
5743                         CURSOR_FORMAT_ARGB;
5744         } else
5745                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
5746         I915_WRITE(_CURACNTR, cntl);
5747
5748         intel_crtc->cursor_visible = visible;
5749 }
5750
5751 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5752 {
5753         struct drm_device *dev = crtc->dev;
5754         struct drm_i915_private *dev_priv = dev->dev_private;
5755         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5756         int pipe = intel_crtc->pipe;
5757         bool visible = base != 0;
5758
5759         if (intel_crtc->cursor_visible != visible) {
5760                 uint32_t cntl = I915_READ(CURCNTR(pipe));
5761                 if (base) {
5762                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5763                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5764                         cntl |= pipe << 28; /* Connect to correct pipe */
5765                 } else {
5766                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5767                         cntl |= CURSOR_MODE_DISABLE;
5768                 }
5769                 I915_WRITE(CURCNTR(pipe), cntl);
5770
5771                 intel_crtc->cursor_visible = visible;
5772         }
5773         /* and commit changes on next vblank */
5774         I915_WRITE(CURBASE(pipe), base);
5775 }
5776
5777 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
5778 {
5779         struct drm_device *dev = crtc->dev;
5780         struct drm_i915_private *dev_priv = dev->dev_private;
5781         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5782         int pipe = intel_crtc->pipe;
5783         bool visible = base != 0;
5784
5785         if (intel_crtc->cursor_visible != visible) {
5786                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
5787                 if (base) {
5788                         cntl &= ~CURSOR_MODE;
5789                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5790                 } else {
5791                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5792                         cntl |= CURSOR_MODE_DISABLE;
5793                 }
5794                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
5795
5796                 intel_crtc->cursor_visible = visible;
5797         }
5798         /* and commit changes on next vblank */
5799         I915_WRITE(CURBASE_IVB(pipe), base);
5800 }
5801
5802 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
5803 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5804                                      bool on)
5805 {
5806         struct drm_device *dev = crtc->dev;
5807         struct drm_i915_private *dev_priv = dev->dev_private;
5808         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5809         int pipe = intel_crtc->pipe;
5810         int x = intel_crtc->cursor_x;
5811         int y = intel_crtc->cursor_y;
5812         u32 base, pos;
5813         bool visible;
5814
5815         pos = 0;
5816
5817         if (on && crtc->enabled && crtc->fb) {
5818                 base = intel_crtc->cursor_addr;
5819                 if (x > (int) crtc->fb->width)
5820                         base = 0;
5821
5822                 if (y > (int) crtc->fb->height)
5823                         base = 0;
5824         } else
5825                 base = 0;
5826
5827         if (x < 0) {
5828                 if (x + intel_crtc->cursor_width < 0)
5829                         base = 0;
5830
5831                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5832                 x = -x;
5833         }
5834         pos |= x << CURSOR_X_SHIFT;
5835
5836         if (y < 0) {
5837                 if (y + intel_crtc->cursor_height < 0)
5838                         base = 0;
5839
5840                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5841                 y = -y;
5842         }
5843         pos |= y << CURSOR_Y_SHIFT;
5844
5845         visible = base != 0;
5846         if (!visible && !intel_crtc->cursor_visible)
5847                 return;
5848
5849         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
5850                 I915_WRITE(CURPOS_IVB(pipe), pos);
5851                 ivb_update_cursor(crtc, base);
5852         } else {
5853                 I915_WRITE(CURPOS(pipe), pos);
5854                 if (IS_845G(dev) || IS_I865G(dev))
5855                         i845_update_cursor(crtc, base);
5856                 else
5857                         i9xx_update_cursor(crtc, base);
5858         }
5859 }
5860
5861 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
5862                                  struct drm_file *file,
5863                                  uint32_t handle,
5864                                  uint32_t width, uint32_t height)
5865 {
5866         struct drm_device *dev = crtc->dev;
5867         struct drm_i915_private *dev_priv = dev->dev_private;
5868         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5869         struct drm_i915_gem_object *obj;
5870         uint32_t addr;
5871         int ret;
5872
5873         /* if we want to turn off the cursor ignore width and height */
5874         if (!handle) {
5875                 DRM_DEBUG_KMS("cursor off\n");
5876                 addr = 0;
5877                 obj = NULL;
5878                 mutex_lock(&dev->struct_mutex);
5879                 goto finish;
5880         }
5881
5882         /* Currently we only support 64x64 cursors */
5883         if (width != 64 || height != 64) {
5884                 DRM_ERROR("we currently only support 64x64 cursors\n");
5885                 return -EINVAL;
5886         }
5887
5888         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
5889         if (&obj->base == NULL)
5890                 return -ENOENT;
5891
5892         if (obj->base.size < width * height * 4) {
5893                 DRM_ERROR("buffer is to small\n");
5894                 ret = -ENOMEM;
5895                 goto fail;
5896         }
5897
5898         /* we only need to pin inside GTT if cursor is non-phy */
5899         mutex_lock(&dev->struct_mutex);
5900         if (!dev_priv->info->cursor_needs_physical) {
5901                 if (obj->tiling_mode) {
5902                         DRM_ERROR("cursor cannot be tiled\n");
5903                         ret = -EINVAL;
5904                         goto fail_locked;
5905                 }
5906
5907                 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
5908                 if (ret) {
5909                         DRM_ERROR("failed to move cursor bo into the GTT\n");
5910                         goto fail_locked;
5911                 }
5912
5913                 ret = i915_gem_object_put_fence(obj);
5914                 if (ret) {
5915                         DRM_ERROR("failed to release fence for cursor");
5916                         goto fail_unpin;
5917                 }
5918
5919                 addr = obj->gtt_offset;
5920         } else {
5921                 int align = IS_I830(dev) ? 16 * 1024 : 256;
5922                 ret = i915_gem_attach_phys_object(dev, obj,
5923                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5924                                                   align);
5925                 if (ret) {
5926                         DRM_ERROR("failed to attach phys object\n");
5927                         goto fail_locked;
5928                 }
5929                 addr = obj->phys_obj->handle->busaddr;
5930         }
5931
5932         if (IS_GEN2(dev))
5933                 I915_WRITE(CURSIZE, (height << 12) | width);
5934
5935  finish:
5936         if (intel_crtc->cursor_bo) {
5937                 if (dev_priv->info->cursor_needs_physical) {
5938                         if (intel_crtc->cursor_bo != obj)
5939                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5940                 } else
5941                         i915_gem_object_unpin(intel_crtc->cursor_bo);
5942                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
5943         }
5944
5945         mutex_unlock(&dev->struct_mutex);
5946
5947         intel_crtc->cursor_addr = addr;
5948         intel_crtc->cursor_bo = obj;
5949         intel_crtc->cursor_width = width;
5950         intel_crtc->cursor_height = height;
5951
5952         intel_crtc_update_cursor(crtc, true);
5953
5954         return 0;
5955 fail_unpin:
5956         i915_gem_object_unpin(obj);
5957 fail_locked:
5958         mutex_unlock(&dev->struct_mutex);
5959 fail:
5960         drm_gem_object_unreference_unlocked(&obj->base);
5961         return ret;
5962 }
5963
5964 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5965 {
5966         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5967
5968         intel_crtc->cursor_x = x;
5969         intel_crtc->cursor_y = y;
5970
5971         intel_crtc_update_cursor(crtc, true);
5972
5973         return 0;
5974 }
5975
5976 /** Sets the color ramps on behalf of RandR */
5977 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5978                                  u16 blue, int regno)
5979 {
5980         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5981
5982         intel_crtc->lut_r[regno] = red >> 8;
5983         intel_crtc->lut_g[regno] = green >> 8;
5984         intel_crtc->lut_b[regno] = blue >> 8;
5985 }
5986
5987 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5988                              u16 *blue, int regno)
5989 {
5990         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5991
5992         *red = intel_crtc->lut_r[regno] << 8;
5993         *green = intel_crtc->lut_g[regno] << 8;
5994         *blue = intel_crtc->lut_b[regno] << 8;
5995 }
5996
5997 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
5998                                  u16 *blue, uint32_t start, uint32_t size)
5999 {
6000         int end = (start + size > 256) ? 256 : start + size, i;
6001         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6002
6003         for (i = start; i < end; i++) {
6004                 intel_crtc->lut_r[i] = red[i] >> 8;
6005                 intel_crtc->lut_g[i] = green[i] >> 8;
6006                 intel_crtc->lut_b[i] = blue[i] >> 8;
6007         }
6008
6009         intel_crtc_load_lut(crtc);
6010 }
6011
6012 /**
6013  * Get a pipe with a simple mode set on it for doing load-based monitor
6014  * detection.
6015  *
6016  * It will be up to the load-detect code to adjust the pipe as appropriate for
6017  * its requirements.  The pipe will be connected to no other encoders.
6018  *
6019  * Currently this code will only succeed if there is a pipe with no encoders
6020  * configured for it.  In the future, it could choose to temporarily disable
6021  * some outputs to free up a pipe for its use.
6022  *
6023  * \return crtc, or NULL if no pipes are available.
6024  */
6025
6026 /* VESA 640x480x72Hz mode to set on the pipe */
6027 static struct drm_display_mode load_detect_mode = {
6028         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6029                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6030 };
6031
6032 static struct drm_framebuffer *
6033 intel_framebuffer_create(struct drm_device *dev,
6034                          struct drm_mode_fb_cmd2 *mode_cmd,
6035                          struct drm_i915_gem_object *obj)
6036 {
6037         struct intel_framebuffer *intel_fb;
6038         int ret;
6039
6040         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6041         if (!intel_fb) {
6042                 drm_gem_object_unreference_unlocked(&obj->base);
6043                 return ERR_PTR(-ENOMEM);
6044         }
6045
6046         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6047         if (ret) {
6048                 drm_gem_object_unreference_unlocked(&obj->base);
6049                 kfree(intel_fb);
6050                 return ERR_PTR(ret);
6051         }
6052
6053         return &intel_fb->base;
6054 }
6055
6056 static u32
6057 intel_framebuffer_pitch_for_width(int width, int bpp)
6058 {
6059         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6060         return ALIGN(pitch, 64);
6061 }
6062
6063 static u32
6064 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6065 {
6066         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6067         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6068 }
6069
6070 static struct drm_framebuffer *
6071 intel_framebuffer_create_for_mode(struct drm_device *dev,
6072                                   struct drm_display_mode *mode,
6073                                   int depth, int bpp)
6074 {
6075         struct drm_i915_gem_object *obj;
6076         struct drm_mode_fb_cmd2 mode_cmd;
6077
6078         obj = i915_gem_alloc_object(dev,
6079                                     intel_framebuffer_size_for_mode(mode, bpp));
6080         if (obj == NULL)
6081                 return ERR_PTR(-ENOMEM);
6082
6083         mode_cmd.width = mode->hdisplay;
6084         mode_cmd.height = mode->vdisplay;
6085         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6086                                                                 bpp);
6087         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6088
6089         return intel_framebuffer_create(dev, &mode_cmd, obj);
6090 }
6091
6092 static struct drm_framebuffer *
6093 mode_fits_in_fbdev(struct drm_device *dev,
6094                    struct drm_display_mode *mode)
6095 {
6096         struct drm_i915_private *dev_priv = dev->dev_private;
6097         struct drm_i915_gem_object *obj;
6098         struct drm_framebuffer *fb;
6099
6100         if (dev_priv->fbdev == NULL)
6101                 return NULL;
6102
6103         obj = dev_priv->fbdev->ifb.obj;
6104         if (obj == NULL)
6105                 return NULL;
6106
6107         fb = &dev_priv->fbdev->ifb.base;
6108         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6109                                                                fb->bits_per_pixel))
6110                 return NULL;
6111
6112         if (obj->base.size < mode->vdisplay * fb->pitches[0])
6113                 return NULL;
6114
6115         return fb;
6116 }
6117
6118 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6119                                 struct drm_display_mode *mode,
6120                                 struct intel_load_detect_pipe *old)
6121 {
6122         struct intel_crtc *intel_crtc;
6123         struct intel_encoder *intel_encoder =
6124                 intel_attached_encoder(connector);
6125         struct drm_crtc *possible_crtc;
6126         struct drm_encoder *encoder = &intel_encoder->base;
6127         struct drm_crtc *crtc = NULL;
6128         struct drm_device *dev = encoder->dev;
6129         struct drm_framebuffer *fb;
6130         int i = -1;
6131
6132         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6133                       connector->base.id, drm_get_connector_name(connector),
6134                       encoder->base.id, drm_get_encoder_name(encoder));
6135
6136         /*
6137          * Algorithm gets a little messy:
6138          *
6139          *   - if the connector already has an assigned crtc, use it (but make
6140          *     sure it's on first)
6141          *
6142          *   - try to find the first unused crtc that can drive this connector,
6143          *     and use that if we find one
6144          */
6145
6146         /* See if we already have a CRTC for this connector */
6147         if (encoder->crtc) {
6148                 crtc = encoder->crtc;
6149
6150                 old->dpms_mode = connector->dpms;
6151                 old->load_detect_temp = false;
6152
6153                 /* Make sure the crtc and connector are running */
6154                 if (connector->dpms != DRM_MODE_DPMS_ON)
6155                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6156
6157                 return true;
6158         }
6159
6160         /* Find an unused one (if possible) */
6161         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6162                 i++;
6163                 if (!(encoder->possible_crtcs & (1 << i)))
6164                         continue;
6165                 if (!possible_crtc->enabled) {
6166                         crtc = possible_crtc;
6167                         break;
6168                 }
6169         }
6170
6171         /*
6172          * If we didn't find an unused CRTC, don't use any.
6173          */
6174         if (!crtc) {
6175                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6176                 return false;
6177         }
6178
6179         intel_encoder->new_crtc = to_intel_crtc(crtc);
6180         to_intel_connector(connector)->new_encoder = intel_encoder;
6181
6182         intel_crtc = to_intel_crtc(crtc);
6183         old->dpms_mode = connector->dpms;
6184         old->load_detect_temp = true;
6185         old->release_fb = NULL;
6186
6187         if (!mode)
6188                 mode = &load_detect_mode;
6189
6190         /* We need a framebuffer large enough to accommodate all accesses
6191          * that the plane may generate whilst we perform load detection.
6192          * We can not rely on the fbcon either being present (we get called
6193          * during its initialisation to detect all boot displays, or it may
6194          * not even exist) or that it is large enough to satisfy the
6195          * requested mode.
6196          */
6197         fb = mode_fits_in_fbdev(dev, mode);
6198         if (fb == NULL) {
6199                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6200                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6201                 old->release_fb = fb;
6202         } else
6203                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6204         if (IS_ERR(fb)) {
6205                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6206                 goto fail;
6207         }
6208
6209         if (!intel_set_mode(crtc, mode, 0, 0, fb)) {
6210                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6211                 if (old->release_fb)
6212                         old->release_fb->funcs->destroy(old->release_fb);
6213                 goto fail;
6214         }
6215
6216         /* let the connector get through one full cycle before testing */
6217         intel_wait_for_vblank(dev, intel_crtc->pipe);
6218
6219         return true;
6220 fail:
6221         connector->encoder = NULL;
6222         encoder->crtc = NULL;
6223         return false;
6224 }
6225
6226 void intel_release_load_detect_pipe(struct drm_connector *connector,
6227                                     struct intel_load_detect_pipe *old)
6228 {
6229         struct intel_encoder *intel_encoder =
6230                 intel_attached_encoder(connector);
6231         struct drm_encoder *encoder = &intel_encoder->base;
6232
6233         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6234                       connector->base.id, drm_get_connector_name(connector),
6235                       encoder->base.id, drm_get_encoder_name(encoder));
6236
6237         if (old->load_detect_temp) {
6238                 struct drm_crtc *crtc = encoder->crtc;
6239
6240                 to_intel_connector(connector)->new_encoder = NULL;
6241                 intel_encoder->new_crtc = NULL;
6242                 intel_set_mode(crtc, NULL, 0, 0, NULL);
6243
6244                 if (old->release_fb)
6245                         old->release_fb->funcs->destroy(old->release_fb);
6246
6247                 return;
6248         }
6249
6250         /* Switch crtc and encoder back off if necessary */
6251         if (old->dpms_mode != DRM_MODE_DPMS_ON)
6252                 connector->funcs->dpms(connector, old->dpms_mode);
6253 }
6254
6255 /* Returns the clock of the currently programmed mode of the given pipe. */
6256 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6257 {
6258         struct drm_i915_private *dev_priv = dev->dev_private;
6259         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6260         int pipe = intel_crtc->pipe;
6261         u32 dpll = I915_READ(DPLL(pipe));
6262         u32 fp;
6263         intel_clock_t clock;
6264
6265         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6266                 fp = I915_READ(FP0(pipe));
6267         else
6268                 fp = I915_READ(FP1(pipe));
6269
6270         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6271         if (IS_PINEVIEW(dev)) {
6272                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6273                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6274         } else {
6275                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6276                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6277         }
6278
6279         if (!IS_GEN2(dev)) {
6280                 if (IS_PINEVIEW(dev))
6281                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6282                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6283                 else
6284                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6285                                DPLL_FPA01_P1_POST_DIV_SHIFT);
6286
6287                 switch (dpll & DPLL_MODE_MASK) {
6288                 case DPLLB_MODE_DAC_SERIAL:
6289                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6290                                 5 : 10;
6291                         break;
6292                 case DPLLB_MODE_LVDS:
6293                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6294                                 7 : 14;
6295                         break;
6296                 default:
6297                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6298                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
6299                         return 0;
6300                 }
6301
6302                 /* XXX: Handle the 100Mhz refclk */
6303                 intel_clock(dev, 96000, &clock);
6304         } else {
6305                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6306
6307                 if (is_lvds) {
6308                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6309                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
6310                         clock.p2 = 14;
6311
6312                         if ((dpll & PLL_REF_INPUT_MASK) ==
6313                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6314                                 /* XXX: might not be 66MHz */
6315                                 intel_clock(dev, 66000, &clock);
6316                         } else
6317                                 intel_clock(dev, 48000, &clock);
6318                 } else {
6319                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
6320                                 clock.p1 = 2;
6321                         else {
6322                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6323                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6324                         }
6325                         if (dpll & PLL_P2_DIVIDE_BY_4)
6326                                 clock.p2 = 4;
6327                         else
6328                                 clock.p2 = 2;
6329
6330                         intel_clock(dev, 48000, &clock);
6331                 }
6332         }
6333
6334         /* XXX: It would be nice to validate the clocks, but we can't reuse
6335          * i830PllIsValid() because it relies on the xf86_config connector
6336          * configuration being accurate, which it isn't necessarily.
6337          */
6338
6339         return clock.dot;
6340 }
6341
6342 /** Returns the currently programmed mode of the given pipe. */
6343 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6344                                              struct drm_crtc *crtc)
6345 {
6346         struct drm_i915_private *dev_priv = dev->dev_private;
6347         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6348         int pipe = intel_crtc->pipe;
6349         struct drm_display_mode *mode;
6350         int htot = I915_READ(HTOTAL(pipe));
6351         int hsync = I915_READ(HSYNC(pipe));
6352         int vtot = I915_READ(VTOTAL(pipe));
6353         int vsync = I915_READ(VSYNC(pipe));
6354
6355         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6356         if (!mode)
6357                 return NULL;
6358
6359         mode->clock = intel_crtc_clock_get(dev, crtc);
6360         mode->hdisplay = (htot & 0xffff) + 1;
6361         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6362         mode->hsync_start = (hsync & 0xffff) + 1;
6363         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6364         mode->vdisplay = (vtot & 0xffff) + 1;
6365         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6366         mode->vsync_start = (vsync & 0xffff) + 1;
6367         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6368
6369         drm_mode_set_name(mode);
6370
6371         return mode;
6372 }
6373
6374 static void intel_increase_pllclock(struct drm_crtc *crtc)
6375 {
6376         struct drm_device *dev = crtc->dev;
6377         drm_i915_private_t *dev_priv = dev->dev_private;
6378         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6379         int pipe = intel_crtc->pipe;
6380         int dpll_reg = DPLL(pipe);
6381         int dpll;
6382
6383         if (HAS_PCH_SPLIT(dev))
6384                 return;
6385
6386         if (!dev_priv->lvds_downclock_avail)
6387                 return;
6388
6389         dpll = I915_READ(dpll_reg);
6390         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6391                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6392
6393                 assert_panel_unlocked(dev_priv, pipe);
6394
6395                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6396                 I915_WRITE(dpll_reg, dpll);
6397                 intel_wait_for_vblank(dev, pipe);
6398
6399                 dpll = I915_READ(dpll_reg);
6400                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6401                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6402         }
6403 }
6404
6405 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6406 {
6407         struct drm_device *dev = crtc->dev;
6408         drm_i915_private_t *dev_priv = dev->dev_private;
6409         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6410
6411         if (HAS_PCH_SPLIT(dev))
6412                 return;
6413
6414         if (!dev_priv->lvds_downclock_avail)
6415                 return;
6416
6417         /*
6418          * Since this is called by a timer, we should never get here in
6419          * the manual case.
6420          */
6421         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6422                 int pipe = intel_crtc->pipe;
6423                 int dpll_reg = DPLL(pipe);
6424                 int dpll;
6425
6426                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6427
6428                 assert_panel_unlocked(dev_priv, pipe);
6429
6430                 dpll = I915_READ(dpll_reg);
6431                 dpll |= DISPLAY_RATE_SELECT_FPA1;
6432                 I915_WRITE(dpll_reg, dpll);
6433                 intel_wait_for_vblank(dev, pipe);
6434                 dpll = I915_READ(dpll_reg);
6435                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6436                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6437         }
6438
6439 }
6440
6441 void intel_mark_busy(struct drm_device *dev)
6442 {
6443         i915_update_gfx_val(dev->dev_private);
6444 }
6445
6446 void intel_mark_idle(struct drm_device *dev)
6447 {
6448 }
6449
6450 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6451 {
6452         struct drm_device *dev = obj->base.dev;
6453         struct drm_crtc *crtc;
6454
6455         if (!i915_powersave)
6456                 return;
6457
6458         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6459                 if (!crtc->fb)
6460                         continue;
6461
6462                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6463                         intel_increase_pllclock(crtc);
6464         }
6465 }
6466
6467 void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
6468 {
6469         struct drm_device *dev = obj->base.dev;
6470         struct drm_crtc *crtc;
6471
6472         if (!i915_powersave)
6473                 return;
6474
6475         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6476                 if (!crtc->fb)
6477                         continue;
6478
6479                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6480                         intel_decrease_pllclock(crtc);
6481         }
6482 }
6483
6484 static void intel_crtc_destroy(struct drm_crtc *crtc)
6485 {
6486         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6487         struct drm_device *dev = crtc->dev;
6488         struct intel_unpin_work *work;
6489         unsigned long flags;
6490
6491         spin_lock_irqsave(&dev->event_lock, flags);
6492         work = intel_crtc->unpin_work;
6493         intel_crtc->unpin_work = NULL;
6494         spin_unlock_irqrestore(&dev->event_lock, flags);
6495
6496         if (work) {
6497                 cancel_work_sync(&work->work);
6498                 kfree(work);
6499         }
6500
6501         drm_crtc_cleanup(crtc);
6502
6503         kfree(intel_crtc);
6504 }
6505
6506 static void intel_unpin_work_fn(struct work_struct *__work)
6507 {
6508         struct intel_unpin_work *work =
6509                 container_of(__work, struct intel_unpin_work, work);
6510
6511         mutex_lock(&work->dev->struct_mutex);
6512         intel_unpin_fb_obj(work->old_fb_obj);
6513         drm_gem_object_unreference(&work->pending_flip_obj->base);
6514         drm_gem_object_unreference(&work->old_fb_obj->base);
6515
6516         intel_update_fbc(work->dev);
6517         mutex_unlock(&work->dev->struct_mutex);
6518         kfree(work);
6519 }
6520
6521 static void do_intel_finish_page_flip(struct drm_device *dev,
6522                                       struct drm_crtc *crtc)
6523 {
6524         drm_i915_private_t *dev_priv = dev->dev_private;
6525         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6526         struct intel_unpin_work *work;
6527         struct drm_i915_gem_object *obj;
6528         struct drm_pending_vblank_event *e;
6529         struct timeval tvbl;
6530         unsigned long flags;
6531
6532         /* Ignore early vblank irqs */
6533         if (intel_crtc == NULL)
6534                 return;
6535
6536         spin_lock_irqsave(&dev->event_lock, flags);
6537         work = intel_crtc->unpin_work;
6538         if (work == NULL || !work->pending) {
6539                 spin_unlock_irqrestore(&dev->event_lock, flags);
6540                 return;
6541         }
6542
6543         intel_crtc->unpin_work = NULL;
6544
6545         if (work->event) {
6546                 e = work->event;
6547                 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
6548
6549                 e->event.tv_sec = tvbl.tv_sec;
6550                 e->event.tv_usec = tvbl.tv_usec;
6551
6552                 list_add_tail(&e->base.link,
6553                               &e->base.file_priv->event_list);
6554                 wake_up_interruptible(&e->base.file_priv->event_wait);
6555         }
6556
6557         drm_vblank_put(dev, intel_crtc->pipe);
6558
6559         spin_unlock_irqrestore(&dev->event_lock, flags);
6560
6561         obj = work->old_fb_obj;
6562
6563         atomic_clear_mask(1 << intel_crtc->plane,
6564                           &obj->pending_flip.counter);
6565
6566         wake_up(&dev_priv->pending_flip_queue);
6567         schedule_work(&work->work);
6568
6569         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6570 }
6571
6572 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6573 {
6574         drm_i915_private_t *dev_priv = dev->dev_private;
6575         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6576
6577         do_intel_finish_page_flip(dev, crtc);
6578 }
6579
6580 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6581 {
6582         drm_i915_private_t *dev_priv = dev->dev_private;
6583         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6584
6585         do_intel_finish_page_flip(dev, crtc);
6586 }
6587
6588 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6589 {
6590         drm_i915_private_t *dev_priv = dev->dev_private;
6591         struct intel_crtc *intel_crtc =
6592                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6593         unsigned long flags;
6594
6595         spin_lock_irqsave(&dev->event_lock, flags);
6596         if (intel_crtc->unpin_work) {
6597                 if ((++intel_crtc->unpin_work->pending) > 1)
6598                         DRM_ERROR("Prepared flip multiple times\n");
6599         } else {
6600                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6601         }
6602         spin_unlock_irqrestore(&dev->event_lock, flags);
6603 }
6604
6605 static int intel_gen2_queue_flip(struct drm_device *dev,
6606                                  struct drm_crtc *crtc,
6607                                  struct drm_framebuffer *fb,
6608                                  struct drm_i915_gem_object *obj)
6609 {
6610         struct drm_i915_private *dev_priv = dev->dev_private;
6611         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6612         u32 flip_mask;
6613         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6614         int ret;
6615
6616         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6617         if (ret)
6618                 goto err;
6619
6620         ret = intel_ring_begin(ring, 6);
6621         if (ret)
6622                 goto err_unpin;
6623
6624         /* Can't queue multiple flips, so wait for the previous
6625          * one to finish before executing the next.
6626          */
6627         if (intel_crtc->plane)
6628                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6629         else
6630                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6631         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6632         intel_ring_emit(ring, MI_NOOP);
6633         intel_ring_emit(ring, MI_DISPLAY_FLIP |
6634                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6635         intel_ring_emit(ring, fb->pitches[0]);
6636         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6637         intel_ring_emit(ring, 0); /* aux display base address, unused */
6638         intel_ring_advance(ring);
6639         return 0;
6640
6641 err_unpin:
6642         intel_unpin_fb_obj(obj);
6643 err:
6644         return ret;
6645 }
6646
6647 static int intel_gen3_queue_flip(struct drm_device *dev,
6648                                  struct drm_crtc *crtc,
6649                                  struct drm_framebuffer *fb,
6650                                  struct drm_i915_gem_object *obj)
6651 {
6652         struct drm_i915_private *dev_priv = dev->dev_private;
6653         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6654         u32 flip_mask;
6655         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6656         int ret;
6657
6658         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6659         if (ret)
6660                 goto err;
6661
6662         ret = intel_ring_begin(ring, 6);
6663         if (ret)
6664                 goto err_unpin;
6665
6666         if (intel_crtc->plane)
6667                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6668         else
6669                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6670         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6671         intel_ring_emit(ring, MI_NOOP);
6672         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
6673                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6674         intel_ring_emit(ring, fb->pitches[0]);
6675         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6676         intel_ring_emit(ring, MI_NOOP);
6677
6678         intel_ring_advance(ring);
6679         return 0;
6680
6681 err_unpin:
6682         intel_unpin_fb_obj(obj);
6683 err:
6684         return ret;
6685 }
6686
6687 static int intel_gen4_queue_flip(struct drm_device *dev,
6688                                  struct drm_crtc *crtc,
6689                                  struct drm_framebuffer *fb,
6690                                  struct drm_i915_gem_object *obj)
6691 {
6692         struct drm_i915_private *dev_priv = dev->dev_private;
6693         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6694         uint32_t pf, pipesrc;
6695         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6696         int ret;
6697
6698         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6699         if (ret)
6700                 goto err;
6701
6702         ret = intel_ring_begin(ring, 4);
6703         if (ret)
6704                 goto err_unpin;
6705
6706         /* i965+ uses the linear or tiled offsets from the
6707          * Display Registers (which do not change across a page-flip)
6708          * so we need only reprogram the base address.
6709          */
6710         intel_ring_emit(ring, MI_DISPLAY_FLIP |
6711                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6712         intel_ring_emit(ring, fb->pitches[0]);
6713         intel_ring_emit(ring,
6714                         (obj->gtt_offset + intel_crtc->dspaddr_offset) |
6715                         obj->tiling_mode);
6716
6717         /* XXX Enabling the panel-fitter across page-flip is so far
6718          * untested on non-native modes, so ignore it for now.
6719          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6720          */
6721         pf = 0;
6722         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6723         intel_ring_emit(ring, pf | pipesrc);
6724         intel_ring_advance(ring);
6725         return 0;
6726
6727 err_unpin:
6728         intel_unpin_fb_obj(obj);
6729 err:
6730         return ret;
6731 }
6732
6733 static int intel_gen6_queue_flip(struct drm_device *dev,
6734                                  struct drm_crtc *crtc,
6735                                  struct drm_framebuffer *fb,
6736                                  struct drm_i915_gem_object *obj)
6737 {
6738         struct drm_i915_private *dev_priv = dev->dev_private;
6739         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6740         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6741         uint32_t pf, pipesrc;
6742         int ret;
6743
6744         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6745         if (ret)
6746                 goto err;
6747
6748         ret = intel_ring_begin(ring, 4);
6749         if (ret)
6750                 goto err_unpin;
6751
6752         intel_ring_emit(ring, MI_DISPLAY_FLIP |
6753                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6754         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
6755         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6756
6757         /* Contrary to the suggestions in the documentation,
6758          * "Enable Panel Fitter" does not seem to be required when page
6759          * flipping with a non-native mode, and worse causes a normal
6760          * modeset to fail.
6761          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6762          */
6763         pf = 0;
6764         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6765         intel_ring_emit(ring, pf | pipesrc);
6766         intel_ring_advance(ring);
6767         return 0;
6768
6769 err_unpin:
6770         intel_unpin_fb_obj(obj);
6771 err:
6772         return ret;
6773 }
6774
6775 /*
6776  * On gen7 we currently use the blit ring because (in early silicon at least)
6777  * the render ring doesn't give us interrpts for page flip completion, which
6778  * means clients will hang after the first flip is queued.  Fortunately the
6779  * blit ring generates interrupts properly, so use it instead.
6780  */
6781 static int intel_gen7_queue_flip(struct drm_device *dev,
6782                                  struct drm_crtc *crtc,
6783                                  struct drm_framebuffer *fb,
6784                                  struct drm_i915_gem_object *obj)
6785 {
6786         struct drm_i915_private *dev_priv = dev->dev_private;
6787         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6788         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
6789         uint32_t plane_bit = 0;
6790         int ret;
6791
6792         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6793         if (ret)
6794                 goto err;
6795
6796         switch(intel_crtc->plane) {
6797         case PLANE_A:
6798                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
6799                 break;
6800         case PLANE_B:
6801                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
6802                 break;
6803         case PLANE_C:
6804                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
6805                 break;
6806         default:
6807                 WARN_ONCE(1, "unknown plane in flip command\n");
6808                 ret = -ENODEV;
6809                 goto err_unpin;
6810         }
6811
6812         ret = intel_ring_begin(ring, 4);
6813         if (ret)
6814                 goto err_unpin;
6815
6816         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
6817         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
6818         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6819         intel_ring_emit(ring, (MI_NOOP));
6820         intel_ring_advance(ring);
6821         return 0;
6822
6823 err_unpin:
6824         intel_unpin_fb_obj(obj);
6825 err:
6826         return ret;
6827 }
6828
6829 static int intel_default_queue_flip(struct drm_device *dev,
6830                                     struct drm_crtc *crtc,
6831                                     struct drm_framebuffer *fb,
6832                                     struct drm_i915_gem_object *obj)
6833 {
6834         return -ENODEV;
6835 }
6836
6837 static int intel_crtc_page_flip(struct drm_crtc *crtc,
6838                                 struct drm_framebuffer *fb,
6839                                 struct drm_pending_vblank_event *event)
6840 {
6841         struct drm_device *dev = crtc->dev;
6842         struct drm_i915_private *dev_priv = dev->dev_private;
6843         struct intel_framebuffer *intel_fb;
6844         struct drm_i915_gem_object *obj;
6845         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6846         struct intel_unpin_work *work;
6847         unsigned long flags;
6848         int ret;
6849
6850         /* Can't change pixel format via MI display flips. */
6851         if (fb->pixel_format != crtc->fb->pixel_format)
6852                 return -EINVAL;
6853
6854         /*
6855          * TILEOFF/LINOFF registers can't be changed via MI display flips.
6856          * Note that pitch changes could also affect these register.
6857          */
6858         if (INTEL_INFO(dev)->gen > 3 &&
6859             (fb->offsets[0] != crtc->fb->offsets[0] ||
6860              fb->pitches[0] != crtc->fb->pitches[0]))
6861                 return -EINVAL;
6862
6863         work = kzalloc(sizeof *work, GFP_KERNEL);
6864         if (work == NULL)
6865                 return -ENOMEM;
6866
6867         work->event = event;
6868         work->dev = crtc->dev;
6869         intel_fb = to_intel_framebuffer(crtc->fb);
6870         work->old_fb_obj = intel_fb->obj;
6871         INIT_WORK(&work->work, intel_unpin_work_fn);
6872
6873         ret = drm_vblank_get(dev, intel_crtc->pipe);
6874         if (ret)
6875                 goto free_work;
6876
6877         /* We borrow the event spin lock for protecting unpin_work */
6878         spin_lock_irqsave(&dev->event_lock, flags);
6879         if (intel_crtc->unpin_work) {
6880                 spin_unlock_irqrestore(&dev->event_lock, flags);
6881                 kfree(work);
6882                 drm_vblank_put(dev, intel_crtc->pipe);
6883
6884                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6885                 return -EBUSY;
6886         }
6887         intel_crtc->unpin_work = work;
6888         spin_unlock_irqrestore(&dev->event_lock, flags);
6889
6890         intel_fb = to_intel_framebuffer(fb);
6891         obj = intel_fb->obj;
6892
6893         ret = i915_mutex_lock_interruptible(dev);
6894         if (ret)
6895                 goto cleanup;
6896
6897         /* Reference the objects for the scheduled work. */
6898         drm_gem_object_reference(&work->old_fb_obj->base);
6899         drm_gem_object_reference(&obj->base);
6900
6901         crtc->fb = fb;
6902
6903         work->pending_flip_obj = obj;
6904
6905         work->enable_stall_check = true;
6906
6907         /* Block clients from rendering to the new back buffer until
6908          * the flip occurs and the object is no longer visible.
6909          */
6910         atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6911
6912         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6913         if (ret)
6914                 goto cleanup_pending;
6915
6916         intel_disable_fbc(dev);
6917         intel_mark_fb_busy(obj);
6918         mutex_unlock(&dev->struct_mutex);
6919
6920         trace_i915_flip_request(intel_crtc->plane, obj);
6921
6922         return 0;
6923
6924 cleanup_pending:
6925         atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6926         drm_gem_object_unreference(&work->old_fb_obj->base);
6927         drm_gem_object_unreference(&obj->base);
6928         mutex_unlock(&dev->struct_mutex);
6929
6930 cleanup:
6931         spin_lock_irqsave(&dev->event_lock, flags);
6932         intel_crtc->unpin_work = NULL;
6933         spin_unlock_irqrestore(&dev->event_lock, flags);
6934
6935         drm_vblank_put(dev, intel_crtc->pipe);
6936 free_work:
6937         kfree(work);
6938
6939         return ret;
6940 }
6941
6942 static struct drm_crtc_helper_funcs intel_helper_funcs = {
6943         .mode_set_base_atomic = intel_pipe_set_base_atomic,
6944         .load_lut = intel_crtc_load_lut,
6945         .disable = intel_crtc_noop,
6946 };
6947
6948 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
6949 {
6950         struct intel_encoder *other_encoder;
6951         struct drm_crtc *crtc = &encoder->new_crtc->base;
6952
6953         if (WARN_ON(!crtc))
6954                 return false;
6955
6956         list_for_each_entry(other_encoder,
6957                             &crtc->dev->mode_config.encoder_list,
6958                             base.head) {
6959
6960                 if (&other_encoder->new_crtc->base != crtc ||
6961                     encoder == other_encoder)
6962                         continue;
6963                 else
6964                         return true;
6965         }
6966
6967         return false;
6968 }
6969
6970 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
6971                                   struct drm_crtc *crtc)
6972 {
6973         struct drm_device *dev;
6974         struct drm_crtc *tmp;
6975         int crtc_mask = 1;
6976
6977         WARN(!crtc, "checking null crtc?\n");
6978
6979         dev = crtc->dev;
6980
6981         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
6982                 if (tmp == crtc)
6983                         break;
6984                 crtc_mask <<= 1;
6985         }
6986
6987         if (encoder->possible_crtcs & crtc_mask)
6988                 return true;
6989         return false;
6990 }
6991
6992 /**
6993  * intel_modeset_update_staged_output_state
6994  *
6995  * Updates the staged output configuration state, e.g. after we've read out the
6996  * current hw state.
6997  */
6998 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
6999 {
7000         struct intel_encoder *encoder;
7001         struct intel_connector *connector;
7002
7003         list_for_each_entry(connector, &dev->mode_config.connector_list,
7004                             base.head) {
7005                 connector->new_encoder =
7006                         to_intel_encoder(connector->base.encoder);
7007         }
7008
7009         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7010                             base.head) {
7011                 encoder->new_crtc =
7012                         to_intel_crtc(encoder->base.crtc);
7013         }
7014 }
7015
7016 /**
7017  * intel_modeset_commit_output_state
7018  *
7019  * This function copies the stage display pipe configuration to the real one.
7020  */
7021 static void intel_modeset_commit_output_state(struct drm_device *dev)
7022 {
7023         struct intel_encoder *encoder;
7024         struct intel_connector *connector;
7025
7026         list_for_each_entry(connector, &dev->mode_config.connector_list,
7027                             base.head) {
7028                 connector->base.encoder = &connector->new_encoder->base;
7029         }
7030
7031         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7032                             base.head) {
7033                 encoder->base.crtc = &encoder->new_crtc->base;
7034         }
7035 }
7036
7037 static struct drm_display_mode *
7038 intel_modeset_adjusted_mode(struct drm_crtc *crtc,
7039                             struct drm_display_mode *mode)
7040 {
7041         struct drm_device *dev = crtc->dev;
7042         struct drm_display_mode *adjusted_mode;
7043         struct drm_encoder_helper_funcs *encoder_funcs;
7044         struct intel_encoder *encoder;
7045
7046         adjusted_mode = drm_mode_duplicate(dev, mode);
7047         if (!adjusted_mode)
7048                 return ERR_PTR(-ENOMEM);
7049
7050         /* Pass our mode to the connectors and the CRTC to give them a chance to
7051          * adjust it according to limitations or connector properties, and also
7052          * a chance to reject the mode entirely.
7053          */
7054         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7055                             base.head) {
7056
7057                 if (&encoder->new_crtc->base != crtc)
7058                         continue;
7059                 encoder_funcs = encoder->base.helper_private;
7060                 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
7061                                                 adjusted_mode))) {
7062                         DRM_DEBUG_KMS("Encoder fixup failed\n");
7063                         goto fail;
7064                 }
7065         }
7066
7067         if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
7068                 DRM_DEBUG_KMS("CRTC fixup failed\n");
7069                 goto fail;
7070         }
7071         DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7072
7073         return adjusted_mode;
7074 fail:
7075         drm_mode_destroy(dev, adjusted_mode);
7076         return ERR_PTR(-EINVAL);
7077 }
7078
7079 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7080  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7081 static void
7082 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7083                              unsigned *prepare_pipes, unsigned *disable_pipes)
7084 {
7085         struct intel_crtc *intel_crtc;
7086         struct drm_device *dev = crtc->dev;
7087         struct intel_encoder *encoder;
7088         struct intel_connector *connector;
7089         struct drm_crtc *tmp_crtc;
7090
7091         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7092
7093         /* Check which crtcs have changed outputs connected to them, these need
7094          * to be part of the prepare_pipes mask. We don't (yet) support global
7095          * modeset across multiple crtcs, so modeset_pipes will only have one
7096          * bit set at most. */
7097         list_for_each_entry(connector, &dev->mode_config.connector_list,
7098                             base.head) {
7099                 if (connector->base.encoder == &connector->new_encoder->base)
7100                         continue;
7101
7102                 if (connector->base.encoder) {
7103                         tmp_crtc = connector->base.encoder->crtc;
7104
7105                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7106                 }
7107
7108                 if (connector->new_encoder)
7109                         *prepare_pipes |=
7110                                 1 << connector->new_encoder->new_crtc->pipe;
7111         }
7112
7113         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7114                             base.head) {
7115                 if (encoder->base.crtc == &encoder->new_crtc->base)
7116                         continue;
7117
7118                 if (encoder->base.crtc) {
7119                         tmp_crtc = encoder->base.crtc;
7120
7121                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7122                 }
7123
7124                 if (encoder->new_crtc)
7125                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7126         }
7127
7128         /* Check for any pipes that will be fully disabled ... */
7129         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7130                             base.head) {
7131                 bool used = false;
7132
7133                 /* Don't try to disable disabled crtcs. */
7134                 if (!intel_crtc->base.enabled)
7135                         continue;
7136
7137                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7138                                     base.head) {
7139                         if (encoder->new_crtc == intel_crtc)
7140                                 used = true;
7141                 }
7142
7143                 if (!used)
7144                         *disable_pipes |= 1 << intel_crtc->pipe;
7145         }
7146
7147
7148         /* set_mode is also used to update properties on life display pipes. */
7149         intel_crtc = to_intel_crtc(crtc);
7150         if (crtc->enabled)
7151                 *prepare_pipes |= 1 << intel_crtc->pipe;
7152
7153         /* We only support modeset on one single crtc, hence we need to do that
7154          * only for the passed in crtc iff we change anything else than just
7155          * disable crtcs.
7156          *
7157          * This is actually not true, to be fully compatible with the old crtc
7158          * helper we automatically disable _any_ output (i.e. doesn't need to be
7159          * connected to the crtc we're modesetting on) if it's disconnected.
7160          * Which is a rather nutty api (since changed the output configuration
7161          * without userspace's explicit request can lead to confusion), but
7162          * alas. Hence we currently need to modeset on all pipes we prepare. */
7163         if (*prepare_pipes)
7164                 *modeset_pipes = *prepare_pipes;
7165
7166         /* ... and mask these out. */
7167         *modeset_pipes &= ~(*disable_pipes);
7168         *prepare_pipes &= ~(*disable_pipes);
7169 }
7170
7171 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7172 {
7173         struct drm_encoder *encoder;
7174         struct drm_device *dev = crtc->dev;
7175
7176         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7177                 if (encoder->crtc == crtc)
7178                         return true;
7179
7180         return false;
7181 }
7182
7183 static void
7184 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7185 {
7186         struct intel_encoder *intel_encoder;
7187         struct intel_crtc *intel_crtc;
7188         struct drm_connector *connector;
7189
7190         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7191                             base.head) {
7192                 if (!intel_encoder->base.crtc)
7193                         continue;
7194
7195                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7196
7197                 if (prepare_pipes & (1 << intel_crtc->pipe))
7198                         intel_encoder->connectors_active = false;
7199         }
7200
7201         intel_modeset_commit_output_state(dev);
7202
7203         /* Update computed state. */
7204         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7205                             base.head) {
7206                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7207         }
7208
7209         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7210                 if (!connector->encoder || !connector->encoder->crtc)
7211                         continue;
7212
7213                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7214
7215                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
7216                         struct drm_property *dpms_property =
7217                                 dev->mode_config.dpms_property;
7218
7219                         connector->dpms = DRM_MODE_DPMS_ON;
7220                         drm_connector_property_set_value(connector,
7221                                                          dpms_property,
7222                                                          DRM_MODE_DPMS_ON);
7223
7224                         intel_encoder = to_intel_encoder(connector->encoder);
7225                         intel_encoder->connectors_active = true;
7226                 }
7227         }
7228
7229 }
7230
7231 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7232         list_for_each_entry((intel_crtc), \
7233                             &(dev)->mode_config.crtc_list, \
7234                             base.head) \
7235                 if (mask & (1 <<(intel_crtc)->pipe)) \
7236
7237 void
7238 intel_modeset_check_state(struct drm_device *dev)
7239 {
7240         struct intel_crtc *crtc;
7241         struct intel_encoder *encoder;
7242         struct intel_connector *connector;
7243
7244         list_for_each_entry(connector, &dev->mode_config.connector_list,
7245                             base.head) {
7246                 /* This also checks the encoder/connector hw state with the
7247                  * ->get_hw_state callbacks. */
7248                 intel_connector_check_state(connector);
7249
7250                 WARN(&connector->new_encoder->base != connector->base.encoder,
7251                      "connector's staged encoder doesn't match current encoder\n");
7252         }
7253
7254         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7255                             base.head) {
7256                 bool enabled = false;
7257                 bool active = false;
7258                 enum pipe pipe, tracked_pipe;
7259
7260                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7261                               encoder->base.base.id,
7262                               drm_get_encoder_name(&encoder->base));
7263
7264                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7265                      "encoder's stage crtc doesn't match current crtc\n");
7266                 WARN(encoder->connectors_active && !encoder->base.crtc,
7267                      "encoder's active_connectors set, but no crtc\n");
7268
7269                 list_for_each_entry(connector, &dev->mode_config.connector_list,
7270                                     base.head) {
7271                         if (connector->base.encoder != &encoder->base)
7272                                 continue;
7273                         enabled = true;
7274                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7275                                 active = true;
7276                 }
7277                 WARN(!!encoder->base.crtc != enabled,
7278                      "encoder's enabled state mismatch "
7279                      "(expected %i, found %i)\n",
7280                      !!encoder->base.crtc, enabled);
7281                 WARN(active && !encoder->base.crtc,
7282                      "active encoder with no crtc\n");
7283
7284                 WARN(encoder->connectors_active != active,
7285                      "encoder's computed active state doesn't match tracked active state "
7286                      "(expected %i, found %i)\n", active, encoder->connectors_active);
7287
7288                 active = encoder->get_hw_state(encoder, &pipe);
7289                 WARN(active != encoder->connectors_active,
7290                      "encoder's hw state doesn't match sw tracking "
7291                      "(expected %i, found %i)\n",
7292                      encoder->connectors_active, active);
7293
7294                 if (!encoder->base.crtc)
7295                         continue;
7296
7297                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7298                 WARN(active && pipe != tracked_pipe,
7299                      "active encoder's pipe doesn't match"
7300                      "(expected %i, found %i)\n",
7301                      tracked_pipe, pipe);
7302
7303         }
7304
7305         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7306                             base.head) {
7307                 bool enabled = false;
7308                 bool active = false;
7309
7310                 DRM_DEBUG_KMS("[CRTC:%d]\n",
7311                               crtc->base.base.id);
7312
7313                 WARN(crtc->active && !crtc->base.enabled,
7314                      "active crtc, but not enabled in sw tracking\n");
7315
7316                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7317                                     base.head) {
7318                         if (encoder->base.crtc != &crtc->base)
7319                                 continue;
7320                         enabled = true;
7321                         if (encoder->connectors_active)
7322                                 active = true;
7323                 }
7324                 WARN(active != crtc->active,
7325                      "crtc's computed active state doesn't match tracked active state "
7326                      "(expected %i, found %i)\n", active, crtc->active);
7327                 WARN(enabled != crtc->base.enabled,
7328                      "crtc's computed enabled state doesn't match tracked enabled state "
7329                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7330
7331                 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7332         }
7333 }
7334
7335 bool intel_set_mode(struct drm_crtc *crtc,
7336                     struct drm_display_mode *mode,
7337                     int x, int y, struct drm_framebuffer *fb)
7338 {
7339         struct drm_device *dev = crtc->dev;
7340         drm_i915_private_t *dev_priv = dev->dev_private;
7341         struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
7342         struct drm_encoder_helper_funcs *encoder_funcs;
7343         struct drm_encoder *encoder;
7344         struct intel_crtc *intel_crtc;
7345         unsigned disable_pipes, prepare_pipes, modeset_pipes;
7346         bool ret = true;
7347
7348         intel_modeset_affected_pipes(crtc, &modeset_pipes,
7349                                      &prepare_pipes, &disable_pipes);
7350
7351         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7352                       modeset_pipes, prepare_pipes, disable_pipes);
7353
7354         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7355                 intel_crtc_disable(&intel_crtc->base);
7356
7357         saved_hwmode = crtc->hwmode;
7358         saved_mode = crtc->mode;
7359
7360         /* Hack: Because we don't (yet) support global modeset on multiple
7361          * crtcs, we don't keep track of the new mode for more than one crtc.
7362          * Hence simply check whether any bit is set in modeset_pipes in all the
7363          * pieces of code that are not yet converted to deal with mutliple crtcs
7364          * changing their mode at the same time. */
7365         adjusted_mode = NULL;
7366         if (modeset_pipes) {
7367                 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7368                 if (IS_ERR(adjusted_mode)) {
7369                         return false;
7370                 }
7371         }
7372
7373         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7374                 if (intel_crtc->base.enabled)
7375                         dev_priv->display.crtc_disable(&intel_crtc->base);
7376         }
7377
7378         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7379          * to set it here already despite that we pass it down the callchain.
7380          */
7381         if (modeset_pipes)
7382                 crtc->mode = *mode;
7383
7384         /* Only after disabling all output pipelines that will be changed can we
7385          * update the the output configuration. */
7386         intel_modeset_update_state(dev, prepare_pipes);
7387
7388         /* Set up the DPLL and any encoders state that needs to adjust or depend
7389          * on the DPLL.
7390          */
7391         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7392                 ret = !intel_crtc_mode_set(&intel_crtc->base,
7393                                            mode, adjusted_mode,
7394                                            x, y, fb);
7395                 if (!ret)
7396                     goto done;
7397
7398                 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
7399
7400                         if (encoder->crtc != &intel_crtc->base)
7401                                 continue;
7402
7403                         DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
7404                                 encoder->base.id, drm_get_encoder_name(encoder),
7405                                 mode->base.id, mode->name);
7406                         encoder_funcs = encoder->helper_private;
7407                         encoder_funcs->mode_set(encoder, mode, adjusted_mode);
7408                 }
7409         }
7410
7411         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7412         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7413                 dev_priv->display.crtc_enable(&intel_crtc->base);
7414
7415         if (modeset_pipes) {
7416                 /* Store real post-adjustment hardware mode. */
7417                 crtc->hwmode = *adjusted_mode;
7418
7419                 /* Calculate and store various constants which
7420                  * are later needed by vblank and swap-completion
7421                  * timestamping. They are derived from true hwmode.
7422                  */
7423                 drm_calc_timestamping_constants(crtc);
7424         }
7425
7426         /* FIXME: add subpixel order */
7427 done:
7428         drm_mode_destroy(dev, adjusted_mode);
7429         if (!ret && crtc->enabled) {
7430                 crtc->hwmode = saved_hwmode;
7431                 crtc->mode = saved_mode;
7432         } else {
7433                 intel_modeset_check_state(dev);
7434         }
7435
7436         return ret;
7437 }
7438
7439 #undef for_each_intel_crtc_masked
7440
7441 static void intel_set_config_free(struct intel_set_config *config)
7442 {
7443         if (!config)
7444                 return;
7445
7446         kfree(config->save_connector_encoders);
7447         kfree(config->save_encoder_crtcs);
7448         kfree(config);
7449 }
7450
7451 static int intel_set_config_save_state(struct drm_device *dev,
7452                                        struct intel_set_config *config)
7453 {
7454         struct drm_encoder *encoder;
7455         struct drm_connector *connector;
7456         int count;
7457
7458         config->save_encoder_crtcs =
7459                 kcalloc(dev->mode_config.num_encoder,
7460                         sizeof(struct drm_crtc *), GFP_KERNEL);
7461         if (!config->save_encoder_crtcs)
7462                 return -ENOMEM;
7463
7464         config->save_connector_encoders =
7465                 kcalloc(dev->mode_config.num_connector,
7466                         sizeof(struct drm_encoder *), GFP_KERNEL);
7467         if (!config->save_connector_encoders)
7468                 return -ENOMEM;
7469
7470         /* Copy data. Note that driver private data is not affected.
7471          * Should anything bad happen only the expected state is
7472          * restored, not the drivers personal bookkeeping.
7473          */
7474         count = 0;
7475         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
7476                 config->save_encoder_crtcs[count++] = encoder->crtc;
7477         }
7478
7479         count = 0;
7480         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7481                 config->save_connector_encoders[count++] = connector->encoder;
7482         }
7483
7484         return 0;
7485 }
7486
7487 static void intel_set_config_restore_state(struct drm_device *dev,
7488                                            struct intel_set_config *config)
7489 {
7490         struct intel_encoder *encoder;
7491         struct intel_connector *connector;
7492         int count;
7493
7494         count = 0;
7495         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7496                 encoder->new_crtc =
7497                         to_intel_crtc(config->save_encoder_crtcs[count++]);
7498         }
7499
7500         count = 0;
7501         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7502                 connector->new_encoder =
7503                         to_intel_encoder(config->save_connector_encoders[count++]);
7504         }
7505 }
7506
7507 static void
7508 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7509                                       struct intel_set_config *config)
7510 {
7511
7512         /* We should be able to check here if the fb has the same properties
7513          * and then just flip_or_move it */
7514         if (set->crtc->fb != set->fb) {
7515                 /* If we have no fb then treat it as a full mode set */
7516                 if (set->crtc->fb == NULL) {
7517                         DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7518                         config->mode_changed = true;
7519                 } else if (set->fb == NULL) {
7520                         config->mode_changed = true;
7521                 } else if (set->fb->depth != set->crtc->fb->depth) {
7522                         config->mode_changed = true;
7523                 } else if (set->fb->bits_per_pixel !=
7524                            set->crtc->fb->bits_per_pixel) {
7525                         config->mode_changed = true;
7526                 } else
7527                         config->fb_changed = true;
7528         }
7529
7530         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
7531                 config->fb_changed = true;
7532
7533         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7534                 DRM_DEBUG_KMS("modes are different, full mode set\n");
7535                 drm_mode_debug_printmodeline(&set->crtc->mode);
7536                 drm_mode_debug_printmodeline(set->mode);
7537                 config->mode_changed = true;
7538         }
7539 }
7540
7541 static int
7542 intel_modeset_stage_output_state(struct drm_device *dev,
7543                                  struct drm_mode_set *set,
7544                                  struct intel_set_config *config)
7545 {
7546         struct drm_crtc *new_crtc;
7547         struct intel_connector *connector;
7548         struct intel_encoder *encoder;
7549         int count, ro;
7550
7551         /* The upper layers ensure that we either disabl a crtc or have a list
7552          * of connectors. For paranoia, double-check this. */
7553         WARN_ON(!set->fb && (set->num_connectors != 0));
7554         WARN_ON(set->fb && (set->num_connectors == 0));
7555
7556         count = 0;
7557         list_for_each_entry(connector, &dev->mode_config.connector_list,
7558                             base.head) {
7559                 /* Otherwise traverse passed in connector list and get encoders
7560                  * for them. */
7561                 for (ro = 0; ro < set->num_connectors; ro++) {
7562                         if (set->connectors[ro] == &connector->base) {
7563                                 connector->new_encoder = connector->encoder;
7564                                 break;
7565                         }
7566                 }
7567
7568                 /* If we disable the crtc, disable all its connectors. Also, if
7569                  * the connector is on the changing crtc but not on the new
7570                  * connector list, disable it. */
7571                 if ((!set->fb || ro == set->num_connectors) &&
7572                     connector->base.encoder &&
7573                     connector->base.encoder->crtc == set->crtc) {
7574                         connector->new_encoder = NULL;
7575
7576                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7577                                 connector->base.base.id,
7578                                 drm_get_connector_name(&connector->base));
7579                 }
7580
7581
7582                 if (&connector->new_encoder->base != connector->base.encoder) {
7583                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
7584                         config->mode_changed = true;
7585                 }
7586
7587                 /* Disable all disconnected encoders. */
7588                 if (connector->base.status == connector_status_disconnected)
7589                         connector->new_encoder = NULL;
7590         }
7591         /* connector->new_encoder is now updated for all connectors. */
7592
7593         /* Update crtc of enabled connectors. */
7594         count = 0;
7595         list_for_each_entry(connector, &dev->mode_config.connector_list,
7596                             base.head) {
7597                 if (!connector->new_encoder)
7598                         continue;
7599
7600                 new_crtc = connector->new_encoder->base.crtc;
7601
7602                 for (ro = 0; ro < set->num_connectors; ro++) {
7603                         if (set->connectors[ro] == &connector->base)
7604                                 new_crtc = set->crtc;
7605                 }
7606
7607                 /* Make sure the new CRTC will work with the encoder */
7608                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
7609                                            new_crtc)) {
7610                         return -EINVAL;
7611                 }
7612                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
7613
7614                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
7615                         connector->base.base.id,
7616                         drm_get_connector_name(&connector->base),
7617                         new_crtc->base.id);
7618         }
7619
7620         /* Check for any encoders that needs to be disabled. */
7621         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7622                             base.head) {
7623                 list_for_each_entry(connector,
7624                                     &dev->mode_config.connector_list,
7625                                     base.head) {
7626                         if (connector->new_encoder == encoder) {
7627                                 WARN_ON(!connector->new_encoder->new_crtc);
7628
7629                                 goto next_encoder;
7630                         }
7631                 }
7632                 encoder->new_crtc = NULL;
7633 next_encoder:
7634                 /* Only now check for crtc changes so we don't miss encoders
7635                  * that will be disabled. */
7636                 if (&encoder->new_crtc->base != encoder->base.crtc) {
7637                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
7638                         config->mode_changed = true;
7639                 }
7640         }
7641         /* Now we've also updated encoder->new_crtc for all encoders. */
7642
7643         return 0;
7644 }
7645
7646 static int intel_crtc_set_config(struct drm_mode_set *set)
7647 {
7648         struct drm_device *dev;
7649         struct drm_mode_set save_set;
7650         struct intel_set_config *config;
7651         int ret;
7652
7653         BUG_ON(!set);
7654         BUG_ON(!set->crtc);
7655         BUG_ON(!set->crtc->helper_private);
7656
7657         if (!set->mode)
7658                 set->fb = NULL;
7659
7660         /* The fb helper likes to play gross jokes with ->mode_set_config.
7661          * Unfortunately the crtc helper doesn't do much at all for this case,
7662          * so we have to cope with this madness until the fb helper is fixed up. */
7663         if (set->fb && set->num_connectors == 0)
7664                 return 0;
7665
7666         if (set->fb) {
7667                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
7668                                 set->crtc->base.id, set->fb->base.id,
7669                                 (int)set->num_connectors, set->x, set->y);
7670         } else {
7671                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
7672         }
7673
7674         dev = set->crtc->dev;
7675
7676         ret = -ENOMEM;
7677         config = kzalloc(sizeof(*config), GFP_KERNEL);
7678         if (!config)
7679                 goto out_config;
7680
7681         ret = intel_set_config_save_state(dev, config);
7682         if (ret)
7683                 goto out_config;
7684
7685         save_set.crtc = set->crtc;
7686         save_set.mode = &set->crtc->mode;
7687         save_set.x = set->crtc->x;
7688         save_set.y = set->crtc->y;
7689         save_set.fb = set->crtc->fb;
7690
7691         /* Compute whether we need a full modeset, only an fb base update or no
7692          * change at all. In the future we might also check whether only the
7693          * mode changed, e.g. for LVDS where we only change the panel fitter in
7694          * such cases. */
7695         intel_set_config_compute_mode_changes(set, config);
7696
7697         ret = intel_modeset_stage_output_state(dev, set, config);
7698         if (ret)
7699                 goto fail;
7700
7701         if (config->mode_changed) {
7702                 if (set->mode) {
7703                         DRM_DEBUG_KMS("attempting to set mode from"
7704                                         " userspace\n");
7705                         drm_mode_debug_printmodeline(set->mode);
7706                 }
7707
7708                 if (!intel_set_mode(set->crtc, set->mode,
7709                                     set->x, set->y, set->fb)) {
7710                         DRM_ERROR("failed to set mode on [CRTC:%d]\n",
7711                                   set->crtc->base.id);
7712                         ret = -EINVAL;
7713                         goto fail;
7714                 }
7715         } else if (config->fb_changed) {
7716                 ret = intel_pipe_set_base(set->crtc,
7717                                           set->x, set->y, set->fb);
7718         }
7719
7720         intel_set_config_free(config);
7721
7722         return 0;
7723
7724 fail:
7725         intel_set_config_restore_state(dev, config);
7726
7727         /* Try to restore the config */
7728         if (config->mode_changed &&
7729             !intel_set_mode(save_set.crtc, save_set.mode,
7730                             save_set.x, save_set.y, save_set.fb))
7731                 DRM_ERROR("failed to restore config after modeset failure\n");
7732
7733 out_config:
7734         intel_set_config_free(config);
7735         return ret;
7736 }
7737
7738 static const struct drm_crtc_funcs intel_crtc_funcs = {
7739         .cursor_set = intel_crtc_cursor_set,
7740         .cursor_move = intel_crtc_cursor_move,
7741         .gamma_set = intel_crtc_gamma_set,
7742         .set_config = intel_crtc_set_config,
7743         .destroy = intel_crtc_destroy,
7744         .page_flip = intel_crtc_page_flip,
7745 };
7746
7747 static void intel_cpu_pll_init(struct drm_device *dev)
7748 {
7749         if (IS_HASWELL(dev))
7750                 intel_ddi_pll_init(dev);
7751 }
7752
7753 static void intel_pch_pll_init(struct drm_device *dev)
7754 {
7755         drm_i915_private_t *dev_priv = dev->dev_private;
7756         int i;
7757
7758         if (dev_priv->num_pch_pll == 0) {
7759                 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
7760                 return;
7761         }
7762
7763         for (i = 0; i < dev_priv->num_pch_pll; i++) {
7764                 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
7765                 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
7766                 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
7767         }
7768 }
7769
7770 static void intel_crtc_init(struct drm_device *dev, int pipe)
7771 {
7772         drm_i915_private_t *dev_priv = dev->dev_private;
7773         struct intel_crtc *intel_crtc;
7774         int i;
7775
7776         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7777         if (intel_crtc == NULL)
7778                 return;
7779
7780         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7781
7782         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
7783         for (i = 0; i < 256; i++) {
7784                 intel_crtc->lut_r[i] = i;
7785                 intel_crtc->lut_g[i] = i;
7786                 intel_crtc->lut_b[i] = i;
7787         }
7788
7789         /* Swap pipes & planes for FBC on pre-965 */
7790         intel_crtc->pipe = pipe;
7791         intel_crtc->plane = pipe;
7792         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
7793                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
7794                 intel_crtc->plane = !pipe;
7795         }
7796
7797         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7798                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7799         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7800         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7801
7802         intel_crtc->bpp = 24; /* default for pre-Ironlake */
7803
7804         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
7805 }
7806
7807 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
7808                                 struct drm_file *file)
7809 {
7810         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7811         struct drm_mode_object *drmmode_obj;
7812         struct intel_crtc *crtc;
7813
7814         if (!drm_core_check_feature(dev, DRIVER_MODESET))
7815                 return -ENODEV;
7816
7817         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7818                         DRM_MODE_OBJECT_CRTC);
7819
7820         if (!drmmode_obj) {
7821                 DRM_ERROR("no such CRTC id\n");
7822                 return -EINVAL;
7823         }
7824
7825         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7826         pipe_from_crtc_id->pipe = crtc->pipe;
7827
7828         return 0;
7829 }
7830
7831 static int intel_encoder_clones(struct intel_encoder *encoder)
7832 {
7833         struct drm_device *dev = encoder->base.dev;
7834         struct intel_encoder *source_encoder;
7835         int index_mask = 0;
7836         int entry = 0;
7837
7838         list_for_each_entry(source_encoder,
7839                             &dev->mode_config.encoder_list, base.head) {
7840
7841                 if (encoder == source_encoder)
7842                         index_mask |= (1 << entry);
7843
7844                 /* Intel hw has only one MUX where enocoders could be cloned. */
7845                 if (encoder->cloneable && source_encoder->cloneable)
7846                         index_mask |= (1 << entry);
7847
7848                 entry++;
7849         }
7850
7851         return index_mask;
7852 }
7853
7854 static bool has_edp_a(struct drm_device *dev)
7855 {
7856         struct drm_i915_private *dev_priv = dev->dev_private;
7857
7858         if (!IS_MOBILE(dev))
7859                 return false;
7860
7861         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7862                 return false;
7863
7864         if (IS_GEN5(dev) &&
7865             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7866                 return false;
7867
7868         return true;
7869 }
7870
7871 static void intel_setup_outputs(struct drm_device *dev)
7872 {
7873         struct drm_i915_private *dev_priv = dev->dev_private;
7874         struct intel_encoder *encoder;
7875         bool dpd_is_edp = false;
7876         bool has_lvds;
7877
7878         has_lvds = intel_lvds_init(dev);
7879         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7880                 /* disable the panel fitter on everything but LVDS */
7881                 I915_WRITE(PFIT_CONTROL, 0);
7882         }
7883
7884         if (HAS_PCH_SPLIT(dev)) {
7885                 dpd_is_edp = intel_dpd_is_edp(dev);
7886
7887                 if (has_edp_a(dev))
7888                         intel_dp_init(dev, DP_A, PORT_A);
7889
7890                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7891                         intel_dp_init(dev, PCH_DP_D, PORT_D);
7892         }
7893
7894         intel_crt_init(dev);
7895
7896         if (IS_HASWELL(dev)) {
7897                 int found;
7898
7899                 /* Haswell uses DDI functions to detect digital outputs */
7900                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
7901                 /* DDI A only supports eDP */
7902                 if (found)
7903                         intel_ddi_init(dev, PORT_A);
7904
7905                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
7906                  * register */
7907                 found = I915_READ(SFUSE_STRAP);
7908
7909                 if (found & SFUSE_STRAP_DDIB_DETECTED)
7910                         intel_ddi_init(dev, PORT_B);
7911                 if (found & SFUSE_STRAP_DDIC_DETECTED)
7912                         intel_ddi_init(dev, PORT_C);
7913                 if (found & SFUSE_STRAP_DDID_DETECTED)
7914                         intel_ddi_init(dev, PORT_D);
7915         } else if (HAS_PCH_SPLIT(dev)) {
7916                 int found;
7917
7918                 if (I915_READ(HDMIB) & PORT_DETECTED) {
7919                         /* PCH SDVOB multiplex with HDMIB */
7920                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
7921                         if (!found)
7922                                 intel_hdmi_init(dev, HDMIB, PORT_B);
7923                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
7924                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
7925                 }
7926
7927                 if (I915_READ(HDMIC) & PORT_DETECTED)
7928                         intel_hdmi_init(dev, HDMIC, PORT_C);
7929
7930                 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
7931                         intel_hdmi_init(dev, HDMID, PORT_D);
7932
7933                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
7934                         intel_dp_init(dev, PCH_DP_C, PORT_C);
7935
7936                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7937                         intel_dp_init(dev, PCH_DP_D, PORT_D);
7938         } else if (IS_VALLEYVIEW(dev)) {
7939                 int found;
7940
7941                 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
7942                 if (I915_READ(DP_C) & DP_DETECTED)
7943                         intel_dp_init(dev, DP_C, PORT_C);
7944
7945                 if (I915_READ(SDVOB) & PORT_DETECTED) {
7946                         /* SDVOB multiplex with HDMIB */
7947                         found = intel_sdvo_init(dev, SDVOB, true);
7948                         if (!found)
7949                                 intel_hdmi_init(dev, SDVOB, PORT_B);
7950                         if (!found && (I915_READ(DP_B) & DP_DETECTED))
7951                                 intel_dp_init(dev, DP_B, PORT_B);
7952                 }
7953
7954                 if (I915_READ(SDVOC) & PORT_DETECTED)
7955                         intel_hdmi_init(dev, SDVOC, PORT_C);
7956
7957         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
7958                 bool found = false;
7959
7960                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7961                         DRM_DEBUG_KMS("probing SDVOB\n");
7962                         found = intel_sdvo_init(dev, SDVOB, true);
7963                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
7964                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
7965                                 intel_hdmi_init(dev, SDVOB, PORT_B);
7966                         }
7967
7968                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
7969                                 DRM_DEBUG_KMS("probing DP_B\n");
7970                                 intel_dp_init(dev, DP_B, PORT_B);
7971                         }
7972                 }
7973
7974                 /* Before G4X SDVOC doesn't have its own detect register */
7975
7976                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7977                         DRM_DEBUG_KMS("probing SDVOC\n");
7978                         found = intel_sdvo_init(dev, SDVOC, false);
7979                 }
7980
7981                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
7982
7983                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
7984                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
7985                                 intel_hdmi_init(dev, SDVOC, PORT_C);
7986                         }
7987                         if (SUPPORTS_INTEGRATED_DP(dev)) {
7988                                 DRM_DEBUG_KMS("probing DP_C\n");
7989                                 intel_dp_init(dev, DP_C, PORT_C);
7990                         }
7991                 }
7992
7993                 if (SUPPORTS_INTEGRATED_DP(dev) &&
7994                     (I915_READ(DP_D) & DP_DETECTED)) {
7995                         DRM_DEBUG_KMS("probing DP_D\n");
7996                         intel_dp_init(dev, DP_D, PORT_D);
7997                 }
7998         } else if (IS_GEN2(dev))
7999                 intel_dvo_init(dev);
8000
8001         if (SUPPORTS_TV(dev))
8002                 intel_tv_init(dev);
8003
8004         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8005                 encoder->base.possible_crtcs = encoder->crtc_mask;
8006                 encoder->base.possible_clones =
8007                         intel_encoder_clones(encoder);
8008         }
8009
8010         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8011                 ironlake_init_pch_refclk(dev);
8012 }
8013
8014 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8015 {
8016         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8017
8018         drm_framebuffer_cleanup(fb);
8019         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8020
8021         kfree(intel_fb);
8022 }
8023
8024 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8025                                                 struct drm_file *file,
8026                                                 unsigned int *handle)
8027 {
8028         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8029         struct drm_i915_gem_object *obj = intel_fb->obj;
8030
8031         return drm_gem_handle_create(file, &obj->base, handle);
8032 }
8033
8034 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8035         .destroy = intel_user_framebuffer_destroy,
8036         .create_handle = intel_user_framebuffer_create_handle,
8037 };
8038
8039 int intel_framebuffer_init(struct drm_device *dev,
8040                            struct intel_framebuffer *intel_fb,
8041                            struct drm_mode_fb_cmd2 *mode_cmd,
8042                            struct drm_i915_gem_object *obj)
8043 {
8044         int ret;
8045
8046         if (obj->tiling_mode == I915_TILING_Y)
8047                 return -EINVAL;
8048
8049         if (mode_cmd->pitches[0] & 63)
8050                 return -EINVAL;
8051
8052         switch (mode_cmd->pixel_format) {
8053         case DRM_FORMAT_RGB332:
8054         case DRM_FORMAT_RGB565:
8055         case DRM_FORMAT_XRGB8888:
8056         case DRM_FORMAT_XBGR8888:
8057         case DRM_FORMAT_ARGB8888:
8058         case DRM_FORMAT_XRGB2101010:
8059         case DRM_FORMAT_ARGB2101010:
8060                 /* RGB formats are common across chipsets */
8061                 break;
8062         case DRM_FORMAT_YUYV:
8063         case DRM_FORMAT_UYVY:
8064         case DRM_FORMAT_YVYU:
8065         case DRM_FORMAT_VYUY:
8066                 break;
8067         default:
8068                 DRM_DEBUG_KMS("unsupported pixel format %u\n",
8069                                 mode_cmd->pixel_format);
8070                 return -EINVAL;
8071         }
8072
8073         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8074         if (ret) {
8075                 DRM_ERROR("framebuffer init failed %d\n", ret);
8076                 return ret;
8077         }
8078
8079         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8080         intel_fb->obj = obj;
8081         return 0;
8082 }
8083
8084 static struct drm_framebuffer *
8085 intel_user_framebuffer_create(struct drm_device *dev,
8086                               struct drm_file *filp,
8087                               struct drm_mode_fb_cmd2 *mode_cmd)
8088 {
8089         struct drm_i915_gem_object *obj;
8090
8091         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8092                                                 mode_cmd->handles[0]));
8093         if (&obj->base == NULL)
8094                 return ERR_PTR(-ENOENT);
8095
8096         return intel_framebuffer_create(dev, mode_cmd, obj);
8097 }
8098
8099 static const struct drm_mode_config_funcs intel_mode_funcs = {
8100         .fb_create = intel_user_framebuffer_create,
8101         .output_poll_changed = intel_fb_output_poll_changed,
8102 };
8103
8104 /* Set up chip specific display functions */
8105 static void intel_init_display(struct drm_device *dev)
8106 {
8107         struct drm_i915_private *dev_priv = dev->dev_private;
8108
8109         /* We always want a DPMS function */
8110         if (IS_HASWELL(dev)) {
8111                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
8112                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8113                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
8114                 dev_priv->display.off = haswell_crtc_off;
8115                 dev_priv->display.update_plane = ironlake_update_plane;
8116         } else if (HAS_PCH_SPLIT(dev)) {
8117                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8118                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8119                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
8120                 dev_priv->display.off = ironlake_crtc_off;
8121                 dev_priv->display.update_plane = ironlake_update_plane;
8122         } else {
8123                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8124                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8125                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8126                 dev_priv->display.off = i9xx_crtc_off;
8127                 dev_priv->display.update_plane = i9xx_update_plane;
8128         }
8129
8130         /* Returns the core display clock speed */
8131         if (IS_VALLEYVIEW(dev))
8132                 dev_priv->display.get_display_clock_speed =
8133                         valleyview_get_display_clock_speed;
8134         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8135                 dev_priv->display.get_display_clock_speed =
8136                         i945_get_display_clock_speed;
8137         else if (IS_I915G(dev))
8138                 dev_priv->display.get_display_clock_speed =
8139                         i915_get_display_clock_speed;
8140         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8141                 dev_priv->display.get_display_clock_speed =
8142                         i9xx_misc_get_display_clock_speed;
8143         else if (IS_I915GM(dev))
8144                 dev_priv->display.get_display_clock_speed =
8145                         i915gm_get_display_clock_speed;
8146         else if (IS_I865G(dev))
8147                 dev_priv->display.get_display_clock_speed =
8148                         i865_get_display_clock_speed;
8149         else if (IS_I85X(dev))
8150                 dev_priv->display.get_display_clock_speed =
8151                         i855_get_display_clock_speed;
8152         else /* 852, 830 */
8153                 dev_priv->display.get_display_clock_speed =
8154                         i830_get_display_clock_speed;
8155
8156         if (HAS_PCH_SPLIT(dev)) {
8157                 if (IS_GEN5(dev)) {
8158                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8159                         dev_priv->display.write_eld = ironlake_write_eld;
8160                 } else if (IS_GEN6(dev)) {
8161                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8162                         dev_priv->display.write_eld = ironlake_write_eld;
8163                 } else if (IS_IVYBRIDGE(dev)) {
8164                         /* FIXME: detect B0+ stepping and use auto training */
8165                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8166                         dev_priv->display.write_eld = ironlake_write_eld;
8167                 } else if (IS_HASWELL(dev)) {
8168                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
8169                         dev_priv->display.write_eld = haswell_write_eld;
8170                 } else
8171                         dev_priv->display.update_wm = NULL;
8172         } else if (IS_G4X(dev)) {
8173                 dev_priv->display.write_eld = g4x_write_eld;
8174         }
8175
8176         /* Default just returns -ENODEV to indicate unsupported */
8177         dev_priv->display.queue_flip = intel_default_queue_flip;
8178
8179         switch (INTEL_INFO(dev)->gen) {
8180         case 2:
8181                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8182                 break;
8183
8184         case 3:
8185                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8186                 break;
8187
8188         case 4:
8189         case 5:
8190                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8191                 break;
8192
8193         case 6:
8194                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8195                 break;
8196         case 7:
8197                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8198                 break;
8199         }
8200 }
8201
8202 /*
8203  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8204  * resume, or other times.  This quirk makes sure that's the case for
8205  * affected systems.
8206  */
8207 static void quirk_pipea_force(struct drm_device *dev)
8208 {
8209         struct drm_i915_private *dev_priv = dev->dev_private;
8210
8211         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8212         DRM_INFO("applying pipe a force quirk\n");
8213 }
8214
8215 /*
8216  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8217  */
8218 static void quirk_ssc_force_disable(struct drm_device *dev)
8219 {
8220         struct drm_i915_private *dev_priv = dev->dev_private;
8221         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8222         DRM_INFO("applying lvds SSC disable quirk\n");
8223 }
8224
8225 /*
8226  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8227  * brightness value
8228  */
8229 static void quirk_invert_brightness(struct drm_device *dev)
8230 {
8231         struct drm_i915_private *dev_priv = dev->dev_private;
8232         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
8233         DRM_INFO("applying inverted panel brightness quirk\n");
8234 }
8235
8236 struct intel_quirk {
8237         int device;
8238         int subsystem_vendor;
8239         int subsystem_device;
8240         void (*hook)(struct drm_device *dev);
8241 };
8242
8243 static struct intel_quirk intel_quirks[] = {
8244         /* HP Mini needs pipe A force quirk (LP: #322104) */
8245         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
8246
8247         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8248         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8249
8250         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8251         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8252
8253         /* 830/845 need to leave pipe A & dpll A up */
8254         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8255         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8256
8257         /* Lenovo U160 cannot use SSC on LVDS */
8258         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8259
8260         /* Sony Vaio Y cannot use SSC on LVDS */
8261         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
8262
8263         /* Acer Aspire 5734Z must invert backlight brightness */
8264         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
8265 };
8266
8267 static void intel_init_quirks(struct drm_device *dev)
8268 {
8269         struct pci_dev *d = dev->pdev;
8270         int i;
8271
8272         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8273                 struct intel_quirk *q = &intel_quirks[i];
8274
8275                 if (d->device == q->device &&
8276                     (d->subsystem_vendor == q->subsystem_vendor ||
8277                      q->subsystem_vendor == PCI_ANY_ID) &&
8278                     (d->subsystem_device == q->subsystem_device ||
8279                      q->subsystem_device == PCI_ANY_ID))
8280                         q->hook(dev);
8281         }
8282 }
8283
8284 /* Disable the VGA plane that we never use */
8285 static void i915_disable_vga(struct drm_device *dev)
8286 {
8287         struct drm_i915_private *dev_priv = dev->dev_private;
8288         u8 sr1;
8289         u32 vga_reg;
8290
8291         if (HAS_PCH_SPLIT(dev))
8292                 vga_reg = CPU_VGACNTRL;
8293         else
8294                 vga_reg = VGACNTRL;
8295
8296         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8297         outb(SR01, VGA_SR_INDEX);
8298         sr1 = inb(VGA_SR_DATA);
8299         outb(sr1 | 1<<5, VGA_SR_DATA);
8300         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8301         udelay(300);
8302
8303         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8304         POSTING_READ(vga_reg);
8305 }
8306
8307 void intel_modeset_init_hw(struct drm_device *dev)
8308 {
8309         /* We attempt to init the necessary power wells early in the initialization
8310          * time, so the subsystems that expect power to be enabled can work.
8311          */
8312         intel_init_power_wells(dev);
8313
8314         intel_prepare_ddi(dev);
8315
8316         intel_init_clock_gating(dev);
8317
8318         mutex_lock(&dev->struct_mutex);
8319         intel_enable_gt_powersave(dev);
8320         mutex_unlock(&dev->struct_mutex);
8321 }
8322
8323 void intel_modeset_init(struct drm_device *dev)
8324 {
8325         struct drm_i915_private *dev_priv = dev->dev_private;
8326         int i, ret;
8327
8328         drm_mode_config_init(dev);
8329
8330         dev->mode_config.min_width = 0;
8331         dev->mode_config.min_height = 0;
8332
8333         dev->mode_config.preferred_depth = 24;
8334         dev->mode_config.prefer_shadow = 1;
8335
8336         dev->mode_config.funcs = &intel_mode_funcs;
8337
8338         intel_init_quirks(dev);
8339
8340         intel_init_pm(dev);
8341
8342         intel_init_display(dev);
8343
8344         if (IS_GEN2(dev)) {
8345                 dev->mode_config.max_width = 2048;
8346                 dev->mode_config.max_height = 2048;
8347         } else if (IS_GEN3(dev)) {
8348                 dev->mode_config.max_width = 4096;
8349                 dev->mode_config.max_height = 4096;
8350         } else {
8351                 dev->mode_config.max_width = 8192;
8352                 dev->mode_config.max_height = 8192;
8353         }
8354         dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
8355
8356         DRM_DEBUG_KMS("%d display pipe%s available.\n",
8357                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
8358
8359         for (i = 0; i < dev_priv->num_pipe; i++) {
8360                 intel_crtc_init(dev, i);
8361                 ret = intel_plane_init(dev, i);
8362                 if (ret)
8363                         DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
8364         }
8365
8366         intel_cpu_pll_init(dev);
8367         intel_pch_pll_init(dev);
8368
8369         /* Just disable it once at startup */
8370         i915_disable_vga(dev);
8371         intel_setup_outputs(dev);
8372 }
8373
8374 static void
8375 intel_connector_break_all_links(struct intel_connector *connector)
8376 {
8377         connector->base.dpms = DRM_MODE_DPMS_OFF;
8378         connector->base.encoder = NULL;
8379         connector->encoder->connectors_active = false;
8380         connector->encoder->base.crtc = NULL;
8381 }
8382
8383 static void intel_enable_pipe_a(struct drm_device *dev)
8384 {
8385         struct intel_connector *connector;
8386         struct drm_connector *crt = NULL;
8387         struct intel_load_detect_pipe load_detect_temp;
8388
8389         /* We can't just switch on the pipe A, we need to set things up with a
8390          * proper mode and output configuration. As a gross hack, enable pipe A
8391          * by enabling the load detect pipe once. */
8392         list_for_each_entry(connector,
8393                             &dev->mode_config.connector_list,
8394                             base.head) {
8395                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8396                         crt = &connector->base;
8397                         break;
8398                 }
8399         }
8400
8401         if (!crt)
8402                 return;
8403
8404         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8405                 intel_release_load_detect_pipe(crt, &load_detect_temp);
8406
8407
8408 }
8409
8410 static bool
8411 intel_check_plane_mapping(struct intel_crtc *crtc)
8412 {
8413         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8414         u32 reg, val;
8415
8416         if (dev_priv->num_pipe == 1)
8417                 return true;
8418
8419         reg = DSPCNTR(!crtc->plane);
8420         val = I915_READ(reg);
8421
8422         if ((val & DISPLAY_PLANE_ENABLE) &&
8423             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8424                 return false;
8425
8426         return true;
8427 }
8428
8429 static void intel_sanitize_crtc(struct intel_crtc *crtc)
8430 {
8431         struct drm_device *dev = crtc->base.dev;
8432         struct drm_i915_private *dev_priv = dev->dev_private;
8433         u32 reg;
8434
8435         /* Clear any frame start delays used for debugging left by the BIOS */
8436         reg = PIPECONF(crtc->pipe);
8437         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8438
8439         /* We need to sanitize the plane -> pipe mapping first because this will
8440          * disable the crtc (and hence change the state) if it is wrong. Note
8441          * that gen4+ has a fixed plane -> pipe mapping.  */
8442         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
8443                 struct intel_connector *connector;
8444                 bool plane;
8445
8446                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8447                               crtc->base.base.id);
8448
8449                 /* Pipe has the wrong plane attached and the plane is active.
8450                  * Temporarily change the plane mapping and disable everything
8451                  * ...  */
8452                 plane = crtc->plane;
8453                 crtc->plane = !plane;
8454                 dev_priv->display.crtc_disable(&crtc->base);
8455                 crtc->plane = plane;
8456
8457                 /* ... and break all links. */
8458                 list_for_each_entry(connector, &dev->mode_config.connector_list,
8459                                     base.head) {
8460                         if (connector->encoder->base.crtc != &crtc->base)
8461                                 continue;
8462
8463                         intel_connector_break_all_links(connector);
8464                 }
8465
8466                 WARN_ON(crtc->active);
8467                 crtc->base.enabled = false;
8468         }
8469
8470         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8471             crtc->pipe == PIPE_A && !crtc->active) {
8472                 /* BIOS forgot to enable pipe A, this mostly happens after
8473                  * resume. Force-enable the pipe to fix this, the update_dpms
8474                  * call below we restore the pipe to the right state, but leave
8475                  * the required bits on. */
8476                 intel_enable_pipe_a(dev);
8477         }
8478
8479         /* Adjust the state of the output pipe according to whether we
8480          * have active connectors/encoders. */
8481         intel_crtc_update_dpms(&crtc->base);
8482
8483         if (crtc->active != crtc->base.enabled) {
8484                 struct intel_encoder *encoder;
8485
8486                 /* This can happen either due to bugs in the get_hw_state
8487                  * functions or because the pipe is force-enabled due to the
8488                  * pipe A quirk. */
8489                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8490                               crtc->base.base.id,
8491                               crtc->base.enabled ? "enabled" : "disabled",
8492                               crtc->active ? "enabled" : "disabled");
8493
8494                 crtc->base.enabled = crtc->active;
8495
8496                 /* Because we only establish the connector -> encoder ->
8497                  * crtc links if something is active, this means the
8498                  * crtc is now deactivated. Break the links. connector
8499                  * -> encoder links are only establish when things are
8500                  *  actually up, hence no need to break them. */
8501                 WARN_ON(crtc->active);
8502
8503                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
8504                         WARN_ON(encoder->connectors_active);
8505                         encoder->base.crtc = NULL;
8506                 }
8507         }
8508 }
8509
8510 static void intel_sanitize_encoder(struct intel_encoder *encoder)
8511 {
8512         struct intel_connector *connector;
8513         struct drm_device *dev = encoder->base.dev;
8514
8515         /* We need to check both for a crtc link (meaning that the
8516          * encoder is active and trying to read from a pipe) and the
8517          * pipe itself being active. */
8518         bool has_active_crtc = encoder->base.crtc &&
8519                 to_intel_crtc(encoder->base.crtc)->active;
8520
8521         if (encoder->connectors_active && !has_active_crtc) {
8522                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
8523                               encoder->base.base.id,
8524                               drm_get_encoder_name(&encoder->base));
8525
8526                 /* Connector is active, but has no active pipe. This is
8527                  * fallout from our resume register restoring. Disable
8528                  * the encoder manually again. */
8529                 if (encoder->base.crtc) {
8530                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
8531                                       encoder->base.base.id,
8532                                       drm_get_encoder_name(&encoder->base));
8533                         encoder->disable(encoder);
8534                 }
8535
8536                 /* Inconsistent output/port/pipe state happens presumably due to
8537                  * a bug in one of the get_hw_state functions. Or someplace else
8538                  * in our code, like the register restore mess on resume. Clamp
8539                  * things to off as a safer default. */
8540                 list_for_each_entry(connector,
8541                                     &dev->mode_config.connector_list,
8542                                     base.head) {
8543                         if (connector->encoder != encoder)
8544                                 continue;
8545
8546                         intel_connector_break_all_links(connector);
8547                 }
8548         }
8549         /* Enabled encoders without active connectors will be fixed in
8550          * the crtc fixup. */
8551 }
8552
8553 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
8554  * and i915 state tracking structures. */
8555 void intel_modeset_setup_hw_state(struct drm_device *dev)
8556 {
8557         struct drm_i915_private *dev_priv = dev->dev_private;
8558         enum pipe pipe;
8559         u32 tmp;
8560         struct intel_crtc *crtc;
8561         struct intel_encoder *encoder;
8562         struct intel_connector *connector;
8563
8564         for_each_pipe(pipe) {
8565                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8566
8567                 tmp = I915_READ(PIPECONF(pipe));
8568                 if (tmp & PIPECONF_ENABLE)
8569                         crtc->active = true;
8570                 else
8571                         crtc->active = false;
8572
8573                 crtc->base.enabled = crtc->active;
8574
8575                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
8576                               crtc->base.base.id,
8577                               crtc->active ? "enabled" : "disabled");
8578         }
8579
8580         if (IS_HASWELL(dev))
8581                 intel_ddi_setup_hw_pll_state(dev);
8582
8583         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8584                             base.head) {
8585                 pipe = 0;
8586
8587                 if (encoder->get_hw_state(encoder, &pipe)) {
8588                         encoder->base.crtc =
8589                                 dev_priv->pipe_to_crtc_mapping[pipe];
8590                 } else {
8591                         encoder->base.crtc = NULL;
8592                 }
8593
8594                 encoder->connectors_active = false;
8595                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
8596                               encoder->base.base.id,
8597                               drm_get_encoder_name(&encoder->base),
8598                               encoder->base.crtc ? "enabled" : "disabled",
8599                               pipe);
8600         }
8601
8602         list_for_each_entry(connector, &dev->mode_config.connector_list,
8603                             base.head) {
8604                 if (connector->get_hw_state(connector)) {
8605                         connector->base.dpms = DRM_MODE_DPMS_ON;
8606                         connector->encoder->connectors_active = true;
8607                         connector->base.encoder = &connector->encoder->base;
8608                 } else {
8609                         connector->base.dpms = DRM_MODE_DPMS_OFF;
8610                         connector->base.encoder = NULL;
8611                 }
8612                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
8613                               connector->base.base.id,
8614                               drm_get_connector_name(&connector->base),
8615                               connector->base.encoder ? "enabled" : "disabled");
8616         }
8617
8618         /* HW state is read out, now we need to sanitize this mess. */
8619         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8620                             base.head) {
8621                 intel_sanitize_encoder(encoder);
8622         }
8623
8624         for_each_pipe(pipe) {
8625                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8626                 intel_sanitize_crtc(crtc);
8627         }
8628
8629         intel_modeset_update_staged_output_state(dev);
8630
8631         intel_modeset_check_state(dev);
8632
8633         drm_mode_config_reset(dev);
8634 }
8635
8636 void intel_modeset_gem_init(struct drm_device *dev)
8637 {
8638         intel_modeset_init_hw(dev);
8639
8640         intel_setup_overlay(dev);
8641
8642         intel_modeset_setup_hw_state(dev);
8643 }
8644
8645 void intel_modeset_cleanup(struct drm_device *dev)
8646 {
8647         struct drm_i915_private *dev_priv = dev->dev_private;
8648         struct drm_crtc *crtc;
8649         struct intel_crtc *intel_crtc;
8650
8651         drm_kms_helper_poll_fini(dev);
8652         mutex_lock(&dev->struct_mutex);
8653
8654         intel_unregister_dsm_handler();
8655
8656
8657         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8658                 /* Skip inactive CRTCs */
8659                 if (!crtc->fb)
8660                         continue;
8661
8662                 intel_crtc = to_intel_crtc(crtc);
8663                 intel_increase_pllclock(crtc);
8664         }
8665
8666         intel_disable_fbc(dev);
8667
8668         intel_disable_gt_powersave(dev);
8669
8670         ironlake_teardown_rc6(dev);
8671
8672         if (IS_VALLEYVIEW(dev))
8673                 vlv_init_dpio(dev);
8674
8675         mutex_unlock(&dev->struct_mutex);
8676
8677         /* Disable the irq before mode object teardown, for the irq might
8678          * enqueue unpin/hotplug work. */
8679         drm_irq_uninstall(dev);
8680         cancel_work_sync(&dev_priv->hotplug_work);
8681         cancel_work_sync(&dev_priv->rps.work);
8682
8683         /* flush any delayed tasks or pending work */
8684         flush_scheduled_work();
8685
8686         drm_mode_config_cleanup(dev);
8687 }
8688
8689 /*
8690  * Return which encoder is currently attached for connector.
8691  */
8692 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
8693 {
8694         return &intel_attached_encoder(connector)->base;
8695 }
8696
8697 void intel_connector_attach_encoder(struct intel_connector *connector,
8698                                     struct intel_encoder *encoder)
8699 {
8700         connector->encoder = encoder;
8701         drm_mode_connector_attach_encoder(&connector->base,
8702                                           &encoder->base);
8703 }
8704
8705 /*
8706  * set vga decode state - true == enable VGA decode
8707  */
8708 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
8709 {
8710         struct drm_i915_private *dev_priv = dev->dev_private;
8711         u16 gmch_ctrl;
8712
8713         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
8714         if (state)
8715                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
8716         else
8717                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
8718         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
8719         return 0;
8720 }
8721
8722 #ifdef CONFIG_DEBUG_FS
8723 #include <linux/seq_file.h>
8724
8725 struct intel_display_error_state {
8726         struct intel_cursor_error_state {
8727                 u32 control;
8728                 u32 position;
8729                 u32 base;
8730                 u32 size;
8731         } cursor[I915_MAX_PIPES];
8732
8733         struct intel_pipe_error_state {
8734                 u32 conf;
8735                 u32 source;
8736
8737                 u32 htotal;
8738                 u32 hblank;
8739                 u32 hsync;
8740                 u32 vtotal;
8741                 u32 vblank;
8742                 u32 vsync;
8743         } pipe[I915_MAX_PIPES];
8744
8745         struct intel_plane_error_state {
8746                 u32 control;
8747                 u32 stride;
8748                 u32 size;
8749                 u32 pos;
8750                 u32 addr;
8751                 u32 surface;
8752                 u32 tile_offset;
8753         } plane[I915_MAX_PIPES];
8754 };
8755
8756 struct intel_display_error_state *
8757 intel_display_capture_error_state(struct drm_device *dev)
8758 {
8759         drm_i915_private_t *dev_priv = dev->dev_private;
8760         struct intel_display_error_state *error;
8761         int i;
8762
8763         error = kmalloc(sizeof(*error), GFP_ATOMIC);
8764         if (error == NULL)
8765                 return NULL;
8766
8767         for_each_pipe(i) {
8768                 error->cursor[i].control = I915_READ(CURCNTR(i));
8769                 error->cursor[i].position = I915_READ(CURPOS(i));
8770                 error->cursor[i].base = I915_READ(CURBASE(i));
8771
8772                 error->plane[i].control = I915_READ(DSPCNTR(i));
8773                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
8774                 error->plane[i].size = I915_READ(DSPSIZE(i));
8775                 error->plane[i].pos = I915_READ(DSPPOS(i));
8776                 error->plane[i].addr = I915_READ(DSPADDR(i));
8777                 if (INTEL_INFO(dev)->gen >= 4) {
8778                         error->plane[i].surface = I915_READ(DSPSURF(i));
8779                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
8780                 }
8781
8782                 error->pipe[i].conf = I915_READ(PIPECONF(i));
8783                 error->pipe[i].source = I915_READ(PIPESRC(i));
8784                 error->pipe[i].htotal = I915_READ(HTOTAL(i));
8785                 error->pipe[i].hblank = I915_READ(HBLANK(i));
8786                 error->pipe[i].hsync = I915_READ(HSYNC(i));
8787                 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
8788                 error->pipe[i].vblank = I915_READ(VBLANK(i));
8789                 error->pipe[i].vsync = I915_READ(VSYNC(i));
8790         }
8791
8792         return error;
8793 }
8794
8795 void
8796 intel_display_print_error_state(struct seq_file *m,
8797                                 struct drm_device *dev,
8798                                 struct intel_display_error_state *error)
8799 {
8800         drm_i915_private_t *dev_priv = dev->dev_private;
8801         int i;
8802
8803         seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
8804         for_each_pipe(i) {
8805                 seq_printf(m, "Pipe [%d]:\n", i);
8806                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
8807                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
8808                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
8809                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
8810                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
8811                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
8812                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
8813                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
8814
8815                 seq_printf(m, "Plane [%d]:\n", i);
8816                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
8817                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
8818                 seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
8819                 seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
8820                 seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
8821                 if (INTEL_INFO(dev)->gen >= 4) {
8822                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
8823                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
8824                 }
8825
8826                 seq_printf(m, "Cursor [%d]:\n", i);
8827                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
8828                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
8829                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
8830         }
8831 }
8832 #endif